Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.66 98.24 93.80 97.02 86.05 96.62 99.77 91.12


Total test records in report: 980
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T789 /workspace/coverage/default/52.edn_err.2156283930 May 19 02:27:32 PM PDT 24 May 19 02:27:36 PM PDT 24 45012170 ps
T790 /workspace/coverage/default/22.edn_smoke.729307105 May 19 02:26:08 PM PDT 24 May 19 02:26:10 PM PDT 24 18965936 ps
T791 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4154763547 May 19 02:25:29 PM PDT 24 May 19 02:34:55 PM PDT 24 63937908142 ps
T792 /workspace/coverage/default/212.edn_genbits.2520528540 May 19 02:28:12 PM PDT 24 May 19 02:28:15 PM PDT 24 30994220 ps
T793 /workspace/coverage/default/4.edn_alert.2371028196 May 19 02:25:05 PM PDT 24 May 19 02:25:06 PM PDT 24 43061045 ps
T794 /workspace/coverage/default/189.edn_genbits.3996073060 May 19 02:28:09 PM PDT 24 May 19 02:28:12 PM PDT 24 68919962 ps
T795 /workspace/coverage/default/248.edn_genbits.4068166528 May 19 02:28:24 PM PDT 24 May 19 02:28:28 PM PDT 24 183971385 ps
T134 /workspace/coverage/default/55.edn_err.3323526229 May 19 02:27:22 PM PDT 24 May 19 02:27:24 PM PDT 24 46111523 ps
T796 /workspace/coverage/default/47.edn_intr.1195236337 May 19 02:27:13 PM PDT 24 May 19 02:27:15 PM PDT 24 31061432 ps
T274 /workspace/coverage/default/42.edn_alert.484764222 May 19 02:26:52 PM PDT 24 May 19 02:26:54 PM PDT 24 31685631 ps
T797 /workspace/coverage/default/26.edn_disable_auto_req_mode.3073948530 May 19 02:26:13 PM PDT 24 May 19 02:26:15 PM PDT 24 40037798 ps
T798 /workspace/coverage/default/68.edn_genbits.2372087887 May 19 02:27:29 PM PDT 24 May 19 02:27:31 PM PDT 24 45383783 ps
T799 /workspace/coverage/default/18.edn_err.3105221144 May 19 02:25:47 PM PDT 24 May 19 02:25:48 PM PDT 24 20756876 ps
T295 /workspace/coverage/default/216.edn_genbits.1264469240 May 19 02:28:13 PM PDT 24 May 19 02:28:17 PM PDT 24 31580567 ps
T800 /workspace/coverage/default/26.edn_err.2900209736 May 19 02:26:14 PM PDT 24 May 19 02:26:17 PM PDT 24 82572784 ps
T801 /workspace/coverage/default/39.edn_smoke.1341923340 May 19 02:26:45 PM PDT 24 May 19 02:26:47 PM PDT 24 150620863 ps
T802 /workspace/coverage/default/17.edn_intr.1999279939 May 19 02:25:43 PM PDT 24 May 19 02:25:45 PM PDT 24 27281313 ps
T803 /workspace/coverage/default/191.edn_genbits.313701138 May 19 02:28:06 PM PDT 24 May 19 02:28:09 PM PDT 24 37957323 ps
T804 /workspace/coverage/default/25.edn_disable_auto_req_mode.2449349511 May 19 02:26:10 PM PDT 24 May 19 02:26:13 PM PDT 24 42219030 ps
T805 /workspace/coverage/default/24.edn_alert_test.2592150944 May 19 02:26:10 PM PDT 24 May 19 02:26:12 PM PDT 24 20007711 ps
T806 /workspace/coverage/default/49.edn_smoke.2510584059 May 19 02:27:16 PM PDT 24 May 19 02:27:18 PM PDT 24 19223749 ps
T807 /workspace/coverage/default/41.edn_alert_test.2218962194 May 19 02:26:53 PM PDT 24 May 19 02:26:55 PM PDT 24 56706491 ps
T808 /workspace/coverage/default/179.edn_genbits.3792291478 May 19 02:28:10 PM PDT 24 May 19 02:28:14 PM PDT 24 116569591 ps
T809 /workspace/coverage/default/198.edn_genbits.669624545 May 19 02:28:12 PM PDT 24 May 19 02:28:16 PM PDT 24 40316540 ps
T810 /workspace/coverage/default/16.edn_alert_test.3413279887 May 19 02:25:43 PM PDT 24 May 19 02:25:45 PM PDT 24 18733085 ps
T811 /workspace/coverage/default/287.edn_genbits.4147383577 May 19 02:28:27 PM PDT 24 May 19 02:28:29 PM PDT 24 36761033 ps
T812 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2855605262 May 19 02:26:55 PM PDT 24 May 19 02:48:04 PM PDT 24 172395258269 ps
T813 /workspace/coverage/default/18.edn_genbits.1967488146 May 19 02:25:50 PM PDT 24 May 19 02:25:52 PM PDT 24 54140587 ps
T814 /workspace/coverage/default/146.edn_genbits.1937720734 May 19 02:27:56 PM PDT 24 May 19 02:28:00 PM PDT 24 61473440 ps
T815 /workspace/coverage/default/4.edn_disable_auto_req_mode.3611798896 May 19 02:25:04 PM PDT 24 May 19 02:25:06 PM PDT 24 33862385 ps
T816 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2671241818 May 19 02:25:28 PM PDT 24 May 19 02:32:20 PM PDT 24 26676535863 ps
T817 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2365911263 May 19 02:25:39 PM PDT 24 May 19 02:29:44 PM PDT 24 40077107779 ps
T818 /workspace/coverage/default/0.edn_genbits.2844880742 May 19 02:24:50 PM PDT 24 May 19 02:24:52 PM PDT 24 76750355 ps
T819 /workspace/coverage/default/13.edn_smoke.3048995729 May 19 02:25:34 PM PDT 24 May 19 02:25:37 PM PDT 24 15647448 ps
T820 /workspace/coverage/default/10.edn_alert_test.2501087028 May 19 02:25:30 PM PDT 24 May 19 02:25:33 PM PDT 24 32480755 ps
T821 /workspace/coverage/default/57.edn_err.2922240711 May 19 02:27:32 PM PDT 24 May 19 02:27:35 PM PDT 24 46680025 ps
T822 /workspace/coverage/default/28.edn_stress_all.1541546096 May 19 02:26:13 PM PDT 24 May 19 02:26:21 PM PDT 24 367033572 ps
T260 /workspace/coverage/default/31.edn_alert.3350772559 May 19 02:26:28 PM PDT 24 May 19 02:26:30 PM PDT 24 27536865 ps
T823 /workspace/coverage/default/37.edn_alert_test.2953040695 May 19 02:26:49 PM PDT 24 May 19 02:26:51 PM PDT 24 54264247 ps
T824 /workspace/coverage/default/256.edn_genbits.2876700774 May 19 02:28:22 PM PDT 24 May 19 02:28:27 PM PDT 24 61222380 ps
T825 /workspace/coverage/default/294.edn_genbits.4286349751 May 19 02:28:33 PM PDT 24 May 19 02:28:36 PM PDT 24 76304640 ps
T826 /workspace/coverage/default/203.edn_genbits.4087113631 May 19 02:28:11 PM PDT 24 May 19 02:28:15 PM PDT 24 60433218 ps
T827 /workspace/coverage/default/127.edn_genbits.4037073437 May 19 02:27:49 PM PDT 24 May 19 02:27:53 PM PDT 24 308509040 ps
T828 /workspace/coverage/default/160.edn_genbits.2880675190 May 19 02:28:04 PM PDT 24 May 19 02:28:06 PM PDT 24 264488919 ps
T829 /workspace/coverage/default/59.edn_err.1232490147 May 19 02:27:30 PM PDT 24 May 19 02:27:32 PM PDT 24 43579885 ps
T830 /workspace/coverage/default/3.edn_disable_auto_req_mode.3768773030 May 19 02:25:00 PM PDT 24 May 19 02:25:02 PM PDT 24 221340746 ps
T831 /workspace/coverage/default/42.edn_disable_auto_req_mode.531132216 May 19 02:26:55 PM PDT 24 May 19 02:26:58 PM PDT 24 47974811 ps
T832 /workspace/coverage/default/8.edn_stress_all.370448937 May 19 02:25:24 PM PDT 24 May 19 02:25:31 PM PDT 24 531276145 ps
T833 /workspace/coverage/default/130.edn_genbits.1075427746 May 19 02:27:50 PM PDT 24 May 19 02:27:53 PM PDT 24 136877721 ps
T834 /workspace/coverage/default/2.edn_smoke.2877532797 May 19 02:24:55 PM PDT 24 May 19 02:24:57 PM PDT 24 24661129 ps
T835 /workspace/coverage/default/116.edn_genbits.216863661 May 19 02:27:44 PM PDT 24 May 19 02:27:47 PM PDT 24 46676395 ps
T836 /workspace/coverage/default/47.edn_disable.2198828839 May 19 02:27:11 PM PDT 24 May 19 02:27:13 PM PDT 24 13124407 ps
T837 /workspace/coverage/default/38.edn_smoke.2374367495 May 19 02:26:45 PM PDT 24 May 19 02:26:46 PM PDT 24 45176781 ps
T838 /workspace/coverage/default/33.edn_err.2539483761 May 19 02:26:30 PM PDT 24 May 19 02:26:32 PM PDT 24 21001374 ps
T839 /workspace/coverage/default/49.edn_genbits.3806018343 May 19 02:27:17 PM PDT 24 May 19 02:27:20 PM PDT 24 34718447 ps
T840 /workspace/coverage/default/12.edn_err.3503797259 May 19 02:25:30 PM PDT 24 May 19 02:25:33 PM PDT 24 18948524 ps
T841 /workspace/coverage/default/12.edn_genbits.1875264600 May 19 02:25:29 PM PDT 24 May 19 02:25:33 PM PDT 24 170623008 ps
T842 /workspace/coverage/default/134.edn_genbits.1582408591 May 19 02:27:56 PM PDT 24 May 19 02:28:00 PM PDT 24 342924423 ps
T843 /workspace/coverage/default/42.edn_err.1685294260 May 19 02:26:52 PM PDT 24 May 19 02:26:54 PM PDT 24 31867547 ps
T844 /workspace/coverage/default/47.edn_stress_all.3799083578 May 19 02:27:08 PM PDT 24 May 19 02:27:14 PM PDT 24 423662056 ps
T845 /workspace/coverage/default/43.edn_smoke.3625266429 May 19 02:26:57 PM PDT 24 May 19 02:26:59 PM PDT 24 25441921 ps
T846 /workspace/coverage/default/83.edn_genbits.49304129 May 19 02:27:40 PM PDT 24 May 19 02:27:43 PM PDT 24 60455795 ps
T847 /workspace/coverage/default/163.edn_genbits.1577776682 May 19 02:28:01 PM PDT 24 May 19 02:28:03 PM PDT 24 47137428 ps
T848 /workspace/coverage/default/172.edn_genbits.2306968063 May 19 02:28:06 PM PDT 24 May 19 02:28:09 PM PDT 24 43361900 ps
T849 /workspace/coverage/default/20.edn_genbits.1504179723 May 19 02:25:54 PM PDT 24 May 19 02:25:56 PM PDT 24 37808651 ps
T850 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1752697944 May 19 01:40:57 PM PDT 24 May 19 01:40:59 PM PDT 24 52597846 ps
T851 /workspace/coverage/cover_reg_top/49.edn_intr_test.209839440 May 19 01:41:01 PM PDT 24 May 19 01:41:03 PM PDT 24 22922115 ps
T852 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1873970280 May 19 01:40:35 PM PDT 24 May 19 01:40:39 PM PDT 24 295143560 ps
T853 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1073424281 May 19 01:40:17 PM PDT 24 May 19 01:40:19 PM PDT 24 23627404 ps
T244 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1971754055 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 171695926 ps
T220 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1969905329 May 19 01:40:28 PM PDT 24 May 19 01:40:30 PM PDT 24 14167104 ps
T854 /workspace/coverage/cover_reg_top/27.edn_intr_test.3262089230 May 19 01:40:56 PM PDT 24 May 19 01:40:58 PM PDT 24 14725634 ps
T246 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1253264569 May 19 01:40:45 PM PDT 24 May 19 01:40:49 PM PDT 24 153624382 ps
T221 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2875242747 May 19 01:40:28 PM PDT 24 May 19 01:40:30 PM PDT 24 57890160 ps
T239 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3957652364 May 19 01:40:28 PM PDT 24 May 19 01:40:29 PM PDT 24 160811057 ps
T222 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2257877341 May 19 01:40:45 PM PDT 24 May 19 01:40:48 PM PDT 24 32095354 ps
T855 /workspace/coverage/cover_reg_top/31.edn_intr_test.1335466698 May 19 01:40:58 PM PDT 24 May 19 01:41:00 PM PDT 24 16692830 ps
T223 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3292696392 May 19 01:40:59 PM PDT 24 May 19 01:41:01 PM PDT 24 14142393 ps
T856 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.38567975 May 19 01:40:50 PM PDT 24 May 19 01:40:52 PM PDT 24 17799708 ps
T857 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3942982905 May 19 01:40:31 PM PDT 24 May 19 01:40:33 PM PDT 24 31698792 ps
T224 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1858467641 May 19 01:40:29 PM PDT 24 May 19 01:40:30 PM PDT 24 19067119 ps
T858 /workspace/coverage/cover_reg_top/36.edn_intr_test.3428497424 May 19 01:41:00 PM PDT 24 May 19 01:41:02 PM PDT 24 131714295 ps
T859 /workspace/coverage/cover_reg_top/47.edn_intr_test.2401966076 May 19 01:41:00 PM PDT 24 May 19 01:41:02 PM PDT 24 15707422 ps
T240 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3776096417 May 19 01:40:51 PM PDT 24 May 19 01:40:53 PM PDT 24 42503457 ps
T860 /workspace/coverage/cover_reg_top/30.edn_intr_test.1238228769 May 19 01:40:54 PM PDT 24 May 19 01:40:55 PM PDT 24 24093465 ps
T225 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3552808841 May 19 01:40:26 PM PDT 24 May 19 01:40:28 PM PDT 24 69469461 ps
T861 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.415787533 May 19 01:40:21 PM PDT 24 May 19 01:40:24 PM PDT 24 58941644 ps
T862 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.893684173 May 19 01:40:38 PM PDT 24 May 19 01:40:40 PM PDT 24 107568394 ps
T863 /workspace/coverage/cover_reg_top/40.edn_intr_test.3807235733 May 19 01:41:00 PM PDT 24 May 19 01:41:03 PM PDT 24 12542148 ps
T245 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4122540377 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 37621616 ps
T864 /workspace/coverage/cover_reg_top/42.edn_intr_test.3384489661 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 13925580 ps
T865 /workspace/coverage/cover_reg_top/1.edn_tl_errors.136024251 May 19 01:40:23 PM PDT 24 May 19 01:40:27 PM PDT 24 124699236 ps
T241 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.421367465 May 19 01:40:40 PM PDT 24 May 19 01:40:42 PM PDT 24 36936098 ps
T866 /workspace/coverage/cover_reg_top/11.edn_intr_test.1086988179 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 33868555 ps
T867 /workspace/coverage/cover_reg_top/13.edn_csr_rw.4121928932 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 51494571 ps
T868 /workspace/coverage/cover_reg_top/29.edn_intr_test.4253153598 May 19 01:41:00 PM PDT 24 May 19 01:41:02 PM PDT 24 52079761 ps
T869 /workspace/coverage/cover_reg_top/39.edn_intr_test.3835120691 May 19 01:41:02 PM PDT 24 May 19 01:41:04 PM PDT 24 24443304 ps
T870 /workspace/coverage/cover_reg_top/7.edn_intr_test.2014640217 May 19 01:40:37 PM PDT 24 May 19 01:40:39 PM PDT 24 14412484 ps
T242 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3701993307 May 19 01:40:33 PM PDT 24 May 19 01:40:34 PM PDT 24 243276084 ps
T247 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1981827223 May 19 01:40:27 PM PDT 24 May 19 01:40:29 PM PDT 24 71465353 ps
T226 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4196588804 May 19 01:40:36 PM PDT 24 May 19 01:40:39 PM PDT 24 309090740 ps
T871 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3282053448 May 19 01:40:38 PM PDT 24 May 19 01:40:41 PM PDT 24 30586618 ps
T872 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1144996402 May 19 01:40:56 PM PDT 24 May 19 01:40:58 PM PDT 24 26091909 ps
T227 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1177902581 May 19 01:40:26 PM PDT 24 May 19 01:40:28 PM PDT 24 92609328 ps
T873 /workspace/coverage/cover_reg_top/4.edn_intr_test.227188528 May 19 01:40:29 PM PDT 24 May 19 01:40:30 PM PDT 24 14485682 ps
T228 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3941896861 May 19 01:40:22 PM PDT 24 May 19 01:40:29 PM PDT 24 1261542828 ps
T874 /workspace/coverage/cover_reg_top/15.edn_tl_errors.263268629 May 19 01:40:47 PM PDT 24 May 19 01:40:53 PM PDT 24 257599065 ps
T875 /workspace/coverage/cover_reg_top/32.edn_intr_test.2974013126 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 42500413 ps
T248 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.809098986 May 19 01:40:46 PM PDT 24 May 19 01:40:50 PM PDT 24 145744157 ps
T876 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1062743963 May 19 01:40:23 PM PDT 24 May 19 01:40:27 PM PDT 24 131225559 ps
T255 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3897808003 May 19 01:40:51 PM PDT 24 May 19 01:40:53 PM PDT 24 68834442 ps
T877 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.387748678 May 19 01:40:46 PM PDT 24 May 19 01:40:49 PM PDT 24 94569374 ps
T878 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1973878431 May 19 01:40:44 PM PDT 24 May 19 01:40:47 PM PDT 24 187697304 ps
T243 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3855353579 May 19 01:40:40 PM PDT 24 May 19 01:40:42 PM PDT 24 60137027 ps
T879 /workspace/coverage/cover_reg_top/34.edn_intr_test.3765961065 May 19 01:40:57 PM PDT 24 May 19 01:40:59 PM PDT 24 22705474 ps
T880 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3463522828 May 19 01:40:58 PM PDT 24 May 19 01:41:00 PM PDT 24 24239845 ps
T881 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2718279080 May 19 01:40:26 PM PDT 24 May 19 01:40:31 PM PDT 24 519457228 ps
T882 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1198142762 May 19 01:40:28 PM PDT 24 May 19 01:40:31 PM PDT 24 37517600 ps
T883 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2093623507 May 19 01:40:58 PM PDT 24 May 19 01:41:01 PM PDT 24 28797840 ps
T252 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.687062652 May 19 01:40:34 PM PDT 24 May 19 01:40:37 PM PDT 24 194627367 ps
T229 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1904098282 May 19 01:40:39 PM PDT 24 May 19 01:40:41 PM PDT 24 29512423 ps
T230 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3139186829 May 19 01:40:22 PM PDT 24 May 19 01:40:25 PM PDT 24 31627722 ps
T884 /workspace/coverage/cover_reg_top/2.edn_intr_test.3131666361 May 19 01:40:31 PM PDT 24 May 19 01:40:32 PM PDT 24 16275224 ps
T885 /workspace/coverage/cover_reg_top/20.edn_intr_test.2378193003 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 13419285 ps
T886 /workspace/coverage/cover_reg_top/35.edn_intr_test.3104691812 May 19 01:40:59 PM PDT 24 May 19 01:41:01 PM PDT 24 13565581 ps
T887 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1781373524 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 29915483 ps
T888 /workspace/coverage/cover_reg_top/1.edn_intr_test.1740266076 May 19 01:40:24 PM PDT 24 May 19 01:40:26 PM PDT 24 53227306 ps
T889 /workspace/coverage/cover_reg_top/12.edn_intr_test.2150910897 May 19 01:40:48 PM PDT 24 May 19 01:40:50 PM PDT 24 13458510 ps
T253 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3383173720 May 19 01:40:27 PM PDT 24 May 19 01:40:30 PM PDT 24 828459309 ps
T890 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3157873865 May 19 01:40:46 PM PDT 24 May 19 01:40:53 PM PDT 24 296420196 ps
T891 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2770098871 May 19 01:40:31 PM PDT 24 May 19 01:40:33 PM PDT 24 151942856 ps
T231 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1225178494 May 19 01:40:51 PM PDT 24 May 19 01:40:53 PM PDT 24 25772752 ps
T892 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2648622381 May 19 01:40:22 PM PDT 24 May 19 01:40:23 PM PDT 24 92100066 ps
T893 /workspace/coverage/cover_reg_top/18.edn_intr_test.1734999754 May 19 01:40:52 PM PDT 24 May 19 01:40:54 PM PDT 24 13577412 ps
T894 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1021365484 May 19 01:40:33 PM PDT 24 May 19 01:40:37 PM PDT 24 221798134 ps
T895 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1108894764 May 19 01:40:36 PM PDT 24 May 19 01:40:38 PM PDT 24 38991226 ps
T232 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1982122863 May 19 01:40:22 PM PDT 24 May 19 01:40:23 PM PDT 24 37020179 ps
T896 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3233091535 May 19 01:40:29 PM PDT 24 May 19 01:40:34 PM PDT 24 483460870 ps
T897 /workspace/coverage/cover_reg_top/19.edn_intr_test.768546632 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 17058587 ps
T898 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2239280732 May 19 01:40:22 PM PDT 24 May 19 01:40:25 PM PDT 24 20236566 ps
T254 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2684049671 May 19 01:40:22 PM PDT 24 May 19 01:40:24 PM PDT 24 136543771 ps
T899 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1742703923 May 19 01:40:37 PM PDT 24 May 19 01:40:39 PM PDT 24 110628304 ps
T900 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.367494564 May 19 01:40:32 PM PDT 24 May 19 01:40:34 PM PDT 24 15868307 ps
T256 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4132998839 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 47068183 ps
T901 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4228483673 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 50919776 ps
T902 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1542765447 May 19 01:40:58 PM PDT 24 May 19 01:41:02 PM PDT 24 169531103 ps
T903 /workspace/coverage/cover_reg_top/14.edn_intr_test.66783100 May 19 01:40:45 PM PDT 24 May 19 01:40:48 PM PDT 24 19676949 ps
T904 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.928743641 May 19 01:40:33 PM PDT 24 May 19 01:40:36 PM PDT 24 199753804 ps
T905 /workspace/coverage/cover_reg_top/26.edn_intr_test.3575188614 May 19 01:40:55 PM PDT 24 May 19 01:40:56 PM PDT 24 11857969 ps
T906 /workspace/coverage/cover_reg_top/13.edn_intr_test.3956056159 May 19 01:40:50 PM PDT 24 May 19 01:40:52 PM PDT 24 15301238 ps
T907 /workspace/coverage/cover_reg_top/10.edn_intr_test.175915949 May 19 01:40:40 PM PDT 24 May 19 01:40:41 PM PDT 24 15509624 ps
T908 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4217030495 May 19 01:40:25 PM PDT 24 May 19 01:40:30 PM PDT 24 559609923 ps
T909 /workspace/coverage/cover_reg_top/17.edn_intr_test.1500087396 May 19 01:40:49 PM PDT 24 May 19 01:40:50 PM PDT 24 19201148 ps
T233 /workspace/coverage/cover_reg_top/18.edn_csr_rw.422694195 May 19 01:40:50 PM PDT 24 May 19 01:40:51 PM PDT 24 43880419 ps
T910 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3852414648 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 51413379 ps
T911 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3294061179 May 19 01:40:27 PM PDT 24 May 19 01:40:29 PM PDT 24 19164803 ps
T912 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3031661929 May 19 01:40:52 PM PDT 24 May 19 01:41:00 PM PDT 24 506720630 ps
T913 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3961099354 May 19 01:40:58 PM PDT 24 May 19 01:41:02 PM PDT 24 52193699 ps
T914 /workspace/coverage/cover_reg_top/22.edn_intr_test.1651030841 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 15164383 ps
T915 /workspace/coverage/cover_reg_top/25.edn_intr_test.3818292230 May 19 01:40:57 PM PDT 24 May 19 01:40:59 PM PDT 24 24514524 ps
T916 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1287142340 May 19 01:40:41 PM PDT 24 May 19 01:40:44 PM PDT 24 157003309 ps
T917 /workspace/coverage/cover_reg_top/24.edn_intr_test.1335604318 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 25257709 ps
T918 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3404739515 May 19 01:40:30 PM PDT 24 May 19 01:40:32 PM PDT 24 38985827 ps
T919 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.190694468 May 19 01:40:37 PM PDT 24 May 19 01:40:40 PM PDT 24 155879364 ps
T234 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1254653276 May 19 01:40:21 PM PDT 24 May 19 01:40:24 PM PDT 24 114829107 ps
T920 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1921100634 May 19 01:40:50 PM PDT 24 May 19 01:40:51 PM PDT 24 76046010 ps
T921 /workspace/coverage/cover_reg_top/48.edn_intr_test.1867467037 May 19 01:41:00 PM PDT 24 May 19 01:41:03 PM PDT 24 13678042 ps
T922 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2925720338 May 19 01:40:42 PM PDT 24 May 19 01:40:44 PM PDT 24 32848184 ps
T923 /workspace/coverage/cover_reg_top/10.edn_csr_rw.295696649 May 19 01:40:42 PM PDT 24 May 19 01:40:44 PM PDT 24 11185885 ps
T924 /workspace/coverage/cover_reg_top/21.edn_intr_test.3267684845 May 19 01:40:57 PM PDT 24 May 19 01:40:58 PM PDT 24 24198608 ps
T925 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2650989194 May 19 01:40:55 PM PDT 24 May 19 01:40:57 PM PDT 24 32586048 ps
T926 /workspace/coverage/cover_reg_top/1.edn_csr_rw.650039295 May 19 01:40:23 PM PDT 24 May 19 01:40:25 PM PDT 24 12804253 ps
T927 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3967714858 May 19 01:40:41 PM PDT 24 May 19 01:40:45 PM PDT 24 96693473 ps
T928 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3484226885 May 19 01:40:38 PM PDT 24 May 19 01:40:41 PM PDT 24 43001882 ps
T929 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2704817488 May 19 01:40:28 PM PDT 24 May 19 01:40:29 PM PDT 24 26909245 ps
T930 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3092872961 May 19 01:40:34 PM PDT 24 May 19 01:40:37 PM PDT 24 99748067 ps
T931 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3602620720 May 19 01:40:16 PM PDT 24 May 19 01:40:18 PM PDT 24 255838865 ps
T932 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3717732522 May 19 01:40:53 PM PDT 24 May 19 01:40:57 PM PDT 24 43728914 ps
T933 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3863720904 May 19 01:40:57 PM PDT 24 May 19 01:40:59 PM PDT 24 70949989 ps
T934 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.812963523 May 19 01:40:45 PM PDT 24 May 19 01:40:47 PM PDT 24 14566535 ps
T935 /workspace/coverage/cover_reg_top/43.edn_intr_test.3686356708 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 48242080 ps
T936 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1307443453 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 68248252 ps
T235 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3169638723 May 19 01:40:30 PM PDT 24 May 19 01:40:31 PM PDT 24 15525697 ps
T937 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2874454610 May 19 01:40:58 PM PDT 24 May 19 01:41:02 PM PDT 24 27625252 ps
T938 /workspace/coverage/cover_reg_top/9.edn_intr_test.4260584316 May 19 01:40:35 PM PDT 24 May 19 01:40:37 PM PDT 24 15055978 ps
T939 /workspace/coverage/cover_reg_top/5.edn_tl_errors.477299221 May 19 01:40:31 PM PDT 24 May 19 01:40:34 PM PDT 24 54619652 ps
T940 /workspace/coverage/cover_reg_top/33.edn_intr_test.1912580547 May 19 01:40:59 PM PDT 24 May 19 01:41:02 PM PDT 24 16676487 ps
T236 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3539112286 May 19 01:40:30 PM PDT 24 May 19 01:40:34 PM PDT 24 132026956 ps
T941 /workspace/coverage/cover_reg_top/5.edn_intr_test.3027610286 May 19 01:40:30 PM PDT 24 May 19 01:40:32 PM PDT 24 60788579 ps
T942 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4017004609 May 19 01:40:33 PM PDT 24 May 19 01:40:36 PM PDT 24 56473192 ps
T943 /workspace/coverage/cover_reg_top/28.edn_intr_test.773965813 May 19 01:40:56 PM PDT 24 May 19 01:40:57 PM PDT 24 44198248 ps
T237 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3773266509 May 19 01:40:25 PM PDT 24 May 19 01:40:27 PM PDT 24 46551052 ps
T944 /workspace/coverage/cover_reg_top/23.edn_intr_test.4099191259 May 19 01:40:57 PM PDT 24 May 19 01:40:59 PM PDT 24 36239351 ps
T945 /workspace/coverage/cover_reg_top/41.edn_intr_test.168081740 May 19 01:40:58 PM PDT 24 May 19 01:41:01 PM PDT 24 19505385 ps
T946 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3404649036 May 19 01:40:46 PM PDT 24 May 19 01:40:48 PM PDT 24 53392972 ps
T947 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2690369365 May 19 01:40:41 PM PDT 24 May 19 01:40:45 PM PDT 24 125867221 ps
T948 /workspace/coverage/cover_reg_top/11.edn_tl_errors.986931774 May 19 01:40:43 PM PDT 24 May 19 01:40:46 PM PDT 24 81899188 ps
T949 /workspace/coverage/cover_reg_top/44.edn_intr_test.1315435504 May 19 01:41:02 PM PDT 24 May 19 01:41:04 PM PDT 24 13609864 ps
T950 /workspace/coverage/cover_reg_top/16.edn_intr_test.2374635814 May 19 01:40:48 PM PDT 24 May 19 01:40:50 PM PDT 24 71436821 ps
T951 /workspace/coverage/cover_reg_top/6.edn_intr_test.1158358648 May 19 01:40:33 PM PDT 24 May 19 01:40:36 PM PDT 24 36969197 ps
T952 /workspace/coverage/cover_reg_top/14.edn_csr_rw.406263019 May 19 01:40:46 PM PDT 24 May 19 01:40:48 PM PDT 24 53347240 ps
T238 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1634205244 May 19 01:40:17 PM PDT 24 May 19 01:40:18 PM PDT 24 43264506 ps
T953 /workspace/coverage/cover_reg_top/38.edn_intr_test.447264506 May 19 01:41:01 PM PDT 24 May 19 01:41:03 PM PDT 24 48496039 ps
T954 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3140880541 May 19 01:40:46 PM PDT 24 May 19 01:40:48 PM PDT 24 21481686 ps
T955 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2391510206 May 19 01:40:47 PM PDT 24 May 19 01:40:50 PM PDT 24 62847131 ps
T956 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1036407683 May 19 01:40:47 PM PDT 24 May 19 01:40:51 PM PDT 24 412791281 ps
T957 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1568547448 May 19 01:40:30 PM PDT 24 May 19 01:40:33 PM PDT 24 158036634 ps
T958 /workspace/coverage/cover_reg_top/17.edn_tl_errors.430097407 May 19 01:40:52 PM PDT 24 May 19 01:40:55 PM PDT 24 47644145 ps
T959 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1079920351 May 19 01:40:42 PM PDT 24 May 19 01:40:44 PM PDT 24 56064056 ps
T960 /workspace/coverage/cover_reg_top/9.edn_csr_rw.696796240 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 31863803 ps
T961 /workspace/coverage/cover_reg_top/8.edn_intr_test.1986621196 May 19 01:40:36 PM PDT 24 May 19 01:40:38 PM PDT 24 16053373 ps
T962 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1681443182 May 19 01:40:53 PM PDT 24 May 19 01:40:56 PM PDT 24 161585788 ps
T963 /workspace/coverage/cover_reg_top/46.edn_intr_test.3851580562 May 19 01:41:00 PM PDT 24 May 19 01:41:03 PM PDT 24 30393526 ps
T964 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2097565176 May 19 01:40:36 PM PDT 24 May 19 01:40:38 PM PDT 24 54299449 ps
T965 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1876623095 May 19 01:40:27 PM PDT 24 May 19 01:40:30 PM PDT 24 174680865 ps
T966 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3175991234 May 19 01:40:41 PM PDT 24 May 19 01:40:44 PM PDT 24 137392079 ps
T967 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.315411410 May 19 01:40:38 PM PDT 24 May 19 01:40:40 PM PDT 24 21783831 ps
T968 /workspace/coverage/cover_reg_top/15.edn_intr_test.4080642989 May 19 01:40:48 PM PDT 24 May 19 01:40:50 PM PDT 24 22988360 ps
T969 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3836328366 May 19 01:40:50 PM PDT 24 May 19 01:40:52 PM PDT 24 29280617 ps
T970 /workspace/coverage/cover_reg_top/45.edn_intr_test.3803670675 May 19 01:41:00 PM PDT 24 May 19 01:41:02 PM PDT 24 24073105 ps
T971 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2094863553 May 19 01:40:56 PM PDT 24 May 19 01:40:57 PM PDT 24 33836725 ps
T972 /workspace/coverage/cover_reg_top/5.edn_csr_rw.134573212 May 19 01:40:41 PM PDT 24 May 19 01:40:43 PM PDT 24 20316997 ps
T973 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2650397973 May 19 01:40:32 PM PDT 24 May 19 01:40:34 PM PDT 24 65471531 ps
T974 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2270014680 May 19 01:40:23 PM PDT 24 May 19 01:40:26 PM PDT 24 33995846 ps
T975 /workspace/coverage/cover_reg_top/37.edn_intr_test.2199358189 May 19 01:40:59 PM PDT 24 May 19 01:41:01 PM PDT 24 50054597 ps
T976 /workspace/coverage/cover_reg_top/3.edn_intr_test.3743372828 May 19 01:40:27 PM PDT 24 May 19 01:40:29 PM PDT 24 22236712 ps
T977 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3144432455 May 19 01:40:40 PM PDT 24 May 19 01:40:42 PM PDT 24 78390025 ps
T978 /workspace/coverage/cover_reg_top/0.edn_intr_test.455118815 May 19 01:40:19 PM PDT 24 May 19 01:40:20 PM PDT 24 24919316 ps
T979 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1914718035 May 19 01:40:28 PM PDT 24 May 19 01:40:35 PM PDT 24 560431103 ps
T980 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4146652946 May 19 01:40:27 PM PDT 24 May 19 01:40:28 PM PDT 24 34996774 ps

Test location /workspace/coverage/default/164.edn_genbits.762176095
Short name T3
Test name
Test status
Simulation time 36066479 ps
CPU time 1.58 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 217920 kb
Host smart-c8dbd310-d74a-44dd-abfc-216c10d80684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762176095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.762176095
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2597369686
Short name T40
Test name
Test status
Simulation time 95196569085 ps
CPU time 2431.1 seconds
Started May 19 02:27:07 PM PDT 24
Finished May 19 03:07:39 PM PDT 24
Peak memory 231072 kb
Host smart-89cb6487-a580-4385-9b79-2d339bfe8f18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597369686 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2597369686
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/278.edn_genbits.3890524939
Short name T10
Test name
Test status
Simulation time 328981238 ps
CPU time 2.54 seconds
Started May 19 02:28:38 PM PDT 24
Finished May 19 02:28:41 PM PDT 24
Peak memory 219760 kb
Host smart-d709b43e-6e39-4413-b3d9-7a7166a50f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890524939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3890524939
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_err.4150978195
Short name T14
Test name
Test status
Simulation time 27688419 ps
CPU time 1 seconds
Started May 19 02:26:11 PM PDT 24
Finished May 19 02:26:14 PM PDT 24
Peak memory 223508 kb
Host smart-83f4c0eb-a1cd-4a69-8516-fabc6bdeddf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150978195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4150978195
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3358406932
Short name T64
Test name
Test status
Simulation time 2402116888 ps
CPU time 8.07 seconds
Started May 19 02:25:03 PM PDT 24
Finished May 19 02:25:12 PM PDT 24
Peak memory 238528 kb
Host smart-c49cecec-f299-497f-8cf6-4c7116ef6af5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358406932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3358406932
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/6.edn_alert.1181214722
Short name T28
Test name
Test status
Simulation time 105529659 ps
CPU time 1.41 seconds
Started May 19 02:25:17 PM PDT 24
Finished May 19 02:25:19 PM PDT 24
Peak memory 215416 kb
Host smart-70f82e9c-ba79-4e9e-beae-dbafc256291b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181214722 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1181214722
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/32.edn_stress_all.1092993118
Short name T4
Test name
Test status
Simulation time 1747581833 ps
CPU time 4.04 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:35 PM PDT 24
Peak memory 215092 kb
Host smart-5d724686-bb13-4b2d-8681-48c83aaeeb74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092993118 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1092993118
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_err.167353490
Short name T29
Test name
Test status
Simulation time 20104647 ps
CPU time 1.04 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 219312 kb
Host smart-94db176a-6e46-4a2a-af50-0e8d4531bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167353490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.167353490
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3703775529
Short name T75
Test name
Test status
Simulation time 56493535 ps
CPU time 1.45 seconds
Started May 19 02:26:49 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 216692 kb
Host smart-04dcbde2-6f8d-4162-8032-d71a06010d8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703775529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3703775529
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_alert.557915325
Short name T153
Test name
Test status
Simulation time 53770924 ps
CPU time 1.22 seconds
Started May 19 02:27:07 PM PDT 24
Finished May 19 02:27:09 PM PDT 24
Peak memory 215408 kb
Host smart-e4b1e905-dc66-4489-8a98-5aa847e30b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557915325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.557915325
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.4156085988
Short name T24
Test name
Test status
Simulation time 31691883 ps
CPU time 1 seconds
Started May 19 02:25:03 PM PDT 24
Finished May 19 02:25:05 PM PDT 24
Peak memory 206844 kb
Host smart-643daa7b-6a7b-4b1c-8cd6-a7e7151325d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156085988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4156085988
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.379367805
Short name T197
Test name
Test status
Simulation time 95397782086 ps
CPU time 1086.4 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:44:54 PM PDT 24
Peak memory 222036 kb
Host smart-5e792408-1fa2-423f-be75-970c36f262b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379367805 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.379367805
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_intr.1380809074
Short name T38
Test name
Test status
Simulation time 24571659 ps
CPU time 0.96 seconds
Started May 19 02:25:31 PM PDT 24
Finished May 19 02:25:34 PM PDT 24
Peak memory 215488 kb
Host smart-0b7d53b4-098c-498c-bd1c-8f0a03dfb3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380809074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1380809074
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3383173720
Short name T253
Test name
Test status
Simulation time 828459309 ps
CPU time 2.71 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206536 kb
Host smart-e952cba7-5d26-4da9-98d5-4c4a2e4e65ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383173720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3383173720
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/18.edn_alert.2987771775
Short name T69
Test name
Test status
Simulation time 69881387 ps
CPU time 1.16 seconds
Started May 19 02:25:49 PM PDT 24
Finished May 19 02:25:51 PM PDT 24
Peak memory 215420 kb
Host smart-151c08b7-eb60-45a8-aa5a-ee33f049bd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987771775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2987771775
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/39.edn_disable.2009438165
Short name T93
Test name
Test status
Simulation time 38147663 ps
CPU time 0.86 seconds
Started May 19 02:26:50 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 216044 kb
Host smart-ddf41046-daf0-4d48-8329-48b2f027ebd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009438165 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2009438165
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1858467641
Short name T224
Test name
Test status
Simulation time 19067119 ps
CPU time 0.84 seconds
Started May 19 01:40:29 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206124 kb
Host smart-c0e0d2cd-03ae-4019-86fc-11898f988b29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858467641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1858467641
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/default/24.edn_disable.147674496
Short name T90
Test name
Test status
Simulation time 13389759 ps
CPU time 0.96 seconds
Started May 19 02:26:07 PM PDT 24
Finished May 19 02:26:10 PM PDT 24
Peak memory 216164 kb
Host smart-b09da7fc-8692-41bd-a521-ccbc77113fe7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147674496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.147674496
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2229821233
Short name T121
Test name
Test status
Simulation time 86529035 ps
CPU time 1.18 seconds
Started May 19 02:26:35 PM PDT 24
Finished May 19 02:26:38 PM PDT 24
Peak memory 216804 kb
Host smart-0938fbd8-c81b-4f3c-9b77-319274a3cd3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229821233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2229821233
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1178899360
Short name T100
Test name
Test status
Simulation time 95950853 ps
CPU time 1.3 seconds
Started May 19 02:25:40 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 216680 kb
Host smart-d9c6be9c-a275-4bdb-aacc-becfd32d33bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178899360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1178899360
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.918659506
Short name T139
Test name
Test status
Simulation time 32437549 ps
CPU time 0.82 seconds
Started May 19 02:25:42 PM PDT 24
Finished May 19 02:25:44 PM PDT 24
Peak memory 216036 kb
Host smart-08dd4dd3-a9ec-466a-90ee-d4b99f3c4cb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918659506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.918659506
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/3.edn_intr.3555800152
Short name T57
Test name
Test status
Simulation time 25340044 ps
CPU time 1.08 seconds
Started May 19 02:25:02 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 223552 kb
Host smart-dec3ef25-9730-4d24-9734-c60e8569e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555800152 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3555800152
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/14.edn_intr.286341901
Short name T32
Test name
Test status
Simulation time 21170393 ps
CPU time 1.06 seconds
Started May 19 02:25:36 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 215356 kb
Host smart-1d83c6e6-9f92-4ef5-974c-bd97fc92be00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286341901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.286341901
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/40.edn_disable.4230548179
Short name T23
Test name
Test status
Simulation time 11305873 ps
CPU time 0.86 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 215268 kb
Host smart-1e394ea6-8576-443f-873a-311bd18e4f12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230548179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4230548179
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/236.edn_genbits.1148862895
Short name T293
Test name
Test status
Simulation time 63431521 ps
CPU time 1.33 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 219416 kb
Host smart-42f7d6d8-0df9-4ee1-9533-ebf52caddace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148862895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1148862895
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_alert.2467123693
Short name T516
Test name
Test status
Simulation time 44851535 ps
CPU time 1.16 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:31 PM PDT 24
Peak memory 215396 kb
Host smart-603b7f30-c0ea-42b2-a160-3a264a839ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467123693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2467123693
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.1299390296
Short name T80
Test name
Test status
Simulation time 33500419 ps
CPU time 0.82 seconds
Started May 19 02:27:21 PM PDT 24
Finished May 19 02:27:22 PM PDT 24
Peak memory 214860 kb
Host smart-7e54c7da-a765-4734-8f01-427abbbc5979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299390296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1299390296
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/152.edn_genbits.405500434
Short name T82
Test name
Test status
Simulation time 94712013 ps
CPU time 1.19 seconds
Started May 19 02:28:04 PM PDT 24
Finished May 19 02:28:07 PM PDT 24
Peak memory 216740 kb
Host smart-6d5ffba7-97f6-4659-8794-49140ccf6125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405500434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.405500434
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1112613188
Short name T78
Test name
Test status
Simulation time 34814679 ps
CPU time 1.19 seconds
Started May 19 02:26:54 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 219336 kb
Host smart-2b2b6711-3550-4131-a5cc-7be1f2e8552c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112613188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1112613188
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/101.edn_genbits.470739947
Short name T249
Test name
Test status
Simulation time 115265942 ps
CPU time 1.34 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 219296 kb
Host smart-bcf1b8b2-3168-45d3-bb0a-7953fd061e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470739947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.470739947
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_disable.2031415610
Short name T148
Test name
Test status
Simulation time 13793774 ps
CPU time 0.94 seconds
Started May 19 02:25:42 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 216176 kb
Host smart-f78e8d18-d212-4f5d-b270-f9f3032f3df3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031415610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2031415610
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.2735527351
Short name T131
Test name
Test status
Simulation time 25546426 ps
CPU time 0.88 seconds
Started May 19 02:24:48 PM PDT 24
Finished May 19 02:24:49 PM PDT 24
Peak memory 216068 kb
Host smart-db5ff3dd-168a-4c82-8432-26b7d1a2cdea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735527351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2735527351
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4234318117
Short name T763
Test name
Test status
Simulation time 28867304 ps
CPU time 1.09 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:24:58 PM PDT 24
Peak memory 216628 kb
Host smart-271f1946-5d4e-43c1-98c0-eb29902f998f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234318117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4234318117
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3394513865
Short name T150
Test name
Test status
Simulation time 35001556 ps
CPU time 0.94 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 223308 kb
Host smart-2f3736e2-cdd1-4434-be96-84892f9c3474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394513865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3394513865
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/2.edn_disable.2163899906
Short name T178
Test name
Test status
Simulation time 30874342 ps
CPU time 0.86 seconds
Started May 19 02:24:55 PM PDT 24
Finished May 19 02:24:57 PM PDT 24
Peak memory 216080 kb
Host smart-173ea1a6-a6db-4d94-8960-1ab0da414424
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163899906 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2163899906
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable.3371308978
Short name T184
Test name
Test status
Simulation time 34955922 ps
CPU time 0.85 seconds
Started May 19 02:26:03 PM PDT 24
Finished May 19 02:26:05 PM PDT 24
Peak memory 216100 kb
Host smart-1f2f3cf2-c72f-4aa4-bffd-3b44f1cdee7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371308978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3371308978
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.1692959982
Short name T172
Test name
Test status
Simulation time 17048732 ps
CPU time 0.88 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:16 PM PDT 24
Peak memory 216236 kb
Host smart-1b951b10-762b-4042-bb6f-afdda33701c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692959982 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1692959982
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.2120108908
Short name T142
Test name
Test status
Simulation time 156863691 ps
CPU time 0.84 seconds
Started May 19 02:26:16 PM PDT 24
Finished May 19 02:26:18 PM PDT 24
Peak memory 216100 kb
Host smart-cd264e18-99d6-42f5-a67e-c127e85fff79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120108908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2120108908
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable.3432459521
Short name T138
Test name
Test status
Simulation time 13134529 ps
CPU time 0.89 seconds
Started May 19 02:26:25 PM PDT 24
Finished May 19 02:26:27 PM PDT 24
Peak memory 216188 kb
Host smart-efb0032b-6eec-4c74-98e2-82f72c0f0265
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432459521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3432459521
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/90.edn_err.1114896607
Short name T60
Test name
Test status
Simulation time 29195289 ps
CPU time 1.01 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 228904 kb
Host smart-5c5cb5d1-d3ac-43c3-838b-7a44e4782f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114896607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1114896607
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/1.edn_alert_test.1218005631
Short name T316
Test name
Test status
Simulation time 135568288 ps
CPU time 1.01 seconds
Started May 19 02:24:57 PM PDT 24
Finished May 19 02:24:59 PM PDT 24
Peak memory 206348 kb
Host smart-04a493bb-3cf3-492e-a3bb-212ecb3b4f28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218005631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1218005631
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_alert.2306330688
Short name T265
Test name
Test status
Simulation time 73746128 ps
CPU time 1.28 seconds
Started May 19 02:24:55 PM PDT 24
Finished May 19 02:24:57 PM PDT 24
Peak memory 215424 kb
Host smart-1fe5771f-8aa9-4af9-9f3b-c7a4e35e9e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306330688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2306330688
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/4.edn_regwen.2315071144
Short name T744
Test name
Test status
Simulation time 31485240 ps
CPU time 1.08 seconds
Started May 19 02:25:02 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 206828 kb
Host smart-90568525-ab70-434d-b32a-21a234e6f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315071144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2315071144
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3139186829
Short name T230
Test name
Test status
Simulation time 31627722 ps
CPU time 1.04 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 206116 kb
Host smart-e9a8937b-1ac9-4d36-af08-f5310d051e97
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139186829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3139186829
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/233.edn_genbits.36056759
Short name T44
Test name
Test status
Simulation time 33042699 ps
CPU time 1.55 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:17 PM PDT 24
Peak memory 217916 kb
Host smart-9ddc19ad-1877-45e7-9c11-1240d8384632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36056759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.36056759
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2133327837
Short name T267
Test name
Test status
Simulation time 175895054 ps
CPU time 1.03 seconds
Started May 19 02:24:45 PM PDT 24
Finished May 19 02:24:47 PM PDT 24
Peak memory 206820 kb
Host smart-dc2c5cf8-c6fc-40c5-91b5-73f0f6313e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133327837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2133327837
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/114.edn_genbits.2452622459
Short name T280
Test name
Test status
Simulation time 45077654 ps
CPU time 1.13 seconds
Started May 19 02:27:45 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 217972 kb
Host smart-d7f496b0-324c-4cf5-b4ca-5ea9cc01480e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452622459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2452622459
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_alert.1355821504
Short name T275
Test name
Test status
Simulation time 76719142 ps
CPU time 1.23 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 215408 kb
Host smart-cda8e97c-697c-4f21-8462-122750d851f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355821504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1355821504
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/277.edn_genbits.3189264025
Short name T196
Test name
Test status
Simulation time 69517368 ps
CPU time 2.65 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 218612 kb
Host smart-b7fa4744-bbd4-4463-99b9-4ce0936b9b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189264025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3189264025
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1546833288
Short name T200
Test name
Test status
Simulation time 174569366675 ps
CPU time 1687.54 seconds
Started May 19 02:25:07 PM PDT 24
Finished May 19 02:53:15 PM PDT 24
Peak memory 226752 kb
Host smart-abc3e8fc-06af-46cd-84ee-262b608d6bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546833288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1546833288
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_intr.1434670538
Short name T157
Test name
Test status
Simulation time 36428330 ps
CPU time 0.98 seconds
Started May 19 02:26:17 PM PDT 24
Finished May 19 02:26:19 PM PDT 24
Peak memory 215644 kb
Host smart-bb6f8bd2-9a16-4421-a445-b609106a3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434670538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1434670538
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/119.edn_genbits.1785383879
Short name T301
Test name
Test status
Simulation time 57784902 ps
CPU time 1.88 seconds
Started May 19 02:27:45 PM PDT 24
Finished May 19 02:27:48 PM PDT 24
Peak memory 219328 kb
Host smart-d8a70772-1bcc-4550-8599-3d30120eb947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785383879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1785383879
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_genbits.2844880742
Short name T818
Test name
Test status
Simulation time 76750355 ps
CPU time 1.08 seconds
Started May 19 02:24:50 PM PDT 24
Finished May 19 02:24:52 PM PDT 24
Peak memory 215048 kb
Host smart-b5a5088b-947a-488f-aa00-0199a485916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844880742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2844880742
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3092729886
Short name T297
Test name
Test status
Simulation time 104501984 ps
CPU time 1.68 seconds
Started May 19 02:27:39 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 218180 kb
Host smart-b42645d6-15eb-45bc-9437-4a8c6285a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092729886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3092729886
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.907470909
Short name T304
Test name
Test status
Simulation time 85563688 ps
CPU time 1.46 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 218024 kb
Host smart-b4b11a5d-f48b-4768-a717-2d5d9c94ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907470909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.907470909
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2738544880
Short name T283
Test name
Test status
Simulation time 35917703 ps
CPU time 1.23 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 218028 kb
Host smart-bba56365-5ea6-428f-b41a-ac81ba76ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738544880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2738544880
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2356057961
Short name T48
Test name
Test status
Simulation time 312426479 ps
CPU time 1.9 seconds
Started May 19 02:28:04 PM PDT 24
Finished May 19 02:28:08 PM PDT 24
Peak memory 218492 kb
Host smart-cbbadcaa-1e3e-4687-aa0e-c80e1ea2ec97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356057961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2356057961
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.1220186002
Short name T25
Test name
Test status
Simulation time 68476591 ps
CPU time 0.85 seconds
Started May 19 02:24:55 PM PDT 24
Finished May 19 02:24:57 PM PDT 24
Peak memory 206676 kb
Host smart-91aa0169-919f-4152-8616-1cf8fd4f501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220186002 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1220186002
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/24.edn_genbits.1691199359
Short name T727
Test name
Test status
Simulation time 76139481 ps
CPU time 1.62 seconds
Started May 19 02:26:06 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 218056 kb
Host smart-9f935fe2-371b-4d9e-a567-ba810302b36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691199359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1691199359
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_alert.484764222
Short name T274
Test name
Test status
Simulation time 31685631 ps
CPU time 1.23 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 215420 kb
Host smart-8e578940-0a44-40f8-a69f-0d6a009e2a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484764222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.484764222
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/88.edn_genbits.1808033043
Short name T284
Test name
Test status
Simulation time 150323439 ps
CPU time 2.17 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 219788 kb
Host smart-92f755e0-df35-4f28-b184-77f67d314700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808033043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1808033043
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2690475819
Short name T159
Test name
Test status
Simulation time 24552925 ps
CPU time 0.97 seconds
Started May 19 02:25:31 PM PDT 24
Finished May 19 02:25:34 PM PDT 24
Peak memory 215492 kb
Host smart-8d40ab31-e2d4-444b-9e7b-81a320cdd7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690475819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2690475819
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable.3986882543
Short name T191
Test name
Test status
Simulation time 23361947 ps
CPU time 0.93 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 216204 kb
Host smart-c949eb27-f653-4557-a3d8-b900513dc1ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986882543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3986882543
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.3001668959
Short name T81
Test name
Test status
Simulation time 21302709 ps
CPU time 1.12 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:13 PM PDT 24
Peak memory 219124 kb
Host smart-a706b26d-25cd-4707-8c54-4f31ed39ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001668959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3001668959
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1062743963
Short name T876
Test name
Test status
Simulation time 131225559 ps
CPU time 3.14 seconds
Started May 19 01:40:23 PM PDT 24
Finished May 19 01:40:27 PM PDT 24
Peak memory 206148 kb
Host smart-cf1472b1-ebdb-4418-8a46-da0b9a9de645
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062743963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1062743963
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1634205244
Short name T238
Test name
Test status
Simulation time 43264506 ps
CPU time 0.89 seconds
Started May 19 01:40:17 PM PDT 24
Finished May 19 01:40:18 PM PDT 24
Peak memory 206380 kb
Host smart-7f0b1335-4b0a-4a78-98d6-1a581d482df3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634205244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1634205244
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.415787533
Short name T861
Test name
Test status
Simulation time 58941644 ps
CPU time 1.34 seconds
Started May 19 01:40:21 PM PDT 24
Finished May 19 01:40:24 PM PDT 24
Peak memory 222704 kb
Host smart-73ddf87e-8da2-4536-a92a-bc17854109ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415787533 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.415787533
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2648622381
Short name T892
Test name
Test status
Simulation time 92100066 ps
CPU time 0.89 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:23 PM PDT 24
Peak memory 206164 kb
Host smart-e52ecd57-2f7b-4fbe-81d2-b03b42022b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648622381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2648622381
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.455118815
Short name T978
Test name
Test status
Simulation time 24919316 ps
CPU time 0.88 seconds
Started May 19 01:40:19 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 206032 kb
Host smart-e0c15043-8343-4546-a28a-94e2edb3ef27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455118815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.455118815
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2239280732
Short name T898
Test name
Test status
Simulation time 20236566 ps
CPU time 1.05 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 206256 kb
Host smart-e53c679c-9947-48aa-9708-9e1b8cc10d72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239280732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2239280732
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1073424281
Short name T853
Test name
Test status
Simulation time 23627404 ps
CPU time 1.66 seconds
Started May 19 01:40:17 PM PDT 24
Finished May 19 01:40:19 PM PDT 24
Peak memory 214436 kb
Host smart-f279fec2-b2ad-4138-ba66-90cbb1925f29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073424281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1073424281
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3602620720
Short name T931
Test name
Test status
Simulation time 255838865 ps
CPU time 2.03 seconds
Started May 19 01:40:16 PM PDT 24
Finished May 19 01:40:18 PM PDT 24
Peak memory 206180 kb
Host smart-ec0a67c0-9c4d-421d-8af4-6407b91e6052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602620720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3602620720
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1254653276
Short name T234
Test name
Test status
Simulation time 114829107 ps
CPU time 1.43 seconds
Started May 19 01:40:21 PM PDT 24
Finished May 19 01:40:24 PM PDT 24
Peak memory 206172 kb
Host smart-19bb0cc0-8656-4177-bcc7-b31acc94fea9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254653276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1254653276
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3941896861
Short name T228
Test name
Test status
Simulation time 1261542828 ps
CPU time 6.5 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 206168 kb
Host smart-a01403b1-3801-44b2-a7fd-7f99c43612a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941896861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3941896861
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1982122863
Short name T232
Test name
Test status
Simulation time 37020179 ps
CPU time 0.83 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:23 PM PDT 24
Peak memory 206148 kb
Host smart-7594083b-e772-4aff-bf48-ebfc700487d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982122863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1982122863
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2270014680
Short name T974
Test name
Test status
Simulation time 33995846 ps
CPU time 1.57 seconds
Started May 19 01:40:23 PM PDT 24
Finished May 19 01:40:26 PM PDT 24
Peak memory 214512 kb
Host smart-e940e580-0d7a-4aaa-8d29-b7d535994e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270014680 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2270014680
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.650039295
Short name T926
Test name
Test status
Simulation time 12804253 ps
CPU time 0.89 seconds
Started May 19 01:40:23 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 206124 kb
Host smart-26d5ebac-4734-4a91-924b-20838c83e3b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650039295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.650039295
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1740266076
Short name T888
Test name
Test status
Simulation time 53227306 ps
CPU time 0.92 seconds
Started May 19 01:40:24 PM PDT 24
Finished May 19 01:40:26 PM PDT 24
Peak memory 206024 kb
Host smart-b13829b2-b73d-4e8e-9427-344767959ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740266076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1740266076
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3552808841
Short name T225
Test name
Test status
Simulation time 69469461 ps
CPU time 1.08 seconds
Started May 19 01:40:26 PM PDT 24
Finished May 19 01:40:28 PM PDT 24
Peak memory 206112 kb
Host smart-a7652901-dfec-4f29-acf3-f1bd458c41f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552808841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3552808841
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.136024251
Short name T865
Test name
Test status
Simulation time 124699236 ps
CPU time 2.43 seconds
Started May 19 01:40:23 PM PDT 24
Finished May 19 01:40:27 PM PDT 24
Peak memory 214420 kb
Host smart-71626a0f-063a-4f43-bbdf-efaede180dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136024251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.136024251
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2684049671
Short name T254
Test name
Test status
Simulation time 136543771 ps
CPU time 1.36 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:24 PM PDT 24
Peak memory 214304 kb
Host smart-6901489d-3457-448c-966c-728cecf21b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684049671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2684049671
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2925720338
Short name T922
Test name
Test status
Simulation time 32848184 ps
CPU time 1.16 seconds
Started May 19 01:40:42 PM PDT 24
Finished May 19 01:40:44 PM PDT 24
Peak memory 214464 kb
Host smart-406800db-1561-4bc9-a659-21033447a934
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925720338 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2925720338
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.295696649
Short name T923
Test name
Test status
Simulation time 11185885 ps
CPU time 0.88 seconds
Started May 19 01:40:42 PM PDT 24
Finished May 19 01:40:44 PM PDT 24
Peak memory 206124 kb
Host smart-9567c281-ba9d-4156-8abc-b8f21307a4b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295696649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.295696649
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.175915949
Short name T907
Test name
Test status
Simulation time 15509624 ps
CPU time 0.89 seconds
Started May 19 01:40:40 PM PDT 24
Finished May 19 01:40:41 PM PDT 24
Peak memory 206024 kb
Host smart-4ea22515-316e-4e2f-86b3-9fd41779620e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175915949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.175915949
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1781373524
Short name T887
Test name
Test status
Simulation time 29915483 ps
CPU time 1.17 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 206220 kb
Host smart-e68aeb1e-38c7-4cf1-8388-ddfff1cc28aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781373524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1781373524
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1973878431
Short name T878
Test name
Test status
Simulation time 187697304 ps
CPU time 2.52 seconds
Started May 19 01:40:44 PM PDT 24
Finished May 19 01:40:47 PM PDT 24
Peak memory 214356 kb
Host smart-11b76147-23e9-41de-8931-ef26994a88bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973878431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1973878431
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3175991234
Short name T966
Test name
Test status
Simulation time 137392079 ps
CPU time 2.12 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:44 PM PDT 24
Peak memory 206400 kb
Host smart-5bf99ccf-98fb-46b5-aa0c-c498abd7d3c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175991234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3175991234
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1079920351
Short name T959
Test name
Test status
Simulation time 56064056 ps
CPU time 1.36 seconds
Started May 19 01:40:42 PM PDT 24
Finished May 19 01:40:44 PM PDT 24
Peak memory 214556 kb
Host smart-fb7debe5-ec91-4f82-970f-0293e753274f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079920351 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1079920351
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3852414648
Short name T910
Test name
Test status
Simulation time 51413379 ps
CPU time 0.94 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 206124 kb
Host smart-40fa69f4-36f6-4124-b7c1-f607eafef1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852414648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3852414648
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1086988179
Short name T866
Test name
Test status
Simulation time 33868555 ps
CPU time 0.82 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 205912 kb
Host smart-0cb7c088-d4fa-4611-998a-7d5c10cf5ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086988179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1086988179
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3855353579
Short name T243
Test name
Test status
Simulation time 60137027 ps
CPU time 1.17 seconds
Started May 19 01:40:40 PM PDT 24
Finished May 19 01:40:42 PM PDT 24
Peak memory 206180 kb
Host smart-232ec27f-e08e-4680-a26e-6c26008f6b5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855353579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3855353579
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.986931774
Short name T948
Test name
Test status
Simulation time 81899188 ps
CPU time 1.91 seconds
Started May 19 01:40:43 PM PDT 24
Finished May 19 01:40:46 PM PDT 24
Peak memory 214368 kb
Host smart-7ed3537f-a123-4b9f-82cd-05bf1d51cefd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986931774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.986931774
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3967714858
Short name T927
Test name
Test status
Simulation time 96693473 ps
CPU time 2.53 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:45 PM PDT 24
Peak memory 206224 kb
Host smart-c017d081-6bad-49c4-85b6-5a8f8b1db1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967714858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3967714858
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3404649036
Short name T946
Test name
Test status
Simulation time 53392972 ps
CPU time 1.38 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 217156 kb
Host smart-dad2fc78-e1ef-4bf2-b233-f0d62f02ef73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404649036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3404649036
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1971754055
Short name T244
Test name
Test status
Simulation time 171695926 ps
CPU time 0.92 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206068 kb
Host smart-d2af02a1-6f26-4392-ac07-ee0bd2567e23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971754055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1971754055
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2150910897
Short name T889
Test name
Test status
Simulation time 13458510 ps
CPU time 0.86 seconds
Started May 19 01:40:48 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 206004 kb
Host smart-e3e918f8-b1c5-41b3-88f6-c3c79d21268a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150910897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2150910897
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3140880541
Short name T954
Test name
Test status
Simulation time 21481686 ps
CPU time 1.14 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 206216 kb
Host smart-76f34558-f2f2-4db9-8dcc-745131ee1121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140880541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3140880541
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1287142340
Short name T916
Test name
Test status
Simulation time 157003309 ps
CPU time 1.94 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:44 PM PDT 24
Peak memory 214436 kb
Host smart-d722e6a7-c998-4089-8e35-c88cbfb3517d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287142340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1287142340
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4132998839
Short name T256
Test name
Test status
Simulation time 47068183 ps
CPU time 1.62 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206068 kb
Host smart-0eae108f-211a-446f-b763-5e46b8c420b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132998839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4132998839
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.387748678
Short name T877
Test name
Test status
Simulation time 94569374 ps
CPU time 1.26 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:49 PM PDT 24
Peak memory 214676 kb
Host smart-b90d5e0a-f7d9-4b79-8817-dc8ae7db30f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387748678 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.387748678
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4121928932
Short name T867
Test name
Test status
Simulation time 51494571 ps
CPU time 0.95 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206068 kb
Host smart-c0f73eaa-9325-4740-8c33-ba909e2c07bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121928932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4121928932
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3956056159
Short name T906
Test name
Test status
Simulation time 15301238 ps
CPU time 0.95 seconds
Started May 19 01:40:50 PM PDT 24
Finished May 19 01:40:52 PM PDT 24
Peak memory 205992 kb
Host smart-c8050833-695e-4c84-aec1-6bbc6cc44c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956056159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3956056159
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3463522828
Short name T880
Test name
Test status
Simulation time 24239845 ps
CPU time 0.93 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:00 PM PDT 24
Peak memory 206108 kb
Host smart-6135cf1f-64e0-4442-baca-29c9c531ebe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463522828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3463522828
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2093623507
Short name T883
Test name
Test status
Simulation time 28797840 ps
CPU time 1.86 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 214276 kb
Host smart-ad3bd0a2-9e28-46f7-a58d-49e72c7e0fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093623507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2093623507
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.809098986
Short name T248
Test name
Test status
Simulation time 145744157 ps
CPU time 2.33 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 206360 kb
Host smart-3ed20e60-67b7-493f-bb08-1dd4e39433f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809098986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.809098986
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2874454610
Short name T937
Test name
Test status
Simulation time 27625252 ps
CPU time 1.59 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 214340 kb
Host smart-e0bd0b74-da56-4bd9-b14c-9751445527f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874454610 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2874454610
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.406263019
Short name T952
Test name
Test status
Simulation time 53347240 ps
CPU time 0.84 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 205928 kb
Host smart-fa865048-bafa-48d4-89be-8286d812ae1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406263019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.406263019
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.66783100
Short name T903
Test name
Test status
Simulation time 19676949 ps
CPU time 0.87 seconds
Started May 19 01:40:45 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 206036 kb
Host smart-5b20f8dc-72a2-477f-9aa3-ed66238afce7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66783100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.66783100
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2257877341
Short name T222
Test name
Test status
Simulation time 32095354 ps
CPU time 1.36 seconds
Started May 19 01:40:45 PM PDT 24
Finished May 19 01:40:48 PM PDT 24
Peak memory 206100 kb
Host smart-329c9c4f-b458-4634-9d83-d0e51803f669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257877341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2257877341
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3863720904
Short name T933
Test name
Test status
Simulation time 70949989 ps
CPU time 1.47 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:59 PM PDT 24
Peak memory 214304 kb
Host smart-dd8ed91a-ad71-4a02-984a-3ea8bcdd4c02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863720904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3863720904
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1036407683
Short name T956
Test name
Test status
Simulation time 412791281 ps
CPU time 2.23 seconds
Started May 19 01:40:47 PM PDT 24
Finished May 19 01:40:51 PM PDT 24
Peak memory 206140 kb
Host smart-474e548f-df54-461f-b8b2-e1331e3f6cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036407683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1036407683
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2391510206
Short name T955
Test name
Test status
Simulation time 62847131 ps
CPU time 1.24 seconds
Started May 19 01:40:47 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 214500 kb
Host smart-254dadc3-6e65-4ae5-a7ab-78b6fc9d273a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391510206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2391510206
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3292696392
Short name T223
Test name
Test status
Simulation time 14142393 ps
CPU time 0.88 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 206068 kb
Host smart-ad4380fe-51a1-4093-8423-e4ce0f233256
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292696392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3292696392
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.4080642989
Short name T968
Test name
Test status
Simulation time 22988360 ps
CPU time 0.9 seconds
Started May 19 01:40:48 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 206008 kb
Host smart-9aa4d4ce-d8c8-4caa-8fe7-2adb5bc06e21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080642989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.4080642989
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.812963523
Short name T934
Test name
Test status
Simulation time 14566535 ps
CPU time 1.04 seconds
Started May 19 01:40:45 PM PDT 24
Finished May 19 01:40:47 PM PDT 24
Peak memory 206260 kb
Host smart-6e1c1e34-5025-481e-8ded-e9281575bb4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812963523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.812963523
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.263268629
Short name T874
Test name
Test status
Simulation time 257599065 ps
CPU time 4.32 seconds
Started May 19 01:40:47 PM PDT 24
Finished May 19 01:40:53 PM PDT 24
Peak memory 214468 kb
Host smart-f408e3ac-632c-48c1-8a75-20811c52a656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263268629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.263268629
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1253264569
Short name T246
Test name
Test status
Simulation time 153624382 ps
CPU time 2.12 seconds
Started May 19 01:40:45 PM PDT 24
Finished May 19 01:40:49 PM PDT 24
Peak memory 214636 kb
Host smart-d5e652cb-bf45-43ef-a444-82d470cea6e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253264569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1253264569
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1921100634
Short name T920
Test name
Test status
Simulation time 76046010 ps
CPU time 0.96 seconds
Started May 19 01:40:50 PM PDT 24
Finished May 19 01:40:51 PM PDT 24
Peak memory 206180 kb
Host smart-bdfa5435-f6f2-4249-a08f-dc4b61d3f58a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921100634 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1921100634
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1225178494
Short name T231
Test name
Test status
Simulation time 25772752 ps
CPU time 0.92 seconds
Started May 19 01:40:51 PM PDT 24
Finished May 19 01:40:53 PM PDT 24
Peak memory 206136 kb
Host smart-f17eadf1-c4e8-482a-a41e-6102d387284f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225178494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1225178494
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2374635814
Short name T950
Test name
Test status
Simulation time 71436821 ps
CPU time 0.86 seconds
Started May 19 01:40:48 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 205912 kb
Host smart-e140b708-4b2f-4bea-8e0a-c326667675b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374635814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2374635814
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4228483673
Short name T901
Test name
Test status
Simulation time 50919776 ps
CPU time 1.18 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206132 kb
Host smart-2beebdfa-f4bb-4c38-84ef-a0ce3fb1665d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228483673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4228483673
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3157873865
Short name T890
Test name
Test status
Simulation time 296420196 ps
CPU time 4.99 seconds
Started May 19 01:40:46 PM PDT 24
Finished May 19 01:40:53 PM PDT 24
Peak memory 214340 kb
Host smart-6d6ce80d-71f8-4e76-9875-cbde9c3910a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157873865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3157873865
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1542765447
Short name T902
Test name
Test status
Simulation time 169531103 ps
CPU time 2.35 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 214304 kb
Host smart-8f3a6621-a0d2-4311-9201-6c8d4b5a9d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542765447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1542765447
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.38567975
Short name T856
Test name
Test status
Simulation time 17799708 ps
CPU time 1.05 seconds
Started May 19 01:40:50 PM PDT 24
Finished May 19 01:40:52 PM PDT 24
Peak memory 214368 kb
Host smart-ab3c1da9-bf15-4304-8e7f-0605bc5dde10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567975 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.38567975
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3836328366
Short name T969
Test name
Test status
Simulation time 29280617 ps
CPU time 1 seconds
Started May 19 01:40:50 PM PDT 24
Finished May 19 01:40:52 PM PDT 24
Peak memory 206164 kb
Host smart-e9e39cdc-9b94-4ac7-a9c9-26a62cd196f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836328366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3836328366
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1500087396
Short name T909
Test name
Test status
Simulation time 19201148 ps
CPU time 0.82 seconds
Started May 19 01:40:49 PM PDT 24
Finished May 19 01:40:50 PM PDT 24
Peak memory 206020 kb
Host smart-4fd84cf7-582b-4c36-bd9c-d9f96c033d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500087396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1500087396
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3776096417
Short name T240
Test name
Test status
Simulation time 42503457 ps
CPU time 1.15 seconds
Started May 19 01:40:51 PM PDT 24
Finished May 19 01:40:53 PM PDT 24
Peak memory 206116 kb
Host smart-7489710e-083b-4cbc-b48f-a7b1b4fbfc40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776096417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3776096417
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.430097407
Short name T958
Test name
Test status
Simulation time 47644145 ps
CPU time 3.04 seconds
Started May 19 01:40:52 PM PDT 24
Finished May 19 01:40:55 PM PDT 24
Peak memory 214368 kb
Host smart-2b1ee469-cac6-488e-ac33-029c6a29fc34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430097407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.430097407
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3031661929
Short name T912
Test name
Test status
Simulation time 506720630 ps
CPU time 7.72 seconds
Started May 19 01:40:52 PM PDT 24
Finished May 19 01:41:00 PM PDT 24
Peak memory 206144 kb
Host smart-40245b46-d3aa-4a96-abec-28c32b060381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031661929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3031661929
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1752697944
Short name T850
Test name
Test status
Simulation time 52597846 ps
CPU time 1.45 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:59 PM PDT 24
Peak memory 214408 kb
Host smart-ab54f46a-d090-422e-ab89-42080c6e6e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752697944 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1752697944
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.422694195
Short name T233
Test name
Test status
Simulation time 43880419 ps
CPU time 0.82 seconds
Started May 19 01:40:50 PM PDT 24
Finished May 19 01:40:51 PM PDT 24
Peak memory 206092 kb
Host smart-84ae46eb-236f-476a-ad76-ece250359ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422694195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.422694195
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1734999754
Short name T893
Test name
Test status
Simulation time 13577412 ps
CPU time 0.88 seconds
Started May 19 01:40:52 PM PDT 24
Finished May 19 01:40:54 PM PDT 24
Peak memory 206004 kb
Host smart-e9494b19-8a5e-4b11-93c2-7be2e3cceade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734999754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1734999754
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2650989194
Short name T925
Test name
Test status
Simulation time 32586048 ps
CPU time 1.35 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 206192 kb
Host smart-b5923983-b242-4b90-a9f4-fc07b49d4df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650989194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2650989194
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1681443182
Short name T962
Test name
Test status
Simulation time 161585788 ps
CPU time 2.98 seconds
Started May 19 01:40:53 PM PDT 24
Finished May 19 01:40:56 PM PDT 24
Peak memory 214372 kb
Host smart-667357f2-168f-4fa7-9851-90c5cda14ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681443182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1681443182
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3897808003
Short name T255
Test name
Test status
Simulation time 68834442 ps
CPU time 1.44 seconds
Started May 19 01:40:51 PM PDT 24
Finished May 19 01:40:53 PM PDT 24
Peak memory 206396 kb
Host smart-88702005-ea07-458e-8c83-7974a8cc4227
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897808003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3897808003
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1144996402
Short name T872
Test name
Test status
Simulation time 26091909 ps
CPU time 1.52 seconds
Started May 19 01:40:56 PM PDT 24
Finished May 19 01:40:58 PM PDT 24
Peak memory 214368 kb
Host smart-35e95db5-b121-41db-a7dd-5b5ed57bdab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144996402 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1144996402
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2094863553
Short name T971
Test name
Test status
Simulation time 33836725 ps
CPU time 0.86 seconds
Started May 19 01:40:56 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 205976 kb
Host smart-acb22db0-5957-4a29-850d-519bccf83c54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094863553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2094863553
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.768546632
Short name T897
Test name
Test status
Simulation time 17058587 ps
CPU time 0.97 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 205996 kb
Host smart-e2887566-9e50-4782-9ddc-05614ec2e5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768546632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.768546632
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1307443453
Short name T936
Test name
Test status
Simulation time 68248252 ps
CPU time 1.05 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206192 kb
Host smart-b77ed562-2275-4e20-bad5-583e0df60bff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307443453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1307443453
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3717732522
Short name T932
Test name
Test status
Simulation time 43728914 ps
CPU time 2.84 seconds
Started May 19 01:40:53 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 214588 kb
Host smart-b64db4af-1898-46af-a5b0-c67532549434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717732522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3717732522
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3961099354
Short name T913
Test name
Test status
Simulation time 52193699 ps
CPU time 1.61 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206180 kb
Host smart-5bc4b6a9-2739-4182-ac41-08d19b61cb91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961099354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3961099354
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1177902581
Short name T227
Test name
Test status
Simulation time 92609328 ps
CPU time 1.17 seconds
Started May 19 01:40:26 PM PDT 24
Finished May 19 01:40:28 PM PDT 24
Peak memory 206252 kb
Host smart-918d16e5-fc8d-42fa-bf83-9de7e8fc94b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177902581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1177902581
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3539112286
Short name T236
Test name
Test status
Simulation time 132026956 ps
CPU time 3.49 seconds
Started May 19 01:40:30 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 206088 kb
Host smart-4866985e-a4bb-4f9d-8e95-d816a642495b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539112286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3539112286
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2875242747
Short name T221
Test name
Test status
Simulation time 57890160 ps
CPU time 0.82 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206036 kb
Host smart-9838fd3e-a2a6-46e7-b6e3-33c8fa6fbd1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875242747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2875242747
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3294061179
Short name T911
Test name
Test status
Simulation time 19164803 ps
CPU time 1.13 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 214508 kb
Host smart-1ebd0e6b-4943-4408-8425-9ac1746c11ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294061179 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3294061179
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3131666361
Short name T884
Test name
Test status
Simulation time 16275224 ps
CPU time 0.93 seconds
Started May 19 01:40:31 PM PDT 24
Finished May 19 01:40:32 PM PDT 24
Peak memory 205972 kb
Host smart-20d33908-3df1-4558-b708-4bb92acd5ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131666361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3131666361
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4146652946
Short name T980
Test name
Test status
Simulation time 34996774 ps
CPU time 0.92 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:28 PM PDT 24
Peak memory 206208 kb
Host smart-d55d701e-404e-472a-a6d2-5e3dbd3293bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146652946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4146652946
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4217030495
Short name T908
Test name
Test status
Simulation time 559609923 ps
CPU time 4.3 seconds
Started May 19 01:40:25 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 214304 kb
Host smart-fd3806fd-ac39-454e-8d2d-bbce5227e86a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217030495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4217030495
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1876623095
Short name T965
Test name
Test status
Simulation time 174680865 ps
CPU time 2.11 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206168 kb
Host smart-fccd9973-4b34-402f-8ffa-15deab8e7afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876623095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1876623095
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2378193003
Short name T885
Test name
Test status
Simulation time 13419285 ps
CPU time 0.89 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 206036 kb
Host smart-8a4c74cb-2d9c-424b-ba38-8aba2b2869c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378193003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2378193003
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3267684845
Short name T924
Test name
Test status
Simulation time 24198608 ps
CPU time 0.83 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:58 PM PDT 24
Peak memory 205900 kb
Host smart-03cd2001-58e9-49e4-baad-b32b096daf82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267684845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3267684845
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1651030841
Short name T914
Test name
Test status
Simulation time 15164383 ps
CPU time 0.9 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 206128 kb
Host smart-e651f31c-676e-4111-949a-69621837eaa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651030841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1651030841
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4099191259
Short name T944
Test name
Test status
Simulation time 36239351 ps
CPU time 0.83 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:59 PM PDT 24
Peak memory 205924 kb
Host smart-2d11ba84-438e-4f29-884f-ee82a6236cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099191259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4099191259
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1335604318
Short name T917
Test name
Test status
Simulation time 25257709 ps
CPU time 0.9 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 206100 kb
Host smart-275cb46b-1fd1-4c6b-8798-549620e7d74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335604318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1335604318
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3818292230
Short name T915
Test name
Test status
Simulation time 24514524 ps
CPU time 0.84 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:59 PM PDT 24
Peak memory 206036 kb
Host smart-96d24205-1694-4f2d-b28c-d5e5f4175ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818292230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3818292230
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3575188614
Short name T905
Test name
Test status
Simulation time 11857969 ps
CPU time 0.83 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:56 PM PDT 24
Peak memory 205944 kb
Host smart-162c3df7-482e-4587-9652-9a0492c84108
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575188614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3575188614
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3262089230
Short name T854
Test name
Test status
Simulation time 14725634 ps
CPU time 0.87 seconds
Started May 19 01:40:56 PM PDT 24
Finished May 19 01:40:58 PM PDT 24
Peak memory 205984 kb
Host smart-d97e5200-6eaa-4d8c-92c3-a2932351447e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262089230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3262089230
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.773965813
Short name T943
Test name
Test status
Simulation time 44198248 ps
CPU time 0.87 seconds
Started May 19 01:40:56 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 206052 kb
Host smart-15f98c8c-d3a7-4e14-95d3-d3aed0d71639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773965813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.773965813
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.4253153598
Short name T868
Test name
Test status
Simulation time 52079761 ps
CPU time 0.82 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 205952 kb
Host smart-b9f10332-602d-4fac-8ab2-6c5bc9889b57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253153598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.4253153598
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3773266509
Short name T237
Test name
Test status
Simulation time 46551052 ps
CPU time 1.16 seconds
Started May 19 01:40:25 PM PDT 24
Finished May 19 01:40:27 PM PDT 24
Peak memory 206180 kb
Host smart-0d469561-6ccc-40a9-ba9f-cdc13695b4d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773266509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3773266509
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1198142762
Short name T882
Test name
Test status
Simulation time 37517600 ps
CPU time 2.07 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:31 PM PDT 24
Peak memory 206184 kb
Host smart-17f108f7-c0dc-448b-bdd9-753c619e134b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198142762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1198142762
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3169638723
Short name T235
Test name
Test status
Simulation time 15525697 ps
CPU time 0.91 seconds
Started May 19 01:40:30 PM PDT 24
Finished May 19 01:40:31 PM PDT 24
Peak memory 206180 kb
Host smart-23707e18-1cfe-4498-8f1a-aba66b5ccbea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169638723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3169638723
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3942982905
Short name T857
Test name
Test status
Simulation time 31698792 ps
CPU time 1.49 seconds
Started May 19 01:40:31 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 214480 kb
Host smart-706f8764-7f79-44da-b41d-f9e3043989d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942982905 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3942982905
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3404739515
Short name T918
Test name
Test status
Simulation time 38985827 ps
CPU time 0.83 seconds
Started May 19 01:40:30 PM PDT 24
Finished May 19 01:40:32 PM PDT 24
Peak memory 206000 kb
Host smart-8ddd118e-946c-43be-8df5-72f353a86ad8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404739515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3404739515
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3743372828
Short name T976
Test name
Test status
Simulation time 22236712 ps
CPU time 0.87 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 205988 kb
Host smart-d3ff0f5a-f92a-4bec-92d1-1c469cec8126
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743372828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3743372828
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3957652364
Short name T239
Test name
Test status
Simulation time 160811057 ps
CPU time 1.03 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 206168 kb
Host smart-f2694884-cb5a-4b9a-a679-88b3aff150ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957652364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3957652364
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2718279080
Short name T881
Test name
Test status
Simulation time 519457228 ps
CPU time 3.54 seconds
Started May 19 01:40:26 PM PDT 24
Finished May 19 01:40:31 PM PDT 24
Peak memory 214496 kb
Host smart-1333db6d-dc99-4253-84ec-d50f232eaec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718279080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2718279080
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1238228769
Short name T860
Test name
Test status
Simulation time 24093465 ps
CPU time 0.9 seconds
Started May 19 01:40:54 PM PDT 24
Finished May 19 01:40:55 PM PDT 24
Peak memory 206148 kb
Host smart-927c945c-8936-4a9c-b88d-185ecf3e469e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238228769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1238228769
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1335466698
Short name T855
Test name
Test status
Simulation time 16692830 ps
CPU time 0.85 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:00 PM PDT 24
Peak memory 206012 kb
Host smart-e291d4ae-fc4e-40e6-a936-8b8b6b25c147
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335466698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1335466698
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2974013126
Short name T875
Test name
Test status
Simulation time 42500413 ps
CPU time 0.86 seconds
Started May 19 01:40:55 PM PDT 24
Finished May 19 01:40:57 PM PDT 24
Peak memory 205972 kb
Host smart-cc5d177e-6ae9-4260-8a17-3e9e18ee1a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974013126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2974013126
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1912580547
Short name T940
Test name
Test status
Simulation time 16676487 ps
CPU time 0.94 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206100 kb
Host smart-25091742-3256-4929-b301-54fc54dcd960
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912580547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1912580547
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3765961065
Short name T879
Test name
Test status
Simulation time 22705474 ps
CPU time 0.85 seconds
Started May 19 01:40:57 PM PDT 24
Finished May 19 01:40:59 PM PDT 24
Peak memory 206036 kb
Host smart-1b3e0043-5ed5-4220-ace5-bef8fea6527b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765961065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3765961065
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3104691812
Short name T886
Test name
Test status
Simulation time 13565581 ps
CPU time 0.9 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 206020 kb
Host smart-cad156d3-44ce-4681-8787-bc625591a4a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104691812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3104691812
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3428497424
Short name T858
Test name
Test status
Simulation time 131714295 ps
CPU time 0.91 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 205912 kb
Host smart-ca0c3f3a-7584-4565-88f3-4e08e848b2a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428497424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3428497424
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2199358189
Short name T975
Test name
Test status
Simulation time 50054597 ps
CPU time 0.92 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 206092 kb
Host smart-6de0c70f-0871-4309-854e-e30d6585fe2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199358189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2199358189
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.447264506
Short name T953
Test name
Test status
Simulation time 48496039 ps
CPU time 0.9 seconds
Started May 19 01:41:01 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 206024 kb
Host smart-3c0c16dc-5814-4f6c-84c5-307dc98224bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447264506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.447264506
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3835120691
Short name T869
Test name
Test status
Simulation time 24443304 ps
CPU time 0.87 seconds
Started May 19 01:41:02 PM PDT 24
Finished May 19 01:41:04 PM PDT 24
Peak memory 206116 kb
Host smart-2d997e9f-5ac8-4b26-92b5-a227f36b9555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835120691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3835120691
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3144432455
Short name T977
Test name
Test status
Simulation time 78390025 ps
CPU time 1.12 seconds
Started May 19 01:40:40 PM PDT 24
Finished May 19 01:40:42 PM PDT 24
Peak memory 206176 kb
Host smart-6de87d92-d20a-413e-b284-9cd21e6b7af9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144432455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3144432455
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1914718035
Short name T979
Test name
Test status
Simulation time 560431103 ps
CPU time 6.4 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:35 PM PDT 24
Peak memory 206184 kb
Host smart-fff33eda-8d9b-4678-bd35-85757fa4271b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914718035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1914718035
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2704817488
Short name T929
Test name
Test status
Simulation time 26909245 ps
CPU time 0.95 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 206160 kb
Host smart-dbf6b89a-f3af-4b94-be2c-9320dc810398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704817488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2704817488
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2770098871
Short name T891
Test name
Test status
Simulation time 151942856 ps
CPU time 1.39 seconds
Started May 19 01:40:31 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 214652 kb
Host smart-21e4bb8c-0602-41c1-b27d-b322692750b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770098871 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2770098871
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1969905329
Short name T220
Test name
Test status
Simulation time 14167104 ps
CPU time 0.94 seconds
Started May 19 01:40:28 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206164 kb
Host smart-25c5bdbc-e5b3-4af2-8f5f-4a16a73661ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969905329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1969905329
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.227188528
Short name T873
Test name
Test status
Simulation time 14485682 ps
CPU time 0.84 seconds
Started May 19 01:40:29 PM PDT 24
Finished May 19 01:40:30 PM PDT 24
Peak memory 206036 kb
Host smart-75229c66-7640-4b7d-b9c4-963db5f51303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227188528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.227188528
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.367494564
Short name T900
Test name
Test status
Simulation time 15868307 ps
CPU time 1 seconds
Started May 19 01:40:32 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 206204 kb
Host smart-d9a04213-7cc4-4996-85e2-90f3b2b0f157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367494564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.367494564
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3233091535
Short name T896
Test name
Test status
Simulation time 483460870 ps
CPU time 3.92 seconds
Started May 19 01:40:29 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 214376 kb
Host smart-11f08283-9331-4004-a2e5-a9b928a0671b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233091535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3233091535
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1981827223
Short name T247
Test name
Test status
Simulation time 71465353 ps
CPU time 1.44 seconds
Started May 19 01:40:27 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 206164 kb
Host smart-10368e8e-0b69-44d6-95d3-902b87c9493f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981827223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1981827223
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3807235733
Short name T863
Test name
Test status
Simulation time 12542148 ps
CPU time 0.89 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 206040 kb
Host smart-d08d32b1-dbaa-46d2-8a38-b62a5e04c6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807235733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3807235733
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.168081740
Short name T945
Test name
Test status
Simulation time 19505385 ps
CPU time 0.84 seconds
Started May 19 01:40:58 PM PDT 24
Finished May 19 01:41:01 PM PDT 24
Peak memory 206024 kb
Host smart-4abf4bb1-2474-4677-82be-64315ac702e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168081740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.168081740
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3384489661
Short name T864
Test name
Test status
Simulation time 13925580 ps
CPU time 0.84 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206008 kb
Host smart-86c51f09-4cca-4653-9f66-a6975df068ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384489661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3384489661
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3686356708
Short name T935
Test name
Test status
Simulation time 48242080 ps
CPU time 0.85 seconds
Started May 19 01:40:59 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 205968 kb
Host smart-479bce71-1fda-44f1-bfff-841f64f84a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686356708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3686356708
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1315435504
Short name T949
Test name
Test status
Simulation time 13609864 ps
CPU time 0.86 seconds
Started May 19 01:41:02 PM PDT 24
Finished May 19 01:41:04 PM PDT 24
Peak memory 205964 kb
Host smart-b2d11c85-1efd-4b14-81b6-fdb0a43bee81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315435504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1315435504
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3803670675
Short name T970
Test name
Test status
Simulation time 24073105 ps
CPU time 0.89 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 206376 kb
Host smart-98b77666-f504-45eb-ab2f-f3462da063ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803670675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3803670675
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3851580562
Short name T963
Test name
Test status
Simulation time 30393526 ps
CPU time 0.83 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 205904 kb
Host smart-4f1ba455-9c91-4138-9642-7e18384d5930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851580562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3851580562
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2401966076
Short name T859
Test name
Test status
Simulation time 15707422 ps
CPU time 0.87 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:02 PM PDT 24
Peak memory 205960 kb
Host smart-8244be00-c177-4720-8db1-f537c93aaa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401966076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2401966076
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1867467037
Short name T921
Test name
Test status
Simulation time 13678042 ps
CPU time 0.96 seconds
Started May 19 01:41:00 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 206028 kb
Host smart-e6ee337f-ac1d-4cc8-9741-f8683aacbffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867467037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1867467037
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.209839440
Short name T851
Test name
Test status
Simulation time 22922115 ps
CPU time 0.89 seconds
Started May 19 01:41:01 PM PDT 24
Finished May 19 01:41:03 PM PDT 24
Peak memory 206016 kb
Host smart-0e24a56a-b5d7-4bac-bacb-3cd43be5e91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209839440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.209839440
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4017004609
Short name T942
Test name
Test status
Simulation time 56473192 ps
CPU time 1.4 seconds
Started May 19 01:40:33 PM PDT 24
Finished May 19 01:40:36 PM PDT 24
Peak memory 214416 kb
Host smart-71e916b7-93e4-4c65-82a2-0938d5b1f056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017004609 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4017004609
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.134573212
Short name T972
Test name
Test status
Simulation time 20316997 ps
CPU time 0.93 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 206052 kb
Host smart-2de1416d-53e2-46f5-ad9a-8ae10aba4ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134573212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.134573212
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3027610286
Short name T941
Test name
Test status
Simulation time 60788579 ps
CPU time 0.9 seconds
Started May 19 01:40:30 PM PDT 24
Finished May 19 01:40:32 PM PDT 24
Peak memory 206032 kb
Host smart-65826166-b79c-4892-82d0-1f481f717de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027610286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3027610286
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.421367465
Short name T241
Test name
Test status
Simulation time 36936098 ps
CPU time 1.13 seconds
Started May 19 01:40:40 PM PDT 24
Finished May 19 01:40:42 PM PDT 24
Peak memory 206128 kb
Host smart-478c6ef5-95c7-4c63-8b2f-98d7c097f537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421367465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.421367465
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.477299221
Short name T939
Test name
Test status
Simulation time 54619652 ps
CPU time 2.16 seconds
Started May 19 01:40:31 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 214392 kb
Host smart-e4099d0e-1d32-4aee-875b-3441356046ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477299221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.477299221
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1568547448
Short name T957
Test name
Test status
Simulation time 158036634 ps
CPU time 2.38 seconds
Started May 19 01:40:30 PM PDT 24
Finished May 19 01:40:33 PM PDT 24
Peak memory 214392 kb
Host smart-10d02e50-648c-406b-8689-0d8473fdba5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568547448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1568547448
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2650397973
Short name T973
Test name
Test status
Simulation time 65471531 ps
CPU time 1.2 seconds
Started May 19 01:40:32 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 214376 kb
Host smart-310c7392-86ee-4ba1-bd1d-2259d56e08ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650397973 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2650397973
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1904098282
Short name T229
Test name
Test status
Simulation time 29512423 ps
CPU time 0.96 seconds
Started May 19 01:40:39 PM PDT 24
Finished May 19 01:40:41 PM PDT 24
Peak memory 206116 kb
Host smart-a9bd42b2-0f54-41e7-a424-5580f274e8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904098282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1904098282
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1158358648
Short name T951
Test name
Test status
Simulation time 36969197 ps
CPU time 0.86 seconds
Started May 19 01:40:33 PM PDT 24
Finished May 19 01:40:36 PM PDT 24
Peak memory 205888 kb
Host smart-861d52f2-8859-40cb-bc4b-7aa7705a2ee6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158358648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1158358648
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3701993307
Short name T242
Test name
Test status
Simulation time 243276084 ps
CPU time 1.19 seconds
Started May 19 01:40:33 PM PDT 24
Finished May 19 01:40:34 PM PDT 24
Peak memory 206116 kb
Host smart-fa472832-70ea-48e5-a297-f008fb0db201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701993307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3701993307
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3092872961
Short name T930
Test name
Test status
Simulation time 99748067 ps
CPU time 1.84 seconds
Started May 19 01:40:34 PM PDT 24
Finished May 19 01:40:37 PM PDT 24
Peak memory 214288 kb
Host smart-4209840e-8cbb-430f-947d-d26b22d8df02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092872961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3092872961
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.928743641
Short name T904
Test name
Test status
Simulation time 199753804 ps
CPU time 1.62 seconds
Started May 19 01:40:33 PM PDT 24
Finished May 19 01:40:36 PM PDT 24
Peak memory 206212 kb
Host smart-25e84f75-039f-4255-becd-165f89143dda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928743641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.928743641
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.893684173
Short name T862
Test name
Test status
Simulation time 107568394 ps
CPU time 1.43 seconds
Started May 19 01:40:38 PM PDT 24
Finished May 19 01:40:40 PM PDT 24
Peak memory 214480 kb
Host smart-094c04fc-4d6c-4f18-8012-7981bc78fa9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893684173 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.893684173
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1108894764
Short name T895
Test name
Test status
Simulation time 38991226 ps
CPU time 0.92 seconds
Started May 19 01:40:36 PM PDT 24
Finished May 19 01:40:38 PM PDT 24
Peak memory 206068 kb
Host smart-d5eb325f-8671-47dd-b04d-f77daff4dc09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108894764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1108894764
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2014640217
Short name T870
Test name
Test status
Simulation time 14412484 ps
CPU time 0.95 seconds
Started May 19 01:40:37 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 205996 kb
Host smart-504a5d42-ed81-40fd-be21-9529a03e2b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014640217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2014640217
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1742703923
Short name T899
Test name
Test status
Simulation time 110628304 ps
CPU time 1.29 seconds
Started May 19 01:40:37 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 206096 kb
Host smart-a1d12293-97ed-482f-bcdd-e2c295cfe219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742703923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1742703923
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1021365484
Short name T894
Test name
Test status
Simulation time 221798134 ps
CPU time 3.18 seconds
Started May 19 01:40:33 PM PDT 24
Finished May 19 01:40:37 PM PDT 24
Peak memory 214392 kb
Host smart-9d4b91a5-f382-4bad-8c82-332656acddb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021365484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1021365484
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.687062652
Short name T252
Test name
Test status
Simulation time 194627367 ps
CPU time 1.94 seconds
Started May 19 01:40:34 PM PDT 24
Finished May 19 01:40:37 PM PDT 24
Peak memory 206336 kb
Host smart-f356a393-59fd-453e-a90b-f55926fcc3f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687062652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.687062652
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3282053448
Short name T871
Test name
Test status
Simulation time 30586618 ps
CPU time 1.39 seconds
Started May 19 01:40:38 PM PDT 24
Finished May 19 01:40:41 PM PDT 24
Peak memory 214548 kb
Host smart-2baa570e-5073-4db9-8b64-3d0d36364607
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282053448 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3282053448
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4122540377
Short name T245
Test name
Test status
Simulation time 37621616 ps
CPU time 0.91 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 206052 kb
Host smart-0732c402-1342-4010-a968-266f5f89d830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122540377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4122540377
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1986621196
Short name T961
Test name
Test status
Simulation time 16053373 ps
CPU time 0.85 seconds
Started May 19 01:40:36 PM PDT 24
Finished May 19 01:40:38 PM PDT 24
Peak memory 205940 kb
Host smart-a667ec43-f803-4121-93f5-32fdf3f3d61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986621196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1986621196
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4196588804
Short name T226
Test name
Test status
Simulation time 309090740 ps
CPU time 1.58 seconds
Started May 19 01:40:36 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 206156 kb
Host smart-03687163-1ea9-4875-bd42-4384196f986e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196588804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4196588804
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1873970280
Short name T852
Test name
Test status
Simulation time 295143560 ps
CPU time 3.36 seconds
Started May 19 01:40:35 PM PDT 24
Finished May 19 01:40:39 PM PDT 24
Peak memory 214312 kb
Host smart-af17e6ef-14b1-4629-b704-f8b28139a90c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873970280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1873970280
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2690369365
Short name T947
Test name
Test status
Simulation time 125867221 ps
CPU time 3.06 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:45 PM PDT 24
Peak memory 206120 kb
Host smart-a54a2dc7-bc35-4e7a-847a-796bf9dcb50a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690369365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2690369365
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.315411410
Short name T967
Test name
Test status
Simulation time 21783831 ps
CPU time 1.07 seconds
Started May 19 01:40:38 PM PDT 24
Finished May 19 01:40:40 PM PDT 24
Peak memory 214344 kb
Host smart-38940799-f1de-4cb9-8011-ffa57a9a9c29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315411410 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.315411410
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.696796240
Short name T960
Test name
Test status
Simulation time 31863803 ps
CPU time 0.97 seconds
Started May 19 01:40:41 PM PDT 24
Finished May 19 01:40:43 PM PDT 24
Peak memory 206148 kb
Host smart-f0351aaf-ad63-46a9-9461-f82399e112e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696796240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.696796240
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4260584316
Short name T938
Test name
Test status
Simulation time 15055978 ps
CPU time 0.99 seconds
Started May 19 01:40:35 PM PDT 24
Finished May 19 01:40:37 PM PDT 24
Peak memory 206012 kb
Host smart-c26f3f81-953c-4242-81f8-2fbc04c8a12f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260584316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4260584316
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2097565176
Short name T964
Test name
Test status
Simulation time 54299449 ps
CPU time 1.05 seconds
Started May 19 01:40:36 PM PDT 24
Finished May 19 01:40:38 PM PDT 24
Peak memory 206260 kb
Host smart-516609c2-691b-4487-b0a5-1bbe0736ae56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097565176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2097565176
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3484226885
Short name T928
Test name
Test status
Simulation time 43001882 ps
CPU time 2.44 seconds
Started May 19 01:40:38 PM PDT 24
Finished May 19 01:40:41 PM PDT 24
Peak memory 214368 kb
Host smart-012bbce1-8aa1-4a7c-99ae-19f56476aebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484226885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3484226885
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.190694468
Short name T919
Test name
Test status
Simulation time 155879364 ps
CPU time 1.59 seconds
Started May 19 01:40:37 PM PDT 24
Finished May 19 01:40:40 PM PDT 24
Peak memory 206580 kb
Host smart-e7edb8bc-78e4-445f-8498-c33b201ea96f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190694468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.190694468
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3977092239
Short name T569
Test name
Test status
Simulation time 71413308 ps
CPU time 1.3 seconds
Started May 19 02:24:46 PM PDT 24
Finished May 19 02:24:48 PM PDT 24
Peak memory 215384 kb
Host smart-afc1ce44-9186-416d-89a6-7495a1665d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977092239 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3977092239
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2036300925
Short name T738
Test name
Test status
Simulation time 129669041 ps
CPU time 1.22 seconds
Started May 19 02:24:49 PM PDT 24
Finished May 19 02:24:51 PM PDT 24
Peak memory 214816 kb
Host smart-4717c657-fe67-4c97-86c2-c2c2510b4332
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036300925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2036300925
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3935083729
Short name T79
Test name
Test status
Simulation time 29406957 ps
CPU time 1.1 seconds
Started May 19 02:24:46 PM PDT 24
Finished May 19 02:24:48 PM PDT 24
Peak memory 219140 kb
Host smart-3b2c723e-1af9-434e-8fc7-f310782451ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935083729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3935083729
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.47178309
Short name T459
Test name
Test status
Simulation time 49288181 ps
CPU time 0.84 seconds
Started May 19 02:24:49 PM PDT 24
Finished May 19 02:24:51 PM PDT 24
Peak memory 218048 kb
Host smart-41d25ff2-a48f-4d95-989d-18bf1e22ecf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47178309 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.47178309
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.1040293882
Short name T773
Test name
Test status
Simulation time 23298374 ps
CPU time 1.21 seconds
Started May 19 02:24:50 PM PDT 24
Finished May 19 02:24:52 PM PDT 24
Peak memory 223608 kb
Host smart-8bff3f4e-f0ed-4849-953e-c695f906f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040293882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1040293882
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1817714963
Short name T788
Test name
Test status
Simulation time 15440140 ps
CPU time 0.94 seconds
Started May 19 02:24:42 PM PDT 24
Finished May 19 02:24:44 PM PDT 24
Peak memory 206848 kb
Host smart-c9a8e5bc-3c88-4bce-a00c-0b45d6fa0f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817714963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1817714963
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1281096305
Short name T65
Test name
Test status
Simulation time 980819625 ps
CPU time 7.79 seconds
Started May 19 02:24:47 PM PDT 24
Finished May 19 02:24:55 PM PDT 24
Peak memory 235296 kb
Host smart-78567c6a-30da-49b1-bd74-e321c9e9bbb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281096305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1281096305
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3537304695
Short name T717
Test name
Test status
Simulation time 25550305 ps
CPU time 0.99 seconds
Started May 19 02:24:40 PM PDT 24
Finished May 19 02:24:43 PM PDT 24
Peak memory 215012 kb
Host smart-b54294f9-c5f4-460c-9ea2-7b15f9965b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537304695 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3537304695
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3185138283
Short name T212
Test name
Test status
Simulation time 95199835 ps
CPU time 2.37 seconds
Started May 19 02:24:47 PM PDT 24
Finished May 19 02:24:50 PM PDT 24
Peak memory 217036 kb
Host smart-cc01913d-2fda-420c-a177-0dad9ee26aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185138283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3185138283
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2704200067
Short name T538
Test name
Test status
Simulation time 83569145956 ps
CPU time 264.5 seconds
Started May 19 02:24:45 PM PDT 24
Finished May 19 02:29:10 PM PDT 24
Peak memory 218700 kb
Host smart-1fcef868-7e43-464a-a4ae-6513955537d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704200067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2704200067
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1901283944
Short name T276
Test name
Test status
Simulation time 47965911 ps
CPU time 1.24 seconds
Started May 19 02:24:52 PM PDT 24
Finished May 19 02:24:54 PM PDT 24
Peak memory 215424 kb
Host smart-f05ad4f2-8a8e-4603-91af-ff38f34b31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901283944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1901283944
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.877673030
Short name T469
Test name
Test status
Simulation time 12881110 ps
CPU time 0.92 seconds
Started May 19 02:24:52 PM PDT 24
Finished May 19 02:24:54 PM PDT 24
Peak memory 215396 kb
Host smart-22c81dd4-126e-4e56-9fe9-f56829c9d655
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877673030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.877673030
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.133655154
Short name T132
Test name
Test status
Simulation time 24971411 ps
CPU time 1.1 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:24:58 PM PDT 24
Peak memory 223500 kb
Host smart-5d379f30-0269-49a0-b7e7-74c6a9b7a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133655154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.133655154
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2676655020
Short name T470
Test name
Test status
Simulation time 170275393 ps
CPU time 3.03 seconds
Started May 19 02:24:48 PM PDT 24
Finished May 19 02:24:52 PM PDT 24
Peak memory 219300 kb
Host smart-4f400b2d-19cf-442b-9fbf-65ea4a61b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676655020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2676655020
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3033428831
Short name T481
Test name
Test status
Simulation time 24220732 ps
CPU time 0.96 seconds
Started May 19 02:24:50 PM PDT 24
Finished May 19 02:24:51 PM PDT 24
Peak memory 215356 kb
Host smart-39cbc6c8-7f78-4059-8885-3820f5f7997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033428831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3033428831
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.318543573
Short name T18
Test name
Test status
Simulation time 1813306534 ps
CPU time 7.62 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 235760 kb
Host smart-fd2762cc-80d5-4a78-ad28-f54e61052f4a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318543573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.318543573
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.280548919
Short name T457
Test name
Test status
Simulation time 181891359 ps
CPU time 0.98 seconds
Started May 19 02:24:49 PM PDT 24
Finished May 19 02:24:51 PM PDT 24
Peak memory 215184 kb
Host smart-3b803223-2516-4589-9be8-044fed245421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280548919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.280548919
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.733844998
Short name T689
Test name
Test status
Simulation time 141857255 ps
CPU time 2.11 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:25:00 PM PDT 24
Peak memory 215032 kb
Host smart-b0009484-4c5a-43ec-8649-ea585b86b201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733844998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.733844998
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2921910027
Short name T198
Test name
Test status
Simulation time 68978213206 ps
CPU time 422.3 seconds
Started May 19 02:24:51 PM PDT 24
Finished May 19 02:31:54 PM PDT 24
Peak memory 217516 kb
Host smart-2e80fbf6-43a5-4d3d-a35f-27ae42471eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921910027 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2921910027
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1453014056
Short name T259
Test name
Test status
Simulation time 29565969 ps
CPU time 1.31 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 215420 kb
Host smart-f0dcfb94-ee1a-414b-8480-712d40cc2389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453014056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1453014056
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2501087028
Short name T820
Test name
Test status
Simulation time 32480755 ps
CPU time 0.96 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 206368 kb
Host smart-aad16132-bfa7-4c86-8e86-a168f9074b60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501087028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2501087028
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.24687354
Short name T616
Test name
Test status
Simulation time 13460313 ps
CPU time 0.9 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:34 PM PDT 24
Peak memory 216028 kb
Host smart-6aa32fc5-8532-4f17-8cf8-59d25fa7c13e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24687354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.24687354
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2519125010
Short name T101
Test name
Test status
Simulation time 60036104 ps
CPU time 1.18 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 216548 kb
Host smart-8b34cc41-d71a-4fd4-97fb-fd76f4a8902d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519125010 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2519125010
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.305764256
Short name T482
Test name
Test status
Simulation time 62084213 ps
CPU time 0.89 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:34 PM PDT 24
Peak memory 219544 kb
Host smart-579594cb-c69a-4071-935e-79586e748ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305764256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.305764256
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1549634760
Short name T406
Test name
Test status
Simulation time 35445415 ps
CPU time 1.25 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 216632 kb
Host smart-7da91c24-ceb2-44f3-a180-28d165aba3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549634760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1549634760
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2243138323
Short name T341
Test name
Test status
Simulation time 28751237 ps
CPU time 1 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 215080 kb
Host smart-529fdc2a-b1bf-448f-99af-79053670cc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243138323 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2243138323
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.414058717
Short name T363
Test name
Test status
Simulation time 16648305 ps
CPU time 0.98 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 215052 kb
Host smart-23464209-8385-4154-a4d3-ad6956c20153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414058717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.414058717
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.915847944
Short name T296
Test name
Test status
Simulation time 349171299 ps
CPU time 3.72 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 216656 kb
Host smart-8706a517-3c7f-4992-beb2-30633fa9d294
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915847944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.915847944
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1678917895
Short name T201
Test name
Test status
Simulation time 54989542392 ps
CPU time 609.88 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:35:41 PM PDT 24
Peak memory 218632 kb
Host smart-c1f16cb0-ba0e-40ce-b8ef-dcf81bf48422
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678917895 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1678917895
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3754244596
Short name T373
Test name
Test status
Simulation time 25757063 ps
CPU time 1.16 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 219388 kb
Host smart-b80be804-04a9-4317-96a7-441be45d0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754244596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3754244596
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.2537195127
Short name T723
Test name
Test status
Simulation time 81412693 ps
CPU time 1.13 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 216860 kb
Host smart-f9f02b61-1638-4823-9cc8-8539d30c1e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537195127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.2537195127
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.958583679
Short name T370
Test name
Test status
Simulation time 48240278 ps
CPU time 1.26 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 218936 kb
Host smart-9fc24b5a-6445-4535-a554-8a16efa988b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958583679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.958583679
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1379533689
Short name T614
Test name
Test status
Simulation time 54400384 ps
CPU time 1.16 seconds
Started May 19 02:27:41 PM PDT 24
Finished May 19 02:27:44 PM PDT 24
Peak memory 219356 kb
Host smart-e6f07fad-93b9-4632-b161-8bd475713db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379533689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1379533689
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.419231681
Short name T502
Test name
Test status
Simulation time 56134429 ps
CPU time 1.19 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 216732 kb
Host smart-f32b0559-612e-4fc6-b6c7-eebad9b79b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419231681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.419231681
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.769027463
Short name T768
Test name
Test status
Simulation time 53231431 ps
CPU time 1.35 seconds
Started May 19 02:27:47 PM PDT 24
Finished May 19 02:27:49 PM PDT 24
Peak memory 216804 kb
Host smart-93c8273f-dce1-4dc2-b25e-1a76f78ece0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769027463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.769027463
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2649816513
Short name T394
Test name
Test status
Simulation time 73309336 ps
CPU time 1.43 seconds
Started May 19 02:27:45 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 218120 kb
Host smart-0e1756e1-fdb9-4f55-8bcc-e5a8ede58367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649816513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2649816513
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3100575149
Short name T770
Test name
Test status
Simulation time 38912057 ps
CPU time 1.36 seconds
Started May 19 02:27:44 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 216564 kb
Host smart-f4a75b4e-437f-436c-b1b9-7825d77ac36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100575149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3100575149
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2103025231
Short name T278
Test name
Test status
Simulation time 29064710 ps
CPU time 1.36 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 215360 kb
Host smart-5e016ab6-0186-4488-a052-35aa4f195df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103025231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2103025231
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3204225090
Short name T474
Test name
Test status
Simulation time 25583814 ps
CPU time 1.2 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 206324 kb
Host smart-68b5d362-212e-49bd-9688-864dab8b3daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204225090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3204225090
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1513030105
Short name T46
Test name
Test status
Simulation time 154311592 ps
CPU time 0.89 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 215472 kb
Host smart-1cf71998-9ecd-4a79-b037-9f35ff23656d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513030105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1513030105
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1090921605
Short name T107
Test name
Test status
Simulation time 60018349 ps
CPU time 1.16 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:31 PM PDT 24
Peak memory 216620 kb
Host smart-36652173-8e18-437f-b695-3154cc802577
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090921605 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1090921605
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1903624100
Short name T116
Test name
Test status
Simulation time 23248412 ps
CPU time 1.08 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 223508 kb
Host smart-6eee80a8-a335-4f01-acec-dd5183433a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903624100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1903624100
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.3340466999
Short name T72
Test name
Test status
Simulation time 16834800 ps
CPU time 1 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 215000 kb
Host smart-25890783-7378-44e9-b4d4-5dbc1d0db8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340466999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3340466999
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.501656004
Short name T539
Test name
Test status
Simulation time 230590203 ps
CPU time 1.69 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:34 PM PDT 24
Peak memory 215144 kb
Host smart-fbad195b-8f9d-450f-beda-de9f16d6e5d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501656004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.501656004
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3518861452
Short name T461
Test name
Test status
Simulation time 25595744499 ps
CPU time 311.62 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:30:40 PM PDT 24
Peak memory 216320 kb
Host smart-9b875249-f989-4654-979d-bd90caefa781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518861452 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3518861452
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2762549002
Short name T699
Test name
Test status
Simulation time 58031870 ps
CPU time 1.34 seconds
Started May 19 02:27:44 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 218072 kb
Host smart-f84f8b2a-3985-4125-97e8-058814f8e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762549002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2762549002
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1302793554
Short name T786
Test name
Test status
Simulation time 57749624 ps
CPU time 1.12 seconds
Started May 19 02:27:44 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 216820 kb
Host smart-d5192d79-55fa-48e1-b259-f10cc1c7f549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302793554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1302793554
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.11345602
Short name T576
Test name
Test status
Simulation time 71106507 ps
CPU time 1.55 seconds
Started May 19 02:27:44 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 218020 kb
Host smart-b8ae99cf-03c5-4f7c-8967-0a1cc7d5d474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11345602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.11345602
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2440797712
Short name T543
Test name
Test status
Simulation time 59466441 ps
CPU time 1.58 seconds
Started May 19 02:27:43 PM PDT 24
Finished May 19 02:27:46 PM PDT 24
Peak memory 219436 kb
Host smart-1c202be8-3769-494e-84f1-7bce3080951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440797712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2440797712
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.3202145204
Short name T47
Test name
Test status
Simulation time 56489478 ps
CPU time 1.99 seconds
Started May 19 02:27:46 PM PDT 24
Finished May 19 02:27:49 PM PDT 24
Peak memory 217876 kb
Host smart-9e0e1463-075b-47f3-a891-570051072088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202145204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.3202145204
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.216863661
Short name T835
Test name
Test status
Simulation time 46676395 ps
CPU time 1.5 seconds
Started May 19 02:27:44 PM PDT 24
Finished May 19 02:27:47 PM PDT 24
Peak memory 217052 kb
Host smart-8d2fe8b4-d848-43c2-98e9-733a798286e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216863661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.216863661
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3699785760
Short name T651
Test name
Test status
Simulation time 59096897 ps
CPU time 2.11 seconds
Started May 19 02:27:47 PM PDT 24
Finished May 19 02:27:50 PM PDT 24
Peak memory 218340 kb
Host smart-8c71387a-90de-45ac-be6f-b58bf8e2b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699785760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3699785760
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1526875928
Short name T647
Test name
Test status
Simulation time 158619127 ps
CPU time 1.29 seconds
Started May 19 02:27:45 PM PDT 24
Finished May 19 02:27:48 PM PDT 24
Peak memory 218352 kb
Host smart-09bbf802-e596-40c0-aaec-064397169411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526875928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1526875928
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.147436456
Short name T271
Test name
Test status
Simulation time 51258792 ps
CPU time 1.25 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 215408 kb
Host smart-a44d3fe5-721d-4d5d-be26-d2f364e29a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147436456 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.147436456
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2501101469
Short name T705
Test name
Test status
Simulation time 15785844 ps
CPU time 0.95 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 214540 kb
Host smart-ce9bc18a-1ee6-44a7-8162-8b8972b0a7c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501101469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2501101469
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3520610787
Short name T671
Test name
Test status
Simulation time 20117055 ps
CPU time 0.87 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 216104 kb
Host smart-7de80efb-3e53-4d74-86bb-49050f98d136
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520610787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3520610787
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3490156429
Short name T745
Test name
Test status
Simulation time 226775212 ps
CPU time 1.24 seconds
Started May 19 02:25:33 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 216620 kb
Host smart-d9b96c71-dca5-4eab-9f28-89490d0cff7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490156429 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3490156429
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3503797259
Short name T840
Test name
Test status
Simulation time 18948524 ps
CPU time 1.06 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 218100 kb
Host smart-356282e3-aecb-4c7d-80eb-dd866f8774e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503797259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3503797259
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1875264600
Short name T841
Test name
Test status
Simulation time 170623008 ps
CPU time 2.7 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 219392 kb
Host smart-5b5b020b-e4d1-4179-8cc7-37ba23d9b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875264600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1875264600
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2552494139
Short name T720
Test name
Test status
Simulation time 21863796 ps
CPU time 0.91 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 215012 kb
Host smart-a40eda43-a6f4-42f6-b1aa-48919ac73760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552494139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2552494139
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.23942711
Short name T372
Test name
Test status
Simulation time 67437112 ps
CPU time 1.06 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 215196 kb
Host smart-74d459d7-f773-4d24-b98d-04bcd229414f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23942711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.23942711
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4154763547
Short name T791
Test name
Test status
Simulation time 63937908142 ps
CPU time 563.92 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:34:55 PM PDT 24
Peak memory 223368 kb
Host smart-49801494-2fb8-4081-bcd0-9e5302f12596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154763547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4154763547
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2973332012
Short name T620
Test name
Test status
Simulation time 103465161 ps
CPU time 2.22 seconds
Started May 19 02:27:46 PM PDT 24
Finished May 19 02:27:50 PM PDT 24
Peak memory 219596 kb
Host smart-c333ba03-738a-441a-9b2e-125fd2160bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973332012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2973332012
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3206756027
Short name T525
Test name
Test status
Simulation time 35527875 ps
CPU time 1.09 seconds
Started May 19 02:27:47 PM PDT 24
Finished May 19 02:27:49 PM PDT 24
Peak memory 216860 kb
Host smart-d3ef1d14-d03f-4cf4-8647-35a1dab48046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206756027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3206756027
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3773384215
Short name T403
Test name
Test status
Simulation time 30577724 ps
CPU time 1.33 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:54 PM PDT 24
Peak memory 219292 kb
Host smart-8cf85eb0-11b2-46f7-8528-11be3b689223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773384215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3773384215
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1599277157
Short name T536
Test name
Test status
Simulation time 84251003 ps
CPU time 1.21 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 218000 kb
Host smart-898c3f60-a61a-4f01-b83c-ee5f68754649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599277157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1599277157
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3210341785
Short name T66
Test name
Test status
Simulation time 181247558 ps
CPU time 1.07 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 215108 kb
Host smart-25bcdc4e-cf25-4d80-a513-1bebd6b057f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210341785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3210341785
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.781873664
Short name T300
Test name
Test status
Simulation time 795067515 ps
CPU time 4.48 seconds
Started May 19 02:27:51 PM PDT 24
Finished May 19 02:27:57 PM PDT 24
Peak memory 219284 kb
Host smart-38be401d-07d7-4230-bb9e-31044f7f8e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781873664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.781873664
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2256373987
Short name T715
Test name
Test status
Simulation time 90855757 ps
CPU time 1.49 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 218288 kb
Host smart-b39622f1-3eb7-4dd3-861e-9f0b19cc3d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256373987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2256373987
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.4037073437
Short name T827
Test name
Test status
Simulation time 308509040 ps
CPU time 1.64 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 218268 kb
Host smart-57ab87d6-3637-4bf6-8e0c-ccf37a2fb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037073437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.4037073437
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.4131859659
Short name T20
Test name
Test status
Simulation time 39020312 ps
CPU time 1.12 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 218016 kb
Host smart-ee28a8a1-46f9-4e61-9669-534647917325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131859659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4131859659
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1451485712
Short name T270
Test name
Test status
Simulation time 26838545 ps
CPU time 1.25 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 215424 kb
Host smart-b4a2d993-2732-48a5-b28f-bc745ff572e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451485712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1451485712
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.592985784
Short name T726
Test name
Test status
Simulation time 64631899 ps
CPU time 0.91 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 214560 kb
Host smart-3efd2bc6-86ec-40a0-a25d-fa72b8863f94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592985784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.592985784
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3108523793
Short name T195
Test name
Test status
Simulation time 12568212 ps
CPU time 0.88 seconds
Started May 19 02:25:32 PM PDT 24
Finished May 19 02:25:35 PM PDT 24
Peak memory 215408 kb
Host smart-2594effe-cd8d-40be-8510-c73b76787133
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108523793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3108523793
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2520908328
Short name T106
Test name
Test status
Simulation time 78591229 ps
CPU time 0.99 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 216728 kb
Host smart-9745b2d0-28e0-48f9-8d4d-8bad3309baef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520908328 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2520908328
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.3693949809
Short name T648
Test name
Test status
Simulation time 28016555 ps
CPU time 1.16 seconds
Started May 19 02:25:37 PM PDT 24
Finished May 19 02:25:40 PM PDT 24
Peak memory 216720 kb
Host smart-69679b92-594f-4e07-99d5-bd8d4948fac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693949809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3693949809
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1572608572
Short name T640
Test name
Test status
Simulation time 20762035 ps
CPU time 1.06 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 215084 kb
Host smart-ac1a52dc-1ea1-44d7-8e72-8405f1e8211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572608572 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1572608572
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3048995729
Short name T819
Test name
Test status
Simulation time 15647448 ps
CPU time 0.99 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:37 PM PDT 24
Peak memory 215004 kb
Host smart-683fb398-8f0d-4848-b4ac-6e5fca0095cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048995729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3048995729
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1724576334
Short name T754
Test name
Test status
Simulation time 292738063 ps
CPU time 5.81 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 216656 kb
Host smart-4fb8d2c0-ffb6-470e-8271-f66ee9093123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724576334 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1724576334
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2889422118
Short name T207
Test name
Test status
Simulation time 562468408965 ps
CPU time 707.98 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:37:25 PM PDT 24
Peak memory 220584 kb
Host smart-5f20b74a-20fa-4deb-af1f-e23aaf56a880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889422118 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2889422118
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1075427746
Short name T833
Test name
Test status
Simulation time 136877721 ps
CPU time 1.36 seconds
Started May 19 02:27:50 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 218216 kb
Host smart-c63cbc23-9530-4bd6-bfb1-426284044351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075427746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1075427746
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.277265843
Short name T425
Test name
Test status
Simulation time 44353155 ps
CPU time 1.45 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:53 PM PDT 24
Peak memory 217820 kb
Host smart-35f84903-2341-4fdc-9693-061f85deab82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277265843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.277265843
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.765089215
Short name T676
Test name
Test status
Simulation time 59574433 ps
CPU time 1.12 seconds
Started May 19 02:27:53 PM PDT 24
Finished May 19 02:27:55 PM PDT 24
Peak memory 216868 kb
Host smart-33573fb2-6b04-4b5f-b8fa-17fafbff3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765089215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.765089215
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1003355864
Short name T609
Test name
Test status
Simulation time 68346903 ps
CPU time 1.63 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:59 PM PDT 24
Peak memory 218144 kb
Host smart-8fdd4e6d-b927-4420-a4d6-f6302ed281c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003355864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1003355864
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1582408591
Short name T842
Test name
Test status
Simulation time 342924423 ps
CPU time 3.19 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:28:00 PM PDT 24
Peak memory 219184 kb
Host smart-66a78093-c2fe-46bd-afbd-44359d113ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582408591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1582408591
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2274867209
Short name T408
Test name
Test status
Simulation time 127937587 ps
CPU time 2.34 seconds
Started May 19 02:27:57 PM PDT 24
Finished May 19 02:28:00 PM PDT 24
Peak memory 219580 kb
Host smart-99bdd222-c844-4dac-ac22-be03a06e691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274867209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2274867209
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.981092386
Short name T399
Test name
Test status
Simulation time 73388021 ps
CPU time 1.39 seconds
Started May 19 02:27:55 PM PDT 24
Finished May 19 02:27:57 PM PDT 24
Peak memory 216612 kb
Host smart-1f32a4b3-970f-48e6-a68a-37ffc4f28c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981092386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.981092386
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.144880122
Short name T338
Test name
Test status
Simulation time 23781912 ps
CPU time 1.22 seconds
Started May 19 02:27:59 PM PDT 24
Finished May 19 02:28:00 PM PDT 24
Peak memory 219460 kb
Host smart-0b79bad0-dbb9-401b-aeb3-8452b43779b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144880122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.144880122
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2387144652
Short name T350
Test name
Test status
Simulation time 36372825 ps
CPU time 1.69 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:59 PM PDT 24
Peak memory 219508 kb
Host smart-b6a86465-1b04-41ef-98f6-097b3341f88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387144652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2387144652
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1769701481
Short name T395
Test name
Test status
Simulation time 79084046 ps
CPU time 1.35 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:58 PM PDT 24
Peak memory 217968 kb
Host smart-27e3fd1c-c96b-4df6-9e4f-ad747ed3405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769701481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1769701481
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.771683677
Short name T520
Test name
Test status
Simulation time 51096095 ps
CPU time 1.31 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 215420 kb
Host smart-30359ced-9886-4b37-b215-f7e084c88de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771683677 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.771683677
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4187529542
Short name T515
Test name
Test status
Simulation time 12567836 ps
CPU time 0.91 seconds
Started May 19 02:25:38 PM PDT 24
Finished May 19 02:25:41 PM PDT 24
Peak memory 206776 kb
Host smart-a3b94e16-8766-4176-90e1-71bfcee052cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187529542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4187529542
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.263978859
Short name T491
Test name
Test status
Simulation time 15357732 ps
CPU time 0.84 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:36 PM PDT 24
Peak memory 215628 kb
Host smart-413db38c-1512-4ec5-92a5-5cf2e8a94153
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263978859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.263978859
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.169609228
Short name T690
Test name
Test status
Simulation time 48353764 ps
CPU time 1.11 seconds
Started May 19 02:25:33 PM PDT 24
Finished May 19 02:25:37 PM PDT 24
Peak memory 219580 kb
Host smart-e35bad35-ace5-4e80-aada-e7f340d5b78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169609228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.169609228
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2748043574
Short name T13
Test name
Test status
Simulation time 58206288 ps
CPU time 1.76 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:39 PM PDT 24
Peak memory 217068 kb
Host smart-30bc6d11-eb28-40b5-9c8c-759c2411ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748043574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2748043574
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.2327464291
Short name T733
Test name
Test status
Simulation time 20140264 ps
CPU time 0.99 seconds
Started May 19 02:25:35 PM PDT 24
Finished May 19 02:25:38 PM PDT 24
Peak memory 215000 kb
Host smart-008abc46-afe5-4dfe-a1b9-de1ab1ecccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327464291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2327464291
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3965960700
Short name T566
Test name
Test status
Simulation time 1414793090 ps
CPU time 2.36 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:25:39 PM PDT 24
Peak memory 216684 kb
Host smart-8c60c50e-7aff-4ea7-91d7-1a0b82770cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965960700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3965960700
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2967846887
Short name T548
Test name
Test status
Simulation time 82406606573 ps
CPU time 811.08 seconds
Started May 19 02:25:34 PM PDT 24
Finished May 19 02:39:07 PM PDT 24
Peak memory 221920 kb
Host smart-3198d856-e2c7-4a71-a2e5-9e529673c5db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967846887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2967846887
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1304444707
Short name T710
Test name
Test status
Simulation time 53508676 ps
CPU time 1.95 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:59 PM PDT 24
Peak memory 216880 kb
Host smart-b49ff443-6545-4bcd-8202-09f88c572e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304444707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1304444707
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1930443836
Short name T476
Test name
Test status
Simulation time 102268766 ps
CPU time 1.68 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:59 PM PDT 24
Peak memory 218412 kb
Host smart-f7ac16a1-656e-4abb-a464-2cdee35549d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930443836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1930443836
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3341658819
Short name T736
Test name
Test status
Simulation time 64620280 ps
CPU time 1.03 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:58 PM PDT 24
Peak memory 216740 kb
Host smart-ed15ae3e-5f08-4e01-af8b-e95c704a62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341658819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3341658819
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1302643447
Short name T323
Test name
Test status
Simulation time 107853252 ps
CPU time 1.3 seconds
Started May 19 02:28:00 PM PDT 24
Finished May 19 02:28:03 PM PDT 24
Peak memory 216692 kb
Host smart-fe23cb40-b212-4331-8a9e-b7f9e90fdb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302643447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1302643447
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.647260098
Short name T514
Test name
Test status
Simulation time 83199268 ps
CPU time 1.2 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:58 PM PDT 24
Peak memory 216824 kb
Host smart-9511ad26-0233-4d30-a3c1-fe2868c08d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647260098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.647260098
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.4158785305
Short name T743
Test name
Test status
Simulation time 285906615 ps
CPU time 1.28 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:27:58 PM PDT 24
Peak memory 216816 kb
Host smart-5fec4166-bb11-4d88-a4bc-12a0fd3d1a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158785305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.4158785305
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1937720734
Short name T814
Test name
Test status
Simulation time 61473440 ps
CPU time 2.05 seconds
Started May 19 02:27:56 PM PDT 24
Finished May 19 02:28:00 PM PDT 24
Peak memory 217852 kb
Host smart-ec0d7ea8-54a5-4d50-9ea8-e7ac20b0bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937720734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1937720734
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3756751847
Short name T701
Test name
Test status
Simulation time 38443192 ps
CPU time 1.54 seconds
Started May 19 02:27:59 PM PDT 24
Finished May 19 02:28:01 PM PDT 24
Peak memory 217960 kb
Host smart-6266e743-25e4-4455-9d6c-d9bc2017e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756751847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3756751847
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2982475009
Short name T380
Test name
Test status
Simulation time 65563867 ps
CPU time 1.71 seconds
Started May 19 02:27:55 PM PDT 24
Finished May 19 02:27:57 PM PDT 24
Peak memory 217980 kb
Host smart-b11b561f-c956-45b3-a30e-30a29c093084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982475009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2982475009
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.4074683565
Short name T411
Test name
Test status
Simulation time 59934109 ps
CPU time 1.26 seconds
Started May 19 02:28:02 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 216836 kb
Host smart-8fbed803-07d9-4389-8f3b-504a21fb4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074683565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.4074683565
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3662206636
Short name T279
Test name
Test status
Simulation time 23441596 ps
CPU time 1.24 seconds
Started May 19 02:25:40 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 215408 kb
Host smart-35d58b73-4752-4904-baaa-8dec3f0a7c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662206636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3662206636
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2715156373
Short name T775
Test name
Test status
Simulation time 13230066 ps
CPU time 0.87 seconds
Started May 19 02:25:42 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 206712 kb
Host smart-66c4f855-6ae2-41fd-bb9c-41a967cbefc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715156373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2715156373
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2083535954
Short name T673
Test name
Test status
Simulation time 37142119 ps
CPU time 1.33 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 216672 kb
Host smart-2120ebc6-80f9-45b3-ac93-65986460ed45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083535954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2083535954
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3877472775
Short name T604
Test name
Test status
Simulation time 23156542 ps
CPU time 1.3 seconds
Started May 19 02:25:41 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 223480 kb
Host smart-7fdd7ef3-8718-4a7f-87ee-fa153de118ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877472775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3877472775
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.68624438
Short name T669
Test name
Test status
Simulation time 61548445 ps
CPU time 1.46 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 218148 kb
Host smart-0af1c544-6b67-47e7-bed0-268cb3a3c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68624438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.68624438
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.478185662
Short name T472
Test name
Test status
Simulation time 23590767 ps
CPU time 1.07 seconds
Started May 19 02:25:41 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 215356 kb
Host smart-910c15e8-e48d-44eb-924d-dba26011bf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478185662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.478185662
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.4266974939
Short name T552
Test name
Test status
Simulation time 18755912 ps
CPU time 0.95 seconds
Started May 19 02:25:38 PM PDT 24
Finished May 19 02:25:40 PM PDT 24
Peak memory 215028 kb
Host smart-68de7415-f02a-4990-abf4-f44c9e37c5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266974939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.4266974939
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1951632997
Short name T728
Test name
Test status
Simulation time 268078481 ps
CPU time 5.8 seconds
Started May 19 02:25:37 PM PDT 24
Finished May 19 02:25:44 PM PDT 24
Peak memory 214996 kb
Host smart-ffd48b0c-a358-4350-a5d8-7f02b1aef2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951632997 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1951632997
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3174716638
Short name T560
Test name
Test status
Simulation time 20915201983 ps
CPU time 393.67 seconds
Started May 19 02:25:38 PM PDT 24
Finished May 19 02:32:13 PM PDT 24
Peak memory 222952 kb
Host smart-ca0ed0ef-2414-4cac-8aa2-c7f246bc8a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174716638 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3174716638
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2523784429
Short name T748
Test name
Test status
Simulation time 149853411 ps
CPU time 1.86 seconds
Started May 19 02:28:00 PM PDT 24
Finished May 19 02:28:03 PM PDT 24
Peak memory 218056 kb
Host smart-26dd012a-4f9b-49ff-b8ae-39fbb6dbf303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523784429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2523784429
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1110604090
Short name T288
Test name
Test status
Simulation time 71171445 ps
CPU time 2.67 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 219712 kb
Host smart-8fc900e0-8261-412b-900f-45c528788935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110604090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1110604090
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3246120815
Short name T661
Test name
Test status
Simulation time 46128556 ps
CPU time 1.9 seconds
Started May 19 02:28:02 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 216944 kb
Host smart-1c0c4ef1-f3db-4ce4-b26a-c7d2e43ea1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246120815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3246120815
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1839007909
Short name T444
Test name
Test status
Simulation time 26931774 ps
CPU time 1.18 seconds
Started May 19 02:28:03 PM PDT 24
Finished May 19 02:28:06 PM PDT 24
Peak memory 217836 kb
Host smart-67eca047-aa3c-4538-99f0-4719329aedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839007909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1839007909
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.4008805924
Short name T484
Test name
Test status
Simulation time 32857561 ps
CPU time 1.54 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 217916 kb
Host smart-cf978a03-1249-4358-9bbf-5558b2e0450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008805924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.4008805924
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4067314907
Short name T307
Test name
Test status
Simulation time 255352216 ps
CPU time 1.25 seconds
Started May 19 02:28:04 PM PDT 24
Finished May 19 02:28:07 PM PDT 24
Peak memory 216808 kb
Host smart-784cdb63-11fa-4d8a-bda4-b2d0b41abbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067314907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4067314907
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2963201167
Short name T368
Test name
Test status
Simulation time 60955544 ps
CPU time 1.53 seconds
Started May 19 02:28:04 PM PDT 24
Finished May 19 02:28:07 PM PDT 24
Peak memory 219764 kb
Host smart-29462586-6f53-4f2e-983a-66599b5a5262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963201167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2963201167
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1006828944
Short name T544
Test name
Test status
Simulation time 55884447 ps
CPU time 1.74 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:03 PM PDT 24
Peak memory 217912 kb
Host smart-354d7729-69e2-4b8e-b6fd-b291fac3bcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006828944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1006828944
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2588620251
Short name T695
Test name
Test status
Simulation time 163075874 ps
CPU time 3.55 seconds
Started May 19 02:28:00 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 219484 kb
Host smart-da29905f-1d4b-4c20-a1af-ae510b081c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588620251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2588620251
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3955914900
Short name T168
Test name
Test status
Simulation time 23489653 ps
CPU time 1.24 seconds
Started May 19 02:25:38 PM PDT 24
Finished May 19 02:25:41 PM PDT 24
Peak memory 215400 kb
Host smart-fd0f191d-7b98-449f-a613-d91a42e186e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955914900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3955914900
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3413279887
Short name T810
Test name
Test status
Simulation time 18733085 ps
CPU time 0.83 seconds
Started May 19 02:25:43 PM PDT 24
Finished May 19 02:25:45 PM PDT 24
Peak memory 206632 kb
Host smart-c6510d82-df9e-42cd-9e40-82d61d062316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413279887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3413279887
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1522707289
Short name T662
Test name
Test status
Simulation time 13860181 ps
CPU time 0.92 seconds
Started May 19 02:25:41 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 215392 kb
Host smart-8ae45d71-7d2c-4b0d-ada9-76b1fa3eb395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522707289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1522707289
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3966164984
Short name T483
Test name
Test status
Simulation time 69828706 ps
CPU time 1.18 seconds
Started May 19 02:25:42 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 216788 kb
Host smart-f1947402-86fc-4329-a63a-4c5f0ed4d0a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966164984 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3966164984
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3495495174
Short name T534
Test name
Test status
Simulation time 23277636 ps
CPU time 1.17 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:42 PM PDT 24
Peak memory 219536 kb
Host smart-f71d8f60-fd4b-4644-b5ee-f13dd4f1b465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495495174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3495495174
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3912562499
Short name T739
Test name
Test status
Simulation time 38098006 ps
CPU time 1.03 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:41 PM PDT 24
Peak memory 216664 kb
Host smart-d79f9ecf-8721-4628-96fb-f9e2a37a2ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912562499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3912562499
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1849932764
Short name T35
Test name
Test status
Simulation time 34738945 ps
CPU time 0.97 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:41 PM PDT 24
Peak memory 215328 kb
Host smart-080a79db-0f9c-45ae-8fa7-c3a2a504afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849932764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1849932764
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2153984182
Short name T319
Test name
Test status
Simulation time 51915988 ps
CPU time 1.04 seconds
Started May 19 02:25:38 PM PDT 24
Finished May 19 02:25:41 PM PDT 24
Peak memory 215016 kb
Host smart-0dc92c51-ca65-42d2-b492-a9321842505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153984182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2153984182
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3536817914
Short name T504
Test name
Test status
Simulation time 385434807 ps
CPU time 3.09 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:25:43 PM PDT 24
Peak memory 215144 kb
Host smart-8e77299f-0f6d-4baf-a39d-f830865e640f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536817914 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3536817914
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2365911263
Short name T817
Test name
Test status
Simulation time 40077107779 ps
CPU time 243.52 seconds
Started May 19 02:25:39 PM PDT 24
Finished May 19 02:29:44 PM PDT 24
Peak memory 218100 kb
Host smart-99a369ae-d1f2-4831-8ebf-377a9e940d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365911263 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2365911263
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2880675190
Short name T828
Test name
Test status
Simulation time 264488919 ps
CPU time 1.13 seconds
Started May 19 02:28:04 PM PDT 24
Finished May 19 02:28:06 PM PDT 24
Peak memory 216804 kb
Host smart-7b8ac190-567c-45b2-8e4e-411a66b0b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880675190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2880675190
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3933677151
Short name T162
Test name
Test status
Simulation time 44679692 ps
CPU time 1.57 seconds
Started May 19 02:28:02 PM PDT 24
Finished May 19 02:28:05 PM PDT 24
Peak memory 217972 kb
Host smart-b04eb12b-f874-49e0-a4ab-31722dd4c2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933677151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3933677151
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1577776682
Short name T847
Test name
Test status
Simulation time 47137428 ps
CPU time 1.3 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:03 PM PDT 24
Peak memory 218012 kb
Host smart-7a56b2ae-2186-4cd2-bcdb-f25ddc185bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577776682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1577776682
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3053656547
Short name T579
Test name
Test status
Simulation time 49811457 ps
CPU time 1.41 seconds
Started May 19 02:28:02 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 218080 kb
Host smart-b77a8c2f-3986-4d06-b074-c32d92c5d9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053656547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3053656547
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.998786399
Short name T649
Test name
Test status
Simulation time 77375834 ps
CPU time 1.64 seconds
Started May 19 02:28:03 PM PDT 24
Finished May 19 02:28:06 PM PDT 24
Peak memory 219536 kb
Host smart-e4d63d48-d224-49a8-9c77-dae14c7809dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998786399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.998786399
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.936976485
Short name T435
Test name
Test status
Simulation time 205948228 ps
CPU time 2.54 seconds
Started May 19 02:28:01 PM PDT 24
Finished May 19 02:28:04 PM PDT 24
Peak memory 216972 kb
Host smart-72600c50-b8d0-4264-b4d8-4b19eb767880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936976485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.936976485
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.544463360
Short name T541
Test name
Test status
Simulation time 67400603 ps
CPU time 1.28 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:09 PM PDT 24
Peak memory 218496 kb
Host smart-ede092ba-89cf-4af8-ace5-e63eaf2a2a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544463360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.544463360
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2649093472
Short name T422
Test name
Test status
Simulation time 85444054 ps
CPU time 2.77 seconds
Started May 19 02:28:07 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 217992 kb
Host smart-3c0d195c-0c3e-4b5d-a648-4647be7ec234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649093472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2649093472
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1243799781
Short name T759
Test name
Test status
Simulation time 166383069 ps
CPU time 1.42 seconds
Started May 19 02:25:45 PM PDT 24
Finished May 19 02:25:47 PM PDT 24
Peak memory 215332 kb
Host smart-76b6f1f1-eb97-4a7d-8130-c74d0bf6ab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243799781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1243799781
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.969297803
Short name T490
Test name
Test status
Simulation time 23526925 ps
CPU time 0.97 seconds
Started May 19 02:25:45 PM PDT 24
Finished May 19 02:25:46 PM PDT 24
Peak memory 206204 kb
Host smart-d9519376-8bc0-49f7-b393-e79dffb7f45e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969297803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.969297803
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1208779608
Short name T119
Test name
Test status
Simulation time 70371243 ps
CPU time 1.17 seconds
Started May 19 02:25:49 PM PDT 24
Finished May 19 02:25:51 PM PDT 24
Peak memory 216700 kb
Host smart-d41cc92d-ea13-4a57-97ba-59fa0f537765
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208779608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1208779608
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.833173712
Short name T61
Test name
Test status
Simulation time 25588666 ps
CPU time 1.08 seconds
Started May 19 02:25:43 PM PDT 24
Finished May 19 02:25:45 PM PDT 24
Peak memory 223456 kb
Host smart-5dc520d5-5f02-4bb7-a913-b6c46d7442a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833173712 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.833173712
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2392577249
Short name T306
Test name
Test status
Simulation time 41468089 ps
CPU time 1.48 seconds
Started May 19 02:25:49 PM PDT 24
Finished May 19 02:25:51 PM PDT 24
Peak memory 218900 kb
Host smart-422e0d49-f029-405b-bee4-18e1c6891e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392577249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2392577249
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1999279939
Short name T802
Test name
Test status
Simulation time 27281313 ps
CPU time 0.97 seconds
Started May 19 02:25:43 PM PDT 24
Finished May 19 02:25:45 PM PDT 24
Peak memory 215420 kb
Host smart-ee936ebd-5f07-4169-a9b7-6c6af548dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999279939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1999279939
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.954565135
Short name T533
Test name
Test status
Simulation time 16675261 ps
CPU time 1 seconds
Started May 19 02:25:50 PM PDT 24
Finished May 19 02:25:52 PM PDT 24
Peak memory 215004 kb
Host smart-7e651cd8-d6b5-4f99-906f-ffe56f440b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954565135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.954565135
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1108765503
Short name T598
Test name
Test status
Simulation time 79439438 ps
CPU time 1.96 seconds
Started May 19 02:25:43 PM PDT 24
Finished May 19 02:25:45 PM PDT 24
Peak memory 215020 kb
Host smart-624bd6e6-f7a1-4f2c-8a76-fedc1250ad75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108765503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1108765503
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3655773302
Short name T582
Test name
Test status
Simulation time 390564768983 ps
CPU time 2845.8 seconds
Started May 19 02:25:45 PM PDT 24
Finished May 19 03:13:11 PM PDT 24
Peak memory 231720 kb
Host smart-36fba2ae-e5e0-4149-a910-bb611d2fcf6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655773302 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3655773302
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2506838786
Short name T299
Test name
Test status
Simulation time 142016674 ps
CPU time 2.1 seconds
Started May 19 02:28:07 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 218048 kb
Host smart-590bb05f-9d81-45b8-a48e-17892a494409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506838786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2506838786
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.4224313871
Short name T589
Test name
Test status
Simulation time 65688887 ps
CPU time 1.52 seconds
Started May 19 02:28:08 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 218048 kb
Host smart-685819cb-2eba-475e-bfb7-ae9df8e0f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224313871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4224313871
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2306968063
Short name T848
Test name
Test status
Simulation time 43361900 ps
CPU time 1.14 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:09 PM PDT 24
Peak memory 217884 kb
Host smart-9e6eaf16-ac00-49aa-bccd-e2082da3d785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306968063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2306968063
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3203855667
Short name T302
Test name
Test status
Simulation time 48832968 ps
CPU time 1.64 seconds
Started May 19 02:28:09 PM PDT 24
Finished May 19 02:28:13 PM PDT 24
Peak memory 218008 kb
Host smart-42954e0c-9890-40f1-aa2b-b94d67f2c2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203855667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3203855667
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.181617647
Short name T766
Test name
Test status
Simulation time 35788805 ps
CPU time 1.07 seconds
Started May 19 02:28:08 PM PDT 24
Finished May 19 02:28:11 PM PDT 24
Peak memory 218956 kb
Host smart-89511145-b462-4edc-9c7e-bcf81423b9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181617647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.181617647
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3638160178
Short name T453
Test name
Test status
Simulation time 61195609 ps
CPU time 1.58 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:08 PM PDT 24
Peak memory 218104 kb
Host smart-463085a2-dd27-434a-92b5-a5b656af6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638160178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3638160178
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2162908481
Short name T402
Test name
Test status
Simulation time 224739438 ps
CPU time 2.64 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:11 PM PDT 24
Peak memory 217908 kb
Host smart-ee33bf15-5900-4faf-86cf-679127d36c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162908481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2162908481
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2057947794
Short name T578
Test name
Test status
Simulation time 66422816 ps
CPU time 1.41 seconds
Started May 19 02:28:11 PM PDT 24
Finished May 19 02:28:14 PM PDT 24
Peak memory 217912 kb
Host smart-2f907c74-6ac1-44a9-a514-be305c99cd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057947794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2057947794
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2857103564
Short name T289
Test name
Test status
Simulation time 124618172 ps
CPU time 2.93 seconds
Started May 19 02:28:07 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 217136 kb
Host smart-e2b5df3f-74c5-473f-b1a1-bd445e941da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857103564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2857103564
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3792291478
Short name T808
Test name
Test status
Simulation time 116569591 ps
CPU time 1.07 seconds
Started May 19 02:28:10 PM PDT 24
Finished May 19 02:28:14 PM PDT 24
Peak memory 219248 kb
Host smart-a2b8c5ec-d034-472b-80d4-d08e1c7f50d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792291478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3792291478
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.1588623593
Short name T478
Test name
Test status
Simulation time 34655245 ps
CPU time 1.05 seconds
Started May 19 02:25:53 PM PDT 24
Finished May 19 02:25:54 PM PDT 24
Peak memory 214572 kb
Host smart-2b01e82e-b3ac-4122-8d23-21fbd16ceb35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588623593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1588623593
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.524875489
Short name T526
Test name
Test status
Simulation time 135363015 ps
CPU time 0.86 seconds
Started May 19 02:25:49 PM PDT 24
Finished May 19 02:25:51 PM PDT 24
Peak memory 215236 kb
Host smart-1e474831-fe0c-445d-b898-0daebac74ace
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524875489 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.524875489
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3039224454
Short name T99
Test name
Test status
Simulation time 63113273 ps
CPU time 1.47 seconds
Started May 19 02:25:52 PM PDT 24
Finished May 19 02:25:54 PM PDT 24
Peak memory 216644 kb
Host smart-601681ef-448d-4201-b1cb-cc74ccfbe4ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039224454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3039224454
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.3105221144
Short name T799
Test name
Test status
Simulation time 20756876 ps
CPU time 1.11 seconds
Started May 19 02:25:47 PM PDT 24
Finished May 19 02:25:48 PM PDT 24
Peak memory 219532 kb
Host smart-498e95fd-3829-4819-8342-6d1a8e879bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105221144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3105221144
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1967488146
Short name T813
Test name
Test status
Simulation time 54140587 ps
CPU time 1.22 seconds
Started May 19 02:25:50 PM PDT 24
Finished May 19 02:25:52 PM PDT 24
Peak memory 218164 kb
Host smart-15c233ec-6cee-4212-965c-da481aca279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967488146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1967488146
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2111287042
Short name T761
Test name
Test status
Simulation time 55332954 ps
CPU time 0.95 seconds
Started May 19 02:25:48 PM PDT 24
Finished May 19 02:25:49 PM PDT 24
Peak memory 223416 kb
Host smart-045c30f4-41c6-4c5e-98b2-5fdd585990b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111287042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2111287042
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3720144434
Short name T677
Test name
Test status
Simulation time 27084076 ps
CPU time 0.91 seconds
Started May 19 02:25:51 PM PDT 24
Finished May 19 02:25:52 PM PDT 24
Peak memory 214984 kb
Host smart-6ca53e8f-0f31-494a-9980-f2527ab786a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720144434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3720144434
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1945886123
Short name T785
Test name
Test status
Simulation time 234075699 ps
CPU time 2.77 seconds
Started May 19 02:25:49 PM PDT 24
Finished May 19 02:25:53 PM PDT 24
Peak memory 216628 kb
Host smart-a52e7ea3-b2f3-458b-8dda-34aa97e78b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945886123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1945886123
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3723945634
Short name T510
Test name
Test status
Simulation time 36951164890 ps
CPU time 991.61 seconds
Started May 19 02:25:48 PM PDT 24
Finished May 19 02:42:20 PM PDT 24
Peak memory 219676 kb
Host smart-139db8ce-d34b-4fa1-9f96-c5778cf40524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723945634 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3723945634
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3461077942
Short name T497
Test name
Test status
Simulation time 90113277 ps
CPU time 1.25 seconds
Started May 19 02:28:11 PM PDT 24
Finished May 19 02:28:14 PM PDT 24
Peak memory 216692 kb
Host smart-3cfe0151-aa34-48fb-8d89-7bccb43f1f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461077942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3461077942
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1522919285
Short name T314
Test name
Test status
Simulation time 60518861 ps
CPU time 1.19 seconds
Started May 19 02:28:07 PM PDT 24
Finished May 19 02:28:10 PM PDT 24
Peak memory 216868 kb
Host smart-999c7daf-5bfc-4722-9990-d8eba6b87310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522919285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1522919285
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2872931304
Short name T599
Test name
Test status
Simulation time 54910861 ps
CPU time 1.22 seconds
Started May 19 02:28:09 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 217792 kb
Host smart-ae4ca5ee-8215-4813-a106-fa6876b82033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872931304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2872931304
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.34806781
Short name T711
Test name
Test status
Simulation time 58166471 ps
CPU time 1.37 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:10 PM PDT 24
Peak memory 218016 kb
Host smart-4ef6ba07-d405-471a-8946-4e5aab7401ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34806781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.34806781
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2685759986
Short name T568
Test name
Test status
Simulation time 74959922 ps
CPU time 1.58 seconds
Started May 19 02:28:09 PM PDT 24
Finished May 19 02:28:13 PM PDT 24
Peak memory 218060 kb
Host smart-134ee1ba-2645-40dd-9b47-ff8d8b236cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685759986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2685759986
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2848269964
Short name T570
Test name
Test status
Simulation time 163717934 ps
CPU time 3.18 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 219828 kb
Host smart-85cc8510-3dc7-4f8f-8619-96d441a8fd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848269964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2848269964
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3670059264
Short name T606
Test name
Test status
Simulation time 143857071 ps
CPU time 1.4 seconds
Started May 19 02:28:10 PM PDT 24
Finished May 19 02:28:14 PM PDT 24
Peak memory 219752 kb
Host smart-3f5cbb85-f16d-48f5-b1a8-133341e7cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670059264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3670059264
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.138459975
Short name T687
Test name
Test status
Simulation time 53823358 ps
CPU time 1.9 seconds
Started May 19 02:28:10 PM PDT 24
Finished May 19 02:28:14 PM PDT 24
Peak memory 217756 kb
Host smart-055458a9-0671-48c7-910d-2da726d5c1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138459975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.138459975
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3045211920
Short name T642
Test name
Test status
Simulation time 99803822 ps
CPU time 1.28 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:10 PM PDT 24
Peak memory 218292 kb
Host smart-75bc4176-d7cb-4277-85b9-5648c93a1b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045211920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3045211920
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3996073060
Short name T794
Test name
Test status
Simulation time 68919962 ps
CPU time 1.19 seconds
Started May 19 02:28:09 PM PDT 24
Finished May 19 02:28:12 PM PDT 24
Peak memory 217976 kb
Host smart-e6fb1970-1248-4ab5-924f-befb86c33255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996073060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3996073060
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2258033809
Short name T431
Test name
Test status
Simulation time 29224577 ps
CPU time 1.23 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 215396 kb
Host smart-7aa5a1a3-bc89-4872-ba5e-88e0b13b0289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258033809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2258033809
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.1256806274
Short name T424
Test name
Test status
Simulation time 136689523 ps
CPU time 0.95 seconds
Started May 19 02:25:53 PM PDT 24
Finished May 19 02:25:55 PM PDT 24
Peak memory 206324 kb
Host smart-6f0b7a76-6240-427e-9b61-1516d03a7812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256806274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1256806274
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1288725615
Short name T781
Test name
Test status
Simulation time 25082547 ps
CPU time 0.98 seconds
Started May 19 02:25:56 PM PDT 24
Finished May 19 02:25:57 PM PDT 24
Peak memory 216528 kb
Host smart-b4493f44-cabb-4619-bd71-1792611107dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288725615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1288725615
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3677577372
Short name T185
Test name
Test status
Simulation time 19422837 ps
CPU time 1.05 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 218288 kb
Host smart-84665ee3-2db5-41db-aa8b-0b7c8484c25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677577372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3677577372
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4248077927
Short name T784
Test name
Test status
Simulation time 72133397 ps
CPU time 1.5 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 217944 kb
Host smart-6da452f0-67db-45ae-a248-ce7c317e3ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248077927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4248077927
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1599551435
Short name T556
Test name
Test status
Simulation time 26331054 ps
CPU time 1.06 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 215660 kb
Host smart-8b24b089-7fde-4937-bf43-ba7784fe2c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599551435 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1599551435
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.126193296
Short name T608
Test name
Test status
Simulation time 17116592 ps
CPU time 0.97 seconds
Started May 19 02:25:51 PM PDT 24
Finished May 19 02:25:53 PM PDT 24
Peak memory 215256 kb
Host smart-56bc51aa-6b4c-4ebf-9374-1f1b89c61ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126193296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.126193296
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2701038520
Short name T358
Test name
Test status
Simulation time 157775615 ps
CPU time 1.41 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 206708 kb
Host smart-ee8932f8-eb75-48a5-8672-77b23b97d8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701038520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2701038520
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.639270056
Short name T206
Test name
Test status
Simulation time 100076190797 ps
CPU time 1247.79 seconds
Started May 19 02:25:56 PM PDT 24
Finished May 19 02:46:44 PM PDT 24
Peak memory 222340 kb
Host smart-0f7793de-016d-4497-9d12-445ea973f7d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639270056 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.639270056
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.282395324
Short name T702
Test name
Test status
Simulation time 50028682 ps
CPU time 1.16 seconds
Started May 19 02:28:07 PM PDT 24
Finished May 19 02:28:10 PM PDT 24
Peak memory 216724 kb
Host smart-910cd36f-4689-486e-a4d0-c05c059d3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282395324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.282395324
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.313701138
Short name T803
Test name
Test status
Simulation time 37957323 ps
CPU time 1.1 seconds
Started May 19 02:28:06 PM PDT 24
Finished May 19 02:28:09 PM PDT 24
Peak memory 219156 kb
Host smart-0abc1cd4-3871-4b28-8faf-189f78b23719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313701138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.313701138
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.674054317
Short name T305
Test name
Test status
Simulation time 947052444 ps
CPU time 6.73 seconds
Started May 19 02:28:09 PM PDT 24
Finished May 19 02:28:18 PM PDT 24
Peak memory 216904 kb
Host smart-9d960aba-df04-4b0e-b433-7b6e741efdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674054317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.674054317
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1762676878
Short name T387
Test name
Test status
Simulation time 46436812 ps
CPU time 1.17 seconds
Started May 19 02:28:12 PM PDT 24
Finished May 19 02:28:16 PM PDT 24
Peak memory 216712 kb
Host smart-1d73e1c2-aa68-429f-87cb-61cb53a40f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762676878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1762676878
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1257318241
Short name T415
Test name
Test status
Simulation time 83527678 ps
CPU time 1.24 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 217952 kb
Host smart-b5b4b8a0-f823-408e-ac13-2b2486b7ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257318241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1257318241
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3015261115
Short name T210
Test name
Test status
Simulation time 146391252 ps
CPU time 3.22 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:25 PM PDT 24
Peak memory 218004 kb
Host smart-b9d421aa-b201-43a0-8684-868a22c1c999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015261115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3015261115
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2564980519
Short name T74
Test name
Test status
Simulation time 38201711 ps
CPU time 1.42 seconds
Started May 19 02:28:11 PM PDT 24
Finished May 19 02:28:15 PM PDT 24
Peak memory 217788 kb
Host smart-be8704a2-87d0-45b1-abc0-8e8967d736cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564980519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2564980519
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3904239205
Short name T719
Test name
Test status
Simulation time 121140081 ps
CPU time 1.81 seconds
Started May 19 02:28:16 PM PDT 24
Finished May 19 02:28:20 PM PDT 24
Peak memory 219600 kb
Host smart-cc10642d-7517-4377-a93a-a0629b6dcb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904239205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3904239205
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.669624545
Short name T809
Test name
Test status
Simulation time 40316540 ps
CPU time 1.44 seconds
Started May 19 02:28:12 PM PDT 24
Finished May 19 02:28:16 PM PDT 24
Peak memory 216664 kb
Host smart-46248c84-8918-47fb-b282-37e96a013c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669624545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.669624545
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2969764780
Short name T343
Test name
Test status
Simulation time 193229324 ps
CPU time 2.22 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:21 PM PDT 24
Peak memory 219716 kb
Host smart-c4e2c9ab-70b8-41c2-aba0-ba11243d053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969764780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2969764780
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.728828298
Short name T774
Test name
Test status
Simulation time 112345384 ps
CPU time 0.83 seconds
Started May 19 02:25:00 PM PDT 24
Finished May 19 02:25:02 PM PDT 24
Peak memory 206152 kb
Host smart-0632ae70-0b45-475c-a6dd-5c81e95b7ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728828298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.728828298
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.267446204
Short name T169
Test name
Test status
Simulation time 38503476 ps
CPU time 1.08 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:24:58 PM PDT 24
Peak memory 216640 kb
Host smart-d5b0e92f-92bb-4002-a094-1c547e29caae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267446204 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.267446204
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3249655976
Short name T130
Test name
Test status
Simulation time 29348571 ps
CPU time 1.06 seconds
Started May 19 02:24:59 PM PDT 24
Finished May 19 02:25:01 PM PDT 24
Peak memory 223348 kb
Host smart-e6905dad-0328-4243-b473-50714b726c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249655976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3249655976
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1339142944
Short name T475
Test name
Test status
Simulation time 260012116 ps
CPU time 2.58 seconds
Started May 19 02:24:55 PM PDT 24
Finished May 19 02:24:59 PM PDT 24
Peak memory 217100 kb
Host smart-ff483134-460d-4a25-a68a-d54a0da646a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339142944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1339142944
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1705048775
Short name T511
Test name
Test status
Simulation time 38004319 ps
CPU time 0.93 seconds
Started May 19 02:24:59 PM PDT 24
Finished May 19 02:25:00 PM PDT 24
Peak memory 215192 kb
Host smart-e401d93f-2f47-4231-ab5f-56447986f932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705048775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1705048775
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.2877532797
Short name T834
Test name
Test status
Simulation time 24661129 ps
CPU time 0.95 seconds
Started May 19 02:24:55 PM PDT 24
Finished May 19 02:24:57 PM PDT 24
Peak memory 215000 kb
Host smart-cb543c79-3ac1-4ec8-8f57-0a7f83e95dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877532797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2877532797
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.381810077
Short name T704
Test name
Test status
Simulation time 343077898 ps
CPU time 2.62 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:24:59 PM PDT 24
Peak memory 216652 kb
Host smart-fd74fcf3-f925-46ef-b667-fa0e59e2058f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381810077 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.381810077
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3382052616
Short name T477
Test name
Test status
Simulation time 323305915035 ps
CPU time 1042.54 seconds
Started May 19 02:24:56 PM PDT 24
Finished May 19 02:42:20 PM PDT 24
Peak memory 223460 kb
Host smart-2a8d8eb4-da97-461e-8811-7115f6e40474
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382052616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3382052616
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.541645838
Short name T318
Test name
Test status
Simulation time 21235826 ps
CPU time 1.06 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 206384 kb
Host smart-a31ee169-f4da-4ea4-943b-0ee788bbce64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541645838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.541645838
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4199584992
Short name T655
Test name
Test status
Simulation time 26774277 ps
CPU time 0.83 seconds
Started May 19 02:26:00 PM PDT 24
Finished May 19 02:26:01 PM PDT 24
Peak memory 216084 kb
Host smart-8445db2e-cbf2-4d2c-8b6b-b2ad7df42495
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199584992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4199584992
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1742878982
Short name T327
Test name
Test status
Simulation time 98035251 ps
CPU time 1.22 seconds
Started May 19 02:26:00 PM PDT 24
Finished May 19 02:26:02 PM PDT 24
Peak memory 216696 kb
Host smart-f52e61bc-58e9-48aa-801d-0c55f5f8b37b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742878982 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1742878982
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3146137795
Short name T117
Test name
Test status
Simulation time 46019354 ps
CPU time 1.09 seconds
Started May 19 02:25:59 PM PDT 24
Finished May 19 02:26:01 PM PDT 24
Peak memory 229316 kb
Host smart-ae1cceb7-5dde-40ab-b84b-6a6c21bf4272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146137795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3146137795
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1504179723
Short name T849
Test name
Test status
Simulation time 37808651 ps
CPU time 1.42 seconds
Started May 19 02:25:54 PM PDT 24
Finished May 19 02:25:56 PM PDT 24
Peak memory 215056 kb
Host smart-99d67014-30b8-4a40-98bc-f5dda814c996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504179723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1504179723
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3116640486
Short name T571
Test name
Test status
Simulation time 35223011 ps
CPU time 1.01 seconds
Started May 19 02:25:57 PM PDT 24
Finished May 19 02:25:59 PM PDT 24
Peak memory 223444 kb
Host smart-c806c2db-f506-4585-af4a-acc0b72d58d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116640486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3116640486
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.949967464
Short name T740
Test name
Test status
Simulation time 24246340 ps
CPU time 0.89 seconds
Started May 19 02:25:53 PM PDT 24
Finished May 19 02:25:55 PM PDT 24
Peak memory 215012 kb
Host smart-dffccde3-086c-451c-89b9-bbe21b98603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949967464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.949967464
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3915381031
Short name T601
Test name
Test status
Simulation time 828268036 ps
CPU time 4.94 seconds
Started May 19 02:26:02 PM PDT 24
Finished May 19 02:26:08 PM PDT 24
Peak memory 214952 kb
Host smart-dc79fb48-31bc-4419-bebb-a01440283ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915381031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3915381031
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1193740653
Short name T594
Test name
Test status
Simulation time 228385420044 ps
CPU time 2284.12 seconds
Started May 19 02:25:59 PM PDT 24
Finished May 19 03:04:04 PM PDT 24
Peak memory 227424 kb
Host smart-6e4f335d-f815-47b8-9311-07d47ea435ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193740653 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1193740653
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3474328580
Short name T487
Test name
Test status
Simulation time 38955021 ps
CPU time 1.39 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 218604 kb
Host smart-a2a650d2-cc6f-4433-b483-2a5bf4c2c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474328580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3474328580
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.198556722
Short name T447
Test name
Test status
Simulation time 22757717 ps
CPU time 1.19 seconds
Started May 19 02:28:12 PM PDT 24
Finished May 19 02:28:16 PM PDT 24
Peak memory 216588 kb
Host smart-4253279b-dc95-40c6-9f6a-802486a62e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198556722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.198556722
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1522507242
Short name T298
Test name
Test status
Simulation time 91539926 ps
CPU time 1.55 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 218432 kb
Host smart-1dcb5620-6617-4a9e-b7c1-8c443cd822c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522507242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1522507242
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4087113631
Short name T826
Test name
Test status
Simulation time 60433218 ps
CPU time 1.45 seconds
Started May 19 02:28:11 PM PDT 24
Finished May 19 02:28:15 PM PDT 24
Peak memory 218132 kb
Host smart-02e5adee-024d-4eb2-88ac-408101115c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087113631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4087113631
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1978667033
Short name T787
Test name
Test status
Simulation time 22125047 ps
CPU time 1.11 seconds
Started May 19 02:28:14 PM PDT 24
Finished May 19 02:28:17 PM PDT 24
Peak memory 216684 kb
Host smart-aa03e5ab-8ef2-4eb7-9162-61de9ca90ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978667033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1978667033
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1437648131
Short name T700
Test name
Test status
Simulation time 43972845 ps
CPU time 1.13 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 216752 kb
Host smart-ef0e1918-3351-4910-9a5a-a14902eb0ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437648131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1437648131
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2588864166
Short name T417
Test name
Test status
Simulation time 69436634 ps
CPU time 1.45 seconds
Started May 19 02:28:16 PM PDT 24
Finished May 19 02:28:20 PM PDT 24
Peak memory 219408 kb
Host smart-cf725674-efce-4859-8cbb-73e6f700ef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588864166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2588864166
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1915735414
Short name T595
Test name
Test status
Simulation time 98582705 ps
CPU time 1.22 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 219288 kb
Host smart-76a16edd-3605-4e5f-8202-881ef678b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915735414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1915735414
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2878697361
Short name T322
Test name
Test status
Simulation time 45161731 ps
CPU time 0.94 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 216568 kb
Host smart-d06284a3-43ce-4e29-91dc-35dd47795c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878697361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2878697361
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4104320007
Short name T287
Test name
Test status
Simulation time 59367991 ps
CPU time 2.03 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 217996 kb
Host smart-519b1fb2-1db1-496f-b931-dc0617916951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104320007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4104320007
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1858899269
Short name T135
Test name
Test status
Simulation time 78674363 ps
CPU time 1.08 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 215380 kb
Host smart-3e32b43f-94e8-4faf-9dc5-803ae9e6bc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858899269 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1858899269
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4194496176
Short name T558
Test name
Test status
Simulation time 28356099 ps
CPU time 0.97 seconds
Started May 19 02:26:00 PM PDT 24
Finished May 19 02:26:01 PM PDT 24
Peak memory 214544 kb
Host smart-c6f91ad3-22fa-47cd-8762-059968469c2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194496176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4194496176
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.470275022
Short name T317
Test name
Test status
Simulation time 38062755 ps
CPU time 0.88 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 215724 kb
Host smart-b3179154-04ec-4491-8539-38abad787481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470275022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.470275022
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3604474196
Short name T573
Test name
Test status
Simulation time 22317988 ps
CPU time 1.15 seconds
Started May 19 02:25:58 PM PDT 24
Finished May 19 02:26:00 PM PDT 24
Peak memory 216740 kb
Host smart-818b79fa-a2c0-4bca-bb0a-45b46729c630
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604474196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3604474196
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3673393768
Short name T125
Test name
Test status
Simulation time 23999537 ps
CPU time 0.93 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 214900 kb
Host smart-99c76208-c4df-4fe5-8aae-1328e1580b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673393768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3673393768
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1558997041
Short name T45
Test name
Test status
Simulation time 40245804 ps
CPU time 1.4 seconds
Started May 19 02:25:58 PM PDT 24
Finished May 19 02:26:01 PM PDT 24
Peak memory 217912 kb
Host smart-d112dadd-046c-4e0d-9f5e-83ff98a74744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558997041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1558997041
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3644036753
Short name T506
Test name
Test status
Simulation time 38395569 ps
CPU time 0.91 seconds
Started May 19 02:25:58 PM PDT 24
Finished May 19 02:26:00 PM PDT 24
Peak memory 215100 kb
Host smart-e8334c71-7062-4f7f-a5c8-54a76de05ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644036753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3644036753
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3908837316
Short name T650
Test name
Test status
Simulation time 18068234 ps
CPU time 1.13 seconds
Started May 19 02:26:01 PM PDT 24
Finished May 19 02:26:03 PM PDT 24
Peak memory 215012 kb
Host smart-122edd75-79bb-449c-953c-bc47f937cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908837316 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3908837316
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2633115073
Short name T414
Test name
Test status
Simulation time 303430752 ps
CPU time 2.54 seconds
Started May 19 02:26:02 PM PDT 24
Finished May 19 02:26:05 PM PDT 24
Peak memory 216828 kb
Host smart-03335730-27ee-4a4b-8950-b80880c4498d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633115073 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2633115073
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1116545538
Short name T623
Test name
Test status
Simulation time 68705291194 ps
CPU time 879.3 seconds
Started May 19 02:25:58 PM PDT 24
Finished May 19 02:40:38 PM PDT 24
Peak memory 223396 kb
Host smart-1bbb6ca8-6258-4051-af03-6447d4b1db75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116545538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1116545538
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2889802182
Short name T501
Test name
Test status
Simulation time 37971950 ps
CPU time 1.68 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 217804 kb
Host smart-91708522-6514-49b1-8f12-05af3e2cc960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889802182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2889802182
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3829543448
Short name T622
Test name
Test status
Simulation time 94294153 ps
CPU time 1.66 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 218228 kb
Host smart-3e9cdb37-bb86-4931-8021-7631307089d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829543448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3829543448
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2520528540
Short name T792
Test name
Test status
Simulation time 30994220 ps
CPU time 1.33 seconds
Started May 19 02:28:12 PM PDT 24
Finished May 19 02:28:15 PM PDT 24
Peak memory 218824 kb
Host smart-64a41e03-67c4-456c-b874-ffbd30e84c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520528540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2520528540
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.882639848
Short name T480
Test name
Test status
Simulation time 61804499 ps
CPU time 1.09 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 216808 kb
Host smart-8295e8cb-59ae-473f-94b3-8ebf565c4e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882639848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.882639848
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4275669404
Short name T12
Test name
Test status
Simulation time 49594742 ps
CPU time 1.72 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 214996 kb
Host smart-cb5437c9-e3cb-4a7a-9cc3-814a5c78a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275669404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4275669404
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1290367926
Short name T294
Test name
Test status
Simulation time 56261522 ps
CPU time 1.17 seconds
Started May 19 02:28:11 PM PDT 24
Finished May 19 02:28:15 PM PDT 24
Peak memory 219188 kb
Host smart-ea1a2c22-e1bd-4ff0-bbbb-26090b13617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290367926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1290367926
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1264469240
Short name T295
Test name
Test status
Simulation time 31580567 ps
CPU time 1.32 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:17 PM PDT 24
Peak memory 218048 kb
Host smart-cbb7c3a6-6958-403b-9710-b204f36a3d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264469240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1264469240
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3580634135
Short name T523
Test name
Test status
Simulation time 122811257 ps
CPU time 2.47 seconds
Started May 19 02:28:14 PM PDT 24
Finished May 19 02:28:19 PM PDT 24
Peak memory 219564 kb
Host smart-2331f01e-553a-4230-8068-492df19dbc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580634135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3580634135
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3136417604
Short name T587
Test name
Test status
Simulation time 39617958 ps
CPU time 1.21 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:17 PM PDT 24
Peak memory 217776 kb
Host smart-bc55da14-1849-49c4-ab3d-898a2a12d916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136417604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3136417604
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3778062794
Short name T19
Test name
Test status
Simulation time 56466004 ps
CPU time 1.21 seconds
Started May 19 02:28:12 PM PDT 24
Finished May 19 02:28:15 PM PDT 24
Peak memory 216692 kb
Host smart-aef84bc1-9a28-4a7a-bf8c-dfe1b7de6d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778062794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3778062794
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.540818660
Short name T615
Test name
Test status
Simulation time 29192776 ps
CPU time 1.32 seconds
Started May 19 02:26:03 PM PDT 24
Finished May 19 02:26:06 PM PDT 24
Peak memory 215388 kb
Host smart-7d21739a-1da1-4a2f-a5f5-c45837eb0f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540818660 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.540818660
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2383830611
Short name T54
Test name
Test status
Simulation time 20152658 ps
CPU time 1 seconds
Started May 19 02:26:05 PM PDT 24
Finished May 19 02:26:07 PM PDT 24
Peak memory 206312 kb
Host smart-2001c4ab-f0fb-4e82-a08d-4d6daa753e55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383830611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2383830611
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3215361741
Short name T454
Test name
Test status
Simulation time 10715310 ps
CPU time 0.86 seconds
Started May 19 02:26:04 PM PDT 24
Finished May 19 02:26:06 PM PDT 24
Peak memory 215200 kb
Host smart-296cd944-351b-4d72-b43e-b43aea2c344e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215361741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3215361741
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3523482580
Short name T173
Test name
Test status
Simulation time 31425573 ps
CPU time 1.23 seconds
Started May 19 02:26:06 PM PDT 24
Finished May 19 02:26:08 PM PDT 24
Peak memory 219272 kb
Host smart-fd25b6d2-460a-4496-be44-d37f46588069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523482580 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3523482580
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.4292322039
Short name T250
Test name
Test status
Simulation time 39783957 ps
CPU time 1.46 seconds
Started May 19 02:26:06 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 217128 kb
Host smart-e617e8eb-29ed-4dab-a886-73262a8387b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292322039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4292322039
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1310720550
Short name T550
Test name
Test status
Simulation time 23163749 ps
CPU time 1.19 seconds
Started May 19 02:26:07 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 223620 kb
Host smart-3d96f0cf-d047-4efe-9c39-64d249be5aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310720550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1310720550
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.729307105
Short name T790
Test name
Test status
Simulation time 18965936 ps
CPU time 1.07 seconds
Started May 19 02:26:08 PM PDT 24
Finished May 19 02:26:10 PM PDT 24
Peak memory 215028 kb
Host smart-aa4d254f-3e96-43c9-b1d5-6266de076274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729307105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.729307105
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1180965900
Short name T161
Test name
Test status
Simulation time 207048683 ps
CPU time 2.62 seconds
Started May 19 02:26:16 PM PDT 24
Finished May 19 02:26:20 PM PDT 24
Peak memory 216860 kb
Host smart-af18323d-36dc-442d-ae71-75bbd68b653c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180965900 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1180965900
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2108184519
Short name T450
Test name
Test status
Simulation time 85808722005 ps
CPU time 1451.41 seconds
Started May 19 02:26:03 PM PDT 24
Finished May 19 02:50:15 PM PDT 24
Peak memory 223612 kb
Host smart-300d813d-ee78-40fd-b0fd-db3656ba89f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108184519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2108184519
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.615989817
Short name T367
Test name
Test status
Simulation time 62333122 ps
CPU time 1.2 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 218324 kb
Host smart-3cc0c174-5fdf-4ac4-8f8e-3b48fd674325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615989817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.615989817
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3173126289
Short name T716
Test name
Test status
Simulation time 69587267 ps
CPU time 2.44 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 218328 kb
Host smart-103725ea-b441-468f-8cbf-d6f7d84196f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173126289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3173126289
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1676721390
Short name T607
Test name
Test status
Simulation time 78926342 ps
CPU time 1.42 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:21 PM PDT 24
Peak memory 218328 kb
Host smart-964662b8-ecca-481e-b2f8-eacf8d5914fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676721390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1676721390
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3463107699
Short name T309
Test name
Test status
Simulation time 73638817 ps
CPU time 1.08 seconds
Started May 19 02:28:14 PM PDT 24
Finished May 19 02:28:17 PM PDT 24
Peak memory 216744 kb
Host smart-d0d2690e-40d7-478c-9e4f-aa84b16c3208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463107699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3463107699
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2003217798
Short name T418
Test name
Test status
Simulation time 46052220 ps
CPU time 1.74 seconds
Started May 19 02:28:16 PM PDT 24
Finished May 19 02:28:19 PM PDT 24
Peak memory 218280 kb
Host smart-9678cbcd-1dc6-415d-8b1c-cb76951c2f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003217798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2003217798
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1790855964
Short name T729
Test name
Test status
Simulation time 78692206 ps
CPU time 1.49 seconds
Started May 19 02:28:16 PM PDT 24
Finished May 19 02:28:20 PM PDT 24
Peak memory 215020 kb
Host smart-ffb1b0ab-7bf9-44eb-a081-6face042bd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790855964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1790855964
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3085242767
Short name T714
Test name
Test status
Simulation time 94191022 ps
CPU time 1.38 seconds
Started May 19 02:28:16 PM PDT 24
Finished May 19 02:28:19 PM PDT 24
Peak memory 216912 kb
Host smart-92fe867f-6a54-4d2d-bc2c-c72539661263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085242767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3085242767
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3708313794
Short name T764
Test name
Test status
Simulation time 39101987 ps
CPU time 1.24 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 218020 kb
Host smart-96300578-faa3-4ca4-b2c9-b177bbb6cf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708313794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3708313794
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.4219690018
Short name T628
Test name
Test status
Simulation time 102680016 ps
CPU time 2.57 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:18 PM PDT 24
Peak memory 217148 kb
Host smart-70ea1520-1ef4-455e-9f4b-e76e9bedb7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219690018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.4219690018
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1258753027
Short name T586
Test name
Test status
Simulation time 85979995 ps
CPU time 1.14 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:16 PM PDT 24
Peak memory 216836 kb
Host smart-4e7d5b76-5d5d-4014-8edb-42f17a429a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258753027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1258753027
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1490158268
Short name T165
Test name
Test status
Simulation time 67374866 ps
CPU time 1.29 seconds
Started May 19 02:26:08 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 215408 kb
Host smart-9cdcadb1-5cc8-4359-b8bb-2af6af7d728c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490158268 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1490158268
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2918562365
Short name T641
Test name
Test status
Simulation time 28091152 ps
CPU time 0.9 seconds
Started May 19 02:26:04 PM PDT 24
Finished May 19 02:26:05 PM PDT 24
Peak memory 206328 kb
Host smart-340f0e25-cc8d-43ac-9a53-e2779e0050bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918562365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2918562365
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4271024613
Short name T725
Test name
Test status
Simulation time 82780020 ps
CPU time 1.06 seconds
Started May 19 02:26:07 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 216580 kb
Host smart-03b899a2-dbf9-491e-afc4-ab19168a7fe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271024613 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4271024613
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3615093443
Short name T36
Test name
Test status
Simulation time 23954470 ps
CPU time 1.02 seconds
Started May 19 02:26:07 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 218052 kb
Host smart-23130130-294e-482c-9d20-044b077018f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615093443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3615093443
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.970544517
Short name T371
Test name
Test status
Simulation time 71968896 ps
CPU time 1.88 seconds
Started May 19 02:26:05 PM PDT 24
Finished May 19 02:26:08 PM PDT 24
Peak memory 217020 kb
Host smart-435cd656-e234-4ff8-ab12-34e67ae1bca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970544517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.970544517
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3003294157
Short name T170
Test name
Test status
Simulation time 29320931 ps
CPU time 0.97 seconds
Started May 19 02:26:03 PM PDT 24
Finished May 19 02:26:05 PM PDT 24
Peak memory 215420 kb
Host smart-a6694aeb-24ea-4f6d-a4d5-ad146b291207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003294157 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3003294157
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1244116245
Short name T22
Test name
Test status
Simulation time 27217150 ps
CPU time 0.96 seconds
Started May 19 02:26:03 PM PDT 24
Finished May 19 02:26:05 PM PDT 24
Peak memory 215012 kb
Host smart-765a33a6-c782-4cb0-a902-d9e50edc8bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244116245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1244116245
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4005716158
Short name T333
Test name
Test status
Simulation time 547592383 ps
CPU time 5.34 seconds
Started May 19 02:26:04 PM PDT 24
Finished May 19 02:26:10 PM PDT 24
Peak memory 216896 kb
Host smart-8278fc4b-4f64-4db8-bcf5-4352b92dddf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005716158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4005716158
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3461651878
Short name T602
Test name
Test status
Simulation time 87384717961 ps
CPU time 536.46 seconds
Started May 19 02:26:07 PM PDT 24
Finished May 19 02:35:05 PM PDT 24
Peak memory 218616 kb
Host smart-133a1238-426a-409d-a26d-84f9af4858da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461651878 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3461651878
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.110357191
Short name T757
Test name
Test status
Simulation time 147061886 ps
CPU time 1.36 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 218284 kb
Host smart-fa982145-4712-4dc4-b664-29f4b9d9ef5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110357191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.110357191
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1619050733
Short name T448
Test name
Test status
Simulation time 51056930 ps
CPU time 1.21 seconds
Started May 19 02:28:14 PM PDT 24
Finished May 19 02:28:18 PM PDT 24
Peak memory 219304 kb
Host smart-b826f6c0-ced7-4de5-851b-e5bc32242f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619050733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1619050733
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1341369120
Short name T547
Test name
Test status
Simulation time 69013073 ps
CPU time 2.49 seconds
Started May 19 02:28:13 PM PDT 24
Finished May 19 02:28:18 PM PDT 24
Peak memory 217000 kb
Host smart-4b0d89b6-d1c3-4c46-b8bf-510aebdf39e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341369120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1341369120
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3807880564
Short name T682
Test name
Test status
Simulation time 42320617 ps
CPU time 1.39 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 216624 kb
Host smart-be511f4c-daef-4df1-82a7-521dff950c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807880564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3807880564
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3663882643
Short name T331
Test name
Test status
Simulation time 106765594 ps
CPU time 1.04 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 216736 kb
Host smart-56f9d1be-8612-4225-840d-806129fa56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663882643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3663882643
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3635469168
Short name T385
Test name
Test status
Simulation time 74169405 ps
CPU time 1.56 seconds
Started May 19 02:28:24 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 216748 kb
Host smart-01273f52-b2e7-4d8e-a574-e9ed346bdc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635469168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3635469168
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1635358303
Short name T351
Test name
Test status
Simulation time 86874335 ps
CPU time 1.43 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 218436 kb
Host smart-8497d9b3-ca12-4320-b4d1-95505db8ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635358303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1635358303
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.521702149
Short name T437
Test name
Test status
Simulation time 131275610 ps
CPU time 1.65 seconds
Started May 19 02:28:24 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 218452 kb
Host smart-0516ec49-a03b-499e-be2a-cc555bc0353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521702149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.521702149
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1226890160
Short name T166
Test name
Test status
Simulation time 30200141 ps
CPU time 1.29 seconds
Started May 19 02:26:11 PM PDT 24
Finished May 19 02:26:14 PM PDT 24
Peak memory 215580 kb
Host smart-894e081b-cebc-46b1-9345-d8d66c48bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226890160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1226890160
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2592150944
Short name T805
Test name
Test status
Simulation time 20007711 ps
CPU time 1.03 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 214504 kb
Host smart-0cb7995d-29a4-476c-955d-b002f554b507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592150944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2592150944
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2834823836
Short name T722
Test name
Test status
Simulation time 68549394 ps
CPU time 1.05 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 216544 kb
Host smart-b252087a-0aaa-4c6e-bf44-93f6e219bf82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834823836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2834823836
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_intr.1201458696
Short name T160
Test name
Test status
Simulation time 23300208 ps
CPU time 0.91 seconds
Started May 19 02:26:04 PM PDT 24
Finished May 19 02:26:06 PM PDT 24
Peak memory 215472 kb
Host smart-60774b70-ca7c-420c-ba98-6158be5b385b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201458696 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1201458696
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2900594780
Short name T352
Test name
Test status
Simulation time 71868593 ps
CPU time 0.79 seconds
Started May 19 02:26:04 PM PDT 24
Finished May 19 02:26:06 PM PDT 24
Peak memory 214892 kb
Host smart-cdd83638-ff39-4ff2-b47a-aa0022201c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900594780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2900594780
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.216755790
Short name T535
Test name
Test status
Simulation time 320824499 ps
CPU time 3.27 seconds
Started May 19 02:26:05 PM PDT 24
Finished May 19 02:26:09 PM PDT 24
Peak memory 215004 kb
Host smart-736f0c2b-213a-49eb-b420-7d3eb7aaf992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216755790 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.216755790
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.609036675
Short name T393
Test name
Test status
Simulation time 13599055053 ps
CPU time 354.12 seconds
Started May 19 02:26:08 PM PDT 24
Finished May 19 02:32:03 PM PDT 24
Peak memory 223104 kb
Host smart-9ed3a923-6a4e-4524-8340-4785552c53df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609036675 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.609036675
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1568715912
Short name T43
Test name
Test status
Simulation time 66803650 ps
CPU time 1.32 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 217848 kb
Host smart-205c8572-0db3-4d44-9775-5450e052b4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568715912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1568715912
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.611561212
Short name T285
Test name
Test status
Simulation time 21732315 ps
CPU time 1.16 seconds
Started May 19 02:28:19 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 216664 kb
Host smart-9eaff745-783a-491d-a28b-1f506bc45a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611561212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.611561212
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.321088167
Short name T755
Test name
Test status
Simulation time 49247401 ps
CPU time 1.15 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 216796 kb
Host smart-76d2e49f-243f-4113-9ed5-c6b7d1cf5f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321088167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.321088167
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1257366972
Short name T776
Test name
Test status
Simulation time 246707816 ps
CPU time 2.67 seconds
Started May 19 02:28:19 PM PDT 24
Finished May 19 02:28:25 PM PDT 24
Peak memory 216900 kb
Host smart-b1812a93-dea3-4257-8d76-450b32dd0baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257366972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1257366972
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2142651577
Short name T156
Test name
Test status
Simulation time 27504082 ps
CPU time 1.26 seconds
Started May 19 02:28:17 PM PDT 24
Finished May 19 02:28:22 PM PDT 24
Peak memory 219200 kb
Host smart-01c4ce6c-cf51-4d50-9a46-66e649206f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142651577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2142651577
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.94698592
Short name T672
Test name
Test status
Simulation time 33598638 ps
CPU time 1.32 seconds
Started May 19 02:28:23 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 216876 kb
Host smart-6f3d41c5-df5e-4f67-915b-f95bf46f65bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94698592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.94698592
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.168224925
Short name T303
Test name
Test status
Simulation time 94340732 ps
CPU time 1.51 seconds
Started May 19 02:28:19 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 218420 kb
Host smart-03266fa8-395f-4769-bdac-c5014814f474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168224925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.168224925
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1928423514
Short name T357
Test name
Test status
Simulation time 36406288 ps
CPU time 1.07 seconds
Started May 19 02:28:24 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 216748 kb
Host smart-ecdce69e-dc43-44da-a9ce-b4d682b508f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928423514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1928423514
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4068166528
Short name T795
Test name
Test status
Simulation time 183971385 ps
CPU time 2.7 seconds
Started May 19 02:28:24 PM PDT 24
Finished May 19 02:28:28 PM PDT 24
Peak memory 216996 kb
Host smart-890099e4-89d5-475c-a941-1f019b100303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068166528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4068166528
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2207372608
Short name T691
Test name
Test status
Simulation time 99873047 ps
CPU time 1.23 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 218324 kb
Host smart-1f35dd72-8f8a-4501-ab7c-d178cccbbbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207372608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2207372608
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3505154597
Short name T452
Test name
Test status
Simulation time 76278831 ps
CPU time 1.08 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 215380 kb
Host smart-f17f4bad-1faa-4bb7-808a-597cfa5098f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505154597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3505154597
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3377643440
Short name T600
Test name
Test status
Simulation time 31873063 ps
CPU time 0.84 seconds
Started May 19 02:26:11 PM PDT 24
Finished May 19 02:26:13 PM PDT 24
Peak memory 206580 kb
Host smart-42968739-5238-4d8d-a60d-d98e26b13fde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377643440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3377643440
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.395832438
Short name T190
Test name
Test status
Simulation time 13119898 ps
CPU time 0.93 seconds
Started May 19 02:26:08 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 215380 kb
Host smart-b783aa73-b198-44c2-8b4c-e942b0bc2b32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395832438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.395832438
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2449349511
Short name T804
Test name
Test status
Simulation time 42219030 ps
CPU time 1.37 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:13 PM PDT 24
Peak memory 216604 kb
Host smart-961b2ba0-9ad3-4be0-b978-5067d5835dd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449349511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2449349511
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2519744897
Short name T747
Test name
Test status
Simulation time 21065856 ps
CPU time 0.93 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 218292 kb
Host smart-5727a63f-5512-462b-9d29-899698bba57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519744897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2519744897
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3463225053
Short name T410
Test name
Test status
Simulation time 171806801 ps
CPU time 1.7 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 218136 kb
Host smart-4f03688b-9ccc-4a04-af21-3a4c90cb2378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463225053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3463225053
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.4097274723
Short name T33
Test name
Test status
Simulation time 21467279 ps
CPU time 1.1 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:13 PM PDT 24
Peak memory 215492 kb
Host smart-dfbe66e2-2295-4813-a27c-54e89e6c7ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097274723 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4097274723
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4182509632
Short name T562
Test name
Test status
Simulation time 31708483 ps
CPU time 0.96 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:16 PM PDT 24
Peak memory 215016 kb
Host smart-38cb5c65-ba48-4f6f-8a3b-ed945ef81e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182509632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4182509632
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.661259403
Short name T681
Test name
Test status
Simulation time 259618518 ps
CPU time 5.52 seconds
Started May 19 02:26:11 PM PDT 24
Finished May 19 02:26:18 PM PDT 24
Peak memory 215108 kb
Host smart-c08e6d46-4d91-4565-8728-c23e8761fc67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661259403 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.661259403
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1502842318
Short name T205
Test name
Test status
Simulation time 239226371726 ps
CPU time 1450.76 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:50:23 PM PDT 24
Peak memory 223368 kb
Host smart-b9c294f0-6f31-4a0f-b39e-72c2fc0acdab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502842318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1502842318
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2630163991
Short name T335
Test name
Test status
Simulation time 58835480 ps
CPU time 0.98 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 215024 kb
Host smart-e49eb037-e4bd-4806-9c1f-ec1280f424f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630163991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2630163991
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.930418805
Short name T391
Test name
Test status
Simulation time 65183938 ps
CPU time 1.04 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 216804 kb
Host smart-8a9597df-0491-46e8-b12f-ff66cc75799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930418805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.930418805
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.22479810
Short name T731
Test name
Test status
Simulation time 107655575 ps
CPU time 1.31 seconds
Started May 19 02:28:19 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 218012 kb
Host smart-29629437-b356-4d96-b8bf-bf8f519cc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22479810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.22479810
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.641798296
Short name T530
Test name
Test status
Simulation time 52732886 ps
CPU time 1.89 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:24 PM PDT 24
Peak memory 217068 kb
Host smart-4d776d1d-4449-4e95-95fe-feb98ed50cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641798296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.641798296
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1784065760
Short name T86
Test name
Test status
Simulation time 44360365 ps
CPU time 1.49 seconds
Started May 19 02:28:18 PM PDT 24
Finished May 19 02:28:23 PM PDT 24
Peak memory 218056 kb
Host smart-88c1c356-6ec5-4a06-9043-dd379592c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784065760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1784065760
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.985551947
Short name T50
Test name
Test status
Simulation time 95491125 ps
CPU time 1.54 seconds
Started May 19 02:28:23 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 218224 kb
Host smart-13e14300-dfe8-4167-a6be-c41af1fa771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985551947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.985551947
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2876700774
Short name T824
Test name
Test status
Simulation time 61222380 ps
CPU time 1.53 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 219620 kb
Host smart-158b31ab-0eac-424d-8fc8-b2de4630b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876700774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2876700774
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2877440708
Short name T211
Test name
Test status
Simulation time 1137477311 ps
CPU time 6.04 seconds
Started May 19 02:28:23 PM PDT 24
Finished May 19 02:28:32 PM PDT 24
Peak memory 217956 kb
Host smart-9ce14453-aa24-4360-9174-94337710eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877440708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2877440708
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2032503607
Short name T52
Test name
Test status
Simulation time 334084156 ps
CPU time 2.15 seconds
Started May 19 02:28:23 PM PDT 24
Finished May 19 02:28:28 PM PDT 24
Peak memory 218456 kb
Host smart-ec1c8f5f-0714-4a0e-a3b2-9138e6f3bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032503607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2032503607
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1885805996
Short name T634
Test name
Test status
Simulation time 49336681 ps
CPU time 1.42 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 217848 kb
Host smart-618b8c04-c764-4ed6-9530-c648c1ec24bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885805996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1885805996
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1750398503
Short name T277
Test name
Test status
Simulation time 49937724 ps
CPU time 1.15 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 215452 kb
Host smart-fb08a229-267c-4c86-a869-7320bebe5cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750398503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1750398503
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2554766868
Short name T77
Test name
Test status
Simulation time 121938782 ps
CPU time 0.81 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 206556 kb
Host smart-9e31fd16-8c07-484b-aa7d-f63abdd03f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554766868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2554766868
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3073948530
Short name T797
Test name
Test status
Simulation time 40037798 ps
CPU time 1.13 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:15 PM PDT 24
Peak memory 216580 kb
Host smart-4b04d6c6-7501-4a15-bdf3-37c0ade9d144
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073948530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3073948530
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2900209736
Short name T800
Test name
Test status
Simulation time 82572784 ps
CPU time 1.13 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 223644 kb
Host smart-58f67151-ca71-43f6-9c27-af4837602277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900209736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2900209736
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2042878222
Short name T778
Test name
Test status
Simulation time 78515821 ps
CPU time 1.49 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 218160 kb
Host smart-f5027b73-e9cd-4310-9c1f-08023d4dbb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042878222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2042878222
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3539579926
Short name T31
Test name
Test status
Simulation time 24488803 ps
CPU time 0.95 seconds
Started May 19 02:26:10 PM PDT 24
Finished May 19 02:26:13 PM PDT 24
Peak memory 215404 kb
Host smart-ac1bf41b-b3ed-41be-9cd0-226dca2fe7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539579926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3539579926
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3154081226
Short name T359
Test name
Test status
Simulation time 43136873 ps
CPU time 0.95 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:11 PM PDT 24
Peak memory 215020 kb
Host smart-f76cfe39-2894-4496-8869-43c46cb71cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154081226 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3154081226
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1126565843
Short name T347
Test name
Test status
Simulation time 3493459658 ps
CPU time 6.09 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:22 PM PDT 24
Peak memory 217056 kb
Host smart-d1a13500-d862-438f-b43b-dec1a8fe03cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126565843 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1126565843
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2349247069
Short name T561
Test name
Test status
Simulation time 211094526081 ps
CPU time 2510.72 seconds
Started May 19 02:26:12 PM PDT 24
Finished May 19 03:08:05 PM PDT 24
Peak memory 231284 kb
Host smart-a6b8a315-573d-42e7-ad08-5b7de5d49315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349247069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2349247069
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.116812358
Short name T412
Test name
Test status
Simulation time 65860918 ps
CPU time 1.4 seconds
Started May 19 02:28:21 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 217904 kb
Host smart-1fb5038d-2878-4693-81b2-83d687595578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116812358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.116812358
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4020300787
Short name T326
Test name
Test status
Simulation time 275541927 ps
CPU time 4.3 seconds
Started May 19 02:28:24 PM PDT 24
Finished May 19 02:28:30 PM PDT 24
Peak memory 219788 kb
Host smart-77eab71f-5b98-460c-b2aa-feead5912438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020300787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4020300787
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1017639556
Short name T737
Test name
Test status
Simulation time 48008774 ps
CPU time 1.88 seconds
Started May 19 02:28:21 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 217820 kb
Host smart-eb4c925b-807c-405b-8d76-cceb8ee15011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017639556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1017639556
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3365387538
Short name T559
Test name
Test status
Simulation time 73168403 ps
CPU time 1.48 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 218112 kb
Host smart-3aee7cf6-b28b-45f4-85fa-a40c8fae6d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365387538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3365387538
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.988243014
Short name T251
Test name
Test status
Simulation time 30529670 ps
CPU time 1.36 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 216968 kb
Host smart-924ab88f-422b-4395-9402-32c00236b20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988243014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.988243014
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1220180505
Short name T85
Test name
Test status
Simulation time 192465847 ps
CPU time 1.46 seconds
Started May 19 02:28:22 PM PDT 24
Finished May 19 02:28:27 PM PDT 24
Peak memory 218196 kb
Host smart-e2335f0d-c98e-414c-8b16-598ae917f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220180505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1220180505
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3307234698
Short name T87
Test name
Test status
Simulation time 28707623 ps
CPU time 1.3 seconds
Started May 19 02:28:21 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 218280 kb
Host smart-7eb30580-f7b3-4eec-9d56-0653457083af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307234698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3307234698
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2989516476
Short name T356
Test name
Test status
Simulation time 736924077 ps
CPU time 5.46 seconds
Started May 19 02:28:23 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 219928 kb
Host smart-59d985a6-a2d9-4c87-9f2b-bfbf7caf5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989516476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2989516476
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.209522861
Short name T644
Test name
Test status
Simulation time 80806544 ps
CPU time 1.16 seconds
Started May 19 02:28:21 PM PDT 24
Finished May 19 02:28:26 PM PDT 24
Peak memory 219240 kb
Host smart-7694dac5-a642-4ee6-869b-2d1fdf54a123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209522861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.209522861
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2525151003
Short name T546
Test name
Test status
Simulation time 25959165 ps
CPU time 1 seconds
Started May 19 02:28:29 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 216820 kb
Host smart-a36d702e-2b30-4acb-9abd-115e2e0e7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525151003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2525151003
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.525923769
Short name T746
Test name
Test status
Simulation time 25141838 ps
CPU time 1.19 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 215408 kb
Host smart-d3b50ba1-180c-42bf-89a6-221666662127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525923769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.525923769
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.758359745
Short name T639
Test name
Test status
Simulation time 34969283 ps
CPU time 0.81 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:15 PM PDT 24
Peak memory 206592 kb
Host smart-57c720a6-b9e4-40c9-a623-1290d37a7557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758359745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.758359745
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.660055184
Short name T626
Test name
Test status
Simulation time 35949539 ps
CPU time 0.89 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:16 PM PDT 24
Peak memory 215992 kb
Host smart-a4c261a1-df08-4194-bb49-b084a5bb0787
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660055184 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.660055184
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1771731009
Short name T51
Test name
Test status
Simulation time 39927587 ps
CPU time 1.25 seconds
Started May 19 02:26:15 PM PDT 24
Finished May 19 02:26:18 PM PDT 24
Peak memory 217936 kb
Host smart-1ea75c26-b40f-485d-a13f-6282d7e8a8bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771731009 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1771731009
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1677451450
Short name T684
Test name
Test status
Simulation time 25296262 ps
CPU time 1.33 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 223532 kb
Host smart-1a4a0b95-6c17-4f4e-9b74-c48c719c8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677451450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1677451450
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1184629232
Short name T590
Test name
Test status
Simulation time 84794468 ps
CPU time 1.25 seconds
Started May 19 02:26:09 PM PDT 24
Finished May 19 02:26:12 PM PDT 24
Peak memory 219488 kb
Host smart-7e2499f3-c239-4c8b-a017-37b3ae7517d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184629232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1184629232
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1511119483
Short name T30
Test name
Test status
Simulation time 24402804 ps
CPU time 0.9 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 215388 kb
Host smart-30037fc1-07a3-4194-9906-4ccd11578566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511119483 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1511119483
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1580121384
Short name T339
Test name
Test status
Simulation time 21962260 ps
CPU time 0.95 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:15 PM PDT 24
Peak memory 215008 kb
Host smart-baaa5dc0-c469-4b7b-89cd-403de1994121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580121384 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1580121384
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3710150817
Short name T621
Test name
Test status
Simulation time 310832928 ps
CPU time 6.02 seconds
Started May 19 02:26:16 PM PDT 24
Finished May 19 02:26:23 PM PDT 24
Peak memory 215036 kb
Host smart-7341df01-7e01-4031-8a66-9b9a08c26c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710150817 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3710150817
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2651015591
Short name T584
Test name
Test status
Simulation time 368287756670 ps
CPU time 955.4 seconds
Started May 19 02:26:15 PM PDT 24
Finished May 19 02:42:12 PM PDT 24
Peak memory 221700 kb
Host smart-a39437cc-90a7-4c73-89b1-8fd33e34dc1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651015591 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2651015591
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3472289590
Short name T92
Test name
Test status
Simulation time 36796419 ps
CPU time 1.56 seconds
Started May 19 02:28:26 PM PDT 24
Finished May 19 02:28:29 PM PDT 24
Peak memory 217948 kb
Host smart-0db8ff9d-bcc3-4a38-8404-e9f470e1e046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472289590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3472289590
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1580390859
Short name T668
Test name
Test status
Simulation time 37155670 ps
CPU time 1.12 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:42 PM PDT 24
Peak memory 216772 kb
Host smart-07527f35-4873-4af9-8228-60b79fbf577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580390859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1580390859
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1087719068
Short name T751
Test name
Test status
Simulation time 85354023 ps
CPU time 1.13 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:41 PM PDT 24
Peak memory 216704 kb
Host smart-55fb17a4-d452-403b-8cea-9e8aa64a62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087719068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1087719068
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3654690434
Short name T392
Test name
Test status
Simulation time 60991931 ps
CPU time 2.16 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 217912 kb
Host smart-0dcdf363-f4bd-4abf-822d-18d8fee77d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654690434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3654690434
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.774007719
Short name T509
Test name
Test status
Simulation time 68686765 ps
CPU time 1.65 seconds
Started May 19 02:28:30 PM PDT 24
Finished May 19 02:28:32 PM PDT 24
Peak memory 219440 kb
Host smart-00020d2d-56cb-4170-941f-adea0d6d7755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774007719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.774007719
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3269224408
Short name T8
Test name
Test status
Simulation time 44425883 ps
CPU time 1.56 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:42 PM PDT 24
Peak memory 218716 kb
Host smart-63fbef37-33b1-4159-b44b-cfb780491c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269224408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3269224408
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3865912811
Short name T693
Test name
Test status
Simulation time 25245653 ps
CPU time 1.4 seconds
Started May 19 02:28:31 PM PDT 24
Finished May 19 02:28:33 PM PDT 24
Peak memory 215052 kb
Host smart-e2ec56bb-d13a-4114-a253-8e5707656423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865912811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3865912811
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1189627548
Short name T89
Test name
Test status
Simulation time 132984859 ps
CPU time 1.49 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:30 PM PDT 24
Peak memory 219420 kb
Host smart-1aec522d-96c5-47bd-ae5f-49eb0f004dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189627548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1189627548
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.986370877
Short name T15
Test name
Test status
Simulation time 33618642 ps
CPU time 1.2 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 215400 kb
Host smart-f68050e7-70d9-4dc1-8803-eb756230f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986370877 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.986370877
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3763813964
Short name T332
Test name
Test status
Simulation time 52995887 ps
CPU time 0.93 seconds
Started May 19 02:26:15 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 214556 kb
Host smart-be92e802-e571-441d-b3ce-93d6120cde3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763813964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3763813964
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2963966899
Short name T706
Test name
Test status
Simulation time 52877998 ps
CPU time 1.57 seconds
Started May 19 02:26:17 PM PDT 24
Finished May 19 02:26:20 PM PDT 24
Peak memory 216800 kb
Host smart-ef51a1ce-5627-4704-8c7f-200c4810def6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963966899 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2963966899
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3626599527
Short name T67
Test name
Test status
Simulation time 23452106 ps
CPU time 1.01 seconds
Started May 19 02:26:15 PM PDT 24
Finished May 19 02:26:18 PM PDT 24
Peak memory 219276 kb
Host smart-dcb4abbf-3daf-48f6-ae9d-9fc8d788df2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626599527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3626599527
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.526239751
Short name T659
Test name
Test status
Simulation time 75116202 ps
CPU time 1.19 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:15 PM PDT 24
Peak memory 219608 kb
Host smart-61d1d6dc-1643-4e3a-b885-97d11f00fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526239751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.526239751
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4068563477
Short name T749
Test name
Test status
Simulation time 20231325 ps
CPU time 1.14 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 215452 kb
Host smart-569e558e-17be-4f5c-812f-69ff5f4ef610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068563477 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4068563477
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1950948662
Short name T340
Test name
Test status
Simulation time 18536500 ps
CPU time 1.04 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:26:17 PM PDT 24
Peak memory 215064 kb
Host smart-7d1ed584-d11e-492a-b59f-5b4bc88cd0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950948662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1950948662
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1541546096
Short name T822
Test name
Test status
Simulation time 367033572 ps
CPU time 6.74 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:21 PM PDT 24
Peak memory 218072 kb
Host smart-dbb1bf77-cd56-457c-8986-600560da1646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541546096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1541546096
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1717565899
Short name T204
Test name
Test status
Simulation time 81722529689 ps
CPU time 1880.12 seconds
Started May 19 02:26:14 PM PDT 24
Finished May 19 02:57:35 PM PDT 24
Peak memory 224800 kb
Host smart-752e0220-b988-4de5-a1c4-1fba6d59c254
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717565899 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1717565899
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2998630077
Short name T348
Test name
Test status
Simulation time 58981739 ps
CPU time 2.02 seconds
Started May 19 02:28:32 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 215108 kb
Host smart-d373c3f4-83da-4f08-89d2-40cff3cae17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998630077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2998630077
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.716096650
Short name T440
Test name
Test status
Simulation time 56063585 ps
CPU time 1.78 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 217884 kb
Host smart-f177990b-2ae6-4b3d-98fc-5c87727b5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716096650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.716096650
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2049270060
Short name T428
Test name
Test status
Simulation time 55920130 ps
CPU time 1.38 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:31 PM PDT 24
Peak memory 216712 kb
Host smart-f0db8365-92d7-4667-81bc-da80112b7dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049270060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2049270060
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3945314010
Short name T449
Test name
Test status
Simulation time 31857889 ps
CPU time 1.2 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:41 PM PDT 24
Peak memory 216704 kb
Host smart-02028240-ff8f-49df-88d3-d78978d77967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945314010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3945314010
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2896603922
Short name T633
Test name
Test status
Simulation time 50807702 ps
CPU time 1.58 seconds
Started May 19 02:28:28 PM PDT 24
Finished May 19 02:28:30 PM PDT 24
Peak memory 217748 kb
Host smart-1b82c2ef-b9d3-44e5-9611-b6da7b8287ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896603922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2896603922
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.638102087
Short name T498
Test name
Test status
Simulation time 731667587 ps
CPU time 5.76 seconds
Started May 19 02:28:31 PM PDT 24
Finished May 19 02:28:37 PM PDT 24
Peak memory 216848 kb
Host smart-a17cd1cf-1443-440f-a3af-fb4b92921ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638102087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.638102087
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1049131954
Short name T388
Test name
Test status
Simulation time 56984583 ps
CPU time 1.3 seconds
Started May 19 02:28:27 PM PDT 24
Finished May 19 02:28:29 PM PDT 24
Peak memory 216788 kb
Host smart-c1077aee-6454-4959-8f90-8578dcdd6365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049131954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1049131954
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.4147383577
Short name T811
Test name
Test status
Simulation time 36761033 ps
CPU time 1.09 seconds
Started May 19 02:28:27 PM PDT 24
Finished May 19 02:28:29 PM PDT 24
Peak memory 216908 kb
Host smart-5f16a583-9dd7-47cb-8753-447324c80ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147383577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.4147383577
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3762341476
Short name T683
Test name
Test status
Simulation time 103544711 ps
CPU time 1.47 seconds
Started May 19 02:28:32 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 218040 kb
Host smart-bbb19e1e-bf7a-42f4-96af-6a4d6f7891b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762341476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3762341476
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.421453543
Short name T741
Test name
Test status
Simulation time 41804935 ps
CPU time 1.36 seconds
Started May 19 02:28:32 PM PDT 24
Finished May 19 02:28:33 PM PDT 24
Peak memory 218104 kb
Host smart-3eb00c02-2a3a-4c94-9996-6a1723f612d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421453543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.421453543
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2396546981
Short name T164
Test name
Test status
Simulation time 27844541 ps
CPU time 1.27 seconds
Started May 19 02:26:13 PM PDT 24
Finished May 19 02:26:16 PM PDT 24
Peak memory 215420 kb
Host smart-7169f4ed-5e6a-4f9a-b3e5-5568d3f61584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396546981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2396546981
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1334309451
Short name T632
Test name
Test status
Simulation time 64116262 ps
CPU time 0.89 seconds
Started May 19 02:26:20 PM PDT 24
Finished May 19 02:26:22 PM PDT 24
Peak memory 214368 kb
Host smart-2db76db3-bdec-40b6-9f16-779c085b277e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334309451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1334309451
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2449178877
Short name T94
Test name
Test status
Simulation time 92962860 ps
CPU time 0.85 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:21 PM PDT 24
Peak memory 215612 kb
Host smart-4f6a0c23-cfca-4318-a132-c8c28b2a83b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449178877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2449178877
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1366892944
Short name T551
Test name
Test status
Simulation time 136704213 ps
CPU time 1.02 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:21 PM PDT 24
Peak memory 216720 kb
Host smart-826e5a0c-f869-4827-8320-bde399fa2f2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366892944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1366892944
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1694523389
Short name T128
Test name
Test status
Simulation time 23050874 ps
CPU time 1.04 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:21 PM PDT 24
Peak memory 223456 kb
Host smart-54c46cd3-da7a-4eb8-a468-b3b96a6e0999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694523389 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1694523389
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2035285199
Short name T783
Test name
Test status
Simulation time 77354383 ps
CPU time 1.94 seconds
Started May 19 02:26:16 PM PDT 24
Finished May 19 02:26:19 PM PDT 24
Peak memory 218036 kb
Host smart-81c1421b-cbd1-40e7-bd5a-50e0d8797544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035285199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2035285199
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.1436664049
Short name T439
Test name
Test status
Simulation time 50270621 ps
CPU time 1.03 seconds
Started May 19 02:26:17 PM PDT 24
Finished May 19 02:26:19 PM PDT 24
Peak memory 215268 kb
Host smart-4b5cbc64-779b-4994-9eb3-e242dbe134df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436664049 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1436664049
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2680065502
Short name T465
Test name
Test status
Simulation time 213732369 ps
CPU time 2.13 seconds
Started May 19 02:26:15 PM PDT 24
Finished May 19 02:26:19 PM PDT 24
Peak memory 216660 kb
Host smart-f9eeb1d1-9be9-44f7-9d5b-0e5d920648a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680065502 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2680065502
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3574415091
Short name T485
Test name
Test status
Simulation time 268762210750 ps
CPU time 1207.63 seconds
Started May 19 02:26:12 PM PDT 24
Finished May 19 02:46:21 PM PDT 24
Peak memory 224312 kb
Host smart-4f0afa84-e6f4-4faa-8674-007fa8bf4daa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574415091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3574415091
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3066246735
Short name T390
Test name
Test status
Simulation time 23909685 ps
CPU time 1.12 seconds
Started May 19 02:28:35 PM PDT 24
Finished May 19 02:28:37 PM PDT 24
Peak memory 216684 kb
Host smart-c6d9df0b-0bc1-4d3c-86a8-860bdbd62c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066246735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3066246735
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3758634563
Short name T83
Test name
Test status
Simulation time 119559992 ps
CPU time 1.21 seconds
Started May 19 02:28:37 PM PDT 24
Finished May 19 02:28:38 PM PDT 24
Peak memory 216852 kb
Host smart-253e7bb3-8dab-4e2e-b6d1-77171258228d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758634563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3758634563
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4034179640
Short name T500
Test name
Test status
Simulation time 41635028 ps
CPU time 1.12 seconds
Started May 19 02:28:32 PM PDT 24
Finished May 19 02:28:34 PM PDT 24
Peak memory 216720 kb
Host smart-482662c0-f343-49cc-8357-754b9df35af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034179640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4034179640
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2577064751
Short name T583
Test name
Test status
Simulation time 64998631 ps
CPU time 1.12 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 216924 kb
Host smart-3f6ce6db-a10b-45fb-9b6d-35fe6fcfcefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577064751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2577064751
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.4286349751
Short name T825
Test name
Test status
Simulation time 76304640 ps
CPU time 2.95 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:28:36 PM PDT 24
Peak memory 217060 kb
Host smart-0ab6a1aa-a0df-4c0a-b256-8c4754745fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286349751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.4286349751
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3600372025
Short name T735
Test name
Test status
Simulation time 78739976 ps
CPU time 1.05 seconds
Started May 19 02:28:39 PM PDT 24
Finished May 19 02:28:42 PM PDT 24
Peak memory 216628 kb
Host smart-aa2a0093-8df1-4753-8b1e-620c45626d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600372025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3600372025
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3463882210
Short name T670
Test name
Test status
Simulation time 39070064 ps
CPU time 1.32 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 217776 kb
Host smart-1af4f502-0c64-49c0-aa8e-0e51fa2d254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463882210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3463882210
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.274060521
Short name T679
Test name
Test status
Simulation time 53176493 ps
CPU time 1.28 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 216780 kb
Host smart-8844af1c-062a-4735-b23f-b6c02677862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274060521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.274060521
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2453064119
Short name T292
Test name
Test status
Simulation time 75632074 ps
CPU time 1.43 seconds
Started May 19 02:28:33 PM PDT 24
Finished May 19 02:28:35 PM PDT 24
Peak memory 218204 kb
Host smart-273fa550-85ab-4739-9b85-1f1f6fec6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453064119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2453064119
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1790512026
Short name T577
Test name
Test status
Simulation time 47834061 ps
CPU time 1.09 seconds
Started May 19 02:28:37 PM PDT 24
Finished May 19 02:28:38 PM PDT 24
Peak memory 217820 kb
Host smart-3586d4bb-15b8-440d-9a73-00d191042e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790512026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1790512026
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.753874669
Short name T272
Test name
Test status
Simulation time 82034890 ps
CPU time 1.24 seconds
Started May 19 02:25:00 PM PDT 24
Finished May 19 02:25:02 PM PDT 24
Peak memory 215420 kb
Host smart-f958d306-3caf-4f56-8044-5884c5d1bc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753874669 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.753874669
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.38866053
Short name T426
Test name
Test status
Simulation time 16110330 ps
CPU time 0.95 seconds
Started May 19 02:25:02 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 206280 kb
Host smart-81ae004e-6416-4193-adf0-37f873f53ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38866053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.38866053
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3217182714
Short name T563
Test name
Test status
Simulation time 12171949 ps
CPU time 1.02 seconds
Started May 19 02:25:01 PM PDT 24
Finished May 19 02:25:03 PM PDT 24
Peak memory 216044 kb
Host smart-6489bdf5-2248-4117-8a76-fecc02d86179
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217182714 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3217182714
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3768773030
Short name T830
Test name
Test status
Simulation time 221340746 ps
CPU time 1.24 seconds
Started May 19 02:25:00 PM PDT 24
Finished May 19 02:25:02 PM PDT 24
Peak memory 217772 kb
Host smart-0829fd08-a71d-4fc4-9dc3-d6e6a04f0a6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768773030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3768773030
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1865655333
Short name T151
Test name
Test status
Simulation time 20249460 ps
CPU time 1.15 seconds
Started May 19 02:25:00 PM PDT 24
Finished May 19 02:25:02 PM PDT 24
Peak memory 218108 kb
Host smart-5b4d37ff-90e5-4ac2-9304-13c3574c0118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865655333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1865655333
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1576465384
Short name T419
Test name
Test status
Simulation time 34780803 ps
CPU time 1.43 seconds
Started May 19 02:25:02 PM PDT 24
Finished May 19 02:25:04 PM PDT 24
Peak memory 218184 kb
Host smart-8dca0c38-0c0c-4936-82b3-0287700b1fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576465384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1576465384
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3016944710
Short name T16
Test name
Test status
Simulation time 492544870 ps
CPU time 4.88 seconds
Started May 19 02:25:01 PM PDT 24
Finished May 19 02:25:06 PM PDT 24
Peak memory 242196 kb
Host smart-b012caa8-8eb9-4447-94df-57700b3899c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016944710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3016944710
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3513702146
Short name T565
Test name
Test status
Simulation time 46576869 ps
CPU time 0.91 seconds
Started May 19 02:24:59 PM PDT 24
Finished May 19 02:25:00 PM PDT 24
Peak memory 215024 kb
Host smart-d0e99a70-922c-482d-9a88-7beb6fdbdd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513702146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3513702146
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1454057875
Short name T360
Test name
Test status
Simulation time 273123739 ps
CPU time 5.42 seconds
Started May 19 02:24:59 PM PDT 24
Finished May 19 02:25:05 PM PDT 24
Peak memory 219792 kb
Host smart-2da55fa9-a0a5-402b-a9e0-50033d626de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454057875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1454057875
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3578838498
Short name T724
Test name
Test status
Simulation time 39866445415 ps
CPU time 921.35 seconds
Started May 19 02:25:03 PM PDT 24
Finished May 19 02:40:25 PM PDT 24
Peak memory 218736 kb
Host smart-603f1cee-7a2a-4f03-8547-bff4f0c813af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578838498 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3578838498
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3629856815
Short name T97
Test name
Test status
Simulation time 29169683 ps
CPU time 1.22 seconds
Started May 19 02:26:20 PM PDT 24
Finished May 19 02:26:22 PM PDT 24
Peak memory 215420 kb
Host smart-4edb4307-0503-4681-b58a-fd5c95cc2031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629856815 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3629856815
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4095917402
Short name T462
Test name
Test status
Simulation time 96450585 ps
CPU time 0.9 seconds
Started May 19 02:26:17 PM PDT 24
Finished May 19 02:26:19 PM PDT 24
Peak memory 206304 kb
Host smart-eb27809c-c293-49c5-a7a0-1512ca6e3997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095917402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4095917402
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1931829181
Short name T84
Test name
Test status
Simulation time 36034109 ps
CPU time 0.83 seconds
Started May 19 02:26:18 PM PDT 24
Finished May 19 02:26:20 PM PDT 24
Peak memory 216048 kb
Host smart-251540ad-df90-4d77-af21-4cb4cdaa9439
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931829181 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1931829181
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1605313308
Short name T772
Test name
Test status
Simulation time 61014176 ps
CPU time 1.27 seconds
Started May 19 02:26:21 PM PDT 24
Finished May 19 02:26:23 PM PDT 24
Peak memory 218060 kb
Host smart-23777832-710e-4288-90b4-465424e89295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605313308 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1605313308
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.491183594
Short name T771
Test name
Test status
Simulation time 82194626 ps
CPU time 0.86 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:21 PM PDT 24
Peak memory 217976 kb
Host smart-93495fec-e949-482c-bcd4-3238a9c2a5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491183594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.491183594
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4091957908
Short name T397
Test name
Test status
Simulation time 54765808 ps
CPU time 1.5 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:22 PM PDT 24
Peak memory 216688 kb
Host smart-be081b3d-ce05-4a64-b0ec-cae30561475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091957908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4091957908
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3007985824
Short name T680
Test name
Test status
Simulation time 25874063 ps
CPU time 0.96 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:20 PM PDT 24
Peak memory 215152 kb
Host smart-6406d89b-e462-4701-bf76-2ab17ce4b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007985824 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3007985824
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3695416244
Short name T458
Test name
Test status
Simulation time 24054311 ps
CPU time 0.89 seconds
Started May 19 02:26:18 PM PDT 24
Finished May 19 02:26:20 PM PDT 24
Peak memory 215016 kb
Host smart-72bd0c71-4e06-4f9d-a41f-be897e7295de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695416244 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3695416244
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1496957184
Short name T219
Test name
Test status
Simulation time 233073835 ps
CPU time 2.85 seconds
Started May 19 02:26:19 PM PDT 24
Finished May 19 02:26:22 PM PDT 24
Peak memory 215008 kb
Host smart-e6eeb439-9b9e-4d88-9e45-7bb2bf5ac3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496957184 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1496957184
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2239121065
Short name T203
Test name
Test status
Simulation time 152343902919 ps
CPU time 1046.33 seconds
Started May 19 02:26:20 PM PDT 24
Finished May 19 02:43:47 PM PDT 24
Peak memory 223224 kb
Host smart-a5e160b8-44fe-4486-8ebe-bdf7fb5dec9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239121065 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2239121065
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3350772559
Short name T260
Test name
Test status
Simulation time 27536865 ps
CPU time 1.26 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:30 PM PDT 24
Peak memory 215364 kb
Host smart-43755a03-d1e4-48df-b22c-677fb36d014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350772559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3350772559
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.823776950
Short name T432
Test name
Test status
Simulation time 59059187 ps
CPU time 0.87 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:29 PM PDT 24
Peak memory 214372 kb
Host smart-afdc2d52-e31a-40e6-8a35-ca7f0c21dad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823776950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.823776950
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.177949696
Short name T494
Test name
Test status
Simulation time 184030131 ps
CPU time 1.12 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:30 PM PDT 24
Peak memory 216728 kb
Host smart-b8ea3865-72b5-4d0f-9d1d-3fda2b358f0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177949696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.177949696
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2715407929
Short name T6
Test name
Test status
Simulation time 34019427 ps
CPU time 1.1 seconds
Started May 19 02:26:24 PM PDT 24
Finished May 19 02:26:26 PM PDT 24
Peak memory 229096 kb
Host smart-49e160de-f2f3-4ab8-bbcc-7011e680f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715407929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2715407929
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4097234152
Short name T281
Test name
Test status
Simulation time 60253382 ps
CPU time 1.79 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 218144 kb
Host smart-24d2db0c-5eee-4fee-9b07-88c1ace465a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097234152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4097234152
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3809512164
Short name T214
Test name
Test status
Simulation time 39737368 ps
CPU time 1.09 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:30 PM PDT 24
Peak memory 223604 kb
Host smart-087cf2cf-ccff-4365-91f6-fceb14c0df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809512164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3809512164
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2935929565
Short name T658
Test name
Test status
Simulation time 15789680 ps
CPU time 0.92 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:29 PM PDT 24
Peak memory 215192 kb
Host smart-722b8ccd-bd85-44c1-a29d-9e849c4d81c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935929565 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2935929565
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4098568254
Short name T688
Test name
Test status
Simulation time 220372895 ps
CPU time 1.79 seconds
Started May 19 02:26:24 PM PDT 24
Finished May 19 02:26:26 PM PDT 24
Peak memory 214988 kb
Host smart-aa94a255-6263-44c2-8b53-6412c03072be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098568254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4098568254
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3079083851
Short name T537
Test name
Test status
Simulation time 42581766061 ps
CPU time 1032.04 seconds
Started May 19 02:26:24 PM PDT 24
Finished May 19 02:43:37 PM PDT 24
Peak memory 218000 kb
Host smart-312729dd-8624-472d-81d1-135545a9eecf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079083851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3079083851
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.4288199753
Short name T313
Test name
Test status
Simulation time 47862175 ps
CPU time 0.88 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:29 PM PDT 24
Peak memory 214724 kb
Host smart-d0a5a598-2776-4753-bd76-d92a80cb872c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288199753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4288199753
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3027583585
Short name T137
Test name
Test status
Simulation time 13138232 ps
CPU time 0.87 seconds
Started May 19 02:26:31 PM PDT 24
Finished May 19 02:26:33 PM PDT 24
Peak memory 216100 kb
Host smart-353be7e0-0892-4558-9ba4-a6748cd95bfe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027583585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3027583585
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2885741090
Short name T105
Test name
Test status
Simulation time 117724558 ps
CPU time 1.2 seconds
Started May 19 02:26:30 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 216644 kb
Host smart-48b88561-9f53-43f7-95cf-802b407d35c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885741090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2885741090
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1255718782
Short name T188
Test name
Test status
Simulation time 31676216 ps
CPU time 0.86 seconds
Started May 19 02:26:28 PM PDT 24
Finished May 19 02:26:30 PM PDT 24
Peak memory 217928 kb
Host smart-4e4f7ab8-3707-4973-bac3-c54400a9f8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255718782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1255718782
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1551081336
Short name T499
Test name
Test status
Simulation time 63449489 ps
CPU time 1.2 seconds
Started May 19 02:26:26 PM PDT 24
Finished May 19 02:26:27 PM PDT 24
Peak memory 217880 kb
Host smart-47b5ce67-5506-4aab-8415-4083580371f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551081336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1551081336
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2643319638
Short name T404
Test name
Test status
Simulation time 21305780 ps
CPU time 1.12 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:31 PM PDT 24
Peak memory 215408 kb
Host smart-7d94f602-3332-4443-89c4-f9a0240db4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643319638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2643319638
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2097528108
Short name T492
Test name
Test status
Simulation time 25881519 ps
CPU time 0.94 seconds
Started May 19 02:26:24 PM PDT 24
Finished May 19 02:26:26 PM PDT 24
Peak memory 215004 kb
Host smart-c9b95f42-3bbe-46ed-8c66-3003a3dcf443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097528108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2097528108
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1018574643
Short name T208
Test name
Test status
Simulation time 78258417103 ps
CPU time 1852.06 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:57:23 PM PDT 24
Peak memory 224708 kb
Host smart-d5ab0c5e-6649-4e60-8a27-c600b6acba4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018574643 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1018574643
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4218239779
Short name T264
Test name
Test status
Simulation time 130308380 ps
CPU time 1.31 seconds
Started May 19 02:26:31 PM PDT 24
Finished May 19 02:26:33 PM PDT 24
Peak memory 215420 kb
Host smart-9f5a3d09-1bab-4aa0-a5fd-6726bcf0d48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218239779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4218239779
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1506813011
Short name T361
Test name
Test status
Simulation time 16759267 ps
CPU time 0.98 seconds
Started May 19 02:26:36 PM PDT 24
Finished May 19 02:26:39 PM PDT 24
Peak memory 206344 kb
Host smart-62e32814-ab9f-4ca9-b3b2-ce6b10bca785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506813011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1506813011
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.874455962
Short name T488
Test name
Test status
Simulation time 17920702 ps
CPU time 0.88 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:26:37 PM PDT 24
Peak memory 215708 kb
Host smart-308d1223-3b84-429d-80ec-088e89cf5e00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874455962 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.874455962
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1585396680
Short name T580
Test name
Test status
Simulation time 194041854 ps
CPU time 1.03 seconds
Started May 19 02:26:37 PM PDT 24
Finished May 19 02:26:40 PM PDT 24
Peak memory 216596 kb
Host smart-c9ffc97d-0d24-4dc2-ade9-bde8bca00b50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585396680 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1585396680
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.2539483761
Short name T838
Test name
Test status
Simulation time 21001374 ps
CPU time 1.17 seconds
Started May 19 02:26:30 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 219532 kb
Host smart-3281c683-a36e-4e0f-aa86-817ea31bd28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539483761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2539483761
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2673144417
Short name T532
Test name
Test status
Simulation time 63517800 ps
CPU time 1.23 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 218336 kb
Host smart-6ae8a3bb-3aa3-4913-84f2-700da877bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673144417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2673144417
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3980916578
Short name T760
Test name
Test status
Simulation time 40648806 ps
CPU time 0.9 seconds
Started May 19 02:26:30 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 215428 kb
Host smart-629812d1-ef97-44ae-9f0c-910bf0e0b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980916578 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3980916578
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3465716724
Short name T692
Test name
Test status
Simulation time 119412703 ps
CPU time 0.94 seconds
Started May 19 02:26:29 PM PDT 24
Finished May 19 02:26:32 PM PDT 24
Peak memory 215264 kb
Host smart-373bec36-50de-48bc-90d3-e4b52ea3deda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465716724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3465716724
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1679745071
Short name T646
Test name
Test status
Simulation time 377808773 ps
CPU time 4.25 seconds
Started May 19 02:26:31 PM PDT 24
Finished May 19 02:26:36 PM PDT 24
Peak memory 217956 kb
Host smart-3f7a3288-815c-4b77-8624-565c52291dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679745071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1679745071
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.944201576
Short name T656
Test name
Test status
Simulation time 19174079778 ps
CPU time 495.09 seconds
Started May 19 02:26:30 PM PDT 24
Finished May 19 02:34:47 PM PDT 24
Peak memory 216668 kb
Host smart-fc1b7751-41d9-418c-8874-1d921d27ffb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944201576 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.944201576
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2643325296
Short name T70
Test name
Test status
Simulation time 27276574 ps
CPU time 1.3 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:26:38 PM PDT 24
Peak memory 215396 kb
Host smart-3aff93dc-dcc3-4045-861e-2ddb10ec2a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643325296 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2643325296
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1581096758
Short name T315
Test name
Test status
Simulation time 21028486 ps
CPU time 0.87 seconds
Started May 19 02:26:37 PM PDT 24
Finished May 19 02:26:39 PM PDT 24
Peak memory 206284 kb
Host smart-68d42a22-d68d-4a33-88f3-7ede641c5f7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581096758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1581096758
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1189084068
Short name T553
Test name
Test status
Simulation time 13472505 ps
CPU time 0.95 seconds
Started May 19 02:26:38 PM PDT 24
Finished May 19 02:26:40 PM PDT 24
Peak memory 215980 kb
Host smart-fd16cbb0-fe32-4a7f-8fc6-f30462dde459
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189084068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1189084068
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.565708110
Short name T337
Test name
Test status
Simulation time 24829983 ps
CPU time 0.95 seconds
Started May 19 02:26:36 PM PDT 24
Finished May 19 02:26:39 PM PDT 24
Peak memory 219256 kb
Host smart-5c51861a-8915-4aee-956e-4c7eec39c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565708110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.565708110
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1397332425
Short name T336
Test name
Test status
Simulation time 54169950 ps
CPU time 1.52 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:26:38 PM PDT 24
Peak memory 218132 kb
Host smart-ace88e70-3082-4c8d-b55b-f8b157df2199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397332425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1397332425
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3926803748
Short name T158
Test name
Test status
Simulation time 20840552 ps
CPU time 1.05 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:26:37 PM PDT 24
Peak memory 215404 kb
Host smart-161b65af-541b-480b-a56f-35fd51dbbf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926803748 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3926803748
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2079582302
Short name T400
Test name
Test status
Simulation time 21856826 ps
CPU time 0.89 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:26:38 PM PDT 24
Peak memory 214996 kb
Host smart-f6f14031-c75a-4d59-b268-ccb9aa5d62b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079582302 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2079582302
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1908084441
Short name T528
Test name
Test status
Simulation time 1421004789 ps
CPU time 4.55 seconds
Started May 19 02:26:37 PM PDT 24
Finished May 19 02:26:43 PM PDT 24
Peak memory 216748 kb
Host smart-5fa1c342-dbc6-4c63-a059-e24d828d02de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908084441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1908084441
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4220087954
Short name T209
Test name
Test status
Simulation time 29674220137 ps
CPU time 634.93 seconds
Started May 19 02:26:34 PM PDT 24
Finished May 19 02:37:11 PM PDT 24
Peak memory 218488 kb
Host smart-3a6feb8f-0981-4b2a-864b-4e5dc77c16b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220087954 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4220087954
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1894698030
Short name T268
Test name
Test status
Simulation time 30834764 ps
CPU time 1.34 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:41 PM PDT 24
Peak memory 215376 kb
Host smart-383da010-a875-4f11-a06f-efb31493ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894698030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1894698030
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2845853318
Short name T675
Test name
Test status
Simulation time 28614582 ps
CPU time 0.9 seconds
Started May 19 02:26:42 PM PDT 24
Finished May 19 02:26:43 PM PDT 24
Peak memory 206312 kb
Host smart-f486dd57-0c88-4a82-accc-1a95599e2c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845853318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2845853318
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1847511670
Short name T540
Test name
Test status
Simulation time 14408798 ps
CPU time 0.9 seconds
Started May 19 02:26:40 PM PDT 24
Finished May 19 02:26:42 PM PDT 24
Peak memory 216216 kb
Host smart-2dcb27bf-257b-4cf8-b114-a1953dbf8551
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847511670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1847511670
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2044621507
Short name T638
Test name
Test status
Simulation time 46551318 ps
CPU time 1.46 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:42 PM PDT 24
Peak memory 216928 kb
Host smart-80b64fad-e4ed-4498-bd29-b7e0ada56ffc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044621507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2044621507
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4252283399
Short name T664
Test name
Test status
Simulation time 28853950 ps
CPU time 1.29 seconds
Started May 19 02:26:41 PM PDT 24
Finished May 19 02:26:43 PM PDT 24
Peak memory 219356 kb
Host smart-11076a1f-b349-46c9-8126-334fff0d6a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252283399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4252283399
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.4227063423
Short name T779
Test name
Test status
Simulation time 45423266 ps
CPU time 1.36 seconds
Started May 19 02:26:33 PM PDT 24
Finished May 19 02:26:35 PM PDT 24
Peak memory 218072 kb
Host smart-d9c92697-9af9-4959-b8fb-0668bd4710aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227063423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.4227063423
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1109141105
Short name T37
Test name
Test status
Simulation time 34343235 ps
CPU time 0.87 seconds
Started May 19 02:26:40 PM PDT 24
Finished May 19 02:26:42 PM PDT 24
Peak memory 215336 kb
Host smart-18c5e330-e93c-4b6b-914e-ff9307ba7710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109141105 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1109141105
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3211410802
Short name T381
Test name
Test status
Simulation time 56987462 ps
CPU time 0.91 seconds
Started May 19 02:26:37 PM PDT 24
Finished May 19 02:26:39 PM PDT 24
Peak memory 214960 kb
Host smart-f7b51340-ce1d-4cf5-b2d1-57a7fb69a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211410802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3211410802
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.286717951
Short name T653
Test name
Test status
Simulation time 302770546 ps
CPU time 6.08 seconds
Started May 19 02:26:35 PM PDT 24
Finished May 19 02:26:43 PM PDT 24
Peak memory 215024 kb
Host smart-a40c6ba8-0873-4e9b-ad83-29845c9b2994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286717951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.286717951
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2213882196
Short name T398
Test name
Test status
Simulation time 27401877126 ps
CPU time 435.49 seconds
Started May 19 02:26:41 PM PDT 24
Finished May 19 02:33:57 PM PDT 24
Peak memory 223420 kb
Host smart-4b753b02-eac6-49e3-88ad-f37a185e857d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213882196 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2213882196
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3192685888
Short name T611
Test name
Test status
Simulation time 25312657 ps
CPU time 1.19 seconds
Started May 19 02:26:41 PM PDT 24
Finished May 19 02:26:43 PM PDT 24
Peak memory 215420 kb
Host smart-da710877-9656-4802-810a-f2c1d8ca4d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192685888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3192685888
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.793939628
Short name T364
Test name
Test status
Simulation time 39299850 ps
CPU time 0.88 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:48 PM PDT 24
Peak memory 206148 kb
Host smart-9dafad98-180f-4797-967d-ecfd7e756aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793939628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.793939628
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2336264028
Short name T186
Test name
Test status
Simulation time 36979829 ps
CPU time 0.87 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:48 PM PDT 24
Peak memory 216220 kb
Host smart-0832fb73-3fcd-4afa-a727-ab68ef6c3008
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336264028 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2336264028
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1447644810
Short name T88
Test name
Test status
Simulation time 106247215 ps
CPU time 1.1 seconds
Started May 19 02:26:47 PM PDT 24
Finished May 19 02:26:50 PM PDT 24
Peak memory 216576 kb
Host smart-57662053-853c-41bc-94ad-f32e4db55d0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447644810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1447644810
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1367315627
Short name T109
Test name
Test status
Simulation time 52083809 ps
CPU time 1.14 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:41 PM PDT 24
Peak memory 229144 kb
Host smart-837ccd81-46ff-4367-932a-4d4dd11ada9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367315627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1367315627
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1211924736
Short name T574
Test name
Test status
Simulation time 50298537 ps
CPU time 1.52 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:42 PM PDT 24
Peak memory 217876 kb
Host smart-14b5675b-26c8-4a82-b381-8448f50f68f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211924736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1211924736
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3276162075
Short name T320
Test name
Test status
Simulation time 22181905 ps
CPU time 1.09 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:41 PM PDT 24
Peak memory 215132 kb
Host smart-cf8b507d-740e-4db8-b79a-ddcb80a7ae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276162075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3276162075
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1229383819
Short name T312
Test name
Test status
Simulation time 14213417 ps
CPU time 0.92 seconds
Started May 19 02:26:40 PM PDT 24
Finished May 19 02:26:42 PM PDT 24
Peak memory 214932 kb
Host smart-e52e0afe-7698-45ec-8a15-7ef6370f929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229383819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1229383819
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2172769021
Short name T353
Test name
Test status
Simulation time 234620376 ps
CPU time 4.17 seconds
Started May 19 02:26:39 PM PDT 24
Finished May 19 02:26:45 PM PDT 24
Peak memory 216728 kb
Host smart-98c0d860-0e1c-4faf-89ef-484818434332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172769021 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2172769021
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3044974238
Short name T460
Test name
Test status
Simulation time 53690097396 ps
CPU time 309.19 seconds
Started May 19 02:26:40 PM PDT 24
Finished May 19 02:31:50 PM PDT 24
Peak memory 221252 kb
Host smart-15a44f4c-9867-437d-8d32-44719ce92016
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044974238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3044974238
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3683699810
Short name T167
Test name
Test status
Simulation time 89490866 ps
CPU time 1.25 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 215420 kb
Host smart-6c20d04c-01db-447a-97c1-2fbfb1668892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683699810 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3683699810
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2953040695
Short name T823
Test name
Test status
Simulation time 54264247 ps
CPU time 0.91 seconds
Started May 19 02:26:49 PM PDT 24
Finished May 19 02:26:51 PM PDT 24
Peak memory 206448 kb
Host smart-814fd347-2cbc-43fa-9480-a56e0c169875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953040695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2953040695
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2856462542
Short name T429
Test name
Test status
Simulation time 26399414 ps
CPU time 0.93 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 215724 kb
Host smart-8ab35976-9eec-459f-9d65-5f9c4057c209
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856462542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2856462542
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2802207699
Short name T73
Test name
Test status
Simulation time 43259769 ps
CPU time 1 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:48 PM PDT 24
Peak memory 217944 kb
Host smart-33a84d98-e87b-458b-97a8-b994da6bb29c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802207699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2802207699
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1530305600
Short name T2
Test name
Test status
Simulation time 19608074 ps
CPU time 1.09 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 218224 kb
Host smart-a9ba3b44-20dd-4336-a463-eace321131ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530305600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1530305600
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.162499239
Short name T624
Test name
Test status
Simulation time 65528659 ps
CPU time 1.15 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 216972 kb
Host smart-60f1ee3f-8e74-418a-9383-245ebc840819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162499239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.162499239
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3018509853
Short name T49
Test name
Test status
Simulation time 29116228 ps
CPU time 1.04 seconds
Started May 19 02:26:45 PM PDT 24
Finished May 19 02:26:47 PM PDT 24
Peak memory 223628 kb
Host smart-db805be3-1779-4fa6-8d7e-0f69f3e61f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018509853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3018509853
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2165174734
Short name T366
Test name
Test status
Simulation time 16168649 ps
CPU time 1 seconds
Started May 19 02:26:48 PM PDT 24
Finished May 19 02:26:50 PM PDT 24
Peak memory 215008 kb
Host smart-4ed0c873-0681-449f-9994-999a5572f99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165174734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2165174734
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3964527011
Short name T433
Test name
Test status
Simulation time 1011924696 ps
CPU time 3.29 seconds
Started May 19 02:26:48 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 216856 kb
Host smart-36757d6e-a305-4ecc-aedf-d0a11df585a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964527011 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3964527011
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert.773039706
Short name T194
Test name
Test status
Simulation time 87527288 ps
CPU time 1.2 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 215408 kb
Host smart-3f0b0ae3-ab9a-4e0c-929e-4b6e55ea78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773039706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.773039706
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.112511229
Short name T529
Test name
Test status
Simulation time 150172660 ps
CPU time 0.87 seconds
Started May 19 02:26:45 PM PDT 24
Finished May 19 02:26:47 PM PDT 24
Peak memory 214864 kb
Host smart-9f37c746-ad74-4a07-8f11-b678a32eb765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112511229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.112511229
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2202211768
Short name T752
Test name
Test status
Simulation time 19015102 ps
CPU time 0.93 seconds
Started May 19 02:26:44 PM PDT 24
Finished May 19 02:26:46 PM PDT 24
Peak memory 216020 kb
Host smart-e1f1a2b7-f9cf-4cf5-80f7-ea95ed5f303d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202211768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2202211768
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.1092632292
Short name T58
Test name
Test status
Simulation time 26801423 ps
CPU time 1.06 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:48 PM PDT 24
Peak memory 223556 kb
Host smart-91ccc14f-df45-4948-8183-47e60ee74407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092632292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1092632292
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1629281353
Short name T308
Test name
Test status
Simulation time 99913300 ps
CPU time 1.16 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 216664 kb
Host smart-e6fcb653-417c-4aaa-96dd-5b61d63f068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629281353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1629281353
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2969617091
Short name T527
Test name
Test status
Simulation time 21528549 ps
CPU time 1.15 seconds
Started May 19 02:26:49 PM PDT 24
Finished May 19 02:26:51 PM PDT 24
Peak memory 223580 kb
Host smart-a9a10a00-5755-4306-9b1d-c1e1c6ae9f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969617091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2969617091
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2374367495
Short name T837
Test name
Test status
Simulation time 45176781 ps
CPU time 0.88 seconds
Started May 19 02:26:45 PM PDT 24
Finished May 19 02:26:46 PM PDT 24
Peak memory 214996 kb
Host smart-3ad32b9a-cac9-4362-a0c6-e433fe62cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374367495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2374367495
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1055089711
Short name T217
Test name
Test status
Simulation time 48444127 ps
CPU time 1.56 seconds
Started May 19 02:26:46 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 214996 kb
Host smart-f5e63615-b0d5-4dcb-b0ad-96c2793a76ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055089711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1055089711
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.652837872
Short name T471
Test name
Test status
Simulation time 61018751919 ps
CPU time 702.76 seconds
Started May 19 02:26:48 PM PDT 24
Finished May 19 02:38:32 PM PDT 24
Peak memory 221820 kb
Host smart-285871d5-9f56-48cb-a4f3-f0b1c2572d45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652837872 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.652837872
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2691140230
Short name T694
Test name
Test status
Simulation time 78078649 ps
CPU time 1.08 seconds
Started May 19 02:26:47 PM PDT 24
Finished May 19 02:26:49 PM PDT 24
Peak memory 215352 kb
Host smart-8427e080-c069-4d76-832d-102cd20c60a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691140230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2691140230
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.211526273
Short name T434
Test name
Test status
Simulation time 21034315 ps
CPU time 0.88 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 214456 kb
Host smart-8ab4ba6a-58d1-4f88-a607-7fd0591dd2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211526273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.211526273
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3389399070
Short name T508
Test name
Test status
Simulation time 30267721 ps
CPU time 1.07 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 216536 kb
Host smart-4b782c56-355a-4c5f-8de4-a5e26a89e769
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389399070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3389399070
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.283963819
Short name T630
Test name
Test status
Simulation time 54447148 ps
CPU time 0.92 seconds
Started May 19 02:26:49 PM PDT 24
Finished May 19 02:26:51 PM PDT 24
Peak memory 223296 kb
Host smart-f8670b47-1260-49f8-8cb8-dd331beabbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283963819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.283963819
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.216067565
Short name T545
Test name
Test status
Simulation time 234085486 ps
CPU time 1.79 seconds
Started May 19 02:26:48 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 217964 kb
Host smart-b0a5885f-fcb5-4123-89aa-fc02fb0cbd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216067565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.216067565
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.856032685
Short name T329
Test name
Test status
Simulation time 23815729 ps
CPU time 1.29 seconds
Started May 19 02:26:47 PM PDT 24
Finished May 19 02:26:50 PM PDT 24
Peak memory 223644 kb
Host smart-c9fd0384-a7ee-4e12-a068-c3723259639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856032685 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.856032685
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1341923340
Short name T801
Test name
Test status
Simulation time 150620863 ps
CPU time 0.94 seconds
Started May 19 02:26:45 PM PDT 24
Finished May 19 02:26:47 PM PDT 24
Peak memory 214864 kb
Host smart-1059e882-20eb-4407-96a6-9d7560444680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341923340 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1341923340
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3580598156
Short name T346
Test name
Test status
Simulation time 206164827 ps
CPU time 4.37 seconds
Started May 19 02:26:49 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 216496 kb
Host smart-87058d87-6e0d-482d-b6e8-d383de5339d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580598156 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3580598156
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1422506296
Short name T593
Test name
Test status
Simulation time 106847468519 ps
CPU time 2849.87 seconds
Started May 19 02:26:47 PM PDT 24
Finished May 19 03:14:18 PM PDT 24
Peak memory 233048 kb
Host smart-72fb333c-7a04-4d7f-8000-e1cb2cff5688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422506296 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1422506296
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2371028196
Short name T793
Test name
Test status
Simulation time 43061045 ps
CPU time 1.19 seconds
Started May 19 02:25:05 PM PDT 24
Finished May 19 02:25:06 PM PDT 24
Peak memory 215444 kb
Host smart-bfddbd51-cc1d-42d7-bd9b-c88a3a38b72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371028196 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2371028196
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4123047654
Short name T441
Test name
Test status
Simulation time 46897763 ps
CPU time 0.93 seconds
Started May 19 02:25:06 PM PDT 24
Finished May 19 02:25:07 PM PDT 24
Peak memory 206596 kb
Host smart-5de89905-1a4b-4513-aa77-73a130a879bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123047654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4123047654
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.632412782
Short name T183
Test name
Test status
Simulation time 12603589 ps
CPU time 0.93 seconds
Started May 19 02:25:06 PM PDT 24
Finished May 19 02:25:07 PM PDT 24
Peak memory 215320 kb
Host smart-c58a0405-ea3d-48b9-9b70-b49429f914ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632412782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.632412782
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3611798896
Short name T815
Test name
Test status
Simulation time 33862385 ps
CPU time 1.18 seconds
Started May 19 02:25:04 PM PDT 24
Finished May 19 02:25:06 PM PDT 24
Peak memory 218168 kb
Host smart-34ecc428-7f74-401a-9ad7-470e30b70d6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611798896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3611798896
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.146935226
Short name T378
Test name
Test status
Simulation time 19144149 ps
CPU time 1.12 seconds
Started May 19 02:25:05 PM PDT 24
Finished May 19 02:25:07 PM PDT 24
Peak memory 219260 kb
Host smart-20f17087-3e87-4143-bf37-d0d1dee6090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146935226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.146935226
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3883142451
Short name T383
Test name
Test status
Simulation time 114791359 ps
CPU time 1.21 seconds
Started May 19 02:25:00 PM PDT 24
Finished May 19 02:25:02 PM PDT 24
Peak memory 218052 kb
Host smart-0a0209a5-f9aa-4dc8-b758-a10bf851e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883142451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3883142451
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3430147267
Short name T379
Test name
Test status
Simulation time 28462950 ps
CPU time 0.95 seconds
Started May 19 02:25:05 PM PDT 24
Finished May 19 02:25:07 PM PDT 24
Peak memory 215108 kb
Host smart-65eece48-388f-419c-97e9-b05879e75034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430147267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3430147267
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.623850761
Short name T17
Test name
Test status
Simulation time 445454596 ps
CPU time 4.31 seconds
Started May 19 02:25:05 PM PDT 24
Finished May 19 02:25:10 PM PDT 24
Peak memory 236140 kb
Host smart-09728e38-f9e9-43cf-9e47-a757208b480b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623850761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.623850761
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.622508513
Short name T718
Test name
Test status
Simulation time 14698897 ps
CPU time 0.93 seconds
Started May 19 02:25:01 PM PDT 24
Finished May 19 02:25:03 PM PDT 24
Peak memory 214992 kb
Host smart-ad725c34-0e3d-4ba6-9c9b-f734dc3416c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622508513 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.622508513
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3512347409
Short name T597
Test name
Test status
Simulation time 154966851 ps
CPU time 2.7 seconds
Started May 19 02:25:06 PM PDT 24
Finished May 19 02:25:09 PM PDT 24
Peak memory 216496 kb
Host smart-d9553937-e92d-48ac-abee-44f98e917091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512347409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3512347409
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_alert.1000874688
Short name T657
Test name
Test status
Simulation time 56762587 ps
CPU time 1.21 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 215380 kb
Host smart-03a1a98a-b0ac-4deb-86c3-4b86cd85aa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000874688 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1000874688
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.275899088
Short name T464
Test name
Test status
Simulation time 25758842 ps
CPU time 0.88 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 206320 kb
Host smart-145bc4f8-9c47-437e-83a9-e18833e11f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275899088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.275899088
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3535699755
Short name T445
Test name
Test status
Simulation time 35850394 ps
CPU time 1.27 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 216620 kb
Host smart-5767ab85-d672-49ed-8e9e-603ed2b84a71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535699755 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3535699755
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3686097797
Short name T176
Test name
Test status
Simulation time 35366453 ps
CPU time 1.09 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 229332 kb
Host smart-c3b47903-8415-426b-9d0e-da99b798107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686097797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3686097797
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4024872762
Short name T438
Test name
Test status
Simulation time 41521648 ps
CPU time 1.33 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:58 PM PDT 24
Peak memory 218164 kb
Host smart-1863348c-0091-4284-a165-84e37c80dd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024872762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4024872762
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.399020984
Short name T742
Test name
Test status
Simulation time 24132256 ps
CPU time 0.92 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 215352 kb
Host smart-4a6d43d0-cf18-4d23-b580-9ce3adaea317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399020984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.399020984
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.584966124
Short name T401
Test name
Test status
Simulation time 46111160 ps
CPU time 0.92 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 215028 kb
Host smart-3ea6aab4-a659-4737-9a50-5fa6ad0d79b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584966124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.584966124
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2598403492
Short name T524
Test name
Test status
Simulation time 124335999 ps
CPU time 1.78 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 217972 kb
Host smart-9141673e-2709-4901-bd1a-14facf76942e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598403492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2598403492
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3184402872
Short name T489
Test name
Test status
Simulation time 73814566028 ps
CPU time 1678.97 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:54:52 PM PDT 24
Peak memory 223324 kb
Host smart-484bff11-9f2b-4690-af9f-392fbb98fed7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184402872 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3184402872
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.440451581
Short name T519
Test name
Test status
Simulation time 69483538 ps
CPU time 1.16 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 215412 kb
Host smart-f3430043-c8db-4762-8fce-8552caf25476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440451581 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.440451581
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2218962194
Short name T807
Test name
Test status
Simulation time 56706491 ps
CPU time 0.93 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 206344 kb
Host smart-bd5ddf09-c7b4-4617-96b6-8548de1c2ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218962194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2218962194
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.624565626
Short name T495
Test name
Test status
Simulation time 12549984 ps
CPU time 0.9 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 215348 kb
Host smart-e875c4b2-f033-4896-809e-69b376be6ab3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624565626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.624565626
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.2180143539
Short name T111
Test name
Test status
Simulation time 88811832 ps
CPU time 1.01 seconds
Started May 19 02:26:53 PM PDT 24
Finished May 19 02:26:55 PM PDT 24
Peak memory 220140 kb
Host smart-d095ee0c-5afe-411c-a15c-b9f6ecace42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180143539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2180143539
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2953499478
Short name T758
Test name
Test status
Simulation time 54224068 ps
CPU time 1.27 seconds
Started May 19 02:26:51 PM PDT 24
Finished May 19 02:26:53 PM PDT 24
Peak memory 218280 kb
Host smart-c0272e9c-f0b5-48a9-8905-53ed3f2e4107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953499478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2953499478
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.988136164
Short name T34
Test name
Test status
Simulation time 31322993 ps
CPU time 0.87 seconds
Started May 19 02:26:54 PM PDT 24
Finished May 19 02:26:56 PM PDT 24
Peak memory 215272 kb
Host smart-3e7e744d-e238-4b18-ac3c-bea881d6592d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988136164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.988136164
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1938284811
Short name T330
Test name
Test status
Simulation time 25683122 ps
CPU time 0.96 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 215016 kb
Host smart-0602c1a4-a9a7-40f2-820f-d00a1c02eeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938284811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1938284811
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.657397612
Short name T451
Test name
Test status
Simulation time 186024579 ps
CPU time 4.07 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 219608 kb
Host smart-ea2dd8d2-6022-4d90-acc4-f87861f4f1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657397612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.657397612
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.76913970
Short name T181
Test name
Test status
Simulation time 78382363197 ps
CPU time 1814.65 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:57:07 PM PDT 24
Peak memory 224180 kb
Host smart-45d72317-5e6f-48bd-90ad-f85884d7c783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76913970 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.76913970
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.613367620
Short name T436
Test name
Test status
Simulation time 75890407 ps
CPU time 0.83 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 206172 kb
Host smart-5b0e6f40-28c2-4a02-b6c1-9240996be221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613367620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.613367620
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3085146789
Short name T127
Test name
Test status
Simulation time 40283612 ps
CPU time 0.89 seconds
Started May 19 02:26:50 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 215220 kb
Host smart-6713e72e-d996-4623-9344-547a9d3814f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085146789 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3085146789
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.531132216
Short name T831
Test name
Test status
Simulation time 47974811 ps
CPU time 1.11 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:58 PM PDT 24
Peak memory 216640 kb
Host smart-b49cff2b-b362-49d0-a4da-55043ce9c1ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531132216 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.531132216
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1685294260
Short name T843
Test name
Test status
Simulation time 31867547 ps
CPU time 0.86 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 217840 kb
Host smart-bdda6a83-b648-4755-bec7-e8e8c9825e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685294260 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1685294260
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1426905169
Short name T282
Test name
Test status
Simulation time 55439061 ps
CPU time 1.36 seconds
Started May 19 02:26:50 PM PDT 24
Finished May 19 02:26:52 PM PDT 24
Peak memory 218372 kb
Host smart-24180e0a-889a-4d2c-b49a-87f626c4cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426905169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1426905169
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3153405134
Short name T39
Test name
Test status
Simulation time 22210750 ps
CPU time 1.09 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 215400 kb
Host smart-27a736d2-8e2a-476a-86a3-70016675a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153405134 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3153405134
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3594753938
Short name T355
Test name
Test status
Simulation time 26397106 ps
CPU time 0.96 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:26:54 PM PDT 24
Peak memory 206828 kb
Host smart-4a1ca19f-78cc-4ff1-9ce4-00a32a8c3e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594753938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3594753938
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.21251268
Short name T703
Test name
Test status
Simulation time 116171386 ps
CPU time 1.33 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:58 PM PDT 24
Peak memory 216632 kb
Host smart-e10c7ca2-be29-419e-b6b9-7cacfb4267b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.21251268
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3916000991
Short name T456
Test name
Test status
Simulation time 14005940387 ps
CPU time 372.37 seconds
Started May 19 02:26:52 PM PDT 24
Finished May 19 02:33:05 PM PDT 24
Peak memory 222928 kb
Host smart-6940fcba-f2b2-4744-954f-0c1fd97f0608
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916000991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3916000991
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2574952611
Short name T27
Test name
Test status
Simulation time 27157202 ps
CPU time 1.22 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 215412 kb
Host smart-3c876e86-dc0f-4f50-bc3f-6ee913dcaa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574952611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2574952611
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3483659357
Short name T76
Test name
Test status
Simulation time 60341085 ps
CPU time 0.84 seconds
Started May 19 02:26:57 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 206064 kb
Host smart-4900b9a3-f40f-4912-a5d1-b20ced1f47a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483659357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3483659357
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1948130487
Short name T575
Test name
Test status
Simulation time 20836759 ps
CPU time 0.9 seconds
Started May 19 02:26:57 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 216092 kb
Host smart-aa3040a4-426f-4b2b-8ce4-c950ec87a857
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948130487 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1948130487
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2743311821
Short name T518
Test name
Test status
Simulation time 279468538 ps
CPU time 1.03 seconds
Started May 19 02:26:54 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 217820 kb
Host smart-120571f1-1805-4bea-bc54-a94d9029b238
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743311821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2743311821
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2238237329
Short name T123
Test name
Test status
Simulation time 162029835 ps
CPU time 1.01 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:58 PM PDT 24
Peak memory 219160 kb
Host smart-06ddc822-6868-4ecb-bded-4fc5e086bf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238237329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2238237329
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3287007684
Short name T389
Test name
Test status
Simulation time 75654066 ps
CPU time 1.09 seconds
Started May 19 02:26:54 PM PDT 24
Finished May 19 02:26:56 PM PDT 24
Peak memory 216872 kb
Host smart-606c5666-cbf8-4f9b-a057-a8c7d0ff9a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287007684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3287007684
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3077765533
Short name T625
Test name
Test status
Simulation time 20687622 ps
CPU time 1.05 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 215432 kb
Host smart-e73f1537-6b4a-4532-a749-bd155c19e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077765533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3077765533
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3625266429
Short name T845
Test name
Test status
Simulation time 25441921 ps
CPU time 0.94 seconds
Started May 19 02:26:57 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 215008 kb
Host smart-2a2af1f3-a0b8-40fe-ad33-f80092a8e30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625266429 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3625266429
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.4214623728
Short name T55
Test name
Test status
Simulation time 965424774 ps
CPU time 5.03 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 216656 kb
Host smart-39b9403f-1789-4eea-8374-686124859472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214623728 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4214623728
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2855605262
Short name T812
Test name
Test status
Simulation time 172395258269 ps
CPU time 1266.8 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:48:04 PM PDT 24
Peak memory 221844 kb
Host smart-49f8ab3b-113c-4122-bf2a-2dc514aec4d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855605262 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2855605262
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2415365620
Short name T665
Test name
Test status
Simulation time 72339101 ps
CPU time 1.18 seconds
Started May 19 02:26:57 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 215408 kb
Host smart-7317201b-598f-4be2-9907-51d42b044fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415365620 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2415365620
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2159774425
Short name T709
Test name
Test status
Simulation time 13018036 ps
CPU time 0.93 seconds
Started May 19 02:27:04 PM PDT 24
Finished May 19 02:27:05 PM PDT 24
Peak memory 206720 kb
Host smart-3ccbcb93-efc7-49e1-99d3-a12637754523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159774425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2159774425
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2620472182
Short name T149
Test name
Test status
Simulation time 24002722 ps
CPU time 0.87 seconds
Started May 19 02:27:00 PM PDT 24
Finished May 19 02:27:02 PM PDT 24
Peak memory 216084 kb
Host smart-f48c2f7d-4eb2-4a14-8a0d-d864116562ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620472182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2620472182
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3764232382
Short name T721
Test name
Test status
Simulation time 77322125 ps
CPU time 1.11 seconds
Started May 19 02:27:01 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 217808 kb
Host smart-05162f6c-e65d-46cb-8291-c9c674e0e017
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764232382 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3764232382
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.976346001
Short name T175
Test name
Test status
Simulation time 74800036 ps
CPU time 1 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:58 PM PDT 24
Peak memory 220024 kb
Host smart-fc97e5e7-1d90-4f6e-9071-d51b1e648b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976346001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.976346001
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.28716643
Short name T215
Test name
Test status
Simulation time 34810369 ps
CPU time 1.16 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 218180 kb
Host smart-cfe76e99-9a05-4426-ae48-06ed7c2b19a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28716643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.28716643
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4940023
Short name T171
Test name
Test status
Simulation time 27720556 ps
CPU time 1.21 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:26:59 PM PDT 24
Peak memory 215476 kb
Host smart-d166ae10-a311-4138-86a6-65f3cda1775f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4940023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4940023
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2113287642
Short name T612
Test name
Test status
Simulation time 26506799 ps
CPU time 0.95 seconds
Started May 19 02:26:55 PM PDT 24
Finished May 19 02:26:57 PM PDT 24
Peak memory 215036 kb
Host smart-51dbe6b6-0028-4180-8b82-6af7da806367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113287642 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2113287642
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.4087629603
Short name T769
Test name
Test status
Simulation time 290604879 ps
CPU time 5.55 seconds
Started May 19 02:26:54 PM PDT 24
Finished May 19 02:27:01 PM PDT 24
Peak memory 216624 kb
Host smart-6e5b203f-a968-4b77-affb-1ea248922124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087629603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.4087629603
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1029860304
Short name T42
Test name
Test status
Simulation time 96060435139 ps
CPU time 572.09 seconds
Started May 19 02:26:56 PM PDT 24
Finished May 19 02:36:30 PM PDT 24
Peak memory 219068 kb
Host smart-0eb55226-4bfc-4968-a5c4-ae2558e7158d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029860304 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1029860304
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3034159158
Short name T53
Test name
Test status
Simulation time 29130933 ps
CPU time 1.25 seconds
Started May 19 02:27:01 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 215496 kb
Host smart-ec0490ea-37d6-4a28-802a-54614aa468d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034159158 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3034159158
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1424132769
Short name T468
Test name
Test status
Simulation time 37633400 ps
CPU time 1.05 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:09 PM PDT 24
Peak memory 214644 kb
Host smart-0db25757-ad77-4f26-afa0-ade8fc276051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424132769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1424132769
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.157043316
Short name T324
Test name
Test status
Simulation time 33243341 ps
CPU time 0.98 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 215712 kb
Host smart-ab5f98ac-f7fd-4989-adad-fa6c19faf6bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157043316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.157043316
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.218413843
Short name T124
Test name
Test status
Simulation time 36016667 ps
CPU time 1.26 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:07 PM PDT 24
Peak memory 216644 kb
Host smart-2b3ddb71-69c2-4d71-9d52-e99843de8b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218413843 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.218413843
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.98478456
Short name T369
Test name
Test status
Simulation time 19242616 ps
CPU time 1.08 seconds
Started May 19 02:27:00 PM PDT 24
Finished May 19 02:27:01 PM PDT 24
Peak memory 218376 kb
Host smart-988288fd-0684-4668-a239-1381591892ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98478456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.98478456
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.633605309
Short name T696
Test name
Test status
Simulation time 35720656 ps
CPU time 1.43 seconds
Started May 19 02:27:01 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 215104 kb
Host smart-7508911e-cfd6-480d-94b5-e3d92a4148c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633605309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.633605309
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2829800509
Short name T345
Test name
Test status
Simulation time 20466403 ps
CPU time 1.14 seconds
Started May 19 02:27:02 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 215384 kb
Host smart-185fcbba-33c4-4357-aff1-e41f2efc6c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829800509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2829800509
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2724151005
Short name T517
Test name
Test status
Simulation time 26523995 ps
CPU time 0.98 seconds
Started May 19 02:27:01 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 214972 kb
Host smart-06eb086d-b1dd-4dac-8c52-f3bea54bbaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724151005 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2724151005
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3630786415
Short name T756
Test name
Test status
Simulation time 138733889 ps
CPU time 1.45 seconds
Started May 19 02:27:01 PM PDT 24
Finished May 19 02:27:03 PM PDT 24
Peak memory 215000 kb
Host smart-b867ad40-73df-4169-967a-ae10c4fcc08e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630786415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3630786415
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3244528109
Short name T423
Test name
Test status
Simulation time 132027139134 ps
CPU time 517.33 seconds
Started May 19 02:27:05 PM PDT 24
Finished May 19 02:35:43 PM PDT 24
Peak memory 219300 kb
Host smart-4e520c14-6217-4550-ac0f-059c6ff67e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244528109 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3244528109
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.2134806359
Short name T71
Test name
Test status
Simulation time 14500804 ps
CPU time 0.87 seconds
Started May 19 02:27:07 PM PDT 24
Finished May 19 02:27:09 PM PDT 24
Peak memory 206328 kb
Host smart-2eac8c3a-5d17-4288-8948-be04b0385b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134806359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2134806359
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.238102085
Short name T187
Test name
Test status
Simulation time 13027573 ps
CPU time 0.9 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 216208 kb
Host smart-a8685045-26ed-466f-b460-15df46123401
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238102085 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.238102085
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.731436026
Short name T613
Test name
Test status
Simulation time 86798941 ps
CPU time 1.34 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 216704 kb
Host smart-d613a148-6d42-4b1b-96fa-83e16057ea9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731436026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.731436026
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.784882697
Short name T427
Test name
Test status
Simulation time 213641339 ps
CPU time 1.63 seconds
Started May 19 02:27:07 PM PDT 24
Finished May 19 02:27:09 PM PDT 24
Peak memory 218208 kb
Host smart-35665dc5-898f-410c-9d59-e7f73a5c1a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784882697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.784882697
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1702203244
Short name T334
Test name
Test status
Simulation time 27113519 ps
CPU time 0.96 seconds
Started May 19 02:27:09 PM PDT 24
Finished May 19 02:27:11 PM PDT 24
Peak memory 215112 kb
Host smart-628e9c7c-5caf-4571-96c9-73f1a5f84105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702203244 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1702203244
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2160139171
Short name T663
Test name
Test status
Simulation time 17785387 ps
CPU time 1.04 seconds
Started May 19 02:27:08 PM PDT 24
Finished May 19 02:27:10 PM PDT 24
Peak memory 215024 kb
Host smart-f04fa602-88f4-4237-90ec-2b7b9ee2a133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160139171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2160139171
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2856405977
Short name T686
Test name
Test status
Simulation time 123788560 ps
CPU time 2.7 seconds
Started May 19 02:27:05 PM PDT 24
Finished May 19 02:27:08 PM PDT 24
Peak memory 219352 kb
Host smart-403a3b97-c431-4cd3-95c5-1aa4d1a33de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856405977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2856405977
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.259425670
Short name T257
Test name
Test status
Simulation time 292751351 ps
CPU time 1.54 seconds
Started May 19 02:27:11 PM PDT 24
Finished May 19 02:27:14 PM PDT 24
Peak memory 215420 kb
Host smart-149616d2-5fa8-4d54-b1ac-e7af9a0f3a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259425670 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.259425670
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4044259319
Short name T557
Test name
Test status
Simulation time 108837370 ps
CPU time 1.04 seconds
Started May 19 02:27:15 PM PDT 24
Finished May 19 02:27:17 PM PDT 24
Peak memory 206300 kb
Host smart-c91255d0-3234-413d-a399-f75bffb3a817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044259319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4044259319
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2198828839
Short name T836
Test name
Test status
Simulation time 13124407 ps
CPU time 0.9 seconds
Started May 19 02:27:11 PM PDT 24
Finished May 19 02:27:13 PM PDT 24
Peak memory 216072 kb
Host smart-14cb7cee-788a-44f7-9f14-584d7af1744c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198828839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2198828839
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3279680279
Short name T697
Test name
Test status
Simulation time 164882578 ps
CPU time 1.33 seconds
Started May 19 02:27:11 PM PDT 24
Finished May 19 02:27:14 PM PDT 24
Peak memory 216760 kb
Host smart-d630aab7-e91c-4be2-9681-8f04f508d5b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279680279 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3279680279
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4178642399
Short name T5
Test name
Test status
Simulation time 20020426 ps
CPU time 1.18 seconds
Started May 19 02:27:15 PM PDT 24
Finished May 19 02:27:18 PM PDT 24
Peak memory 219020 kb
Host smart-930823ad-713f-4e94-a308-4d028cbb1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178642399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4178642399
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2910037583
Short name T707
Test name
Test status
Simulation time 86899413 ps
CPU time 1.14 seconds
Started May 19 02:27:06 PM PDT 24
Finished May 19 02:27:09 PM PDT 24
Peak memory 216756 kb
Host smart-57ef8165-af93-4f0f-9150-1a3c4d94e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910037583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2910037583
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1195236337
Short name T796
Test name
Test status
Simulation time 31061432 ps
CPU time 0.94 seconds
Started May 19 02:27:13 PM PDT 24
Finished May 19 02:27:15 PM PDT 24
Peak memory 215248 kb
Host smart-aee02451-f475-49a6-872e-a55db2711819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195236337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1195236337
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2558022600
Short name T605
Test name
Test status
Simulation time 18351593 ps
CPU time 1.02 seconds
Started May 19 02:27:08 PM PDT 24
Finished May 19 02:27:10 PM PDT 24
Peak memory 215048 kb
Host smart-3801f857-76aa-4634-b368-df35a2f7b281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558022600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2558022600
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3799083578
Short name T844
Test name
Test status
Simulation time 423662056 ps
CPU time 4.45 seconds
Started May 19 02:27:08 PM PDT 24
Finished May 19 02:27:14 PM PDT 24
Peak memory 216732 kb
Host smart-83e0fbb5-ac64-4499-a1d3-4c02b97af512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799083578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3799083578
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.696370258
Short name T382
Test name
Test status
Simulation time 51462133734 ps
CPU time 1210.36 seconds
Started May 19 02:27:12 PM PDT 24
Finished May 19 02:47:24 PM PDT 24
Peak memory 223468 kb
Host smart-e8f45355-a568-4d64-b912-866cfff89689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696370258 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.696370258
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1270315627
Short name T263
Test name
Test status
Simulation time 43059796 ps
CPU time 1.17 seconds
Started May 19 02:27:13 PM PDT 24
Finished May 19 02:27:15 PM PDT 24
Peak memory 215396 kb
Host smart-31d35014-bc40-40af-8359-63e4fa769ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270315627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1270315627
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1150550080
Short name T384
Test name
Test status
Simulation time 15586205 ps
CPU time 0.92 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 206296 kb
Host smart-660df5c0-6830-4c79-a5d0-c39cfb1a9ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150550080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1150550080
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2873930376
Short name T619
Test name
Test status
Simulation time 31971213 ps
CPU time 0.86 seconds
Started May 19 02:27:13 PM PDT 24
Finished May 19 02:27:15 PM PDT 24
Peak memory 215720 kb
Host smart-39b6ad2a-4ebc-433f-8b5d-4dbea6f68a32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873930376 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2873930376
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1893342445
Short name T513
Test name
Test status
Simulation time 268669848 ps
CPU time 1.17 seconds
Started May 19 02:27:14 PM PDT 24
Finished May 19 02:27:16 PM PDT 24
Peak memory 216596 kb
Host smart-f2cae491-53df-4e7f-ad4f-39e16dbd5aa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893342445 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1893342445
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.844971341
Short name T96
Test name
Test status
Simulation time 48578728 ps
CPU time 0.92 seconds
Started May 19 02:27:10 PM PDT 24
Finished May 19 02:27:12 PM PDT 24
Peak memory 219228 kb
Host smart-d09641b4-0789-4c0f-b007-8f31376da926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844971341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.844971341
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2824575288
Short name T407
Test name
Test status
Simulation time 48549781 ps
CPU time 1.6 seconds
Started May 19 02:27:12 PM PDT 24
Finished May 19 02:27:15 PM PDT 24
Peak memory 215056 kb
Host smart-0aaf9d30-a1d3-4fe7-b3c8-799e960f2251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824575288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2824575288
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1932834162
Short name T68
Test name
Test status
Simulation time 49089053 ps
CPU time 0.87 seconds
Started May 19 02:27:10 PM PDT 24
Finished May 19 02:27:12 PM PDT 24
Peak memory 215176 kb
Host smart-ddd66c93-7dff-4cf6-bf09-d1bd1f912fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932834162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1932834162
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.711236075
Short name T636
Test name
Test status
Simulation time 29043318 ps
CPU time 0.94 seconds
Started May 19 02:27:10 PM PDT 24
Finished May 19 02:27:12 PM PDT 24
Peak memory 215108 kb
Host smart-c63fe70e-f5a3-4912-baf2-9291abf5dda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711236075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.711236075
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.505491339
Short name T420
Test name
Test status
Simulation time 312340503 ps
CPU time 6.18 seconds
Started May 19 02:27:12 PM PDT 24
Finished May 19 02:27:19 PM PDT 24
Peak memory 215044 kb
Host smart-46876568-f7e4-4fdd-b3e1-4bf36015300e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505491339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.505491339
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3249692580
Short name T202
Test name
Test status
Simulation time 20370526207 ps
CPU time 539.45 seconds
Started May 19 02:27:12 PM PDT 24
Finished May 19 02:36:13 PM PDT 24
Peak memory 217516 kb
Host smart-0c566611-d45e-4978-b5e5-a6be65f1957d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249692580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3249692580
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3957685032
Short name T273
Test name
Test status
Simulation time 70477578 ps
CPU time 1.07 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 215380 kb
Host smart-778e02d8-fc85-4134-a171-47a554832cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957685032 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3957685032
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.733387143
Short name T413
Test name
Test status
Simulation time 13844321 ps
CPU time 0.92 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 214504 kb
Host smart-7cd8ee09-b057-443b-a1ee-a33952ea545a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733387143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.733387143
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3709341879
Short name T174
Test name
Test status
Simulation time 16323208 ps
CPU time 0.94 seconds
Started May 19 02:27:18 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 216192 kb
Host smart-48f8c955-d7de-447e-882a-a0754b4d1733
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709341879 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3709341879
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1426140568
Short name T114
Test name
Test status
Simulation time 26334375 ps
CPU time 1.07 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 216576 kb
Host smart-c8b282f0-faf4-4074-804f-7abfcb881ec9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426140568 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1426140568
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3413854240
Short name T7
Test name
Test status
Simulation time 45619274 ps
CPU time 1.07 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 223544 kb
Host smart-4e349051-5dc3-4499-8296-452045d179d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413854240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3413854240
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3806018343
Short name T839
Test name
Test status
Simulation time 34718447 ps
CPU time 1.52 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 219560 kb
Host smart-9806ed21-daf4-4b92-a2d0-6b44c7a4980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806018343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3806018343
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3491662259
Short name T430
Test name
Test status
Simulation time 26649353 ps
CPU time 0.96 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 215136 kb
Host smart-1e671795-4231-48ec-aa5b-8a22df016ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491662259 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3491662259
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2510584059
Short name T806
Test name
Test status
Simulation time 19223749 ps
CPU time 1.03 seconds
Started May 19 02:27:16 PM PDT 24
Finished May 19 02:27:18 PM PDT 24
Peak memory 215020 kb
Host smart-7fd70bd1-4e0e-4c6c-8448-f20ecfba30a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510584059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2510584059
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.454291942
Short name T654
Test name
Test status
Simulation time 20102806 ps
CPU time 1.04 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 206704 kb
Host smart-54ab290d-57f6-4bce-9733-3803cd72fc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454291942 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.454291942
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2238980123
Short name T660
Test name
Test status
Simulation time 211398668018 ps
CPU time 1005.98 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:44:09 PM PDT 24
Peak memory 223376 kb
Host smart-201bda80-574d-46d7-8e1d-c08a47d22273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238980123 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2238980123
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1836256364
Short name T136
Test name
Test status
Simulation time 43686899 ps
CPU time 1.08 seconds
Started May 19 02:25:11 PM PDT 24
Finished May 19 02:25:12 PM PDT 24
Peak memory 215404 kb
Host smart-04adb757-510d-4845-b4fd-96f185eeef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836256364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1836256364
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2000518394
Short name T753
Test name
Test status
Simulation time 27908326 ps
CPU time 0.95 seconds
Started May 19 02:25:12 PM PDT 24
Finished May 19 02:25:14 PM PDT 24
Peak memory 214508 kb
Host smart-a6ea9ef2-41d5-443d-af93-c07f8d149e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000518394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2000518394
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3117112749
Short name T531
Test name
Test status
Simulation time 27508008 ps
CPU time 0.87 seconds
Started May 19 02:25:12 PM PDT 24
Finished May 19 02:25:13 PM PDT 24
Peak memory 215184 kb
Host smart-6f210511-deec-4986-a955-025c9134b174
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117112749 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3117112749
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1719884537
Short name T113
Test name
Test status
Simulation time 123261714 ps
CPU time 1.15 seconds
Started May 19 02:25:11 PM PDT 24
Finished May 19 02:25:13 PM PDT 24
Peak memory 219444 kb
Host smart-b8ac75fb-e4de-4262-bf1a-1bef942fbb67
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719884537 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1719884537
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2543606490
Short name T118
Test name
Test status
Simulation time 34763476 ps
CPU time 1.16 seconds
Started May 19 02:25:12 PM PDT 24
Finished May 19 02:25:14 PM PDT 24
Peak memory 229216 kb
Host smart-75b64c6d-92f0-4e0c-8628-2f1c96f58b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543606490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2543606490
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.724130480
Short name T442
Test name
Test status
Simulation time 116886774 ps
CPU time 1.1 seconds
Started May 19 02:25:11 PM PDT 24
Finished May 19 02:25:12 PM PDT 24
Peak memory 216760 kb
Host smart-570a4376-ad41-4187-8a2a-db96e0f60617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724130480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.724130480
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3781754383
Short name T154
Test name
Test status
Simulation time 23707407 ps
CPU time 1.11 seconds
Started May 19 02:25:12 PM PDT 24
Finished May 19 02:25:14 PM PDT 24
Peak memory 214924 kb
Host smart-6cccd986-c784-45a2-9d88-ecc0955ad0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781754383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3781754383
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1623626531
Short name T269
Test name
Test status
Simulation time 16278852 ps
CPU time 0.95 seconds
Started May 19 02:25:09 PM PDT 24
Finished May 19 02:25:10 PM PDT 24
Peak memory 206836 kb
Host smart-ac6f6843-054d-4bd8-aee1-a5448921eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623626531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1623626531
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.839991787
Short name T588
Test name
Test status
Simulation time 44109330 ps
CPU time 0.95 seconds
Started May 19 02:25:06 PM PDT 24
Finished May 19 02:25:08 PM PDT 24
Peak memory 215020 kb
Host smart-200b2cfd-9679-4384-a3ea-e03945c7e5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839991787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.839991787
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1121522309
Short name T290
Test name
Test status
Simulation time 382365705 ps
CPU time 4.33 seconds
Started May 19 02:25:12 PM PDT 24
Finished May 19 02:25:17 PM PDT 24
Peak memory 216680 kb
Host smart-84cd8b85-81b1-49b0-87be-718645d404ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121522309 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1121522309
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3800698621
Short name T41
Test name
Test status
Simulation time 156023601663 ps
CPU time 1442.51 seconds
Started May 19 02:25:10 PM PDT 24
Finished May 19 02:49:13 PM PDT 24
Peak memory 223860 kb
Host smart-6a692ad9-3f27-4264-b831-3b96f0713c29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800698621 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3800698621
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3279849732
Short name T108
Test name
Test status
Simulation time 25134903 ps
CPU time 1.11 seconds
Started May 19 02:27:16 PM PDT 24
Finished May 19 02:27:19 PM PDT 24
Peak memory 229072 kb
Host smart-5dfb2ac6-ba67-4f1b-bade-db0063326134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279849732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3279849732
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3938684942
Short name T685
Test name
Test status
Simulation time 619391457 ps
CPU time 4.13 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:23 PM PDT 24
Peak memory 219776 kb
Host smart-f044674b-0387-46b7-baf6-8dec9b801a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938684942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3938684942
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2421034644
Short name T129
Test name
Test status
Simulation time 18527196 ps
CPU time 1.14 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 223496 kb
Host smart-49e79f86-de2f-44e2-b00f-9d8bc3e50d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421034644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2421034644
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4082636128
Short name T678
Test name
Test status
Simulation time 63692909 ps
CPU time 1.43 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:26 PM PDT 24
Peak memory 218316 kb
Host smart-25ede0e7-3670-40c5-a48e-61853225f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082636128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4082636128
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2156283930
Short name T789
Test name
Test status
Simulation time 45012170 ps
CPU time 1.31 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 225008 kb
Host smart-5bf182a2-fe69-49af-8add-32a678c58c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156283930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2156283930
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3838974675
Short name T493
Test name
Test status
Simulation time 109520120 ps
CPU time 1.13 seconds
Started May 19 02:27:17 PM PDT 24
Finished May 19 02:27:20 PM PDT 24
Peak memory 216820 kb
Host smart-13276301-c687-4f55-ac91-807ce51a4316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838974675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3838974675
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.718978566
Short name T98
Test name
Test status
Simulation time 60220313 ps
CPU time 1.11 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 229164 kb
Host smart-c380a2df-054a-40c4-92d4-44802000321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718978566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.718978566
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.645572228
Short name T666
Test name
Test status
Simulation time 31152173 ps
CPU time 1.33 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 216892 kb
Host smart-cdae0486-80f9-4e99-b1dd-3885c05be7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645572228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.645572228
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.474274432
Short name T635
Test name
Test status
Simulation time 22793288 ps
CPU time 1.06 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:25 PM PDT 24
Peak memory 223552 kb
Host smart-5ff6e9fb-1192-4446-bb61-a57807139dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474274432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.474274432
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3346667709
Short name T631
Test name
Test status
Simulation time 44469876 ps
CPU time 1.48 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:26 PM PDT 24
Peak memory 217948 kb
Host smart-963b159e-20b2-4deb-b24f-2195eb149d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346667709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3346667709
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3323526229
Short name T134
Test name
Test status
Simulation time 46111523 ps
CPU time 1.18 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 225240 kb
Host smart-4fdaec26-3d97-42e8-b469-b5affd81f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323526229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3323526229
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3144305577
Short name T328
Test name
Test status
Simulation time 46586376 ps
CPU time 1.74 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:26 PM PDT 24
Peak memory 217828 kb
Host smart-b4a7a018-397f-444f-a188-22336d332f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144305577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3144305577
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2827929007
Short name T146
Test name
Test status
Simulation time 34167642 ps
CPU time 0.89 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:32 PM PDT 24
Peak memory 217980 kb
Host smart-aab445e7-8839-4be4-9f56-67abd99e5131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827929007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2827929007
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3460711307
Short name T643
Test name
Test status
Simulation time 39060370 ps
CPU time 1.55 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:26 PM PDT 24
Peak memory 219388 kb
Host smart-91b08ff7-648a-4e50-b23e-959c3565d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460711307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3460711307
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2922240711
Short name T821
Test name
Test status
Simulation time 46680025 ps
CPU time 1.03 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:35 PM PDT 24
Peak memory 219716 kb
Host smart-c5fd6cd7-e782-4ade-88d8-aee9c723cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922240711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2922240711
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.338255721
Short name T572
Test name
Test status
Simulation time 28644508 ps
CPU time 1.35 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 218992 kb
Host smart-e23b77e4-8e59-4f8c-89af-50a27b2a2e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338255721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.338255721
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.318165378
Short name T386
Test name
Test status
Simulation time 30474679 ps
CPU time 1.29 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:37 PM PDT 24
Peak memory 225216 kb
Host smart-d3d30d0d-9b37-4ebf-95c5-9f0c13e423e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318165378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.318165378
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.277302210
Short name T344
Test name
Test status
Simulation time 56768702 ps
CPU time 1.23 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:25 PM PDT 24
Peak memory 218088 kb
Host smart-d1c5a230-4825-4d98-a96a-f86c6ccdd0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277302210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.277302210
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1232490147
Short name T829
Test name
Test status
Simulation time 43579885 ps
CPU time 1.16 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:32 PM PDT 24
Peak memory 220220 kb
Host smart-4abb0206-e0e1-469f-aff6-3f854c4215a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232490147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1232490147
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2721540388
Short name T585
Test name
Test status
Simulation time 42193342 ps
CPU time 1.33 seconds
Started May 19 02:27:21 PM PDT 24
Finished May 19 02:27:23 PM PDT 24
Peak memory 218352 kb
Host smart-c172d9e9-07a0-4e9a-b772-a225b74d53e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721540388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2721540388
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.1244460894
Short name T708
Test name
Test status
Simulation time 14359208 ps
CPU time 0.93 seconds
Started May 19 02:25:18 PM PDT 24
Finished May 19 02:25:20 PM PDT 24
Peak memory 206248 kb
Host smart-9fab6d73-3c3a-43df-a3c3-43589ca99660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244460894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1244460894
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.4060979412
Short name T765
Test name
Test status
Simulation time 12551939 ps
CPU time 0.92 seconds
Started May 19 02:25:18 PM PDT 24
Finished May 19 02:25:19 PM PDT 24
Peak memory 216184 kb
Host smart-48a4195f-5144-4dc0-b45c-80d15c47f773
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060979412 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4060979412
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.751816334
Short name T120
Test name
Test status
Simulation time 278023717 ps
CPU time 1.15 seconds
Started May 19 02:25:15 PM PDT 24
Finished May 19 02:25:17 PM PDT 24
Peak memory 217040 kb
Host smart-ab9373a9-95fd-44d9-a65a-40be2b3023af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751816334 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.751816334
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.62942903
Short name T762
Test name
Test status
Simulation time 34740576 ps
CPU time 1.26 seconds
Started May 19 02:25:17 PM PDT 24
Finished May 19 02:25:19 PM PDT 24
Peak memory 229060 kb
Host smart-6ae3b3c0-d9e5-4356-82de-2c8f7c4a7646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62942903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.62942903
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.9399204
Short name T421
Test name
Test status
Simulation time 65759192 ps
CPU time 1.23 seconds
Started May 19 02:25:17 PM PDT 24
Finished May 19 02:25:19 PM PDT 24
Peak memory 218012 kb
Host smart-08fdb953-fc8b-4b75-8041-bf341f5c1ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9399204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.9399204
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1218173045
Short name T416
Test name
Test status
Simulation time 49890858 ps
CPU time 0.92 seconds
Started May 19 02:25:17 PM PDT 24
Finished May 19 02:25:19 PM PDT 24
Peak memory 215192 kb
Host smart-a6340ed4-825a-4fbb-96a2-46fbdacb9da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218173045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1218173045
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1211591036
Short name T266
Test name
Test status
Simulation time 15666548 ps
CPU time 1.01 seconds
Started May 19 02:25:16 PM PDT 24
Finished May 19 02:25:18 PM PDT 24
Peak memory 207072 kb
Host smart-79908397-0e6d-4668-b23a-321b183e94d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211591036 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1211591036
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2659923374
Short name T555
Test name
Test status
Simulation time 28560526 ps
CPU time 0.95 seconds
Started May 19 02:25:11 PM PDT 24
Finished May 19 02:25:13 PM PDT 24
Peak memory 215000 kb
Host smart-8a96be7f-c54c-41e6-84e6-6ec9cd2760f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659923374 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2659923374
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2059149292
Short name T216
Test name
Test status
Simulation time 314279942 ps
CPU time 3.38 seconds
Started May 19 02:25:18 PM PDT 24
Finished May 19 02:25:22 PM PDT 24
Peak memory 216492 kb
Host smart-1c3f6de2-2bdd-4744-a42e-17d69aeba42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059149292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2059149292
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1827304561
Short name T286
Test name
Test status
Simulation time 98726099540 ps
CPU time 1309.35 seconds
Started May 19 02:25:17 PM PDT 24
Finished May 19 02:47:07 PM PDT 24
Peak memory 225044 kb
Host smart-589a4c29-cfe0-4ab6-aca1-61191d732539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827304561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1827304561
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_genbits.3869008401
Short name T409
Test name
Test status
Simulation time 75407342 ps
CPU time 1.02 seconds
Started May 19 02:27:22 PM PDT 24
Finished May 19 02:27:24 PM PDT 24
Peak memory 219108 kb
Host smart-3d175b32-b120-463a-adb8-3836bb87a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869008401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3869008401
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1257601813
Short name T618
Test name
Test status
Simulation time 31173504 ps
CPU time 0.91 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:35 PM PDT 24
Peak memory 218396 kb
Host smart-93d28e89-34d0-4f0d-ba2a-ce472932527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257601813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1257601813
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1733301158
Short name T21
Test name
Test status
Simulation time 55808931 ps
CPU time 1.22 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 218244 kb
Host smart-1b9100ab-fd73-4f69-b21b-000b65d0df35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733301158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1733301158
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1121192471
Short name T627
Test name
Test status
Simulation time 17899343 ps
CPU time 1.17 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:37 PM PDT 24
Peak memory 232232 kb
Host smart-2fca8697-87d6-4937-9573-1bd0a27ff914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121192471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1121192471
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2952438981
Short name T549
Test name
Test status
Simulation time 110587570 ps
CPU time 1.43 seconds
Started May 19 02:27:23 PM PDT 24
Finished May 19 02:27:26 PM PDT 24
Peak memory 218288 kb
Host smart-a9c0accf-57c8-43bc-b36a-a43260a062bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952438981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2952438981
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1683775886
Short name T155
Test name
Test status
Simulation time 27679629 ps
CPU time 0.96 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:37 PM PDT 24
Peak memory 219132 kb
Host smart-d682546d-43a2-4cb3-8b5f-35766a9d7691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683775886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1683775886
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.250312231
Short name T503
Test name
Test status
Simulation time 107832447 ps
CPU time 1.12 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:35 PM PDT 24
Peak memory 217140 kb
Host smart-2ccf3794-34ba-4787-83ba-87194c09c7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250312231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.250312231
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2659840890
Short name T144
Test name
Test status
Simulation time 26699270 ps
CPU time 1.08 seconds
Started May 19 02:27:21 PM PDT 24
Finished May 19 02:27:23 PM PDT 24
Peak memory 223476 kb
Host smart-a2e7a30f-ae29-4139-81a5-6726e9d9bd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659840890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2659840890
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2240867234
Short name T637
Test name
Test status
Simulation time 89612479 ps
CPU time 1.39 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 217844 kb
Host smart-8fe510f2-1c90-4cf9-83e2-a5ad21c7ef3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240867234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2240867234
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2128040100
Short name T104
Test name
Test status
Simulation time 36167287 ps
CPU time 1.07 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 219168 kb
Host smart-ea510bf6-c540-4bf3-b786-919613c5ea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128040100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2128040100
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3209630959
Short name T443
Test name
Test status
Simulation time 46355144 ps
CPU time 1.54 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:33 PM PDT 24
Peak memory 218116 kb
Host smart-a3b6142d-9cd0-41a0-b2c3-7910444923a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209630959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3209630959
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2063633503
Short name T610
Test name
Test status
Simulation time 19331284 ps
CPU time 1.13 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 218088 kb
Host smart-32bd85b7-701b-4d0b-9a37-be78543dcc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063633503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2063633503
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3801007410
Short name T645
Test name
Test status
Simulation time 33950095 ps
CPU time 1.41 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 216860 kb
Host smart-7cc8c828-f445-4b61-a6e5-5301d1842630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801007410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3801007410
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.627041647
Short name T698
Test name
Test status
Simulation time 28291020 ps
CPU time 1.27 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 219364 kb
Host smart-b6b7d1f5-6f4f-4870-98b4-f8e1478f4521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627041647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.627041647
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3306964011
Short name T512
Test name
Test status
Simulation time 38090776 ps
CPU time 1.12 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 218832 kb
Host smart-1f584d29-7eaa-4fbb-980d-a06a6f84f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306964011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3306964011
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.360233653
Short name T103
Test name
Test status
Simulation time 48577286 ps
CPU time 1.01 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 219248 kb
Host smart-17343829-5abe-401a-be37-d770692e2d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360233653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.360233653
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2372087887
Short name T798
Test name
Test status
Simulation time 45383783 ps
CPU time 1.2 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 216644 kb
Host smart-3bbb32c8-b13b-47b1-8d5b-7c32c1b30636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372087887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2372087887
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1505092437
Short name T1
Test name
Test status
Simulation time 24599421 ps
CPU time 0.98 seconds
Started May 19 02:27:27 PM PDT 24
Finished May 19 02:27:29 PM PDT 24
Peak memory 218348 kb
Host smart-6d1d26e3-8738-4fc7-8045-86a52ba06519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505092437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1505092437
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.234075861
Short name T63
Test name
Test status
Simulation time 55353565 ps
CPU time 1.29 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 218132 kb
Host smart-00c8fed7-1126-4984-b989-0396127fb745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234075861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.234075861
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.61829362
Short name T152
Test name
Test status
Simulation time 23367503 ps
CPU time 1.2 seconds
Started May 19 02:25:26 PM PDT 24
Finished May 19 02:25:28 PM PDT 24
Peak memory 215392 kb
Host smart-b019b67c-7aef-4e83-bac7-2a345eed34b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61829362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.61829362
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.419251354
Short name T396
Test name
Test status
Simulation time 27716636 ps
CPU time 1.01 seconds
Started May 19 02:25:26 PM PDT 24
Finished May 19 02:25:28 PM PDT 24
Peak memory 206364 kb
Host smart-4bfac90c-a522-4491-b00b-4dc03776c263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419251354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.419251354
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3943881500
Short name T192
Test name
Test status
Simulation time 13548960 ps
CPU time 0.91 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:24 PM PDT 24
Peak memory 215360 kb
Host smart-28cd4a53-d8a7-44a3-bd21-1714825c65ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943881500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3943881500
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4225259520
Short name T521
Test name
Test status
Simulation time 43138019 ps
CPU time 1.12 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:25 PM PDT 24
Peak memory 218084 kb
Host smart-5c329a25-3747-419e-b557-4d1d7cb399c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225259520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4225259520
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1577300744
Short name T126
Test name
Test status
Simulation time 33130086 ps
CPU time 0.95 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:25 PM PDT 24
Peak memory 223264 kb
Host smart-b946350a-f652-4386-b845-c53074bd686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577300744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1577300744
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3363622908
Short name T467
Test name
Test status
Simulation time 36295152 ps
CPU time 1.26 seconds
Started May 19 02:25:25 PM PDT 24
Finished May 19 02:25:27 PM PDT 24
Peak memory 219292 kb
Host smart-d49b931b-140a-4626-a31b-86769dcfa36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363622908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3363622908
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1081974097
Short name T507
Test name
Test status
Simulation time 22627395 ps
CPU time 0.93 seconds
Started May 19 02:25:25 PM PDT 24
Finished May 19 02:25:27 PM PDT 24
Peak memory 215492 kb
Host smart-a300df5d-599a-4edf-aa61-c4c5ee634310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081974097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1081974097
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3512429381
Short name T261
Test name
Test status
Simulation time 42589519 ps
CPU time 0.9 seconds
Started May 19 02:25:26 PM PDT 24
Finished May 19 02:25:28 PM PDT 24
Peak memory 206808 kb
Host smart-cd3a0587-35a4-4de9-af8c-be9619b446dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512429381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3512429381
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3352393366
Short name T321
Test name
Test status
Simulation time 16537758 ps
CPU time 1.01 seconds
Started May 19 02:25:16 PM PDT 24
Finished May 19 02:25:17 PM PDT 24
Peak memory 215004 kb
Host smart-346ca1c0-233d-4429-b466-179392badb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352393366 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3352393366
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1479303037
Short name T218
Test name
Test status
Simulation time 341331672 ps
CPU time 6.3 seconds
Started May 19 02:25:25 PM PDT 24
Finished May 19 02:25:33 PM PDT 24
Peak memory 216604 kb
Host smart-1f42cafa-9df8-46d1-b421-95b40b1d00a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479303037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1479303037
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1834891984
Short name T567
Test name
Test status
Simulation time 139639278449 ps
CPU time 456.68 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:33:00 PM PDT 24
Peak memory 219300 kb
Host smart-b2a6379d-a52f-45ab-8aac-1f6080a54e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834891984 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1834891984
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.584201124
Short name T354
Test name
Test status
Simulation time 32342148 ps
CPU time 0.87 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 217916 kb
Host smart-700ef1d4-c0c3-4794-8d61-4e11c7deb5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584201124 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.584201124
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1889178809
Short name T375
Test name
Test status
Simulation time 48151739 ps
CPU time 1.79 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:35 PM PDT 24
Peak memory 216836 kb
Host smart-b41ef531-8a39-443c-960f-5fedfdfe657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889178809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1889178809
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2650565462
Short name T179
Test name
Test status
Simulation time 24551791 ps
CPU time 0.99 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:32 PM PDT 24
Peak memory 219308 kb
Host smart-019ee177-e9f4-4c8a-b16e-aa3de17ecf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650565462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2650565462
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1550095799
Short name T405
Test name
Test status
Simulation time 87716618 ps
CPU time 1.11 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 216780 kb
Host smart-378e7904-0240-4d77-9b63-061e8e4aec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550095799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1550095799
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1309266185
Short name T189
Test name
Test status
Simulation time 38415669 ps
CPU time 1.12 seconds
Started May 19 02:27:31 PM PDT 24
Finished May 19 02:27:33 PM PDT 24
Peak memory 219992 kb
Host smart-a6eb85a5-19f8-4b76-ba40-8eafd9e6cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309266185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1309266185
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3774351748
Short name T486
Test name
Test status
Simulation time 40909934 ps
CPU time 1.66 seconds
Started May 19 02:27:31 PM PDT 24
Finished May 19 02:27:34 PM PDT 24
Peak memory 217960 kb
Host smart-3375c237-b32c-4be5-bc43-1e5d7e929178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774351748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3774351748
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.207508043
Short name T95
Test name
Test status
Simulation time 50575602 ps
CPU time 1.01 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 219132 kb
Host smart-49514a81-943a-47f5-aa56-404183b2e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207508043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.207508043
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2412955117
Short name T342
Test name
Test status
Simulation time 43768212 ps
CPU time 1.04 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:30 PM PDT 24
Peak memory 215064 kb
Host smart-00d2abe1-72cf-4de2-8ee1-f984228987f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412955117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2412955117
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4074793382
Short name T629
Test name
Test status
Simulation time 24738208 ps
CPU time 1.19 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 220340 kb
Host smart-15e98373-5f5a-48d6-87ed-6e5ee62d321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074793382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4074793382
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2908172922
Short name T376
Test name
Test status
Simulation time 76130829 ps
CPU time 1.21 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:34 PM PDT 24
Peak memory 216656 kb
Host smart-17174fc3-3e9b-4fea-b81b-aa84bb76d94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908172922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2908172922
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1529785804
Short name T712
Test name
Test status
Simulation time 41958772 ps
CPU time 1.03 seconds
Started May 19 02:27:32 PM PDT 24
Finished May 19 02:27:34 PM PDT 24
Peak memory 223308 kb
Host smart-bdf5d9da-386f-40ac-917e-9f59b42bb7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529785804 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1529785804
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.931767185
Short name T213
Test name
Test status
Simulation time 63346866 ps
CPU time 1.42 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:32 PM PDT 24
Peak memory 215140 kb
Host smart-f6a20e03-5deb-4868-b394-806e47085a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931767185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.931767185
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2097003683
Short name T115
Test name
Test status
Simulation time 31980373 ps
CPU time 1.05 seconds
Started May 19 02:27:30 PM PDT 24
Finished May 19 02:27:32 PM PDT 24
Peak memory 223616 kb
Host smart-0c338304-c009-4f0a-95a1-6baccb59c574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097003683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2097003683
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2257111476
Short name T767
Test name
Test status
Simulation time 29911736 ps
CPU time 1.28 seconds
Started May 19 02:27:37 PM PDT 24
Finished May 19 02:27:41 PM PDT 24
Peak memory 218020 kb
Host smart-4b23031b-62c4-4608-9d7f-0150b79820bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257111476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2257111476
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2700974153
Short name T177
Test name
Test status
Simulation time 190823796 ps
CPU time 1 seconds
Started May 19 02:27:28 PM PDT 24
Finished May 19 02:27:30 PM PDT 24
Peak memory 220340 kb
Host smart-47459ab1-fffc-4812-938b-ee744e73651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700974153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2700974153
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3144505979
Short name T463
Test name
Test status
Simulation time 42483885 ps
CPU time 1.78 seconds
Started May 19 02:27:28 PM PDT 24
Finished May 19 02:27:31 PM PDT 24
Peak memory 218136 kb
Host smart-1ef4d79c-fda1-4b2d-b490-0e5f99d173f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144505979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3144505979
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2010387620
Short name T110
Test name
Test status
Simulation time 46759858 ps
CPU time 1.21 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 229176 kb
Host smart-d9242a80-56cb-4f52-b763-ec557d22f69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010387620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2010387620
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.4098588716
Short name T310
Test name
Test status
Simulation time 277320361 ps
CPU time 3.71 seconds
Started May 19 02:27:31 PM PDT 24
Finished May 19 02:27:36 PM PDT 24
Peak memory 219456 kb
Host smart-7448af4b-610a-4005-990b-70b48fc1578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098588716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.4098588716
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1438129985
Short name T147
Test name
Test status
Simulation time 23054735 ps
CPU time 1.07 seconds
Started May 19 02:27:28 PM PDT 24
Finished May 19 02:27:29 PM PDT 24
Peak memory 223500 kb
Host smart-f38a3f67-dacb-4ec8-a3b1-5d4f9fdfb0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438129985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1438129985
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2278161516
Short name T377
Test name
Test status
Simulation time 89085006 ps
CPU time 1.23 seconds
Started May 19 02:27:29 PM PDT 24
Finished May 19 02:27:30 PM PDT 24
Peak memory 219096 kb
Host smart-7f4997e3-29dc-4a65-8577-6e61391de3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278161516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2278161516
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1238285749
Short name T193
Test name
Test status
Simulation time 49098202 ps
CPU time 1.25 seconds
Started May 19 02:25:27 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 215588 kb
Host smart-54dd0dd4-6460-460e-a344-6e945fa8224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238285749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1238285749
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.277298820
Short name T325
Test name
Test status
Simulation time 37451615 ps
CPU time 0.83 seconds
Started May 19 02:25:26 PM PDT 24
Finished May 19 02:25:28 PM PDT 24
Peak memory 214548 kb
Host smart-063d2423-3d47-4918-92ef-74657cf10eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277298820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.277298820
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4160665533
Short name T143
Test name
Test status
Simulation time 17556705 ps
CPU time 0.84 seconds
Started May 19 02:25:25 PM PDT 24
Finished May 19 02:25:27 PM PDT 24
Peak memory 216040 kb
Host smart-46e7d5c8-c3a5-4e4d-a8b0-ea54fa8d417d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160665533 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4160665533
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2900693686
Short name T750
Test name
Test status
Simulation time 29442704 ps
CPU time 1.16 seconds
Started May 19 02:25:27 PM PDT 24
Finished May 19 02:25:29 PM PDT 24
Peak memory 216724 kb
Host smart-fa2c2816-3da8-447d-95d5-a75b410a0d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900693686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2900693686
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1173965864
Short name T102
Test name
Test status
Simulation time 32849180 ps
CPU time 1.12 seconds
Started May 19 02:25:22 PM PDT 24
Finished May 19 02:25:24 PM PDT 24
Peak memory 219152 kb
Host smart-9c178199-75d6-40f0-bbd9-e56ed3bec8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173965864 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1173965864
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2174944142
Short name T496
Test name
Test status
Simulation time 33298121 ps
CPU time 1.29 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:26 PM PDT 24
Peak memory 216860 kb
Host smart-00772766-cc34-4139-8ed7-efc6783a5b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174944142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2174944142
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3019898999
Short name T466
Test name
Test status
Simulation time 42900037 ps
CPU time 0.98 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:25 PM PDT 24
Peak memory 223440 kb
Host smart-928cff3c-3cf9-4804-be98-c638103f6bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019898999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3019898999
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.458642393
Short name T26
Test name
Test status
Simulation time 18220815 ps
CPU time 1.04 seconds
Started May 19 02:25:24 PM PDT 24
Finished May 19 02:25:26 PM PDT 24
Peak memory 206840 kb
Host smart-3d117b47-c505-4ef3-86dc-ab4060662674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458642393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.458642393
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2750214782
Short name T782
Test name
Test status
Simulation time 134545350 ps
CPU time 0.92 seconds
Started May 19 02:25:22 PM PDT 24
Finished May 19 02:25:24 PM PDT 24
Peak memory 215028 kb
Host smart-058df1c1-190d-48b2-a6d4-2bda7c869b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750214782 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2750214782
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.370448937
Short name T832
Test name
Test status
Simulation time 531276145 ps
CPU time 6.04 seconds
Started May 19 02:25:24 PM PDT 24
Finished May 19 02:25:31 PM PDT 24
Peak memory 216768 kb
Host smart-64b8f849-8bb4-42a2-9d1c-f0be9e660faa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370448937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.370448937
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1436266950
Short name T199
Test name
Test status
Simulation time 246399342091 ps
CPU time 1420.65 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:49:05 PM PDT 24
Peak memory 223552 kb
Host smart-b4349158-22ac-4161-bb7a-e6c99042cc33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436266950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1436266950
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2155740128
Short name T596
Test name
Test status
Simulation time 24062559 ps
CPU time 0.92 seconds
Started May 19 02:27:31 PM PDT 24
Finished May 19 02:27:33 PM PDT 24
Peak memory 218276 kb
Host smart-5cde05f7-3a41-42e7-851c-e01e7f9eaf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155740128 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2155740128
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1900715396
Short name T349
Test name
Test status
Simulation time 81944550 ps
CPU time 1.16 seconds
Started May 19 02:27:37 PM PDT 24
Finished May 19 02:27:41 PM PDT 24
Peak memory 216720 kb
Host smart-f622c42b-91cf-4faa-b8b2-1da49d0e1d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900715396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1900715396
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3814207663
Short name T581
Test name
Test status
Simulation time 37262528 ps
CPU time 1.16 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:51 PM PDT 24
Peak memory 229308 kb
Host smart-b84a1112-acc2-443a-9ea4-003e1d92d034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814207663 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3814207663
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1463067618
Short name T591
Test name
Test status
Simulation time 83876578 ps
CPU time 2.96 seconds
Started May 19 02:27:31 PM PDT 24
Finished May 19 02:27:35 PM PDT 24
Peak memory 218560 kb
Host smart-6bd53da5-6586-4db7-9d81-809b6cee25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463067618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1463067618
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3911597678
Short name T145
Test name
Test status
Simulation time 19258668 ps
CPU time 1.12 seconds
Started May 19 02:27:35 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 218100 kb
Host smart-5f922fff-13c7-4073-8b34-2ddc06ac8383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911597678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3911597678
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3561817220
Short name T667
Test name
Test status
Simulation time 70133936 ps
CPU time 1.42 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:37 PM PDT 24
Peak memory 219236 kb
Host smart-0744c518-a2ed-4082-810d-1258ad3fcfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561817220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3561817220
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1014711068
Short name T652
Test name
Test status
Simulation time 36936536 ps
CPU time 1.47 seconds
Started May 19 02:27:38 PM PDT 24
Finished May 19 02:27:42 PM PDT 24
Peak memory 225004 kb
Host smart-ff796a7e-e091-4c34-9a59-8791cdb9795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014711068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1014711068
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.49304129
Short name T846
Test name
Test status
Simulation time 60455795 ps
CPU time 1.03 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 216840 kb
Host smart-f2513d6d-a9b2-4e0c-8947-bd95f9931b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49304129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.49304129
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.483625732
Short name T564
Test name
Test status
Simulation time 32305913 ps
CPU time 1.17 seconds
Started May 19 02:27:38 PM PDT 24
Finished May 19 02:27:41 PM PDT 24
Peak memory 223488 kb
Host smart-aae514ef-ae93-4f15-a284-891e9e7081ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483625732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.483625732
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3213029922
Short name T62
Test name
Test status
Simulation time 82155999 ps
CPU time 1.33 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 218104 kb
Host smart-84b39665-673e-4128-af08-7090773d43f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213029922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3213029922
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3274059991
Short name T112
Test name
Test status
Simulation time 23792401 ps
CPU time 0.95 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 219192 kb
Host smart-cb2ecd08-8197-4da3-8355-bf3b62797d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274059991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3274059991
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1971007386
Short name T617
Test name
Test status
Simulation time 45282472 ps
CPU time 1.44 seconds
Started May 19 02:27:35 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 217876 kb
Host smart-8bd692cd-1f11-4b76-9f6b-fcecb3f5e3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971007386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1971007386
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2285374627
Short name T140
Test name
Test status
Simulation time 18119538 ps
CPU time 1.03 seconds
Started May 19 02:27:37 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 217804 kb
Host smart-26b0e499-07b9-4fbb-a49c-c496e92e4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285374627 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2285374627
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3019513337
Short name T734
Test name
Test status
Simulation time 49838743 ps
CPU time 1.68 seconds
Started May 19 02:27:35 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 219120 kb
Host smart-fd91c303-b4df-4c35-86af-6763c55225f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019513337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3019513337
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3095298156
Short name T592
Test name
Test status
Simulation time 48679622 ps
CPU time 0.85 seconds
Started May 19 02:27:37 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 218132 kb
Host smart-5f4b7aa0-aa6e-4ac9-9986-5fc93c6e7414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095298156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3095298156
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3477220212
Short name T365
Test name
Test status
Simulation time 50750673 ps
CPU time 1.55 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 218020 kb
Host smart-5ab5ea16-53a8-4712-aa57-3368459dfe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477220212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3477220212
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.4174896816
Short name T141
Test name
Test status
Simulation time 33622339 ps
CPU time 0.99 seconds
Started May 19 02:27:35 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 223296 kb
Host smart-d4933c92-194c-47a8-b239-2be007d6e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174896816 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4174896816
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/89.edn_err.103726163
Short name T59
Test name
Test status
Simulation time 44386008 ps
CPU time 1.04 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 229192 kb
Host smart-8fcfae90-8429-4f55-9322-51c209fe3c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103726163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.103726163
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1214870705
Short name T542
Test name
Test status
Simulation time 54662097 ps
CPU time 1.5 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 216720 kb
Host smart-85973638-ae0b-4404-a981-249745539c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214870705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1214870705
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2432845501
Short name T258
Test name
Test status
Simulation time 23422958 ps
CPU time 1.14 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:31 PM PDT 24
Peak memory 215504 kb
Host smart-6676665f-dd9b-4220-b2e6-f0ee158868fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432845501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2432845501
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.353349289
Short name T446
Test name
Test status
Simulation time 40100792 ps
CPU time 0.9 seconds
Started May 19 02:25:27 PM PDT 24
Finished May 19 02:25:29 PM PDT 24
Peak memory 214516 kb
Host smart-1adb0100-9080-4129-94e4-04c56ccbb223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353349289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.353349289
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4058942044
Short name T180
Test name
Test status
Simulation time 33931883 ps
CPU time 0.8 seconds
Started May 19 02:25:30 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 216164 kb
Host smart-b66c2143-476b-41a9-a758-7604305cb06b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058942044 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4058942044
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1004315452
Short name T9
Test name
Test status
Simulation time 27991091 ps
CPU time 1.12 seconds
Started May 19 02:25:29 PM PDT 24
Finished May 19 02:25:32 PM PDT 24
Peak memory 217796 kb
Host smart-ca5118f7-fec9-49b5-960f-8e89aca23fe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004315452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1004315452
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3338027946
Short name T56
Test name
Test status
Simulation time 28702772 ps
CPU time 1.1 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 229192 kb
Host smart-7af29166-c42b-449e-b7f3-2d77f7036a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338027946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3338027946
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3965972755
Short name T163
Test name
Test status
Simulation time 103409812 ps
CPU time 1.27 seconds
Started May 19 02:25:27 PM PDT 24
Finished May 19 02:25:30 PM PDT 24
Peak memory 216780 kb
Host smart-3cd1e09b-6ad6-4a94-84ab-6238df9e0f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965972755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3965972755
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1381914928
Short name T732
Test name
Test status
Simulation time 22175494 ps
CPU time 0.92 seconds
Started May 19 02:25:27 PM PDT 24
Finished May 19 02:25:29 PM PDT 24
Peak memory 215484 kb
Host smart-8998d0da-ef25-4278-ab78-2d6afe0ebaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381914928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1381914928
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.71580098
Short name T262
Test name
Test status
Simulation time 23296890 ps
CPU time 0.89 seconds
Started May 19 02:25:26 PM PDT 24
Finished May 19 02:25:28 PM PDT 24
Peak memory 206808 kb
Host smart-dceb9b2e-6797-4695-be0e-f20243ec5bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71580098 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.71580098
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2675045785
Short name T713
Test name
Test status
Simulation time 14251730 ps
CPU time 0.94 seconds
Started May 19 02:25:23 PM PDT 24
Finished May 19 02:25:25 PM PDT 24
Peak memory 215032 kb
Host smart-6a508b91-2bba-4ee5-a61a-fe8d8af9aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675045785 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2675045785
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.452584484
Short name T505
Test name
Test status
Simulation time 594317297 ps
CPU time 2.08 seconds
Started May 19 02:25:24 PM PDT 24
Finished May 19 02:25:27 PM PDT 24
Peak memory 215040 kb
Host smart-5977b03e-8443-4f53-a532-966bc0da3e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452584484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.452584484
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2671241818
Short name T816
Test name
Test status
Simulation time 26676535863 ps
CPU time 410.73 seconds
Started May 19 02:25:28 PM PDT 24
Finished May 19 02:32:20 PM PDT 24
Peak memory 218020 kb
Host smart-095a57ca-ef74-4a64-bbaa-4c44b1198f88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671241818 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2671241818
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_genbits.554288926
Short name T455
Test name
Test status
Simulation time 41393057 ps
CPU time 1.35 seconds
Started May 19 02:27:34 PM PDT 24
Finished May 19 02:27:38 PM PDT 24
Peak memory 217940 kb
Host smart-01f5345c-44e9-4b04-b9d9-fba43052ad41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554288926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.554288926
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3953778468
Short name T479
Test name
Test status
Simulation time 48360807 ps
CPU time 0.82 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 218140 kb
Host smart-5c53a5e9-8a30-4a1c-b7b4-bc8e2d4683c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953778468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3953778468
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2798904842
Short name T291
Test name
Test status
Simulation time 33692684 ps
CPU time 1.43 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 218136 kb
Host smart-debbb951-541a-4556-9e0b-1c0515013eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798904842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2798904842
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3414541498
Short name T603
Test name
Test status
Simulation time 52162693 ps
CPU time 1.01 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 223544 kb
Host smart-afb29e81-24f9-40b2-9954-d8779aa577d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414541498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3414541498
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2337360980
Short name T362
Test name
Test status
Simulation time 82250860 ps
CPU time 1.1 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 216916 kb
Host smart-519667c4-92e3-407b-b4e1-31d1ed8b7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337360980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2337360980
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.937545604
Short name T122
Test name
Test status
Simulation time 40136448 ps
CPU time 1.15 seconds
Started May 19 02:27:33 PM PDT 24
Finished May 19 02:27:37 PM PDT 24
Peak memory 217084 kb
Host smart-56b94c0c-2890-4ed9-868c-c3e5e69d4eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937545604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.937545604
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3840735774
Short name T311
Test name
Test status
Simulation time 98382983 ps
CPU time 1.23 seconds
Started May 19 02:27:35 PM PDT 24
Finished May 19 02:27:39 PM PDT 24
Peak memory 219244 kb
Host smart-c442b0fb-2adc-4cdd-ab77-73611a915a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840735774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3840735774
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1503982006
Short name T554
Test name
Test status
Simulation time 22245213 ps
CPU time 1.24 seconds
Started May 19 02:27:40 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 223460 kb
Host smart-7501040e-2a92-4fb1-9649-39b2ebdbc5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503982006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1503982006
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3566376822
Short name T473
Test name
Test status
Simulation time 75198486 ps
CPU time 1.41 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 218056 kb
Host smart-f065c26a-e0e3-4d9e-b55b-2cd0865f3744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566376822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3566376822
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1462711983
Short name T133
Test name
Test status
Simulation time 71044322 ps
CPU time 1.06 seconds
Started May 19 02:27:37 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 219224 kb
Host smart-b9d2dbfd-63dd-40cd-afa4-9cb6952615fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462711983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1462711983
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3627939316
Short name T374
Test name
Test status
Simulation time 87256211 ps
CPU time 1.57 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 217816 kb
Host smart-8ecc65f1-473f-439c-9b09-3184b77b6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627939316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3627939316
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1521621939
Short name T777
Test name
Test status
Simulation time 21971626 ps
CPU time 0.88 seconds
Started May 19 02:27:49 PM PDT 24
Finished May 19 02:27:52 PM PDT 24
Peak memory 217856 kb
Host smart-c90a317a-870b-4906-991f-81c2342e0408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521621939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1521621939
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3601910621
Short name T11
Test name
Test status
Simulation time 73552825 ps
CPU time 1.52 seconds
Started May 19 02:27:36 PM PDT 24
Finished May 19 02:27:40 PM PDT 24
Peak memory 219484 kb
Host smart-2b082700-1b42-4679-8fbc-d69f45419986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601910621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3601910621
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2318085425
Short name T182
Test name
Test status
Simulation time 25912627 ps
CPU time 1.24 seconds
Started May 19 02:27:41 PM PDT 24
Finished May 19 02:27:44 PM PDT 24
Peak memory 218072 kb
Host smart-edd5a7ca-d32b-4f12-89fd-6a02bbb6eaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318085425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2318085425
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4139541394
Short name T522
Test name
Test status
Simulation time 43053095 ps
CPU time 1.1 seconds
Started May 19 02:27:38 PM PDT 24
Finished May 19 02:27:41 PM PDT 24
Peak memory 217976 kb
Host smart-70db07ff-0bba-4d82-802e-6c8908fc9580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139541394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4139541394
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.4064920989
Short name T674
Test name
Test status
Simulation time 38006219 ps
CPU time 0.9 seconds
Started May 19 02:27:41 PM PDT 24
Finished May 19 02:27:44 PM PDT 24
Peak memory 218996 kb
Host smart-10c26f96-ed6c-4c61-9481-0a2a41dce31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064920989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4064920989
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1944021838
Short name T91
Test name
Test status
Simulation time 148796324 ps
CPU time 1.3 seconds
Started May 19 02:27:39 PM PDT 24
Finished May 19 02:27:43 PM PDT 24
Peak memory 218472 kb
Host smart-0bd8dfe6-6e4b-4c74-9984-0289fbc62dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944021838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1944021838
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3063570649
Short name T780
Test name
Test status
Simulation time 32597716 ps
CPU time 0.92 seconds
Started May 19 02:27:41 PM PDT 24
Finished May 19 02:27:44 PM PDT 24
Peak memory 217948 kb
Host smart-9a847f8a-6878-46c1-b9a5-ef9861a40754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063570649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3063570649
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3117329199
Short name T730
Test name
Test status
Simulation time 53451726 ps
CPU time 1.27 seconds
Started May 19 02:27:41 PM PDT 24
Finished May 19 02:27:44 PM PDT 24
Peak memory 216900 kb
Host smart-df74c3ed-aa25-43bf-a536-b406e26b112b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117329199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3117329199
Directory /workspace/99.edn_genbits/latest
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