Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.58 98.24 93.80 97.02 85.47 96.62 99.77 91.12


Total test records in report: 979
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T793 /workspace/coverage/default/38.edn_genbits.3768931236 May 21 02:15:53 PM PDT 24 May 21 02:15:55 PM PDT 24 203504329 ps
T794 /workspace/coverage/default/257.edn_genbits.1191877711 May 21 02:24:55 PM PDT 24 May 21 02:24:57 PM PDT 24 48439021 ps
T795 /workspace/coverage/default/14.edn_alert_test.3045683192 May 21 02:13:48 PM PDT 24 May 21 02:13:55 PM PDT 24 135620640 ps
T130 /workspace/coverage/default/76.edn_err.3842403223 May 21 02:20:33 PM PDT 24 May 21 02:20:35 PM PDT 24 18795462 ps
T796 /workspace/coverage/default/3.edn_alert.4021890146 May 21 02:12:56 PM PDT 24 May 21 02:13:00 PM PDT 24 150306944 ps
T797 /workspace/coverage/default/38.edn_err.913421934 May 21 02:15:54 PM PDT 24 May 21 02:15:55 PM PDT 24 35929876 ps
T140 /workspace/coverage/default/17.edn_err.178781659 May 21 02:14:05 PM PDT 24 May 21 02:14:11 PM PDT 24 28613159 ps
T798 /workspace/coverage/default/51.edn_genbits.251000202 May 21 02:19:01 PM PDT 24 May 21 02:19:04 PM PDT 24 60736718 ps
T799 /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3156582728 May 21 02:14:13 PM PDT 24 May 21 02:22:33 PM PDT 24 21477421856 ps
T800 /workspace/coverage/default/82.edn_err.1682813352 May 21 02:21:02 PM PDT 24 May 21 02:21:04 PM PDT 24 72711542 ps
T131 /workspace/coverage/default/53.edn_err.641240714 May 21 02:19:08 PM PDT 24 May 21 02:19:10 PM PDT 24 18504305 ps
T801 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1941034520 May 21 02:15:36 PM PDT 24 May 21 02:24:14 PM PDT 24 295299707465 ps
T802 /workspace/coverage/default/110.edn_genbits.4278899360 May 21 02:22:46 PM PDT 24 May 21 02:22:49 PM PDT 24 65905942 ps
T803 /workspace/coverage/default/160.edn_genbits.3526196025 May 21 02:24:04 PM PDT 24 May 21 02:24:06 PM PDT 24 342880427 ps
T804 /workspace/coverage/default/21.edn_stress_all.4221729186 May 21 02:14:16 PM PDT 24 May 21 02:14:24 PM PDT 24 449360937 ps
T805 /workspace/coverage/default/32.edn_err.484229298 May 21 02:15:03 PM PDT 24 May 21 02:15:14 PM PDT 24 86767400 ps
T806 /workspace/coverage/default/31.edn_disable.348851487 May 21 02:15:00 PM PDT 24 May 21 02:15:09 PM PDT 24 29619278 ps
T807 /workspace/coverage/default/11.edn_stress_all.1598253916 May 21 02:13:34 PM PDT 24 May 21 02:13:47 PM PDT 24 394986624 ps
T808 /workspace/coverage/default/20.edn_stress_all.3827566664 May 21 02:14:12 PM PDT 24 May 21 02:14:18 PM PDT 24 318670848 ps
T809 /workspace/coverage/default/215.edn_genbits.1438077870 May 21 02:24:38 PM PDT 24 May 21 02:24:41 PM PDT 24 32967355 ps
T810 /workspace/coverage/default/27.edn_stress_all.1854590276 May 21 02:14:34 PM PDT 24 May 21 02:14:40 PM PDT 24 442868113 ps
T811 /workspace/coverage/default/49.edn_smoke.1264835387 May 21 02:18:31 PM PDT 24 May 21 02:18:33 PM PDT 24 17026296 ps
T812 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3420959395 May 21 02:14:34 PM PDT 24 May 21 02:27:36 PM PDT 24 518883758894 ps
T204 /workspace/coverage/default/32.edn_alert.2032771748 May 21 02:15:04 PM PDT 24 May 21 02:15:14 PM PDT 24 30355918 ps
T813 /workspace/coverage/default/41.edn_disable.2406640021 May 21 02:16:17 PM PDT 24 May 21 02:16:20 PM PDT 24 39256238 ps
T814 /workspace/coverage/default/44.edn_intr.1663974662 May 21 02:17:15 PM PDT 24 May 21 02:17:18 PM PDT 24 23795469 ps
T815 /workspace/coverage/default/169.edn_genbits.466538006 May 21 02:24:12 PM PDT 24 May 21 02:24:14 PM PDT 24 157028297 ps
T816 /workspace/coverage/default/13.edn_alert.3399669576 May 21 02:13:45 PM PDT 24 May 21 02:13:54 PM PDT 24 132184993 ps
T817 /workspace/coverage/default/60.edn_genbits.3064068446 May 21 02:19:38 PM PDT 24 May 21 02:19:40 PM PDT 24 37062255 ps
T818 /workspace/coverage/default/37.edn_disable_auto_req_mode.2327415986 May 21 02:15:47 PM PDT 24 May 21 02:15:49 PM PDT 24 29532822 ps
T819 /workspace/coverage/default/9.edn_regwen.3797671105 May 21 02:13:27 PM PDT 24 May 21 02:13:38 PM PDT 24 19320380 ps
T820 /workspace/coverage/default/22.edn_stress_all.3844253458 May 21 02:14:15 PM PDT 24 May 21 02:14:20 PM PDT 24 52954656 ps
T821 /workspace/coverage/default/53.edn_genbits.2196785522 May 21 02:19:07 PM PDT 24 May 21 02:19:09 PM PDT 24 52123990 ps
T822 /workspace/coverage/default/116.edn_genbits.1470686841 May 21 02:23:06 PM PDT 24 May 21 02:23:08 PM PDT 24 40071217 ps
T823 /workspace/coverage/default/93.edn_genbits.1500166061 May 21 02:21:42 PM PDT 24 May 21 02:21:44 PM PDT 24 47898604 ps
T824 /workspace/coverage/default/11.edn_smoke.3660304637 May 21 02:13:34 PM PDT 24 May 21 02:13:46 PM PDT 24 15753714 ps
T825 /workspace/coverage/default/19.edn_disable.3119405808 May 21 02:14:10 PM PDT 24 May 21 02:14:15 PM PDT 24 13663540 ps
T826 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1187827734 May 21 02:14:08 PM PDT 24 May 21 02:38:03 PM PDT 24 246692324113 ps
T827 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3005369536 May 21 02:18:38 PM PDT 24 May 21 03:07:54 PM PDT 24 115772697572 ps
T828 /workspace/coverage/default/88.edn_genbits.1373055137 May 21 02:21:24 PM PDT 24 May 21 02:21:27 PM PDT 24 43311393 ps
T829 /workspace/coverage/default/46.edn_disable_auto_req_mode.736153916 May 21 02:17:54 PM PDT 24 May 21 02:17:56 PM PDT 24 86139666 ps
T159 /workspace/coverage/default/46.edn_intr.4233502116 May 21 02:17:44 PM PDT 24 May 21 02:17:48 PM PDT 24 21670103 ps
T830 /workspace/coverage/default/28.edn_disable.4240938875 May 21 02:14:38 PM PDT 24 May 21 02:14:42 PM PDT 24 26816201 ps
T831 /workspace/coverage/default/191.edn_genbits.403916461 May 21 02:24:24 PM PDT 24 May 21 02:26:33 PM PDT 24 9125238847 ps
T832 /workspace/coverage/default/18.edn_stress_all.3663740476 May 21 02:14:06 PM PDT 24 May 21 02:14:16 PM PDT 24 240929482 ps
T833 /workspace/coverage/default/58.edn_genbits.3619984894 May 21 02:19:28 PM PDT 24 May 21 02:19:30 PM PDT 24 47897398 ps
T834 /workspace/coverage/default/48.edn_stress_all_with_rand_reset.468816501 May 21 02:18:21 PM PDT 24 May 21 02:27:02 PM PDT 24 37450702858 ps
T289 /workspace/coverage/default/142.edn_genbits.1464450652 May 21 02:23:52 PM PDT 24 May 21 02:23:54 PM PDT 24 64343532 ps
T835 /workspace/coverage/default/18.edn_err.40456983 May 21 02:14:07 PM PDT 24 May 21 02:14:13 PM PDT 24 25709467 ps
T836 /workspace/coverage/default/22.edn_disable.2191721569 May 21 02:14:12 PM PDT 24 May 21 02:14:17 PM PDT 24 11277975 ps
T837 /workspace/coverage/default/130.edn_genbits.3060040339 May 21 02:23:38 PM PDT 24 May 21 02:23:41 PM PDT 24 52162407 ps
T838 /workspace/coverage/default/47.edn_disable_auto_req_mode.1789580629 May 21 02:18:10 PM PDT 24 May 21 02:18:12 PM PDT 24 50278497 ps
T188 /workspace/coverage/default/67.edn_err.3068302509 May 21 02:20:02 PM PDT 24 May 21 02:20:04 PM PDT 24 62596717 ps
T839 /workspace/coverage/default/19.edn_genbits.305290075 May 21 02:14:05 PM PDT 24 May 21 02:14:11 PM PDT 24 38395275 ps
T840 /workspace/coverage/default/20.edn_alert_test.2487777864 May 21 02:14:13 PM PDT 24 May 21 02:14:18 PM PDT 24 18373064 ps
T841 /workspace/coverage/default/93.edn_err.2400883950 May 21 02:21:43 PM PDT 24 May 21 02:21:45 PM PDT 24 37944624 ps
T842 /workspace/coverage/default/1.edn_disable_auto_req_mode.2169901610 May 21 02:12:46 PM PDT 24 May 21 02:12:51 PM PDT 24 71028209 ps
T843 /workspace/coverage/default/95.edn_genbits.614833088 May 21 02:21:55 PM PDT 24 May 21 02:21:58 PM PDT 24 52658105 ps
T844 /workspace/coverage/default/206.edn_genbits.3230444225 May 21 02:24:32 PM PDT 24 May 21 02:24:34 PM PDT 24 87603175 ps
T104 /workspace/coverage/default/29.edn_err.2139182415 May 21 02:14:59 PM PDT 24 May 21 02:15:08 PM PDT 24 60537663 ps
T845 /workspace/coverage/default/224.edn_genbits.524445790 May 21 02:24:37 PM PDT 24 May 21 02:24:40 PM PDT 24 58411859 ps
T304 /workspace/coverage/default/14.edn_alert.1547367886 May 21 02:13:54 PM PDT 24 May 21 02:14:01 PM PDT 24 23036422 ps
T846 /workspace/coverage/default/92.edn_genbits.1575463545 May 21 02:21:42 PM PDT 24 May 21 02:21:44 PM PDT 24 84590127 ps
T847 /workspace/coverage/default/18.edn_disable_auto_req_mode.1680274618 May 21 02:14:10 PM PDT 24 May 21 02:14:15 PM PDT 24 51330822 ps
T848 /workspace/coverage/cover_reg_top/2.edn_tl_errors.4136500042 May 21 01:13:02 PM PDT 24 May 21 01:13:07 PM PDT 24 63575795 ps
T849 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2112784848 May 21 01:13:07 PM PDT 24 May 21 01:13:12 PM PDT 24 45985479 ps
T228 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2447421849 May 21 01:13:18 PM PDT 24 May 21 01:13:21 PM PDT 24 28099095 ps
T850 /workspace/coverage/cover_reg_top/41.edn_intr_test.3726336597 May 21 01:13:26 PM PDT 24 May 21 01:13:28 PM PDT 24 15135759 ps
T851 /workspace/coverage/cover_reg_top/35.edn_intr_test.1109280305 May 21 01:13:26 PM PDT 24 May 21 01:13:29 PM PDT 24 20129055 ps
T852 /workspace/coverage/cover_reg_top/6.edn_intr_test.3743337412 May 21 01:13:10 PM PDT 24 May 21 01:13:14 PM PDT 24 17067699 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.136712414 May 21 01:13:10 PM PDT 24 May 21 01:13:16 PM PDT 24 205340617 ps
T254 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2959347343 May 21 01:13:25 PM PDT 24 May 21 01:13:28 PM PDT 24 132380534 ps
T853 /workspace/coverage/cover_reg_top/17.edn_tl_errors.795971223 May 21 01:13:25 PM PDT 24 May 21 01:13:30 PM PDT 24 298110672 ps
T230 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1499939280 May 21 01:13:04 PM PDT 24 May 21 01:13:08 PM PDT 24 14345152 ps
T251 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.171461992 May 21 01:13:02 PM PDT 24 May 21 01:13:06 PM PDT 24 46128833 ps
T854 /workspace/coverage/cover_reg_top/10.edn_intr_test.2824839031 May 21 01:13:15 PM PDT 24 May 21 01:13:17 PM PDT 24 12748799 ps
T855 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4236447777 May 21 01:13:09 PM PDT 24 May 21 01:13:14 PM PDT 24 42126472 ps
T856 /workspace/coverage/cover_reg_top/11.edn_intr_test.4090630139 May 21 01:13:17 PM PDT 24 May 21 01:13:20 PM PDT 24 11927381 ps
T255 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3623870658 May 21 01:13:04 PM PDT 24 May 21 01:13:10 PM PDT 24 154637609 ps
T857 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1332618830 May 21 01:13:05 PM PDT 24 May 21 01:13:10 PM PDT 24 25017958 ps
T252 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1776180756 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 20734938 ps
T231 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1891930252 May 21 01:13:11 PM PDT 24 May 21 01:13:15 PM PDT 24 20877034 ps
T858 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2503440048 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 43021532 ps
T256 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1028471312 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 156289449 ps
T261 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1387911017 May 21 01:13:10 PM PDT 24 May 21 01:13:15 PM PDT 24 176897469 ps
T859 /workspace/coverage/cover_reg_top/48.edn_intr_test.2866552557 May 21 01:13:34 PM PDT 24 May 21 01:13:35 PM PDT 24 30783803 ps
T253 /workspace/coverage/cover_reg_top/12.edn_csr_rw.482244735 May 21 01:13:16 PM PDT 24 May 21 01:13:18 PM PDT 24 15915214 ps
T860 /workspace/coverage/cover_reg_top/3.edn_intr_test.1008121513 May 21 01:13:05 PM PDT 24 May 21 01:13:09 PM PDT 24 127064546 ps
T861 /workspace/coverage/cover_reg_top/20.edn_intr_test.2845000845 May 21 01:13:23 PM PDT 24 May 21 01:13:25 PM PDT 24 24434584 ps
T862 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1963579373 May 21 01:13:00 PM PDT 24 May 21 01:13:03 PM PDT 24 30374460 ps
T863 /workspace/coverage/cover_reg_top/3.edn_tl_errors.4162655458 May 21 01:13:03 PM PDT 24 May 21 01:13:10 PM PDT 24 82184733 ps
T246 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2235151345 May 21 01:13:17 PM PDT 24 May 21 01:13:20 PM PDT 24 17214878 ps
T232 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4241179837 May 21 01:13:17 PM PDT 24 May 21 01:13:20 PM PDT 24 50396500 ps
T247 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1781621777 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 62114050 ps
T864 /workspace/coverage/cover_reg_top/4.edn_intr_test.3564875082 May 21 01:13:10 PM PDT 24 May 21 01:13:14 PM PDT 24 22009642 ps
T865 /workspace/coverage/cover_reg_top/22.edn_intr_test.1264997670 May 21 01:13:21 PM PDT 24 May 21 01:13:24 PM PDT 24 44048032 ps
T262 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2595595674 May 21 01:13:09 PM PDT 24 May 21 01:13:15 PM PDT 24 94020893 ps
T233 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2850412944 May 21 01:13:09 PM PDT 24 May 21 01:13:14 PM PDT 24 362972355 ps
T866 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3496650376 May 21 01:13:03 PM PDT 24 May 21 01:13:10 PM PDT 24 175359478 ps
T867 /workspace/coverage/cover_reg_top/24.edn_intr_test.3473627789 May 21 01:13:23 PM PDT 24 May 21 01:13:26 PM PDT 24 22159985 ps
T868 /workspace/coverage/cover_reg_top/10.edn_tl_errors.4058679734 May 21 01:13:17 PM PDT 24 May 21 01:13:22 PM PDT 24 52411017 ps
T234 /workspace/coverage/cover_reg_top/18.edn_csr_rw.277402197 May 21 01:13:24 PM PDT 24 May 21 01:13:26 PM PDT 24 43525030 ps
T869 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3487709866 May 21 01:13:10 PM PDT 24 May 21 01:13:14 PM PDT 24 41244674 ps
T870 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1869619555 May 21 01:13:20 PM PDT 24 May 21 01:13:23 PM PDT 24 26421610 ps
T871 /workspace/coverage/cover_reg_top/30.edn_intr_test.2126744426 May 21 01:13:26 PM PDT 24 May 21 01:13:29 PM PDT 24 13260316 ps
T872 /workspace/coverage/cover_reg_top/44.edn_intr_test.1833111523 May 21 01:13:27 PM PDT 24 May 21 01:13:29 PM PDT 24 25788718 ps
T235 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4044278336 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 83298406 ps
T248 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1614406357 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 20673514 ps
T236 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2727335638 May 21 01:13:16 PM PDT 24 May 21 01:13:19 PM PDT 24 54581306 ps
T873 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2090511917 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 95172861 ps
T249 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3823381085 May 21 01:13:19 PM PDT 24 May 21 01:13:22 PM PDT 24 114932591 ps
T874 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.113378720 May 21 01:13:08 PM PDT 24 May 21 01:13:12 PM PDT 24 33845670 ps
T875 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1497849402 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 16880122 ps
T876 /workspace/coverage/cover_reg_top/14.edn_intr_test.393168689 May 21 01:13:17 PM PDT 24 May 21 01:13:20 PM PDT 24 21264743 ps
T264 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2924139245 May 21 01:13:07 PM PDT 24 May 21 01:13:12 PM PDT 24 90251849 ps
T237 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2495044828 May 21 01:13:04 PM PDT 24 May 21 01:13:08 PM PDT 24 45957406 ps
T877 /workspace/coverage/cover_reg_top/21.edn_intr_test.3365456112 May 21 01:13:22 PM PDT 24 May 21 01:13:24 PM PDT 24 35918281 ps
T878 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1267751927 May 21 01:13:22 PM PDT 24 May 21 01:13:24 PM PDT 24 27944935 ps
T879 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2500170556 May 21 01:13:16 PM PDT 24 May 21 01:13:21 PM PDT 24 155156267 ps
T880 /workspace/coverage/cover_reg_top/13.edn_intr_test.1921833050 May 21 01:13:15 PM PDT 24 May 21 01:13:17 PM PDT 24 39749100 ps
T881 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1481746452 May 21 01:13:19 PM PDT 24 May 21 01:13:22 PM PDT 24 19045583 ps
T244 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1816188996 May 21 01:13:10 PM PDT 24 May 21 01:13:17 PM PDT 24 112479284 ps
T238 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3975181718 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 62899163 ps
T882 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1388856298 May 21 01:13:08 PM PDT 24 May 21 01:13:13 PM PDT 24 22362953 ps
T883 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3170478041 May 21 01:13:06 PM PDT 24 May 21 01:13:11 PM PDT 24 48287037 ps
T884 /workspace/coverage/cover_reg_top/0.edn_intr_test.1007057616 May 21 01:12:58 PM PDT 24 May 21 01:13:00 PM PDT 24 29451984 ps
T885 /workspace/coverage/cover_reg_top/31.edn_intr_test.1944793094 May 21 01:13:27 PM PDT 24 May 21 01:13:29 PM PDT 24 19952428 ps
T886 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2539305827 May 21 01:13:19 PM PDT 24 May 21 01:13:24 PM PDT 24 205201266 ps
T887 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.389656489 May 21 01:13:07 PM PDT 24 May 21 01:13:11 PM PDT 24 297984809 ps
T888 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1414968561 May 21 01:12:55 PM PDT 24 May 21 01:12:59 PM PDT 24 73351035 ps
T889 /workspace/coverage/cover_reg_top/7.edn_intr_test.461856488 May 21 01:13:10 PM PDT 24 May 21 01:13:14 PM PDT 24 15180244 ps
T890 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1186194092 May 21 01:13:02 PM PDT 24 May 21 01:13:06 PM PDT 24 55260215 ps
T239 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2121642625 May 21 01:13:04 PM PDT 24 May 21 01:13:08 PM PDT 24 16033243 ps
T891 /workspace/coverage/cover_reg_top/1.edn_tl_errors.282099965 May 21 01:13:02 PM PDT 24 May 21 01:13:06 PM PDT 24 194919028 ps
T892 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3644733148 May 21 01:13:22 PM PDT 24 May 21 01:13:25 PM PDT 24 56433924 ps
T893 /workspace/coverage/cover_reg_top/25.edn_intr_test.3916984544 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 85193338 ps
T894 /workspace/coverage/cover_reg_top/33.edn_intr_test.2487592874 May 21 01:13:27 PM PDT 24 May 21 01:13:29 PM PDT 24 14076394 ps
T895 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1662211222 May 21 01:13:02 PM PDT 24 May 21 01:13:07 PM PDT 24 85166485 ps
T896 /workspace/coverage/cover_reg_top/7.edn_csr_rw.953119335 May 21 01:13:09 PM PDT 24 May 21 01:13:14 PM PDT 24 34754556 ps
T897 /workspace/coverage/cover_reg_top/8.edn_intr_test.3943015441 May 21 01:13:11 PM PDT 24 May 21 01:13:15 PM PDT 24 64888614 ps
T898 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.480718693 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 37496543 ps
T899 /workspace/coverage/cover_reg_top/18.edn_intr_test.3654656057 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 153780265 ps
T900 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2689770051 May 21 01:13:24 PM PDT 24 May 21 01:13:28 PM PDT 24 66102337 ps
T265 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.200604918 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 236904387 ps
T901 /workspace/coverage/cover_reg_top/40.edn_intr_test.3009819165 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 17247811 ps
T902 /workspace/coverage/cover_reg_top/9.edn_intr_test.1421391390 May 21 01:13:11 PM PDT 24 May 21 01:13:15 PM PDT 24 27266423 ps
T903 /workspace/coverage/cover_reg_top/17.edn_intr_test.3668613885 May 21 01:13:23 PM PDT 24 May 21 01:13:25 PM PDT 24 15248012 ps
T904 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1347467932 May 21 01:13:18 PM PDT 24 May 21 01:13:24 PM PDT 24 103066381 ps
T905 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.285912487 May 21 01:13:03 PM PDT 24 May 21 01:13:07 PM PDT 24 91078889 ps
T906 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3468264889 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 53720466 ps
T907 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2865582211 May 21 01:13:19 PM PDT 24 May 21 01:13:23 PM PDT 24 52041170 ps
T908 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.696801821 May 21 01:13:20 PM PDT 24 May 21 01:13:23 PM PDT 24 29352497 ps
T909 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3776179195 May 21 01:13:22 PM PDT 24 May 21 01:13:24 PM PDT 24 37316961 ps
T910 /workspace/coverage/cover_reg_top/43.edn_intr_test.3822848534 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 15555021 ps
T911 /workspace/coverage/cover_reg_top/42.edn_intr_test.1462496285 May 21 01:13:29 PM PDT 24 May 21 01:13:32 PM PDT 24 25641448 ps
T912 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1655145673 May 21 01:13:12 PM PDT 24 May 21 01:13:16 PM PDT 24 20356258 ps
T240 /workspace/coverage/cover_reg_top/16.edn_csr_rw.4178642538 May 21 01:13:24 PM PDT 24 May 21 01:13:27 PM PDT 24 53038223 ps
T241 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1224685196 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 31866922 ps
T913 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2101834456 May 21 01:13:16 PM PDT 24 May 21 01:13:18 PM PDT 24 32173684 ps
T242 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3194047288 May 21 01:13:02 PM PDT 24 May 21 01:13:06 PM PDT 24 13193764 ps
T914 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1278131327 May 21 01:13:05 PM PDT 24 May 21 01:13:10 PM PDT 24 70614801 ps
T915 /workspace/coverage/cover_reg_top/15.edn_intr_test.2429937367 May 21 01:13:19 PM PDT 24 May 21 01:13:22 PM PDT 24 42501444 ps
T916 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3254869467 May 21 01:13:03 PM PDT 24 May 21 01:13:11 PM PDT 24 171928269 ps
T917 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.423548569 May 21 01:13:01 PM PDT 24 May 21 01:13:04 PM PDT 24 30452155 ps
T918 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.51755600 May 21 01:13:05 PM PDT 24 May 21 01:13:14 PM PDT 24 346108501 ps
T919 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2985448038 May 21 01:13:09 PM PDT 24 May 21 01:13:14 PM PDT 24 107886366 ps
T243 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1015044852 May 21 01:13:15 PM PDT 24 May 21 01:13:18 PM PDT 24 65211560 ps
T920 /workspace/coverage/cover_reg_top/29.edn_intr_test.3804414029 May 21 01:13:27 PM PDT 24 May 21 01:13:30 PM PDT 24 27524737 ps
T921 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.811898946 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 61126491 ps
T922 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1667300532 May 21 01:13:23 PM PDT 24 May 21 01:13:26 PM PDT 24 85132234 ps
T923 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2500283390 May 21 01:13:08 PM PDT 24 May 21 01:13:14 PM PDT 24 38191144 ps
T924 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.134715095 May 21 01:13:08 PM PDT 24 May 21 01:13:12 PM PDT 24 120105961 ps
T925 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.17785438 May 21 01:13:06 PM PDT 24 May 21 01:13:11 PM PDT 24 65960627 ps
T926 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1562978020 May 21 01:13:20 PM PDT 24 May 21 01:13:25 PM PDT 24 105138846 ps
T927 /workspace/coverage/cover_reg_top/19.edn_intr_test.4008341917 May 21 01:13:22 PM PDT 24 May 21 01:13:24 PM PDT 24 14745216 ps
T928 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1455305565 May 21 01:13:10 PM PDT 24 May 21 01:13:15 PM PDT 24 38572758 ps
T929 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2848799688 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 126758419 ps
T930 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1301201485 May 21 01:13:03 PM PDT 24 May 21 01:13:07 PM PDT 24 77839609 ps
T931 /workspace/coverage/cover_reg_top/5.edn_intr_test.465967591 May 21 01:13:01 PM PDT 24 May 21 01:13:04 PM PDT 24 18348964 ps
T263 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2364393274 May 21 01:13:23 PM PDT 24 May 21 01:13:27 PM PDT 24 156242941 ps
T932 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1458345072 May 21 01:13:09 PM PDT 24 May 21 01:13:13 PM PDT 24 102580707 ps
T933 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.803181847 May 21 01:13:18 PM PDT 24 May 21 01:13:23 PM PDT 24 258159864 ps
T934 /workspace/coverage/cover_reg_top/28.edn_intr_test.4137595447 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 67468984 ps
T935 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.534366669 May 21 01:13:19 PM PDT 24 May 21 01:13:22 PM PDT 24 42115717 ps
T936 /workspace/coverage/cover_reg_top/47.edn_intr_test.2518219529 May 21 01:13:34 PM PDT 24 May 21 01:13:35 PM PDT 24 38553412 ps
T937 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.237692050 May 21 01:13:10 PM PDT 24 May 21 01:13:14 PM PDT 24 91631224 ps
T938 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3735875390 May 21 01:13:06 PM PDT 24 May 21 01:13:11 PM PDT 24 123183335 ps
T939 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.106183107 May 21 01:13:17 PM PDT 24 May 21 01:13:21 PM PDT 24 32225763 ps
T940 /workspace/coverage/cover_reg_top/45.edn_intr_test.3533324302 May 21 01:13:36 PM PDT 24 May 21 01:13:37 PM PDT 24 19254538 ps
T941 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4187980377 May 21 01:13:14 PM PDT 24 May 21 01:13:17 PM PDT 24 52895087 ps
T942 /workspace/coverage/cover_reg_top/46.edn_intr_test.3072227967 May 21 01:13:38 PM PDT 24 May 21 01:13:39 PM PDT 24 85908592 ps
T943 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2972612581 May 21 01:13:02 PM PDT 24 May 21 01:13:06 PM PDT 24 15063966 ps
T944 /workspace/coverage/cover_reg_top/36.edn_intr_test.2839071110 May 21 01:13:25 PM PDT 24 May 21 01:13:28 PM PDT 24 113470651 ps
T945 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2764874936 May 21 01:13:16 PM PDT 24 May 21 01:13:19 PM PDT 24 18736511 ps
T946 /workspace/coverage/cover_reg_top/38.edn_intr_test.484713168 May 21 01:13:27 PM PDT 24 May 21 01:13:30 PM PDT 24 15001533 ps
T947 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2950659211 May 21 01:13:10 PM PDT 24 May 21 01:13:15 PM PDT 24 48761003 ps
T948 /workspace/coverage/cover_reg_top/39.edn_intr_test.4255304968 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 15268043 ps
T949 /workspace/coverage/cover_reg_top/2.edn_intr_test.1493416792 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 32601414 ps
T950 /workspace/coverage/cover_reg_top/37.edn_intr_test.2234388987 May 21 01:13:27 PM PDT 24 May 21 01:13:29 PM PDT 24 56915732 ps
T951 /workspace/coverage/cover_reg_top/1.edn_intr_test.729360857 May 21 01:13:04 PM PDT 24 May 21 01:13:09 PM PDT 24 38702748 ps
T952 /workspace/coverage/cover_reg_top/23.edn_intr_test.3915491071 May 21 01:13:24 PM PDT 24 May 21 01:13:26 PM PDT 24 41343521 ps
T953 /workspace/coverage/cover_reg_top/27.edn_intr_test.903363219 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 19608231 ps
T954 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3039062920 May 21 01:13:08 PM PDT 24 May 21 01:13:14 PM PDT 24 55430883 ps
T955 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2915897916 May 21 01:13:01 PM PDT 24 May 21 01:13:05 PM PDT 24 33356241 ps
T956 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1607490613 May 21 01:13:05 PM PDT 24 May 21 01:13:09 PM PDT 24 24736198 ps
T957 /workspace/coverage/cover_reg_top/26.edn_intr_test.3601640525 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 30211914 ps
T958 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1050615629 May 21 01:13:17 PM PDT 24 May 21 01:13:22 PM PDT 24 92717117 ps
T959 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2558738367 May 21 01:13:10 PM PDT 24 May 21 01:13:17 PM PDT 24 357167232 ps
T960 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3783269752 May 21 01:13:03 PM PDT 24 May 21 01:13:07 PM PDT 24 135778204 ps
T961 /workspace/coverage/cover_reg_top/15.edn_csr_rw.177839975 May 21 01:13:18 PM PDT 24 May 21 01:13:21 PM PDT 24 23752532 ps
T962 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1899385519 May 21 01:13:07 PM PDT 24 May 21 01:13:12 PM PDT 24 25566839 ps
T963 /workspace/coverage/cover_reg_top/16.edn_intr_test.3513179212 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 23835528 ps
T964 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4182164598 May 21 01:13:28 PM PDT 24 May 21 01:13:32 PM PDT 24 82520839 ps
T965 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4112496603 May 21 01:12:54 PM PDT 24 May 21 01:12:57 PM PDT 24 70451151 ps
T966 /workspace/coverage/cover_reg_top/12.edn_intr_test.4013199017 May 21 01:13:15 PM PDT 24 May 21 01:13:17 PM PDT 24 104882099 ps
T967 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2032944417 May 21 01:13:08 PM PDT 24 May 21 01:13:12 PM PDT 24 12021305 ps
T968 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1622638472 May 21 01:13:27 PM PDT 24 May 21 01:13:31 PM PDT 24 57985883 ps
T245 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1078157039 May 21 01:13:22 PM PDT 24 May 21 01:13:24 PM PDT 24 28921791 ps
T969 /workspace/coverage/cover_reg_top/32.edn_intr_test.205099542 May 21 01:13:30 PM PDT 24 May 21 01:13:33 PM PDT 24 19454555 ps
T970 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2916657245 May 21 01:13:28 PM PDT 24 May 21 01:13:33 PM PDT 24 38331674 ps
T971 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3644281782 May 21 01:13:16 PM PDT 24 May 21 01:13:20 PM PDT 24 249266060 ps
T972 /workspace/coverage/cover_reg_top/49.edn_intr_test.3597673722 May 21 01:13:36 PM PDT 24 May 21 01:13:37 PM PDT 24 34748989 ps
T973 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2725528325 May 21 01:13:09 PM PDT 24 May 21 01:13:13 PM PDT 24 12126720 ps
T974 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4265719980 May 21 01:13:17 PM PDT 24 May 21 01:13:21 PM PDT 24 373482048 ps
T975 /workspace/coverage/cover_reg_top/34.edn_intr_test.3323098929 May 21 01:13:29 PM PDT 24 May 21 01:13:32 PM PDT 24 14215212 ps
T976 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2526207683 May 21 01:13:28 PM PDT 24 May 21 01:13:31 PM PDT 24 52489853 ps
T977 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3787912225 May 21 01:13:18 PM PDT 24 May 21 01:13:22 PM PDT 24 666592973 ps
T978 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.339520500 May 21 01:13:15 PM PDT 24 May 21 01:13:18 PM PDT 24 17887429 ps
T979 /workspace/coverage/cover_reg_top/3.edn_csr_rw.52517057 May 21 01:13:04 PM PDT 24 May 21 01:13:08 PM PDT 24 44386244 ps

Test location /workspace/coverage/default/208.edn_genbits.1395988394
Short name T9
Test name
Test status
Simulation time 48130374 ps
CPU time 2.16 seconds
Started May 21 02:24:31 PM PDT 24
Finished May 21 02:24:34 PM PDT 24
Peak memory 219704 kb
Host smart-06799a0d-42ad-411c-b252-4cb14f70ec96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395988394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1395988394
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2452293380
Short name T39
Test name
Test status
Simulation time 532292612534 ps
CPU time 1420.29 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:37:43 PM PDT 24
Peak memory 224652 kb
Host smart-041bf89b-c3c8-4fef-be9e-24524e2c61af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452293380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2452293380
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.edn_err.476658079
Short name T4
Test name
Test status
Simulation time 24708708 ps
CPU time 1 seconds
Started May 21 02:19:56 PM PDT 24
Finished May 21 02:19:58 PM PDT 24
Peak memory 218108 kb
Host smart-1ef0153b-9dca-48f6-92a4-84731684085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476658079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.476658079
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/260.edn_genbits.4271836191
Short name T44
Test name
Test status
Simulation time 86257822 ps
CPU time 1.32 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 218208 kb
Host smart-e8ae0fef-d3d6-4cae-b620-133305209034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271836191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4271836191
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3571772211
Short name T16
Test name
Test status
Simulation time 498269046 ps
CPU time 4.41 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 236708 kb
Host smart-febfbd10-5527-4520-a219-2b30e8450645
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571772211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3571772211
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/6.edn_alert.3677255007
Short name T28
Test name
Test status
Simulation time 45544740 ps
CPU time 1.12 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 215456 kb
Host smart-d2319b64-668f-4ae1-9909-e76636d12755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677255007 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3677255007
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.829374734
Short name T65
Test name
Test status
Simulation time 258343118 ps
CPU time 4.1 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:50 PM PDT 24
Peak memory 235384 kb
Host smart-11b09922-bddb-4b94-b48d-1b08532193bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829374734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.829374734
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/45.edn_disable.3050632644
Short name T137
Test name
Test status
Simulation time 12958194 ps
CPU time 0.88 seconds
Started May 21 02:17:37 PM PDT 24
Finished May 21 02:17:39 PM PDT 24
Peak memory 216172 kb
Host smart-b11ec9ab-f3d3-4fca-b50b-0c3875a5c4c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050632644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3050632644
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/63.edn_err.1463823832
Short name T154
Test name
Test status
Simulation time 38530668 ps
CPU time 1.15 seconds
Started May 21 02:19:44 PM PDT 24
Finished May 21 02:19:46 PM PDT 24
Peak memory 220464 kb
Host smart-1e2cce43-b1fc-40c2-bde6-460163337117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463823832 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1463823832
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.132628065
Short name T30
Test name
Test status
Simulation time 79502056 ps
CPU time 1.21 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 215384 kb
Host smart-5442f52a-3017-475d-91dc-207da146bf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132628065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.132628065
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.897751485
Short name T206
Test name
Test status
Simulation time 326804164700 ps
CPU time 1175.1 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:32:21 PM PDT 24
Peak memory 222364 kb
Host smart-124063b3-8605-48a3-ba9f-ae9ce5b1e185
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897751485 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.897751485
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1053523135
Short name T112
Test name
Test status
Simulation time 49789244 ps
CPU time 1.02 seconds
Started May 21 02:13:58 PM PDT 24
Finished May 21 02:14:05 PM PDT 24
Peak memory 216608 kb
Host smart-e7bc636e-7e93-4fe7-b613-142c2f768c91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053523135 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1053523135
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_regwen.1653476989
Short name T27
Test name
Test status
Simulation time 30333257 ps
CPU time 1 seconds
Started May 21 02:12:51 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 206756 kb
Host smart-20337559-2542-4e2b-af73-15c49f6a6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653476989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1653476989
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2865522594
Short name T99
Test name
Test status
Simulation time 104540954 ps
CPU time 1.24 seconds
Started May 21 02:14:09 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 216840 kb
Host smart-8ee673a8-b67f-4492-91cd-6b4baee719ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865522594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2865522594
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_alert.1952545133
Short name T147
Test name
Test status
Simulation time 70683367 ps
CPU time 1.19 seconds
Started May 21 02:14:53 PM PDT 24
Finished May 21 02:15:00 PM PDT 24
Peak memory 215400 kb
Host smart-219f3e6b-20ea-41a0-aa58-029d430a55dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952545133 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1952545133
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3623870658
Short name T255
Test name
Test status
Simulation time 154637609 ps
CPU time 1.65 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 206464 kb
Host smart-5aa895c5-f02e-4c51-9004-da139427f0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623870658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3623870658
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.136712414
Short name T229
Test name
Test status
Simulation time 205340617 ps
CPU time 3.3 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:16 PM PDT 24
Peak memory 205952 kb
Host smart-80f3bedb-601a-4e68-9fa4-3d83b5043a59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136712414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.136712414
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/2.edn_alert.1676525839
Short name T631
Test name
Test status
Simulation time 29940825 ps
CPU time 1.25 seconds
Started May 21 02:12:52 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 215364 kb
Host smart-bb1921ac-587b-40a9-85a4-fd22dcf1e545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676525839 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1676525839
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/20.edn_disable.3241183560
Short name T186
Test name
Test status
Simulation time 28555650 ps
CPU time 0.93 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 216040 kb
Host smart-438da0af-ef65-48d1-99a2-e75460917076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241183560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3241183560
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable.964968301
Short name T143
Test name
Test status
Simulation time 25263396 ps
CPU time 0.87 seconds
Started May 21 02:14:55 PM PDT 24
Finished May 21 02:15:03 PM PDT 24
Peak memory 216056 kb
Host smart-f6c042c9-8b27-457c-8276-45f5fddd2d55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964968301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.964968301
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/20.edn_genbits.3745396611
Short name T41
Test name
Test status
Simulation time 140869504 ps
CPU time 1.15 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 216808 kb
Host smart-89fe3409-aec9-47a4-b2f4-ffb0fcfbb665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745396611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3745396611
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_disable.3901890239
Short name T723
Test name
Test status
Simulation time 16452628 ps
CPU time 0.83 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 216036 kb
Host smart-6cd9cc63-c2fe-4d00-b520-06a8b8e77e8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901890239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3901890239
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.913421934
Short name T797
Test name
Test status
Simulation time 35929876 ps
CPU time 0.85 seconds
Started May 21 02:15:54 PM PDT 24
Finished May 21 02:15:55 PM PDT 24
Peak memory 218584 kb
Host smart-7b0891f6-3c3e-451e-b0c3-dfe21fe9421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913421934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.913421934
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.475287070
Short name T284
Test name
Test status
Simulation time 41538188 ps
CPU time 1.58 seconds
Started May 21 02:20:39 PM PDT 24
Finished May 21 02:20:41 PM PDT 24
Peak memory 219352 kb
Host smart-efab7d76-09c5-4a08-a38f-5298a8722b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475287070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.475287070
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable.3175836063
Short name T119
Test name
Test status
Simulation time 29487487 ps
CPU time 0.9 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 215164 kb
Host smart-7a47a7db-29d8-4ab5-8def-5db12adc2d11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175836063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3175836063
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/45.edn_intr.1193222450
Short name T35
Test name
Test status
Simulation time 25473963 ps
CPU time 0.99 seconds
Started May 21 02:17:34 PM PDT 24
Finished May 21 02:17:35 PM PDT 24
Peak memory 215348 kb
Host smart-0b297a3a-b431-4259-81da-b28c1db190ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193222450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1193222450
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.431648591
Short name T260
Test name
Test status
Simulation time 117872670 ps
CPU time 1.14 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 219068 kb
Host smart-de2509b5-b181-4393-b845-9d3cb9f23295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431648591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.431648591
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert.1035077649
Short name T201
Test name
Test status
Simulation time 72409609 ps
CPU time 1.23 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 215608 kb
Host smart-5872a581-6816-4499-a183-28b01bc7c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035077649 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1035077649
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/5.edn_regwen.1091671348
Short name T297
Test name
Test status
Simulation time 23821451 ps
CPU time 0.95 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 206752 kb
Host smart-6736435c-4595-401e-a90d-be3714ca1e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091671348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1091671348
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/42.edn_disable.1827748245
Short name T172
Test name
Test status
Simulation time 16672003 ps
CPU time 0.93 seconds
Started May 21 02:16:39 PM PDT 24
Finished May 21 02:16:41 PM PDT 24
Peak memory 216300 kb
Host smart-043050bf-df7a-432f-b42a-90874dab2f98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827748245 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1827748245
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.1845522847
Short name T68
Test name
Test status
Simulation time 20677921 ps
CPU time 0.9 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:36 PM PDT 24
Peak memory 216012 kb
Host smart-0b05fc17-6f8f-41af-bc54-ce689a9c00f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845522847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1845522847
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/16.edn_intr.3911448318
Short name T157
Test name
Test status
Simulation time 27689610 ps
CPU time 0.95 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:09 PM PDT 24
Peak memory 215360 kb
Host smart-811f9453-eb16-4ace-bdce-0c5b14433fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911448318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3911448318
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2169901610
Short name T842
Test name
Test status
Simulation time 71028209 ps
CPU time 1.06 seconds
Started May 21 02:12:46 PM PDT 24
Finished May 21 02:12:51 PM PDT 24
Peak memory 219200 kb
Host smart-d42f8cfb-c08f-41d3-bcf2-c07d387b3b43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169901610 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2169901610
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1703890282
Short name T117
Test name
Test status
Simulation time 62409791 ps
CPU time 1.13 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:52 PM PDT 24
Peak memory 216520 kb
Host smart-4d6d2094-b227-4bee-a848-61c1daba1fcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703890282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1703890282
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1080455368
Short name T98
Test name
Test status
Simulation time 93388280 ps
CPU time 1.32 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:13:58 PM PDT 24
Peak memory 216748 kb
Host smart-15d8584a-b6d4-458e-a192-7eba49197e8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080455368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1080455368
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.178781659
Short name T140
Test name
Test status
Simulation time 28613159 ps
CPU time 0.92 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 217784 kb
Host smart-3fafb9a6-bef9-4281-859d-31b0615b8cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178781659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.178781659
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.4244690437
Short name T525
Test name
Test status
Simulation time 81724331 ps
CPU time 1.05 seconds
Started May 21 02:14:27 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 216456 kb
Host smart-76a28024-2357-4bd0-af7f-ac492de24eb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244690437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.4244690437
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2688516246
Short name T102
Test name
Test status
Simulation time 53568460 ps
CPU time 1.15 seconds
Started May 21 02:14:53 PM PDT 24
Finished May 21 02:15:00 PM PDT 24
Peak memory 216724 kb
Host smart-91ecabf3-5da9-4457-bd28-f23bcf9513fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688516246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2688516246
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.3495459355
Short name T83
Test name
Test status
Simulation time 153325058 ps
CPU time 1.64 seconds
Started May 21 02:15:01 PM PDT 24
Finished May 21 02:15:12 PM PDT 24
Peak memory 218160 kb
Host smart-ba8890a3-c2a7-4d3d-8890-d784768283f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495459355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3495459355
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3918436371
Short name T168
Test name
Test status
Simulation time 55908759 ps
CPU time 1 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 214604 kb
Host smart-59322948-7cf6-4ff9-8526-80b3b0affa88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918436371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3918436371
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/162.edn_genbits.2775815083
Short name T273
Test name
Test status
Simulation time 35041403 ps
CPU time 1.11 seconds
Started May 21 02:24:07 PM PDT 24
Finished May 21 02:24:10 PM PDT 24
Peak memory 218000 kb
Host smart-8cc96e42-915a-48d4-a8fa-959bb51d39f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775815083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2775815083
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_genbits.3590329588
Short name T271
Test name
Test status
Simulation time 49573590 ps
CPU time 1.44 seconds
Started May 21 02:20:02 PM PDT 24
Finished May 21 02:20:05 PM PDT 24
Peak memory 218276 kb
Host smart-78355066-b748-471c-b8a2-0b6cc597b6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590329588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3590329588
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_alert.3530846188
Short name T29
Test name
Test status
Simulation time 100323972 ps
CPU time 1.29 seconds
Started May 21 02:16:07 PM PDT 24
Finished May 21 02:16:13 PM PDT 24
Peak memory 215284 kb
Host smart-8afb046c-d665-48f5-af25-ceb1c31726f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530846188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3530846188
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/274.edn_genbits.3378306714
Short name T565
Test name
Test status
Simulation time 114523213 ps
CPU time 1.38 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 217968 kb
Host smart-b5a330fb-6a31-4cf5-864e-9f2f783df7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378306714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3378306714
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all.1446337388
Short name T270
Test name
Test status
Simulation time 176780610 ps
CPU time 4.25 seconds
Started May 21 02:12:47 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 216588 kb
Host smart-6c78152b-9d02-4042-8f14-93c5a61e3739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446337388 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1446337388
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_regwen.1167382149
Short name T26
Test name
Test status
Simulation time 78341339 ps
CPU time 0.93 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:27 PM PDT 24
Peak memory 206820 kb
Host smart-2d8afbf2-95db-43a3-923b-2baa60267270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167382149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1167382149
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/94.edn_genbits.1465579072
Short name T222
Test name
Test status
Simulation time 681428139 ps
CPU time 5.55 seconds
Started May 21 02:21:47 PM PDT 24
Finished May 21 02:21:54 PM PDT 24
Peak memory 219712 kb
Host smart-c221abee-e295-4a8b-bc9f-25bf72d9da5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465579072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1465579072
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3859929554
Short name T21
Test name
Test status
Simulation time 87995012 ps
CPU time 1.26 seconds
Started May 21 02:24:30 PM PDT 24
Finished May 21 02:24:33 PM PDT 24
Peak memory 219132 kb
Host smart-1eee7d02-4c21-43aa-a9b4-9c24576f4e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859929554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3859929554
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1759349677
Short name T36
Test name
Test status
Simulation time 36773710 ps
CPU time 0.87 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:14:04 PM PDT 24
Peak memory 215180 kb
Host smart-10860c85-7a36-4dcd-baf3-ec5ce401ebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759349677 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1759349677
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/108.edn_genbits.1302024369
Short name T89
Test name
Test status
Simulation time 54241223 ps
CPU time 2.26 seconds
Started May 21 02:22:41 PM PDT 24
Finished May 21 02:22:44 PM PDT 24
Peak memory 217952 kb
Host smart-a4cb7459-54bc-4ae3-a2c3-4ac760b20250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302024369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1302024369
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_genbits.2389002406
Short name T279
Test name
Test status
Simulation time 74674070 ps
CPU time 1.58 seconds
Started May 21 02:22:07 PM PDT 24
Finished May 21 02:22:09 PM PDT 24
Peak memory 219448 kb
Host smart-5b0c628a-8a5e-4ef9-abbe-6fec25b4de02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389002406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2389002406
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2495044828
Short name T237
Test name
Test status
Simulation time 45957406 ps
CPU time 1.2 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 206040 kb
Host smart-7d13ce39-ba3e-473d-ad3c-dc25144edbfa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495044828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2495044828
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1614406357
Short name T248
Test name
Test status
Simulation time 20673514 ps
CPU time 0.87 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 206180 kb
Host smart-19788ce8-4102-4a11-bcb8-9e817c77d43b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614406357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1614406357
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.803181847
Short name T933
Test name
Test status
Simulation time 258159864 ps
CPU time 2.58 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:23 PM PDT 24
Peak memory 206216 kb
Host smart-1a58fb87-92d3-4760-b6b0-4f774ff7a77e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803181847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.803181847
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all.1273739133
Short name T701
Test name
Test status
Simulation time 164057769 ps
CPU time 3.62 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:49 PM PDT 24
Peak memory 214996 kb
Host smart-37be9ce0-51f1-47f4-99eb-b5383a4bf07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273739133 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1273739133
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3043412211
Short name T739
Test name
Test status
Simulation time 62343753135 ps
CPU time 1047.12 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:31:03 PM PDT 24
Peak memory 220224 kb
Host smart-abf8b233-0e8f-46c4-b54c-391ca6408cde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043412211 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3043412211
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.edn_genbits.568020675
Short name T475
Test name
Test status
Simulation time 56120240 ps
CPU time 1.13 seconds
Started May 21 02:22:29 PM PDT 24
Finished May 21 02:22:31 PM PDT 24
Peak memory 216776 kb
Host smart-c2ddf8b7-c82f-4c67-86bf-62876e1e4840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568020675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.568020675
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.716322527
Short name T751
Test name
Test status
Simulation time 29891730 ps
CPU time 1.24 seconds
Started May 21 02:23:41 PM PDT 24
Finished May 21 02:23:44 PM PDT 24
Peak memory 217744 kb
Host smart-8c8c5787-9b06-4acd-aa9b-c2f9228bf560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716322527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.716322527
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_err.1068702732
Short name T54
Test name
Test status
Simulation time 23120454 ps
CPU time 1.21 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:13:58 PM PDT 24
Peak memory 223432 kb
Host smart-14b3c03a-b7ea-42aa-9113-766861d03185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068702732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1068702732
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/242.edn_genbits.1440874488
Short name T274
Test name
Test status
Simulation time 206001051 ps
CPU time 2.9 seconds
Started May 21 02:24:51 PM PDT 24
Finished May 21 02:24:55 PM PDT 24
Peak memory 219272 kb
Host smart-a863b6be-72a0-484f-a791-00fd60c9f9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440874488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1440874488
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_alert.210019772
Short name T165
Test name
Test status
Simulation time 26754614 ps
CPU time 1.21 seconds
Started May 21 02:17:51 PM PDT 24
Finished May 21 02:17:53 PM PDT 24
Peak memory 215456 kb
Host smart-2d687c23-6f03-430d-a1a0-dce56ed7d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210019772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.210019772
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/26.edn_intr.496204063
Short name T33
Test name
Test status
Simulation time 67563002 ps
CPU time 0.86 seconds
Started May 21 02:14:30 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 214976 kb
Host smart-6ef7d715-4d6f-4879-a56a-7153af938cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496204063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.496204063
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/17.edn_disable.2363756473
Short name T122
Test name
Test status
Simulation time 23311354 ps
CPU time 0.91 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 216032 kb
Host smart-0e5ee3ea-8762-40f1-9695-b3ac94f692da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363756473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2363756473
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.4112496603
Short name T965
Test name
Test status
Simulation time 70451151 ps
CPU time 0.95 seconds
Started May 21 01:12:54 PM PDT 24
Finished May 21 01:12:57 PM PDT 24
Peak memory 206132 kb
Host smart-81bcb8ec-bfe7-4980-9c2b-cf3bc7b4117d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112496603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.4112496603
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1332618830
Short name T857
Test name
Test status
Simulation time 25017958 ps
CPU time 0.94 seconds
Started May 21 01:13:05 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 206224 kb
Host smart-eb77dcf3-6123-42d8-b173-585411a8d5cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332618830 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1332618830
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1607490613
Short name T956
Test name
Test status
Simulation time 24736198 ps
CPU time 0.91 seconds
Started May 21 01:13:05 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 206224 kb
Host smart-899d9b53-eb16-4d2d-bf4d-685e46322f2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607490613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1607490613
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1007057616
Short name T884
Test name
Test status
Simulation time 29451984 ps
CPU time 0.77 seconds
Started May 21 01:12:58 PM PDT 24
Finished May 21 01:13:00 PM PDT 24
Peak memory 205924 kb
Host smart-f530ac8e-43db-4fd0-8907-26f114585ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007057616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1007057616
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3783269752
Short name T960
Test name
Test status
Simulation time 135778204 ps
CPU time 1.14 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 206084 kb
Host smart-b7933e55-9d19-4ec4-b3eb-0732dbe3f497
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783269752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3783269752
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1963579373
Short name T862
Test name
Test status
Simulation time 30374460 ps
CPU time 2.05 seconds
Started May 21 01:13:00 PM PDT 24
Finished May 21 01:13:03 PM PDT 24
Peak memory 214392 kb
Host smart-4365986b-1ff3-4468-9ee6-ce4a1c6c8cf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963579373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1963579373
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1414968561
Short name T888
Test name
Test status
Simulation time 73351035 ps
CPU time 2.02 seconds
Started May 21 01:12:55 PM PDT 24
Finished May 21 01:12:59 PM PDT 24
Peak memory 206188 kb
Host smart-aa4b84c3-f819-4c0c-ad7f-01c74e4f5874
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414968561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1414968561
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3975181718
Short name T238
Test name
Test status
Simulation time 62899163 ps
CPU time 1.25 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 206184 kb
Host smart-886a0dcb-72b6-4dbd-89c2-f6f3002bd978
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975181718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3975181718
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3254869467
Short name T916
Test name
Test status
Simulation time 171928269 ps
CPU time 5.09 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 206180 kb
Host smart-e9389d85-f90f-45ff-8660-1331be135e54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254869467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3254869467
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1186194092
Short name T890
Test name
Test status
Simulation time 55260215 ps
CPU time 0.93 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 206072 kb
Host smart-5621baaa-3fc2-44f6-b833-f14aede75352
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186194092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1186194092
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3487709866
Short name T869
Test name
Test status
Simulation time 41244674 ps
CPU time 1.16 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 214452 kb
Host smart-c665feac-0482-415d-8008-f2a697729316
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487709866 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3487709866
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.729360857
Short name T951
Test name
Test status
Simulation time 38702748 ps
CPU time 0.78 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205824 kb
Host smart-36b48cbf-c7f3-4459-aa7a-6fff6bbe0600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729360857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.729360857
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2915897916
Short name T955
Test name
Test status
Simulation time 33356241 ps
CPU time 1.46 seconds
Started May 21 01:13:01 PM PDT 24
Finished May 21 01:13:05 PM PDT 24
Peak memory 206236 kb
Host smart-c52e8f73-ff17-47a9-9627-248d491adf7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915897916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2915897916
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.282099965
Short name T891
Test name
Test status
Simulation time 194919028 ps
CPU time 2.13 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 214360 kb
Host smart-99cf28b9-7415-4837-8aa3-4904abdaa2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282099965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.282099965
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1497849402
Short name T875
Test name
Test status
Simulation time 16880122 ps
CPU time 1.2 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 214444 kb
Host smart-3844349c-e4c9-4328-848d-70b21dfec242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497849402 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1497849402
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1015044852
Short name T243
Test name
Test status
Simulation time 65211560 ps
CPU time 0.9 seconds
Started May 21 01:13:15 PM PDT 24
Finished May 21 01:13:18 PM PDT 24
Peak memory 206200 kb
Host smart-35783973-f4ec-4914-bfcb-f9bb85658cae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015044852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1015044852
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2824839031
Short name T854
Test name
Test status
Simulation time 12748799 ps
CPU time 0.89 seconds
Started May 21 01:13:15 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 206052 kb
Host smart-fdca53ca-14e4-4dc6-a0b2-31d7cabbcff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824839031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2824839031
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2727335638
Short name T236
Test name
Test status
Simulation time 54581306 ps
CPU time 1.32 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:19 PM PDT 24
Peak memory 206184 kb
Host smart-85e3d537-fd2b-483d-80ac-73099a6eaa18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727335638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2727335638
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.4058679734
Short name T868
Test name
Test status
Simulation time 52411017 ps
CPU time 3.56 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 214340 kb
Host smart-004de514-fc18-4bc1-97ff-889c0bd5455a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058679734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.4058679734
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3787912225
Short name T977
Test name
Test status
Simulation time 666592973 ps
CPU time 1.51 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206188 kb
Host smart-69bd8d37-d532-4f33-8e51-b710a6eccaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787912225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3787912225
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.696801821
Short name T908
Test name
Test status
Simulation time 29352497 ps
CPU time 1.6 seconds
Started May 21 01:13:20 PM PDT 24
Finished May 21 01:13:23 PM PDT 24
Peak memory 214460 kb
Host smart-d0b55e73-3cf9-4076-885c-97b8755e40cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696801821 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.696801821
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4187980377
Short name T941
Test name
Test status
Simulation time 52895087 ps
CPU time 0.99 seconds
Started May 21 01:13:14 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 206160 kb
Host smart-fcf866b4-8cae-43b4-a0bb-648c9b638068
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187980377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4187980377
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4090630139
Short name T856
Test name
Test status
Simulation time 11927381 ps
CPU time 0.85 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:20 PM PDT 24
Peak memory 206024 kb
Host smart-3bfcb51f-f83b-4a06-ac0a-19c6ef3945e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090630139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4090630139
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3823381085
Short name T249
Test name
Test status
Simulation time 114932591 ps
CPU time 0.99 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206088 kb
Host smart-64a2ad48-99d9-4b44-953e-bff2b271b573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823381085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3823381085
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2503440048
Short name T858
Test name
Test status
Simulation time 43021532 ps
CPU time 1.78 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 214368 kb
Host smart-fef45f08-3389-4c68-a7ee-786ca344e3d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503440048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2503440048
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.106183107
Short name T939
Test name
Test status
Simulation time 32225763 ps
CPU time 1.41 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 217540 kb
Host smart-dbafab8e-ec1b-4119-9f77-173f6dbbedec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106183107 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.106183107
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.482244735
Short name T253
Test name
Test status
Simulation time 15915214 ps
CPU time 0.91 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:18 PM PDT 24
Peak memory 206156 kb
Host smart-8bf396f5-e128-4292-9e45-54db12765751
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482244735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.482244735
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.4013199017
Short name T966
Test name
Test status
Simulation time 104882099 ps
CPU time 0.84 seconds
Started May 21 01:13:15 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 205968 kb
Host smart-e6f5f42a-23d7-4bce-857c-62efb7232985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013199017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4013199017
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2101834456
Short name T913
Test name
Test status
Simulation time 32173684 ps
CPU time 1.01 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:18 PM PDT 24
Peak memory 206156 kb
Host smart-c16ee021-4e42-4ac8-8da4-f61c515c736b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101834456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2101834456
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1347467932
Short name T904
Test name
Test status
Simulation time 103066381 ps
CPU time 4.31 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 214456 kb
Host smart-f8fdd727-c1e9-4352-99d0-5680264c9d74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347467932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1347467932
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4265719980
Short name T974
Test name
Test status
Simulation time 373482048 ps
CPU time 2.56 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 214376 kb
Host smart-19fc52e8-daf6-4c73-8abf-a00258b81311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265719980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4265719980
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1869619555
Short name T870
Test name
Test status
Simulation time 26421610 ps
CPU time 1.5 seconds
Started May 21 01:13:20 PM PDT 24
Finished May 21 01:13:23 PM PDT 24
Peak memory 214464 kb
Host smart-0f7ac876-1b46-4b35-994b-3604670e86ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869619555 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1869619555
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2447421849
Short name T228
Test name
Test status
Simulation time 28099095 ps
CPU time 0.94 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 206104 kb
Host smart-f39316dd-0cc4-40d3-a925-16f1bf5093a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447421849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2447421849
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1921833050
Short name T880
Test name
Test status
Simulation time 39749100 ps
CPU time 0.9 seconds
Started May 21 01:13:15 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 205956 kb
Host smart-bda09c1e-0bdd-4140-89b9-92e57f410d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921833050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1921833050
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.534366669
Short name T935
Test name
Test status
Simulation time 42115717 ps
CPU time 1.16 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206196 kb
Host smart-59121291-f67a-4d65-8970-2c73e20eb952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534366669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.534366669
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2500170556
Short name T879
Test name
Test status
Simulation time 155156267 ps
CPU time 3.02 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 214436 kb
Host smart-fc778d8b-bcea-4a05-ac3f-7999dde7165f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500170556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2500170556
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.200604918
Short name T265
Test name
Test status
Simulation time 236904387 ps
CPU time 1.59 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206184 kb
Host smart-78464dfb-b429-4993-bb9c-39828bc357d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200604918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.200604918
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.339520500
Short name T978
Test name
Test status
Simulation time 17887429 ps
CPU time 1.03 seconds
Started May 21 01:13:15 PM PDT 24
Finished May 21 01:13:18 PM PDT 24
Peak memory 214408 kb
Host smart-af7a144c-727d-4c4f-bedd-b01b1231fcc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339520500 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.339520500
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1481746452
Short name T881
Test name
Test status
Simulation time 19045583 ps
CPU time 0.82 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206064 kb
Host smart-b1080036-5b19-4a3f-b9e9-85bfdebb949e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481746452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1481746452
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.393168689
Short name T876
Test name
Test status
Simulation time 21264743 ps
CPU time 0.86 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:20 PM PDT 24
Peak memory 206028 kb
Host smart-a599a135-8fba-4536-a07a-ec17002e1de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393168689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.393168689
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2235151345
Short name T246
Test name
Test status
Simulation time 17214878 ps
CPU time 1.17 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:20 PM PDT 24
Peak memory 206100 kb
Host smart-dfdad155-7187-4c97-adb6-4e5c999f5594
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235151345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2235151345
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2539305827
Short name T886
Test name
Test status
Simulation time 205201266 ps
CPU time 3.55 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 214384 kb
Host smart-63dfd689-7303-4173-9efe-becc5ce1f25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539305827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2539305827
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1028471312
Short name T256
Test name
Test status
Simulation time 156289449 ps
CPU time 1.59 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206408 kb
Host smart-f3e8e1b5-e691-47ab-81a3-c4f36d7efae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028471312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1028471312
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2090511917
Short name T873
Test name
Test status
Simulation time 95172861 ps
CPU time 1.63 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 214472 kb
Host smart-6b0accf8-d357-4b4e-8eb1-87e7bba8ed3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090511917 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2090511917
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.177839975
Short name T961
Test name
Test status
Simulation time 23752532 ps
CPU time 0.91 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:21 PM PDT 24
Peak memory 206156 kb
Host smart-3369044a-55f1-41ee-a63a-e41ab265abf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177839975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.177839975
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2429937367
Short name T915
Test name
Test status
Simulation time 42501444 ps
CPU time 0.89 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 205960 kb
Host smart-0fbccc74-2d7f-420e-8cb6-137aed1961b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429937367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2429937367
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4044278336
Short name T235
Test name
Test status
Simulation time 83298406 ps
CPU time 1.1 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206208 kb
Host smart-56e24722-bb4d-423d-8468-61f45d8e70f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044278336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4044278336
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1050615629
Short name T958
Test name
Test status
Simulation time 92717117 ps
CPU time 3.37 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 214372 kb
Host smart-4c8959a0-7262-4e5b-a3fa-195698b0d698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050615629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1050615629
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2865582211
Short name T907
Test name
Test status
Simulation time 52041170 ps
CPU time 1.8 seconds
Started May 21 01:13:19 PM PDT 24
Finished May 21 01:13:23 PM PDT 24
Peak memory 214380 kb
Host smart-0987bb27-3407-4bfd-8015-2f627527f924
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865582211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2865582211
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2526207683
Short name T976
Test name
Test status
Simulation time 52489853 ps
CPU time 1.39 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 214484 kb
Host smart-e28712c4-db6a-4c96-b8e9-882443c58c21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526207683 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2526207683
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.4178642538
Short name T240
Test name
Test status
Simulation time 53038223 ps
CPU time 0.84 seconds
Started May 21 01:13:24 PM PDT 24
Finished May 21 01:13:27 PM PDT 24
Peak memory 206120 kb
Host smart-1cd01091-b511-43ee-8af7-ca1a1454ddd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178642538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.4178642538
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3513179212
Short name T963
Test name
Test status
Simulation time 23835528 ps
CPU time 0.85 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 205980 kb
Host smart-b54c3699-a524-478c-882f-d307dcdc10f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513179212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3513179212
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1267751927
Short name T878
Test name
Test status
Simulation time 27944935 ps
CPU time 1.1 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 206240 kb
Host smart-1871802b-49b0-4c8f-bf04-d7887f150d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267751927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1267751927
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1562978020
Short name T926
Test name
Test status
Simulation time 105138846 ps
CPU time 3.01 seconds
Started May 21 01:13:20 PM PDT 24
Finished May 21 01:13:25 PM PDT 24
Peak memory 214444 kb
Host smart-1ccecce6-0fd3-4223-9034-5b442ec57bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562978020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1562978020
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3644281782
Short name T971
Test name
Test status
Simulation time 249266060 ps
CPU time 1.6 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:20 PM PDT 24
Peak memory 206368 kb
Host smart-c9815883-9d99-41ae-8dbc-d08d0c3f674d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644281782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3644281782
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2689770051
Short name T900
Test name
Test status
Simulation time 66102337 ps
CPU time 1.57 seconds
Started May 21 01:13:24 PM PDT 24
Finished May 21 01:13:28 PM PDT 24
Peak memory 214424 kb
Host smart-77586f6e-639c-4cb7-9962-d731f6877c44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689770051 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2689770051
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3776179195
Short name T909
Test name
Test status
Simulation time 37316961 ps
CPU time 0.84 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 206168 kb
Host smart-8a02156b-d67b-41d9-b87f-fce028b682ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776179195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3776179195
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3668613885
Short name T903
Test name
Test status
Simulation time 15248012 ps
CPU time 0.81 seconds
Started May 21 01:13:23 PM PDT 24
Finished May 21 01:13:25 PM PDT 24
Peak memory 205956 kb
Host smart-c646ae48-f8b9-44f7-b96a-b76f3fd93f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668613885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3668613885
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1667300532
Short name T922
Test name
Test status
Simulation time 85132234 ps
CPU time 1.17 seconds
Started May 21 01:13:23 PM PDT 24
Finished May 21 01:13:26 PM PDT 24
Peak memory 206092 kb
Host smart-49111130-def1-4615-a6d3-786c34c304bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667300532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1667300532
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.795971223
Short name T853
Test name
Test status
Simulation time 298110672 ps
CPU time 3.03 seconds
Started May 21 01:13:25 PM PDT 24
Finished May 21 01:13:30 PM PDT 24
Peak memory 214344 kb
Host smart-c14536e8-3aa0-4de4-a9c2-bc84c358b4fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795971223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.795971223
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2959347343
Short name T254
Test name
Test status
Simulation time 132380534 ps
CPU time 1.63 seconds
Started May 21 01:13:25 PM PDT 24
Finished May 21 01:13:28 PM PDT 24
Peak memory 206208 kb
Host smart-26ee115e-4d42-43e6-9d1c-b04451dc6ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959347343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2959347343
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3468264889
Short name T906
Test name
Test status
Simulation time 53720466 ps
CPU time 1.53 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 214424 kb
Host smart-dc57331f-c6a4-4d09-8721-37ff93881730
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468264889 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3468264889
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.277402197
Short name T234
Test name
Test status
Simulation time 43525030 ps
CPU time 0.95 seconds
Started May 21 01:13:24 PM PDT 24
Finished May 21 01:13:26 PM PDT 24
Peak memory 206188 kb
Host smart-a7710c58-e152-449a-b31c-eb690afbe91c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277402197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.277402197
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3654656057
Short name T899
Test name
Test status
Simulation time 153780265 ps
CPU time 0.94 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206152 kb
Host smart-4d2950fc-d9aa-4b52-92ce-c69e4ab645eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654656057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3654656057
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.480718693
Short name T898
Test name
Test status
Simulation time 37496543 ps
CPU time 1.46 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206160 kb
Host smart-b8181499-d0fa-49c3-b602-d5d3f47713ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480718693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.480718693
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2916657245
Short name T970
Test name
Test status
Simulation time 38331674 ps
CPU time 2.7 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:33 PM PDT 24
Peak memory 214484 kb
Host smart-4d0be705-bf21-4ebc-a27f-1247abed7ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916657245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2916657245
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4182164598
Short name T964
Test name
Test status
Simulation time 82520839 ps
CPU time 2.29 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206188 kb
Host smart-3d3c5374-c9ec-4c1b-a96a-e39aa7c8cf44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182164598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4182164598
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3644733148
Short name T892
Test name
Test status
Simulation time 56433924 ps
CPU time 1.44 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:25 PM PDT 24
Peak memory 214468 kb
Host smart-0a7588c3-c7ba-47ea-953e-38c396c3a251
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644733148 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3644733148
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1078157039
Short name T245
Test name
Test status
Simulation time 28921791 ps
CPU time 0.78 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 206048 kb
Host smart-31fbefff-5c51-4167-82e1-c64fce933f45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078157039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1078157039
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4008341917
Short name T927
Test name
Test status
Simulation time 14745216 ps
CPU time 0.95 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 206000 kb
Host smart-d3f336a9-7395-4d22-826e-ee49181e13ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008341917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4008341917
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.811898946
Short name T921
Test name
Test status
Simulation time 61126491 ps
CPU time 1.35 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206184 kb
Host smart-2fab81ec-b128-404b-9b64-491628c241f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811898946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.811898946
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1622638472
Short name T968
Test name
Test status
Simulation time 57985883 ps
CPU time 2.37 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 214344 kb
Host smart-a7d8d1e9-a5d0-4697-a449-8fc38adaa619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622638472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1622638472
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2364393274
Short name T263
Test name
Test status
Simulation time 156242941 ps
CPU time 2.51 seconds
Started May 21 01:13:23 PM PDT 24
Finished May 21 01:13:27 PM PDT 24
Peak memory 206240 kb
Host smart-1a8fc8ad-e40a-4752-a1f0-f1801c8f5730
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364393274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2364393274
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3735875390
Short name T938
Test name
Test status
Simulation time 123183335 ps
CPU time 1.42 seconds
Started May 21 01:13:06 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 206184 kb
Host smart-57331f46-3d54-44a5-bfa7-766557d77dbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735875390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3735875390
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1816188996
Short name T244
Test name
Test status
Simulation time 112479284 ps
CPU time 3.22 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 206156 kb
Host smart-06df1760-c7e6-4634-b5ba-38b4cd2f0f44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816188996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1816188996
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1224685196
Short name T241
Test name
Test status
Simulation time 31866922 ps
CPU time 1 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 206204 kb
Host smart-688414d5-8add-457b-9f9f-2bb2e2644dff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224685196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1224685196
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.423548569
Short name T917
Test name
Test status
Simulation time 30452155 ps
CPU time 1.04 seconds
Started May 21 01:13:01 PM PDT 24
Finished May 21 01:13:04 PM PDT 24
Peak memory 206252 kb
Host smart-bc7152ea-2dc5-42d1-9a7b-e4bd68063612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423548569 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.423548569
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3194047288
Short name T242
Test name
Test status
Simulation time 13193764 ps
CPU time 0.95 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 206164 kb
Host smart-b4773e65-08f2-48ed-a5d8-879f92d277f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194047288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3194047288
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1493416792
Short name T949
Test name
Test status
Simulation time 32601414 ps
CPU time 0.81 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205984 kb
Host smart-13501861-2d4f-4421-98d0-a97bf73a5abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493416792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1493416792
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1891930252
Short name T231
Test name
Test status
Simulation time 20877034 ps
CPU time 1.05 seconds
Started May 21 01:13:11 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206196 kb
Host smart-ffbc48ca-db4b-4d85-bf41-bdc6b98bc753
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891930252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1891930252
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4136500042
Short name T848
Test name
Test status
Simulation time 63575795 ps
CPU time 1.76 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 214384 kb
Host smart-6dfe1631-6362-43e9-b743-66f588ebca0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136500042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4136500042
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2848799688
Short name T929
Test name
Test status
Simulation time 126758419 ps
CPU time 1.65 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 214304 kb
Host smart-0d9fc3f6-11da-4562-b1c1-a096fd5a3dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848799688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2848799688
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2845000845
Short name T861
Test name
Test status
Simulation time 24434584 ps
CPU time 0.9 seconds
Started May 21 01:13:23 PM PDT 24
Finished May 21 01:13:25 PM PDT 24
Peak memory 206056 kb
Host smart-67733993-2387-4fe6-9249-784f684d28d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845000845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2845000845
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3365456112
Short name T877
Test name
Test status
Simulation time 35918281 ps
CPU time 0.9 seconds
Started May 21 01:13:22 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 206032 kb
Host smart-653427e4-7b47-4a3b-a9b8-14084511cbf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365456112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3365456112
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1264997670
Short name T865
Test name
Test status
Simulation time 44048032 ps
CPU time 0.93 seconds
Started May 21 01:13:21 PM PDT 24
Finished May 21 01:13:24 PM PDT 24
Peak memory 205928 kb
Host smart-8233b5a4-bc6c-4a3b-b3c4-9f6f60c2876a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264997670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1264997670
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3915491071
Short name T952
Test name
Test status
Simulation time 41343521 ps
CPU time 0.83 seconds
Started May 21 01:13:24 PM PDT 24
Finished May 21 01:13:26 PM PDT 24
Peak memory 205972 kb
Host smart-52c96c8c-e71b-4aa7-b2e0-481d6b95844e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915491071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3915491071
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3473627789
Short name T867
Test name
Test status
Simulation time 22159985 ps
CPU time 0.88 seconds
Started May 21 01:13:23 PM PDT 24
Finished May 21 01:13:26 PM PDT 24
Peak memory 206072 kb
Host smart-6011ce30-6833-4ad6-91b4-129cd382a195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473627789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3473627789
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3916984544
Short name T893
Test name
Test status
Simulation time 85193338 ps
CPU time 0.86 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206152 kb
Host smart-37154c98-8567-4c08-bba2-1bb209193a44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916984544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3916984544
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3601640525
Short name T957
Test name
Test status
Simulation time 30211914 ps
CPU time 0.89 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 206016 kb
Host smart-8c151aa6-f36a-4df7-b772-c332987d5f38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601640525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3601640525
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.903363219
Short name T953
Test name
Test status
Simulation time 19608231 ps
CPU time 0.89 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 205976 kb
Host smart-2dcf4ff7-e27e-48f5-9e40-a3b60dbf7460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903363219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.903363219
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4137595447
Short name T934
Test name
Test status
Simulation time 67468984 ps
CPU time 0.79 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 205952 kb
Host smart-22ddf75b-f553-42cf-a880-1a8b29f7d96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137595447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4137595447
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3804414029
Short name T920
Test name
Test status
Simulation time 27524737 ps
CPU time 0.94 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:30 PM PDT 24
Peak memory 205968 kb
Host smart-bdece704-0846-40fc-9118-494761bfd1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804414029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3804414029
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1301201485
Short name T930
Test name
Test status
Simulation time 77839609 ps
CPU time 1.15 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 206160 kb
Host smart-36887d6c-9a1b-4f5d-a0c8-e85725c54477
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301201485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1301201485
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1662211222
Short name T895
Test name
Test status
Simulation time 85166485 ps
CPU time 2.05 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 206120 kb
Host smart-841faed4-57f3-43d7-ab6c-024ec5e37642
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662211222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1662211222
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2121642625
Short name T239
Test name
Test status
Simulation time 16033243 ps
CPU time 0.97 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 206388 kb
Host smart-b2bdf209-fa5e-492f-98b5-6fd2c344c5e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121642625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2121642625
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.285912487
Short name T905
Test name
Test status
Simulation time 91078889 ps
CPU time 1.41 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:07 PM PDT 24
Peak memory 214440 kb
Host smart-09e63776-eebd-4741-b5f9-08be92305591
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285912487 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.285912487
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.52517057
Short name T979
Test name
Test status
Simulation time 44386244 ps
CPU time 0.9 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 206296 kb
Host smart-42603a18-cb52-4526-b47c-841d67e3ddee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52517057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.52517057
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1008121513
Short name T860
Test name
Test status
Simulation time 127064546 ps
CPU time 0.79 seconds
Started May 21 01:13:05 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 205924 kb
Host smart-0b423777-50dd-4e85-89ce-82c83f890808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008121513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1008121513
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2972612581
Short name T943
Test name
Test status
Simulation time 15063966 ps
CPU time 0.97 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 206244 kb
Host smart-153abfc5-d354-45bf-bee3-40727be8d668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972612581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2972612581
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.4162655458
Short name T863
Test name
Test status
Simulation time 82184733 ps
CPU time 2.87 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 214392 kb
Host smart-521e0560-628b-4a63-96c0-c277b6be0c00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162655458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4162655458
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1278131327
Short name T914
Test name
Test status
Simulation time 70614801 ps
CPU time 1.66 seconds
Started May 21 01:13:05 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 214412 kb
Host smart-753f91d8-21e2-4e25-bbe5-15720094f7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278131327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1278131327
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2126744426
Short name T871
Test name
Test status
Simulation time 13260316 ps
CPU time 0.88 seconds
Started May 21 01:13:26 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 206080 kb
Host smart-ab54071e-7ea7-4a12-b8d3-0c0aef4db4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126744426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2126744426
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1944793094
Short name T885
Test name
Test status
Simulation time 19952428 ps
CPU time 0.82 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 205996 kb
Host smart-4fde1ab7-080c-47c2-a586-c460edbe2ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944793094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1944793094
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.205099542
Short name T969
Test name
Test status
Simulation time 19454555 ps
CPU time 0.89 seconds
Started May 21 01:13:30 PM PDT 24
Finished May 21 01:13:33 PM PDT 24
Peak memory 206024 kb
Host smart-077130f9-e04b-4dd6-a162-e7d01308c391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205099542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.205099542
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2487592874
Short name T894
Test name
Test status
Simulation time 14076394 ps
CPU time 0.89 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 206044 kb
Host smart-6493bae1-99b3-4ac0-959f-cf193557cec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487592874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2487592874
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3323098929
Short name T975
Test name
Test status
Simulation time 14215212 ps
CPU time 0.9 seconds
Started May 21 01:13:29 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206024 kb
Host smart-478e9422-8c8e-42de-b38e-91d41b16f9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323098929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3323098929
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1109280305
Short name T851
Test name
Test status
Simulation time 20129055 ps
CPU time 1 seconds
Started May 21 01:13:26 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 206068 kb
Host smart-baadbee1-c364-4725-8752-e58b6cbf7e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109280305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1109280305
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2839071110
Short name T944
Test name
Test status
Simulation time 113470651 ps
CPU time 0.91 seconds
Started May 21 01:13:25 PM PDT 24
Finished May 21 01:13:28 PM PDT 24
Peak memory 205956 kb
Host smart-208779f3-6528-46ac-9107-37839faf4559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839071110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2839071110
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2234388987
Short name T950
Test name
Test status
Simulation time 56915732 ps
CPU time 0.79 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 205908 kb
Host smart-ffafd70a-c787-4cbd-b7e1-a342c71c91bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234388987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2234388987
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.484713168
Short name T946
Test name
Test status
Simulation time 15001533 ps
CPU time 0.89 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:30 PM PDT 24
Peak memory 206088 kb
Host smart-8234d5c8-be80-441d-82fe-2d4be41b6756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484713168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.484713168
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4255304968
Short name T948
Test name
Test status
Simulation time 15268043 ps
CPU time 0.97 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206060 kb
Host smart-a7f8bbd6-dc68-4107-b4be-e8d9ec3ab1cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255304968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4255304968
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.171461992
Short name T251
Test name
Test status
Simulation time 46128833 ps
CPU time 1.22 seconds
Started May 21 01:13:02 PM PDT 24
Finished May 21 01:13:06 PM PDT 24
Peak memory 206188 kb
Host smart-3900af71-df98-4f93-8a21-1c4ba735e423
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171461992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.171461992
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.51755600
Short name T918
Test name
Test status
Simulation time 346108501 ps
CPU time 5.2 seconds
Started May 21 01:13:05 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206216 kb
Host smart-de4e07a0-f7d0-49f8-a66b-fb6bb43c9d1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51755600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.51755600
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1776180756
Short name T252
Test name
Test status
Simulation time 20734938 ps
CPU time 0.86 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:09 PM PDT 24
Peak memory 206220 kb
Host smart-6071714c-d6c0-4fae-81bc-acc5e4032d0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776180756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1776180756
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.17785438
Short name T925
Test name
Test status
Simulation time 65960627 ps
CPU time 1.6 seconds
Started May 21 01:13:06 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 214444 kb
Host smart-289b6b47-57a6-4c3a-a99c-96d06d30033c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785438 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.17785438
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1499939280
Short name T230
Test name
Test status
Simulation time 14345152 ps
CPU time 0.93 seconds
Started May 21 01:13:04 PM PDT 24
Finished May 21 01:13:08 PM PDT 24
Peak memory 206212 kb
Host smart-0a2e4e91-e5eb-40ad-96e9-bd95e550294e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499939280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1499939280
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3564875082
Short name T864
Test name
Test status
Simulation time 22009642 ps
CPU time 0.82 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 205848 kb
Host smart-9a6c2232-b683-4af2-b48f-4a14ec041906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564875082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3564875082
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.237692050
Short name T937
Test name
Test status
Simulation time 91631224 ps
CPU time 1.01 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206112 kb
Host smart-7dcb31b5-5c0c-4540-8543-5547991d8837
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237692050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.237692050
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3496650376
Short name T866
Test name
Test status
Simulation time 175359478 ps
CPU time 3.74 seconds
Started May 21 01:13:03 PM PDT 24
Finished May 21 01:13:10 PM PDT 24
Peak memory 214332 kb
Host smart-309ba405-6ed5-4bdd-9c41-1b49ef87d8b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496650376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3496650376
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2985448038
Short name T919
Test name
Test status
Simulation time 107886366 ps
CPU time 1.68 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206132 kb
Host smart-a0501a8e-5954-41ef-99cd-3adb94ba01cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985448038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2985448038
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3009819165
Short name T901
Test name
Test status
Simulation time 17247811 ps
CPU time 0.94 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 206176 kb
Host smart-d5a782ef-49ad-4f09-a01c-daeadc8829ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009819165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3009819165
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3726336597
Short name T850
Test name
Test status
Simulation time 15135759 ps
CPU time 0.88 seconds
Started May 21 01:13:26 PM PDT 24
Finished May 21 01:13:28 PM PDT 24
Peak memory 206024 kb
Host smart-06949aad-a733-42bc-aca7-a4596a390cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726336597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3726336597
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1462496285
Short name T911
Test name
Test status
Simulation time 25641448 ps
CPU time 0.88 seconds
Started May 21 01:13:29 PM PDT 24
Finished May 21 01:13:32 PM PDT 24
Peak memory 206040 kb
Host smart-012f09b8-b1b9-449b-b439-deae2d608288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462496285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1462496285
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3822848534
Short name T910
Test name
Test status
Simulation time 15555021 ps
CPU time 0.82 seconds
Started May 21 01:13:28 PM PDT 24
Finished May 21 01:13:31 PM PDT 24
Peak memory 206016 kb
Host smart-2e898e2b-40b6-4e07-8314-4e83736d3e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822848534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3822848534
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1833111523
Short name T872
Test name
Test status
Simulation time 25788718 ps
CPU time 0.81 seconds
Started May 21 01:13:27 PM PDT 24
Finished May 21 01:13:29 PM PDT 24
Peak memory 205980 kb
Host smart-081c3544-f079-4fef-ac4f-81d04436b202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833111523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1833111523
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3533324302
Short name T940
Test name
Test status
Simulation time 19254538 ps
CPU time 0.94 seconds
Started May 21 01:13:36 PM PDT 24
Finished May 21 01:13:37 PM PDT 24
Peak memory 206076 kb
Host smart-d42a12aa-02a2-4fc8-91d0-d9a2bc5095b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533324302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3533324302
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3072227967
Short name T942
Test name
Test status
Simulation time 85908592 ps
CPU time 0.84 seconds
Started May 21 01:13:38 PM PDT 24
Finished May 21 01:13:39 PM PDT 24
Peak memory 205952 kb
Host smart-dffb8dd6-88c1-4869-b715-539e5901b7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072227967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3072227967
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2518219529
Short name T936
Test name
Test status
Simulation time 38553412 ps
CPU time 0.84 seconds
Started May 21 01:13:34 PM PDT 24
Finished May 21 01:13:35 PM PDT 24
Peak memory 206080 kb
Host smart-a3ff1792-5d77-41c5-8b1a-60fcfff99afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518219529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2518219529
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2866552557
Short name T859
Test name
Test status
Simulation time 30783803 ps
CPU time 0.8 seconds
Started May 21 01:13:34 PM PDT 24
Finished May 21 01:13:35 PM PDT 24
Peak memory 205944 kb
Host smart-8aec14cd-9cc5-46ad-8524-e6a2c5169a28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866552557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2866552557
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3597673722
Short name T972
Test name
Test status
Simulation time 34748989 ps
CPU time 0.82 seconds
Started May 21 01:13:36 PM PDT 24
Finished May 21 01:13:37 PM PDT 24
Peak memory 205876 kb
Host smart-ad2b9c6d-f5b1-4e00-8809-352634ca1cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597673722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3597673722
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1899385519
Short name T962
Test name
Test status
Simulation time 25566839 ps
CPU time 1.08 seconds
Started May 21 01:13:07 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 206340 kb
Host smart-f5d7bcfc-5c7f-4cd2-87b1-d5c3f9ecf92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899385519 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1899385519
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2032944417
Short name T967
Test name
Test status
Simulation time 12021305 ps
CPU time 0.83 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 206136 kb
Host smart-9d60314d-c60d-45a7-a20c-4dda298cf495
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032944417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2032944417
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.465967591
Short name T931
Test name
Test status
Simulation time 18348964 ps
CPU time 0.8 seconds
Started May 21 01:13:01 PM PDT 24
Finished May 21 01:13:04 PM PDT 24
Peak memory 205984 kb
Host smart-070a1552-0bb8-4468-8105-5af26dc8c02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465967591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.465967591
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2850412944
Short name T233
Test name
Test status
Simulation time 362972355 ps
CPU time 1.41 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206208 kb
Host smart-9f7e5460-ed8a-4700-85ef-3e2035ba3bb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850412944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2850412944
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3170478041
Short name T883
Test name
Test status
Simulation time 48287037 ps
CPU time 1.88 seconds
Started May 21 01:13:06 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 214376 kb
Host smart-2ed4acc6-668a-475f-b1f5-2ea45b8a8aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170478041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3170478041
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.389656489
Short name T887
Test name
Test status
Simulation time 297984809 ps
CPU time 1.47 seconds
Started May 21 01:13:07 PM PDT 24
Finished May 21 01:13:11 PM PDT 24
Peak memory 214308 kb
Host smart-0f1c618e-5419-4413-9851-deb40a3b6682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389656489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.389656489
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.4236447777
Short name T855
Test name
Test status
Simulation time 42126472 ps
CPU time 1.6 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 214352 kb
Host smart-9d3f9d7e-f037-47a8-bb6f-25f270f73ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236447777 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.4236447777
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1388856298
Short name T882
Test name
Test status
Simulation time 22362953 ps
CPU time 0.87 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:13 PM PDT 24
Peak memory 206084 kb
Host smart-2ad4adf6-cde0-466e-94c2-0fc6e97a23dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388856298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1388856298
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3743337412
Short name T852
Test name
Test status
Simulation time 17067699 ps
CPU time 0.97 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206056 kb
Host smart-beb02a6a-228c-436c-bf4f-80c463a9ac87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743337412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3743337412
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2950659211
Short name T947
Test name
Test status
Simulation time 48761003 ps
CPU time 1.23 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206168 kb
Host smart-d61fc26f-51b9-4f54-9aa5-088245d3de2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950659211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2950659211
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2558738367
Short name T959
Test name
Test status
Simulation time 357167232 ps
CPU time 3.55 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:17 PM PDT 24
Peak memory 214320 kb
Host smart-af9207ca-1bac-43e1-abdc-1bcef2eb773a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558738367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2558738367
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2595595674
Short name T262
Test name
Test status
Simulation time 94020893 ps
CPU time 2.54 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206200 kb
Host smart-93df1357-5d4e-491a-8c79-87272d93877b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595595674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2595595674
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2112784848
Short name T849
Test name
Test status
Simulation time 45985479 ps
CPU time 1.21 seconds
Started May 21 01:13:07 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 214428 kb
Host smart-5345b237-1ea5-498d-8bcf-de613d43475b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112784848 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2112784848
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.953119335
Short name T896
Test name
Test status
Simulation time 34754556 ps
CPU time 0.82 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206092 kb
Host smart-7d9125d7-379c-460f-8f53-c178f28c4a58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953119335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.953119335
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.461856488
Short name T889
Test name
Test status
Simulation time 15180244 ps
CPU time 0.87 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 206072 kb
Host smart-d7fe1811-3b6a-49b5-8c6a-2b7425d0951e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461856488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.461856488
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1458345072
Short name T932
Test name
Test status
Simulation time 102580707 ps
CPU time 1.1 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:13 PM PDT 24
Peak memory 206204 kb
Host smart-526b8620-fd4f-445a-aab3-b69afbeeed2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458345072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1458345072
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3039062920
Short name T954
Test name
Test status
Simulation time 55430883 ps
CPU time 2.35 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 214472 kb
Host smart-3085a687-0f76-4040-a851-e76211b5d6f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039062920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3039062920
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2924139245
Short name T264
Test name
Test status
Simulation time 90251849 ps
CPU time 1.63 seconds
Started May 21 01:13:07 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 206200 kb
Host smart-203c1b1c-903e-42af-8fd3-53422669c15a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924139245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2924139245
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.113378720
Short name T874
Test name
Test status
Simulation time 33845670 ps
CPU time 1.09 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 216136 kb
Host smart-bff10616-0ddb-482e-94f3-ab8c2e31b7c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113378720 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.113378720
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2725528325
Short name T973
Test name
Test status
Simulation time 12126720 ps
CPU time 0.86 seconds
Started May 21 01:13:09 PM PDT 24
Finished May 21 01:13:13 PM PDT 24
Peak memory 206056 kb
Host smart-f0b3c364-7c80-47ee-917a-8ab470a41e36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725528325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2725528325
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3943015441
Short name T897
Test name
Test status
Simulation time 64888614 ps
CPU time 0.88 seconds
Started May 21 01:13:11 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206080 kb
Host smart-9c68cb2b-ac46-47f4-ab9d-0e5948872495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943015441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3943015441
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1455305565
Short name T928
Test name
Test status
Simulation time 38572758 ps
CPU time 1.17 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206200 kb
Host smart-3b1dc3d8-8455-4750-a72f-6f3f965d21a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455305565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1455305565
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1655145673
Short name T912
Test name
Test status
Simulation time 20356258 ps
CPU time 1.49 seconds
Started May 21 01:13:12 PM PDT 24
Finished May 21 01:13:16 PM PDT 24
Peak memory 214348 kb
Host smart-4095addf-3ab1-41a3-83b2-adbbebb3dd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655145673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1655145673
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.134715095
Short name T924
Test name
Test status
Simulation time 120105961 ps
CPU time 1.34 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:12 PM PDT 24
Peak memory 206204 kb
Host smart-3da59f54-21f7-4f71-9f28-f7d2e7e80d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134715095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.134715095
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2764874936
Short name T945
Test name
Test status
Simulation time 18736511 ps
CPU time 1.1 seconds
Started May 21 01:13:16 PM PDT 24
Finished May 21 01:13:19 PM PDT 24
Peak memory 206272 kb
Host smart-36e441b2-adc3-4758-8132-0b7964ab9188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764874936 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2764874936
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4241179837
Short name T232
Test name
Test status
Simulation time 50396500 ps
CPU time 0.92 seconds
Started May 21 01:13:17 PM PDT 24
Finished May 21 01:13:20 PM PDT 24
Peak memory 206164 kb
Host smart-5101d124-f136-4361-bb5e-f1af4e69d4fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241179837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4241179837
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1421391390
Short name T902
Test name
Test status
Simulation time 27266423 ps
CPU time 0.93 seconds
Started May 21 01:13:11 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206020 kb
Host smart-da8adfb5-1659-48ea-bd01-dfcfa40fc561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421391390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1421391390
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1781621777
Short name T247
Test name
Test status
Simulation time 62114050 ps
CPU time 1.09 seconds
Started May 21 01:13:18 PM PDT 24
Finished May 21 01:13:22 PM PDT 24
Peak memory 206204 kb
Host smart-dc73f431-6770-4be8-bcbd-36dfd385ce74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781621777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1781621777
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2500283390
Short name T923
Test name
Test status
Simulation time 38191144 ps
CPU time 2.72 seconds
Started May 21 01:13:08 PM PDT 24
Finished May 21 01:13:14 PM PDT 24
Peak memory 214380 kb
Host smart-b23455c7-7c7b-4f0e-817a-86ecd9c6f9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500283390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2500283390
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1387911017
Short name T261
Test name
Test status
Simulation time 176897469 ps
CPU time 1.57 seconds
Started May 21 01:13:10 PM PDT 24
Finished May 21 01:13:15 PM PDT 24
Peak memory 206192 kb
Host smart-e671d6f3-7e94-44b4-85ad-4cc606366d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387911017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1387911017
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.4198036312
Short name T295
Test name
Test status
Simulation time 25393070 ps
CPU time 1.24 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 215400 kb
Host smart-f212c36a-5097-4adc-a26f-e60a98c2ce5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198036312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.4198036312
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3009346844
Short name T423
Test name
Test status
Simulation time 37164821 ps
CPU time 0.83 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 206464 kb
Host smart-41b2235b-3164-47b0-ba1d-f0221ca753f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009346844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3009346844
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.3709255447
Short name T746
Test name
Test status
Simulation time 16863196 ps
CPU time 0.87 seconds
Started May 21 02:12:42 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 215096 kb
Host smart-fccdeb86-9f5e-4535-8322-9abe4f9cb3e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709255447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3709255447
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1373652654
Short name T433
Test name
Test status
Simulation time 58452067 ps
CPU time 1.27 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 215392 kb
Host smart-ccb9d3b4-04e2-43d8-89a3-5af1b9818b95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373652654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1373652654
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.61097444
Short name T184
Test name
Test status
Simulation time 27400223 ps
CPU time 0.95 seconds
Started May 21 02:12:41 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 223244 kb
Host smart-d811f5f9-2ae5-4376-adfe-91ba4dd4b83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61097444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.61097444
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4083178322
Short name T290
Test name
Test status
Simulation time 51149166 ps
CPU time 1.23 seconds
Started May 21 02:12:40 PM PDT 24
Finished May 21 02:12:47 PM PDT 24
Peak memory 217096 kb
Host smart-8dd941e2-8afc-425a-8979-cab6cf913752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083178322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4083178322
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.819211740
Short name T170
Test name
Test status
Simulation time 73471807 ps
CPU time 0.83 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 215100 kb
Host smart-a0819f56-01d2-458b-a840-4394425832f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819211740 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.819211740
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.833811636
Short name T25
Test name
Test status
Simulation time 97610939 ps
CPU time 0.88 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 206776 kb
Host smart-489eae31-a3a7-4f5a-8c84-b85a7396e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833811636 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.833811636
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.3486456010
Short name T313
Test name
Test status
Simulation time 35247700 ps
CPU time 0.88 seconds
Started May 21 02:12:43 PM PDT 24
Finished May 21 02:12:48 PM PDT 24
Peak memory 206752 kb
Host smart-eea4c5c8-cc2f-4df0-93d5-fb765db4f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486456010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3486456010
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_alert.3271727439
Short name T733
Test name
Test status
Simulation time 47612791 ps
CPU time 1.18 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 215360 kb
Host smart-a8ed5f5b-d29b-4949-8db3-f6e91bd8aa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271727439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3271727439
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3121557745
Short name T52
Test name
Test status
Simulation time 33762118 ps
CPU time 0.84 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 205648 kb
Host smart-f65fb685-ee1e-4a79-bb4e-3378ace4bda7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121557745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3121557745
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.717831913
Short name T506
Test name
Test status
Simulation time 11741608 ps
CPU time 0.9 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 216320 kb
Host smart-986d8022-287f-416d-bf9d-b14e8f4f642b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717831913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.717831913
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2301713340
Short name T126
Test name
Test status
Simulation time 20827070 ps
CPU time 0.92 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 218040 kb
Host smart-98789a03-c548-4a91-b410-e8c91ce9c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301713340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2301713340
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.756820360
Short name T419
Test name
Test status
Simulation time 48633366 ps
CPU time 1.56 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 217816 kb
Host smart-9915b12f-d620-4ad3-a5d5-79c06051148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756820360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.756820360
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3703869094
Short name T511
Test name
Test status
Simulation time 21838401 ps
CPU time 1.11 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:52 PM PDT 24
Peak memory 216312 kb
Host smart-c42e9faf-62cc-424f-8bfa-7c7167859983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703869094 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3703869094
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.782759331
Short name T679
Test name
Test status
Simulation time 52671638 ps
CPU time 0.95 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 206772 kb
Host smart-cc6db89c-1ecf-4940-bd22-970658fc2553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782759331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.782759331
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.199588540
Short name T18
Test name
Test status
Simulation time 2538979758 ps
CPU time 10.41 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 236800 kb
Host smart-f6e31c89-33b0-46cb-8b0a-144948bed228
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199588540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.199588540
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1469868646
Short name T774
Test name
Test status
Simulation time 39652109 ps
CPU time 0.95 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:54 PM PDT 24
Peak memory 214920 kb
Host smart-b339e1fc-afd6-4e9e-bd9b-ca6f48bb920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469868646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1469868646
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1287249000
Short name T628
Test name
Test status
Simulation time 119765373731 ps
CPU time 3021.94 seconds
Started May 21 02:12:48 PM PDT 24
Finished May 21 03:03:14 PM PDT 24
Peak memory 234872 kb
Host smart-c227fc60-caa1-42aa-8f3f-e8e97f9268fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287249000 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1287249000
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.1776279485
Short name T614
Test name
Test status
Simulation time 30580146 ps
CPU time 0.94 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 214860 kb
Host smart-85454393-041a-4a7c-8b81-811d123588d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776279485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1776279485
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2793833750
Short name T226
Test name
Test status
Simulation time 44962301 ps
CPU time 0.89 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 216188 kb
Host smart-fdad69a2-49ba-4c43-b626-ebe38973cbe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793833750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2793833750
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.4238383236
Short name T107
Test name
Test status
Simulation time 42914480 ps
CPU time 1.04 seconds
Started May 21 02:13:36 PM PDT 24
Finished May 21 02:13:48 PM PDT 24
Peak memory 218192 kb
Host smart-8c40e2ce-4571-4d75-b27b-e025db3cf3ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238383236 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.4238383236
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.583081622
Short name T555
Test name
Test status
Simulation time 24658429 ps
CPU time 0.94 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 218364 kb
Host smart-fd04c094-ee96-4820-86bc-a8f673eea815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583081622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.583081622
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1466759659
Short name T43
Test name
Test status
Simulation time 28338513 ps
CPU time 1.38 seconds
Started May 21 02:13:33 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 216800 kb
Host smart-9a57f3ef-ad5f-4e3a-a3a2-8d33b4a83e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466759659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1466759659
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3779246879
Short name T160
Test name
Test status
Simulation time 21103814 ps
CPU time 1.04 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:39 PM PDT 24
Peak memory 215408 kb
Host smart-1a74c676-2d7e-4987-be40-2c57b82b9326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779246879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3779246879
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3726794683
Short name T424
Test name
Test status
Simulation time 18610641 ps
CPU time 1.01 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:37 PM PDT 24
Peak memory 214972 kb
Host smart-915a9eb6-faec-4f22-ba02-9e798f8ba819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726794683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3726794683
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.137183329
Short name T173
Test name
Test status
Simulation time 818908632 ps
CPU time 4.54 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 219364 kb
Host smart-ad815fdc-7f3c-4aa7-8ece-9cbcc48e032d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137183329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.137183329
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.780219063
Short name T430
Test name
Test status
Simulation time 45934269 ps
CPU time 0.93 seconds
Started May 21 02:22:19 PM PDT 24
Finished May 21 02:22:21 PM PDT 24
Peak memory 216652 kb
Host smart-6fa4bd18-337d-42a5-a02a-12dd59b8ca50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780219063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.780219063
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.128654741
Short name T711
Test name
Test status
Simulation time 48215302 ps
CPU time 1.3 seconds
Started May 21 02:22:20 PM PDT 24
Finished May 21 02:22:22 PM PDT 24
Peak memory 218260 kb
Host smart-cd599a83-c6d5-4b1f-9bc5-b7c3a036dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128654741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.128654741
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1294730483
Short name T653
Test name
Test status
Simulation time 74216736 ps
CPU time 1.34 seconds
Started May 21 02:22:19 PM PDT 24
Finished May 21 02:22:21 PM PDT 24
Peak memory 218148 kb
Host smart-f3864403-b2c5-4633-b1a8-e817e5d40353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294730483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1294730483
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4212133290
Short name T670
Test name
Test status
Simulation time 60845985 ps
CPU time 1.42 seconds
Started May 21 02:22:28 PM PDT 24
Finished May 21 02:22:30 PM PDT 24
Peak memory 218088 kb
Host smart-647383f3-5b98-4618-b48d-dd3cfadd6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212133290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4212133290
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.4130000173
Short name T658
Test name
Test status
Simulation time 39005300 ps
CPU time 1.3 seconds
Started May 21 02:22:33 PM PDT 24
Finished May 21 02:22:37 PM PDT 24
Peak memory 216688 kb
Host smart-de032e52-7eaf-469e-b45c-ea1081ff2d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130000173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4130000173
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.4029124656
Short name T520
Test name
Test status
Simulation time 53498128 ps
CPU time 1.33 seconds
Started May 21 02:22:35 PM PDT 24
Finished May 21 02:22:38 PM PDT 24
Peak memory 216796 kb
Host smart-47f76806-2180-4bba-8ed7-2ed33699778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029124656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4029124656
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1722294028
Short name T452
Test name
Test status
Simulation time 72616871 ps
CPU time 1.27 seconds
Started May 21 02:22:40 PM PDT 24
Finished May 21 02:22:43 PM PDT 24
Peak memory 218052 kb
Host smart-ea15fa8f-496a-4ca2-af79-f56f46041881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722294028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1722294028
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.204506747
Short name T366
Test name
Test status
Simulation time 88716372 ps
CPU time 1.29 seconds
Started May 21 02:22:47 PM PDT 24
Finished May 21 02:22:50 PM PDT 24
Peak memory 217988 kb
Host smart-c3475a8a-3f8c-4113-b7a9-3d5ea5ec6e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204506747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.204506747
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4159475494
Short name T94
Test name
Test status
Simulation time 27669712 ps
CPU time 1.27 seconds
Started May 21 02:13:36 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 215332 kb
Host smart-3befa89a-c155-46da-b814-561c7bf63cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159475494 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4159475494
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2204217619
Short name T778
Test name
Test status
Simulation time 15005412 ps
CPU time 0.93 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 214472 kb
Host smart-9b448ecb-9a04-4aa2-a4a3-abdb462c172e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204217619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2204217619
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.54587267
Short name T425
Test name
Test status
Simulation time 12557717 ps
CPU time 0.92 seconds
Started May 21 02:13:38 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 215968 kb
Host smart-954deda9-c9f3-48b9-acfa-e342dc847d5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54587267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.54587267
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3564478744
Short name T344
Test name
Test status
Simulation time 157003815 ps
CPU time 1.14 seconds
Started May 21 02:13:39 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 216708 kb
Host smart-4ef437f5-9a37-41b5-bf09-126b80550f38
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564478744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3564478744
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.1133935426
Short name T185
Test name
Test status
Simulation time 18851513 ps
CPU time 1.07 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 218160 kb
Host smart-f1677e33-2d6a-431e-b0f0-703c9dcb3119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133935426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1133935426
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2918323450
Short name T60
Test name
Test status
Simulation time 38396658 ps
CPU time 1.31 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 217880 kb
Host smart-555bee58-1125-4699-baf8-bf93c30b1e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918323450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2918323450
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3109196550
Short name T645
Test name
Test status
Simulation time 23620775 ps
CPU time 1.07 seconds
Started May 21 02:13:37 PM PDT 24
Finished May 21 02:13:49 PM PDT 24
Peak memory 215268 kb
Host smart-7494e580-65eb-4762-830b-5b0e682671cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109196550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3109196550
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3660304637
Short name T824
Test name
Test status
Simulation time 15753714 ps
CPU time 0.99 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:46 PM PDT 24
Peak memory 214936 kb
Host smart-f32c857d-6c82-4845-a73d-eff801e82d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660304637 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3660304637
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1598253916
Short name T807
Test name
Test status
Simulation time 394986624 ps
CPU time 2.19 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 216576 kb
Host smart-71d04b3f-a75c-48d7-9128-97a42d3586a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598253916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1598253916
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3757645994
Short name T687
Test name
Test status
Simulation time 58732676265 ps
CPU time 731.52 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:26:01 PM PDT 24
Peak memory 218796 kb
Host smart-bd3bb829-b1cf-4599-9752-c367a8256952
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757645994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3757645994
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.4278899360
Short name T802
Test name
Test status
Simulation time 65905942 ps
CPU time 1.1 seconds
Started May 21 02:22:46 PM PDT 24
Finished May 21 02:22:49 PM PDT 24
Peak memory 219328 kb
Host smart-84588387-9791-4ca5-9e3a-7236c31465b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278899360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.4278899360
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2471243257
Short name T521
Test name
Test status
Simulation time 37448743 ps
CPU time 1.36 seconds
Started May 21 02:22:46 PM PDT 24
Finished May 21 02:22:49 PM PDT 24
Peak memory 217924 kb
Host smart-c56e1512-76f7-46ea-8aea-47177156a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471243257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2471243257
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2242057786
Short name T459
Test name
Test status
Simulation time 60733359 ps
CPU time 1.43 seconds
Started May 21 02:22:52 PM PDT 24
Finished May 21 02:22:54 PM PDT 24
Peak memory 218136 kb
Host smart-12d1c88f-5c5a-436d-9359-3de692406b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242057786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2242057786
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.855882792
Short name T315
Test name
Test status
Simulation time 88119273 ps
CPU time 1.51 seconds
Started May 21 02:22:54 PM PDT 24
Finished May 21 02:22:56 PM PDT 24
Peak memory 218288 kb
Host smart-8e8d0873-cb8f-43a1-ae9e-611f066b2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855882792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.855882792
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2746107159
Short name T492
Test name
Test status
Simulation time 52014308 ps
CPU time 0.97 seconds
Started May 21 02:22:58 PM PDT 24
Finished May 21 02:23:00 PM PDT 24
Peak memory 216972 kb
Host smart-647fd976-1a62-4f1c-9a78-149636e57984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746107159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2746107159
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.4278765007
Short name T623
Test name
Test status
Simulation time 201467884 ps
CPU time 3.21 seconds
Started May 21 02:23:06 PM PDT 24
Finished May 21 02:23:10 PM PDT 24
Peak memory 219640 kb
Host smart-565c4bd0-e39a-4233-bee3-279a1b91403f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278765007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4278765007
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1470686841
Short name T822
Test name
Test status
Simulation time 40071217 ps
CPU time 1.46 seconds
Started May 21 02:23:06 PM PDT 24
Finished May 21 02:23:08 PM PDT 24
Peak memory 217780 kb
Host smart-0277d0ab-fefa-4814-b128-c519f8633e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470686841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1470686841
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.611099580
Short name T533
Test name
Test status
Simulation time 90317928 ps
CPU time 1.48 seconds
Started May 21 02:23:13 PM PDT 24
Finished May 21 02:23:16 PM PDT 24
Peak memory 218400 kb
Host smart-226bb645-e0c4-4763-8bdb-8cb81f305425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611099580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.611099580
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4100382947
Short name T571
Test name
Test status
Simulation time 50189019 ps
CPU time 1.28 seconds
Started May 21 02:23:12 PM PDT 24
Finished May 21 02:23:14 PM PDT 24
Peak memory 217064 kb
Host smart-b0363a0a-dbb6-43ae-aa8b-c9742a0a43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100382947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4100382947
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2550706746
Short name T600
Test name
Test status
Simulation time 40994337 ps
CPU time 1.08 seconds
Started May 21 02:23:19 PM PDT 24
Finished May 21 02:23:21 PM PDT 24
Peak memory 219340 kb
Host smart-f3923822-302e-4fe6-ab70-0bf8166891b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550706746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2550706746
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4196670841
Short name T516
Test name
Test status
Simulation time 59554305 ps
CPU time 1.25 seconds
Started May 21 02:13:39 PM PDT 24
Finished May 21 02:13:50 PM PDT 24
Peak memory 215388 kb
Host smart-150942e9-2dab-4989-ae5a-ed37f26eb066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196670841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4196670841
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.904269431
Short name T363
Test name
Test status
Simulation time 14807582 ps
CPU time 0.9 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:52 PM PDT 24
Peak memory 214476 kb
Host smart-b74601b6-0864-4979-b336-f61cac119820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904269431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.904269431
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1827799660
Short name T591
Test name
Test status
Simulation time 10990868 ps
CPU time 0.9 seconds
Started May 21 02:13:45 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 215684 kb
Host smart-4363571b-bf28-486b-a056-403bb6186bbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827799660 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1827799660
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.2701508186
Short name T179
Test name
Test status
Simulation time 30449475 ps
CPU time 0.84 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 218124 kb
Host smart-7a3efd5f-2641-4c04-8d0f-1eef4d23e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701508186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2701508186
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2840475775
Short name T338
Test name
Test status
Simulation time 44778772 ps
CPU time 1.86 seconds
Started May 21 02:13:34 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 218072 kb
Host smart-d39531d6-9655-4bdf-86fe-b4504b441504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840475775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2840475775
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1049462103
Short name T354
Test name
Test status
Simulation time 37179037 ps
CPU time 0.87 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 214932 kb
Host smart-1f12b9aa-5fb7-44d2-a9ef-3ca0da40f632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049462103 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1049462103
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2756649865
Short name T365
Test name
Test status
Simulation time 16808035 ps
CPU time 1.01 seconds
Started May 21 02:13:35 PM PDT 24
Finished May 21 02:13:47 PM PDT 24
Peak memory 215032 kb
Host smart-e3553bfd-7903-48db-ac47-68d6429cb04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756649865 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2756649865
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.906572223
Short name T536
Test name
Test status
Simulation time 41680179 ps
CPU time 1.41 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 216636 kb
Host smart-ab12eaa8-40eb-4a81-a4e8-fabd1b294bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906572223 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.906572223
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3086588502
Short name T730
Test name
Test status
Simulation time 209427722184 ps
CPU time 1066.24 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:31:39 PM PDT 24
Peak memory 221820 kb
Host smart-324e0066-7668-407d-8c4b-642ce638f7aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086588502 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3086588502
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3765012627
Short name T387
Test name
Test status
Simulation time 30857453 ps
CPU time 1.03 seconds
Started May 21 02:23:27 PM PDT 24
Finished May 21 02:23:28 PM PDT 24
Peak memory 216724 kb
Host smart-c4416a7c-7b6e-426a-a20d-140764d37a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765012627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3765012627
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3874622821
Short name T343
Test name
Test status
Simulation time 51215018 ps
CPU time 1.21 seconds
Started May 21 02:23:27 PM PDT 24
Finished May 21 02:23:29 PM PDT 24
Peak memory 216772 kb
Host smart-95dbbb37-6d10-418f-9967-24433acf266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874622821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3874622821
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1773329318
Short name T402
Test name
Test status
Simulation time 86203599 ps
CPU time 1.44 seconds
Started May 21 02:23:39 PM PDT 24
Finished May 21 02:23:42 PM PDT 24
Peak memory 218436 kb
Host smart-13c98927-aa8d-4af7-8e1b-4f0f05bf6cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773329318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1773329318
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3467481477
Short name T287
Test name
Test status
Simulation time 42109925 ps
CPU time 1.36 seconds
Started May 21 02:23:38 PM PDT 24
Finished May 21 02:23:41 PM PDT 24
Peak memory 217844 kb
Host smart-fa0f8c15-eac6-41a0-96bd-bc22f183e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467481477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3467481477
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3339856999
Short name T700
Test name
Test status
Simulation time 29705143 ps
CPU time 1.26 seconds
Started May 21 02:23:40 PM PDT 24
Finished May 21 02:23:43 PM PDT 24
Peak memory 217056 kb
Host smart-6d01a932-14b3-4ad0-b62d-b7d71d403dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339856999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3339856999
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3392587771
Short name T45
Test name
Test status
Simulation time 274087979 ps
CPU time 1.68 seconds
Started May 21 02:23:42 PM PDT 24
Finished May 21 02:23:45 PM PDT 24
Peak memory 218288 kb
Host smart-08100ca7-4219-4457-9bea-91a3a5ab7f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392587771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3392587771
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.87873250
Short name T672
Test name
Test status
Simulation time 67205412 ps
CPU time 1.31 seconds
Started May 21 02:23:43 PM PDT 24
Finished May 21 02:23:45 PM PDT 24
Peak memory 216612 kb
Host smart-1020aa83-e470-4f27-b698-eebe679d3140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87873250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.87873250
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.174964368
Short name T612
Test name
Test status
Simulation time 88190267 ps
CPU time 1.3 seconds
Started May 21 02:23:39 PM PDT 24
Finished May 21 02:23:42 PM PDT 24
Peak memory 216792 kb
Host smart-2653fea4-b2c7-46b7-8286-53fcc3baa252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174964368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.174964368
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2599191959
Short name T87
Test name
Test status
Simulation time 93610522 ps
CPU time 1.17 seconds
Started May 21 02:23:41 PM PDT 24
Finished May 21 02:23:43 PM PDT 24
Peak memory 216548 kb
Host smart-2fc7905c-c3fe-4547-b1ac-0db2d1b778b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599191959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2599191959
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3399669576
Short name T816
Test name
Test status
Simulation time 132184993 ps
CPU time 1.15 seconds
Started May 21 02:13:45 PM PDT 24
Finished May 21 02:13:54 PM PDT 24
Peak memory 215368 kb
Host smart-b00def81-be60-4984-8045-e4bbf6be9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399669576 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3399669576
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3624869650
Short name T352
Test name
Test status
Simulation time 62620101 ps
CPU time 0.93 seconds
Started May 21 02:13:49 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 206316 kb
Host smart-64da0edc-5d15-4f58-a06c-021a17cef9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624869650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3624869650
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1786479851
Short name T121
Test name
Test status
Simulation time 18707510 ps
CPU time 0.89 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:56 PM PDT 24
Peak memory 215188 kb
Host smart-55c0c3da-d0a2-4ba9-9a0c-88b21c035a8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786479851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1786479851
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1233582765
Short name T75
Test name
Test status
Simulation time 33267308 ps
CPU time 1.14 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 217848 kb
Host smart-3ae85177-a8e4-473b-8fb6-41123a53c457
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233582765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1233582765
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2395711022
Short name T717
Test name
Test status
Simulation time 24074724 ps
CPU time 1.03 seconds
Started May 21 02:13:41 PM PDT 24
Finished May 21 02:13:52 PM PDT 24
Peak memory 217884 kb
Host smart-d70321e6-c55a-4c75-8795-7852c0111f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395711022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2395711022
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2826189413
Short name T259
Test name
Test status
Simulation time 63573075 ps
CPU time 1.61 seconds
Started May 21 02:13:40 PM PDT 24
Finished May 21 02:13:51 PM PDT 24
Peak memory 218044 kb
Host smart-c17b5d16-1a27-40e1-bcf3-1221b8d450e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826189413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2826189413
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2860432086
Short name T31
Test name
Test status
Simulation time 25068866 ps
CPU time 0.93 seconds
Started May 21 02:13:47 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 215476 kb
Host smart-3e4864cd-f6e8-4a3e-bbe8-bacb0848508f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860432086 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2860432086
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1845552333
Short name T718
Test name
Test status
Simulation time 30568257 ps
CPU time 1 seconds
Started May 21 02:13:44 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 214948 kb
Host smart-aa5276bf-9905-457d-b1cb-cb5372f05321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845552333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1845552333
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.507507458
Short name T752
Test name
Test status
Simulation time 201848632 ps
CPU time 1.62 seconds
Started May 21 02:13:42 PM PDT 24
Finished May 21 02:13:53 PM PDT 24
Peak memory 214852 kb
Host smart-f8a30863-466c-46a9-ada9-cbdb9c05c28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507507458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.507507458
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.710714189
Short name T211
Test name
Test status
Simulation time 344727627248 ps
CPU time 3764.76 seconds
Started May 21 02:13:47 PM PDT 24
Finished May 21 03:16:39 PM PDT 24
Peak memory 232964 kb
Host smart-9dbcfd4a-aeb4-433f-af83-5f458bb51fb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710714189 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.710714189
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3060040339
Short name T837
Test name
Test status
Simulation time 52162407 ps
CPU time 1.62 seconds
Started May 21 02:23:38 PM PDT 24
Finished May 21 02:23:41 PM PDT 24
Peak memory 217912 kb
Host smart-17c94836-a3ea-47b4-810e-eb2bd2be4197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060040339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3060040339
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1694136226
Short name T399
Test name
Test status
Simulation time 70524404 ps
CPU time 1.37 seconds
Started May 21 02:23:40 PM PDT 24
Finished May 21 02:23:42 PM PDT 24
Peak memory 218200 kb
Host smart-fa6ed832-9e73-4e46-bfc5-67e562890a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694136226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1694136226
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3812970284
Short name T458
Test name
Test status
Simulation time 31701210 ps
CPU time 1.26 seconds
Started May 21 02:23:37 PM PDT 24
Finished May 21 02:23:38 PM PDT 24
Peak memory 216760 kb
Host smart-882f233d-337c-44ab-9f8f-97076af3d636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812970284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3812970284
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2038343790
Short name T581
Test name
Test status
Simulation time 50936389 ps
CPU time 1.16 seconds
Started May 21 02:23:46 PM PDT 24
Finished May 21 02:23:48 PM PDT 24
Peak memory 216612 kb
Host smart-c7bac547-eb6f-49c8-ac4b-f9cfa8dd2e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038343790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2038343790
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.693698668
Short name T403
Test name
Test status
Simulation time 38033522 ps
CPU time 1.51 seconds
Started May 21 02:23:47 PM PDT 24
Finished May 21 02:23:49 PM PDT 24
Peak memory 218176 kb
Host smart-adb7d108-6039-4e19-989e-1ef5162a9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693698668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.693698668
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1853479776
Short name T85
Test name
Test status
Simulation time 51404895 ps
CPU time 1.95 seconds
Started May 21 02:23:46 PM PDT 24
Finished May 21 02:23:49 PM PDT 24
Peak memory 217932 kb
Host smart-071b1652-3f6c-4670-b4d3-aaffc429511c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853479776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1853479776
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1241879784
Short name T538
Test name
Test status
Simulation time 225684285 ps
CPU time 1.22 seconds
Started May 21 02:23:47 PM PDT 24
Finished May 21 02:23:49 PM PDT 24
Peak memory 218188 kb
Host smart-74e5f03b-fcf7-4a3d-be27-f1595ee97059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241879784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1241879784
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.4246809414
Short name T467
Test name
Test status
Simulation time 69238553 ps
CPU time 1.24 seconds
Started May 21 02:23:48 PM PDT 24
Finished May 21 02:23:50 PM PDT 24
Peak memory 216736 kb
Host smart-bd8ae0c3-191d-4028-8d95-e7830130b1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246809414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4246809414
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2178268368
Short name T652
Test name
Test status
Simulation time 50440197 ps
CPU time 1.88 seconds
Started May 21 02:23:48 PM PDT 24
Finished May 21 02:23:50 PM PDT 24
Peak memory 218144 kb
Host smart-883d1753-9e14-4994-8ea9-14997db3b6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178268368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2178268368
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1207600391
Short name T579
Test name
Test status
Simulation time 35534971 ps
CPU time 1.37 seconds
Started May 21 02:23:48 PM PDT 24
Finished May 21 02:23:50 PM PDT 24
Peak memory 217700 kb
Host smart-172e15d1-2cf2-4249-adc2-3e530d60faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207600391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1207600391
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1547367886
Short name T304
Test name
Test status
Simulation time 23036422 ps
CPU time 1.21 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 215356 kb
Host smart-01fc1c4b-70a0-48e5-840f-ccc49eb4fe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547367886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1547367886
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3045683192
Short name T795
Test name
Test status
Simulation time 135620640 ps
CPU time 0.9 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:13:55 PM PDT 24
Peak memory 214812 kb
Host smart-119b0e2b-536e-440a-aa07-fa40123e5560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045683192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3045683192
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1181082615
Short name T661
Test name
Test status
Simulation time 38946935 ps
CPU time 0.88 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:13:59 PM PDT 24
Peak memory 215932 kb
Host smart-d8501e54-4f01-41f9-b83e-abcb30ec8710
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181082615 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1181082615
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.932217367
Short name T397
Test name
Test status
Simulation time 26855253 ps
CPU time 1.12 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 218016 kb
Host smart-75fcf678-97c5-4ab6-8e85-b400d4b45dc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932217367 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.932217367
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.997037054
Short name T339
Test name
Test status
Simulation time 61414160 ps
CPU time 1.62 seconds
Started May 21 02:13:55 PM PDT 24
Finished May 21 02:14:02 PM PDT 24
Peak memory 218244 kb
Host smart-534aaa19-603c-4d87-ae5a-32f8ba1e4582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997037054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.997037054
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1091932958
Short name T784
Test name
Test status
Simulation time 29455690 ps
CPU time 1.24 seconds
Started May 21 02:13:50 PM PDT 24
Finished May 21 02:13:58 PM PDT 24
Peak memory 215328 kb
Host smart-72ffb402-d4c3-4ed2-a3ca-f667d8650152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091932958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1091932958
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3604083715
Short name T740
Test name
Test status
Simulation time 18175751 ps
CPU time 1.06 seconds
Started May 21 02:13:54 PM PDT 24
Finished May 21 02:14:01 PM PDT 24
Peak memory 214984 kb
Host smart-8ebb9fd4-e116-4bc9-921a-2899aa39ecfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604083715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3604083715
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1431841314
Short name T269
Test name
Test status
Simulation time 932242054 ps
CPU time 4.84 seconds
Started May 21 02:13:48 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 215016 kb
Host smart-251c43fb-6522-4ba9-8087-91353ee9c836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431841314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1431841314
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3661457695
Short name T417
Test name
Test status
Simulation time 123466549052 ps
CPU time 2901.51 seconds
Started May 21 02:13:53 PM PDT 24
Finished May 21 03:02:20 PM PDT 24
Peak memory 230200 kb
Host smart-c22de499-f4e2-4a15-9e5b-cd6cb5a9c4d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661457695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3661457695
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1241824195
Short name T351
Test name
Test status
Simulation time 81287583 ps
CPU time 1.33 seconds
Started May 21 02:23:46 PM PDT 24
Finished May 21 02:23:48 PM PDT 24
Peak memory 216616 kb
Host smart-daf4970f-132f-4771-942f-1c7dd046a5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241824195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1241824195
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3084181737
Short name T709
Test name
Test status
Simulation time 98095132 ps
CPU time 1.19 seconds
Started May 21 02:23:56 PM PDT 24
Finished May 21 02:23:57 PM PDT 24
Peak memory 216768 kb
Host smart-c2b3b7c8-1269-4a76-955d-c2ba9afe5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084181737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3084181737
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1464450652
Short name T289
Test name
Test status
Simulation time 64343532 ps
CPU time 1.52 seconds
Started May 21 02:23:52 PM PDT 24
Finished May 21 02:23:54 PM PDT 24
Peak memory 217940 kb
Host smart-ae3d4277-4698-4cf8-984a-3f295a50767e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464450652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1464450652
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2730717429
Short name T378
Test name
Test status
Simulation time 64157619 ps
CPU time 0.97 seconds
Started May 21 02:23:53 PM PDT 24
Finished May 21 02:23:54 PM PDT 24
Peak memory 216840 kb
Host smart-39eec959-7b78-48b2-99f7-86ef4d3b5ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730717429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2730717429
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2508809893
Short name T669
Test name
Test status
Simulation time 210178110 ps
CPU time 3 seconds
Started May 21 02:23:51 PM PDT 24
Finished May 21 02:23:55 PM PDT 24
Peak memory 219008 kb
Host smart-5214d6b6-087a-45e5-b9f3-46e78372b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508809893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2508809893
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1747543537
Short name T288
Test name
Test status
Simulation time 129954251 ps
CPU time 1.45 seconds
Started May 21 02:23:51 PM PDT 24
Finished May 21 02:23:53 PM PDT 24
Peak memory 218244 kb
Host smart-43c26dd5-8790-4686-8d89-c6f00661a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747543537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1747543537
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3931219587
Short name T70
Test name
Test status
Simulation time 124121284 ps
CPU time 1.24 seconds
Started May 21 02:23:53 PM PDT 24
Finished May 21 02:23:55 PM PDT 24
Peak memory 217164 kb
Host smart-ccccbd91-c850-455f-9a28-83fd4facca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931219587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3931219587
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.655019109
Short name T567
Test name
Test status
Simulation time 46054320 ps
CPU time 1.56 seconds
Started May 21 02:23:56 PM PDT 24
Finished May 21 02:23:58 PM PDT 24
Peak memory 216744 kb
Host smart-1a5dc97d-e21f-44c7-8260-ed8f3e88dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655019109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.655019109
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1901878023
Short name T690
Test name
Test status
Simulation time 39951621 ps
CPU time 1.34 seconds
Started May 21 02:23:52 PM PDT 24
Finished May 21 02:23:54 PM PDT 24
Peak memory 217748 kb
Host smart-63b5839d-ff29-4c66-aa18-87e1cdb7d24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901878023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1901878023
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.467602718
Short name T224
Test name
Test status
Simulation time 20219556 ps
CPU time 1.09 seconds
Started May 21 02:23:52 PM PDT 24
Finished May 21 02:23:53 PM PDT 24
Peak memory 216552 kb
Host smart-92d4c23a-2f08-453d-b8a5-b8667686a45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467602718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.467602718
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.219668067
Short name T129
Test name
Test status
Simulation time 155372830 ps
CPU time 1.11 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 215408 kb
Host smart-c444dac8-9dc0-4e8e-8fce-63c9320f7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219668067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.219668067
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.971742981
Short name T187
Test name
Test status
Simulation time 45611156 ps
CPU time 0.88 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 216016 kb
Host smart-70c9c135-d259-484a-8b0a-fca5e76a5248
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971742981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.971742981
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.1798963809
Short name T677
Test name
Test status
Simulation time 30081645 ps
CPU time 1.32 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:14:04 PM PDT 24
Peak memory 224988 kb
Host smart-797df48b-d747-42b7-9825-6fe3e8067d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798963809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1798963809
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2269537828
Short name T310
Test name
Test status
Simulation time 33694863 ps
CPU time 1.33 seconds
Started May 21 02:13:55 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 219248 kb
Host smart-d32a177b-ab95-4e95-bbaf-56ef3bbf87dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269537828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2269537828
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.1639248938
Short name T561
Test name
Test status
Simulation time 16174501 ps
CPU time 0.99 seconds
Started May 21 02:13:57 PM PDT 24
Finished May 21 02:14:04 PM PDT 24
Peak memory 214960 kb
Host smart-f42eed2a-46e5-48e3-8562-db1d87aab336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639248938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1639248938
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2443322316
Short name T282
Test name
Test status
Simulation time 1608680931 ps
CPU time 5.35 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 215020 kb
Host smart-d1d4d626-fcac-4ed2-985f-cb4f3344fde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443322316 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2443322316
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.21978597
Short name T781
Test name
Test status
Simulation time 15676643155 ps
CPU time 355.29 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:19:57 PM PDT 24
Peak memory 216804 kb
Host smart-c0deda39-4822-4786-87a7-1f2708aeeca3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21978597 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.21978597
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.344753682
Short name T722
Test name
Test status
Simulation time 36711735 ps
CPU time 1.19 seconds
Started May 21 02:23:52 PM PDT 24
Finished May 21 02:23:54 PM PDT 24
Peak memory 216824 kb
Host smart-5323c1c9-c634-4d97-a367-c3e2ab90f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344753682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.344753682
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2493363221
Short name T86
Test name
Test status
Simulation time 55479408 ps
CPU time 1.66 seconds
Started May 21 02:23:58 PM PDT 24
Finished May 21 02:24:00 PM PDT 24
Peak memory 217908 kb
Host smart-6b87a5e6-c887-4826-8a5c-1a2c04e83d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493363221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2493363221
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2777806844
Short name T710
Test name
Test status
Simulation time 146720788 ps
CPU time 1.82 seconds
Started May 21 02:23:59 PM PDT 24
Finished May 21 02:24:01 PM PDT 24
Peak memory 219608 kb
Host smart-fc420496-5537-4c06-9212-c6511d2d652f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777806844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2777806844
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.405503713
Short name T633
Test name
Test status
Simulation time 67032717 ps
CPU time 1.23 seconds
Started May 21 02:23:58 PM PDT 24
Finished May 21 02:23:59 PM PDT 24
Peak memory 218040 kb
Host smart-a3f36d08-8a85-41c0-9465-9221a4891244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405503713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.405503713
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3067203849
Short name T611
Test name
Test status
Simulation time 29461383 ps
CPU time 1.12 seconds
Started May 21 02:24:00 PM PDT 24
Finished May 21 02:24:03 PM PDT 24
Peak memory 219376 kb
Host smart-24237109-e3b7-4328-b867-7208fd7e4b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067203849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3067203849
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1471294773
Short name T524
Test name
Test status
Simulation time 232039089 ps
CPU time 1.1 seconds
Started May 21 02:24:00 PM PDT 24
Finished May 21 02:24:01 PM PDT 24
Peak memory 216780 kb
Host smart-d39f041b-a4fd-454e-ba9f-64af41831156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471294773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1471294773
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3992162563
Short name T515
Test name
Test status
Simulation time 42397693 ps
CPU time 1.1 seconds
Started May 21 02:24:00 PM PDT 24
Finished May 21 02:24:01 PM PDT 24
Peak memory 216752 kb
Host smart-9f7a5325-03d0-42ca-9047-f304fd4e332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992162563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3992162563
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3741368540
Short name T334
Test name
Test status
Simulation time 78649087 ps
CPU time 1.22 seconds
Started May 21 02:24:00 PM PDT 24
Finished May 21 02:24:02 PM PDT 24
Peak memory 218320 kb
Host smart-ca9d16f0-9346-44f2-a4c6-565eeabb0e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741368540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3741368540
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3741060490
Short name T682
Test name
Test status
Simulation time 111248731 ps
CPU time 2.16 seconds
Started May 21 02:24:01 PM PDT 24
Finished May 21 02:24:04 PM PDT 24
Peak memory 219088 kb
Host smart-ae53d85e-3b7c-463b-b958-292065bd3c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741060490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3741060490
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2210574130
Short name T437
Test name
Test status
Simulation time 46574163 ps
CPU time 1.13 seconds
Started May 21 02:23:58 PM PDT 24
Finished May 21 02:24:00 PM PDT 24
Peak memory 216608 kb
Host smart-cd8ce927-123c-4b60-a1af-0da9e3316f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210574130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2210574130
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.763397191
Short name T514
Test name
Test status
Simulation time 26627923 ps
CPU time 1.27 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 215360 kb
Host smart-1beba687-2a36-4a9d-940d-a9b3678de2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763397191 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.763397191
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.207926713
Short name T519
Test name
Test status
Simulation time 27729690 ps
CPU time 0.92 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 214400 kb
Host smart-d6e119ba-3f83-44f0-918c-93590d19131d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207926713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.207926713
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2957988283
Short name T324
Test name
Test status
Simulation time 15734753 ps
CPU time 0.86 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:09 PM PDT 24
Peak memory 215684 kb
Host smart-c1b35e07-2d5a-41da-b242-61513b8edeec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957988283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2957988283
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2039294340
Short name T409
Test name
Test status
Simulation time 36104096 ps
CPU time 1.35 seconds
Started May 21 02:14:01 PM PDT 24
Finished May 21 02:14:08 PM PDT 24
Peak memory 216512 kb
Host smart-46ce1e0c-324c-4974-a3ea-d28e6610660c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039294340 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2039294340
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.942461001
Short name T651
Test name
Test status
Simulation time 37248495 ps
CPU time 0.97 seconds
Started May 21 02:14:03 PM PDT 24
Finished May 21 02:14:10 PM PDT 24
Peak memory 223284 kb
Host smart-b0fb29aa-c982-4fb2-b760-0f999274647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942461001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.942461001
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1889088044
Short name T771
Test name
Test status
Simulation time 31823869 ps
CPU time 1.37 seconds
Started May 21 02:13:52 PM PDT 24
Finished May 21 02:14:00 PM PDT 24
Peak memory 217844 kb
Host smart-eb1f0979-edff-4643-aa6c-bb2e5749fbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889088044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1889088044
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_smoke.3562821553
Short name T434
Test name
Test status
Simulation time 16293709 ps
CPU time 1 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:03 PM PDT 24
Peak memory 215024 kb
Host smart-8942f5a7-a9dc-477b-9c83-b57d0965927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562821553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3562821553
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3607775497
Short name T606
Test name
Test status
Simulation time 758189997 ps
CPU time 4.2 seconds
Started May 21 02:13:56 PM PDT 24
Finished May 21 02:14:06 PM PDT 24
Peak memory 216604 kb
Host smart-62173674-4e94-4a62-a17b-a8a5e6594467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607775497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3607775497
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.3526196025
Short name T803
Test name
Test status
Simulation time 342880427 ps
CPU time 1.32 seconds
Started May 21 02:24:04 PM PDT 24
Finished May 21 02:24:06 PM PDT 24
Peak memory 216904 kb
Host smart-8b394fef-41db-4ad8-b717-987b088d80e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526196025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3526196025
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3270559708
Short name T307
Test name
Test status
Simulation time 37787833 ps
CPU time 1.43 seconds
Started May 21 02:24:07 PM PDT 24
Finished May 21 02:24:10 PM PDT 24
Peak memory 218036 kb
Host smart-63c978b5-64bd-4f9d-b9cd-6d79feaeeecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270559708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3270559708
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2439838748
Short name T292
Test name
Test status
Simulation time 163851022 ps
CPU time 2.27 seconds
Started May 21 02:24:07 PM PDT 24
Finished May 21 02:24:10 PM PDT 24
Peak memory 218804 kb
Host smart-9ec52933-6a0e-47b8-90d8-5a15e8c877bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439838748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2439838748
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4004188199
Short name T10
Test name
Test status
Simulation time 36739364 ps
CPU time 1.41 seconds
Started May 21 02:24:08 PM PDT 24
Finished May 21 02:24:11 PM PDT 24
Peak memory 219304 kb
Host smart-3a2bc3ef-ced7-423f-bb76-d6684f89bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004188199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4004188199
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3474137278
Short name T760
Test name
Test status
Simulation time 77310310 ps
CPU time 1.14 seconds
Started May 21 02:24:12 PM PDT 24
Finished May 21 02:24:14 PM PDT 24
Peak memory 218208 kb
Host smart-19578a19-e1b7-41e4-b203-3813d586f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474137278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3474137278
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2708505453
Short name T389
Test name
Test status
Simulation time 41049189 ps
CPU time 1.83 seconds
Started May 21 02:24:13 PM PDT 24
Finished May 21 02:24:15 PM PDT 24
Peak memory 216768 kb
Host smart-9cbe308b-3719-4efb-9c07-180030ca05de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708505453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2708505453
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1883518332
Short name T648
Test name
Test status
Simulation time 58849321 ps
CPU time 0.98 seconds
Started May 21 02:24:11 PM PDT 24
Finished May 21 02:24:13 PM PDT 24
Peak memory 216828 kb
Host smart-95ad8407-1f6d-452a-aebb-864ba06f3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883518332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1883518332
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.142781593
Short name T47
Test name
Test status
Simulation time 29741253 ps
CPU time 1.31 seconds
Started May 21 02:24:12 PM PDT 24
Finished May 21 02:24:14 PM PDT 24
Peak memory 216868 kb
Host smart-35d40105-f50f-4b01-b9e2-190327ca60f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142781593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.142781593
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.466538006
Short name T815
Test name
Test status
Simulation time 157028297 ps
CPU time 1.18 seconds
Started May 21 02:24:12 PM PDT 24
Finished May 21 02:24:14 PM PDT 24
Peak memory 216708 kb
Host smart-4bd3fc02-e82c-450c-a6d0-8e59031d2da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466538006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.466538006
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.489171776
Short name T306
Test name
Test status
Simulation time 96995571 ps
CPU time 1.33 seconds
Started May 21 02:13:58 PM PDT 24
Finished May 21 02:14:06 PM PDT 24
Peak memory 215340 kb
Host smart-28c05328-eaa4-4cc5-993d-a6b4b3ce3229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489171776 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.489171776
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2712332470
Short name T697
Test name
Test status
Simulation time 57459676 ps
CPU time 1.03 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 214860 kb
Host smart-fca36699-52e5-4366-95d1-cdf8de2f80c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712332470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2712332470
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_genbits.1744390366
Short name T563
Test name
Test status
Simulation time 65546635 ps
CPU time 2.51 seconds
Started May 21 02:14:04 PM PDT 24
Finished May 21 02:14:12 PM PDT 24
Peak memory 219612 kb
Host smart-e0d7aa74-54d8-47b3-9610-f980baf7d6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744390366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1744390366
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3181108997
Short name T37
Test name
Test status
Simulation time 33438743 ps
CPU time 0.9 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:06 PM PDT 24
Peak memory 215348 kb
Host smart-d2f57d79-a481-499d-ac6d-4c3727bacaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181108997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3181108997
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2999722234
Short name T460
Test name
Test status
Simulation time 18190914 ps
CPU time 1.06 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:06 PM PDT 24
Peak memory 214964 kb
Host smart-89ea5a30-a3ef-4c54-8035-04e7ceac9a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999722234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2999722234
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.533485732
Short name T278
Test name
Test status
Simulation time 280988300 ps
CPU time 5.8 seconds
Started May 21 02:13:59 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 216572 kb
Host smart-2355e1ae-eb41-44dd-818d-212ee8d2566b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533485732 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.533485732
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1466153722
Short name T605
Test name
Test status
Simulation time 341117864628 ps
CPU time 1934.42 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:46:27 PM PDT 24
Peak memory 226408 kb
Host smart-7d174728-3964-4bc0-a452-ca303dc3f602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466153722 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1466153722
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.187528774
Short name T444
Test name
Test status
Simulation time 164217467 ps
CPU time 1.97 seconds
Started May 21 02:24:12 PM PDT 24
Finished May 21 02:24:15 PM PDT 24
Peak memory 219460 kb
Host smart-586e3d06-b2c9-485b-bd96-cc054f4ccb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187528774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.187528774
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.534128572
Short name T291
Test name
Test status
Simulation time 81940584 ps
CPU time 1.06 seconds
Started May 21 02:24:20 PM PDT 24
Finished May 21 02:24:22 PM PDT 24
Peak memory 219208 kb
Host smart-f582b387-0f54-4a58-8792-90d0babe2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534128572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.534128572
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.810790834
Short name T498
Test name
Test status
Simulation time 61367491 ps
CPU time 2.04 seconds
Started May 21 02:24:23 PM PDT 24
Finished May 21 02:24:26 PM PDT 24
Peak memory 218208 kb
Host smart-be08341c-1bba-4016-99ec-6e86741d45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810790834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.810790834
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3915905745
Short name T280
Test name
Test status
Simulation time 43199795 ps
CPU time 1.13 seconds
Started May 21 02:24:20 PM PDT 24
Finished May 21 02:24:22 PM PDT 24
Peak memory 216988 kb
Host smart-e93f63d9-14d6-44a6-a61f-78f956a15b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915905745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3915905745
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.182352492
Short name T462
Test name
Test status
Simulation time 70058290 ps
CPU time 1.45 seconds
Started May 21 02:24:20 PM PDT 24
Finished May 21 02:24:23 PM PDT 24
Peak memory 217972 kb
Host smart-0ac89946-343a-432d-a29d-da059882d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182352492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.182352492
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1629266276
Short name T518
Test name
Test status
Simulation time 51170501 ps
CPU time 1.75 seconds
Started May 21 02:24:17 PM PDT 24
Finished May 21 02:24:20 PM PDT 24
Peak memory 217664 kb
Host smart-73220e5e-0f76-43b3-bed4-a6a84e066e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629266276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1629266276
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1303546200
Short name T330
Test name
Test status
Simulation time 83747071 ps
CPU time 1.08 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:24:26 PM PDT 24
Peak memory 216580 kb
Host smart-c7507279-ef28-42ee-b470-4f2d2e39ebd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303546200 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1303546200
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1951198563
Short name T552
Test name
Test status
Simulation time 24889730 ps
CPU time 1.08 seconds
Started May 21 02:24:20 PM PDT 24
Finished May 21 02:24:22 PM PDT 24
Peak memory 215012 kb
Host smart-03a73443-94cf-4a71-a80d-0939e4bfcb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951198563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1951198563
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1442867203
Short name T383
Test name
Test status
Simulation time 39062964 ps
CPU time 1.62 seconds
Started May 21 02:24:18 PM PDT 24
Finished May 21 02:24:20 PM PDT 24
Peak memory 217768 kb
Host smart-f2ba94a6-b9b8-488b-a512-e802148ccbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442867203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1442867203
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1114849211
Short name T588
Test name
Test status
Simulation time 33059411 ps
CPU time 1.48 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:24:26 PM PDT 24
Peak memory 217796 kb
Host smart-cba7d2c0-898a-4e04-863f-1bda62f1af39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114849211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1114849211
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1061916498
Short name T167
Test name
Test status
Simulation time 48643365 ps
CPU time 1.3 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:14:16 PM PDT 24
Peak memory 215384 kb
Host smart-d06a5b61-88cf-4e46-b780-78ee7ba5e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061916498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1061916498
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.689970424
Short name T328
Test name
Test status
Simulation time 51393354 ps
CPU time 0.96 seconds
Started May 21 02:14:08 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 206172 kb
Host smart-0c4439fe-4a3e-4312-acde-6030d3c6a33f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689970424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.689970424
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1680274618
Short name T847
Test name
Test status
Simulation time 51330822 ps
CPU time 1.24 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 216492 kb
Host smart-acbda513-cf8b-4974-bb7f-4e4670f75cce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680274618 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1680274618
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.40456983
Short name T835
Test name
Test status
Simulation time 25709467 ps
CPU time 1.07 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 223444 kb
Host smart-fca9c422-f9d2-46e5-a520-cba579cf6cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40456983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.40456983
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1704062549
Short name T357
Test name
Test status
Simulation time 66619955 ps
CPU time 1.24 seconds
Started May 21 02:14:06 PM PDT 24
Finished May 21 02:14:12 PM PDT 24
Peak memory 216644 kb
Host smart-8a525e9c-09db-495e-9ba9-0a6893a70851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704062549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1704062549
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1842406207
Short name T789
Test name
Test status
Simulation time 31512055 ps
CPU time 1.04 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:14:12 PM PDT 24
Peak memory 215044 kb
Host smart-d4ac9ecb-0600-4036-a1d8-b18dddcfa5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842406207 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1842406207
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1008856268
Short name T674
Test name
Test status
Simulation time 44277851 ps
CPU time 0.98 seconds
Started May 21 02:14:11 PM PDT 24
Finished May 21 02:14:17 PM PDT 24
Peak memory 214964 kb
Host smart-e50480d4-4005-4c63-bf92-910b44178936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008856268 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1008856268
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3663740476
Short name T832
Test name
Test status
Simulation time 240929482 ps
CPU time 4.84 seconds
Started May 21 02:14:06 PM PDT 24
Finished May 21 02:14:16 PM PDT 24
Peak memory 216620 kb
Host smart-0c204895-159c-4b4a-aa4d-3bdc26ec36b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663740476 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3663740476
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2523074202
Short name T625
Test name
Test status
Simulation time 126402472226 ps
CPU time 1689.16 seconds
Started May 21 02:14:09 PM PDT 24
Finished May 21 02:42:23 PM PDT 24
Peak memory 224612 kb
Host smart-6bda64f4-d8c8-464e-a93a-a52cc086d562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523074202 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2523074202
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3189076396
Short name T762
Test name
Test status
Simulation time 45345199 ps
CPU time 1.23 seconds
Started May 21 02:24:18 PM PDT 24
Finished May 21 02:24:19 PM PDT 24
Peak memory 217992 kb
Host smart-90112612-50d7-4171-ae34-7bbcdfe8a450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189076396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3189076396
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2248907577
Short name T765
Test name
Test status
Simulation time 119691305 ps
CPU time 1.3 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:24:26 PM PDT 24
Peak memory 218316 kb
Host smart-ae98d5d3-9581-4f07-84cd-129072b29b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248907577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2248907577
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.3439291562
Short name T696
Test name
Test status
Simulation time 28628440 ps
CPU time 1.33 seconds
Started May 21 02:24:20 PM PDT 24
Finished May 21 02:24:23 PM PDT 24
Peak memory 217964 kb
Host smart-f77a2e30-f599-47e5-a4d6-dc4def230042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439291562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3439291562
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4054602031
Short name T594
Test name
Test status
Simulation time 98063990 ps
CPU time 1.27 seconds
Started May 21 02:24:19 PM PDT 24
Finished May 21 02:24:21 PM PDT 24
Peak memory 218980 kb
Host smart-77f5d1e1-df9b-49c3-b7f1-9eaf059ae069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054602031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4054602031
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1938544083
Short name T360
Test name
Test status
Simulation time 64714629 ps
CPU time 1.24 seconds
Started May 21 02:24:21 PM PDT 24
Finished May 21 02:24:23 PM PDT 24
Peak memory 218524 kb
Host smart-aec6af41-a94f-4a6c-afdc-ce6053824f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938544083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1938544083
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4042384831
Short name T604
Test name
Test status
Simulation time 45503662 ps
CPU time 1.99 seconds
Started May 21 02:24:25 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 219380 kb
Host smart-f1b08d92-c13d-416e-853e-d912f3bfb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042384831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4042384831
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4264689406
Short name T775
Test name
Test status
Simulation time 54401553 ps
CPU time 1.25 seconds
Started May 21 02:24:25 PM PDT 24
Finished May 21 02:24:27 PM PDT 24
Peak memory 218260 kb
Host smart-57f9023f-ba89-47b9-b059-32daf332c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264689406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4264689406
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1703137017
Short name T311
Test name
Test status
Simulation time 538064813 ps
CPU time 4.31 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:24:30 PM PDT 24
Peak memory 219540 kb
Host smart-84b5650d-21d5-426f-b2b1-4e8fc49a8beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703137017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1703137017
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1231406787
Short name T451
Test name
Test status
Simulation time 39863474 ps
CPU time 1.15 seconds
Started May 21 02:24:26 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 216804 kb
Host smart-55822b34-2799-4e20-a9d1-605ec91163b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231406787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1231406787
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.513795829
Short name T675
Test name
Test status
Simulation time 127955110 ps
CPU time 1.55 seconds
Started May 21 02:24:28 PM PDT 24
Finished May 21 02:24:31 PM PDT 24
Peak memory 216704 kb
Host smart-47c2607c-718b-4dac-b780-94b26ff00840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513795829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.513795829
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3086997087
Short name T199
Test name
Test status
Simulation time 46548495 ps
CPU time 1.14 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 215328 kb
Host smart-a76b557c-21f8-430a-8f36-aa738a0de2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086997087 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3086997087
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2510039435
Short name T497
Test name
Test status
Simulation time 35963448 ps
CPU time 1.08 seconds
Started May 21 02:14:07 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 214492 kb
Host smart-f33b085f-7cbf-487e-857b-9530ce1e2b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510039435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2510039435
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3119405808
Short name T825
Test name
Test status
Simulation time 13663540 ps
CPU time 0.92 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 215336 kb
Host smart-5df9c2c4-3505-4530-929f-254ec0e5c624
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119405808 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3119405808
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.2112163113
Short name T340
Test name
Test status
Simulation time 23133707 ps
CPU time 1.02 seconds
Started May 21 02:14:09 PM PDT 24
Finished May 21 02:14:14 PM PDT 24
Peak memory 218340 kb
Host smart-1b26fe5c-6df4-42b6-9f78-2a372cb871d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112163113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2112163113
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.305290075
Short name T839
Test name
Test status
Simulation time 38395275 ps
CPU time 1.08 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 216632 kb
Host smart-808e6161-6ef9-4278-b6f4-2e7bce13bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305290075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.305290075
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3355966754
Short name T465
Test name
Test status
Simulation time 37923438 ps
CPU time 1.05 seconds
Started May 21 02:14:11 PM PDT 24
Finished May 21 02:14:16 PM PDT 24
Peak memory 223396 kb
Host smart-5752ae95-4bea-4067-8c20-5ee3ce89247d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355966754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3355966754
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2501662197
Short name T541
Test name
Test status
Simulation time 24769518 ps
CPU time 0.92 seconds
Started May 21 02:14:06 PM PDT 24
Finished May 21 02:14:12 PM PDT 24
Peak memory 214948 kb
Host smart-e860fa08-b420-4f31-92ca-1b075ca8da60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501662197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2501662197
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1702966765
Short name T418
Test name
Test status
Simulation time 402806916 ps
CPU time 1.71 seconds
Started May 21 02:14:06 PM PDT 24
Finished May 21 02:14:13 PM PDT 24
Peak memory 214964 kb
Host smart-8665f879-726e-4029-9cab-9c2be136e694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702966765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1702966765
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1187827734
Short name T826
Test name
Test status
Simulation time 246692324113 ps
CPU time 1430.62 seconds
Started May 21 02:14:08 PM PDT 24
Finished May 21 02:38:03 PM PDT 24
Peak memory 223016 kb
Host smart-815a644b-1c89-47b4-a4b8-02ed9554001d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187827734 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1187827734
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1164632249
Short name T421
Test name
Test status
Simulation time 37397112 ps
CPU time 1.45 seconds
Started May 21 02:24:28 PM PDT 24
Finished May 21 02:24:30 PM PDT 24
Peak memory 216624 kb
Host smart-ab6cf48c-260b-4b22-9364-6d67b66bc2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164632249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1164632249
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.403916461
Short name T831
Test name
Test status
Simulation time 9125238847 ps
CPU time 127.9 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:26:33 PM PDT 24
Peak memory 216988 kb
Host smart-7a8beb72-b0ea-4ddd-b5da-0995a802f263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403916461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.403916461
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2571031257
Short name T502
Test name
Test status
Simulation time 56762331 ps
CPU time 1.92 seconds
Started May 21 02:24:26 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 217884 kb
Host smart-a2a984ca-ecea-4330-81d5-9c523b5109f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571031257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2571031257
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2034422607
Short name T333
Test name
Test status
Simulation time 48539053 ps
CPU time 1.68 seconds
Started May 21 02:24:26 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 217960 kb
Host smart-a54f8fcd-d8ff-42dc-af9c-7576507c38ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034422607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2034422607
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1378506188
Short name T785
Test name
Test status
Simulation time 83326029 ps
CPU time 1.14 seconds
Started May 21 02:24:27 PM PDT 24
Finished May 21 02:24:29 PM PDT 24
Peak memory 216700 kb
Host smart-83fd4584-210c-40bb-8090-d14d99876bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378506188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1378506188
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.4087708185
Short name T401
Test name
Test status
Simulation time 64652185 ps
CPU time 1.53 seconds
Started May 21 02:24:27 PM PDT 24
Finished May 21 02:24:30 PM PDT 24
Peak memory 218016 kb
Host smart-adbf1475-a4f2-4ecc-bbe1-dbc33bd60b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087708185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4087708185
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2183982491
Short name T569
Test name
Test status
Simulation time 223273102 ps
CPU time 3.33 seconds
Started May 21 02:24:24 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 216904 kb
Host smart-a2440b4d-c528-4369-b06f-3ed4bd915f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183982491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2183982491
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1587619353
Short name T637
Test name
Test status
Simulation time 39546783 ps
CPU time 1.44 seconds
Started May 21 02:24:26 PM PDT 24
Finished May 21 02:24:28 PM PDT 24
Peak memory 216692 kb
Host smart-cc3a3043-2774-4fc5-bcad-542a8b15196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587619353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1587619353
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2415171649
Short name T626
Test name
Test status
Simulation time 47488193 ps
CPU time 1.28 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:38 PM PDT 24
Peak memory 219304 kb
Host smart-ea3057a4-ee31-4a85-8d7e-c5e2adbdf79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415171649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2415171649
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2318711992
Short name T346
Test name
Test status
Simulation time 84901759 ps
CPU time 1.75 seconds
Started May 21 02:24:30 PM PDT 24
Finished May 21 02:24:33 PM PDT 24
Peak memory 218024 kb
Host smart-f0ff6ff3-3fee-450b-9106-604fcc16e2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318711992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2318711992
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.3999398675
Short name T318
Test name
Test status
Simulation time 18452736 ps
CPU time 1.08 seconds
Started May 21 02:13:00 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 206272 kb
Host smart-7d62c954-eed8-44be-ad63-cac29ea378e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999398675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3999398675
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2797291620
Short name T62
Test name
Test status
Simulation time 38834008 ps
CPU time 0.91 seconds
Started May 21 02:12:53 PM PDT 24
Finished May 21 02:12:57 PM PDT 24
Peak memory 216156 kb
Host smart-3c6fa415-dd10-4033-9f29-113340bf43ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797291620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2797291620
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1595669638
Short name T428
Test name
Test status
Simulation time 39411958 ps
CPU time 1.25 seconds
Started May 21 02:12:56 PM PDT 24
Finished May 21 02:13:01 PM PDT 24
Peak memory 216560 kb
Host smart-81316fcb-6291-435c-82a9-8f46a2a60b8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595669638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1595669638
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.603599600
Short name T705
Test name
Test status
Simulation time 27354349 ps
CPU time 0.99 seconds
Started May 21 02:12:53 PM PDT 24
Finished May 21 02:12:57 PM PDT 24
Peak memory 219544 kb
Host smart-0dd189eb-3a3f-4307-b2fe-dbcf6c495eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603599600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.603599600
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2933908400
Short name T756
Test name
Test status
Simulation time 54113369 ps
CPU time 1.47 seconds
Started May 21 02:12:50 PM PDT 24
Finished May 21 02:12:55 PM PDT 24
Peak memory 216776 kb
Host smart-749b4911-9539-4d9b-991e-462e155b4f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933908400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2933908400
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.337129361
Short name T636
Test name
Test status
Simulation time 29437232 ps
CPU time 0.96 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:53 PM PDT 24
Peak memory 215072 kb
Host smart-a65b3ad8-4036-40b6-8d08-e4a968321e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337129361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.337129361
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.826275796
Short name T469
Test name
Test status
Simulation time 17562765 ps
CPU time 1.03 seconds
Started May 21 02:12:52 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 214996 kb
Host smart-4df77c21-b5c4-419d-b2e9-5118a0c27ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826275796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.826275796
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.265735299
Short name T316
Test name
Test status
Simulation time 157393323 ps
CPU time 3.67 seconds
Started May 21 02:12:49 PM PDT 24
Finished May 21 02:12:56 PM PDT 24
Peak memory 216472 kb
Host smart-1388fc70-c213-428b-98c8-56bbee02d0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265735299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.265735299
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4116991270
Short name T480
Test name
Test status
Simulation time 52870722411 ps
CPU time 1218.22 seconds
Started May 21 02:12:52 PM PDT 24
Finished May 21 02:33:14 PM PDT 24
Peak memory 219688 kb
Host smart-1d73ed70-9b3b-47b6-903d-d335ea90ffde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116991270 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4116991270
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1903810263
Short name T296
Test name
Test status
Simulation time 30162105 ps
CPU time 1.27 seconds
Started May 21 02:14:04 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 215396 kb
Host smart-cb58c048-c60a-4e3b-93d3-437f597ec558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903810263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1903810263
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2487777864
Short name T840
Test name
Test status
Simulation time 18373064 ps
CPU time 0.95 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 206484 kb
Host smart-f345c463-aa7c-4d2a-8fa8-f1b1e9ed5570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487777864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2487777864
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3895935048
Short name T176
Test name
Test status
Simulation time 35728127 ps
CPU time 1.33 seconds
Started May 21 02:14:17 PM PDT 24
Finished May 21 02:14:22 PM PDT 24
Peak memory 216664 kb
Host smart-aff0caaf-2919-476a-8272-b17484cae900
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895935048 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3895935048
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.766721688
Short name T640
Test name
Test status
Simulation time 19499645 ps
CPU time 1.1 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 217972 kb
Host smart-a179ce02-5539-4af9-80f6-efd4c9cf601a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766721688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.766721688
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.1035693932
Short name T227
Test name
Test status
Simulation time 25171798 ps
CPU time 0.95 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 215424 kb
Host smart-a8562302-d8e8-48b7-94b5-55c0f30674d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035693932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1035693932
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2370468075
Short name T331
Test name
Test status
Simulation time 37705647 ps
CPU time 0.97 seconds
Started May 21 02:14:05 PM PDT 24
Finished May 21 02:14:11 PM PDT 24
Peak memory 214920 kb
Host smart-b8d14c29-e724-4707-9cbc-5cfbb7a59011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370468075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2370468075
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3827566664
Short name T808
Test name
Test status
Simulation time 318670848 ps
CPU time 2.36 seconds
Started May 21 02:14:12 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 214964 kb
Host smart-739f5b7d-cb75-4c07-bb97-03b83b60a7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827566664 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3827566664
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.693857488
Short name T757
Test name
Test status
Simulation time 56429702115 ps
CPU time 1203.93 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:34:18 PM PDT 24
Peak memory 223404 kb
Host smart-bffeb175-ed5b-4109-9f07-612309a47f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693857488 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.693857488
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2464233005
Short name T512
Test name
Test status
Simulation time 83120364 ps
CPU time 1.13 seconds
Started May 21 02:24:30 PM PDT 24
Finished May 21 02:24:32 PM PDT 24
Peak memory 216520 kb
Host smart-61f280fb-6cb7-4f35-b4e0-19a60c750500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464233005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2464233005
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.656388782
Short name T726
Test name
Test status
Simulation time 35460164 ps
CPU time 1.56 seconds
Started May 21 02:24:33 PM PDT 24
Finished May 21 02:24:36 PM PDT 24
Peak memory 218120 kb
Host smart-ea5f66ed-ee88-48f3-a4b4-496cc2d0c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656388782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.656388782
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3939003299
Short name T447
Test name
Test status
Simulation time 108520420 ps
CPU time 1.66 seconds
Started May 21 02:24:31 PM PDT 24
Finished May 21 02:24:33 PM PDT 24
Peak memory 218152 kb
Host smart-ec5b3861-4acc-45f5-962f-b4aa2c906366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939003299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3939003299
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.877796046
Short name T501
Test name
Test status
Simulation time 97302138 ps
CPU time 1.16 seconds
Started May 21 02:24:34 PM PDT 24
Finished May 21 02:24:36 PM PDT 24
Peak memory 216812 kb
Host smart-a9e03d97-da07-4c27-8577-ebd131f000c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877796046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.877796046
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3973013675
Short name T388
Test name
Test status
Simulation time 38976432 ps
CPU time 1.42 seconds
Started May 21 02:24:33 PM PDT 24
Finished May 21 02:24:35 PM PDT 24
Peak memory 216716 kb
Host smart-ea2c34a7-c171-4a37-8a98-51c0555e14c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973013675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3973013675
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3074855888
Short name T667
Test name
Test status
Simulation time 118487001 ps
CPU time 1.14 seconds
Started May 21 02:24:30 PM PDT 24
Finished May 21 02:24:32 PM PDT 24
Peak memory 216816 kb
Host smart-62293cec-4eac-40b6-9ab4-2dbf3357f3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074855888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3074855888
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3230444225
Short name T844
Test name
Test status
Simulation time 87603175 ps
CPU time 1.13 seconds
Started May 21 02:24:32 PM PDT 24
Finished May 21 02:24:34 PM PDT 24
Peak memory 216780 kb
Host smart-85525850-098e-48d9-9ae1-52cf849aa909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230444225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3230444225
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3146402972
Short name T616
Test name
Test status
Simulation time 393836347 ps
CPU time 1.21 seconds
Started May 21 02:24:31 PM PDT 24
Finished May 21 02:24:33 PM PDT 24
Peak memory 216896 kb
Host smart-2bfbd097-0590-496a-978c-776a2dac5017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146402972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3146402972
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2835969207
Short name T223
Test name
Test status
Simulation time 31042477 ps
CPU time 1.28 seconds
Started May 21 02:24:33 PM PDT 24
Finished May 21 02:24:35 PM PDT 24
Peak memory 216644 kb
Host smart-75008ca6-1055-4555-90c0-c3b289c4c625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835969207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2835969207
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3785835001
Short name T568
Test name
Test status
Simulation time 86129980 ps
CPU time 1.21 seconds
Started May 21 02:14:11 PM PDT 24
Finished May 21 02:14:16 PM PDT 24
Peak memory 215392 kb
Host smart-a5072fb4-03f7-483b-b276-8ffc7af6bb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785835001 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3785835001
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3055500101
Short name T638
Test name
Test status
Simulation time 104381911 ps
CPU time 0.89 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 206264 kb
Host smart-64e78867-5636-4b17-b849-2e71a65b05d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055500101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3055500101
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4042641406
Short name T181
Test name
Test status
Simulation time 22200434 ps
CPU time 0.89 seconds
Started May 21 02:14:17 PM PDT 24
Finished May 21 02:14:22 PM PDT 24
Peak memory 216036 kb
Host smart-57b2e6cf-6370-4e3f-9029-5d7950fa2341
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042641406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4042641406
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.1635716832
Short name T629
Test name
Test status
Simulation time 50188091 ps
CPU time 1.01 seconds
Started May 21 02:14:10 PM PDT 24
Finished May 21 02:14:15 PM PDT 24
Peak memory 217684 kb
Host smart-bd45135c-d610-48b9-9056-a703e5cb3bc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635716832 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.1635716832
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3896774122
Short name T183
Test name
Test status
Simulation time 44956616 ps
CPU time 1.29 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 219224 kb
Host smart-dcaaf412-582c-4b3f-9c22-c143421ecc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896774122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3896774122
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2810239809
Short name T531
Test name
Test status
Simulation time 53408186 ps
CPU time 1.25 seconds
Started May 21 02:14:15 PM PDT 24
Finished May 21 02:14:21 PM PDT 24
Peak memory 214868 kb
Host smart-044281b9-2b7b-45d8-a4c4-929291cc05e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810239809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2810239809
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1911505959
Short name T597
Test name
Test status
Simulation time 33324655 ps
CPU time 1.02 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 223604 kb
Host smart-79d928a9-b73f-4b4c-89a5-6ab3359e22d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911505959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1911505959
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3284928518
Short name T593
Test name
Test status
Simulation time 19127746 ps
CPU time 1.09 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 214968 kb
Host smart-a4acaa07-65dd-4c88-9bcf-905544886fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284928518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3284928518
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4221729186
Short name T804
Test name
Test status
Simulation time 449360937 ps
CPU time 3.79 seconds
Started May 21 02:14:16 PM PDT 24
Finished May 21 02:14:24 PM PDT 24
Peak memory 217824 kb
Host smart-6ee8f245-31a1-445e-b3fd-563b40de5546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221729186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4221729186
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2427425738
Short name T281
Test name
Test status
Simulation time 1044276086546 ps
CPU time 1661.42 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:42:00 PM PDT 24
Peak memory 224092 kb
Host smart-cc0fffc4-7ab3-4899-bd7b-f1a0b2e2340a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427425738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2427425738
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2799959142
Short name T655
Test name
Test status
Simulation time 67693940 ps
CPU time 1.09 seconds
Started May 21 02:24:35 PM PDT 24
Finished May 21 02:24:36 PM PDT 24
Peak memory 219260 kb
Host smart-8992a207-0810-4293-a96d-064e4ef0d394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799959142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2799959142
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2991396068
Short name T66
Test name
Test status
Simulation time 32765959 ps
CPU time 1.44 seconds
Started May 21 02:24:31 PM PDT 24
Finished May 21 02:24:33 PM PDT 24
Peak memory 219400 kb
Host smart-716c7611-cdf9-4229-ab09-90dea9850423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991396068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2991396068
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1934578918
Short name T540
Test name
Test status
Simulation time 151162152 ps
CPU time 1.57 seconds
Started May 21 02:24:33 PM PDT 24
Finished May 21 02:24:36 PM PDT 24
Peak memory 218172 kb
Host smart-a846215b-6539-43fd-b8d8-6740650573c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934578918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1934578918
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3937814379
Short name T345
Test name
Test status
Simulation time 32199240 ps
CPU time 1.1 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:39 PM PDT 24
Peak memory 218304 kb
Host smart-74e5e968-af08-4cb4-a5e0-a24803217195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937814379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3937814379
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1438077870
Short name T809
Test name
Test status
Simulation time 32967355 ps
CPU time 1.41 seconds
Started May 21 02:24:38 PM PDT 24
Finished May 21 02:24:41 PM PDT 24
Peak memory 217924 kb
Host smart-e08378f2-0d21-489d-97b2-b4dd9e06a701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438077870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1438077870
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1484619937
Short name T769
Test name
Test status
Simulation time 35861831 ps
CPU time 1.62 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:39 PM PDT 24
Peak memory 219676 kb
Host smart-cc11608b-8260-4bdc-ab5b-c12f506e2ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484619937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1484619937
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.676058093
Short name T258
Test name
Test status
Simulation time 238892957 ps
CPU time 3.38 seconds
Started May 21 02:24:39 PM PDT 24
Finished May 21 02:24:43 PM PDT 24
Peak memory 219624 kb
Host smart-cc97b794-9198-46db-ba60-9f08f315cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676058093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.676058093
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1719889042
Short name T12
Test name
Test status
Simulation time 41196600 ps
CPU time 1.54 seconds
Started May 21 02:24:43 PM PDT 24
Finished May 21 02:24:46 PM PDT 24
Peak memory 219244 kb
Host smart-d8d1999d-efee-41de-b1b1-65a1ad5bcf80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719889042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1719889042
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2127728333
Short name T580
Test name
Test status
Simulation time 51086613 ps
CPU time 1.23 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:39 PM PDT 24
Peak memory 217920 kb
Host smart-b2dfb319-2eaf-4ee9-ae0b-ab3f4700da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127728333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2127728333
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.661748221
Short name T268
Test name
Test status
Simulation time 38409588 ps
CPU time 1.25 seconds
Started May 21 02:14:12 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 215356 kb
Host smart-b56e559e-e9bf-4b92-bbc5-c9d968855095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661748221 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.661748221
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2173267906
Short name T582
Test name
Test status
Simulation time 15359048 ps
CPU time 0.99 seconds
Started May 21 02:14:15 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 206276 kb
Host smart-52b10c48-a158-491e-a9bc-602e3dccb5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173267906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2173267906
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2191721569
Short name T836
Test name
Test status
Simulation time 11277975 ps
CPU time 0.94 seconds
Started May 21 02:14:12 PM PDT 24
Finished May 21 02:14:17 PM PDT 24
Peak memory 216032 kb
Host smart-9883461b-8008-4e4b-aff0-945a621ef0e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191721569 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2191721569
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1025447100
Short name T250
Test name
Test status
Simulation time 47309936 ps
CPU time 1.06 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 217892 kb
Host smart-cc45c2a8-90e2-42cc-a581-a8215c3527d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025447100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1025447100
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.224246490
Short name T118
Test name
Test status
Simulation time 45498380 ps
CPU time 1.3 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 225280 kb
Host smart-7a7f2def-f378-4e53-9c68-c48ec385f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224246490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.224246490
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3388289107
Short name T394
Test name
Test status
Simulation time 206481477 ps
CPU time 1.96 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 218184 kb
Host smart-ec53a28d-216e-4225-918d-ba78e1a3a962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388289107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3388289107
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3822682792
Short name T359
Test name
Test status
Simulation time 26710765 ps
CPU time 0.93 seconds
Started May 21 02:14:12 PM PDT 24
Finished May 21 02:14:18 PM PDT 24
Peak memory 215032 kb
Host smart-a1cf27d9-299a-4b78-a9d6-b2b977b3e018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822682792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3822682792
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1954719221
Short name T358
Test name
Test status
Simulation time 18497053 ps
CPU time 1.06 seconds
Started May 21 02:14:15 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 214956 kb
Host smart-b335d9de-fab9-43a0-959a-a882093d6b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954719221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1954719221
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3844253458
Short name T820
Test name
Test status
Simulation time 52954656 ps
CPU time 1.03 seconds
Started May 21 02:14:15 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 214996 kb
Host smart-755b47c8-79a6-4538-aa85-bf75f35b6f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844253458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3844253458
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3156582728
Short name T799
Test name
Test status
Simulation time 21477421856 ps
CPU time 495.09 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:22:33 PM PDT 24
Peak memory 223480 kb
Host smart-dabff87a-08fd-45fa-9318-462ceac508e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156582728 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3156582728
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3557532607
Short name T275
Test name
Test status
Simulation time 37408415 ps
CPU time 1.43 seconds
Started May 21 02:24:36 PM PDT 24
Finished May 21 02:24:38 PM PDT 24
Peak memory 217988 kb
Host smart-955454b8-8619-4f86-8346-ed465d73c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557532607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3557532607
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.821944964
Short name T688
Test name
Test status
Simulation time 80109680 ps
CPU time 2.61 seconds
Started May 21 02:24:38 PM PDT 24
Finished May 21 02:24:41 PM PDT 24
Peak memory 219128 kb
Host smart-cf712c6c-dea3-4451-a0b9-88af06550fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821944964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.821944964
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2489136797
Short name T461
Test name
Test status
Simulation time 39233892 ps
CPU time 1.09 seconds
Started May 21 02:24:39 PM PDT 24
Finished May 21 02:24:41 PM PDT 24
Peak memory 216584 kb
Host smart-94a3e09c-53fd-4a98-b12d-d8eb885e21bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489136797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2489136797
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2169651346
Short name T750
Test name
Test status
Simulation time 157739710 ps
CPU time 3.45 seconds
Started May 21 02:24:38 PM PDT 24
Finished May 21 02:24:43 PM PDT 24
Peak memory 218716 kb
Host smart-132422aa-b132-4a68-b764-170665f7a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169651346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2169651346
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.524445790
Short name T845
Test name
Test status
Simulation time 58411859 ps
CPU time 2.12 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:40 PM PDT 24
Peak memory 218008 kb
Host smart-e29eea6c-95c3-456e-a3d1-db47faa6db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524445790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.524445790
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.202258017
Short name T347
Test name
Test status
Simulation time 30758189 ps
CPU time 1.31 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:40 PM PDT 24
Peak memory 217736 kb
Host smart-97a1ea35-9423-40a0-bdb6-b092aef229fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202258017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.202258017
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1267845031
Short name T790
Test name
Test status
Simulation time 122669406 ps
CPU time 1.85 seconds
Started May 21 02:24:39 PM PDT 24
Finished May 21 02:24:42 PM PDT 24
Peak memory 218252 kb
Host smart-1d65584b-58a9-4c98-8b3a-197847903937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267845031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1267845031
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1078244737
Short name T622
Test name
Test status
Simulation time 59254096 ps
CPU time 1.3 seconds
Started May 21 02:24:43 PM PDT 24
Finished May 21 02:24:46 PM PDT 24
Peak memory 217848 kb
Host smart-7083845d-a9fd-491c-84d1-faa2acbc90ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078244737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1078244737
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1032400480
Short name T496
Test name
Test status
Simulation time 244001752 ps
CPU time 1.64 seconds
Started May 21 02:24:37 PM PDT 24
Finished May 21 02:24:40 PM PDT 24
Peak memory 219780 kb
Host smart-40a96a0e-1798-4f72-a59c-75f7de9f5158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032400480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1032400480
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3156575532
Short name T79
Test name
Test status
Simulation time 58560764 ps
CPU time 1.16 seconds
Started May 21 02:24:45 PM PDT 24
Finished May 21 02:24:47 PM PDT 24
Peak memory 218032 kb
Host smart-0c170459-e70c-431c-b80b-c252ece4ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156575532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3156575532
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3593652373
Short name T267
Test name
Test status
Simulation time 76486212 ps
CPU time 1.17 seconds
Started May 21 02:14:16 PM PDT 24
Finished May 21 02:14:21 PM PDT 24
Peak memory 215280 kb
Host smart-0a865e10-2b77-4359-b2ea-ba7b23aa2b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593652373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3593652373
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1919780086
Short name T24
Test name
Test status
Simulation time 17458320 ps
CPU time 1.01 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 206292 kb
Host smart-3d6d2458-5a8b-4b30-b4df-2b4264afc3d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919780086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1919780086
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.491661932
Short name T554
Test name
Test status
Simulation time 75872563 ps
CPU time 1.08 seconds
Started May 21 02:14:19 PM PDT 24
Finished May 21 02:14:24 PM PDT 24
Peak memory 216680 kb
Host smart-ef3c3642-440d-49e4-a6e4-86bda249e348
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491661932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.491661932
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1322734391
Short name T656
Test name
Test status
Simulation time 35362500 ps
CPU time 1.16 seconds
Started May 21 02:14:13 PM PDT 24
Finished May 21 02:14:19 PM PDT 24
Peak memory 229228 kb
Host smart-67a286d6-3132-465c-bda8-08cf8b545843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322734391 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1322734391
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3311452161
Short name T272
Test name
Test status
Simulation time 35545860 ps
CPU time 1.37 seconds
Started May 21 02:14:16 PM PDT 24
Finished May 21 02:14:21 PM PDT 24
Peak memory 217884 kb
Host smart-8341d0db-eb73-429f-a04e-a2ea8af8cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311452161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3311452161
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3962173368
Short name T161
Test name
Test status
Simulation time 25145487 ps
CPU time 0.96 seconds
Started May 21 02:14:15 PM PDT 24
Finished May 21 02:14:20 PM PDT 24
Peak memory 215324 kb
Host smart-6243bf4e-9490-454d-abba-c252265d8e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962173368 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3962173368
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.4132262883
Short name T317
Test name
Test status
Simulation time 16792252 ps
CPU time 0.99 seconds
Started May 21 02:14:16 PM PDT 24
Finished May 21 02:14:22 PM PDT 24
Peak memory 214972 kb
Host smart-36499d03-56f9-47a6-8541-cf58386d45ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132262883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.4132262883
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1486729804
Short name T635
Test name
Test status
Simulation time 471860058 ps
CPU time 4.85 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:14:24 PM PDT 24
Peak memory 217936 kb
Host smart-428b9022-929d-4ce3-957b-4422b8c4dd58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486729804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1486729804
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.155014646
Short name T609
Test name
Test status
Simulation time 438511297220 ps
CPU time 967.62 seconds
Started May 21 02:14:14 PM PDT 24
Finished May 21 02:30:26 PM PDT 24
Peak memory 220544 kb
Host smart-4c4f3185-d6b3-4f83-9b68-696531e677ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155014646 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.155014646
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4015776721
Short name T361
Test name
Test status
Simulation time 36489108 ps
CPU time 1.4 seconds
Started May 21 02:24:42 PM PDT 24
Finished May 21 02:24:44 PM PDT 24
Peak memory 218140 kb
Host smart-7a649d14-a438-4c96-bc36-ab82368b324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015776721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4015776721
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.318261895
Short name T534
Test name
Test status
Simulation time 135918074 ps
CPU time 1.03 seconds
Started May 21 02:24:42 PM PDT 24
Finished May 21 02:24:43 PM PDT 24
Peak memory 216532 kb
Host smart-59c8757b-f3c1-495f-8823-8068b0e67d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318261895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.318261895
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1134534006
Short name T693
Test name
Test status
Simulation time 563666200 ps
CPU time 6.07 seconds
Started May 21 02:24:43 PM PDT 24
Finished May 21 02:24:50 PM PDT 24
Peak memory 219328 kb
Host smart-5c17f3e9-fd03-4a28-8ea7-9a45a90460c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134534006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1134534006
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1314714473
Short name T543
Test name
Test status
Simulation time 73544784 ps
CPU time 1.28 seconds
Started May 21 02:24:44 PM PDT 24
Finished May 21 02:24:46 PM PDT 24
Peak memory 216736 kb
Host smart-48404545-b32c-4ee9-a050-76f96845a9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314714473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1314714473
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2319523494
Short name T350
Test name
Test status
Simulation time 48571922 ps
CPU time 1.6 seconds
Started May 21 02:24:42 PM PDT 24
Finished May 21 02:24:44 PM PDT 24
Peak memory 216764 kb
Host smart-8997602f-6023-417b-bee0-75e68eff4087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319523494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2319523494
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4108357805
Short name T42
Test name
Test status
Simulation time 32555044 ps
CPU time 1.54 seconds
Started May 21 02:24:43 PM PDT 24
Finished May 21 02:24:45 PM PDT 24
Peak memory 216716 kb
Host smart-15d848d4-2eab-4552-8b1b-709e94d55393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108357805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4108357805
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3146096770
Short name T431
Test name
Test status
Simulation time 101062295 ps
CPU time 1.1 seconds
Started May 21 02:24:46 PM PDT 24
Finished May 21 02:24:47 PM PDT 24
Peak memory 219004 kb
Host smart-021aa5e1-26ee-4571-b96c-1a89ecb63f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146096770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3146096770
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.363991362
Short name T684
Test name
Test status
Simulation time 24602288 ps
CPU time 1.23 seconds
Started May 21 02:24:48 PM PDT 24
Finished May 21 02:24:50 PM PDT 24
Peak memory 219276 kb
Host smart-8ac3219f-c9cc-411c-8bf7-54737a6a8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363991362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.363991362
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.619177859
Short name T369
Test name
Test status
Simulation time 150417294 ps
CPU time 3.16 seconds
Started May 21 02:24:44 PM PDT 24
Finished May 21 02:24:48 PM PDT 24
Peak memory 219484 kb
Host smart-4b58da12-08b8-47da-b076-1d100d1efac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619177859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.619177859
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3436149463
Short name T742
Test name
Test status
Simulation time 38315394 ps
CPU time 1.58 seconds
Started May 21 02:24:49 PM PDT 24
Finished May 21 02:24:52 PM PDT 24
Peak memory 217816 kb
Host smart-c5f750c9-6514-404e-a35c-5efc5b897b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436149463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3436149463
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1440295486
Short name T171
Test name
Test status
Simulation time 25044761 ps
CPU time 1.26 seconds
Started May 21 02:14:25 PM PDT 24
Finished May 21 02:14:30 PM PDT 24
Peak memory 215380 kb
Host smart-d5040b32-9cf1-43e4-b2bf-69f52147f15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440295486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1440295486
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3757799212
Short name T749
Test name
Test status
Simulation time 17200847 ps
CPU time 0.96 seconds
Started May 21 02:14:19 PM PDT 24
Finished May 21 02:14:25 PM PDT 24
Peak memory 214524 kb
Host smart-83ebe7cd-ff08-4624-8252-a2554882af4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757799212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3757799212
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1930487386
Short name T725
Test name
Test status
Simulation time 12783859 ps
CPU time 0.92 seconds
Started May 21 02:14:25 PM PDT 24
Finished May 21 02:14:29 PM PDT 24
Peak memory 215964 kb
Host smart-c4ed634b-8c7d-4f02-80e3-7cf696ee6ea2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930487386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1930487386
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2047486368
Short name T392
Test name
Test status
Simulation time 37762366 ps
CPU time 1.21 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 217920 kb
Host smart-4030fd69-e19e-45d6-adad-3f01cdc473ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047486368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2047486368
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.912756646
Short name T128
Test name
Test status
Simulation time 33814702 ps
CPU time 0.98 seconds
Started May 21 02:14:19 PM PDT 24
Finished May 21 02:14:24 PM PDT 24
Peak memory 223276 kb
Host smart-2bfa6a01-6f8a-466c-8da4-2cc513a75842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912756646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.912756646
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2880003762
Short name T446
Test name
Test status
Simulation time 66298556 ps
CPU time 1.47 seconds
Started May 21 02:14:23 PM PDT 24
Finished May 21 02:14:28 PM PDT 24
Peak memory 218100 kb
Host smart-5f279072-2b3a-426a-998f-12ca7ae41e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880003762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2880003762
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4103247708
Short name T169
Test name
Test status
Simulation time 26489557 ps
CPU time 0.89 seconds
Started May 21 02:14:20 PM PDT 24
Finished May 21 02:14:25 PM PDT 24
Peak memory 215200 kb
Host smart-5ef4cdc7-ec4b-4964-b043-8637aa82d413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103247708 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4103247708
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.590153861
Short name T599
Test name
Test status
Simulation time 20131559 ps
CPU time 1 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 215004 kb
Host smart-7fc74046-356f-4f3c-b1ce-708461d2e348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590153861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.590153861
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.531941530
Short name T368
Test name
Test status
Simulation time 168194690 ps
CPU time 3.86 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:30 PM PDT 24
Peak memory 216464 kb
Host smart-5f51272c-9467-4ccf-908b-5dc60b1e7617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531941530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.531941530
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2692236973
Short name T213
Test name
Test status
Simulation time 27353769934 ps
CPU time 291.57 seconds
Started May 21 02:14:25 PM PDT 24
Finished May 21 02:19:21 PM PDT 24
Peak memory 218336 kb
Host smart-1d1dd616-3c2b-494f-a817-560a480e6007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692236973 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2692236973
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2524395268
Short name T761
Test name
Test status
Simulation time 75829317 ps
CPU time 1.55 seconds
Started May 21 02:24:51 PM PDT 24
Finished May 21 02:24:54 PM PDT 24
Peak memory 219248 kb
Host smart-f048a9fe-a791-48f5-b8ac-fdba5ee7255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524395268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2524395268
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3527306918
Short name T618
Test name
Test status
Simulation time 37218581 ps
CPU time 1.38 seconds
Started May 21 02:24:50 PM PDT 24
Finished May 21 02:24:52 PM PDT 24
Peak memory 216592 kb
Host smart-cca985aa-06b4-4e0e-829b-d607e746cd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527306918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3527306918
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.142098417
Short name T507
Test name
Test status
Simulation time 93142271 ps
CPU time 1.33 seconds
Started May 21 02:24:50 PM PDT 24
Finished May 21 02:24:52 PM PDT 24
Peak memory 218368 kb
Host smart-3c5e09e2-8145-435f-a676-b72e98940003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142098417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.142098417
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3245775031
Short name T767
Test name
Test status
Simulation time 34597124 ps
CPU time 1.44 seconds
Started May 21 02:24:49 PM PDT 24
Finished May 21 02:24:52 PM PDT 24
Peak memory 218020 kb
Host smart-a16b16ab-9b39-44e7-917e-e0a4d348d26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245775031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3245775031
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2508424910
Short name T639
Test name
Test status
Simulation time 90441392 ps
CPU time 1.86 seconds
Started May 21 02:24:50 PM PDT 24
Finished May 21 02:24:53 PM PDT 24
Peak memory 217948 kb
Host smart-97c0ecc3-d523-4b79-84b8-fecadbb70c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508424910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2508424910
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.422899190
Short name T748
Test name
Test status
Simulation time 76263822 ps
CPU time 2.94 seconds
Started May 21 02:24:48 PM PDT 24
Finished May 21 02:24:51 PM PDT 24
Peak memory 218568 kb
Host smart-5c7f7d11-bbd9-4a49-afa5-2e5926355c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422899190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.422899190
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.105074989
Short name T768
Test name
Test status
Simulation time 99775181 ps
CPU time 1.3 seconds
Started May 21 02:24:49 PM PDT 24
Finished May 21 02:24:51 PM PDT 24
Peak memory 219120 kb
Host smart-7e268673-39a4-4dd0-bc7b-4f29507d1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105074989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.105074989
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1306078685
Short name T657
Test name
Test status
Simulation time 124280388 ps
CPU time 1.62 seconds
Started May 21 02:24:50 PM PDT 24
Finished May 21 02:24:53 PM PDT 24
Peak memory 219252 kb
Host smart-e76f4134-7e31-4dc2-a5e6-17137a967115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306078685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1306078685
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.443811702
Short name T13
Test name
Test status
Simulation time 36788599 ps
CPU time 1.35 seconds
Started May 21 02:24:56 PM PDT 24
Finished May 21 02:24:58 PM PDT 24
Peak memory 218956 kb
Host smart-99ead46c-b15a-4076-8a27-07cb5010806d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443811702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.443811702
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.815843951
Short name T737
Test name
Test status
Simulation time 44037923 ps
CPU time 1.18 seconds
Started May 21 02:14:35 PM PDT 24
Finished May 21 02:14:39 PM PDT 24
Peak memory 215404 kb
Host smart-c6e5b324-718b-4353-912c-8ac239836177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815843951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.815843951
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1552547255
Short name T484
Test name
Test status
Simulation time 33967363 ps
CPU time 0.89 seconds
Started May 21 02:14:25 PM PDT 24
Finished May 21 02:14:29 PM PDT 24
Peak memory 206232 kb
Host smart-3f773a6a-c503-4e54-ac9c-a2b64ee2672c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552547255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1552547255
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.261258383
Short name T704
Test name
Test status
Simulation time 22317044 ps
CPU time 0.89 seconds
Started May 21 02:14:29 PM PDT 24
Finished May 21 02:14:34 PM PDT 24
Peak memory 216140 kb
Host smart-02bd22b2-6d8a-4f27-b20f-81d892cc5302
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261258383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.261258383
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.3928019626
Short name T103
Test name
Test status
Simulation time 25239747 ps
CPU time 1.01 seconds
Started May 21 02:14:28 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 219140 kb
Host smart-310e6f78-de20-46c6-9a04-bb95a4ab8d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928019626 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3928019626
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1218230264
Short name T411
Test name
Test status
Simulation time 117317412 ps
CPU time 1.21 seconds
Started May 21 02:14:18 PM PDT 24
Finished May 21 02:14:24 PM PDT 24
Peak memory 218556 kb
Host smart-32211cec-256c-475f-9ab6-f70bab79103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218230264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1218230264
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3949193454
Short name T151
Test name
Test status
Simulation time 22379959 ps
CPU time 1.14 seconds
Started May 21 02:14:27 PM PDT 24
Finished May 21 02:14:32 PM PDT 24
Peak memory 215132 kb
Host smart-46825efb-b1e5-4b56-aeb3-e9460bde3659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949193454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3949193454
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3621771991
Short name T472
Test name
Test status
Simulation time 27256333 ps
CPU time 0.95 seconds
Started May 21 02:14:22 PM PDT 24
Finished May 21 02:14:27 PM PDT 24
Peak memory 214884 kb
Host smart-da1ed600-85b5-4a40-ae58-75ae3c31b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621771991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3621771991
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2397163727
Short name T277
Test name
Test status
Simulation time 233993108 ps
CPU time 4.76 seconds
Started May 21 02:14:26 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 216576 kb
Host smart-f07a5a84-9148-48bb-b3fd-9a65a05e9a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397163727 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2397163727
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1600492056
Short name T209
Test name
Test status
Simulation time 151655739966 ps
CPU time 880.79 seconds
Started May 21 02:14:30 PM PDT 24
Finished May 21 02:29:15 PM PDT 24
Peak memory 223380 kb
Host smart-edcadda2-4bb3-45fc-8cee-aee915f83332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600492056 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1600492056
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3268620575
Short name T322
Test name
Test status
Simulation time 71330811 ps
CPU time 1.11 seconds
Started May 21 02:24:57 PM PDT 24
Finished May 21 02:24:59 PM PDT 24
Peak memory 216712 kb
Host smart-0f9a9e47-a4c2-4be9-ab30-a6037088e905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268620575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3268620575
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2100974993
Short name T508
Test name
Test status
Simulation time 51398873 ps
CPU time 1.03 seconds
Started May 21 02:24:56 PM PDT 24
Finished May 21 02:24:58 PM PDT 24
Peak memory 216728 kb
Host smart-9645b738-d73b-4b19-b5a4-3f4365cfe37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100974993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2100974993
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2504801282
Short name T481
Test name
Test status
Simulation time 51059008 ps
CPU time 1.22 seconds
Started May 21 02:24:58 PM PDT 24
Finished May 21 02:25:00 PM PDT 24
Peak memory 216516 kb
Host smart-9717ee84-d420-4803-8207-16f49c450d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504801282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2504801282
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1170431895
Short name T615
Test name
Test status
Simulation time 693932820 ps
CPU time 4.16 seconds
Started May 21 02:24:57 PM PDT 24
Finished May 21 02:25:03 PM PDT 24
Peak memory 217920 kb
Host smart-cfdc827d-dc8b-476f-a29e-4480561400ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170431895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1170431895
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.7344102
Short name T427
Test name
Test status
Simulation time 81087250 ps
CPU time 1.09 seconds
Started May 21 02:24:55 PM PDT 24
Finished May 21 02:24:56 PM PDT 24
Peak memory 218352 kb
Host smart-3949b714-1d91-46f9-aef3-d05308570d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7344102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.7344102
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3695672158
Short name T560
Test name
Test status
Simulation time 157209250 ps
CPU time 1.47 seconds
Started May 21 02:24:56 PM PDT 24
Finished May 21 02:24:58 PM PDT 24
Peak memory 218412 kb
Host smart-786d6886-40e9-445f-9ca0-daeb849aa679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695672158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3695672158
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2322331924
Short name T440
Test name
Test status
Simulation time 47598979 ps
CPU time 1.66 seconds
Started May 21 02:24:57 PM PDT 24
Finished May 21 02:24:59 PM PDT 24
Peak memory 217940 kb
Host smart-a9d8d99c-4141-4fc1-9f01-4e5217d4163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322331924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2322331924
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1191877711
Short name T794
Test name
Test status
Simulation time 48439021 ps
CPU time 1.54 seconds
Started May 21 02:24:55 PM PDT 24
Finished May 21 02:24:57 PM PDT 24
Peak memory 218084 kb
Host smart-60aff47d-fe43-4252-9f0f-1baa4eccf4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191877711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1191877711
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.94556659
Short name T747
Test name
Test status
Simulation time 67976046 ps
CPU time 1.12 seconds
Started May 21 02:24:57 PM PDT 24
Finished May 21 02:24:59 PM PDT 24
Peak memory 216784 kb
Host smart-abb43749-524f-4279-ad1e-39bffe063c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94556659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.94556659
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2783060616
Short name T355
Test name
Test status
Simulation time 71707648 ps
CPU time 2.54 seconds
Started May 21 02:24:58 PM PDT 24
Finished May 21 02:25:01 PM PDT 24
Peak memory 217988 kb
Host smart-28af7852-55e8-4ed4-85dd-630fd8c88dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783060616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2783060616
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2821859863
Short name T145
Test name
Test status
Simulation time 51055134 ps
CPU time 1.21 seconds
Started May 21 02:14:29 PM PDT 24
Finished May 21 02:14:34 PM PDT 24
Peak memory 215396 kb
Host smart-2c45e08b-dcd3-44fa-97eb-6b7d3c8adf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821859863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2821859863
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2386657539
Short name T548
Test name
Test status
Simulation time 26118302 ps
CPU time 0.89 seconds
Started May 21 02:14:28 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 206280 kb
Host smart-749c8bfb-f412-47d2-ac66-4c33c851438d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386657539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2386657539
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3515029277
Short name T666
Test name
Test status
Simulation time 22432636 ps
CPU time 0.94 seconds
Started May 21 02:14:30 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 215684 kb
Host smart-5b5fee11-d5f2-4d2d-a072-6967b2e8c98f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515029277 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3515029277
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3587144338
Short name T477
Test name
Test status
Simulation time 40656015 ps
CPU time 1.22 seconds
Started May 21 02:14:33 PM PDT 24
Finished May 21 02:14:38 PM PDT 24
Peak memory 217848 kb
Host smart-52b0a90a-f220-41ec-82c7-5a825cc6d524
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587144338 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3587144338
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4179740496
Short name T575
Test name
Test status
Simulation time 53199191 ps
CPU time 0.92 seconds
Started May 21 02:14:27 PM PDT 24
Finished May 21 02:14:33 PM PDT 24
Peak memory 217832 kb
Host smart-4d64a83e-5a3f-4b08-937b-02fb1ff0233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179740496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4179740496
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3598199915
Short name T356
Test name
Test status
Simulation time 153960062 ps
CPU time 3.28 seconds
Started May 21 02:14:29 PM PDT 24
Finished May 21 02:14:37 PM PDT 24
Peak memory 219512 kb
Host smart-47130386-d3bc-4585-8467-0f8573f197e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598199915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3598199915
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.3950990877
Short name T787
Test name
Test status
Simulation time 16471387 ps
CPU time 1.01 seconds
Started May 21 02:14:30 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 214968 kb
Host smart-9cace0d6-8348-44bb-a174-54bb1d6c281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950990877 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3950990877
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.84855677
Short name T743
Test name
Test status
Simulation time 396454287 ps
CPU time 2.01 seconds
Started May 21 02:14:29 PM PDT 24
Finished May 21 02:14:35 PM PDT 24
Peak memory 216388 kb
Host smart-58863c4e-f5b6-4fe0-b4c7-02199fefa0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84855677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.84855677
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1563380741
Short name T385
Test name
Test status
Simulation time 21606206389 ps
CPU time 139.32 seconds
Started May 21 02:14:32 PM PDT 24
Finished May 21 02:16:56 PM PDT 24
Peak memory 218372 kb
Host smart-237f207f-83dc-4024-a615-98b38744a6ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563380741 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1563380741
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/261.edn_genbits.3862515243
Short name T3
Test name
Test status
Simulation time 55847970 ps
CPU time 1.92 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 217924 kb
Host smart-860da778-f81f-4595-9353-163f48937a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862515243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3862515243
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3250885986
Short name T323
Test name
Test status
Simulation time 66872490 ps
CPU time 1.26 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:10 PM PDT 24
Peak memory 216744 kb
Host smart-c52df2de-0b4f-446c-a69a-f9e28ed00aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250885986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3250885986
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4152536193
Short name T698
Test name
Test status
Simulation time 28296032 ps
CPU time 1.36 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 219356 kb
Host smart-3705b92d-ec13-469a-b463-e08add8726ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152536193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4152536193
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2206958067
Short name T326
Test name
Test status
Simulation time 38265522 ps
CPU time 1.37 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 217944 kb
Host smart-4bba1f8c-c370-438f-9062-2caeba36bdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206958067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2206958067
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2250694184
Short name T217
Test name
Test status
Simulation time 77968511 ps
CPU time 1.52 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 218660 kb
Host smart-8f07f5f4-aade-402f-8b48-22980515455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250694184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2250694184
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3140707866
Short name T719
Test name
Test status
Simulation time 37762481 ps
CPU time 1.1 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 216908 kb
Host smart-f93659f2-7fb3-4002-9be1-0e23572f6025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140707866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3140707866
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2289870176
Short name T736
Test name
Test status
Simulation time 116914463 ps
CPU time 3.18 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 214956 kb
Host smart-63f9bf3e-a5bb-4e80-9c19-e0bec647fed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289870176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2289870176
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.320399548
Short name T285
Test name
Test status
Simulation time 109888000 ps
CPU time 1.64 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 216900 kb
Host smart-8d8f83b0-b073-4972-a8b2-acf1933c307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320399548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.320399548
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4001167409
Short name T573
Test name
Test status
Simulation time 20922179 ps
CPU time 1.1 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 218220 kb
Host smart-43584991-a313-4125-a816-598c7906fa26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001167409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4001167409
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1223532443
Short name T727
Test name
Test status
Simulation time 78841943 ps
CPU time 1.14 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:14:39 PM PDT 24
Peak memory 215400 kb
Host smart-ca615a2b-c899-49f3-9a14-f4886c92fd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223532443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1223532443
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2926440443
Short name T51
Test name
Test status
Simulation time 18647732 ps
CPU time 0.95 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:14:39 PM PDT 24
Peak memory 206304 kb
Host smart-3ca4bb62-4406-4382-8c02-cc2dd3ef2cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926440443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2926440443
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.345447169
Short name T194
Test name
Test status
Simulation time 19296751 ps
CPU time 0.84 seconds
Started May 21 02:14:37 PM PDT 24
Finished May 21 02:14:40 PM PDT 24
Peak memory 216044 kb
Host smart-26a02480-9933-4af2-be41-5e77c43e1602
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345447169 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.345447169
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2617203914
Short name T77
Test name
Test status
Simulation time 77867132 ps
CPU time 1 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:14:39 PM PDT 24
Peak memory 219200 kb
Host smart-8558c289-046b-4de2-993f-797ae90d1b46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617203914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2617203914
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3487215801
Short name T595
Test name
Test status
Simulation time 22870435 ps
CPU time 0.88 seconds
Started May 21 02:14:40 PM PDT 24
Finished May 21 02:14:45 PM PDT 24
Peak memory 218028 kb
Host smart-bf2702ba-cfcd-46ef-adea-c513b8e39101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487215801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3487215801
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3024957428
Short name T676
Test name
Test status
Simulation time 39274567 ps
CPU time 1.55 seconds
Started May 21 02:14:33 PM PDT 24
Finished May 21 02:14:38 PM PDT 24
Peak memory 219344 kb
Host smart-6cb6d6fd-6376-407a-be14-b26c3205debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024957428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3024957428
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.636070764
Short name T57
Test name
Test status
Simulation time 21950324 ps
CPU time 1.11 seconds
Started May 21 02:14:38 PM PDT 24
Finished May 21 02:14:45 PM PDT 24
Peak memory 223580 kb
Host smart-05d50b3c-3a6d-40f1-998c-e4f5f8dd00bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636070764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.636070764
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1293551962
Short name T405
Test name
Test status
Simulation time 35505391 ps
CPU time 0.92 seconds
Started May 21 02:14:31 PM PDT 24
Finished May 21 02:14:36 PM PDT 24
Peak memory 215032 kb
Host smart-e0a26980-c421-409b-81b8-3f23f34a14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293551962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1293551962
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1854590276
Short name T810
Test name
Test status
Simulation time 442868113 ps
CPU time 2.95 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:14:40 PM PDT 24
Peak memory 216748 kb
Host smart-c12991a2-4df9-499a-8798-fea1c1c0aa3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854590276 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1854590276
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3420959395
Short name T812
Test name
Test status
Simulation time 518883758894 ps
CPU time 778.77 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:27:36 PM PDT 24
Peak memory 220248 kb
Host smart-45e258b5-54d4-4ef8-8a07-45bf90145874
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420959395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3420959395
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1166531861
Short name T257
Test name
Test status
Simulation time 45404097 ps
CPU time 1.47 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 216624 kb
Host smart-8a8e67c1-de5f-4457-9700-d946461cde25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166531861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1166531861
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3727199630
Short name T577
Test name
Test status
Simulation time 44889716 ps
CPU time 1.47 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 217904 kb
Host smart-12f46d1b-96ca-489e-be18-a0f0b52f4001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727199630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3727199630
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1549780442
Short name T510
Test name
Test status
Simulation time 36373625 ps
CPU time 1.71 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 218100 kb
Host smart-519de849-eecf-4fc0-bf54-dc0dd7446067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549780442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1549780442
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1213168416
Short name T686
Test name
Test status
Simulation time 123490470 ps
CPU time 2.18 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:16 PM PDT 24
Peak memory 219576 kb
Host smart-cd1797e5-e596-49be-bb2e-9b6bfaa86d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213168416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1213168416
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2018171338
Short name T584
Test name
Test status
Simulation time 84137152 ps
CPU time 1.46 seconds
Started May 21 02:25:14 PM PDT 24
Finished May 21 02:25:16 PM PDT 24
Peak memory 218196 kb
Host smart-bebf6a67-6a2c-400b-842c-24c0f1282ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018171338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2018171338
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3291872308
Short name T738
Test name
Test status
Simulation time 45520690 ps
CPU time 1.98 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 219464 kb
Host smart-d79db1bc-036f-4e6c-ad2a-5a1310df7b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291872308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3291872308
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3623201639
Short name T504
Test name
Test status
Simulation time 106613031 ps
CPU time 1.22 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 216796 kb
Host smart-b45815cf-3ccc-43eb-a3e2-7abf6c78552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623201639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3623201639
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4143569396
Short name T544
Test name
Test status
Simulation time 79265727 ps
CPU time 1.08 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 216556 kb
Host smart-8654fb6b-038b-443e-a692-d504f15ca689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143569396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4143569396
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3161585456
Short name T309
Test name
Test status
Simulation time 29796379 ps
CPU time 1.34 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 219220 kb
Host smart-1699761b-a75c-4c2a-952d-f916607da448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161585456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3161585456
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2987731235
Short name T463
Test name
Test status
Simulation time 48834298 ps
CPU time 1.13 seconds
Started May 21 02:14:44 PM PDT 24
Finished May 21 02:14:49 PM PDT 24
Peak memory 215400 kb
Host smart-0fb1bfbb-0e6e-42bf-8c2d-8c88fda3eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987731235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2987731235
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2962247736
Short name T583
Test name
Test status
Simulation time 58584494 ps
CPU time 0.93 seconds
Started May 21 02:14:38 PM PDT 24
Finished May 21 02:14:45 PM PDT 24
Peak memory 214492 kb
Host smart-32c557ee-f563-419c-9059-126037b8d0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962247736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2962247736
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4240938875
Short name T830
Test name
Test status
Simulation time 26816201 ps
CPU time 0.82 seconds
Started May 21 02:14:38 PM PDT 24
Finished May 21 02:14:42 PM PDT 24
Peak memory 216032 kb
Host smart-5cef48b8-c2e8-41a4-be0e-058fa743f3ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240938875 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4240938875
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3828728157
Short name T759
Test name
Test status
Simulation time 98122764 ps
CPU time 1.11 seconds
Started May 21 02:14:41 PM PDT 24
Finished May 21 02:14:47 PM PDT 24
Peak memory 216500 kb
Host smart-63f5cfcd-b0bc-4c5c-bff0-7ce1fa8587db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828728157 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3828728157
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.580967009
Short name T610
Test name
Test status
Simulation time 18799196 ps
CPU time 1.12 seconds
Started May 21 02:14:42 PM PDT 24
Finished May 21 02:14:48 PM PDT 24
Peak memory 218140 kb
Host smart-348d3900-7e88-4dda-8e14-50f6ea120957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580967009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.580967009
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1211527015
Short name T416
Test name
Test status
Simulation time 163070720 ps
CPU time 1.1 seconds
Started May 21 02:14:34 PM PDT 24
Finished May 21 02:14:39 PM PDT 24
Peak memory 216772 kb
Host smart-46a5c104-b2c9-4888-8e5b-c9fe88d4ff6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211527015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1211527015
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1664008009
Short name T695
Test name
Test status
Simulation time 64045662 ps
CPU time 0.79 seconds
Started May 21 02:14:40 PM PDT 24
Finished May 21 02:14:46 PM PDT 24
Peak memory 214936 kb
Host smart-c74d8436-cd74-49c9-a7ea-afc8576ee3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664008009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1664008009
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1438248112
Short name T650
Test name
Test status
Simulation time 16011094 ps
CPU time 0.99 seconds
Started May 21 02:14:42 PM PDT 24
Finished May 21 02:14:47 PM PDT 24
Peak memory 215012 kb
Host smart-e9d472a0-54d5-4dd0-bfe5-6a8fedde1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438248112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1438248112
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3026225704
Short name T216
Test name
Test status
Simulation time 380755126 ps
CPU time 5.67 seconds
Started May 21 02:14:38 PM PDT 24
Finished May 21 02:14:47 PM PDT 24
Peak memory 216800 kb
Host smart-45199a4f-166e-4480-b272-584e5ff8ba7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026225704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3026225704
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3883492547
Short name T689
Test name
Test status
Simulation time 323181948684 ps
CPU time 615.85 seconds
Started May 21 02:14:42 PM PDT 24
Finished May 21 02:25:02 PM PDT 24
Peak memory 218484 kb
Host smart-3347d986-2c82-4d56-87de-d6ad7280e514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883492547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3883492547
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4057440323
Short name T673
Test name
Test status
Simulation time 34451193 ps
CPU time 1.4 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 217820 kb
Host smart-30007a9c-5dd6-45a3-80a6-54eb7ac3c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057440323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4057440323
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2185223496
Short name T404
Test name
Test status
Simulation time 68379535 ps
CPU time 1.62 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 218192 kb
Host smart-ffb881be-d64a-44f3-9065-f2414749c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185223496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2185223496
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2505696345
Short name T479
Test name
Test status
Simulation time 60660951 ps
CPU time 1.33 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 218044 kb
Host smart-02e618fb-85f0-46a7-aa4d-37ae2e4a11f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505696345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2505696345
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2953715411
Short name T728
Test name
Test status
Simulation time 92101104 ps
CPU time 1.44 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 219644 kb
Host smart-e517460e-070e-4ec6-a15a-cd200374595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953715411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2953715411
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3807662792
Short name T11
Test name
Test status
Simulation time 62281139 ps
CPU time 1.47 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 219472 kb
Host smart-4fdc21ce-9397-499d-ae66-0fbbf44a3c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807662792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3807662792
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.119929541
Short name T391
Test name
Test status
Simulation time 59798123 ps
CPU time 1.76 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:12 PM PDT 24
Peak memory 218316 kb
Host smart-a54021dd-164a-46a1-aa1a-b8ecee27454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119929541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.119929541
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2755811760
Short name T84
Test name
Test status
Simulation time 42933973 ps
CPU time 1.7 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 217880 kb
Host smart-3084cdfe-ea14-44c6-9960-cd2bd9816494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755811760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2755811760
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1031512830
Short name T642
Test name
Test status
Simulation time 67065244 ps
CPU time 2.54 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 219400 kb
Host smart-6f6522a4-28d1-42fc-99f3-74c19d12df48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031512830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1031512830
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.416370121
Short name T276
Test name
Test status
Simulation time 46289708 ps
CPU time 1.23 seconds
Started May 21 02:25:09 PM PDT 24
Finished May 21 02:25:11 PM PDT 24
Peak memory 218648 kb
Host smart-ed88c647-881e-4054-978b-700d5bbedb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416370121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.416370121
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3937099657
Short name T442
Test name
Test status
Simulation time 75527336 ps
CPU time 1.31 seconds
Started May 21 02:25:11 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 218156 kb
Host smart-4685e3ed-79b8-44ca-9e71-645e68b41727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937099657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3937099657
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.6146624
Short name T598
Test name
Test status
Simulation time 27745736 ps
CPU time 0.9 seconds
Started May 21 02:14:48 PM PDT 24
Finished May 21 02:14:53 PM PDT 24
Peak memory 206260 kb
Host smart-90dc97fe-358c-4de8-97e1-21ff4df8a06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6146624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.6146624
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.289032815
Short name T353
Test name
Test status
Simulation time 14125424 ps
CPU time 0.93 seconds
Started May 21 02:14:53 PM PDT 24
Finished May 21 02:14:59 PM PDT 24
Peak memory 215996 kb
Host smart-4e854d17-ef40-4b5c-9343-eee7655b5b65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289032815 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.289032815
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1635743375
Short name T372
Test name
Test status
Simulation time 44079855 ps
CPU time 1.21 seconds
Started May 21 02:14:56 PM PDT 24
Finished May 21 02:15:04 PM PDT 24
Peak memory 219192 kb
Host smart-0c98ca03-f22d-49e5-9344-fe15fe568bce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635743375 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1635743375
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2139182415
Short name T104
Test name
Test status
Simulation time 60537663 ps
CPU time 0.96 seconds
Started May 21 02:14:59 PM PDT 24
Finished May 21 02:15:08 PM PDT 24
Peak memory 219020 kb
Host smart-c556a270-8c30-4c00-b1c0-9925c2b87ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139182415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2139182415
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4253327261
Short name T450
Test name
Test status
Simulation time 98561431 ps
CPU time 1.21 seconds
Started May 21 02:14:46 PM PDT 24
Finished May 21 02:14:51 PM PDT 24
Peak memory 218924 kb
Host smart-1cc43077-4482-4afa-a55a-fb41de7c3716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253327261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4253327261
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3609270622
Short name T162
Test name
Test status
Simulation time 33360205 ps
CPU time 0.87 seconds
Started May 21 02:14:49 PM PDT 24
Finished May 21 02:14:54 PM PDT 24
Peak memory 215188 kb
Host smart-d25ee7e8-626f-4032-aac4-1503e938ae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609270622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3609270622
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2415916682
Short name T499
Test name
Test status
Simulation time 30197370 ps
CPU time 0.96 seconds
Started May 21 02:14:48 PM PDT 24
Finished May 21 02:14:53 PM PDT 24
Peak memory 206772 kb
Host smart-8796b66d-bc88-4e17-8fbf-358c16ad69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415916682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2415916682
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1059133622
Short name T694
Test name
Test status
Simulation time 144962345 ps
CPU time 1.33 seconds
Started May 21 02:14:52 PM PDT 24
Finished May 21 02:14:58 PM PDT 24
Peak memory 215100 kb
Host smart-edd8b65b-bd62-48ed-98bc-3ae615a2af61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059133622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1059133622
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1839553529
Short name T466
Test name
Test status
Simulation time 98703951856 ps
CPU time 636.84 seconds
Started May 21 02:14:40 PM PDT 24
Finished May 21 02:25:22 PM PDT 24
Peak memory 219120 kb
Host smart-0bbb8e65-bbee-453c-bbe4-bfa5b12fb674
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839553529 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1839553529
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3475853691
Short name T327
Test name
Test status
Simulation time 33496055 ps
CPU time 1.39 seconds
Started May 21 02:25:15 PM PDT 24
Finished May 21 02:25:17 PM PDT 24
Peak memory 218232 kb
Host smart-79c27976-2ca6-445b-8781-1870e95e9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475853691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3475853691
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.585305407
Short name T716
Test name
Test status
Simulation time 48566787 ps
CPU time 1.56 seconds
Started May 21 02:25:10 PM PDT 24
Finished May 21 02:25:13 PM PDT 24
Peak memory 215000 kb
Host smart-9a105cd6-af0e-49ec-b69e-219101b35c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585305407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.585305407
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1907287468
Short name T486
Test name
Test status
Simulation time 74825590 ps
CPU time 1.07 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:14 PM PDT 24
Peak memory 216620 kb
Host smart-371600d5-1d3a-4cf4-bf2c-2c97273f3752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907287468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1907287468
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3480388224
Short name T754
Test name
Test status
Simulation time 38243880 ps
CPU time 1.43 seconds
Started May 21 02:25:12 PM PDT 24
Finished May 21 02:25:15 PM PDT 24
Peak memory 217816 kb
Host smart-b3257f02-f4c6-4273-9cd9-a4359f38d342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480388224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3480388224
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3855288340
Short name T408
Test name
Test status
Simulation time 114376685 ps
CPU time 1.65 seconds
Started May 21 02:25:19 PM PDT 24
Finished May 21 02:25:21 PM PDT 24
Peak memory 218208 kb
Host smart-19377a97-8685-41e7-80e8-d7793f13cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855288340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3855288340
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1867013880
Short name T712
Test name
Test status
Simulation time 149856082 ps
CPU time 2.87 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:22 PM PDT 24
Peak memory 219256 kb
Host smart-82836184-029e-4b86-9f29-bfc46c8b6f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867013880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1867013880
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.392504191
Short name T283
Test name
Test status
Simulation time 68433885 ps
CPU time 1.43 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:19 PM PDT 24
Peak memory 218212 kb
Host smart-9a07b1cd-6960-490b-b2ed-4f02921f4464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392504191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.392504191
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1417300269
Short name T293
Test name
Test status
Simulation time 55692852 ps
CPU time 1.39 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 216576 kb
Host smart-ad242f9d-a156-45c3-ac25-bd94b8084bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417300269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1417300269
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1894982086
Short name T542
Test name
Test status
Simulation time 63758327 ps
CPU time 1.31 seconds
Started May 21 02:25:18 PM PDT 24
Finished May 21 02:25:20 PM PDT 24
Peak memory 218064 kb
Host smart-b5652f2f-b802-426c-ac5e-1d962139f4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894982086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1894982086
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3337914106
Short name T668
Test name
Test status
Simulation time 39550190 ps
CPU time 1.44 seconds
Started May 21 02:25:17 PM PDT 24
Finished May 21 02:25:19 PM PDT 24
Peak memory 219108 kb
Host smart-e9f59b10-8974-41c2-8dc7-c25b6ba0089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337914106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3337914106
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4021890146
Short name T796
Test name
Test status
Simulation time 150306944 ps
CPU time 1.27 seconds
Started May 21 02:12:56 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 215256 kb
Host smart-b20e6690-7d26-4c6d-bb43-ab44af5be961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021890146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4021890146
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2700029871
Short name T602
Test name
Test status
Simulation time 96029099 ps
CPU time 0.96 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 206136 kb
Host smart-cc023007-b6fe-4b6c-a889-496db5850876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700029871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2700029871
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.892354308
Short name T120
Test name
Test status
Simulation time 38372412 ps
CPU time 0.86 seconds
Started May 21 02:12:55 PM PDT 24
Finished May 21 02:12:59 PM PDT 24
Peak memory 215188 kb
Host smart-34702cfb-cb58-4e30-9272-59bac7db3192
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892354308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.892354308
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2707270241
Short name T329
Test name
Test status
Simulation time 23619484 ps
CPU time 1.14 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 217820 kb
Host smart-9be1adef-5698-4b7e-908c-b9161a88ceea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707270241 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2707270241
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.4224399750
Short name T617
Test name
Test status
Simulation time 26129845 ps
CPU time 1.07 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 223444 kb
Host smart-a5d57e62-6764-4a00-bb15-f681deb3dbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224399750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.4224399750
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1840088890
Short name T532
Test name
Test status
Simulation time 193204987 ps
CPU time 1.02 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 216760 kb
Host smart-f656f2db-cfd2-4765-b4bb-ef6887874b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840088890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1840088890
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.624084253
Short name T457
Test name
Test status
Simulation time 22559534 ps
CPU time 1.12 seconds
Started May 21 02:12:54 PM PDT 24
Finished May 21 02:12:58 PM PDT 24
Peak memory 215052 kb
Host smart-e94f91f7-f16a-4439-8d51-9c405a0b3001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624084253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.624084253
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1226167033
Short name T788
Test name
Test status
Simulation time 15229665 ps
CPU time 0.97 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 206792 kb
Host smart-82a04c7c-4229-408d-a783-c86e9988967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226167033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1226167033
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2261748311
Short name T64
Test name
Test status
Simulation time 4546002623 ps
CPU time 7.97 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:15 PM PDT 24
Peak memory 238672 kb
Host smart-0b560b57-f6a0-4a5c-8e4b-1f9a478d4d6b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261748311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2261748311
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2340207678
Short name T426
Test name
Test status
Simulation time 111393085 ps
CPU time 0.94 seconds
Started May 21 02:12:56 PM PDT 24
Finished May 21 02:13:00 PM PDT 24
Peak memory 214992 kb
Host smart-62e394ce-5218-4073-94ba-9cd0a3deacdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340207678 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2340207678
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3412784350
Short name T489
Test name
Test status
Simulation time 144564652 ps
CPU time 2.07 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:04 PM PDT 24
Peak memory 214956 kb
Host smart-b9277946-77b4-45ea-96c2-50611ca0b5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412784350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3412784350
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3685398741
Short name T429
Test name
Test status
Simulation time 253105653241 ps
CPU time 1130.03 seconds
Started May 21 02:12:57 PM PDT 24
Finished May 21 02:31:50 PM PDT 24
Peak memory 224080 kb
Host smart-0249cf85-8132-4618-bd60-014257004574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685398741 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3685398741
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1274893161
Short name T607
Test name
Test status
Simulation time 317022684 ps
CPU time 1.26 seconds
Started May 21 02:14:55 PM PDT 24
Finished May 21 02:15:03 PM PDT 24
Peak memory 215400 kb
Host smart-5b2cf76f-83b6-4433-9b10-b74e6168ba8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274893161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1274893161
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1766305548
Short name T438
Test name
Test status
Simulation time 12061794 ps
CPU time 0.93 seconds
Started May 21 02:14:57 PM PDT 24
Finished May 21 02:15:06 PM PDT 24
Peak memory 206536 kb
Host smart-8f6527c6-04f8-4fbc-b969-41e7ee9939d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766305548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1766305548
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.1359088828
Short name T559
Test name
Test status
Simulation time 20188401 ps
CPU time 0.98 seconds
Started May 21 02:14:57 PM PDT 24
Finished May 21 02:15:06 PM PDT 24
Peak memory 217620 kb
Host smart-29368e9b-1b1f-41c0-bf16-7a65cec30bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359088828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1359088828
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3648143707
Short name T613
Test name
Test status
Simulation time 55459671 ps
CPU time 1.21 seconds
Started May 21 02:14:55 PM PDT 24
Finished May 21 02:15:04 PM PDT 24
Peak memory 217680 kb
Host smart-b2f6b2bb-952d-4b65-944f-fd51dae93256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648143707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3648143707
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.4102706391
Short name T420
Test name
Test status
Simulation time 28468706 ps
CPU time 1.08 seconds
Started May 21 02:15:00 PM PDT 24
Finished May 21 02:15:10 PM PDT 24
Peak memory 223580 kb
Host smart-6a9607be-60db-4df4-8660-97f1f00d0ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102706391 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.4102706391
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3129373634
Short name T325
Test name
Test status
Simulation time 25367859 ps
CPU time 0.94 seconds
Started May 21 02:15:04 PM PDT 24
Finished May 21 02:15:14 PM PDT 24
Peak memory 206752 kb
Host smart-8e01628b-1537-4ad1-a6ab-d5b6cd83e36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129373634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3129373634
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3437760738
Short name T400
Test name
Test status
Simulation time 823199025 ps
CPU time 4.05 seconds
Started May 21 02:14:55 PM PDT 24
Finished May 21 02:15:06 PM PDT 24
Peak memory 215064 kb
Host smart-7098200c-8e61-4d5e-a191-ac435da0222e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437760738 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3437760738
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2493830380
Short name T699
Test name
Test status
Simulation time 85139562817 ps
CPU time 1854.74 seconds
Started May 21 02:14:54 PM PDT 24
Finished May 21 02:45:56 PM PDT 24
Peak memory 225920 kb
Host smart-a2c4fab5-3407-4685-bdf7-8b05ca5a02db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493830380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2493830380
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1201749851
Short name T545
Test name
Test status
Simulation time 86920705 ps
CPU time 1.19 seconds
Started May 21 02:15:01 PM PDT 24
Finished May 21 02:15:11 PM PDT 24
Peak memory 215396 kb
Host smart-ebc3f3ff-a32f-484a-8e12-84ea2991237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201749851 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1201749851
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4220185794
Short name T603
Test name
Test status
Simulation time 16563147 ps
CPU time 0.92 seconds
Started May 21 02:14:56 PM PDT 24
Finished May 21 02:15:04 PM PDT 24
Peak memory 206280 kb
Host smart-d811679c-0fa8-43c3-bedf-727cf75009fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220185794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4220185794
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.348851487
Short name T806
Test name
Test status
Simulation time 29619278 ps
CPU time 0.84 seconds
Started May 21 02:15:00 PM PDT 24
Finished May 21 02:15:09 PM PDT 24
Peak memory 216056 kb
Host smart-9934b571-3011-4eb9-8298-6c0a6bac37e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348851487 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.348851487
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3632425303
Short name T660
Test name
Test status
Simulation time 29077414 ps
CPU time 0.94 seconds
Started May 21 02:15:02 PM PDT 24
Finished May 21 02:15:12 PM PDT 24
Peak memory 215324 kb
Host smart-1e9b9b7a-d3a0-4af0-9c58-d6fb3228fd4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632425303 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3632425303
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.573266283
Short name T123
Test name
Test status
Simulation time 64835959 ps
CPU time 0.95 seconds
Started May 21 02:14:54 PM PDT 24
Finished May 21 02:15:02 PM PDT 24
Peak memory 217932 kb
Host smart-e6d273e2-e9c6-4596-97bf-a48e6acf381d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573266283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.573266283
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4123286479
Short name T641
Test name
Test status
Simulation time 35265236 ps
CPU time 1.48 seconds
Started May 21 02:14:56 PM PDT 24
Finished May 21 02:15:06 PM PDT 24
Peak memory 217984 kb
Host smart-000ca0e9-6325-4617-8f72-63b02b09f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123286479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4123286479
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3514568050
Short name T732
Test name
Test status
Simulation time 24078245 ps
CPU time 1.1 seconds
Started May 21 02:15:03 PM PDT 24
Finished May 21 02:15:14 PM PDT 24
Peak memory 223496 kb
Host smart-6466b86b-7da0-4908-9123-af8a907e9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514568050 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3514568050
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.789387924
Short name T69
Test name
Test status
Simulation time 40116969 ps
CPU time 0.91 seconds
Started May 21 02:15:01 PM PDT 24
Finished May 21 02:15:11 PM PDT 24
Peak memory 215004 kb
Host smart-8b346ad0-837f-4120-afef-2924e575021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789387924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.789387924
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.166578959
Short name T556
Test name
Test status
Simulation time 199224521 ps
CPU time 4.07 seconds
Started May 21 02:15:02 PM PDT 24
Finished May 21 02:15:15 PM PDT 24
Peak memory 218928 kb
Host smart-966ce09c-325f-4cab-a3ee-84b76c9a2981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166578959 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.166578959
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1272438379
Short name T212
Test name
Test status
Simulation time 55346308800 ps
CPU time 300.97 seconds
Started May 21 02:15:06 PM PDT 24
Finished May 21 02:20:16 PM PDT 24
Peak memory 217768 kb
Host smart-d43024cb-f73a-4e87-b1b1-86505b9a37f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272438379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1272438379
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2032771748
Short name T204
Test name
Test status
Simulation time 30355918 ps
CPU time 1.33 seconds
Started May 21 02:15:04 PM PDT 24
Finished May 21 02:15:14 PM PDT 24
Peak memory 215408 kb
Host smart-65cc525d-38b4-4de5-82b7-5b629d1a715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032771748 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2032771748
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2513310025
Short name T464
Test name
Test status
Simulation time 31308687 ps
CPU time 1.14 seconds
Started May 21 02:15:03 PM PDT 24
Finished May 21 02:15:13 PM PDT 24
Peak memory 206356 kb
Host smart-9208826c-de47-4fa5-a9c8-4c2075ff2b12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513310025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2513310025
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1182317722
Short name T189
Test name
Test status
Simulation time 24344688 ps
CPU time 0.85 seconds
Started May 21 02:15:07 PM PDT 24
Finished May 21 02:15:17 PM PDT 24
Peak memory 216016 kb
Host smart-9d3a8461-de00-4e5f-a76d-aceb38f009c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182317722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1182317722
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1233892838
Short name T692
Test name
Test status
Simulation time 30606683 ps
CPU time 1.18 seconds
Started May 21 02:15:03 PM PDT 24
Finished May 21 02:15:14 PM PDT 24
Peak memory 217868 kb
Host smart-5d208731-198b-4e6b-b87c-74082588f89f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233892838 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1233892838
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.484229298
Short name T805
Test name
Test status
Simulation time 86767400 ps
CPU time 0.92 seconds
Started May 21 02:15:03 PM PDT 24
Finished May 21 02:15:14 PM PDT 24
Peak memory 217620 kb
Host smart-47d89f43-c055-4262-8249-bc9d7bd9c93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484229298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.484229298
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_intr.3531287968
Short name T535
Test name
Test status
Simulation time 25631079 ps
CPU time 1.03 seconds
Started May 21 02:15:06 PM PDT 24
Finished May 21 02:15:16 PM PDT 24
Peak memory 223608 kb
Host smart-0e8b4b20-7141-4332-9747-e7aec7d3174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531287968 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3531287968
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1132119203
Short name T379
Test name
Test status
Simulation time 14189545 ps
CPU time 0.99 seconds
Started May 21 02:14:59 PM PDT 24
Finished May 21 02:15:09 PM PDT 24
Peak memory 206780 kb
Host smart-4e91fc11-e433-415a-9059-287063e3b18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132119203 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1132119203
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2723784720
Short name T485
Test name
Test status
Simulation time 283928550 ps
CPU time 1.96 seconds
Started May 21 02:15:04 PM PDT 24
Finished May 21 02:15:15 PM PDT 24
Peak memory 215032 kb
Host smart-46542ddf-d45c-40ca-a171-169dcb19f315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723784720 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2723784720
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2915327362
Short name T71
Test name
Test status
Simulation time 15882263530 ps
CPU time 382.32 seconds
Started May 21 02:15:02 PM PDT 24
Finished May 21 02:21:33 PM PDT 24
Peak memory 216180 kb
Host smart-47e6b447-0372-4df8-9147-dd1e9476dd45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915327362 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2915327362
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.452716597
Short name T266
Test name
Test status
Simulation time 85756743 ps
CPU time 1.23 seconds
Started May 21 02:15:09 PM PDT 24
Finished May 21 02:15:18 PM PDT 24
Peak memory 215364 kb
Host smart-0768f54b-b376-4b51-9891-0595e78b8dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452716597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.452716597
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.160405874
Short name T335
Test name
Test status
Simulation time 15003266 ps
CPU time 0.92 seconds
Started May 21 02:15:11 PM PDT 24
Finished May 21 02:15:19 PM PDT 24
Peak memory 214844 kb
Host smart-7bf767b8-4f7e-4d06-9426-3265920a8cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160405874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.160405874
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.87673228
Short name T142
Test name
Test status
Simulation time 13741401 ps
CPU time 0.95 seconds
Started May 21 02:15:13 PM PDT 24
Finished May 21 02:15:20 PM PDT 24
Peak memory 216412 kb
Host smart-781fe9c0-e9f5-41be-9a34-9e6d127381cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87673228 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.87673228
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.313495085
Short name T97
Test name
Test status
Simulation time 195132910 ps
CPU time 1.19 seconds
Started May 21 02:15:14 PM PDT 24
Finished May 21 02:15:21 PM PDT 24
Peak memory 216564 kb
Host smart-4fd36a81-b771-4e82-a2ae-78032c4970a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313495085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.313495085
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3878498304
Short name T110
Test name
Test status
Simulation time 24516509 ps
CPU time 1.15 seconds
Started May 21 02:15:06 PM PDT 24
Finished May 21 02:15:17 PM PDT 24
Peak memory 218036 kb
Host smart-2798d0ce-7252-4d8b-8949-c06895fac42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878498304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3878498304
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.135818184
Short name T601
Test name
Test status
Simulation time 27624568 ps
CPU time 1.17 seconds
Started May 21 02:15:08 PM PDT 24
Finished May 21 02:15:18 PM PDT 24
Peak memory 216744 kb
Host smart-ee2cfaa8-529d-45e8-b191-f5720731fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135818184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.135818184
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.186352025
Short name T156
Test name
Test status
Simulation time 36347755 ps
CPU time 0.85 seconds
Started May 21 02:15:06 PM PDT 24
Finished May 21 02:15:16 PM PDT 24
Peak memory 215196 kb
Host smart-314e7396-8121-42d3-8d3f-5d94826437eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186352025 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.186352025
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1308397162
Short name T445
Test name
Test status
Simulation time 14304992 ps
CPU time 0.94 seconds
Started May 21 02:15:02 PM PDT 24
Finished May 21 02:15:11 PM PDT 24
Peak memory 215032 kb
Host smart-846bdb5e-1f2a-4418-8b1f-deec857c7e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308397162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1308397162
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3949446018
Short name T586
Test name
Test status
Simulation time 443660933 ps
CPU time 2.79 seconds
Started May 21 02:15:09 PM PDT 24
Finished May 21 02:15:20 PM PDT 24
Peak memory 216596 kb
Host smart-b3818b84-2eb5-4b59-b576-6e5715f1a030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949446018 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3949446018
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2939977783
Short name T691
Test name
Test status
Simulation time 17530334955 ps
CPU time 424.24 seconds
Started May 21 02:15:11 PM PDT 24
Finished May 21 02:22:22 PM PDT 24
Peak memory 217600 kb
Host smart-e31fdf88-594b-45e0-b5ce-6f6b70f4a379
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939977783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2939977783
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3869359586
Short name T200
Test name
Test status
Simulation time 96513695 ps
CPU time 1.33 seconds
Started May 21 02:15:23 PM PDT 24
Finished May 21 02:15:27 PM PDT 24
Peak memory 215300 kb
Host smart-6d2cc37c-0c69-4e1a-9dd1-ce7db710654a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869359586 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3869359586
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3725042301
Short name T753
Test name
Test status
Simulation time 40623493 ps
CPU time 0.82 seconds
Started May 21 02:15:19 PM PDT 24
Finished May 21 02:15:24 PM PDT 24
Peak memory 214368 kb
Host smart-3c277619-977d-48a1-a5fb-e4972bd10ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725042301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3725042301
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2576413753
Short name T138
Test name
Test status
Simulation time 105782907 ps
CPU time 0.84 seconds
Started May 21 02:15:17 PM PDT 24
Finished May 21 02:15:23 PM PDT 24
Peak memory 216168 kb
Host smart-ed0a4a42-6482-42c9-80df-b15c84ac344f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576413753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2576413753
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.854876175
Short name T195
Test name
Test status
Simulation time 36733265 ps
CPU time 1.21 seconds
Started May 21 02:15:18 PM PDT 24
Finished May 21 02:15:24 PM PDT 24
Peak memory 216716 kb
Host smart-e7db2fed-7519-416a-b7df-291fc69ea6a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854876175 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.854876175
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2842507759
Short name T530
Test name
Test status
Simulation time 30196417 ps
CPU time 1.22 seconds
Started May 21 02:15:21 PM PDT 24
Finished May 21 02:15:26 PM PDT 24
Peak memory 219032 kb
Host smart-abc6111a-c19d-4540-8a3d-b5f2a7b88193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842507759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2842507759
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.2029158703
Short name T596
Test name
Test status
Simulation time 108415294 ps
CPU time 1.65 seconds
Started May 21 02:15:10 PM PDT 24
Finished May 21 02:15:19 PM PDT 24
Peak memory 219148 kb
Host smart-bad61d86-229c-479f-ad92-254717ff4413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029158703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2029158703
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1200440114
Short name T152
Test name
Test status
Simulation time 28290151 ps
CPU time 0.9 seconds
Started May 21 02:15:11 PM PDT 24
Finished May 21 02:15:19 PM PDT 24
Peak memory 215036 kb
Host smart-f2c57473-487b-40c9-b867-997732020c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200440114 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1200440114
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.492156869
Short name T776
Test name
Test status
Simulation time 36856663 ps
CPU time 0.91 seconds
Started May 21 02:15:17 PM PDT 24
Finished May 21 02:15:23 PM PDT 24
Peak memory 206756 kb
Host smart-72949b38-381e-473d-8dba-21fecfc2843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492156869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.492156869
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3635737597
Short name T218
Test name
Test status
Simulation time 175369802 ps
CPU time 2.3 seconds
Started May 21 02:15:10 PM PDT 24
Finished May 21 02:15:20 PM PDT 24
Peak memory 216580 kb
Host smart-ed6dfc78-49d6-4e7b-904b-28ec423ccd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635737597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3635737597
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1356859914
Short name T576
Test name
Test status
Simulation time 29849097126 ps
CPU time 376.23 seconds
Started May 21 02:15:16 PM PDT 24
Finished May 21 02:21:38 PM PDT 24
Peak memory 223600 kb
Host smart-f370ed75-c074-401f-93b1-0fc69b278929
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356859914 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1356859914
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2971279343
Short name T198
Test name
Test status
Simulation time 81498636 ps
CPU time 1.18 seconds
Started May 21 02:15:23 PM PDT 24
Finished May 21 02:15:27 PM PDT 24
Peak memory 215368 kb
Host smart-e46a64f4-7555-4d50-91b6-f53b682bc1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971279343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2971279343
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3830553182
Short name T741
Test name
Test status
Simulation time 50640501 ps
CPU time 0.91 seconds
Started May 21 02:15:22 PM PDT 24
Finished May 21 02:15:26 PM PDT 24
Peak memory 206288 kb
Host smart-bdb4c912-070a-4835-944d-496e00e0a15d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830553182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3830553182
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1616663797
Short name T180
Test name
Test status
Simulation time 13372668 ps
CPU time 0.98 seconds
Started May 21 02:15:24 PM PDT 24
Finished May 21 02:15:29 PM PDT 24
Peak memory 216144 kb
Host smart-a244616d-2348-4a76-a221-a5e3993bb012
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616663797 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1616663797
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1531860335
Short name T713
Test name
Test status
Simulation time 35369761 ps
CPU time 1.29 seconds
Started May 21 02:15:24 PM PDT 24
Finished May 21 02:15:29 PM PDT 24
Peak memory 216516 kb
Host smart-c6a8fef8-fb19-461c-aa22-e1de25df3368
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531860335 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1531860335
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4073397689
Short name T6
Test name
Test status
Simulation time 45342509 ps
CPU time 1.13 seconds
Started May 21 02:15:18 PM PDT 24
Finished May 21 02:15:24 PM PDT 24
Peak memory 229060 kb
Host smart-c8be3128-c8c3-4210-bbe9-041b97d4aa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073397689 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4073397689
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3445991705
Short name T454
Test name
Test status
Simulation time 109067173 ps
CPU time 1.3 seconds
Started May 21 02:15:18 PM PDT 24
Finished May 21 02:15:24 PM PDT 24
Peak memory 217972 kb
Host smart-106edc95-0802-48e2-acfe-53bb31a9a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445991705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3445991705
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1340957039
Short name T714
Test name
Test status
Simulation time 22892626 ps
CPU time 1.21 seconds
Started May 21 02:15:17 PM PDT 24
Finished May 21 02:15:23 PM PDT 24
Peak memory 223580 kb
Host smart-cc775a53-5ddd-43b0-bcfe-033f20a91bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340957039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1340957039
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2614876106
Short name T80
Test name
Test status
Simulation time 74817011 ps
CPU time 0.92 seconds
Started May 21 02:15:16 PM PDT 24
Finished May 21 02:15:22 PM PDT 24
Peak memory 214996 kb
Host smart-49074833-50bd-42a8-a5dc-fc2407fee4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614876106 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2614876106
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.160018281
Short name T336
Test name
Test status
Simulation time 220811853 ps
CPU time 1.8 seconds
Started May 21 02:15:19 PM PDT 24
Finished May 21 02:15:25 PM PDT 24
Peak memory 206848 kb
Host smart-89e24261-a08c-4fc2-9c68-2468b25b45b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160018281 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.160018281
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1061388932
Short name T649
Test name
Test status
Simulation time 169318317158 ps
CPU time 880.41 seconds
Started May 21 02:15:18 PM PDT 24
Finished May 21 02:30:04 PM PDT 24
Peak memory 223392 kb
Host smart-ba5bd4aa-f1d4-46df-a189-c8f84e02bcc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061388932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1061388932
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.576992094
Short name T303
Test name
Test status
Simulation time 30555297 ps
CPU time 1.29 seconds
Started May 21 02:15:29 PM PDT 24
Finished May 21 02:15:32 PM PDT 24
Peak memory 215352 kb
Host smart-ad7d9fd8-c3fa-4498-bff3-57e1e674f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576992094 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.576992094
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2909571395
Short name T321
Test name
Test status
Simulation time 19610567 ps
CPU time 0.89 seconds
Started May 21 02:15:35 PM PDT 24
Finished May 21 02:15:37 PM PDT 24
Peak memory 206040 kb
Host smart-009ad9ed-b2b8-4be8-adfa-e026ac6417d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909571395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2909571395
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3609118784
Short name T663
Test name
Test status
Simulation time 25954892 ps
CPU time 0.82 seconds
Started May 21 02:15:29 PM PDT 24
Finished May 21 02:15:32 PM PDT 24
Peak memory 215680 kb
Host smart-dcc65fea-7dae-4e89-82d9-76b96c22b6f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609118784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3609118784
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.2602857345
Short name T630
Test name
Test status
Simulation time 35234168 ps
CPU time 1.1 seconds
Started May 21 02:15:33 PM PDT 24
Finished May 21 02:15:36 PM PDT 24
Peak memory 216540 kb
Host smart-4eb67d32-96e0-43c3-adf6-7c270b33d684
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602857345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.2602857345
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3726662045
Short name T413
Test name
Test status
Simulation time 28785077 ps
CPU time 0.82 seconds
Started May 21 02:15:29 PM PDT 24
Finished May 21 02:15:32 PM PDT 24
Peak memory 217888 kb
Host smart-c2f36789-f775-4e64-9cd1-15fab66ca58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726662045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3726662045
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2937454497
Short name T72
Test name
Test status
Simulation time 45375849 ps
CPU time 1.62 seconds
Started May 21 02:15:25 PM PDT 24
Finished May 21 02:15:30 PM PDT 24
Peak memory 217932 kb
Host smart-3642e8fa-8aa0-4785-898e-e3c9f6e8104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937454497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2937454497
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3980910297
Short name T634
Test name
Test status
Simulation time 31748371 ps
CPU time 1.1 seconds
Started May 21 02:15:29 PM PDT 24
Finished May 21 02:15:32 PM PDT 24
Peak memory 223576 kb
Host smart-0bf84119-25b9-49c5-9053-a9232da54e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980910297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3980910297
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1555436859
Short name T432
Test name
Test status
Simulation time 44323552 ps
CPU time 0.94 seconds
Started May 21 02:15:25 PM PDT 24
Finished May 21 02:15:29 PM PDT 24
Peak memory 214924 kb
Host smart-ccdee063-6c5c-4021-bbe1-1adc217933d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555436859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1555436859
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.875299716
Short name T724
Test name
Test status
Simulation time 440959059 ps
CPU time 4.41 seconds
Started May 21 02:15:28 PM PDT 24
Finished May 21 02:15:35 PM PDT 24
Peak memory 216456 kb
Host smart-ddb39ae7-f803-43a7-8f94-37ec10e8bb3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875299716 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.875299716
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1529851260
Short name T782
Test name
Test status
Simulation time 42895144276 ps
CPU time 1099.11 seconds
Started May 21 02:15:43 PM PDT 24
Finished May 21 02:34:03 PM PDT 24
Peak memory 219856 kb
Host smart-5a7512a1-d6c1-4975-b4ad-f0ff13dd7a9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529851260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1529851260
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3638219099
Short name T146
Test name
Test status
Simulation time 25496223 ps
CPU time 1.23 seconds
Started May 21 02:15:43 PM PDT 24
Finished May 21 02:15:45 PM PDT 24
Peak memory 215384 kb
Host smart-ddce96d4-e94b-4515-8cdd-404b9efae0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638219099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3638219099
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3502733460
Short name T478
Test name
Test status
Simulation time 45384891 ps
CPU time 0.88 seconds
Started May 21 02:15:44 PM PDT 24
Finished May 21 02:15:45 PM PDT 24
Peak memory 206248 kb
Host smart-6522a3d4-553d-4ff1-937b-aa5809e1992f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502733460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3502733460
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2734070465
Short name T177
Test name
Test status
Simulation time 15368218 ps
CPU time 0.9 seconds
Started May 21 02:15:40 PM PDT 24
Finished May 21 02:15:42 PM PDT 24
Peak memory 215932 kb
Host smart-2e116bb8-bec0-4e0b-a290-1bc23092f593
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734070465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2734070465
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2327415986
Short name T818
Test name
Test status
Simulation time 29532822 ps
CPU time 1.07 seconds
Started May 21 02:15:47 PM PDT 24
Finished May 21 02:15:49 PM PDT 24
Peak memory 217752 kb
Host smart-2bc419bc-a283-4c0c-85b4-d170e7b655a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327415986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2327415986
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.948871524
Short name T190
Test name
Test status
Simulation time 49240515 ps
CPU time 1.03 seconds
Started May 21 02:15:54 PM PDT 24
Finished May 21 02:15:57 PM PDT 24
Peak memory 220284 kb
Host smart-74e88695-adcd-49e0-8f53-04328beb1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948871524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.948871524
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2427164915
Short name T67
Test name
Test status
Simulation time 212859421 ps
CPU time 3.71 seconds
Started May 21 02:15:34 PM PDT 24
Finished May 21 02:15:39 PM PDT 24
Peak memory 219600 kb
Host smart-fd6550a2-6414-4757-b0ee-ad48d45f8d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427164915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2427164915
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.8378055
Short name T654
Test name
Test status
Simulation time 35180242 ps
CPU time 0.91 seconds
Started May 21 02:15:39 PM PDT 24
Finished May 21 02:15:40 PM PDT 24
Peak memory 215340 kb
Host smart-b930df53-52db-4bea-a2c8-ea54c6566df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8378055 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.8378055
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2424318300
Short name T380
Test name
Test status
Simulation time 22753287 ps
CPU time 0.88 seconds
Started May 21 02:15:33 PM PDT 24
Finished May 21 02:15:36 PM PDT 24
Peak memory 214976 kb
Host smart-fcd48681-5519-424d-a7ea-ffeeb39c89f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424318300 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2424318300
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.753338804
Short name T527
Test name
Test status
Simulation time 532379622 ps
CPU time 4.97 seconds
Started May 21 02:15:33 PM PDT 24
Finished May 21 02:15:40 PM PDT 24
Peak memory 216832 kb
Host smart-3a35f5ee-11be-44c2-8443-96c2dee14aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753338804 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.753338804
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1941034520
Short name T801
Test name
Test status
Simulation time 295299707465 ps
CPU time 516.1 seconds
Started May 21 02:15:36 PM PDT 24
Finished May 21 02:24:14 PM PDT 24
Peak memory 218724 kb
Host smart-e7c0ba67-189a-4a21-acde-dbae8e1749e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941034520 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1941034520
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1936095780
Short name T124
Test name
Test status
Simulation time 41348879 ps
CPU time 1.12 seconds
Started May 21 02:15:54 PM PDT 24
Finished May 21 02:15:58 PM PDT 24
Peak memory 215340 kb
Host smart-289246d2-e92b-4145-872a-f9c7f794492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936095780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1936095780
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2138769783
Short name T551
Test name
Test status
Simulation time 22973128 ps
CPU time 1.05 seconds
Started May 21 02:15:57 PM PDT 24
Finished May 21 02:16:00 PM PDT 24
Peak memory 206348 kb
Host smart-61bbe993-8a3b-42fd-a5e1-765553575fc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138769783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2138769783
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1272164505
Short name T191
Test name
Test status
Simulation time 17248867 ps
CPU time 0.88 seconds
Started May 21 02:15:56 PM PDT 24
Finished May 21 02:15:59 PM PDT 24
Peak memory 216012 kb
Host smart-1a6f0918-28bf-46fc-bff9-ce2ceea55b45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272164505 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1272164505
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.559050245
Short name T643
Test name
Test status
Simulation time 75100369 ps
CPU time 1.1 seconds
Started May 21 02:15:55 PM PDT 24
Finished May 21 02:15:59 PM PDT 24
Peak memory 215320 kb
Host smart-a37284cf-95c9-4f78-abc1-9dadef5dc13e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559050245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.559050245
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_genbits.3768931236
Short name T793
Test name
Test status
Simulation time 203504329 ps
CPU time 1.78 seconds
Started May 21 02:15:53 PM PDT 24
Finished May 21 02:15:55 PM PDT 24
Peak memory 218124 kb
Host smart-30679e0d-cb6f-4878-bab0-20d69a37400b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768931236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3768931236
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.375611007
Short name T342
Test name
Test status
Simulation time 40067300 ps
CPU time 0.92 seconds
Started May 21 02:15:55 PM PDT 24
Finished May 21 02:15:58 PM PDT 24
Peak memory 215060 kb
Host smart-0753aab3-3bd0-4231-ac4d-7d5aeb045c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375611007 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.375611007
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1786891963
Short name T163
Test name
Test status
Simulation time 21946063 ps
CPU time 0.9 seconds
Started May 21 02:15:47 PM PDT 24
Finished May 21 02:15:49 PM PDT 24
Peak memory 214984 kb
Host smart-79816038-2ff6-4e1f-8895-4bf32dd78e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786891963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1786891963
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3017997597
Short name T720
Test name
Test status
Simulation time 347613951 ps
CPU time 3.75 seconds
Started May 21 02:15:56 PM PDT 24
Finished May 21 02:16:02 PM PDT 24
Peak memory 216564 kb
Host smart-26260986-c7b1-41f4-8757-0ebc36fbc938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017997597 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3017997597
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.834499485
Short name T76
Test name
Test status
Simulation time 45679811187 ps
CPU time 1012.62 seconds
Started May 21 02:15:52 PM PDT 24
Finished May 21 02:32:45 PM PDT 24
Peak memory 223408 kb
Host smart-a100ea2f-21d4-48bc-a69a-b77992024795
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834499485 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.834499485
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert_test.1851872660
Short name T473
Test name
Test status
Simulation time 30686126 ps
CPU time 0.96 seconds
Started May 21 02:16:06 PM PDT 24
Finished May 21 02:16:10 PM PDT 24
Peak memory 214560 kb
Host smart-9fc42eec-c087-422c-811e-3986ec2447e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851872660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1851872660
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2233605618
Short name T384
Test name
Test status
Simulation time 97832375 ps
CPU time 0.89 seconds
Started May 21 02:16:06 PM PDT 24
Finished May 21 02:16:11 PM PDT 24
Peak memory 215696 kb
Host smart-9b322052-1d39-4f65-9095-a9742cccef8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233605618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2233605618
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2243619827
Short name T386
Test name
Test status
Simulation time 199614194 ps
CPU time 1.34 seconds
Started May 21 02:16:07 PM PDT 24
Finished May 21 02:16:14 PM PDT 24
Peak memory 216784 kb
Host smart-abeca171-2812-40c5-b797-253ccb0a69cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243619827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2243619827
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3955144493
Short name T92
Test name
Test status
Simulation time 24530914 ps
CPU time 0.98 seconds
Started May 21 02:16:05 PM PDT 24
Finished May 21 02:16:10 PM PDT 24
Peak memory 219328 kb
Host smart-d3fd2e90-ec3b-4d6a-8729-65a300de52db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955144493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3955144493
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.626966661
Short name T706
Test name
Test status
Simulation time 91190103 ps
CPU time 1.12 seconds
Started May 21 02:16:04 PM PDT 24
Finished May 21 02:16:07 PM PDT 24
Peak memory 217880 kb
Host smart-14d11e62-6d31-4f83-82f4-d24550d1f585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626966661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.626966661
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3678273761
Short name T488
Test name
Test status
Simulation time 22807338 ps
CPU time 1.08 seconds
Started May 21 02:16:06 PM PDT 24
Finished May 21 02:16:11 PM PDT 24
Peak memory 223564 kb
Host smart-3ff26259-5645-4e74-83fa-cdd285e74451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678273761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3678273761
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1731929686
Short name T487
Test name
Test status
Simulation time 41559600 ps
CPU time 0.86 seconds
Started May 21 02:15:54 PM PDT 24
Finished May 21 02:15:56 PM PDT 24
Peak memory 214992 kb
Host smart-8cace0e7-ae67-4c75-b1bf-93877af534ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731929686 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1731929686
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2253513556
Short name T448
Test name
Test status
Simulation time 193396791 ps
CPU time 2.37 seconds
Started May 21 02:16:06 PM PDT 24
Finished May 21 02:16:13 PM PDT 24
Peak memory 216852 kb
Host smart-71f67b2e-7e81-4e37-a98a-4a02e72ce528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253513556 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2253513556
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3367200195
Short name T214
Test name
Test status
Simulation time 41393618563 ps
CPU time 745.14 seconds
Started May 21 02:16:07 PM PDT 24
Finished May 21 02:28:37 PM PDT 24
Peak memory 218060 kb
Host smart-490f2e75-285b-484e-ad11-e224c10f26d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367200195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3367200195
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.477125580
Short name T779
Test name
Test status
Simulation time 68437703 ps
CPU time 1.11 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 215408 kb
Host smart-a8a48c08-b885-4049-8c02-4c3e40c14ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477125580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.477125580
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.833819580
Short name T371
Test name
Test status
Simulation time 52659159 ps
CPU time 0.92 seconds
Started May 21 02:13:09 PM PDT 24
Finished May 21 02:13:15 PM PDT 24
Peak memory 214488 kb
Host smart-707d6126-8df9-418a-819a-542d302577d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833819580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.833819580
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2331529175
Short name T221
Test name
Test status
Simulation time 17855246 ps
CPU time 0.89 seconds
Started May 21 02:12:59 PM PDT 24
Finished May 21 02:13:03 PM PDT 24
Peak memory 216168 kb
Host smart-518bbfc3-fc55-44ba-90b8-0f4b74d41de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331529175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2331529175
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3187873824
Short name T108
Test name
Test status
Simulation time 27562600 ps
CPU time 1.13 seconds
Started May 21 02:13:03 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 216700 kb
Host smart-dfb3ea7e-bfef-47bc-90b8-eafd3eb893ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187873824 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3187873824
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3401789029
Short name T96
Test name
Test status
Simulation time 40753962 ps
CPU time 1.35 seconds
Started May 21 02:13:02 PM PDT 24
Finished May 21 02:13:07 PM PDT 24
Peak memory 228952 kb
Host smart-ec299abf-4a46-4bde-83b8-5df12a2261b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401789029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3401789029
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2035844267
Short name T22
Test name
Test status
Simulation time 65956135 ps
CPU time 1.34 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:05 PM PDT 24
Peak memory 217644 kb
Host smart-8dca30df-82dc-4f38-a60b-a2d5a157b21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035844267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2035844267
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2226618056
Short name T539
Test name
Test status
Simulation time 20937431 ps
CPU time 1.08 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:12 PM PDT 24
Peak memory 215080 kb
Host smart-c747e463-89c5-4474-be29-0a3f895ce2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226618056 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2226618056
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1063967126
Short name T300
Test name
Test status
Simulation time 25596660 ps
CPU time 0.92 seconds
Started May 21 02:13:04 PM PDT 24
Finished May 21 02:13:09 PM PDT 24
Peak memory 206756 kb
Host smart-1bb0ee8c-ac4b-4a9c-9d5b-b069f9d5ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063967126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1063967126
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2392785576
Short name T17
Test name
Test status
Simulation time 668360777 ps
CPU time 4.11 seconds
Started May 21 02:13:05 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 236228 kb
Host smart-48763bdf-ef52-48c9-8730-88e994ac0dbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392785576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2392785576
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3802809261
Short name T490
Test name
Test status
Simulation time 49742491 ps
CPU time 0.93 seconds
Started May 21 02:13:01 PM PDT 24
Finished May 21 02:13:06 PM PDT 24
Peak memory 214888 kb
Host smart-85be66cf-5e47-42cd-947d-18524460a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802809261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3802809261
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1234061260
Short name T644
Test name
Test status
Simulation time 331557344 ps
CPU time 2.28 seconds
Started May 21 02:13:02 PM PDT 24
Finished May 21 02:13:08 PM PDT 24
Peak memory 216512 kb
Host smart-9851097a-cb51-489e-9cdf-4baf7dc7d759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234061260 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1234061260
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3916495880
Short name T210
Test name
Test status
Simulation time 101100155230 ps
CPU time 2298.47 seconds
Started May 21 02:13:02 PM PDT 24
Finished May 21 02:51:25 PM PDT 24
Peak memory 227548 kb
Host smart-6d8c32a5-4b35-4a1b-a6bb-67318761a69a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916495880 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3916495880
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1170583366
Short name T659
Test name
Test status
Simulation time 75075435 ps
CPU time 1.11 seconds
Started May 21 02:16:07 PM PDT 24
Finished May 21 02:16:13 PM PDT 24
Peak memory 215356 kb
Host smart-141806d9-69d5-47f6-9fa4-3d72fe2371cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170583366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1170583366
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1856021049
Short name T773
Test name
Test status
Simulation time 39216355 ps
CPU time 0.91 seconds
Started May 21 02:16:12 PM PDT 24
Finished May 21 02:16:18 PM PDT 24
Peak memory 206292 kb
Host smart-8c551b7b-2989-4c14-bacc-d72b0f1c4234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856021049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1856021049
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2900281005
Short name T203
Test name
Test status
Simulation time 37229107 ps
CPU time 0.9 seconds
Started May 21 02:16:11 PM PDT 24
Finished May 21 02:16:17 PM PDT 24
Peak memory 216044 kb
Host smart-71d2e4ca-f43a-413d-9173-5679f004ddac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900281005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2900281005
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1208431253
Short name T19
Test name
Test status
Simulation time 155553514 ps
CPU time 1.09 seconds
Started May 21 02:16:09 PM PDT 24
Finished May 21 02:16:16 PM PDT 24
Peak memory 216472 kb
Host smart-d2a72097-37bf-4922-a9aa-9b035c6311be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208431253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1208431253
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1061092052
Short name T49
Test name
Test status
Simulation time 20210695 ps
CPU time 1.11 seconds
Started May 21 02:16:08 PM PDT 24
Finished May 21 02:16:15 PM PDT 24
Peak memory 219164 kb
Host smart-cc2f2511-a503-44c2-98f4-1f208c7dc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061092052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1061092052
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3081339731
Short name T589
Test name
Test status
Simulation time 353705543 ps
CPU time 3.27 seconds
Started May 21 02:16:06 PM PDT 24
Finished May 21 02:16:13 PM PDT 24
Peak memory 219188 kb
Host smart-2c5083c4-2670-463a-92de-90c0bb589a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081339731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3081339731
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3577337092
Short name T685
Test name
Test status
Simulation time 22338047 ps
CPU time 1.21 seconds
Started May 21 02:16:10 PM PDT 24
Finished May 21 02:16:17 PM PDT 24
Peak memory 223608 kb
Host smart-28a96447-f212-470f-ae7a-09dc964d375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577337092 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3577337092
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1646556857
Short name T627
Test name
Test status
Simulation time 15440838 ps
CPU time 0.98 seconds
Started May 21 02:16:05 PM PDT 24
Finished May 21 02:16:08 PM PDT 24
Peak memory 214868 kb
Host smart-4f3ee22c-ccb4-4d5e-9041-6612da8c4e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646556857 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1646556857
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1967344443
Short name T381
Test name
Test status
Simulation time 168099445 ps
CPU time 2.3 seconds
Started May 21 02:16:12 PM PDT 24
Finished May 21 02:16:19 PM PDT 24
Peak memory 216592 kb
Host smart-9f4b34c3-94bb-4e17-9762-19b3afb1f4c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967344443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1967344443
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.4150241244
Short name T78
Test name
Test status
Simulation time 639789720247 ps
CPU time 1166.94 seconds
Started May 21 02:16:09 PM PDT 24
Finished May 21 02:35:42 PM PDT 24
Peak memory 220020 kb
Host smart-adefd126-9cf2-4bae-a139-5cc561eb9a11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150241244 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.4150241244
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1785801615
Short name T302
Test name
Test status
Simulation time 26531207 ps
CPU time 1.23 seconds
Started May 21 02:16:16 PM PDT 24
Finished May 21 02:16:20 PM PDT 24
Peak memory 215360 kb
Host smart-beeec254-fabd-41eb-b78e-628f4eee3374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785801615 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1785801615
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1114370042
Short name T526
Test name
Test status
Simulation time 57665276 ps
CPU time 0.91 seconds
Started May 21 02:16:23 PM PDT 24
Finished May 21 02:16:25 PM PDT 24
Peak memory 214520 kb
Host smart-210940f1-f146-4e7e-9aa9-069dfd263fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114370042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1114370042
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.2406640021
Short name T813
Test name
Test status
Simulation time 39256238 ps
CPU time 0.92 seconds
Started May 21 02:16:17 PM PDT 24
Finished May 21 02:16:20 PM PDT 24
Peak memory 216260 kb
Host smart-8c232e8c-3575-4e03-9a18-59c52e535b36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406640021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2406640021
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1851438701
Short name T549
Test name
Test status
Simulation time 104724727 ps
CPU time 1.01 seconds
Started May 21 02:16:22 PM PDT 24
Finished May 21 02:16:24 PM PDT 24
Peak memory 219312 kb
Host smart-8fec3f1b-fa29-4a03-8623-5786c677d210
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851438701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1851438701
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.947343064
Short name T777
Test name
Test status
Simulation time 33993557 ps
CPU time 0.9 seconds
Started May 21 02:16:16 PM PDT 24
Finished May 21 02:16:19 PM PDT 24
Peak memory 218032 kb
Host smart-841bf8ab-5d22-4ecd-a300-3440e26c019f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947343064 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.947343064
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3356926230
Short name T294
Test name
Test status
Simulation time 102281133 ps
CPU time 1.25 seconds
Started May 21 02:16:11 PM PDT 24
Finished May 21 02:16:18 PM PDT 24
Peak memory 214916 kb
Host smart-e81a6189-45c0-4f74-9136-d2cfff97ea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356926230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3356926230
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2750362905
Short name T572
Test name
Test status
Simulation time 54466977 ps
CPU time 0.87 seconds
Started May 21 02:16:18 PM PDT 24
Finished May 21 02:16:20 PM PDT 24
Peak memory 215148 kb
Host smart-0e74c8be-cbf4-4cbd-8201-a2b5579a4cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750362905 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2750362905
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2509410171
Short name T348
Test name
Test status
Simulation time 33464489 ps
CPU time 0.91 seconds
Started May 21 02:16:11 PM PDT 24
Finished May 21 02:16:18 PM PDT 24
Peak memory 206744 kb
Host smart-6c97fbdf-4eaa-4626-83a4-2f0496f9b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509410171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2509410171
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3637158977
Short name T523
Test name
Test status
Simulation time 752241895 ps
CPU time 4.15 seconds
Started May 21 02:16:10 PM PDT 24
Finished May 21 02:16:20 PM PDT 24
Peak memory 218824 kb
Host smart-072f12ee-4b68-4eaf-806c-d09e7289ba91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637158977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3637158977
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1744825312
Short name T702
Test name
Test status
Simulation time 202853672191 ps
CPU time 663.01 seconds
Started May 21 02:16:11 PM PDT 24
Finished May 21 02:27:20 PM PDT 24
Peak memory 219948 kb
Host smart-dc05b85e-be50-429a-a0f3-4b31dc0c8dba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744825312 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1744825312
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.539686198
Short name T305
Test name
Test status
Simulation time 26631739 ps
CPU time 1.26 seconds
Started May 21 02:16:37 PM PDT 24
Finished May 21 02:16:39 PM PDT 24
Peak memory 215280 kb
Host smart-09b406e6-a38e-44f2-9012-e41e50030bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539686198 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.539686198
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1580487946
Short name T770
Test name
Test status
Simulation time 50861091 ps
CPU time 0.91 seconds
Started May 21 02:16:46 PM PDT 24
Finished May 21 02:16:47 PM PDT 24
Peak memory 214864 kb
Host smart-9187b240-b839-49e7-bb9d-5b12ce29bd9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580487946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1580487946
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3588588713
Short name T574
Test name
Test status
Simulation time 75211717 ps
CPU time 1.07 seconds
Started May 21 02:16:48 PM PDT 24
Finished May 21 02:16:51 PM PDT 24
Peak memory 216520 kb
Host smart-4c2f5d0b-0ae8-45d0-ba8d-273b88027a91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588588713 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3588588713
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1464881588
Short name T109
Test name
Test status
Simulation time 44348731 ps
CPU time 1.01 seconds
Started May 21 02:16:34 PM PDT 24
Finished May 21 02:16:37 PM PDT 24
Peak memory 217896 kb
Host smart-a6c76258-c545-43ac-8671-63aedec4f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464881588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1464881588
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1047766924
Short name T63
Test name
Test status
Simulation time 93618633 ps
CPU time 1.34 seconds
Started May 21 02:16:27 PM PDT 24
Finished May 21 02:16:30 PM PDT 24
Peak memory 216560 kb
Host smart-fd66c1f5-2493-42e6-849c-2a1656980190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047766924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1047766924
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.211345951
Short name T509
Test name
Test status
Simulation time 27923954 ps
CPU time 0.98 seconds
Started May 21 02:16:32 PM PDT 24
Finished May 21 02:16:34 PM PDT 24
Peak memory 215044 kb
Host smart-4910e1d2-a374-41ba-b2a4-64a4452661d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211345951 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.211345951
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3754150262
Short name T374
Test name
Test status
Simulation time 38252550 ps
CPU time 0.91 seconds
Started May 21 02:16:25 PM PDT 24
Finished May 21 02:16:28 PM PDT 24
Peak memory 215032 kb
Host smart-cc696a46-f8ea-4ae8-8cf8-db30d5438b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754150262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3754150262
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1691656562
Short name T220
Test name
Test status
Simulation time 328499254 ps
CPU time 6.72 seconds
Started May 21 02:16:32 PM PDT 24
Finished May 21 02:16:40 PM PDT 24
Peak memory 216468 kb
Host smart-88885475-c2d9-4a97-bb93-08b7a6dc93fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691656562 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1691656562
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4125301345
Short name T517
Test name
Test status
Simulation time 102015721385 ps
CPU time 742.26 seconds
Started May 21 02:16:29 PM PDT 24
Finished May 21 02:28:53 PM PDT 24
Peak memory 220328 kb
Host smart-e440c367-8e21-4d8a-a1f3-e82123143393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125301345 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4125301345
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2683644248
Short name T125
Test name
Test status
Simulation time 101114652 ps
CPU time 1.29 seconds
Started May 21 02:16:52 PM PDT 24
Finished May 21 02:16:55 PM PDT 24
Peak memory 215408 kb
Host smart-aee8f68b-0178-41c9-b05c-1afa2db6af9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683644248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2683644248
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3557092539
Short name T731
Test name
Test status
Simulation time 45052781 ps
CPU time 0.94 seconds
Started May 21 02:16:55 PM PDT 24
Finished May 21 02:16:57 PM PDT 24
Peak memory 214920 kb
Host smart-0485200b-2aab-4fca-a9c9-e8ed77765847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557092539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3557092539
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.924783834
Short name T132
Test name
Test status
Simulation time 13762503 ps
CPU time 0.91 seconds
Started May 21 02:17:00 PM PDT 24
Finished May 21 02:17:01 PM PDT 24
Peak memory 216404 kb
Host smart-2224273d-cb1e-4bab-9c4a-d58ed01c7587
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924783834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.924783834
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.4037668775
Short name T495
Test name
Test status
Simulation time 24490687 ps
CPU time 0.95 seconds
Started May 21 02:16:58 PM PDT 24
Finished May 21 02:17:00 PM PDT 24
Peak memory 217732 kb
Host smart-e34b6451-4f65-457d-a542-fadc725567ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037668775 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.4037668775
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2580182318
Short name T766
Test name
Test status
Simulation time 35431991 ps
CPU time 1.08 seconds
Started May 21 02:16:52 PM PDT 24
Finished May 21 02:16:54 PM PDT 24
Peak memory 220112 kb
Host smart-40a1b4f2-dc1a-457d-94c0-096411cd0c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580182318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2580182318
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.525410379
Short name T707
Test name
Test status
Simulation time 87919055 ps
CPU time 1.18 seconds
Started May 21 02:16:50 PM PDT 24
Finished May 21 02:16:53 PM PDT 24
Peak memory 214960 kb
Host smart-4020fbcb-3431-496a-aa37-9781ba4f44db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525410379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.525410379
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1406703653
Short name T14
Test name
Test status
Simulation time 23356009 ps
CPU time 1.24 seconds
Started May 21 02:16:52 PM PDT 24
Finished May 21 02:16:54 PM PDT 24
Peak memory 223572 kb
Host smart-9e1c888e-bec4-47da-8798-2f0e8ca02164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406703653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1406703653
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.294633851
Short name T476
Test name
Test status
Simulation time 15881502 ps
CPU time 0.98 seconds
Started May 21 02:16:59 PM PDT 24
Finished May 21 02:17:01 PM PDT 24
Peak memory 214916 kb
Host smart-99f0009e-77ad-45c6-8ae9-2db21473526f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294633851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.294633851
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.881925250
Short name T412
Test name
Test status
Simulation time 310551455 ps
CPU time 6.06 seconds
Started May 21 02:16:52 PM PDT 24
Finished May 21 02:16:59 PM PDT 24
Peak memory 216616 kb
Host smart-96b051bb-e7a8-455d-972c-3dcb8b7d8f1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881925250 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.881925250
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2679060609
Short name T620
Test name
Test status
Simulation time 200647177112 ps
CPU time 1289.13 seconds
Started May 21 02:16:51 PM PDT 24
Finished May 21 02:38:22 PM PDT 24
Peak memory 224776 kb
Host smart-a8c419cf-116c-4a86-9a0b-282fb946971f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679060609 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2679060609
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4175880053
Short name T219
Test name
Test status
Simulation time 101740226 ps
CPU time 1.32 seconds
Started May 21 02:17:15 PM PDT 24
Finished May 21 02:17:19 PM PDT 24
Peak memory 215280 kb
Host smart-0ea6b9c3-b047-470d-9f9f-85dae13734db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175880053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4175880053
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2993928658
Short name T319
Test name
Test status
Simulation time 40062260 ps
CPU time 0.84 seconds
Started May 21 02:17:28 PM PDT 24
Finished May 21 02:17:29 PM PDT 24
Peak memory 206080 kb
Host smart-9d9582b0-200d-4446-a672-5fd97fbcb1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993928658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2993928658
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.477224610
Short name T134
Test name
Test status
Simulation time 25065644 ps
CPU time 0.86 seconds
Started May 21 02:17:24 PM PDT 24
Finished May 21 02:17:26 PM PDT 24
Peak memory 216028 kb
Host smart-2cf04334-2a64-4ecc-82d8-c4a6926e34ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477224610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.477224610
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4120256192
Short name T410
Test name
Test status
Simulation time 62719873 ps
CPU time 1.08 seconds
Started May 21 02:17:25 PM PDT 24
Finished May 21 02:17:27 PM PDT 24
Peak memory 217768 kb
Host smart-fe3cc36b-e001-44d3-b27e-00d1f95e7d86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120256192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4120256192
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2256972551
Short name T587
Test name
Test status
Simulation time 24099904 ps
CPU time 0.95 seconds
Started May 21 02:17:14 PM PDT 24
Finished May 21 02:17:17 PM PDT 24
Peak memory 218216 kb
Host smart-9f304238-6fcb-4be3-a2d5-bdb1cc5a734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256972551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2256972551
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1965083562
Short name T764
Test name
Test status
Simulation time 43318726 ps
CPU time 1.2 seconds
Started May 21 02:17:05 PM PDT 24
Finished May 21 02:17:07 PM PDT 24
Peak memory 217772 kb
Host smart-eb0a367e-f812-418f-9017-257a3934b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965083562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1965083562
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1663974662
Short name T814
Test name
Test status
Simulation time 23795469 ps
CPU time 1.18 seconds
Started May 21 02:17:15 PM PDT 24
Finished May 21 02:17:18 PM PDT 24
Peak memory 223632 kb
Host smart-6424dfb3-8a63-492e-9812-2c9de64e8bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663974662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1663974662
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.303008933
Short name T414
Test name
Test status
Simulation time 140425316 ps
CPU time 0.88 seconds
Started May 21 02:17:05 PM PDT 24
Finished May 21 02:17:07 PM PDT 24
Peak memory 214992 kb
Host smart-df29faa9-b920-4281-8015-db354147351f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303008933 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.303008933
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3949535788
Short name T175
Test name
Test status
Simulation time 408764689 ps
CPU time 3.07 seconds
Started May 21 02:17:11 PM PDT 24
Finished May 21 02:17:17 PM PDT 24
Peak memory 216664 kb
Host smart-75ebd0d0-0fd8-4ce2-ab3f-2465f4188802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949535788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3949535788
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2799867750
Short name T207
Test name
Test status
Simulation time 258803485665 ps
CPU time 1603.55 seconds
Started May 21 02:17:12 PM PDT 24
Finished May 21 02:43:58 PM PDT 24
Peak memory 232236 kb
Host smart-a6433788-3e2c-4f6e-9820-f77e1581ce46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799867750 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2799867750
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2049131574
Short name T73
Test name
Test status
Simulation time 53549660 ps
CPU time 1.21 seconds
Started May 21 02:17:31 PM PDT 24
Finished May 21 02:17:33 PM PDT 24
Peak memory 215484 kb
Host smart-3b5d22f8-8c8b-4a3d-b562-9646540f4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049131574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2049131574
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.502741063
Short name T415
Test name
Test status
Simulation time 23337072 ps
CPU time 0.82 seconds
Started May 21 02:17:37 PM PDT 24
Finished May 21 02:17:39 PM PDT 24
Peak memory 206288 kb
Host smart-ea8b7c99-8d2e-42d1-9c36-1dc587dffb2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502741063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.502741063
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.131570108
Short name T115
Test name
Test status
Simulation time 111133516 ps
CPU time 1.09 seconds
Started May 21 02:17:38 PM PDT 24
Finished May 21 02:17:41 PM PDT 24
Peak memory 216568 kb
Host smart-fdcb13d6-3dc0-4ff3-94cb-93961b91e99b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131570108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.131570108
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2027103606
Short name T715
Test name
Test status
Simulation time 24646834 ps
CPU time 1 seconds
Started May 21 02:17:34 PM PDT 24
Finished May 21 02:17:36 PM PDT 24
Peak memory 223276 kb
Host smart-df4848b9-25ac-44f0-af05-8b834c3b5c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027103606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2027103606
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3423000090
Short name T681
Test name
Test status
Simulation time 51582853 ps
CPU time 1.03 seconds
Started May 21 02:17:26 PM PDT 24
Finished May 21 02:17:28 PM PDT 24
Peak memory 219368 kb
Host smart-fb3f741c-0469-41dd-9db9-3b3540223743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423000090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3423000090
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_smoke.2982312281
Short name T382
Test name
Test status
Simulation time 24454927 ps
CPU time 0.9 seconds
Started May 21 02:17:29 PM PDT 24
Finished May 21 02:17:31 PM PDT 24
Peak memory 206768 kb
Host smart-9b2c38cc-695a-4733-af8c-7fa681e706f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982312281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2982312281
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3272628933
Short name T592
Test name
Test status
Simulation time 281072924 ps
CPU time 5.63 seconds
Started May 21 02:17:33 PM PDT 24
Finished May 21 02:17:40 PM PDT 24
Peak memory 216472 kb
Host smart-50b2ae31-cdba-4fa5-aead-d4eb13288f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272628933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3272628933
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2199712903
Short name T215
Test name
Test status
Simulation time 3689761071 ps
CPU time 66.68 seconds
Started May 21 02:17:31 PM PDT 24
Finished May 21 02:18:39 PM PDT 24
Peak memory 220532 kb
Host smart-6f797ad8-d950-4959-bea4-438a5bd58d69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199712903 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2199712903
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert_test.3587153914
Short name T332
Test name
Test status
Simulation time 44863677 ps
CPU time 0.87 seconds
Started May 21 02:17:53 PM PDT 24
Finished May 21 02:17:55 PM PDT 24
Peak memory 214904 kb
Host smart-baef6bbe-ccb6-442e-97ac-41be6f7c22da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587153914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3587153914
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2388603131
Short name T182
Test name
Test status
Simulation time 21531718 ps
CPU time 0.9 seconds
Started May 21 02:17:55 PM PDT 24
Finished May 21 02:17:57 PM PDT 24
Peak memory 216024 kb
Host smart-e9c9eb07-5f42-4ad6-a315-24f32fa0d1cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388603131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2388603131
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.736153916
Short name T829
Test name
Test status
Simulation time 86139666 ps
CPU time 1.18 seconds
Started May 21 02:17:54 PM PDT 24
Finished May 21 02:17:56 PM PDT 24
Peak memory 217956 kb
Host smart-284c4881-a7f4-4cea-ad94-738f987e9007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736153916 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.736153916
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3619016520
Short name T91
Test name
Test status
Simulation time 32476018 ps
CPU time 1.15 seconds
Started May 21 02:17:55 PM PDT 24
Finished May 21 02:17:57 PM PDT 24
Peak memory 220336 kb
Host smart-1aff591a-e068-4d83-8f4b-d87cccf2e4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619016520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3619016520
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3275407250
Short name T376
Test name
Test status
Simulation time 88236886 ps
CPU time 1.4 seconds
Started May 21 02:17:43 PM PDT 24
Finished May 21 02:17:48 PM PDT 24
Peak memory 216932 kb
Host smart-56437251-2592-43ba-ada9-53eeb2baf881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275407250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3275407250
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.4233502116
Short name T159
Test name
Test status
Simulation time 21670103 ps
CPU time 1 seconds
Started May 21 02:17:44 PM PDT 24
Finished May 21 02:17:48 PM PDT 24
Peak memory 215524 kb
Host smart-4b48c9d9-7f47-47de-9d31-a7d54c00d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233502116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.4233502116
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3497720629
Short name T537
Test name
Test status
Simulation time 17071548 ps
CPU time 1.02 seconds
Started May 21 02:17:38 PM PDT 24
Finished May 21 02:17:41 PM PDT 24
Peak memory 215020 kb
Host smart-f265de13-c6df-4644-b2dc-f9cda6193c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497720629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3497720629
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2967794149
Short name T174
Test name
Test status
Simulation time 193765360 ps
CPU time 4.08 seconds
Started May 21 02:17:43 PM PDT 24
Finished May 21 02:17:49 PM PDT 24
Peak memory 216592 kb
Host smart-f555e92f-b3d8-4619-b255-9946b8c884bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967794149 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2967794149
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4268778387
Short name T208
Test name
Test status
Simulation time 210033195817 ps
CPU time 1234.31 seconds
Started May 21 02:17:44 PM PDT 24
Finished May 21 02:38:21 PM PDT 24
Peak memory 221500 kb
Host smart-109112b7-b94d-41ab-9974-6330cf137e31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268778387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4268778387
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2180312800
Short name T608
Test name
Test status
Simulation time 78872101 ps
CPU time 1.12 seconds
Started May 21 02:18:04 PM PDT 24
Finished May 21 02:18:07 PM PDT 24
Peak memory 215356 kb
Host smart-dd02decb-8f6b-4dc9-b80d-5fc3f9bc81ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180312800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2180312800
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2305562475
Short name T337
Test name
Test status
Simulation time 29102204 ps
CPU time 0.93 seconds
Started May 21 02:18:16 PM PDT 24
Finished May 21 02:18:19 PM PDT 24
Peak memory 206196 kb
Host smart-a7b1d54e-5eb7-4cb3-9449-172ea7ddad9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305562475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2305562475
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2138127383
Short name T88
Test name
Test status
Simulation time 17953908 ps
CPU time 0.9 seconds
Started May 21 02:18:11 PM PDT 24
Finished May 21 02:18:13 PM PDT 24
Peak memory 215960 kb
Host smart-253417dd-1ee7-476b-8c79-920abfec9254
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138127383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2138127383
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1789580629
Short name T838
Test name
Test status
Simulation time 50278497 ps
CPU time 1 seconds
Started May 21 02:18:10 PM PDT 24
Finished May 21 02:18:12 PM PDT 24
Peak memory 217628 kb
Host smart-c7537781-8c3c-473e-91ef-42c1b9de5a63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789580629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1789580629
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.645490476
Short name T8
Test name
Test status
Simulation time 36906806 ps
CPU time 1.01 seconds
Started May 21 02:18:07 PM PDT 24
Finished May 21 02:18:10 PM PDT 24
Peak memory 219324 kb
Host smart-32444435-94a5-4fab-8bd3-48a30d5269d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645490476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.645490476
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1947306846
Short name T436
Test name
Test status
Simulation time 48824670 ps
CPU time 1.22 seconds
Started May 21 02:18:00 PM PDT 24
Finished May 21 02:18:03 PM PDT 24
Peak memory 217856 kb
Host smart-ce8d8208-875a-4caa-ad1b-11729acecec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947306846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1947306846
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2452234008
Short name T435
Test name
Test status
Simulation time 22270716 ps
CPU time 1.14 seconds
Started May 21 02:18:05 PM PDT 24
Finished May 21 02:18:08 PM PDT 24
Peak memory 215284 kb
Host smart-9b8e646f-bae1-46d1-9a2e-0df252204681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452234008 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2452234008
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1727276506
Short name T745
Test name
Test status
Simulation time 59001464 ps
CPU time 0.88 seconds
Started May 21 02:17:55 PM PDT 24
Finished May 21 02:17:57 PM PDT 24
Peak memory 215004 kb
Host smart-ce81252a-57a7-43cf-b05f-d842da8bd0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727276506 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1727276506
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3605403440
Short name T553
Test name
Test status
Simulation time 369977683 ps
CPU time 4.46 seconds
Started May 21 02:18:01 PM PDT 24
Finished May 21 02:18:07 PM PDT 24
Peak memory 215000 kb
Host smart-37175942-03c5-4785-afe8-2cc4bec68cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605403440 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3605403440
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3631636185
Short name T377
Test name
Test status
Simulation time 12547010638 ps
CPU time 321.57 seconds
Started May 21 02:17:59 PM PDT 24
Finished May 21 02:23:21 PM PDT 24
Peak memory 216372 kb
Host smart-030972d3-9416-4d65-b421-00df03a908db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631636185 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3631636185
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.328310770
Short name T166
Test name
Test status
Simulation time 92279224 ps
CPU time 1.3 seconds
Started May 21 02:18:22 PM PDT 24
Finished May 21 02:18:25 PM PDT 24
Peak memory 215296 kb
Host smart-e89a6ff0-c231-4d68-b91a-c8a0626f5ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328310770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.328310770
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.448769066
Short name T703
Test name
Test status
Simulation time 17311624 ps
CPU time 0.96 seconds
Started May 21 02:18:34 PM PDT 24
Finished May 21 02:18:36 PM PDT 24
Peak memory 206316 kb
Host smart-67cfb7a1-af0b-40c1-bfa2-bec303f0b73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448769066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.448769066
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1389277845
Short name T202
Test name
Test status
Simulation time 22135669 ps
CPU time 0.91 seconds
Started May 21 02:18:26 PM PDT 24
Finished May 21 02:18:28 PM PDT 24
Peak memory 215160 kb
Host smart-40b1a435-89a9-40b8-b367-c7f42fe445ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389277845 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1389277845
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2136000436
Short name T113
Test name
Test status
Simulation time 55491452 ps
CPU time 0.99 seconds
Started May 21 02:18:27 PM PDT 24
Finished May 21 02:18:29 PM PDT 24
Peak memory 216536 kb
Host smart-2b8df535-04f0-4ecf-aa2a-63b2adeb02c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136000436 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2136000436
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.164889510
Short name T93
Test name
Test status
Simulation time 24721434 ps
CPU time 1.04 seconds
Started May 21 02:18:26 PM PDT 24
Finished May 21 02:18:28 PM PDT 24
Peak memory 219148 kb
Host smart-6701c847-0de2-48b0-8bd0-bc209a48c87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164889510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.164889510
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1269705817
Short name T443
Test name
Test status
Simulation time 45057709 ps
CPU time 1.58 seconds
Started May 21 02:18:17 PM PDT 24
Finished May 21 02:18:20 PM PDT 24
Peak memory 217968 kb
Host smart-5b82bdfa-81ff-41ec-bf1f-9f6cbe257f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269705817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1269705817
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2833137361
Short name T483
Test name
Test status
Simulation time 23656333 ps
CPU time 1.01 seconds
Started May 21 02:18:21 PM PDT 24
Finished May 21 02:18:23 PM PDT 24
Peak memory 215292 kb
Host smart-c3d47c59-5391-4e90-8658-94856777aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833137361 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2833137361
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1449711923
Short name T468
Test name
Test status
Simulation time 15332652 ps
CPU time 0.98 seconds
Started May 21 02:18:17 PM PDT 24
Finished May 21 02:18:19 PM PDT 24
Peak memory 215064 kb
Host smart-4ab1fd1c-52a4-4247-a456-2f2c2965ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449711923 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1449711923
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1329778708
Short name T647
Test name
Test status
Simulation time 82688181 ps
CPU time 2.16 seconds
Started May 21 02:18:23 PM PDT 24
Finished May 21 02:18:27 PM PDT 24
Peak memory 216580 kb
Host smart-31b90031-02da-4630-af58-fa96e57e49ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329778708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1329778708
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.468816501
Short name T834
Test name
Test status
Simulation time 37450702858 ps
CPU time 519.31 seconds
Started May 21 02:18:21 PM PDT 24
Finished May 21 02:27:02 PM PDT 24
Peak memory 217528 kb
Host smart-c58c3d5c-23ab-40de-bf8f-ba5bc91f0517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468816501 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.468816501
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2250897965
Short name T164
Test name
Test status
Simulation time 31671452 ps
CPU time 1.36 seconds
Started May 21 02:18:45 PM PDT 24
Finished May 21 02:18:49 PM PDT 24
Peak memory 215388 kb
Host smart-94272e22-308d-4d6d-9c12-14cd3f083014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250897965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2250897965
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4078988556
Short name T393
Test name
Test status
Simulation time 39738327 ps
CPU time 0.82 seconds
Started May 21 02:18:56 PM PDT 24
Finished May 21 02:18:58 PM PDT 24
Peak memory 206032 kb
Host smart-02002191-64b0-4e45-a5c5-04a199ab1a60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078988556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4078988556
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4211847021
Short name T133
Test name
Test status
Simulation time 26336403 ps
CPU time 0.85 seconds
Started May 21 02:18:51 PM PDT 24
Finished May 21 02:18:53 PM PDT 24
Peak memory 215976 kb
Host smart-531060c4-5402-432d-b4b8-5828c1eb7b96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211847021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4211847021
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2252022939
Short name T116
Test name
Test status
Simulation time 46989061 ps
CPU time 1.36 seconds
Started May 21 02:18:49 PM PDT 24
Finished May 21 02:18:52 PM PDT 24
Peak memory 216492 kb
Host smart-53963d11-72a5-470d-bf0f-1f484c83fad0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252022939 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2252022939
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2706890621
Short name T56
Test name
Test status
Simulation time 38136011 ps
CPU time 1.21 seconds
Started May 21 02:18:43 PM PDT 24
Finished May 21 02:18:47 PM PDT 24
Peak memory 231636 kb
Host smart-156b8acd-d2d6-4b21-bc40-e272b22308c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706890621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2706890621
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1369431365
Short name T375
Test name
Test status
Simulation time 91729811 ps
CPU time 3.04 seconds
Started May 21 02:18:32 PM PDT 24
Finished May 21 02:18:37 PM PDT 24
Peak memory 219236 kb
Host smart-a358ef36-f87d-474f-95c4-c19b77779e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369431365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1369431365
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3453607130
Short name T32
Test name
Test status
Simulation time 36551731 ps
CPU time 0.91 seconds
Started May 21 02:18:43 PM PDT 24
Finished May 21 02:18:46 PM PDT 24
Peak memory 215228 kb
Host smart-00b3130b-e942-4cc8-b753-ceb6ddd00a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453607130 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3453607130
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1264835387
Short name T811
Test name
Test status
Simulation time 17026296 ps
CPU time 1.02 seconds
Started May 21 02:18:31 PM PDT 24
Finished May 21 02:18:33 PM PDT 24
Peak memory 214972 kb
Host smart-f0377c03-a129-4a1f-bf2d-4b95a7bba6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264835387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1264835387
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3991100283
Short name T390
Test name
Test status
Simulation time 225715383 ps
CPU time 4.83 seconds
Started May 21 02:18:33 PM PDT 24
Finished May 21 02:18:39 PM PDT 24
Peak memory 218376 kb
Host smart-02bd7976-a326-4c07-a4da-bf47ee405b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991100283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3991100283
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3005369536
Short name T827
Test name
Test status
Simulation time 115772697572 ps
CPU time 2955.21 seconds
Started May 21 02:18:38 PM PDT 24
Finished May 21 03:07:54 PM PDT 24
Peak memory 234488 kb
Host smart-07ff7a9c-61ba-409b-983a-2a61d5e1ed2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005369536 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3005369536
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3964181427
Short name T791
Test name
Test status
Simulation time 69627182 ps
CPU time 1.2 seconds
Started May 21 02:13:12 PM PDT 24
Finished May 21 02:13:19 PM PDT 24
Peak memory 215380 kb
Host smart-537ea907-1973-4eb0-9a42-973e431bb794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964181427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3964181427
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.620503745
Short name T471
Test name
Test status
Simulation time 18395915 ps
CPU time 0.87 seconds
Started May 21 02:13:12 PM PDT 24
Finished May 21 02:13:18 PM PDT 24
Peak memory 206116 kb
Host smart-30a7257e-fca0-4708-8ee4-073122575720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620503745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.620503745
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.793189250
Short name T74
Test name
Test status
Simulation time 13765417 ps
CPU time 0.92 seconds
Started May 21 02:13:06 PM PDT 24
Finished May 21 02:13:12 PM PDT 24
Peak memory 215376 kb
Host smart-852cd906-8e46-47a3-8891-c7d76cc031e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793189250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.793189250
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3606255282
Short name T407
Test name
Test status
Simulation time 103735551 ps
CPU time 1.12 seconds
Started May 21 02:13:13 PM PDT 24
Finished May 21 02:13:20 PM PDT 24
Peak memory 217852 kb
Host smart-c5122170-6ff0-475e-ba5f-a7e879fb5c93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606255282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3606255282
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3206035377
Short name T646
Test name
Test status
Simulation time 20856862 ps
CPU time 1.14 seconds
Started May 21 02:13:10 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 219300 kb
Host smart-7ec28d98-d5f4-47db-86b9-19fef52078dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206035377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3206035377
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1448204845
Short name T493
Test name
Test status
Simulation time 72507037 ps
CPU time 1.51 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:13:14 PM PDT 24
Peak memory 218052 kb
Host smart-90bd0619-c924-4073-bd11-b696eb5382c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448204845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1448204845
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.840071357
Short name T5
Test name
Test status
Simulation time 71342084 ps
CPU time 0.88 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:13 PM PDT 24
Peak memory 215132 kb
Host smart-b1b2842c-2412-4b32-a3d4-c1d4735c3a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840071357 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.840071357
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.1118349553
Short name T474
Test name
Test status
Simulation time 14357511 ps
CPU time 1 seconds
Started May 21 02:13:10 PM PDT 24
Finished May 21 02:13:16 PM PDT 24
Peak memory 214884 kb
Host smart-7d831a14-c3c9-4f7f-9e5a-424d0d4084ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118349553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1118349553
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3033512255
Short name T367
Test name
Test status
Simulation time 786049782 ps
CPU time 2.73 seconds
Started May 21 02:13:07 PM PDT 24
Finished May 21 02:13:15 PM PDT 24
Peak memory 215032 kb
Host smart-5a3ace7e-d291-4020-ac71-c61afb94db03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033512255 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3033512255
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2434774245
Short name T40
Test name
Test status
Simulation time 18653413712 ps
CPU time 450.12 seconds
Started May 21 02:13:08 PM PDT 24
Finished May 21 02:20:43 PM PDT 24
Peak memory 218204 kb
Host smart-c51ee1b9-4867-4f8d-a798-198b0c8b7896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434774245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2434774245
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.4114515872
Short name T95
Test name
Test status
Simulation time 55390958 ps
CPU time 0.92 seconds
Started May 21 02:18:56 PM PDT 24
Finished May 21 02:18:58 PM PDT 24
Peak memory 219176 kb
Host smart-c155fcf1-bb26-4a0f-a9b9-71b050ea39ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114515872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.4114515872
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2520552627
Short name T547
Test name
Test status
Simulation time 37848180 ps
CPU time 1.46 seconds
Started May 21 02:18:56 PM PDT 24
Finished May 21 02:18:58 PM PDT 24
Peak memory 219588 kb
Host smart-0fb96519-fe92-4b06-aa92-c40a1405ade3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520552627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2520552627
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3150388686
Short name T780
Test name
Test status
Simulation time 48872186 ps
CPU time 1.01 seconds
Started May 21 02:19:02 PM PDT 24
Finished May 21 02:19:03 PM PDT 24
Peak memory 217928 kb
Host smart-3e3896df-9c72-40ea-8cb7-f9993bef47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150388686 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3150388686
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.251000202
Short name T798
Test name
Test status
Simulation time 60736718 ps
CPU time 1.43 seconds
Started May 21 02:19:01 PM PDT 24
Finished May 21 02:19:04 PM PDT 24
Peak memory 216572 kb
Host smart-785fd48a-1ac4-4903-8f8c-a75242c377a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251000202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.251000202
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.4103366851
Short name T105
Test name
Test status
Simulation time 61991581 ps
CPU time 1.07 seconds
Started May 21 02:19:02 PM PDT 24
Finished May 21 02:19:05 PM PDT 24
Peak memory 219104 kb
Host smart-ea50a368-a791-45cc-b06a-f146af2725f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103366851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4103366851
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1292615136
Short name T491
Test name
Test status
Simulation time 34571958 ps
CPU time 1.56 seconds
Started May 21 02:19:01 PM PDT 24
Finished May 21 02:19:03 PM PDT 24
Peak memory 217792 kb
Host smart-075b94a8-e830-4c47-9cf8-72e4481e005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292615136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1292615136
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.641240714
Short name T131
Test name
Test status
Simulation time 18504305 ps
CPU time 1.05 seconds
Started May 21 02:19:08 PM PDT 24
Finished May 21 02:19:10 PM PDT 24
Peak memory 218000 kb
Host smart-440dbc1a-8870-4ad8-8224-1f05dd854041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641240714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.641240714
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2196785522
Short name T821
Test name
Test status
Simulation time 52123990 ps
CPU time 1.21 seconds
Started May 21 02:19:07 PM PDT 24
Finished May 21 02:19:09 PM PDT 24
Peak memory 216928 kb
Host smart-644e58e8-58df-4d3a-9670-8669d56238fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196785522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2196785522
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2257492506
Short name T196
Test name
Test status
Simulation time 42023834 ps
CPU time 1.28 seconds
Started May 21 02:19:16 PM PDT 24
Finished May 21 02:19:18 PM PDT 24
Peak memory 219372 kb
Host smart-0bc4521c-a92e-4146-bf27-7a58ca9cc6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257492506 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2257492506
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2631983603
Short name T585
Test name
Test status
Simulation time 64304398 ps
CPU time 1.06 seconds
Started May 21 02:19:17 PM PDT 24
Finished May 21 02:19:19 PM PDT 24
Peak memory 215108 kb
Host smart-3017e45c-1a04-4178-9084-4f8b18f2a9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631983603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2631983603
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1915736443
Short name T100
Test name
Test status
Simulation time 48687679 ps
CPU time 1.09 seconds
Started May 21 02:19:19 PM PDT 24
Finished May 21 02:19:20 PM PDT 24
Peak memory 229120 kb
Host smart-6431ab53-2a3d-44e9-bcb8-763032356b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915736443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1915736443
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1003449193
Short name T396
Test name
Test status
Simulation time 141291703 ps
CPU time 1.48 seconds
Started May 21 02:19:17 PM PDT 24
Finished May 21 02:19:19 PM PDT 24
Peak memory 218256 kb
Host smart-39ea5c1f-7cf7-4f4b-b5ba-a7e3dab2f9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003449193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1003449193
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.727125361
Short name T558
Test name
Test status
Simulation time 32140482 ps
CPU time 0.87 seconds
Started May 21 02:19:17 PM PDT 24
Finished May 21 02:19:19 PM PDT 24
Peak memory 217948 kb
Host smart-8255efcc-f24f-4345-8cbd-b9bfdae3987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727125361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.727125361
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3446447339
Short name T46
Test name
Test status
Simulation time 122571331 ps
CPU time 1.3 seconds
Started May 21 02:19:17 PM PDT 24
Finished May 21 02:19:19 PM PDT 24
Peak memory 216676 kb
Host smart-08d67279-2be9-45d6-8da9-e76ee579cb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446447339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3446447339
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2286731492
Short name T61
Test name
Test status
Simulation time 29218331 ps
CPU time 1.22 seconds
Started May 21 02:19:24 PM PDT 24
Finished May 21 02:19:26 PM PDT 24
Peak memory 219364 kb
Host smart-08ce38f8-9f5e-4f6c-9619-f4a4b912738b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286731492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2286731492
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1218855262
Short name T562
Test name
Test status
Simulation time 80989478 ps
CPU time 1.12 seconds
Started May 21 02:19:25 PM PDT 24
Finished May 21 02:19:27 PM PDT 24
Peak memory 216700 kb
Host smart-1ad15f6e-e4f0-4058-9b7e-5e0dc9ad4be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218855262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1218855262
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.654414585
Short name T149
Test name
Test status
Simulation time 35325408 ps
CPU time 0.89 seconds
Started May 21 02:19:33 PM PDT 24
Finished May 21 02:19:36 PM PDT 24
Peak memory 218904 kb
Host smart-df460768-f571-42cb-834c-1ffdc46533c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654414585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.654414585
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3619984894
Short name T833
Test name
Test status
Simulation time 47897398 ps
CPU time 1.27 seconds
Started May 21 02:19:28 PM PDT 24
Finished May 21 02:19:30 PM PDT 24
Peak memory 218100 kb
Host smart-850dd2b9-c014-4407-9e7f-3b3b82316c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619984894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3619984894
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1094927150
Short name T557
Test name
Test status
Simulation time 30248558 ps
CPU time 1.27 seconds
Started May 21 02:19:33 PM PDT 24
Finished May 21 02:19:36 PM PDT 24
Peak memory 219284 kb
Host smart-d8826a2d-ba1d-4d8b-875d-b34cc957a457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094927150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1094927150
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1056397204
Short name T503
Test name
Test status
Simulation time 40550563 ps
CPU time 0.93 seconds
Started May 21 02:19:33 PM PDT 24
Finished May 21 02:19:36 PM PDT 24
Peak memory 216696 kb
Host smart-f0d354db-04a4-4aee-baa4-4c2fb06321d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056397204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1056397204
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.472803764
Short name T453
Test name
Test status
Simulation time 59914818 ps
CPU time 0.93 seconds
Started May 21 02:13:16 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 214496 kb
Host smart-21e289d4-d404-45e1-8570-b9737e99dc0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472803764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.472803764
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1319305126
Short name T20
Test name
Test status
Simulation time 54646496 ps
CPU time 1.23 seconds
Started May 21 02:13:15 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 216528 kb
Host smart-770e951a-98ad-4de7-b47d-4a6e2686254d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319305126 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1319305126
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.519277090
Short name T671
Test name
Test status
Simulation time 19352591 ps
CPU time 1.02 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 218336 kb
Host smart-bb73371e-227c-4744-bc3f-f49047a4008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519277090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.519277090
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1420945418
Short name T570
Test name
Test status
Simulation time 59647419 ps
CPU time 1.27 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 216624 kb
Host smart-85db5471-9108-44aa-b199-33195ec0b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420945418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1420945418
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2473485362
Short name T34
Test name
Test status
Simulation time 30330443 ps
CPU time 0.95 seconds
Started May 21 02:13:15 PM PDT 24
Finished May 21 02:13:21 PM PDT 24
Peak memory 215316 kb
Host smart-38dea17a-e40e-4c9f-984c-290ab1737a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473485362 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2473485362
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.597152470
Short name T298
Test name
Test status
Simulation time 29756034 ps
CPU time 1 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:13:23 PM PDT 24
Peak memory 206804 kb
Host smart-9f433cda-ce01-46e4-98b3-8df7f2677063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597152470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.597152470
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1450450888
Short name T373
Test name
Test status
Simulation time 14763795 ps
CPU time 1.01 seconds
Started May 21 02:13:11 PM PDT 24
Finished May 21 02:13:17 PM PDT 24
Peak memory 214976 kb
Host smart-54901701-d747-43c4-9296-1a1dd2632220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450450888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1450450888
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3756679245
Short name T482
Test name
Test status
Simulation time 63549443 ps
CPU time 1.71 seconds
Started May 21 02:13:20 PM PDT 24
Finished May 21 02:13:26 PM PDT 24
Peak memory 216784 kb
Host smart-f246ff97-a96b-43ee-adac-7ee9a75d7895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756679245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3756679245
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1759612021
Short name T395
Test name
Test status
Simulation time 40560952493 ps
CPU time 521.23 seconds
Started May 21 02:13:17 PM PDT 24
Finished May 21 02:22:03 PM PDT 24
Peak memory 221312 kb
Host smart-60fea355-c344-4ee0-9f2c-cc80263e1416
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759612021 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1759612021
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2531464367
Short name T135
Test name
Test status
Simulation time 28083329 ps
CPU time 0.94 seconds
Started May 21 02:19:39 PM PDT 24
Finished May 21 02:19:41 PM PDT 24
Peak memory 223296 kb
Host smart-09153fc0-bba4-43b3-8da3-4ac27f70aeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531464367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2531464367
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3064068446
Short name T817
Test name
Test status
Simulation time 37062255 ps
CPU time 1.38 seconds
Started May 21 02:19:38 PM PDT 24
Finished May 21 02:19:40 PM PDT 24
Peak memory 217952 kb
Host smart-0b6a9a2f-e561-4d31-a591-9801ba4b4154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064068446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3064068446
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1395414715
Short name T758
Test name
Test status
Simulation time 20963511 ps
CPU time 1.17 seconds
Started May 21 02:19:39 PM PDT 24
Finished May 21 02:19:42 PM PDT 24
Peak memory 219380 kb
Host smart-e7e984a9-4aae-4fe4-a569-af6b47ab891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395414715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1395414715
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1052532311
Short name T792
Test name
Test status
Simulation time 232102266 ps
CPU time 1.05 seconds
Started May 21 02:19:39 PM PDT 24
Finished May 21 02:19:41 PM PDT 24
Peak memory 216556 kb
Host smart-c9c1f89e-ff1a-4ace-89b1-959ed2b91112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052532311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1052532311
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.746168021
Short name T505
Test name
Test status
Simulation time 20121212 ps
CPU time 1.2 seconds
Started May 21 02:19:45 PM PDT 24
Finished May 21 02:19:48 PM PDT 24
Peak memory 223496 kb
Host smart-c378afe2-d68f-4f07-843d-398f1b754874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746168021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.746168021
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1019235421
Short name T786
Test name
Test status
Simulation time 48643315 ps
CPU time 1.41 seconds
Started May 21 02:19:47 PM PDT 24
Finished May 21 02:19:49 PM PDT 24
Peak memory 217720 kb
Host smart-cb8da766-0f56-4ce3-a660-db8329b0af08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019235421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1019235421
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_genbits.2624999356
Short name T90
Test name
Test status
Simulation time 91244468 ps
CPU time 1.62 seconds
Started May 21 02:19:45 PM PDT 24
Finished May 21 02:19:48 PM PDT 24
Peak memory 218300 kb
Host smart-912ad9db-0a78-4327-96d0-f9306f337381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624999356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2624999356
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1310194697
Short name T362
Test name
Test status
Simulation time 24750971 ps
CPU time 1.18 seconds
Started May 21 02:19:52 PM PDT 24
Finished May 21 02:19:55 PM PDT 24
Peak memory 219520 kb
Host smart-2c8a74c8-c704-425e-a141-5dc2d925879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310194697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1310194697
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2004000890
Short name T678
Test name
Test status
Simulation time 123527543 ps
CPU time 2.64 seconds
Started May 21 02:19:50 PM PDT 24
Finished May 21 02:19:55 PM PDT 24
Peak memory 218008 kb
Host smart-b24ea022-f9d7-4c25-8eb1-84f5bd804e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004000890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2004000890
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1074731789
Short name T2
Test name
Test status
Simulation time 31417521 ps
CPU time 0.89 seconds
Started May 21 02:19:57 PM PDT 24
Finished May 21 02:19:59 PM PDT 24
Peak memory 218336 kb
Host smart-9f64532b-1172-4050-a353-8671167371b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074731789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1074731789
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.247832449
Short name T48
Test name
Test status
Simulation time 39554037 ps
CPU time 1.81 seconds
Started May 21 02:19:50 PM PDT 24
Finished May 21 02:19:54 PM PDT 24
Peak memory 218108 kb
Host smart-8177f494-1354-496a-8378-dcb677d06784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247832449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.247832449
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.560194746
Short name T578
Test name
Test status
Simulation time 62751761 ps
CPU time 0.99 seconds
Started May 21 02:19:56 PM PDT 24
Finished May 21 02:19:58 PM PDT 24
Peak memory 216692 kb
Host smart-31911eda-b24f-40eb-be83-4abc1dd2e15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560194746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.560194746
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3068302509
Short name T188
Test name
Test status
Simulation time 62596717 ps
CPU time 1.26 seconds
Started May 21 02:20:02 PM PDT 24
Finished May 21 02:20:04 PM PDT 24
Peak memory 224896 kb
Host smart-0c6ffa8a-b15e-4ea6-848b-b919e8909b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068302509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3068302509
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/68.edn_err.3014894061
Short name T81
Test name
Test status
Simulation time 19700618 ps
CPU time 1.04 seconds
Started May 21 02:20:08 PM PDT 24
Finished May 21 02:20:10 PM PDT 24
Peak memory 217928 kb
Host smart-52051946-0c1f-44a7-b15f-3d8c2edd2265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014894061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3014894061
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3924624599
Short name T744
Test name
Test status
Simulation time 91932409 ps
CPU time 1.15 seconds
Started May 21 02:20:02 PM PDT 24
Finished May 21 02:20:04 PM PDT 24
Peak memory 216908 kb
Host smart-19dc1627-c2c9-4f86-91e7-1b54fa1a369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924624599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3924624599
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3790058717
Short name T721
Test name
Test status
Simulation time 27170998 ps
CPU time 0.93 seconds
Started May 21 02:20:14 PM PDT 24
Finished May 21 02:20:15 PM PDT 24
Peak memory 218212 kb
Host smart-2dc490db-878f-4b61-ad24-804c8218a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790058717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3790058717
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3593509807
Short name T755
Test name
Test status
Simulation time 50308861 ps
CPU time 1.2 seconds
Started May 21 02:20:14 PM PDT 24
Finished May 21 02:20:15 PM PDT 24
Peak memory 216960 kb
Host smart-bdde1ac1-1f0b-40ff-95ee-51531ea0c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593509807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3593509807
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.4240304350
Short name T729
Test name
Test status
Simulation time 17730730 ps
CPU time 1 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:35 PM PDT 24
Peak memory 206304 kb
Host smart-8d6a4835-10e2-466e-ae1f-307554ae82c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240304350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4240304350
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3314652961
Short name T624
Test name
Test status
Simulation time 14305016 ps
CPU time 0.92 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:31 PM PDT 24
Peak memory 216060 kb
Host smart-95afdc6d-460b-4416-b9da-24478e067803
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314652961 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3314652961
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1269917977
Short name T763
Test name
Test status
Simulation time 34420225 ps
CPU time 1.18 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 216856 kb
Host smart-df5fe7c1-aee7-4dd8-9a2f-060f6a35f05b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269917977 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1269917977
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3760888187
Short name T136
Test name
Test status
Simulation time 20087867 ps
CPU time 1.18 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 223476 kb
Host smart-a14c13ac-0b11-461c-bf64-22b2a17a9679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760888187 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3760888187
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2325521446
Short name T513
Test name
Test status
Simulation time 96157821 ps
CPU time 1.25 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:33 PM PDT 24
Peak memory 216832 kb
Host smart-b9674031-e50c-403f-acbc-dfebe6dfb852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325521446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2325521446
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2273272299
Short name T632
Test name
Test status
Simulation time 40282503 ps
CPU time 0.93 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 215272 kb
Host smart-c8073c56-8727-41aa-8cb8-80ae5668cb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273272299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2273272299
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3328851773
Short name T301
Test name
Test status
Simulation time 14839341 ps
CPU time 1.07 seconds
Started May 21 02:13:16 PM PDT 24
Finished May 21 02:13:22 PM PDT 24
Peak memory 206772 kb
Host smart-0133c11e-0ee8-46b4-9a31-314e2a80f2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328851773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3328851773
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1583320225
Short name T522
Test name
Test status
Simulation time 18984255 ps
CPU time 1.06 seconds
Started May 21 02:13:18 PM PDT 24
Finished May 21 02:13:24 PM PDT 24
Peak memory 214948 kb
Host smart-5f5350d5-6b92-4069-891b-fb3ce41d524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583320225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1583320225
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2490442343
Short name T708
Test name
Test status
Simulation time 66510902 ps
CPU time 1.93 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 217808 kb
Host smart-e34ac242-0149-4792-b9cc-b2ef63642d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490442343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2490442343
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.282375574
Short name T286
Test name
Test status
Simulation time 637832637463 ps
CPU time 1363.08 seconds
Started May 21 02:13:21 PM PDT 24
Finished May 21 02:36:10 PM PDT 24
Peak memory 224164 kb
Host smart-c543b402-a309-4648-866c-242557a955d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282375574 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.282375574
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.975468659
Short name T735
Test name
Test status
Simulation time 29531974 ps
CPU time 0.89 seconds
Started May 21 02:20:16 PM PDT 24
Finished May 21 02:20:18 PM PDT 24
Peak memory 218112 kb
Host smart-e0251a54-f0fd-4f1b-8ea5-f534d44c6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975468659 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.975468659
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2106772284
Short name T621
Test name
Test status
Simulation time 24891628 ps
CPU time 1.21 seconds
Started May 21 02:20:16 PM PDT 24
Finished May 21 02:20:18 PM PDT 24
Peak memory 216876 kb
Host smart-fc7fcca3-9faf-4f98-87cf-8d2cc4e4ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106772284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2106772284
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3936957754
Short name T455
Test name
Test status
Simulation time 26037435 ps
CPU time 1.24 seconds
Started May 21 02:20:20 PM PDT 24
Finished May 21 02:20:22 PM PDT 24
Peak memory 220384 kb
Host smart-562c640c-3003-4039-a439-7244f6ae9d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936957754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3936957754
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.739239801
Short name T550
Test name
Test status
Simulation time 84994821 ps
CPU time 1.26 seconds
Started May 21 02:20:18 PM PDT 24
Finished May 21 02:20:20 PM PDT 24
Peak memory 214964 kb
Host smart-d1cfe8b7-631d-49e3-a065-2a9355a27f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739239801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.739239801
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.4252621428
Short name T144
Test name
Test status
Simulation time 20737973 ps
CPU time 1.04 seconds
Started May 21 02:20:20 PM PDT 24
Finished May 21 02:20:22 PM PDT 24
Peak memory 217956 kb
Host smart-aef48aa3-7df1-47d9-9b7b-ba000bc2d4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252621428 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.4252621428
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2016161350
Short name T398
Test name
Test status
Simulation time 30630785 ps
CPU time 1.64 seconds
Started May 21 02:20:21 PM PDT 24
Finished May 21 02:20:23 PM PDT 24
Peak memory 216896 kb
Host smart-7fa183ab-0f52-4be3-8824-a63b1a1044c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016161350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2016161350
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2394691338
Short name T15
Test name
Test status
Simulation time 41658245 ps
CPU time 1.25 seconds
Started May 21 02:20:26 PM PDT 24
Finished May 21 02:20:28 PM PDT 24
Peak memory 225252 kb
Host smart-d8b02113-d99d-44b4-8b4e-d2ac4f9c1b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394691338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2394691338
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2094311431
Short name T662
Test name
Test status
Simulation time 177232217 ps
CPU time 1.24 seconds
Started May 21 02:20:27 PM PDT 24
Finished May 21 02:20:29 PM PDT 24
Peak memory 216624 kb
Host smart-4b24383e-97fa-42e2-bc44-257186da9f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094311431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2094311431
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2549506537
Short name T341
Test name
Test status
Simulation time 26657476 ps
CPU time 1.03 seconds
Started May 21 02:20:25 PM PDT 24
Finished May 21 02:20:27 PM PDT 24
Peak memory 219692 kb
Host smart-d8b57cd1-e911-4523-baa0-f127aaa81dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549506537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2549506537
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1196015015
Short name T370
Test name
Test status
Simulation time 47781311 ps
CPU time 1.54 seconds
Started May 21 02:20:28 PM PDT 24
Finished May 21 02:20:30 PM PDT 24
Peak memory 217668 kb
Host smart-00ef390f-127a-43be-8681-6f3bdc7022c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196015015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1196015015
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1020005606
Short name T150
Test name
Test status
Simulation time 30201748 ps
CPU time 0.91 seconds
Started May 21 02:20:30 PM PDT 24
Finished May 21 02:20:32 PM PDT 24
Peak memory 218824 kb
Host smart-71f58750-7484-4c01-9e56-a847b69b5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020005606 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1020005606
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1895418740
Short name T441
Test name
Test status
Simulation time 70055151 ps
CPU time 2.7 seconds
Started May 21 02:20:31 PM PDT 24
Finished May 21 02:20:35 PM PDT 24
Peak memory 218928 kb
Host smart-b0fe431a-b84a-4f51-8d00-7f157baa0373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895418740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1895418740
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3842403223
Short name T130
Test name
Test status
Simulation time 18795462 ps
CPU time 1.06 seconds
Started May 21 02:20:33 PM PDT 24
Finished May 21 02:20:35 PM PDT 24
Peak memory 218036 kb
Host smart-90ab78fc-462e-41e0-b9c8-17982ab83560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842403223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3842403223
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3154501328
Short name T500
Test name
Test status
Simulation time 40635757 ps
CPU time 1.78 seconds
Started May 21 02:20:31 PM PDT 24
Finished May 21 02:20:33 PM PDT 24
Peak memory 218060 kb
Host smart-8d803583-56af-4036-8a22-1a9870c0dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154501328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3154501328
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.368250624
Short name T197
Test name
Test status
Simulation time 20549106 ps
CPU time 1.11 seconds
Started May 21 02:20:44 PM PDT 24
Finished May 21 02:20:46 PM PDT 24
Peak memory 223412 kb
Host smart-612dad62-c4b1-430d-8445-2f75414984fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368250624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.368250624
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.1333741024
Short name T55
Test name
Test status
Simulation time 18802690 ps
CPU time 1.17 seconds
Started May 21 02:20:44 PM PDT 24
Finished May 21 02:20:47 PM PDT 24
Peak memory 223432 kb
Host smart-9a75daed-b636-4b52-81de-5c752771f546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333741024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1333741024
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.357759153
Short name T308
Test name
Test status
Simulation time 55623420 ps
CPU time 1.27 seconds
Started May 21 02:20:44 PM PDT 24
Finished May 21 02:20:47 PM PDT 24
Peak memory 219220 kb
Host smart-d4f693c1-48de-4df7-80e8-1dd948753848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357759153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.357759153
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3231724005
Short name T225
Test name
Test status
Simulation time 89194646 ps
CPU time 1.29 seconds
Started May 21 02:20:44 PM PDT 24
Finished May 21 02:20:47 PM PDT 24
Peak memory 225200 kb
Host smart-24e8583b-dccb-4ef0-967a-1bccff0ed986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231724005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3231724005
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.568171312
Short name T364
Test name
Test status
Simulation time 65288799 ps
CPU time 1.41 seconds
Started May 21 02:20:44 PM PDT 24
Finished May 21 02:20:47 PM PDT 24
Peak memory 218936 kb
Host smart-0270bdad-413b-4748-8e5e-8261aabb855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568171312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.568171312
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.4071678751
Short name T299
Test name
Test status
Simulation time 101928456 ps
CPU time 1.21 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 215356 kb
Host smart-9dcc45b6-416e-44cc-a6aa-da739ae722ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071678751 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.4071678751
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1997741977
Short name T683
Test name
Test status
Simulation time 82043897 ps
CPU time 0.8 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 206012 kb
Host smart-a27acc4f-1036-429b-a74c-44eec7cecf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997741977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1997741977
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_err.2184978859
Short name T148
Test name
Test status
Simulation time 23260393 ps
CPU time 1.09 seconds
Started May 21 02:13:24 PM PDT 24
Finished May 21 02:13:32 PM PDT 24
Peak memory 229000 kb
Host smart-97bffa89-a492-4535-bffe-fc0e9e2db131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184978859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2184978859
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1432011614
Short name T546
Test name
Test status
Simulation time 63451973 ps
CPU time 1.29 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:29 PM PDT 24
Peak memory 217908 kb
Host smart-de0ee5af-283b-439e-8e4b-9c4c96547e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432011614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1432011614
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1069088171
Short name T59
Test name
Test status
Simulation time 45647441 ps
CPU time 0.98 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 223424 kb
Host smart-3626f36e-79db-4000-b9c2-d0a2ff1d1d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069088171 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1069088171
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.847945323
Short name T783
Test name
Test status
Simulation time 38233345 ps
CPU time 0.91 seconds
Started May 21 02:13:22 PM PDT 24
Finished May 21 02:13:28 PM PDT 24
Peak memory 215004 kb
Host smart-e802d2ae-3c14-4c0c-a962-e0ab7be4c920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847945323 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.847945323
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2563333185
Short name T53
Test name
Test status
Simulation time 834947893 ps
CPU time 5.21 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 214980 kb
Host smart-331882ec-11dc-4006-9829-0100d19a18ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563333185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2563333185
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2308123043
Short name T205
Test name
Test status
Simulation time 117873114053 ps
CPU time 1999.61 seconds
Started May 21 02:13:23 PM PDT 24
Finished May 21 02:46:50 PM PDT 24
Peak memory 229244 kb
Host smart-c0be140a-967d-462e-9321-caeae5d2c4b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308123043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2308123043
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3183886690
Short name T665
Test name
Test status
Simulation time 32408884 ps
CPU time 0.99 seconds
Started May 21 02:20:55 PM PDT 24
Finished May 21 02:20:57 PM PDT 24
Peak memory 223296 kb
Host smart-3787d939-065e-4a14-b86a-78f25034abc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183886690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3183886690
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2771142175
Short name T23
Test name
Test status
Simulation time 55331910 ps
CPU time 1.18 seconds
Started May 21 02:20:50 PM PDT 24
Finished May 21 02:20:52 PM PDT 24
Peak memory 216548 kb
Host smart-fa101873-43ee-43e0-b18c-c694b1b71b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771142175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2771142175
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2879674453
Short name T566
Test name
Test status
Simulation time 50586758 ps
CPU time 1.29 seconds
Started May 21 02:20:58 PM PDT 24
Finished May 21 02:21:00 PM PDT 24
Peak memory 225148 kb
Host smart-5dca9528-ddfc-45d2-a9ba-e59fe39f2720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879674453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2879674453
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2604696899
Short name T314
Test name
Test status
Simulation time 33560399 ps
CPU time 1.32 seconds
Started May 21 02:20:57 PM PDT 24
Finished May 21 02:20:59 PM PDT 24
Peak memory 216628 kb
Host smart-ed036b8f-e207-4abd-964e-d96f75e0c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604696899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2604696899
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1682813352
Short name T800
Test name
Test status
Simulation time 72711542 ps
CPU time 1.06 seconds
Started May 21 02:21:02 PM PDT 24
Finished May 21 02:21:04 PM PDT 24
Peak memory 218540 kb
Host smart-94d438b1-4203-444b-8841-4cefdd8e05a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682813352 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1682813352
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3289311911
Short name T1
Test name
Test status
Simulation time 28392697 ps
CPU time 1.15 seconds
Started May 21 02:20:55 PM PDT 24
Finished May 21 02:20:57 PM PDT 24
Peak memory 216572 kb
Host smart-e6bcf460-3f6a-4760-a53d-1f10d132bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289311911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3289311911
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1387094884
Short name T529
Test name
Test status
Simulation time 59721382 ps
CPU time 1.21 seconds
Started May 21 02:21:09 PM PDT 24
Finished May 21 02:21:11 PM PDT 24
Peak memory 214868 kb
Host smart-c7b13fdf-3ab7-40a3-b08d-13ec55d91c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387094884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1387094884
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2750478132
Short name T312
Test name
Test status
Simulation time 24416922 ps
CPU time 1.18 seconds
Started May 21 02:21:02 PM PDT 24
Finished May 21 02:21:05 PM PDT 24
Peak memory 219220 kb
Host smart-93c87c86-9ba8-44d0-a2af-0b1fc4d96fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750478132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2750478132
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1599369266
Short name T82
Test name
Test status
Simulation time 49049647 ps
CPU time 0.83 seconds
Started May 21 02:21:08 PM PDT 24
Finished May 21 02:21:10 PM PDT 24
Peak memory 214784 kb
Host smart-b6377ee7-91d3-4276-aaf1-b2486bb3e18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599369266 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1599369266
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.388705820
Short name T664
Test name
Test status
Simulation time 51510881 ps
CPU time 1.46 seconds
Started May 21 02:21:07 PM PDT 24
Finished May 21 02:21:09 PM PDT 24
Peak memory 217852 kb
Host smart-40092c77-48c8-4461-ac87-2da43d0b8db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388705820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.388705820
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3622935388
Short name T58
Test name
Test status
Simulation time 137831210 ps
CPU time 1.16 seconds
Started May 21 02:21:11 PM PDT 24
Finished May 21 02:21:14 PM PDT 24
Peak memory 224960 kb
Host smart-827359d7-4a8d-47f1-8307-2d3668aafb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622935388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3622935388
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3013898330
Short name T494
Test name
Test status
Simulation time 32759275 ps
CPU time 1.28 seconds
Started May 21 02:21:13 PM PDT 24
Finished May 21 02:21:15 PM PDT 24
Peak memory 216584 kb
Host smart-cfbf5c33-79ac-4b0d-ab5d-1b1cf788cd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013898330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3013898330
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.968394870
Short name T141
Test name
Test status
Simulation time 35845466 ps
CPU time 0.83 seconds
Started May 21 02:21:19 PM PDT 24
Finished May 21 02:21:21 PM PDT 24
Peak memory 217776 kb
Host smart-1352401a-d190-4c2c-8baf-ca39fac75582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968394870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.968394870
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.507180279
Short name T590
Test name
Test status
Simulation time 214295256 ps
CPU time 1.39 seconds
Started May 21 02:21:19 PM PDT 24
Finished May 21 02:21:22 PM PDT 24
Peak memory 218064 kb
Host smart-e0aa148b-649e-4867-a132-f1cd41508fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507180279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.507180279
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3155170179
Short name T193
Test name
Test status
Simulation time 18188592 ps
CPU time 1.05 seconds
Started May 21 02:21:25 PM PDT 24
Finished May 21 02:21:27 PM PDT 24
Peak memory 218228 kb
Host smart-bf82ef3d-7804-48a1-a861-1178d0357238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155170179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3155170179
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.95854118
Short name T564
Test name
Test status
Simulation time 59625420 ps
CPU time 1.56 seconds
Started May 21 02:21:22 PM PDT 24
Finished May 21 02:21:24 PM PDT 24
Peak memory 216732 kb
Host smart-d3aa3023-2513-42cc-a12f-4a0fb5b5c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95854118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.95854118
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3740629386
Short name T192
Test name
Test status
Simulation time 30246198 ps
CPU time 1.35 seconds
Started May 21 02:21:24 PM PDT 24
Finished May 21 02:21:26 PM PDT 24
Peak memory 225268 kb
Host smart-44b59230-b5d5-4417-bee3-010da983627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740629386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3740629386
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1373055137
Short name T828
Test name
Test status
Simulation time 43311393 ps
CPU time 1.25 seconds
Started May 21 02:21:24 PM PDT 24
Finished May 21 02:21:27 PM PDT 24
Peak memory 218200 kb
Host smart-eb013b4d-db8c-46c1-b3df-dec774a10f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373055137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1373055137
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3075744817
Short name T153
Test name
Test status
Simulation time 99554130 ps
CPU time 0.85 seconds
Started May 21 02:21:32 PM PDT 24
Finished May 21 02:21:34 PM PDT 24
Peak memory 218972 kb
Host smart-cd762c6a-9628-450a-b4d0-46974ee122c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075744817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3075744817
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2650784644
Short name T619
Test name
Test status
Simulation time 23762620 ps
CPU time 1.11 seconds
Started May 21 02:21:27 PM PDT 24
Finished May 21 02:21:28 PM PDT 24
Peak memory 216660 kb
Host smart-f602ae38-f3c9-4da1-8f8f-b8f194ce9be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650784644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2650784644
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.2948838257
Short name T50
Test name
Test status
Simulation time 32089471 ps
CPU time 1.36 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:42 PM PDT 24
Peak memory 215368 kb
Host smart-3e47f4a8-61af-43ed-91ce-5cdd0b577b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948838257 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2948838257
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1163873616
Short name T528
Test name
Test status
Simulation time 16813216 ps
CPU time 0.97 seconds
Started May 21 02:13:30 PM PDT 24
Finished May 21 02:13:41 PM PDT 24
Peak memory 214504 kb
Host smart-b3749436-3a9d-4a03-aef2-fa53f9891a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163873616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1163873616
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3625569219
Short name T456
Test name
Test status
Simulation time 31829481 ps
CPU time 0.87 seconds
Started May 21 02:13:28 PM PDT 24
Finished May 21 02:13:40 PM PDT 24
Peak memory 215624 kb
Host smart-152a793b-fcc2-4a0c-a511-0b2154562e47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625569219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3625569219
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4140771598
Short name T101
Test name
Test status
Simulation time 54641127 ps
CPU time 1.59 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 216444 kb
Host smart-014c5c80-3919-4dca-9656-2661ea1deb12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140771598 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4140771598
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1083584386
Short name T139
Test name
Test status
Simulation time 22942945 ps
CPU time 0.94 seconds
Started May 21 02:13:31 PM PDT 24
Finished May 21 02:13:43 PM PDT 24
Peak memory 218152 kb
Host smart-edafaf5e-986f-4c2f-ab88-d6f29795b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083584386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1083584386
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.479916117
Short name T439
Test name
Test status
Simulation time 32358466 ps
CPU time 1.48 seconds
Started May 21 02:13:33 PM PDT 24
Finished May 21 02:13:45 PM PDT 24
Peak memory 217820 kb
Host smart-7fe43237-9b37-4d26-8e69-f76a0a3af8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479916117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.479916117
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1014296377
Short name T158
Test name
Test status
Simulation time 22427107 ps
CPU time 0.95 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 215440 kb
Host smart-f50516e3-c692-452e-800f-069effc804d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014296377 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1014296377
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3797671105
Short name T819
Test name
Test status
Simulation time 19320380 ps
CPU time 1 seconds
Started May 21 02:13:27 PM PDT 24
Finished May 21 02:13:38 PM PDT 24
Peak memory 206792 kb
Host smart-83789604-de70-4a60-b82d-b9e06d418084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797671105 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3797671105
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3212818843
Short name T320
Test name
Test status
Simulation time 18539605 ps
CPU time 0.98 seconds
Started May 21 02:13:25 PM PDT 24
Finished May 21 02:13:34 PM PDT 24
Peak memory 215016 kb
Host smart-bfb8b803-29da-4b9e-a1b9-fa9b59b195d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212818843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3212818843
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.621961547
Short name T772
Test name
Test status
Simulation time 433995242 ps
CPU time 4.58 seconds
Started May 21 02:13:29 PM PDT 24
Finished May 21 02:13:44 PM PDT 24
Peak memory 216664 kb
Host smart-d4d134ad-ee16-403b-903a-b97a0204e17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621961547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.621961547
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2999368212
Short name T38
Test name
Test status
Simulation time 467456808438 ps
CPU time 1802.89 seconds
Started May 21 02:13:32 PM PDT 24
Finished May 21 02:43:46 PM PDT 24
Peak memory 227612 kb
Host smart-48973634-6802-452e-8722-41ab4cda2646
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999368212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2999368212
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2776319090
Short name T470
Test name
Test status
Simulation time 20377129 ps
CPU time 1.1 seconds
Started May 21 02:21:30 PM PDT 24
Finished May 21 02:21:33 PM PDT 24
Peak memory 219412 kb
Host smart-5676169c-865e-416b-90a7-aa17ccf0aa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776319090 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2776319090
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1486199054
Short name T406
Test name
Test status
Simulation time 70705880 ps
CPU time 1.76 seconds
Started May 21 02:21:31 PM PDT 24
Finished May 21 02:21:33 PM PDT 24
Peak memory 219780 kb
Host smart-345bb0ce-10b9-48c8-8119-c609badb20f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486199054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1486199054
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.585360676
Short name T127
Test name
Test status
Simulation time 18803760 ps
CPU time 1.02 seconds
Started May 21 02:21:38 PM PDT 24
Finished May 21 02:21:40 PM PDT 24
Peak memory 217848 kb
Host smart-fae1cdbd-2872-4a45-aba8-44bc23552812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585360676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.585360676
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2776762628
Short name T734
Test name
Test status
Simulation time 73754077 ps
CPU time 1.21 seconds
Started May 21 02:21:38 PM PDT 24
Finished May 21 02:21:40 PM PDT 24
Peak memory 218052 kb
Host smart-23bdd45b-4335-47b7-b305-fd3048ac34cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776762628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2776762628
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2491763791
Short name T106
Test name
Test status
Simulation time 25481414 ps
CPU time 1.22 seconds
Started May 21 02:21:44 PM PDT 24
Finished May 21 02:21:46 PM PDT 24
Peak memory 220248 kb
Host smart-4068a035-6db2-4a20-805f-950038ce6d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491763791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2491763791
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1575463545
Short name T846
Test name
Test status
Simulation time 84590127 ps
CPU time 1.43 seconds
Started May 21 02:21:42 PM PDT 24
Finished May 21 02:21:44 PM PDT 24
Peak memory 218012 kb
Host smart-09eb5872-8189-4785-9439-b987c8a5518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575463545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1575463545
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2400883950
Short name T841
Test name
Test status
Simulation time 37944624 ps
CPU time 0.96 seconds
Started May 21 02:21:43 PM PDT 24
Finished May 21 02:21:45 PM PDT 24
Peak memory 219644 kb
Host smart-ee46601e-ce30-4631-9421-4c7e6358c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400883950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2400883950
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1500166061
Short name T823
Test name
Test status
Simulation time 47898604 ps
CPU time 1.3 seconds
Started May 21 02:21:42 PM PDT 24
Finished May 21 02:21:44 PM PDT 24
Peak memory 217848 kb
Host smart-f074510e-14ea-4f53-8bb7-0c16810cb334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500166061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1500166061
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.701153763
Short name T114
Test name
Test status
Simulation time 29728809 ps
CPU time 1.3 seconds
Started May 21 02:21:49 PM PDT 24
Finished May 21 02:21:51 PM PDT 24
Peak memory 229376 kb
Host smart-223d65d4-28e0-41ce-914c-8881ba08f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701153763 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.701153763
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/95.edn_err.125703918
Short name T349
Test name
Test status
Simulation time 33122056 ps
CPU time 0.88 seconds
Started May 21 02:21:54 PM PDT 24
Finished May 21 02:21:57 PM PDT 24
Peak memory 217824 kb
Host smart-cc28592f-50f7-42af-b49e-63b92d686ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125703918 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.125703918
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.614833088
Short name T843
Test name
Test status
Simulation time 52658105 ps
CPU time 1.85 seconds
Started May 21 02:21:55 PM PDT 24
Finished May 21 02:21:58 PM PDT 24
Peak memory 217700 kb
Host smart-769d48c0-cdc5-4f9b-b75d-bbda25a89161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614833088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.614833088
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2822216855
Short name T111
Test name
Test status
Simulation time 20603423 ps
CPU time 1.21 seconds
Started May 21 02:22:01 PM PDT 24
Finished May 21 02:22:03 PM PDT 24
Peak memory 219284 kb
Host smart-cd619f6c-265f-4bd0-8219-fdd05c1f673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822216855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2822216855
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.330050588
Short name T449
Test name
Test status
Simulation time 48334950 ps
CPU time 1.6 seconds
Started May 21 02:22:02 PM PDT 24
Finished May 21 02:22:04 PM PDT 24
Peak memory 217696 kb
Host smart-9576ffcc-9dcd-46d7-b7f0-6954de87c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330050588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.330050588
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2375324342
Short name T422
Test name
Test status
Simulation time 114824379 ps
CPU time 0.95 seconds
Started May 21 02:22:07 PM PDT 24
Finished May 21 02:22:08 PM PDT 24
Peak memory 218156 kb
Host smart-10923cd2-ffc1-42fb-b6b2-4f3b3929365a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375324342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2375324342
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2153608648
Short name T155
Test name
Test status
Simulation time 86817854 ps
CPU time 1.12 seconds
Started May 21 02:22:10 PM PDT 24
Finished May 21 02:22:12 PM PDT 24
Peak memory 219480 kb
Host smart-7383bea7-8b4b-4b05-9d44-6bdb962cfd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153608648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2153608648
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1757270851
Short name T178
Test name
Test status
Simulation time 20767753 ps
CPU time 1.16 seconds
Started May 21 02:22:05 PM PDT 24
Finished May 21 02:22:07 PM PDT 24
Peak memory 219524 kb
Host smart-7d3a8bdc-ce88-4e38-a5f5-779869082dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757270851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1757270851
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/99.edn_err.1465400030
Short name T7
Test name
Test status
Simulation time 19310586 ps
CPU time 1.11 seconds
Started May 21 02:22:16 PM PDT 24
Finished May 21 02:22:18 PM PDT 24
Peak memory 218128 kb
Host smart-edadf589-a556-40c6-88e5-4ac0ac08f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465400030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1465400030
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.639443084
Short name T680
Test name
Test status
Simulation time 102080937 ps
CPU time 1.28 seconds
Started May 21 02:22:14 PM PDT 24
Finished May 21 02:22:17 PM PDT 24
Peak memory 217004 kb
Host smart-3e31a558-f71b-4fb9-9dab-2ab71c9c6956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639443084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.639443084
Directory /workspace/99.edn_genbits/latest
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