Unified Coverage Report :: Cond split page

Go back

 LINE       292
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
             ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T20,T10
1	1	Covered	T1,T3,T4

 LINE       297
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T5,T6,T76
0	0	0	1	0	Covered	T6,T105,T8
0	0	1	0	0	Covered	T6,T14,T7
0	1	0	0	0	Covered	T6,T15,T16
1	0	0	0	0	Covered	T6,T15,T16

 LINE       304
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T14
1	0	Covered	T111,T112,T110

 LINE       304
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T111
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T15,T111

 LINE       304
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T15,T111
1	0	Covered	T6,T15,T110

 LINE       310
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T15,T110

 LINE       312
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T15,T111

 LINE       314
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T6,T14

 LINE       316
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T5,T6,T14

 LINE       318
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6,T14,T7

 LINE       321
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T112
1	0	0	Covered	T113,T114,T143

 LINE       325
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T141,T142
1	0	0	Covered	T110,T115,T116

 LINE       329
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T6,T15,T111
1	0	0	Covered	T6,T15,T113

 LINE       337
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T110
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T15,T110

 LINE       340
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T111
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T15,T111

 LINE       357
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T112,T113,T114
1	0	Covered	T1,T3,T4
1	1	Covered	T112,T113,T114

 LINE       360
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T110,T115,T116
1	0	Covered	T1,T3,T4
1	1	Covered	T110,T115,T116

 LINE       363
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T15,T111
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T15,T111

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T103,T117
1	1	Covered	T4,T103,T117

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T103,T117

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T117,T75
1	1	Covered	T4,T117,T75

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T117,T75

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T55,T118
1	1	Covered	T4,T55,T118

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T55,T118

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T14,T117
1	1	Covered	T4,T14,T117

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T14,T117

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T13,T144,T62
1	1	Covered	T13,T144,T62

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T144,T62

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T145,T146
1	1	Covered	T4,T145,T146

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T145,T146

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T103,T17
1	1	Covered	T4,T103,T17

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T103,T17

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T117,T7
1	1	Covered	T4,T117,T7

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T117,T7

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T117,T8,T147
1	1	Covered	T117,T8,T147

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T117,T8,T147

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T19,T10
1	0	Covered	T3,T24,T22
1	1	Covered	T3,T24,T22

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T24,T22

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T117,T118
1	1	Covered	T4,T117,T118

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T117,T118

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T118,T148
1	1	Covered	T4,T118,T148

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T118,T148

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T120,T149
1	1	Covered	T4,T120,T149

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T120,T149

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T117,T118
1	1	Covered	T4,T117,T118

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T117,T118

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T118,T127
1	1	Covered	T4,T118,T127

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T118,T127

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T103,T147,T150
1	1	Covered	T103,T147,T150

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T147,T150

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T17,T56
1	1	Covered	T4,T17,T56

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T17,T56

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T21,T117
1	1	Covered	T4,T21,T117

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T21,T117

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T103,T117,T55
1	1	Covered	T103,T117,T55

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T117,T55

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T10,T151,T122
1	1	Covered	T10,T151,T122

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T151,T122

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T23,T117
1	1	Covered	T4,T23,T117

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T23,T117

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T4,T117,T8
1	1	Covered	T4,T117,T8

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T117,T8

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Covered	T86,T117,T118
1	1	Covered	T86,T117,T118

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T86,T117,T118

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       368
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T19
1	0	Not Covered
1	1	Not Covered

 LINE       368
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       372
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
             -------------1------------    ------------2------------    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T20,T26,T27

 LINE       372
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T26,T27

 LINE       378
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T20,T26,T27
0	0	0	0	1	0	Covered	T27,T69,T71
0	0	0	1	0	0	Covered	T99,T152,T100
0	0	1	0	0	0	Covered	T20,T26,T32
0	1	0	0	0	0	Covered	T153,T77,T154
1	0	0	0	0	0	Covered	T20,T26,T27

 LINE       397
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T5,T6,T14

 LINE       400
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T155,T156
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T155,T156

 LINE       404
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T155,T156
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T155,T156

 LINE       480
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T11,T18
1	1	Covered	T1,T3,T4

 LINE       492
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       493
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T10,T11

 LINE       494
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T11
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T10,T11

 LINE       497
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       497
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T14,T24

 LINE       497
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T14,T24

 LINE       497
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T28,T29

 LINE       497
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       506
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       506
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       506
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       506
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T3,T4
0	0	0	1	Covered	T20,T28,T29
0	0	1	0	Covered	T20,T14,T24
0	1	0	0	Covered	T20,T14,T24
1	0	0	0	Covered	T1,T3,T4

 LINE       513
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       517
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       517
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T3,T10,T11

 LINE       517
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       517
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       533
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       533
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       533
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       533
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       533
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       533
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       533
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       548
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       552
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       552
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T5,T6

 LINE       552
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       552
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       552
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       563
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       563
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T5,T6

 LINE       563
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       563
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       563
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       574
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       574
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       574
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T20,T10
1	1	Covered	T1,T3,T4

 LINE       582
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q)))
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       582
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       582
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_sw_cmd_ack_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       582
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T20,T10
1	1	Covered	T1,T3,T4

 LINE       594
 EXPRESSION ((main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts]))) ? 1'b0 : (boot_wr_ins_cmd ? 1'b1 : boot_mode_q))
             --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       594
 SUB-EXPRESSION (main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts])))
                 ---------1--------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       594
 SUB-EXPRESSION (boot_wr_ins_cmd ? 1'b1 : boot_mode_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T20,T14,T24

 LINE       600
 EXPRESSION ((main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts]))) ? 1'b0 : (auto_req_mode_busy ? 1'b1 : auto_mode_q))
             --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       600
 SUB-EXPRESSION (main_sm_done_pulse || ((!edn_enable_fo[HwCmdSts])))
                 ---------1--------    --------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4

 LINE       600
 SUB-EXPRESSION (auto_req_mode_busy ? 1'b1 : auto_mode_q)
                 ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T10,T11

 LINE       607
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? CMD_STS_SUCCESS : (sw_cmd_valid ? csrng_hw_cmd_sts_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       607
 SUB-EXPRESSION 
 Number  Term
      1  sw_cmd_valid ? csrng_hw_cmd_sts_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T3,T4

 LINE       607
 SUB-EXPRESSION 
 Number  Term
      1  (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T20,T10

 LINE       607
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 ----------1---------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T20,T10
1	1	Covered	T3,T20,T10

 LINE       607
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)) ? csrng_cmd_i.csrng_rsp_sts : csrng_hw_cmd_sts_q)
                 --------------------------------------1--------------------------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T20,T26,T27

 LINE       607
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
                 ------------1------------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T20,T10
1	1	Covered	T20,T26,T27

 LINE       607
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T20,T26,T27

 LINE       618
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? 1'b0 : (sw_cmd_valid ? csrng_hw_cmd_ack_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       618
 SUB-EXPRESSION 
 Number  Term
      1  sw_cmd_valid ? csrng_hw_cmd_ack_q : ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q)))

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T3,T4

 LINE       618
 SUB-EXPRESSION ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? 1'b0 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q))
                 --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T20,T10

 LINE       618
 SUB-EXPRESSION (cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 ----------1---------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T3,T20,T10
1	1	Covered	T3,T20,T10

 LINE       618
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : csrng_hw_cmd_ack_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T3,T20,T10

 LINE       628
 EXPRESSION ((edn_enable_fo[HwCmdSts] && ((!sw_cmd_valid)) && cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready) ? cs_cmd_req_out_q[3:0] : cmd_type_q)
             --------------------------------------------------1--------------------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T20,T10

 LINE       628
 SUB-EXPRESSION (edn_enable_fo[HwCmdSts] && ((!sw_cmd_valid)) && cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)
                 -----------1-----------    --------2--------    ----------3---------    -------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T14,T56,T75
1	0	1	1	Covered	T1,T3,T4
1	1	0	1	Covered	T3,T5,T6
1	1	1	0	Covered	T3,T20,T10
1	1	1	1	Covered	T3,T20,T10

 LINE       655
 EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       655
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       657
 EXPRESSION (rescmd_handshake ? 1'b1 : reseed_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       661
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       665
 EXPRESSION ((rescmd_handshake && ((!cmd_sent))) || capt_rescmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T17

 LINE       665
 SUB-EXPRESSION (rescmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T17

 LINE       667
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T5,T20

 LINE       669
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T9,T44,T140
1	0	Covered	T3,T10,T14
1	1	Covered	T113,T114,T143

 LINE       669
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T110,T115,T116

 LINE       669
 SUB-EXPRESSION ((sfifo_rescmd_full && ((!sfifo_rescmd_not_empty))) || sfifo_rescmd_int_err)
                 -------------------------1------------------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T15,T16
1	0	Covered	T113,T157,T114

 LINE       669
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T9,T44,T140
1	1	Covered	T113,T157,T114

 LINE       698
 EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       698
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11

 LINE       700
 EXPRESSION (gencmd_handshake ? 1'b1 : generate_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       704
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T10,T11

 LINE       708
 EXPRESSION ((gencmd_handshake && ((!cmd_sent))) || capt_gencmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T10,T11
1	0	Covered	T3,T10,T11