Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.41 98.24 93.80 97.02 84.30 96.62 99.77 91.12


Total test records in report: 980
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T785 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1703817366 May 23 02:50:49 PM PDT 24 May 23 03:11:30 PM PDT 24 53018877286 ps
T786 /workspace/coverage/default/46.edn_disable_auto_req_mode.660385659 May 23 02:52:50 PM PDT 24 May 23 02:52:53 PM PDT 24 27513931 ps
T787 /workspace/coverage/default/9.edn_alert_test.390479220 May 23 02:50:51 PM PDT 24 May 23 02:50:56 PM PDT 24 18310809 ps
T788 /workspace/coverage/default/28.edn_stress_all.410845694 May 23 02:51:46 PM PDT 24 May 23 02:51:52 PM PDT 24 1944535655 ps
T789 /workspace/coverage/default/0.edn_intr.493002898 May 23 02:49:56 PM PDT 24 May 23 02:49:59 PM PDT 24 41220584 ps
T790 /workspace/coverage/default/47.edn_disable.4087163390 May 23 02:52:49 PM PDT 24 May 23 02:52:51 PM PDT 24 34783385 ps
T174 /workspace/coverage/default/16.edn_disable_auto_req_mode.1619375663 May 23 02:51:05 PM PDT 24 May 23 02:51:08 PM PDT 24 55593512 ps
T791 /workspace/coverage/default/19.edn_err.1331679393 May 23 02:51:19 PM PDT 24 May 23 02:51:23 PM PDT 24 23719415 ps
T792 /workspace/coverage/default/117.edn_genbits.1384450139 May 23 02:53:33 PM PDT 24 May 23 02:53:36 PM PDT 24 183065212 ps
T793 /workspace/coverage/default/131.edn_genbits.3354893425 May 23 02:53:49 PM PDT 24 May 23 02:53:54 PM PDT 24 56899867 ps
T794 /workspace/coverage/default/34.edn_stress_all.3633584166 May 23 02:52:05 PM PDT 24 May 23 02:52:18 PM PDT 24 196447276 ps
T795 /workspace/coverage/default/160.edn_genbits.1046415444 May 23 02:53:47 PM PDT 24 May 23 02:53:51 PM PDT 24 400898482 ps
T796 /workspace/coverage/default/39.edn_intr.2299247271 May 23 02:52:16 PM PDT 24 May 23 02:52:24 PM PDT 24 29106698 ps
T797 /workspace/coverage/default/6.edn_disable.1848591416 May 23 02:50:29 PM PDT 24 May 23 02:50:32 PM PDT 24 23240790 ps
T798 /workspace/coverage/default/0.edn_smoke.380777499 May 23 02:49:39 PM PDT 24 May 23 02:49:42 PM PDT 24 17778186 ps
T799 /workspace/coverage/default/113.edn_genbits.353217871 May 23 02:53:35 PM PDT 24 May 23 02:53:38 PM PDT 24 44306410 ps
T800 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3612866921 May 23 02:51:47 PM PDT 24 May 23 03:26:09 PM PDT 24 368324876728 ps
T801 /workspace/coverage/default/40.edn_alert_test.1278115160 May 23 02:52:30 PM PDT 24 May 23 02:52:33 PM PDT 24 29416972 ps
T802 /workspace/coverage/default/86.edn_genbits.233248323 May 23 02:53:18 PM PDT 24 May 23 02:53:20 PM PDT 24 67183429 ps
T803 /workspace/coverage/default/152.edn_genbits.271643600 May 23 02:53:46 PM PDT 24 May 23 02:53:49 PM PDT 24 37757338 ps
T804 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3986067895 May 23 02:51:03 PM PDT 24 May 23 03:16:14 PM PDT 24 67339728548 ps
T805 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.721119481 May 23 02:50:26 PM PDT 24 May 23 03:15:26 PM PDT 24 229056117445 ps
T806 /workspace/coverage/default/185.edn_genbits.3523082720 May 23 02:54:01 PM PDT 24 May 23 02:54:06 PM PDT 24 82564689 ps
T807 /workspace/coverage/default/45.edn_disable_auto_req_mode.3182400321 May 23 02:52:51 PM PDT 24 May 23 02:52:55 PM PDT 24 31241309 ps
T808 /workspace/coverage/default/38.edn_disable.1616360556 May 23 02:52:17 PM PDT 24 May 23 02:52:24 PM PDT 24 23899865 ps
T275 /workspace/coverage/default/206.edn_genbits.1913482649 May 23 02:54:05 PM PDT 24 May 23 02:54:11 PM PDT 24 37586682 ps
T809 /workspace/coverage/default/7.edn_alert.3849702420 May 23 02:50:27 PM PDT 24 May 23 02:50:30 PM PDT 24 96215423 ps
T810 /workspace/coverage/default/7.edn_smoke.3815741499 May 23 02:50:27 PM PDT 24 May 23 02:50:29 PM PDT 24 18788660 ps
T811 /workspace/coverage/default/18.edn_smoke.3177619976 May 23 02:51:06 PM PDT 24 May 23 02:51:09 PM PDT 24 17304089 ps
T812 /workspace/coverage/default/16.edn_err.754981582 May 23 02:51:08 PM PDT 24 May 23 02:51:11 PM PDT 24 18329102 ps
T813 /workspace/coverage/default/170.edn_genbits.2160738557 May 23 02:53:46 PM PDT 24 May 23 02:53:49 PM PDT 24 40610461 ps
T814 /workspace/coverage/default/8.edn_genbits.938237285 May 23 02:50:51 PM PDT 24 May 23 02:50:58 PM PDT 24 104750345 ps
T272 /workspace/coverage/default/298.edn_genbits.3018922966 May 23 02:54:13 PM PDT 24 May 23 02:54:18 PM PDT 24 70729622 ps
T815 /workspace/coverage/default/14.edn_alert.4248367146 May 23 02:51:10 PM PDT 24 May 23 02:51:13 PM PDT 24 78055162 ps
T816 /workspace/coverage/default/17.edn_disable.3268892924 May 23 02:51:09 PM PDT 24 May 23 02:51:13 PM PDT 24 41729308 ps
T817 /workspace/coverage/default/36.edn_disable_auto_req_mode.348604629 May 23 02:52:19 PM PDT 24 May 23 02:52:25 PM PDT 24 80545392 ps
T818 /workspace/coverage/default/38.edn_alert_test.3738020612 May 23 02:52:17 PM PDT 24 May 23 02:52:24 PM PDT 24 35076706 ps
T819 /workspace/coverage/default/23.edn_alert_test.4090621532 May 23 02:51:20 PM PDT 24 May 23 02:51:25 PM PDT 24 42376042 ps
T820 /workspace/coverage/default/3.edn_genbits.2176496481 May 23 02:49:56 PM PDT 24 May 23 02:49:59 PM PDT 24 91738420 ps
T821 /workspace/coverage/default/45.edn_err.1984322295 May 23 02:52:52 PM PDT 24 May 23 02:52:56 PM PDT 24 18638328 ps
T822 /workspace/coverage/default/5.edn_err.269688262 May 23 02:50:28 PM PDT 24 May 23 02:50:31 PM PDT 24 20328882 ps
T823 /workspace/coverage/default/26.edn_stress_all.4039945214 May 23 02:51:47 PM PDT 24 May 23 02:51:54 PM PDT 24 329101447 ps
T824 /workspace/coverage/default/239.edn_genbits.2870149505 May 23 02:54:15 PM PDT 24 May 23 02:54:20 PM PDT 24 37114360 ps
T825 /workspace/coverage/default/30.edn_stress_all.1949996698 May 23 02:51:51 PM PDT 24 May 23 02:51:59 PM PDT 24 115535479 ps
T826 /workspace/coverage/default/144.edn_genbits.4167712206 May 23 02:53:46 PM PDT 24 May 23 02:53:48 PM PDT 24 48625787 ps
T827 /workspace/coverage/default/22.edn_alert.40436169 May 23 02:51:22 PM PDT 24 May 23 02:51:27 PM PDT 24 29012952 ps
T828 /workspace/coverage/default/55.edn_genbits.3844344572 May 23 02:53:03 PM PDT 24 May 23 02:53:08 PM PDT 24 93373618 ps
T171 /workspace/coverage/default/0.edn_disable.549664442 May 23 02:49:58 PM PDT 24 May 23 02:50:01 PM PDT 24 12368226 ps
T829 /workspace/coverage/default/263.edn_genbits.3258026421 May 23 02:54:18 PM PDT 24 May 23 02:54:23 PM PDT 24 69442679 ps
T830 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2962828527 May 23 02:52:22 PM PDT 24 May 23 03:08:24 PM PDT 24 254011180030 ps
T831 /workspace/coverage/default/4.edn_err.829228057 May 23 02:50:28 PM PDT 24 May 23 02:50:32 PM PDT 24 45511693 ps
T832 /workspace/coverage/default/275.edn_genbits.2750902826 May 23 02:54:18 PM PDT 24 May 23 02:54:23 PM PDT 24 84302403 ps
T833 /workspace/coverage/default/133.edn_genbits.2332463022 May 23 02:53:47 PM PDT 24 May 23 02:53:52 PM PDT 24 69043598 ps
T834 /workspace/coverage/default/20.edn_disable_auto_req_mode.1596213201 May 23 02:51:20 PM PDT 24 May 23 02:51:25 PM PDT 24 122953772 ps
T835 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1205134567 May 23 02:52:30 PM PDT 24 May 23 03:13:21 PM PDT 24 52866398016 ps
T836 /workspace/coverage/default/89.edn_err.2593835501 May 23 02:53:18 PM PDT 24 May 23 02:53:21 PM PDT 24 77960642 ps
T837 /workspace/coverage/default/43.edn_stress_all.1484454373 May 23 02:52:53 PM PDT 24 May 23 02:52:58 PM PDT 24 141428045 ps
T838 /workspace/coverage/default/25.edn_alert.1123558861 May 23 02:51:50 PM PDT 24 May 23 02:51:57 PM PDT 24 97911671 ps
T839 /workspace/coverage/default/136.edn_genbits.3804819980 May 23 02:53:49 PM PDT 24 May 23 02:53:55 PM PDT 24 35558263 ps
T840 /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2640359028 May 23 02:51:49 PM PDT 24 May 23 03:02:18 PM PDT 24 105386842548 ps
T841 /workspace/coverage/default/39.edn_genbits.4131151966 May 23 02:52:16 PM PDT 24 May 23 02:52:24 PM PDT 24 46662694 ps
T842 /workspace/coverage/default/56.edn_err.148071359 May 23 02:53:09 PM PDT 24 May 23 02:53:14 PM PDT 24 25336523 ps
T843 /workspace/coverage/default/294.edn_genbits.3326471396 May 23 02:54:21 PM PDT 24 May 23 02:54:26 PM PDT 24 168552701 ps
T844 /workspace/coverage/default/5.edn_disable.835079680 May 23 02:50:26 PM PDT 24 May 23 02:50:27 PM PDT 24 44196281 ps
T845 /workspace/coverage/default/21.edn_genbits.2845780749 May 23 02:51:19 PM PDT 24 May 23 02:51:23 PM PDT 24 49737107 ps
T846 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1173508524 May 23 03:29:34 PM PDT 24 May 23 03:29:37 PM PDT 24 57684241 ps
T208 /workspace/coverage/cover_reg_top/17.edn_csr_rw.4233864511 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 55787395 ps
T847 /workspace/coverage/cover_reg_top/19.edn_intr_test.1805575790 May 23 03:30:18 PM PDT 24 May 23 03:30:22 PM PDT 24 29189732 ps
T233 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3861455005 May 23 03:29:48 PM PDT 24 May 23 03:29:52 PM PDT 24 80558267 ps
T848 /workspace/coverage/cover_reg_top/41.edn_intr_test.2291021206 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 16752942 ps
T234 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1262126836 May 23 03:29:38 PM PDT 24 May 23 03:29:42 PM PDT 24 158004386 ps
T849 /workspace/coverage/cover_reg_top/0.edn_intr_test.4194651699 May 23 03:29:21 PM PDT 24 May 23 03:29:26 PM PDT 24 18170640 ps
T235 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.365564542 May 23 03:30:02 PM PDT 24 May 23 03:30:06 PM PDT 24 88285403 ps
T224 /workspace/coverage/cover_reg_top/7.edn_csr_rw.4099312145 May 23 03:29:35 PM PDT 24 May 23 03:29:37 PM PDT 24 10788340 ps
T209 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1379831940 May 23 03:29:23 PM PDT 24 May 23 03:29:27 PM PDT 24 16233889 ps
T210 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1711290198 May 23 03:29:22 PM PDT 24 May 23 03:29:27 PM PDT 24 53593419 ps
T211 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4119673831 May 23 03:29:35 PM PDT 24 May 23 03:29:38 PM PDT 24 20326899 ps
T225 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1985717593 May 23 03:30:02 PM PDT 24 May 23 03:30:05 PM PDT 24 46487530 ps
T850 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1830085645 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 63523376 ps
T851 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2264667480 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 49788561 ps
T852 /workspace/coverage/cover_reg_top/12.edn_tl_errors.858958339 May 23 03:30:03 PM PDT 24 May 23 03:30:07 PM PDT 24 95134443 ps
T853 /workspace/coverage/cover_reg_top/45.edn_intr_test.2028028896 May 23 03:30:30 PM PDT 24 May 23 03:30:32 PM PDT 24 74057155 ps
T242 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1856386969 May 23 03:29:35 PM PDT 24 May 23 03:29:39 PM PDT 24 132324943 ps
T212 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2483312067 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 15208772 ps
T226 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.799875674 May 23 03:30:18 PM PDT 24 May 23 03:30:21 PM PDT 24 440338066 ps
T854 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2621024467 May 23 03:29:24 PM PDT 24 May 23 03:29:28 PM PDT 24 395075178 ps
T855 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1896847657 May 23 03:29:21 PM PDT 24 May 23 03:29:23 PM PDT 24 24344494 ps
T227 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2496082023 May 23 03:29:50 PM PDT 24 May 23 03:29:54 PM PDT 24 17067764 ps
T856 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.377135873 May 23 03:29:26 PM PDT 24 May 23 03:29:30 PM PDT 24 22792922 ps
T857 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1337709732 May 23 03:30:20 PM PDT 24 May 23 03:30:24 PM PDT 24 16917788 ps
T858 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1908261467 May 23 03:30:18 PM PDT 24 May 23 03:30:22 PM PDT 24 18051477 ps
T213 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1385052839 May 23 03:29:22 PM PDT 24 May 23 03:29:27 PM PDT 24 152338891 ps
T859 /workspace/coverage/cover_reg_top/18.edn_intr_test.1770243200 May 23 03:30:18 PM PDT 24 May 23 03:30:21 PM PDT 24 19718168 ps
T228 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2213790412 May 23 03:29:49 PM PDT 24 May 23 03:29:51 PM PDT 24 49886902 ps
T860 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1516420134 May 23 03:29:21 PM PDT 24 May 23 03:29:29 PM PDT 24 252829234 ps
T214 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3315762268 May 23 03:29:36 PM PDT 24 May 23 03:29:44 PM PDT 24 259585314 ps
T861 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1000617374 May 23 03:29:50 PM PDT 24 May 23 03:29:55 PM PDT 24 92729316 ps
T862 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4018772918 May 23 03:29:35 PM PDT 24 May 23 03:29:38 PM PDT 24 25022335 ps
T215 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3157296399 May 23 03:29:22 PM PDT 24 May 23 03:29:27 PM PDT 24 18723633 ps
T863 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2400660628 May 23 03:29:52 PM PDT 24 May 23 03:29:58 PM PDT 24 110406029 ps
T864 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3777081362 May 23 03:29:24 PM PDT 24 May 23 03:29:28 PM PDT 24 60789675 ps
T865 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2945111725 May 23 03:30:16 PM PDT 24 May 23 03:30:19 PM PDT 24 27409888 ps
T866 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2157734102 May 23 03:29:49 PM PDT 24 May 23 03:29:53 PM PDT 24 54191718 ps
T229 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2631823606 May 23 03:29:38 PM PDT 24 May 23 03:29:40 PM PDT 24 134995163 ps
T243 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.997281404 May 23 03:30:19 PM PDT 24 May 23 03:30:32 PM PDT 24 1250086629 ps
T867 /workspace/coverage/cover_reg_top/13.edn_tl_errors.307962250 May 23 03:30:04 PM PDT 24 May 23 03:30:09 PM PDT 24 522259187 ps
T868 /workspace/coverage/cover_reg_top/11.edn_intr_test.3786738714 May 23 03:29:50 PM PDT 24 May 23 03:29:54 PM PDT 24 52208967 ps
T869 /workspace/coverage/cover_reg_top/44.edn_intr_test.2851764334 May 23 03:30:21 PM PDT 24 May 23 03:30:27 PM PDT 24 56854915 ps
T244 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3392307792 May 23 03:29:22 PM PDT 24 May 23 03:29:29 PM PDT 24 287776768 ps
T870 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3366470896 May 23 03:29:49 PM PDT 24 May 23 03:29:51 PM PDT 24 24694909 ps
T216 /workspace/coverage/cover_reg_top/8.edn_csr_rw.1637640689 May 23 03:29:52 PM PDT 24 May 23 03:29:57 PM PDT 24 64315200 ps
T871 /workspace/coverage/cover_reg_top/30.edn_intr_test.2804323702 May 23 03:30:21 PM PDT 24 May 23 03:30:26 PM PDT 24 43051495 ps
T230 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2005942464 May 23 03:30:02 PM PDT 24 May 23 03:30:04 PM PDT 24 13410682 ps
T872 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2426890650 May 23 03:30:17 PM PDT 24 May 23 03:30:20 PM PDT 24 60012246 ps
T873 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3467700993 May 23 03:29:23 PM PDT 24 May 23 03:29:27 PM PDT 24 52110840 ps
T874 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3996495206 May 23 03:29:40 PM PDT 24 May 23 03:29:43 PM PDT 24 68343243 ps
T875 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3026675291 May 23 03:30:03 PM PDT 24 May 23 03:30:06 PM PDT 24 46844635 ps
T876 /workspace/coverage/cover_reg_top/23.edn_intr_test.2756753300 May 23 03:30:19 PM PDT 24 May 23 03:30:22 PM PDT 24 31218987 ps
T877 /workspace/coverage/cover_reg_top/14.edn_intr_test.2812420186 May 23 03:30:03 PM PDT 24 May 23 03:30:06 PM PDT 24 14309228 ps
T878 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.987323873 May 23 03:29:53 PM PDT 24 May 23 03:29:58 PM PDT 24 52794368 ps
T879 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4040447460 May 23 03:29:21 PM PDT 24 May 23 03:29:26 PM PDT 24 77954841 ps
T880 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1820801934 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 38722836 ps
T245 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.749275926 May 23 03:30:17 PM PDT 24 May 23 03:30:21 PM PDT 24 870918874 ps
T881 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2765611336 May 23 03:29:24 PM PDT 24 May 23 03:29:28 PM PDT 24 127919914 ps
T882 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2761500118 May 23 03:29:50 PM PDT 24 May 23 03:29:55 PM PDT 24 321945758 ps
T883 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2693375068 May 23 03:29:36 PM PDT 24 May 23 03:29:38 PM PDT 24 18893664 ps
T884 /workspace/coverage/cover_reg_top/40.edn_intr_test.3370227788 May 23 03:30:20 PM PDT 24 May 23 03:30:26 PM PDT 24 16566002 ps
T885 /workspace/coverage/cover_reg_top/49.edn_intr_test.3150533325 May 23 03:30:32 PM PDT 24 May 23 03:30:34 PM PDT 24 20633635 ps
T886 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.575754169 May 23 03:29:51 PM PDT 24 May 23 03:29:55 PM PDT 24 213236033 ps
T887 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.825564508 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 24749436 ps
T888 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1839575619 May 23 03:29:34 PM PDT 24 May 23 03:29:36 PM PDT 24 11935349 ps
T889 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.493826196 May 23 03:29:36 PM PDT 24 May 23 03:29:38 PM PDT 24 20397855 ps
T890 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2836992682 May 23 03:29:49 PM PDT 24 May 23 03:29:52 PM PDT 24 218367979 ps
T891 /workspace/coverage/cover_reg_top/26.edn_intr_test.1439059578 May 23 03:30:22 PM PDT 24 May 23 03:30:27 PM PDT 24 17159297 ps
T892 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1371351036 May 23 03:30:17 PM PDT 24 May 23 03:30:22 PM PDT 24 141910726 ps
T217 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1547323073 May 23 03:29:26 PM PDT 24 May 23 03:29:30 PM PDT 24 33169930 ps
T893 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2001559610 May 23 03:29:38 PM PDT 24 May 23 03:29:40 PM PDT 24 60645323 ps
T894 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2907160750 May 23 03:30:00 PM PDT 24 May 23 03:30:03 PM PDT 24 41740437 ps
T895 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3136343512 May 23 03:30:16 PM PDT 24 May 23 03:30:19 PM PDT 24 131496395 ps
T896 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3742326729 May 23 03:29:52 PM PDT 24 May 23 03:29:57 PM PDT 24 34522196 ps
T897 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1826639450 May 23 03:29:50 PM PDT 24 May 23 03:29:56 PM PDT 24 147015892 ps
T898 /workspace/coverage/cover_reg_top/2.edn_intr_test.2223064046 May 23 03:29:23 PM PDT 24 May 23 03:29:27 PM PDT 24 11493931 ps
T899 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4104829490 May 23 03:30:02 PM PDT 24 May 23 03:30:05 PM PDT 24 26523044 ps
T900 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1601630091 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 58986332 ps
T901 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1349228487 May 23 03:30:20 PM PDT 24 May 23 03:30:26 PM PDT 24 50338062 ps
T902 /workspace/coverage/cover_reg_top/39.edn_intr_test.586694311 May 23 03:30:20 PM PDT 24 May 23 03:30:24 PM PDT 24 34502011 ps
T903 /workspace/coverage/cover_reg_top/46.edn_intr_test.517720744 May 23 03:30:31 PM PDT 24 May 23 03:30:33 PM PDT 24 14412147 ps
T904 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3876998266 May 23 03:30:03 PM PDT 24 May 23 03:30:07 PM PDT 24 19762011 ps
T905 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2893101 May 23 03:29:50 PM PDT 24 May 23 03:29:54 PM PDT 24 307141821 ps
T906 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3519836171 May 23 03:30:17 PM PDT 24 May 23 03:30:20 PM PDT 24 62933667 ps
T907 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2031310940 May 23 03:29:34 PM PDT 24 May 23 03:29:36 PM PDT 24 14143641 ps
T908 /workspace/coverage/cover_reg_top/24.edn_intr_test.1490359988 May 23 03:30:22 PM PDT 24 May 23 03:30:27 PM PDT 24 40933591 ps
T909 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2173179822 May 23 03:30:17 PM PDT 24 May 23 03:30:22 PM PDT 24 467923162 ps
T910 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2629364382 May 23 03:30:03 PM PDT 24 May 23 03:30:06 PM PDT 24 21475270 ps
T911 /workspace/coverage/cover_reg_top/13.edn_intr_test.2335228673 May 23 03:30:02 PM PDT 24 May 23 03:30:04 PM PDT 24 14988732 ps
T912 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2193982106 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 28484939 ps
T913 /workspace/coverage/cover_reg_top/25.edn_intr_test.2764307861 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 14625090 ps
T914 /workspace/coverage/cover_reg_top/33.edn_intr_test.3994565626 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 43385449 ps
T222 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.62126247 May 23 03:29:22 PM PDT 24 May 23 03:29:28 PM PDT 24 64266871 ps
T915 /workspace/coverage/cover_reg_top/32.edn_intr_test.563288094 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 29627018 ps
T916 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2751207255 May 23 03:30:18 PM PDT 24 May 23 03:30:21 PM PDT 24 43051798 ps
T917 /workspace/coverage/cover_reg_top/9.edn_intr_test.1826600640 May 23 03:29:48 PM PDT 24 May 23 03:29:51 PM PDT 24 22399364 ps
T918 /workspace/coverage/cover_reg_top/38.edn_intr_test.1910967923 May 23 03:30:22 PM PDT 24 May 23 03:30:27 PM PDT 24 12875384 ps
T919 /workspace/coverage/cover_reg_top/29.edn_intr_test.698346477 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 13437655 ps
T920 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3587793522 May 23 03:29:34 PM PDT 24 May 23 03:29:38 PM PDT 24 204123799 ps
T921 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2458951054 May 23 03:29:24 PM PDT 24 May 23 03:29:30 PM PDT 24 268691897 ps
T922 /workspace/coverage/cover_reg_top/43.edn_intr_test.3883588732 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 32144809 ps
T923 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1764960842 May 23 03:30:18 PM PDT 24 May 23 03:30:22 PM PDT 24 64036722 ps
T924 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2783307881 May 23 03:30:26 PM PDT 24 May 23 03:30:29 PM PDT 24 43173456 ps
T925 /workspace/coverage/cover_reg_top/31.edn_intr_test.4146897997 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 42141902 ps
T926 /workspace/coverage/cover_reg_top/0.edn_tl_errors.577824547 May 23 03:29:21 PM PDT 24 May 23 03:29:26 PM PDT 24 38672963 ps
T927 /workspace/coverage/cover_reg_top/35.edn_intr_test.1201308494 May 23 03:30:19 PM PDT 24 May 23 03:30:24 PM PDT 24 17263812 ps
T928 /workspace/coverage/cover_reg_top/4.edn_intr_test.239516200 May 23 03:29:37 PM PDT 24 May 23 03:29:40 PM PDT 24 67095373 ps
T218 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.439810819 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 86665503 ps
T929 /workspace/coverage/cover_reg_top/6.edn_intr_test.3235682142 May 23 03:29:39 PM PDT 24 May 23 03:29:41 PM PDT 24 63156968 ps
T930 /workspace/coverage/cover_reg_top/20.edn_intr_test.1597542517 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 41989326 ps
T931 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3580720151 May 23 03:30:03 PM PDT 24 May 23 03:30:06 PM PDT 24 16769922 ps
T932 /workspace/coverage/cover_reg_top/48.edn_intr_test.1330772550 May 23 03:30:32 PM PDT 24 May 23 03:30:35 PM PDT 24 15144128 ps
T933 /workspace/coverage/cover_reg_top/12.edn_intr_test.1492169460 May 23 03:30:03 PM PDT 24 May 23 03:30:05 PM PDT 24 23745443 ps
T934 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.617663848 May 23 03:29:39 PM PDT 24 May 23 03:29:42 PM PDT 24 73659881 ps
T935 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4041664542 May 23 03:29:21 PM PDT 24 May 23 03:29:26 PM PDT 24 16525320 ps
T936 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.969744651 May 23 03:29:21 PM PDT 24 May 23 03:29:27 PM PDT 24 174982741 ps
T937 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3903985164 May 23 03:30:18 PM PDT 24 May 23 03:30:21 PM PDT 24 63058490 ps
T938 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1283153303 May 23 03:29:38 PM PDT 24 May 23 03:29:41 PM PDT 24 35824716 ps
T939 /workspace/coverage/cover_reg_top/15.edn_intr_test.1695501777 May 23 03:30:20 PM PDT 24 May 23 03:30:26 PM PDT 24 49493957 ps
T940 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2032537546 May 23 03:29:49 PM PDT 24 May 23 03:29:52 PM PDT 24 26686187 ps
T941 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2479854369 May 23 03:29:49 PM PDT 24 May 23 03:29:54 PM PDT 24 165521207 ps
T942 /workspace/coverage/cover_reg_top/22.edn_intr_test.3274317754 May 23 03:30:21 PM PDT 24 May 23 03:30:26 PM PDT 24 10458822 ps
T943 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1736291148 May 23 03:29:35 PM PDT 24 May 23 03:29:38 PM PDT 24 22106533 ps
T944 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1601050116 May 23 03:29:24 PM PDT 24 May 23 03:29:28 PM PDT 24 53131493 ps
T945 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2637411014 May 23 03:30:22 PM PDT 24 May 23 03:30:28 PM PDT 24 200938823 ps
T946 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2595391504 May 23 03:29:20 PM PDT 24 May 23 03:29:22 PM PDT 24 159187338 ps
T947 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3899460525 May 23 03:29:20 PM PDT 24 May 23 03:29:22 PM PDT 24 16819851 ps
T219 /workspace/coverage/cover_reg_top/10.edn_csr_rw.795390355 May 23 03:29:50 PM PDT 24 May 23 03:29:54 PM PDT 24 17859771 ps
T948 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3822456601 May 23 03:30:19 PM PDT 24 May 23 03:30:25 PM PDT 24 28761436 ps
T949 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1691200328 May 23 03:29:37 PM PDT 24 May 23 03:29:41 PM PDT 24 56140519 ps
T950 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.928084388 May 23 03:29:36 PM PDT 24 May 23 03:29:39 PM PDT 24 77160762 ps
T951 /workspace/coverage/cover_reg_top/16.edn_intr_test.2299437005 May 23 03:30:21 PM PDT 24 May 23 03:30:26 PM PDT 24 86407543 ps
T952 /workspace/coverage/cover_reg_top/10.edn_intr_test.2385225561 May 23 03:29:50 PM PDT 24 May 23 03:29:53 PM PDT 24 159548196 ps
T953 /workspace/coverage/cover_reg_top/7.edn_intr_test.2235125892 May 23 03:29:36 PM PDT 24 May 23 03:29:38 PM PDT 24 66558140 ps
T954 /workspace/coverage/cover_reg_top/47.edn_intr_test.227668722 May 23 03:30:33 PM PDT 24 May 23 03:30:37 PM PDT 24 36455908 ps
T220 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.916944182 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 81361065 ps
T955 /workspace/coverage/cover_reg_top/28.edn_intr_test.4264042835 May 23 03:30:19 PM PDT 24 May 23 03:30:24 PM PDT 24 12558201 ps
T956 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4161780577 May 23 03:30:02 PM PDT 24 May 23 03:30:05 PM PDT 24 67921714 ps
T957 /workspace/coverage/cover_reg_top/3.edn_intr_test.836038735 May 23 03:29:23 PM PDT 24 May 23 03:29:28 PM PDT 24 40670114 ps
T958 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.726809021 May 23 03:29:24 PM PDT 24 May 23 03:29:32 PM PDT 24 346156272 ps
T959 /workspace/coverage/cover_reg_top/34.edn_intr_test.3059132059 May 23 03:30:22 PM PDT 24 May 23 03:30:27 PM PDT 24 29671311 ps
T960 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1609497722 May 23 03:29:34 PM PDT 24 May 23 03:29:39 PM PDT 24 75194292 ps
T961 /workspace/coverage/cover_reg_top/36.edn_intr_test.3131739653 May 23 03:30:18 PM PDT 24 May 23 03:30:22 PM PDT 24 51401353 ps
T962 /workspace/coverage/cover_reg_top/37.edn_intr_test.1735618927 May 23 03:30:17 PM PDT 24 May 23 03:30:19 PM PDT 24 38235463 ps
T963 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2541615314 May 23 03:29:35 PM PDT 24 May 23 03:29:39 PM PDT 24 287221970 ps
T964 /workspace/coverage/cover_reg_top/21.edn_intr_test.3265700614 May 23 03:30:20 PM PDT 24 May 23 03:30:24 PM PDT 24 21133348 ps
T965 /workspace/coverage/cover_reg_top/42.edn_intr_test.2855861879 May 23 03:30:22 PM PDT 24 May 23 03:30:27 PM PDT 24 24942511 ps
T966 /workspace/coverage/cover_reg_top/17.edn_intr_test.3205305725 May 23 03:30:19 PM PDT 24 May 23 03:30:23 PM PDT 24 14108805 ps
T967 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3799398729 May 23 03:29:26 PM PDT 24 May 23 03:29:31 PM PDT 24 26044761 ps
T968 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2951194478 May 23 03:30:22 PM PDT 24 May 23 03:30:31 PM PDT 24 232970528 ps
T969 /workspace/coverage/cover_reg_top/5.edn_intr_test.3188757895 May 23 03:29:38 PM PDT 24 May 23 03:29:41 PM PDT 24 26907207 ps
T223 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3626054389 May 23 03:30:20 PM PDT 24 May 23 03:30:24 PM PDT 24 40479875 ps
T970 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2750016848 May 23 03:30:06 PM PDT 24 May 23 03:30:09 PM PDT 24 60079077 ps
T971 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1947436429 May 23 03:30:20 PM PDT 24 May 23 03:30:25 PM PDT 24 50316507 ps
T972 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3288212319 May 23 03:30:00 PM PDT 24 May 23 03:30:03 PM PDT 24 19297959 ps
T973 /workspace/coverage/cover_reg_top/2.edn_tl_errors.283026576 May 23 03:29:22 PM PDT 24 May 23 03:29:28 PM PDT 24 22103785 ps
T974 /workspace/coverage/cover_reg_top/8.edn_intr_test.2984481760 May 23 03:29:50 PM PDT 24 May 23 03:29:54 PM PDT 24 14586096 ps
T975 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3627105140 May 23 03:30:20 PM PDT 24 May 23 03:30:26 PM PDT 24 58390826 ps
T976 /workspace/coverage/cover_reg_top/27.edn_intr_test.3766266684 May 23 03:30:21 PM PDT 24 May 23 03:30:26 PM PDT 24 40711048 ps
T977 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2227797283 May 23 03:30:03 PM PDT 24 May 23 03:30:06 PM PDT 24 23388547 ps
T978 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3382698675 May 23 03:30:03 PM PDT 24 May 23 03:30:09 PM PDT 24 113698073 ps
T979 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.371430025 May 23 03:30:02 PM PDT 24 May 23 03:30:05 PM PDT 24 781238713 ps
T980 /workspace/coverage/cover_reg_top/1.edn_intr_test.294131810 May 23 03:29:21 PM PDT 24 May 23 03:29:25 PM PDT 24 13679354 ps
T221 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1764455702 May 23 03:29:34 PM PDT 24 May 23 03:29:36 PM PDT 24 46692542 ps

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.472078169
Short name T4
Test name
Test status
Simulation time 183006172030 ps
CPU time 1172.23 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 03:11:45 PM PDT 24
Peak memory 223452 kb
Host smart-090b2862-9f57-4f9e-9b76-4afd7b884e1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472078169 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.472078169
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/237.edn_genbits.1945679713
Short name T3
Test name
Test status
Simulation time 43410087 ps
CPU time 1.66 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 219532 kb
Host smart-b6378b92-60ec-4988-a732-63850092d294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945679713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1945679713
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2399280947
Short name T6
Test name
Test status
Simulation time 3244560305 ps
CPU time 8.1 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:37 PM PDT 24
Peak memory 238904 kb
Host smart-d672e9a0-f4e2-4d32-8a2e-2475d2ad1240
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399280947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2399280947
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/171.edn_genbits.3317038845
Short name T28
Test name
Test status
Simulation time 80310771 ps
CPU time 1.47 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 218168 kb
Host smart-e93a2523-218d-4237-bc19-28aabebb2247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317038845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3317038845
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.801321549
Short name T69
Test name
Test status
Simulation time 23583112 ps
CPU time 1.24 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 215424 kb
Host smart-9cedbb84-2cdc-4790-921a-e9e505b59e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801321549 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.801321549
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.424115627
Short name T10
Test name
Test status
Simulation time 36021153 ps
CPU time 1.23 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 217904 kb
Host smart-513bb29d-7b26-4165-8c68-baffee9a2f15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424115627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.424115627
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1606390847
Short name T16
Test name
Test status
Simulation time 269082084 ps
CPU time 4.81 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:07 PM PDT 24
Peak memory 235120 kb
Host smart-13250f64-8f8a-46a9-ba98-270be03d9e73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606390847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1606390847
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/90.edn_err.1048867759
Short name T14
Test name
Test status
Simulation time 21180513 ps
CPU time 1.03 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 223512 kb
Host smart-02cc57f2-c7c3-4426-ba0d-55767116415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048867759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1048867759
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/24.edn_alert.1368747736
Short name T27
Test name
Test status
Simulation time 108316213 ps
CPU time 1.21 seconds
Started May 23 02:51:36 PM PDT 24
Finished May 23 02:51:39 PM PDT 24
Peak memory 215420 kb
Host smart-5fd813e0-536a-48bb-976d-cc4aec7fcfac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368747736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1368747736
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.1237045753
Short name T107
Test name
Test status
Simulation time 20285048 ps
CPU time 1.01 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:54 PM PDT 24
Peak memory 206748 kb
Host smart-ede5530a-f124-4e92-a6c4-73133ec34e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237045753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1237045753
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/175.edn_genbits.2273332838
Short name T13
Test name
Test status
Simulation time 119210719 ps
CPU time 1.38 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 219536 kb
Host smart-c6355c1a-8e4b-453d-9023-5b47af318302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273332838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2273332838
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2038288693
Short name T100
Test name
Test status
Simulation time 46688830 ps
CPU time 1.23 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 215256 kb
Host smart-e16d1e48-1a28-4836-bb57-bbe3cb308d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038288693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2038288693
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1637640689
Short name T216
Test name
Test status
Simulation time 64315200 ps
CPU time 0.92 seconds
Started May 23 03:29:52 PM PDT 24
Finished May 23 03:29:57 PM PDT 24
Peak memory 206236 kb
Host smart-b149fa2c-2407-4bf9-bd39-6ffa0fa58027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637640689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1637640689
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3861455005
Short name T233
Test name
Test status
Simulation time 80558267 ps
CPU time 2.28 seconds
Started May 23 03:29:48 PM PDT 24
Finished May 23 03:29:52 PM PDT 24
Peak memory 206324 kb
Host smart-04e53834-416e-4b5f-8215-d1f27929e019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861455005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3861455005
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3602981038
Short name T35
Test name
Test status
Simulation time 117649576 ps
CPU time 1.21 seconds
Started May 23 02:52:29 PM PDT 24
Finished May 23 02:52:33 PM PDT 24
Peak memory 216560 kb
Host smart-423e6cde-ed28-45c7-9d34-856fe751a664
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602981038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3602981038
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.35288404
Short name T22
Test name
Test status
Simulation time 14257571 ps
CPU time 0.89 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:53 PM PDT 24
Peak memory 216072 kb
Host smart-36ab8fa9-5ae7-439a-b4be-b0625f3142ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35288404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.35288404
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable.867192414
Short name T94
Test name
Test status
Simulation time 13624199 ps
CPU time 0.86 seconds
Started May 23 02:51:35 PM PDT 24
Finished May 23 02:51:37 PM PDT 24
Peak memory 216144 kb
Host smart-1e6ba2f6-386f-4ae8-95f9-91cf168018d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867192414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.867192414
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.690393560
Short name T68
Test name
Test status
Simulation time 36326380 ps
CPU time 0.88 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:54 PM PDT 24
Peak memory 216228 kb
Host smart-095d1dc9-87d4-486b-a907-3b3948061e2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690393560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.690393560
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.660601139
Short name T53
Test name
Test status
Simulation time 22396385 ps
CPU time 1.13 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 216772 kb
Host smart-ff02d336-20c3-441a-94f5-7f238b054ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660601139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.660601139
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/88.edn_err.2436598851
Short name T101
Test name
Test status
Simulation time 29723465 ps
CPU time 0.88 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 218772 kb
Host smart-c39e1ddf-cfb8-4832-a6d9-629fbf576846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436598851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2436598851
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/34.edn_alert.1954036482
Short name T77
Test name
Test status
Simulation time 80637517 ps
CPU time 1.13 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:15 PM PDT 24
Peak memory 215396 kb
Host smart-a019a793-516d-4610-bc08-1995a73b76f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954036482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1954036482
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.643722641
Short name T247
Test name
Test status
Simulation time 74276342 ps
CPU time 1.09 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 215396 kb
Host smart-ee04d86b-be15-4087-929a-29a3ff875f71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643722641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.643722641
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/295.edn_genbits.3491689258
Short name T236
Test name
Test status
Simulation time 35738560 ps
CPU time 1.67 seconds
Started May 23 02:54:23 PM PDT 24
Finished May 23 02:54:28 PM PDT 24
Peak memory 217924 kb
Host smart-5131d2e3-9188-4cf9-ac22-87e0f2211230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491689258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3491689258
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_alert.262994818
Short name T159
Test name
Test status
Simulation time 34030247 ps
CPU time 1.33 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 215388 kb
Host smart-f7177175-5c11-4ea9-96bf-b4348c99a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262994818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.262994818
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/42.edn_intr.1071639112
Short name T112
Test name
Test status
Simulation time 72690084 ps
CPU time 0.89 seconds
Started May 23 02:52:31 PM PDT 24
Finished May 23 02:52:35 PM PDT 24
Peak memory 215176 kb
Host smart-2b6abeb0-02a2-4a31-96c1-8f580021d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071639112 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1071639112
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/17.edn_err.1712755188
Short name T62
Test name
Test status
Simulation time 30001029 ps
CPU time 1.24 seconds
Started May 23 02:51:08 PM PDT 24
Finished May 23 02:51:11 PM PDT 24
Peak memory 215220 kb
Host smart-62cae847-bd61-4395-974f-f49c03e8eae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712755188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1712755188
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.605514565
Short name T56
Test name
Test status
Simulation time 168465582 ps
CPU time 1.13 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:55 PM PDT 24
Peak memory 216624 kb
Host smart-793c244d-9900-4b2e-8535-ec5d2b22778a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605514565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.605514565
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/181.edn_genbits.261919053
Short name T269
Test name
Test status
Simulation time 82567834 ps
CPU time 1.28 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 218344 kb
Host smart-9e68f92d-05c5-435c-a0d9-d8ff623d3fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261919053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.261919053
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_disable.3904663538
Short name T95
Test name
Test status
Simulation time 29207636 ps
CPU time 0.84 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 216064 kb
Host smart-7c14059a-75d8-4e06-b89d-0b9b4d512b3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904663538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3904663538
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/57.edn_err.3668935502
Short name T7
Test name
Test status
Simulation time 20540103 ps
CPU time 1.24 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 229148 kb
Host smart-5ad0a5aa-d99d-49ba-b451-0383b73a4b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668935502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3668935502
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.2919523037
Short name T141
Test name
Test status
Simulation time 35852766 ps
CPU time 0.9 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 215248 kb
Host smart-b5644148-62e5-4ace-bbe5-eb9eb3c0c007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919523037 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2919523037
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.549664442
Short name T171
Test name
Test status
Simulation time 12368226 ps
CPU time 0.89 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 216084 kb
Host smart-c9d969fc-3301-4c44-a902-b864f3175f68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549664442 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.549664442
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2196130110
Short name T741
Test name
Test status
Simulation time 35799360 ps
CPU time 0.93 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 217956 kb
Host smart-9332c573-85a8-452e-8381-9617a4bec071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196130110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2196130110
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.712022249
Short name T38
Test name
Test status
Simulation time 91593731 ps
CPU time 1.17 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216712 kb
Host smart-03f64973-1754-458b-89bd-c426ff502692
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712022249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_di
sable_auto_req_mode.712022249
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2082430828
Short name T91
Test name
Test status
Simulation time 19742527 ps
CPU time 1.09 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 218132 kb
Host smart-c39310c4-e07e-4ce8-9d82-c99d24340d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082430828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2082430828
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.4160351691
Short name T163
Test name
Test status
Simulation time 57724653 ps
CPU time 1.04 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 216652 kb
Host smart-fa06a991-3ce5-4047-8b45-e074b50303e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160351691 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.4160351691
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1619375663
Short name T174
Test name
Test status
Simulation time 55593512 ps
CPU time 1.21 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 02:51:08 PM PDT 24
Peak memory 216548 kb
Host smart-724301af-2bb7-483c-aa36-259e11196b43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619375663 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1619375663
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.1241727016
Short name T86
Test name
Test status
Simulation time 23011766 ps
CPU time 0.91 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:27 PM PDT 24
Peak memory 215812 kb
Host smart-ce94dff7-148a-4c52-b6b9-473ae7633005
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241727016 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1241727016
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/19.edn_alert.2207308567
Short name T153
Test name
Test status
Simulation time 99727160 ps
CPU time 1.26 seconds
Started May 23 02:51:24 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215420 kb
Host smart-66d8ea7f-acf9-4100-a8f0-884f29980936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207308567 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2207308567
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/166.edn_genbits.2479563311
Short name T276
Test name
Test status
Simulation time 90900842 ps
CPU time 1.87 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 219592 kb
Host smart-9a6ce6b0-79d3-45dc-8db4-697c788c3416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479563311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2479563311
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.388445708
Short name T135
Test name
Test status
Simulation time 39899337 ps
CPU time 1.32 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:07 PM PDT 24
Peak memory 216876 kb
Host smart-2852bdfe-3083-40b0-88c1-093642e1c7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388445708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.388445708
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.2868940270
Short name T718
Test name
Test status
Simulation time 17724095 ps
CPU time 1.01 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 206816 kb
Host smart-a5540f27-bfff-44a2-b1d8-be3a4b2a1345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868940270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2868940270
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1215066859
Short name T145
Test name
Test status
Simulation time 174476157044 ps
CPU time 1332.34 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 03:15:09 PM PDT 24
Peak memory 223596 kb
Host smart-3d8f8677-0544-4a1d-8092-24bd1a671701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215066859 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1215066859
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.3284656161
Short name T2
Test name
Test status
Simulation time 186274715 ps
CPU time 0.89 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 214936 kb
Host smart-1c776f6c-9b97-4223-a554-1ba565828e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284656161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3284656161
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_stress_all.4238545923
Short name T286
Test name
Test status
Simulation time 59349103 ps
CPU time 1.26 seconds
Started May 23 02:49:56 PM PDT 24
Finished May 23 02:49:58 PM PDT 24
Peak memory 215032 kb
Host smart-e8adb95b-ab37-4e17-8b48-c9253a405a35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238545923 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4238545923
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_intr.766868411
Short name T113
Test name
Test status
Simulation time 36811674 ps
CPU time 0.87 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:57 PM PDT 24
Peak memory 215220 kb
Host smart-311790ae-659c-408a-b8fc-5558cf208883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766868411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.766868411
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/153.edn_genbits.1934931067
Short name T285
Test name
Test status
Simulation time 128129827 ps
CPU time 1.43 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 219448 kb
Host smart-1097cd87-b732-4f08-8aa7-1f35182e4beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934931067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1934931067
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.654846909
Short name T246
Test name
Test status
Simulation time 107783961 ps
CPU time 1.32 seconds
Started May 23 02:51:08 PM PDT 24
Finished May 23 02:51:11 PM PDT 24
Peak memory 215364 kb
Host smart-e42e252d-2ef4-4d88-a812-731c7de0b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654846909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.654846909
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/126.edn_genbits.50232486
Short name T134
Test name
Test status
Simulation time 96718267 ps
CPU time 1.17 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 216940 kb
Host smart-13929ab5-0916-4928-983e-3fd34d729826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50232486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.50232486
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.749275926
Short name T245
Test name
Test status
Simulation time 870918874 ps
CPU time 2.71 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 206280 kb
Host smart-b1056b53-b523-406e-aec8-f0e2a356b7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749275926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.749275926
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/default/11.edn_stress_all.3538901188
Short name T144
Test name
Test status
Simulation time 44673055 ps
CPU time 1.56 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 215012 kb
Host smart-40e7f720-cfa6-4dbf-b858-d746649766d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538901188 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3538901188
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/114.edn_genbits.3904168450
Short name T280
Test name
Test status
Simulation time 38993723 ps
CPU time 1.55 seconds
Started May 23 02:53:34 PM PDT 24
Finished May 23 02:53:37 PM PDT 24
Peak memory 218924 kb
Host smart-06f2c18b-e9b4-46ad-af2a-d13b7bbe26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904168450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3904168450
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.772444417
Short name T271
Test name
Test status
Simulation time 34766470 ps
CPU time 1.36 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 216892 kb
Host smart-4fc4e957-ed50-431e-899f-169589c4a0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772444417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.772444417
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all.2289761807
Short name T266
Test name
Test status
Simulation time 45375599 ps
CPU time 1.06 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 206816 kb
Host smart-f4232a1a-8777-47f0-a94b-ab75f3abb99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289761807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2289761807
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/145.edn_genbits.1193289436
Short name T364
Test name
Test status
Simulation time 52602743 ps
CPU time 1.11 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 216600 kb
Host smart-7d41aecf-0ee4-496e-b7ac-81244299058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193289436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1193289436
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3307775408
Short name T290
Test name
Test status
Simulation time 73853402 ps
CPU time 1.17 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 216900 kb
Host smart-ca5c7f62-5754-4360-ad90-912cd62605ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307775408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3307775408
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2699422066
Short name T267
Test name
Test status
Simulation time 85933958 ps
CPU time 1.33 seconds
Started May 23 02:53:50 PM PDT 24
Finished May 23 02:53:56 PM PDT 24
Peak memory 218180 kb
Host smart-aa3faeec-c1a3-4008-8f87-fba7d1c70dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699422066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2699422066
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1913482649
Short name T275
Test name
Test status
Simulation time 37586682 ps
CPU time 1.56 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 218020 kb
Host smart-6e3c6923-603a-4883-bb32-16a13496fdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913482649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1913482649
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3311206370
Short name T183
Test name
Test status
Simulation time 43224842 ps
CPU time 1.18 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:50 PM PDT 24
Peak memory 215464 kb
Host smart-08d2d87b-e6ec-413d-a09c-182c00674459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311206370 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3311206370
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/298.edn_genbits.3018922966
Short name T272
Test name
Test status
Simulation time 70729622 ps
CPU time 1.35 seconds
Started May 23 02:54:13 PM PDT 24
Finished May 23 02:54:18 PM PDT 24
Peak memory 217944 kb
Host smart-08e8b915-2663-46e1-90ab-b2442e3d7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018922966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3018922966
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2992363042
Short name T241
Test name
Test status
Simulation time 58636614 ps
CPU time 1.24 seconds
Started May 23 02:52:00 PM PDT 24
Finished May 23 02:52:10 PM PDT 24
Peak memory 216616 kb
Host smart-4f28fcfd-b41e-4954-a90f-f21231216a20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992363042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2992363042
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_regwen.667854924
Short name T255
Test name
Test status
Simulation time 23199143 ps
CPU time 1.03 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 206852 kb
Host smart-940f006b-3888-43ac-9aed-5faaa9416172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667854924 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.667854924
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/13.edn_intr.2843269595
Short name T720
Test name
Test status
Simulation time 35654046 ps
CPU time 0.9 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 215240 kb
Host smart-7605ee90-f847-4751-a118-3d3c40d98001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843269595 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2843269595
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1385052839
Short name T213
Test name
Test status
Simulation time 152338891 ps
CPU time 1.62 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206220 kb
Host smart-20a19259-b401-4303-9924-0758e4507528
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385052839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1385052839
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1516420134
Short name T860
Test name
Test status
Simulation time 252829234 ps
CPU time 3.18 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:29 PM PDT 24
Peak memory 206324 kb
Host smart-2dd02d73-033d-4bba-987f-ee582ba956dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516420134 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1516420134
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1896847657
Short name T855
Test name
Test status
Simulation time 24344494 ps
CPU time 0.96 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:23 PM PDT 24
Peak memory 206124 kb
Host smart-afa59b9f-fe77-4ce0-9d5c-17ec245b4215
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896847657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1896847657
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2595391504
Short name T946
Test name
Test status
Simulation time 159187338 ps
CPU time 1.16 seconds
Started May 23 03:29:20 PM PDT 24
Finished May 23 03:29:22 PM PDT 24
Peak memory 214532 kb
Host smart-c2622a24-6a22-49ef-bfb3-f66ddd1b2925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595391504 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2595391504
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3899460525
Short name T947
Test name
Test status
Simulation time 16819851 ps
CPU time 0.94 seconds
Started May 23 03:29:20 PM PDT 24
Finished May 23 03:29:22 PM PDT 24
Peak memory 206232 kb
Host smart-93e254d5-bc34-4b96-8b70-b73604c05b52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899460525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3899460525
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4194651699
Short name T849
Test name
Test status
Simulation time 18170640 ps
CPU time 0.83 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:26 PM PDT 24
Peak memory 206088 kb
Host smart-72430a28-6ada-4833-99b9-aa41abfb1b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194651699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4194651699
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4041664542
Short name T935
Test name
Test status
Simulation time 16525320 ps
CPU time 1.01 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:26 PM PDT 24
Peak memory 206300 kb
Host smart-9821d860-5e85-4f3b-884e-d0691ad56068
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041664542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.4041664542
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.577824547
Short name T926
Test name
Test status
Simulation time 38672963 ps
CPU time 2.59 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:26 PM PDT 24
Peak memory 214492 kb
Host smart-4f98be78-09ca-401b-85f3-9c4c41e76d08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577824547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.577824547
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1830085645
Short name T850
Test name
Test status
Simulation time 63523376 ps
CPU time 1.81 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206232 kb
Host smart-8c181820-464d-4962-8634-b5ec706f4c25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830085645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1830085645
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.916944182
Short name T220
Test name
Test status
Simulation time 81361065 ps
CPU time 1.09 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206224 kb
Host smart-b1a796d1-634b-4f98-a6ff-d0edc5116c74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916944182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.916944182
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.62126247
Short name T222
Test name
Test status
Simulation time 64266871 ps
CPU time 2.04 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206224 kb
Host smart-7c97f741-f16c-44ab-9635-4a4088902a24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62126247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.62126247
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1601050116
Short name T944
Test name
Test status
Simulation time 53131493 ps
CPU time 0.91 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206200 kb
Host smart-c3a37711-cb5c-43ca-8e63-09065e4e6c2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601050116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1601050116
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2264667480
Short name T851
Test name
Test status
Simulation time 49788561 ps
CPU time 1.32 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 214492 kb
Host smart-ecdea2e7-77e6-4312-b80f-58f57606ee8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264667480 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2264667480
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1379831940
Short name T209
Test name
Test status
Simulation time 16233889 ps
CPU time 0.93 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206216 kb
Host smart-f05b6a39-98fc-466c-983e-db10678d16bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379831940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1379831940
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.294131810
Short name T980
Test name
Test status
Simulation time 13679354 ps
CPU time 0.86 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:25 PM PDT 24
Peak memory 206060 kb
Host smart-d5c4f40e-dd2a-4239-be05-766614c6f998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294131810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.294131810
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3157296399
Short name T215
Test name
Test status
Simulation time 18723633 ps
CPU time 1.19 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206240 kb
Host smart-8266d773-14a4-412c-a691-0357453b78a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157296399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3157296399
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1601630091
Short name T900
Test name
Test status
Simulation time 58986332 ps
CPU time 1.98 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 218492 kb
Host smart-abc66919-c897-488c-b461-4efec3a7346d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601630091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1601630091
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.969744651
Short name T936
Test name
Test status
Simulation time 174982741 ps
CPU time 1.6 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 214416 kb
Host smart-2936d899-f162-4309-ab47-2b4b6b8a48f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969744651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.969744651
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2836992682
Short name T890
Test name
Test status
Simulation time 218367979 ps
CPU time 1.02 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:52 PM PDT 24
Peak memory 215664 kb
Host smart-3dcfe2d4-1f0d-4e78-acf6-241e13544913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836992682 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2836992682
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.795390355
Short name T219
Test name
Test status
Simulation time 17859771 ps
CPU time 0.85 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 206188 kb
Host smart-9c06c497-f120-4298-875b-cfdaa595e28d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795390355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.795390355
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2385225561
Short name T952
Test name
Test status
Simulation time 159548196 ps
CPU time 0.83 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:53 PM PDT 24
Peak memory 206096 kb
Host smart-045874b4-6345-470a-9c38-7809b0e438ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385225561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2385225561
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2032537546
Short name T940
Test name
Test status
Simulation time 26686187 ps
CPU time 1.2 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:52 PM PDT 24
Peak memory 206200 kb
Host smart-24cfae17-99e0-4f5e-a3aa-ec12b8f212cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032537546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2032537546
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1000617374
Short name T861
Test name
Test status
Simulation time 92729316 ps
CPU time 3.12 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:55 PM PDT 24
Peak memory 214408 kb
Host smart-6dccd60a-74d2-4c54-b599-855bd8e3e36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000617374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1000617374
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3876998266
Short name T904
Test name
Test status
Simulation time 19762011 ps
CPU time 1.39 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:07 PM PDT 24
Peak memory 214540 kb
Host smart-274a4d2f-6acc-4abb-b29b-29564cbb7e3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876998266 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3876998266
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2907160750
Short name T894
Test name
Test status
Simulation time 41740437 ps
CPU time 0.84 seconds
Started May 23 03:30:00 PM PDT 24
Finished May 23 03:30:03 PM PDT 24
Peak memory 206184 kb
Host smart-a7a2c809-f5eb-41af-ae0c-780546793a85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907160750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2907160750
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3786738714
Short name T868
Test name
Test status
Simulation time 52208967 ps
CPU time 0.89 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 206092 kb
Host smart-7eb146e7-4669-42c3-bbed-651a3fc75c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786738714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3786738714
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4161780577
Short name T956
Test name
Test status
Simulation time 67921714 ps
CPU time 1.05 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:05 PM PDT 24
Peak memory 206208 kb
Host smart-9af245b9-b14e-40a6-a9d5-dc63d160412e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161780577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.4161780577
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2479854369
Short name T941
Test name
Test status
Simulation time 165521207 ps
CPU time 2.97 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 214404 kb
Host smart-cbf77858-d3c2-490a-8e28-f109cc04540e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479854369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2479854369
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2761500118
Short name T882
Test name
Test status
Simulation time 321945758 ps
CPU time 1.6 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:55 PM PDT 24
Peak memory 214532 kb
Host smart-c9a487df-4bf0-4136-924e-ab2bc22f3234
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761500118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2761500118
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2227797283
Short name T977
Test name
Test status
Simulation time 23388547 ps
CPU time 1.17 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 214500 kb
Host smart-a1f70abe-b0e3-4757-b44b-207681831410
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227797283 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2227797283
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1985717593
Short name T225
Test name
Test status
Simulation time 46487530 ps
CPU time 0.87 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:05 PM PDT 24
Peak memory 206184 kb
Host smart-9605ec36-c22a-43d0-95f1-4011ce079dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985717593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1985717593
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1492169460
Short name T933
Test name
Test status
Simulation time 23745443 ps
CPU time 0.86 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:05 PM PDT 24
Peak memory 206108 kb
Host smart-67f85779-97bc-4890-aa63-a490522e82b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492169460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1492169460
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2629364382
Short name T910
Test name
Test status
Simulation time 21475270 ps
CPU time 1.24 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 206236 kb
Host smart-d53d21ef-f11d-4d5d-8c2f-a14a289f6467
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629364382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2629364382
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.858958339
Short name T852
Test name
Test status
Simulation time 95134443 ps
CPU time 1.74 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:07 PM PDT 24
Peak memory 214428 kb
Host smart-d66386c8-5f14-422c-ad88-73a4718764a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858958339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.858958339
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2750016848
Short name T970
Test name
Test status
Simulation time 60079077 ps
CPU time 1.82 seconds
Started May 23 03:30:06 PM PDT 24
Finished May 23 03:30:09 PM PDT 24
Peak memory 214412 kb
Host smart-f34f9d5e-89da-4a35-9382-bcfb2da2b65c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750016848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2750016848
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4104829490
Short name T899
Test name
Test status
Simulation time 26523044 ps
CPU time 1.55 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:05 PM PDT 24
Peak memory 214532 kb
Host smart-1203bb83-bc49-4e8f-875b-5cd6328bba52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104829490 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4104829490
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2005942464
Short name T230
Test name
Test status
Simulation time 13410682 ps
CPU time 0.85 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:04 PM PDT 24
Peak memory 206164 kb
Host smart-af5c33d8-4e9b-4874-a549-4365f38c62e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005942464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2005942464
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2335228673
Short name T911
Test name
Test status
Simulation time 14988732 ps
CPU time 0.99 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:04 PM PDT 24
Peak memory 206120 kb
Host smart-7ab289ef-bd6a-4dd4-9cd8-aa167a060263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335228673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2335228673
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3580720151
Short name T931
Test name
Test status
Simulation time 16769922 ps
CPU time 1.04 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 206232 kb
Host smart-7eeb6a1d-1536-49d8-87ab-5aa4f8f38fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580720151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3580720151
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.307962250
Short name T867
Test name
Test status
Simulation time 522259187 ps
CPU time 3.13 seconds
Started May 23 03:30:04 PM PDT 24
Finished May 23 03:30:09 PM PDT 24
Peak memory 214492 kb
Host smart-26c33445-9c2d-456e-bbc0-9d25c4369e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307962250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.307962250
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.371430025
Short name T979
Test name
Test status
Simulation time 781238713 ps
CPU time 1.76 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:05 PM PDT 24
Peak memory 206304 kb
Host smart-d6e1cd60-88c2-4751-84d4-88544a28cf9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371430025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.371430025
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3903985164
Short name T937
Test name
Test status
Simulation time 63058490 ps
CPU time 1.22 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 214592 kb
Host smart-9c2275dd-37e1-466b-801e-9a9568869470
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903985164 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3903985164
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3288212319
Short name T972
Test name
Test status
Simulation time 19297959 ps
CPU time 0.83 seconds
Started May 23 03:30:00 PM PDT 24
Finished May 23 03:30:03 PM PDT 24
Peak memory 206032 kb
Host smart-939a826c-d753-4743-bfc6-11eb8cce08d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288212319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3288212319
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2812420186
Short name T877
Test name
Test status
Simulation time 14309228 ps
CPU time 0.91 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 206144 kb
Host smart-21984865-c97f-44b0-85a7-b8326d038296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812420186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2812420186
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3026675291
Short name T875
Test name
Test status
Simulation time 46844635 ps
CPU time 1.12 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 206224 kb
Host smart-ae633bf7-ed7f-4a0d-b14b-6e39c793fb86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026675291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3026675291
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3382698675
Short name T978
Test name
Test status
Simulation time 113698073 ps
CPU time 3.83 seconds
Started May 23 03:30:03 PM PDT 24
Finished May 23 03:30:09 PM PDT 24
Peak memory 214484 kb
Host smart-075ed77b-4cef-446e-b15e-963a4c9e8249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382698675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3382698675
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.365564542
Short name T235
Test name
Test status
Simulation time 88285403 ps
CPU time 2.59 seconds
Started May 23 03:30:02 PM PDT 24
Finished May 23 03:30:06 PM PDT 24
Peak memory 206352 kb
Host smart-57e61ff4-1efb-4f0a-a6bd-39a051c3bbe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365564542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.365564542
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2426890650
Short name T872
Test name
Test status
Simulation time 60012246 ps
CPU time 1.03 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:20 PM PDT 24
Peak memory 216100 kb
Host smart-f82fc303-8ad3-48eb-b914-7844114e2876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426890650 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2426890650
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3626054389
Short name T223
Test name
Test status
Simulation time 40479875 ps
CPU time 0.84 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206172 kb
Host smart-cfd13019-4f9b-4a58-9f7d-91c6f05da9c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626054389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3626054389
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1695501777
Short name T939
Test name
Test status
Simulation time 49493957 ps
CPU time 0.97 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206056 kb
Host smart-f7a6ba68-7061-46a2-8edc-80dccffd3441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695501777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1695501777
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3519836171
Short name T906
Test name
Test status
Simulation time 62933667 ps
CPU time 1.37 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:20 PM PDT 24
Peak memory 206228 kb
Host smart-761eb3c5-92ea-49b0-9c52-d5d36e64c883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519836171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3519836171
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1764960842
Short name T923
Test name
Test status
Simulation time 64036722 ps
CPU time 2.43 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 214516 kb
Host smart-0456e7b3-7490-4b44-91d8-7da2d358c7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764960842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1764960842
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.997281404
Short name T243
Test name
Test status
Simulation time 1250086629 ps
CPU time 9.94 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:32 PM PDT 24
Peak memory 206144 kb
Host smart-302d2e2e-69c0-4099-98e5-29e33b99f29e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997281404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.997281404
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2751207255
Short name T916
Test name
Test status
Simulation time 43051798 ps
CPU time 1.28 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 214532 kb
Host smart-043acd40-5d6a-4b42-9416-2cbdf23f9cb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751207255 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2751207255
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1908261467
Short name T858
Test name
Test status
Simulation time 18051477 ps
CPU time 0.9 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 206196 kb
Host smart-0858e666-aae7-4feb-87b4-3fa099f8eb23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908261467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1908261467
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2299437005
Short name T951
Test name
Test status
Simulation time 86407543 ps
CPU time 0.83 seconds
Started May 23 03:30:21 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206016 kb
Host smart-7d718f85-e858-439e-a6a4-888738b1ac59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299437005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2299437005
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2783307881
Short name T924
Test name
Test status
Simulation time 43173456 ps
CPU time 0.92 seconds
Started May 23 03:30:26 PM PDT 24
Finished May 23 03:30:29 PM PDT 24
Peak memory 206252 kb
Host smart-68be31e9-7253-4bf9-a84a-ebee7942374e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783307881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2783307881
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2637411014
Short name T945
Test name
Test status
Simulation time 200938823 ps
CPU time 2.12 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:28 PM PDT 24
Peak memory 214500 kb
Host smart-baf5e0b2-4d62-4288-8175-6602a679db9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637411014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2637411014
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1371351036
Short name T892
Test name
Test status
Simulation time 141910726 ps
CPU time 3.14 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 206364 kb
Host smart-4a18c62d-3348-498e-8fa9-1ff1714912b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371351036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1371351036
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.825564508
Short name T887
Test name
Test status
Simulation time 24749436 ps
CPU time 1.6 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 214504 kb
Host smart-803fd0b7-d95d-4dd4-a13b-ca4c04110c4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825564508 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.825564508
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4233864511
Short name T208
Test name
Test status
Simulation time 55787395 ps
CPU time 0.81 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206228 kb
Host smart-3f65aa86-17b1-4c59-96f2-1fc794c841b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233864511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4233864511
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3205305725
Short name T966
Test name
Test status
Simulation time 14108805 ps
CPU time 0.93 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206100 kb
Host smart-8eedf16c-8214-4072-8658-7cb93e05e846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205305725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3205305725
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1947436429
Short name T971
Test name
Test status
Simulation time 50316507 ps
CPU time 1.07 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 206196 kb
Host smart-6d65ad5d-3ef3-4cb6-87f4-457a24790e42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947436429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1947436429
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3136343512
Short name T895
Test name
Test status
Simulation time 131496395 ps
CPU time 1.66 seconds
Started May 23 03:30:16 PM PDT 24
Finished May 23 03:30:19 PM PDT 24
Peak memory 214412 kb
Host smart-10cd899b-f9cd-46c2-b431-2b649d910a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136343512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3136343512
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2173179822
Short name T909
Test name
Test status
Simulation time 467923162 ps
CPU time 2.38 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 214428 kb
Host smart-860d8c97-f704-493a-acf0-b5e2a5fc6f3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173179822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2173179822
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2945111725
Short name T865
Test name
Test status
Simulation time 27409888 ps
CPU time 1.25 seconds
Started May 23 03:30:16 PM PDT 24
Finished May 23 03:30:19 PM PDT 24
Peak memory 214536 kb
Host smart-87462f5c-3f8f-46ac-8122-2b8119c25169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945111725 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2945111725
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2483312067
Short name T212
Test name
Test status
Simulation time 15208772 ps
CPU time 0.88 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 206232 kb
Host smart-0797fb86-8d58-4a60-8aef-2382b506c1d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483312067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2483312067
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1770243200
Short name T859
Test name
Test status
Simulation time 19718168 ps
CPU time 0.91 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 206048 kb
Host smart-b46725ab-1860-4673-811b-89d15f6f247e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770243200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1770243200
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.799875674
Short name T226
Test name
Test status
Simulation time 440338066 ps
CPU time 1.35 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:21 PM PDT 24
Peak memory 206316 kb
Host smart-bf577b0b-7c17-4b31-9294-347758657b34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799875674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.799875674
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2951194478
Short name T968
Test name
Test status
Simulation time 232970528 ps
CPU time 4.14 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:31 PM PDT 24
Peak memory 214428 kb
Host smart-22bcf762-5dfe-4f82-a398-90b0aac631ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951194478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2951194478
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1349228487
Short name T901
Test name
Test status
Simulation time 50338062 ps
CPU time 1.68 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206232 kb
Host smart-a55b1a7b-70fd-49b7-8f66-0f2ea9728a25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349228487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1349228487
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2193982106
Short name T912
Test name
Test status
Simulation time 28484939 ps
CPU time 1.46 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 214536 kb
Host smart-4a4ea3e5-9d90-4d59-9607-09d942cb5364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193982106 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2193982106
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1337709732
Short name T857
Test name
Test status
Simulation time 16917788 ps
CPU time 0.96 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206212 kb
Host smart-4ecf8880-5795-4ec0-85a2-df21f751fb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337709732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1337709732
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1805575790
Short name T847
Test name
Test status
Simulation time 29189732 ps
CPU time 0.98 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 206192 kb
Host smart-9c0e88b8-2ae2-4974-bb5b-24f32ec5aa15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805575790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1805575790
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3627105140
Short name T975
Test name
Test status
Simulation time 58390826 ps
CPU time 1.38 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206224 kb
Host smart-3ec9b2b1-6631-4499-902b-0c1213caa1f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627105140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3627105140
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3822456601
Short name T948
Test name
Test status
Simulation time 28761436 ps
CPU time 2.03 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 214492 kb
Host smart-6b23e999-31d8-4251-8890-91ef2f32f9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822456601 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3822456601
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.439810819
Short name T218
Test name
Test status
Simulation time 86665503 ps
CPU time 1.21 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206300 kb
Host smart-ae6302fb-fd47-411d-bfbb-437b2a78c868
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439810819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.439810819
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2458951054
Short name T921
Test name
Test status
Simulation time 268691897 ps
CPU time 3.61 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:30 PM PDT 24
Peak memory 206216 kb
Host smart-3bacdd4d-a929-4b64-9732-b8cc9d1973ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458951054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2458951054
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3777081362
Short name T864
Test name
Test status
Simulation time 60789675 ps
CPU time 0.91 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206220 kb
Host smart-0cd3565d-33f9-4b29-9858-fa04f935c9e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777081362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3777081362
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2621024467
Short name T854
Test name
Test status
Simulation time 395075178 ps
CPU time 1.34 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 214448 kb
Host smart-8a179770-c54c-404a-b4b1-6a15cb6cb1a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621024467 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2621024467
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1711290198
Short name T210
Test name
Test status
Simulation time 53593419 ps
CPU time 0.81 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206100 kb
Host smart-8236f01f-0951-4fb0-9edc-6508d98bf736
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711290198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1711290198
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2223064046
Short name T898
Test name
Test status
Simulation time 11493931 ps
CPU time 0.88 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206064 kb
Host smart-c9bbc8b0-6bc4-4525-b02f-b7a12477c24f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223064046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2223064046
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1820801934
Short name T880
Test name
Test status
Simulation time 38722836 ps
CPU time 1.15 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206216 kb
Host smart-60a43979-87bf-4972-9cda-0cbbe6eb4cc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820801934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1820801934
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.283026576
Short name T973
Test name
Test status
Simulation time 22103785 ps
CPU time 1.53 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 214528 kb
Host smart-a4866255-e67f-448c-9344-8dcef7a2f532
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283026576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.283026576
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4040447460
Short name T879
Test name
Test status
Simulation time 77954841 ps
CPU time 2.28 seconds
Started May 23 03:29:21 PM PDT 24
Finished May 23 03:29:26 PM PDT 24
Peak memory 206268 kb
Host smart-98cfdf0b-800a-45f2-a9d6-98ebd688b8f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040447460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4040447460
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1597542517
Short name T930
Test name
Test status
Simulation time 41989326 ps
CPU time 0.86 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 206096 kb
Host smart-edca68cc-e256-40fe-997c-e35a8f23db5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597542517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1597542517
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3265700614
Short name T964
Test name
Test status
Simulation time 21133348 ps
CPU time 0.82 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206008 kb
Host smart-e2164ff5-ca67-4362-a82e-f9f49f012cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265700614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3265700614
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3274317754
Short name T942
Test name
Test status
Simulation time 10458822 ps
CPU time 0.83 seconds
Started May 23 03:30:21 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206108 kb
Host smart-d4e47b28-6f35-42ca-9162-1b215aa9a3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274317754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3274317754
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2756753300
Short name T876
Test name
Test status
Simulation time 31218987 ps
CPU time 0.8 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 206004 kb
Host smart-082fe8c4-eeef-4229-9038-a72947aa61cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756753300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2756753300
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1490359988
Short name T908
Test name
Test status
Simulation time 40933591 ps
CPU time 0.83 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206084 kb
Host smart-86025498-1ced-4cc1-9de4-e796b811eb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490359988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1490359988
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2764307861
Short name T913
Test name
Test status
Simulation time 14625090 ps
CPU time 0.89 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 206084 kb
Host smart-3566eb41-db67-418c-8e45-8f149f6de16c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764307861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2764307861
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1439059578
Short name T891
Test name
Test status
Simulation time 17159297 ps
CPU time 0.93 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206180 kb
Host smart-125d91a1-979c-4095-b403-13762748823b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439059578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1439059578
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3766266684
Short name T976
Test name
Test status
Simulation time 40711048 ps
CPU time 0.78 seconds
Started May 23 03:30:21 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206012 kb
Host smart-fb702eed-70e1-439a-af34-f6881ae12ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766266684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3766266684
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4264042835
Short name T955
Test name
Test status
Simulation time 12558201 ps
CPU time 0.85 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206056 kb
Host smart-548cd3a0-e02c-471a-8628-8ae77bd0070e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264042835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4264042835
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.698346477
Short name T919
Test name
Test status
Simulation time 13437655 ps
CPU time 0.84 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206136 kb
Host smart-2d1c38a8-bec6-4068-b36e-6905c3430aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698346477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.698346477
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.377135873
Short name T856
Test name
Test status
Simulation time 22792922 ps
CPU time 1.17 seconds
Started May 23 03:29:26 PM PDT 24
Finished May 23 03:29:30 PM PDT 24
Peak memory 206192 kb
Host smart-f632b4eb-c428-4c80-8399-bc0ace5a0778
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377135873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.377135873
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.726809021
Short name T958
Test name
Test status
Simulation time 346156272 ps
CPU time 4.98 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:32 PM PDT 24
Peak memory 206220 kb
Host smart-321931fe-9945-4394-8497-a351aed92c0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726809021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.726809021
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3467700993
Short name T873
Test name
Test status
Simulation time 52110840 ps
CPU time 0.89 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:27 PM PDT 24
Peak memory 206184 kb
Host smart-246290e8-c09f-4412-a4c1-f07deab107ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467700993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3467700993
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.617663848
Short name T934
Test name
Test status
Simulation time 73659881 ps
CPU time 1.15 seconds
Started May 23 03:29:39 PM PDT 24
Finished May 23 03:29:42 PM PDT 24
Peak memory 214484 kb
Host smart-def3ca51-4852-48a0-bf40-18fcb73e8641
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617663848 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.617663848
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1547323073
Short name T217
Test name
Test status
Simulation time 33169930 ps
CPU time 0.85 seconds
Started May 23 03:29:26 PM PDT 24
Finished May 23 03:29:30 PM PDT 24
Peak memory 206128 kb
Host smart-8586007d-276a-449b-bf96-477bc3b39bd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547323073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1547323073
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.836038735
Short name T957
Test name
Test status
Simulation time 40670114 ps
CPU time 0.85 seconds
Started May 23 03:29:23 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 206212 kb
Host smart-d363cc50-e24c-44f3-97ef-1de3af3de1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836038735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.836038735
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3799398729
Short name T967
Test name
Test status
Simulation time 26044761 ps
CPU time 1.03 seconds
Started May 23 03:29:26 PM PDT 24
Finished May 23 03:29:31 PM PDT 24
Peak memory 206196 kb
Host smart-4d9ba459-8fa9-4d2b-920f-7da30cf052d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799398729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3799398729
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2765611336
Short name T881
Test name
Test status
Simulation time 127919914 ps
CPU time 1.51 seconds
Started May 23 03:29:24 PM PDT 24
Finished May 23 03:29:28 PM PDT 24
Peak memory 214444 kb
Host smart-d1602b08-cbcd-48b3-9cbe-24550992ea1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765611336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2765611336
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3392307792
Short name T244
Test name
Test status
Simulation time 287776768 ps
CPU time 2.31 seconds
Started May 23 03:29:22 PM PDT 24
Finished May 23 03:29:29 PM PDT 24
Peak memory 206328 kb
Host smart-06156694-fdcf-48f1-9532-4a17305c28e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392307792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3392307792
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2804323702
Short name T871
Test name
Test status
Simulation time 43051495 ps
CPU time 0.85 seconds
Started May 23 03:30:21 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206100 kb
Host smart-a8664364-7f2f-4d76-ad90-03e241e2dcdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804323702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2804323702
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4146897997
Short name T925
Test name
Test status
Simulation time 42141902 ps
CPU time 0.85 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206100 kb
Host smart-ccabc920-4fcf-4b18-8b38-917d9544d4a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146897997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4146897997
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.563288094
Short name T915
Test name
Test status
Simulation time 29627018 ps
CPU time 0.89 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206012 kb
Host smart-fcc4382c-c213-4ec5-b2a0-959f591e7c58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563288094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.563288094
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3994565626
Short name T914
Test name
Test status
Simulation time 43385449 ps
CPU time 0.87 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 206124 kb
Host smart-3a6b6be9-9c77-43ba-bd85-4edae8f22161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994565626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3994565626
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3059132059
Short name T959
Test name
Test status
Simulation time 29671311 ps
CPU time 0.9 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206108 kb
Host smart-9d54bb62-3c18-405f-85a3-3ba3aa43d31f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059132059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3059132059
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1201308494
Short name T927
Test name
Test status
Simulation time 17263812 ps
CPU time 0.83 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206052 kb
Host smart-b4ff02a1-37bf-44cc-8658-cc606d15beca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201308494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1201308494
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3131739653
Short name T961
Test name
Test status
Simulation time 51401353 ps
CPU time 0.89 seconds
Started May 23 03:30:18 PM PDT 24
Finished May 23 03:30:22 PM PDT 24
Peak memory 206084 kb
Host smart-db7f7ca9-470b-4b29-9a5d-5ca9d4102477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131739653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3131739653
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1735618927
Short name T962
Test name
Test status
Simulation time 38235463 ps
CPU time 0.84 seconds
Started May 23 03:30:17 PM PDT 24
Finished May 23 03:30:19 PM PDT 24
Peak memory 206060 kb
Host smart-13b635d7-c373-44ac-91b5-30da5ffd65b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735618927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1735618927
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1910967923
Short name T918
Test name
Test status
Simulation time 12875384 ps
CPU time 0.86 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206060 kb
Host smart-95a74ec1-98b2-450d-ba6a-08107c9ed94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910967923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1910967923
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.586694311
Short name T902
Test name
Test status
Simulation time 34502011 ps
CPU time 0.8 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:24 PM PDT 24
Peak memory 206088 kb
Host smart-95d146aa-dc42-40c2-b601-0d0ad904f221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586694311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.586694311
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4119673831
Short name T211
Test name
Test status
Simulation time 20326899 ps
CPU time 1.12 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 206148 kb
Host smart-63822478-a694-4eb2-a7d5-e64064b64aad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119673831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4119673831
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3315762268
Short name T214
Test name
Test status
Simulation time 259585314 ps
CPU time 6.36 seconds
Started May 23 03:29:36 PM PDT 24
Finished May 23 03:29:44 PM PDT 24
Peak memory 206228 kb
Host smart-965856b9-327e-41fa-9c87-d80eff45991e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315762268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3315762268
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1764455702
Short name T221
Test name
Test status
Simulation time 46692542 ps
CPU time 0.89 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:36 PM PDT 24
Peak memory 206184 kb
Host smart-884a6deb-002d-471a-bfac-01a08cb09d34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764455702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1764455702
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.928084388
Short name T950
Test name
Test status
Simulation time 77160762 ps
CPU time 0.98 seconds
Started May 23 03:29:36 PM PDT 24
Finished May 23 03:29:39 PM PDT 24
Peak memory 206268 kb
Host smart-d7830470-d7ee-417a-807a-37128da09046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928084388 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.928084388
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1839575619
Short name T888
Test name
Test status
Simulation time 11935349 ps
CPU time 0.88 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:36 PM PDT 24
Peak memory 206212 kb
Host smart-196928c9-7506-482d-b09e-3c93152b3e63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839575619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1839575619
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.239516200
Short name T928
Test name
Test status
Simulation time 67095373 ps
CPU time 0.93 seconds
Started May 23 03:29:37 PM PDT 24
Finished May 23 03:29:40 PM PDT 24
Peak memory 206068 kb
Host smart-2c896f00-fda3-4650-a261-94b970d38a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239516200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.239516200
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1736291148
Short name T943
Test name
Test status
Simulation time 22106533 ps
CPU time 0.92 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 206200 kb
Host smart-bb6ba86d-3ee4-44d7-82e3-eda1812ff1a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736291148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1736291148
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1609497722
Short name T960
Test name
Test status
Simulation time 75194292 ps
CPU time 2.74 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:39 PM PDT 24
Peak memory 214420 kb
Host smart-dc2b8903-3411-45f5-8b85-aafdd430fc03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609497722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1609497722
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3996495206
Short name T874
Test name
Test status
Simulation time 68343243 ps
CPU time 1.93 seconds
Started May 23 03:29:40 PM PDT 24
Finished May 23 03:29:43 PM PDT 24
Peak memory 206188 kb
Host smart-01af950c-80bf-41f7-84fc-e4007938a9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996495206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3996495206
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3370227788
Short name T884
Test name
Test status
Simulation time 16566002 ps
CPU time 0.92 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:26 PM PDT 24
Peak memory 206088 kb
Host smart-987af76c-a2ec-4adb-bdc0-76632bb4f33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370227788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3370227788
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2291021206
Short name T848
Test name
Test status
Simulation time 16752942 ps
CPU time 0.86 seconds
Started May 23 03:30:19 PM PDT 24
Finished May 23 03:30:23 PM PDT 24
Peak memory 206100 kb
Host smart-2735b1fd-a5cf-4cbe-8d1b-af96fdb3fb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291021206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2291021206
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2855861879
Short name T965
Test name
Test status
Simulation time 24942511 ps
CPU time 0.89 seconds
Started May 23 03:30:22 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206088 kb
Host smart-411077e3-6575-4d32-a462-6ca771ce2864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855861879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2855861879
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3883588732
Short name T922
Test name
Test status
Simulation time 32144809 ps
CPU time 0.82 seconds
Started May 23 03:30:20 PM PDT 24
Finished May 23 03:30:25 PM PDT 24
Peak memory 205968 kb
Host smart-cc811304-218c-48e6-8f74-5c94c739c961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883588732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3883588732
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2851764334
Short name T869
Test name
Test status
Simulation time 56854915 ps
CPU time 0.89 seconds
Started May 23 03:30:21 PM PDT 24
Finished May 23 03:30:27 PM PDT 24
Peak memory 206196 kb
Host smart-34e96d84-4bc7-4d17-88ac-471474076bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851764334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2851764334
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2028028896
Short name T853
Test name
Test status
Simulation time 74057155 ps
CPU time 0.92 seconds
Started May 23 03:30:30 PM PDT 24
Finished May 23 03:30:32 PM PDT 24
Peak memory 206072 kb
Host smart-c22453f9-aee1-43f6-b909-b0eca176aeeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028028896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2028028896
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.517720744
Short name T903
Test name
Test status
Simulation time 14412147 ps
CPU time 0.83 seconds
Started May 23 03:30:31 PM PDT 24
Finished May 23 03:30:33 PM PDT 24
Peak memory 206032 kb
Host smart-24134eb7-d4bc-49f5-b509-c1c32d236817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517720744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.517720744
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.227668722
Short name T954
Test name
Test status
Simulation time 36455908 ps
CPU time 0.81 seconds
Started May 23 03:30:33 PM PDT 24
Finished May 23 03:30:37 PM PDT 24
Peak memory 206096 kb
Host smart-0a122700-0a68-4c96-8a91-425e345f22d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227668722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.227668722
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1330772550
Short name T932
Test name
Test status
Simulation time 15144128 ps
CPU time 0.9 seconds
Started May 23 03:30:32 PM PDT 24
Finished May 23 03:30:35 PM PDT 24
Peak memory 206084 kb
Host smart-e48f99eb-5d37-4ace-ad64-3f1f328582f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330772550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1330772550
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3150533325
Short name T885
Test name
Test status
Simulation time 20633635 ps
CPU time 0.83 seconds
Started May 23 03:30:32 PM PDT 24
Finished May 23 03:30:34 PM PDT 24
Peak memory 206100 kb
Host smart-340387d8-025d-47e6-9509-f3449abf075a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150533325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3150533325
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1173508524
Short name T846
Test name
Test status
Simulation time 57684241 ps
CPU time 1.09 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:37 PM PDT 24
Peak memory 214464 kb
Host smart-eaa40aa3-4d0d-49ab-9b0f-6e62135c996a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173508524 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1173508524
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2631823606
Short name T229
Test name
Test status
Simulation time 134995163 ps
CPU time 0.84 seconds
Started May 23 03:29:38 PM PDT 24
Finished May 23 03:29:40 PM PDT 24
Peak memory 206188 kb
Host smart-d60b820a-a67b-4c58-859b-9255e16a9cb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631823606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2631823606
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3188757895
Short name T969
Test name
Test status
Simulation time 26907207 ps
CPU time 0.87 seconds
Started May 23 03:29:38 PM PDT 24
Finished May 23 03:29:41 PM PDT 24
Peak memory 206060 kb
Host smart-ef84d2c7-41d5-40d1-995b-17e93156d3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188757895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3188757895
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2031310940
Short name T907
Test name
Test status
Simulation time 14143641 ps
CPU time 0.96 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:36 PM PDT 24
Peak memory 206240 kb
Host smart-7d8b2672-7e21-436e-9901-56a07bbf82b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031310940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2031310940
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4018772918
Short name T862
Test name
Test status
Simulation time 25022335 ps
CPU time 1.63 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 214428 kb
Host smart-53cbe64e-1cd9-400e-b569-ef26384cb14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018772918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4018772918
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.1262126836
Short name T234
Test name
Test status
Simulation time 158004386 ps
CPU time 2.32 seconds
Started May 23 03:29:38 PM PDT 24
Finished May 23 03:29:42 PM PDT 24
Peak memory 206188 kb
Host smart-211dbea7-d2b0-44fe-9a23-b5c0e87f8c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262126836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.1262126836
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1283153303
Short name T938
Test name
Test status
Simulation time 35824716 ps
CPU time 0.98 seconds
Started May 23 03:29:38 PM PDT 24
Finished May 23 03:29:41 PM PDT 24
Peak memory 206276 kb
Host smart-830cf667-2e1e-4fe5-a85d-7d6d73ec63e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283153303 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1283153303
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2693375068
Short name T883
Test name
Test status
Simulation time 18893664 ps
CPU time 0.78 seconds
Started May 23 03:29:36 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 206124 kb
Host smart-67ed7e6b-7c73-46a8-b9b8-9caa44dd5125
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693375068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2693375068
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3235682142
Short name T929
Test name
Test status
Simulation time 63156968 ps
CPU time 0.79 seconds
Started May 23 03:29:39 PM PDT 24
Finished May 23 03:29:41 PM PDT 24
Peak memory 205956 kb
Host smart-2361c1c3-50cf-43db-8c1b-4d4387a7f32a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235682142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3235682142
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.493826196
Short name T889
Test name
Test status
Simulation time 20397855 ps
CPU time 1.15 seconds
Started May 23 03:29:36 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 206328 kb
Host smart-a08ff052-ed94-4d88-a4f1-cd27895542f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493826196 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.493826196
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2541615314
Short name T963
Test name
Test status
Simulation time 287221970 ps
CPU time 2.92 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:39 PM PDT 24
Peak memory 214520 kb
Host smart-87f8d1ee-77ad-49bb-ad2a-dc7f4cdcda85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541615314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2541615314
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.1856386969
Short name T242
Test name
Test status
Simulation time 132324943 ps
CPU time 2.15 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:39 PM PDT 24
Peak memory 206244 kb
Host smart-6d07a699-9bf0-42d9-b1d4-9f49728d3e4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856386969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.1856386969
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3366470896
Short name T870
Test name
Test status
Simulation time 24694909 ps
CPU time 0.92 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:51 PM PDT 24
Peak memory 206220 kb
Host smart-465f619d-c9ce-42c1-b73f-d08e290b180c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366470896 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3366470896
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.4099312145
Short name T224
Test name
Test status
Simulation time 10788340 ps
CPU time 0.83 seconds
Started May 23 03:29:35 PM PDT 24
Finished May 23 03:29:37 PM PDT 24
Peak memory 206240 kb
Host smart-00191fe6-f4b3-4231-b4f0-f128ca43513b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099312145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.4099312145
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2235125892
Short name T953
Test name
Test status
Simulation time 66558140 ps
CPU time 0.88 seconds
Started May 23 03:29:36 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 206088 kb
Host smart-bdd797de-8773-4639-87f9-4c871e256361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235125892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2235125892
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2001559610
Short name T893
Test name
Test status
Simulation time 60645323 ps
CPU time 0.98 seconds
Started May 23 03:29:38 PM PDT 24
Finished May 23 03:29:40 PM PDT 24
Peak memory 206232 kb
Host smart-e59572fe-49b4-4a65-969d-49b3061d63ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001559610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2001559610
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3587793522
Short name T920
Test name
Test status
Simulation time 204123799 ps
CPU time 1.89 seconds
Started May 23 03:29:34 PM PDT 24
Finished May 23 03:29:38 PM PDT 24
Peak memory 214436 kb
Host smart-b81431ad-1e69-4dcf-93d2-61577c02163e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587793522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3587793522
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1691200328
Short name T949
Test name
Test status
Simulation time 56140519 ps
CPU time 1.77 seconds
Started May 23 03:29:37 PM PDT 24
Finished May 23 03:29:41 PM PDT 24
Peak memory 206200 kb
Host smart-49c619d8-4373-4849-b5b7-eddb332a20d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691200328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1691200328
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2157734102
Short name T866
Test name
Test status
Simulation time 54191718 ps
CPU time 1.33 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:53 PM PDT 24
Peak memory 217360 kb
Host smart-eec7b6fe-8c89-4734-ba74-6e6b21d6a29e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157734102 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2157734102
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2984481760
Short name T974
Test name
Test status
Simulation time 14586096 ps
CPU time 0.89 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 206060 kb
Host smart-37d2b663-44ca-4898-aff0-4127f700c5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984481760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2984481760
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3742326729
Short name T896
Test name
Test status
Simulation time 34522196 ps
CPU time 1.45 seconds
Started May 23 03:29:52 PM PDT 24
Finished May 23 03:29:57 PM PDT 24
Peak memory 206228 kb
Host smart-ca1fd74d-73f3-4bed-a8b1-7eac06e24cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742326729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3742326729
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1826639450
Short name T897
Test name
Test status
Simulation time 147015892 ps
CPU time 4.6 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:56 PM PDT 24
Peak memory 214460 kb
Host smart-57ce7fc4-63bc-4fc3-b83b-d87a721139e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826639450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1826639450
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.987323873
Short name T878
Test name
Test status
Simulation time 52794368 ps
CPU time 1.8 seconds
Started May 23 03:29:53 PM PDT 24
Finished May 23 03:29:58 PM PDT 24
Peak memory 206448 kb
Host smart-ada4a581-8ec4-4a48-b51c-a3872353c30e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987323873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.987323873
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.575754169
Short name T886
Test name
Test status
Simulation time 213236033 ps
CPU time 1.67 seconds
Started May 23 03:29:51 PM PDT 24
Finished May 23 03:29:55 PM PDT 24
Peak memory 214516 kb
Host smart-a2da6011-900b-4ce1-b393-921ca2fc8358
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575754169 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.575754169
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2496082023
Short name T227
Test name
Test status
Simulation time 17067764 ps
CPU time 0.81 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 206224 kb
Host smart-510e5236-0b74-4854-9f91-d124232527b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496082023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2496082023
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1826600640
Short name T917
Test name
Test status
Simulation time 22399364 ps
CPU time 0.83 seconds
Started May 23 03:29:48 PM PDT 24
Finished May 23 03:29:51 PM PDT 24
Peak memory 206000 kb
Host smart-7e1eddf5-c3af-4243-b4d6-f2b2776350ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826600640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1826600640
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2213790412
Short name T228
Test name
Test status
Simulation time 49886902 ps
CPU time 0.95 seconds
Started May 23 03:29:49 PM PDT 24
Finished May 23 03:29:51 PM PDT 24
Peak memory 206172 kb
Host smart-b7cd1bcf-fa31-4eef-95fa-2594c1969f95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213790412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2213790412
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2400660628
Short name T863
Test name
Test status
Simulation time 110406029 ps
CPU time 3.01 seconds
Started May 23 03:29:52 PM PDT 24
Finished May 23 03:29:58 PM PDT 24
Peak memory 214460 kb
Host smart-f9d20d25-30f1-4a6b-a2fa-6a4f31643561
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400660628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2400660628
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2893101
Short name T905
Test name
Test status
Simulation time 307141821 ps
CPU time 2.17 seconds
Started May 23 03:29:50 PM PDT 24
Finished May 23 03:29:54 PM PDT 24
Peak memory 214460 kb
Host smart-dae8709d-c490-4542-ad2e-7f107313c035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2893101
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3880879147
Short name T746
Test name
Test status
Simulation time 44947404 ps
CPU time 1.19 seconds
Started May 23 02:50:00 PM PDT 24
Finished May 23 02:50:04 PM PDT 24
Peak memory 215396 kb
Host smart-6c821b6a-bfe0-4e5f-9876-1a5ebcc29086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880879147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3880879147
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.3352183306
Short name T775
Test name
Test status
Simulation time 26771067 ps
CPU time 0.88 seconds
Started May 23 02:50:00 PM PDT 24
Finished May 23 02:50:04 PM PDT 24
Peak memory 214528 kb
Host smart-2ba0b1a9-adae-407b-8f41-c7bdae900507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352183306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3352183306
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.4083471734
Short name T416
Test name
Test status
Simulation time 26684295 ps
CPU time 1.09 seconds
Started May 23 02:49:56 PM PDT 24
Finished May 23 02:49:59 PM PDT 24
Peak memory 219164 kb
Host smart-18fd558e-b2fa-4d6e-bc42-e7625ba16c0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083471734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.4083471734
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1567380406
Short name T657
Test name
Test status
Simulation time 71396338 ps
CPU time 1.05 seconds
Started May 23 02:49:55 PM PDT 24
Finished May 23 02:49:57 PM PDT 24
Peak memory 219080 kb
Host smart-a53fc370-fe6a-4bcb-a74f-dfe838af2671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567380406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1567380406
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.4049184557
Short name T636
Test name
Test status
Simulation time 28556823 ps
CPU time 1.29 seconds
Started May 23 02:49:39 PM PDT 24
Finished May 23 02:49:42 PM PDT 24
Peak memory 216928 kb
Host smart-35875097-f469-47f1-8460-1ab08314aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049184557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.4049184557
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.493002898
Short name T789
Test name
Test status
Simulation time 41220584 ps
CPU time 0.83 seconds
Started May 23 02:49:56 PM PDT 24
Finished May 23 02:49:59 PM PDT 24
Peak memory 215152 kb
Host smart-804e6fa0-813d-4510-9d4c-eb7ff59204d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493002898 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.493002898
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.212271907
Short name T108
Test name
Test status
Simulation time 55300985 ps
CPU time 0.9 seconds
Started May 23 02:49:38 PM PDT 24
Finished May 23 02:49:41 PM PDT 24
Peak memory 206820 kb
Host smart-9d97818e-5607-4942-acb4-7a3fa990c3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212271907 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.212271907
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4016801677
Short name T129
Test name
Test status
Simulation time 915557178 ps
CPU time 4.61 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:06 PM PDT 24
Peak memory 236784 kb
Host smart-d7efb257-4402-4d9f-9e73-e5ef3c715512
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016801677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4016801677
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.380777499
Short name T798
Test name
Test status
Simulation time 17778186 ps
CPU time 1.04 seconds
Started May 23 02:49:39 PM PDT 24
Finished May 23 02:49:42 PM PDT 24
Peak memory 215064 kb
Host smart-869bcb6b-912c-490b-b8dd-24877fd3d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380777499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.380777499
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.2396230426
Short name T730
Test name
Test status
Simulation time 307775775 ps
CPU time 3.62 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:03 PM PDT 24
Peak memory 215020 kb
Host smart-9012dbe8-edec-47b5-b77e-683da914aa17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396230426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.2396230426
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2155655796
Short name T694
Test name
Test status
Simulation time 78826503483 ps
CPU time 2009.78 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 03:23:30 PM PDT 24
Peak memory 228500 kb
Host smart-451d53b1-35d5-4c2d-bc90-b568b9b75a39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155655796 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2155655796
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1294814547
Short name T182
Test name
Test status
Simulation time 41412554 ps
CPU time 1.21 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 215396 kb
Host smart-35a3ac8b-e4d1-49e0-ab6d-4e602565d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294814547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1294814547
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.2553338042
Short name T66
Test name
Test status
Simulation time 13434142 ps
CPU time 0.95 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:02 PM PDT 24
Peak memory 216248 kb
Host smart-393dc289-e30e-42f9-839d-179e72c0662c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553338042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2553338042
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3597065034
Short name T602
Test name
Test status
Simulation time 96463085 ps
CPU time 1.13 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 216576 kb
Host smart-a1346045-1dcb-4f36-90aa-5b1855cca327
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597065034 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3597065034
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.2221957808
Short name T1
Test name
Test status
Simulation time 65717276 ps
CPU time 1.37 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 217820 kb
Host smart-3cdcffe3-bc72-40a0-a58c-2ecb77c2c9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221957808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2221957808
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3553336944
Short name T527
Test name
Test status
Simulation time 49681546 ps
CPU time 1 seconds
Started May 23 02:49:55 PM PDT 24
Finished May 23 02:49:57 PM PDT 24
Peak memory 223260 kb
Host smart-0463abd4-5c8a-47dd-9e6b-d7ef9a87c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553336944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3553336944
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.39985028
Short name T779
Test name
Test status
Simulation time 32109551 ps
CPU time 1.02 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 206848 kb
Host smart-7b9d7a5b-a1e2-4975-9b33-6a5cfa153df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39985028 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.39985028
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.542958873
Short name T588
Test name
Test status
Simulation time 52831969 ps
CPU time 0.98 seconds
Started May 23 02:50:00 PM PDT 24
Finished May 23 02:50:04 PM PDT 24
Peak memory 215024 kb
Host smart-110ce338-a8ad-45aa-ba2e-68a23e3d7b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542958873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.542958873
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2287911516
Short name T546
Test name
Test status
Simulation time 72800535329 ps
CPU time 884.62 seconds
Started May 23 02:50:00 PM PDT 24
Finished May 23 03:04:48 PM PDT 24
Peak memory 220496 kb
Host smart-cbee3bfa-8320-4dec-83e6-13405f561a76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287911516 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2287911516
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2283298339
Short name T634
Test name
Test status
Simulation time 41072962 ps
CPU time 1.24 seconds
Started May 23 02:50:48 PM PDT 24
Finished May 23 02:50:50 PM PDT 24
Peak memory 215424 kb
Host smart-646e5360-ad24-497e-99cb-08310ff74939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283298339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2283298339
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3838122016
Short name T647
Test name
Test status
Simulation time 21992352 ps
CPU time 0.99 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 206344 kb
Host smart-f4d906b7-30ef-4fc7-a946-dc8327196fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838122016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3838122016
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3549763385
Short name T430
Test name
Test status
Simulation time 76035466 ps
CPU time 0.88 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:54 PM PDT 24
Peak memory 215240 kb
Host smart-de81565a-e620-4f17-8671-e20527f5dd66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549763385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3549763385
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3591553721
Short name T17
Test name
Test status
Simulation time 73078030 ps
CPU time 1.08 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216676 kb
Host smart-295f44c4-50ee-4ed3-b219-e4e7e9cf6d5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591553721 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3591553721
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.32230651
Short name T85
Test name
Test status
Simulation time 18231139 ps
CPU time 1.05 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 217728 kb
Host smart-6d2b8f2d-a5c9-4eac-993b-054696dd19f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32230651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.32230651
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2811212087
Short name T601
Test name
Test status
Simulation time 40247994 ps
CPU time 1.45 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 217344 kb
Host smart-fdca1194-dc3c-4d07-8401-de6e2762c7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811212087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2811212087
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3480643526
Short name T111
Test name
Test status
Simulation time 20349107 ps
CPU time 1.1 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:52 PM PDT 24
Peak memory 215400 kb
Host smart-14d17dfc-c2ac-46ec-a68e-e6fc1f032353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480643526 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3480643526
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2356855707
Short name T673
Test name
Test status
Simulation time 18917567 ps
CPU time 0.98 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 214984 kb
Host smart-b7489215-69f6-4a91-956e-e2bb969026d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356855707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2356855707
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3583205251
Short name T752
Test name
Test status
Simulation time 1255033844 ps
CPU time 4.71 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:51:01 PM PDT 24
Peak memory 215048 kb
Host smart-5df85201-29b8-456a-b02a-310609906f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583205251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3583205251
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2995145395
Short name T187
Test name
Test status
Simulation time 49415966932 ps
CPU time 522.07 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:59:35 PM PDT 24
Peak memory 217756 kb
Host smart-2fe77366-aa2f-4492-8fb1-9337f5d680ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995145395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2995145395
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.693270805
Short name T511
Test name
Test status
Simulation time 44346764 ps
CPU time 1.65 seconds
Started May 23 02:53:24 PM PDT 24
Finished May 23 02:53:28 PM PDT 24
Peak memory 216764 kb
Host smart-dc755a42-2c8c-4a0b-b613-cac58b597d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693270805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.693270805
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3483140612
Short name T781
Test name
Test status
Simulation time 52708673 ps
CPU time 1.21 seconds
Started May 23 02:53:25 PM PDT 24
Finished May 23 02:53:29 PM PDT 24
Peak memory 217712 kb
Host smart-307a1bfe-f1f4-4274-b6f1-a517162530fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483140612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3483140612
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.270169883
Short name T596
Test name
Test status
Simulation time 105546236 ps
CPU time 2.21 seconds
Started May 23 02:53:24 PM PDT 24
Finished May 23 02:53:30 PM PDT 24
Peak memory 219580 kb
Host smart-58e62ac6-4cd2-4be9-9ecb-22291c354b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270169883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.270169883
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4102109364
Short name T12
Test name
Test status
Simulation time 100205777 ps
CPU time 1.25 seconds
Started May 23 02:53:25 PM PDT 24
Finished May 23 02:53:29 PM PDT 24
Peak memory 219156 kb
Host smart-2c9b5313-7746-4cf2-b03f-4d4e839afaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102109364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4102109364
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2215017554
Short name T131
Test name
Test status
Simulation time 44597814 ps
CPU time 1.48 seconds
Started May 23 02:53:25 PM PDT 24
Finished May 23 02:53:29 PM PDT 24
Peak memory 215032 kb
Host smart-13823441-1ead-467e-bcb8-8924936bcab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215017554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2215017554
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2182073523
Short name T605
Test name
Test status
Simulation time 139828263 ps
CPU time 1.76 seconds
Started May 23 02:53:24 PM PDT 24
Finished May 23 02:53:29 PM PDT 24
Peak memory 218400 kb
Host smart-c83d5656-7ead-4d1f-bc6f-d12176255815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182073523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2182073523
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.70760926
Short name T768
Test name
Test status
Simulation time 48462567 ps
CPU time 1.79 seconds
Started May 23 02:53:26 PM PDT 24
Finished May 23 02:53:30 PM PDT 24
Peak memory 219604 kb
Host smart-0c2d474d-f957-4195-8ca6-1c5b249b651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70760926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.70760926
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1176887013
Short name T493
Test name
Test status
Simulation time 39237435 ps
CPU time 1.36 seconds
Started May 23 02:53:32 PM PDT 24
Finished May 23 02:53:34 PM PDT 24
Peak memory 217952 kb
Host smart-5b814deb-ebf0-4715-85ba-9e799cd591e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176887013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1176887013
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2591426987
Short name T386
Test name
Test status
Simulation time 106191094 ps
CPU time 1.33 seconds
Started May 23 02:53:33 PM PDT 24
Finished May 23 02:53:36 PM PDT 24
Peak memory 216728 kb
Host smart-9fbb7fe8-5e98-4593-8a2c-2b2b4e917b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591426987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2591426987
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3219667259
Short name T263
Test name
Test status
Simulation time 42879209 ps
CPU time 1.16 seconds
Started May 23 02:53:32 PM PDT 24
Finished May 23 02:53:34 PM PDT 24
Peak memory 216552 kb
Host smart-10914418-4d55-442f-a920-9079f926846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219667259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3219667259
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1770839648
Short name T629
Test name
Test status
Simulation time 17915239 ps
CPU time 0.82 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 206612 kb
Host smart-c861b057-fb9f-4799-a85f-08fe05c9d01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770839648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1770839648
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.345140413
Short name T41
Test name
Test status
Simulation time 42556278 ps
CPU time 1.17 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 229204 kb
Host smart-14591b7e-1163-4300-b76c-b9b513395889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345140413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.345140413
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3973845663
Short name T700
Test name
Test status
Simulation time 34734056 ps
CPU time 1.37 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216652 kb
Host smart-9078b248-5356-438f-90f6-85a31eb2377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973845663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3973845663
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.880671097
Short name T765
Test name
Test status
Simulation time 23519604 ps
CPU time 1.03 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 215016 kb
Host smart-8c4a8be3-0374-4b4a-94ae-8352e391d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880671097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.880671097
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1966552174
Short name T151
Test name
Test status
Simulation time 25288003739 ps
CPU time 325.56 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:56:21 PM PDT 24
Peak memory 223492 kb
Host smart-774e7f3b-050a-453d-bfaf-a990cb082f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966552174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1966552174
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2363983182
Short name T759
Test name
Test status
Simulation time 51437329 ps
CPU time 1.82 seconds
Started May 23 02:53:31 PM PDT 24
Finished May 23 02:53:34 PM PDT 24
Peak memory 218092 kb
Host smart-640a9940-6f68-4b3e-a7fe-a22de9ad6217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363983182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2363983182
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.4109574679
Short name T273
Test name
Test status
Simulation time 73961651 ps
CPU time 1.29 seconds
Started May 23 02:53:31 PM PDT 24
Finished May 23 02:53:33 PM PDT 24
Peak memory 216808 kb
Host smart-e823de4b-4762-4f1b-846c-93c03a5f9402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109574679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.4109574679
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1945095345
Short name T308
Test name
Test status
Simulation time 45955915 ps
CPU time 1.52 seconds
Started May 23 02:53:31 PM PDT 24
Finished May 23 02:53:33 PM PDT 24
Peak memory 217756 kb
Host smart-f4e95f15-febc-46f6-88d7-74ac214c8452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945095345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1945095345
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.353217871
Short name T799
Test name
Test status
Simulation time 44306410 ps
CPU time 1.48 seconds
Started May 23 02:53:35 PM PDT 24
Finished May 23 02:53:38 PM PDT 24
Peak memory 218016 kb
Host smart-66053bd8-f276-4468-9c95-183cf7057288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353217871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.353217871
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1991692971
Short name T332
Test name
Test status
Simulation time 177676036 ps
CPU time 2.74 seconds
Started May 23 02:53:35 PM PDT 24
Finished May 23 02:53:39 PM PDT 24
Peak memory 219712 kb
Host smart-20c00c92-14cd-4ae3-927f-80165f9a0992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991692971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1991692971
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3912867001
Short name T505
Test name
Test status
Simulation time 141399008 ps
CPU time 1.76 seconds
Started May 23 02:53:31 PM PDT 24
Finished May 23 02:53:33 PM PDT 24
Peak memory 218676 kb
Host smart-1463895d-02fd-4d85-94d3-c9b56a635016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912867001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3912867001
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1384450139
Short name T792
Test name
Test status
Simulation time 183065212 ps
CPU time 1.4 seconds
Started May 23 02:53:33 PM PDT 24
Finished May 23 02:53:36 PM PDT 24
Peak memory 217964 kb
Host smart-2a6e6905-d56b-4a31-a3f5-b8781a01bd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384450139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1384450139
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.968811401
Short name T522
Test name
Test status
Simulation time 42648750 ps
CPU time 1.52 seconds
Started May 23 02:53:33 PM PDT 24
Finished May 23 02:53:35 PM PDT 24
Peak memory 217804 kb
Host smart-583fb533-0a48-467e-8110-010669e6fe3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968811401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.968811401
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.4263325100
Short name T492
Test name
Test status
Simulation time 225268034 ps
CPU time 2.65 seconds
Started May 23 02:53:33 PM PDT 24
Finished May 23 02:53:37 PM PDT 24
Peak memory 219488 kb
Host smart-83b06722-e26d-4d61-843c-9874a865f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263325100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.4263325100
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1251246775
Short name T309
Test name
Test status
Simulation time 53883981 ps
CPU time 0.95 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 206352 kb
Host smart-ccb8b1ae-5139-4d57-a745-06666551c5ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251246775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1251246775
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2522769751
Short name T554
Test name
Test status
Simulation time 13901736 ps
CPU time 0.92 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 216244 kb
Host smart-f87476a5-938f-478f-aa5d-d2d52c980b30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522769751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2522769751
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1571547317
Short name T37
Test name
Test status
Simulation time 32852058 ps
CPU time 1.27 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216736 kb
Host smart-abe56b97-d59c-4ba8-af57-38dbd274f431
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571547317 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1571547317
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.2455831558
Short name T378
Test name
Test status
Simulation time 197855026 ps
CPU time 2.42 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 218964 kb
Host smart-392d3360-0cde-4aed-8e49-f476f6ab46ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455831558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2455831558
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3366579760
Short name T497
Test name
Test status
Simulation time 22680934 ps
CPU time 0.94 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 215492 kb
Host smart-7ac3ad0f-7a80-423a-986f-58394de4c92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366579760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3366579760
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.992751530
Short name T326
Test name
Test status
Simulation time 86023740 ps
CPU time 0.93 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:51 PM PDT 24
Peak memory 214984 kb
Host smart-e4e57fbe-8633-4521-9acd-e5b07360d110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992751530 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.992751530
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.226067706
Short name T676
Test name
Test status
Simulation time 923225178 ps
CPU time 2.95 seconds
Started May 23 02:50:48 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 215036 kb
Host smart-58a63a3b-4365-4654-8afc-ba7d2336b688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226067706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.226067706
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1246341067
Short name T188
Test name
Test status
Simulation time 865010401860 ps
CPU time 1545.22 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 03:16:36 PM PDT 24
Peak memory 223400 kb
Host smart-18b8b3cb-e731-498c-9edf-5e37cab5c09d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246341067 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1246341067
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.999182227
Short name T661
Test name
Test status
Simulation time 68995437 ps
CPU time 1.21 seconds
Started May 23 02:53:32 PM PDT 24
Finished May 23 02:53:35 PM PDT 24
Peak memory 216828 kb
Host smart-e5f90765-8821-4746-8170-325fbe243d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999182227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.999182227
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.325294816
Short name T603
Test name
Test status
Simulation time 102777477 ps
CPU time 1.35 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:50 PM PDT 24
Peak memory 218292 kb
Host smart-ab315de2-0f1d-46e2-80bb-82fd6c1bc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325294816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.325294816
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1373379380
Short name T712
Test name
Test status
Simulation time 69130848 ps
CPU time 1.5 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 218508 kb
Host smart-2cae9fc2-0937-4972-862a-9f85f7541be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373379380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1373379380
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2664395974
Short name T323
Test name
Test status
Simulation time 54311044 ps
CPU time 1.28 seconds
Started May 23 02:53:50 PM PDT 24
Finished May 23 02:53:56 PM PDT 24
Peak memory 216732 kb
Host smart-edb35f99-5687-40bb-a8d5-dd37649ce6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664395974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2664395974
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.978884226
Short name T119
Test name
Test status
Simulation time 81253742 ps
CPU time 1.28 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:51 PM PDT 24
Peak memory 216756 kb
Host smart-580c2e8c-1ce1-4459-84fc-e30bb9f665ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978884226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.978884226
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2013485830
Short name T483
Test name
Test status
Simulation time 54778707 ps
CPU time 1.15 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:50 PM PDT 24
Peak memory 216768 kb
Host smart-67715be1-699e-4eb8-9b1c-ffde49707cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013485830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2013485830
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.700174879
Short name T599
Test name
Test status
Simulation time 115398591 ps
CPU time 0.98 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 216612 kb
Host smart-b618168e-fb2f-44cd-91ea-43419e7652c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700174879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.700174879
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1573995104
Short name T202
Test name
Test status
Simulation time 58960643 ps
CPU time 1.77 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 218180 kb
Host smart-98989f66-2f8d-4005-9de0-c48ae44d928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573995104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1573995104
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1306180096
Short name T660
Test name
Test status
Simulation time 55139662 ps
CPU time 1.15 seconds
Started May 23 02:53:51 PM PDT 24
Finished May 23 02:53:56 PM PDT 24
Peak memory 218848 kb
Host smart-dd8764a1-abbb-4f0f-a441-90762e0586b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306180096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1306180096
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.707769942
Short name T701
Test name
Test status
Simulation time 29187931 ps
CPU time 1.32 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 215408 kb
Host smart-6c4adee2-c996-48f7-b78f-daaea0324a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707769942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.707769942
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2299225023
Short name T461
Test name
Test status
Simulation time 18894218 ps
CPU time 1.09 seconds
Started May 23 02:51:04 PM PDT 24
Finished May 23 02:51:06 PM PDT 24
Peak memory 214548 kb
Host smart-981757b8-db63-49ee-abfd-7b33f8cb7c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299225023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2299225023
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.127635688
Short name T626
Test name
Test status
Simulation time 68383335 ps
CPU time 0.88 seconds
Started May 23 02:51:03 PM PDT 24
Finished May 23 02:51:05 PM PDT 24
Peak memory 216096 kb
Host smart-cb050224-0a72-4e18-b1f0-b537197ad6fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127635688 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.127635688
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2279223684
Short name T543
Test name
Test status
Simulation time 94494606 ps
CPU time 1.05 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 02:51:07 PM PDT 24
Peak memory 219332 kb
Host smart-d370eaba-6a2d-4a91-b07a-c7ed2e9a401e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279223684 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2279223684
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2127495008
Short name T710
Test name
Test status
Simulation time 43359328 ps
CPU time 0.97 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 223324 kb
Host smart-4b8e3865-59aa-4b8b-bab2-a28a1b471a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127495008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2127495008
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3974584291
Short name T307
Test name
Test status
Simulation time 43584572 ps
CPU time 1.49 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 217792 kb
Host smart-64eb030e-f81c-43f8-ad19-e2d201685fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974584291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3974584291
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.68350856
Short name T714
Test name
Test status
Simulation time 18817541 ps
CPU time 1.11 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 214652 kb
Host smart-9be1d6d1-af33-48df-a52d-e22f261b3ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68350856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.68350856
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.288203950
Short name T397
Test name
Test status
Simulation time 389528881 ps
CPU time 4.98 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 216780 kb
Host smart-5de888df-5237-4084-802a-1e63b1474e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288203950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.288203950
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2077493116
Short name T726
Test name
Test status
Simulation time 120204214818 ps
CPU time 667.93 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 03:02:04 PM PDT 24
Peak memory 223404 kb
Host smart-e24b28c2-ea48-4e11-92bf-0901b4a47b66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077493116 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2077493116
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1466283740
Short name T745
Test name
Test status
Simulation time 82716722 ps
CPU time 1.14 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 219420 kb
Host smart-6328f48e-fb87-4807-8cc8-54dd609949e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466283740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1466283740
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3354893425
Short name T793
Test name
Test status
Simulation time 56899867 ps
CPU time 1.36 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 216736 kb
Host smart-8c936e80-951c-49ba-a516-ed614a36d98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354893425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3354893425
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1916816739
Short name T392
Test name
Test status
Simulation time 33229202 ps
CPU time 1.3 seconds
Started May 23 02:53:50 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 216804 kb
Host smart-69e1c2ed-93a5-4ab5-9a75-98097559bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916816739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1916816739
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2332463022
Short name T833
Test name
Test status
Simulation time 69043598 ps
CPU time 1.11 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218044 kb
Host smart-79250537-4845-4e05-93dd-d13b78982eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332463022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2332463022
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3308048262
Short name T487
Test name
Test status
Simulation time 24633109 ps
CPU time 1.24 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 216796 kb
Host smart-c81bd1fa-cb37-4125-9772-cdb05f76120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308048262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3308048262
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3804819980
Short name T839
Test name
Test status
Simulation time 35558263 ps
CPU time 1.41 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 217900 kb
Host smart-d7371f0e-6106-41f3-9c55-eba4b0ff6f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804819980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3804819980
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.803192209
Short name T312
Test name
Test status
Simulation time 66940735 ps
CPU time 1.18 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:51 PM PDT 24
Peak memory 218352 kb
Host smart-cefcb3d2-4232-4c17-bdbf-e585d9b6e915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803192209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.803192209
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4017179869
Short name T591
Test name
Test status
Simulation time 151801152 ps
CPU time 3.15 seconds
Started May 23 02:53:50 PM PDT 24
Finished May 23 02:53:57 PM PDT 24
Peak memory 219064 kb
Host smart-8a85de94-39ce-4544-bf0b-49a1f61c0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017179869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4017179869
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3715478649
Short name T366
Test name
Test status
Simulation time 64190910 ps
CPU time 1.34 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 217904 kb
Host smart-a2b4334e-d0c9-4585-b35f-fb0df8e8187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715478649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3715478649
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.4248367146
Short name T815
Test name
Test status
Simulation time 78055162 ps
CPU time 1.2 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 215396 kb
Host smart-a34606dd-2a17-4728-b4f1-55990a283c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248367146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.4248367146
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1350657024
Short name T156
Test name
Test status
Simulation time 19205626 ps
CPU time 0.99 seconds
Started May 23 02:51:07 PM PDT 24
Finished May 23 02:51:10 PM PDT 24
Peak memory 206328 kb
Host smart-b9d0f9be-bcbb-4fd0-b233-d467eca180c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350657024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1350657024
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.237766454
Short name T447
Test name
Test status
Simulation time 10580661 ps
CPU time 0.91 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 215268 kb
Host smart-f23f329e-fdaf-4063-bfdd-3df5de6902df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237766454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.237766454
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.125955464
Short name T587
Test name
Test status
Simulation time 82499895 ps
CPU time 1.07 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 216688 kb
Host smart-a751f019-54b7-47b1-baa0-c00a32a18434
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125955464 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.125955464
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.619803861
Short name T395
Test name
Test status
Simulation time 21702532 ps
CPU time 1.05 seconds
Started May 23 02:51:08 PM PDT 24
Finished May 23 02:51:11 PM PDT 24
Peak memory 217928 kb
Host smart-9d3ef1db-14f2-42ca-a13a-4ceae2ceea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619803861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.619803861
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1600034288
Short name T357
Test name
Test status
Simulation time 99053869 ps
CPU time 1.22 seconds
Started May 23 02:51:06 PM PDT 24
Finished May 23 02:51:09 PM PDT 24
Peak memory 217972 kb
Host smart-7ae61c9f-9b5d-4749-890f-6359257321a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600034288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1600034288
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3641677574
Short name T519
Test name
Test status
Simulation time 24845627 ps
CPU time 0.96 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 02:51:08 PM PDT 24
Peak memory 215292 kb
Host smart-63bee301-6f93-49d9-a78c-a46870eaec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641677574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3641677574
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.387729331
Short name T317
Test name
Test status
Simulation time 20164685 ps
CPU time 1.03 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 206820 kb
Host smart-507672f1-d82c-4eac-adba-d7d55d4fc12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387729331 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.387729331
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2542747827
Short name T747
Test name
Test status
Simulation time 236051259410 ps
CPU time 1359.44 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 03:13:46 PM PDT 24
Peak memory 223100 kb
Host smart-7e7665f0-f901-4b4c-9a1c-f5005d6897b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542747827 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2542747827
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.4270701959
Short name T778
Test name
Test status
Simulation time 162228942 ps
CPU time 1.41 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 218316 kb
Host smart-7e0a423e-868d-43c8-b317-349bcd6ea6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270701959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4270701959
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.4216166147
Short name T304
Test name
Test status
Simulation time 22554099 ps
CPU time 1.12 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 216740 kb
Host smart-85df4a7b-b63d-42e3-a4ad-91bf609b306f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216166147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4216166147
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1650075071
Short name T659
Test name
Test status
Simulation time 133586681 ps
CPU time 1.47 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218236 kb
Host smart-f8b07bac-0723-4f7a-bdb1-38cfd741cb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650075071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1650075071
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.3721908198
Short name T426
Test name
Test status
Simulation time 38298084 ps
CPU time 1.59 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218644 kb
Host smart-42d95804-58b5-490d-8240-1eebca392d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721908198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.3721908198
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.4167712206
Short name T826
Test name
Test status
Simulation time 48625787 ps
CPU time 1.13 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:48 PM PDT 24
Peak memory 216640 kb
Host smart-f164047f-9bac-4076-9b9a-752e4dcf9693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167712206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4167712206
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3802055708
Short name T139
Test name
Test status
Simulation time 114207387 ps
CPU time 1.72 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 218120 kb
Host smart-9e68a82c-7832-4238-91c2-b05ee7e05555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802055708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3802055708
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.787641527
Short name T682
Test name
Test status
Simulation time 77953699 ps
CPU time 1.13 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 216864 kb
Host smart-35f9dcda-5fe1-4b2b-b8cd-2c568a68de4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787641527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.787641527
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.958508741
Short name T717
Test name
Test status
Simulation time 62782399 ps
CPU time 1.12 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 216752 kb
Host smart-abfdcc70-a404-45ad-8500-93537cc02dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958508741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.958508741
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.714615483
Short name T26
Test name
Test status
Simulation time 88638188 ps
CPU time 1.28 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:14 PM PDT 24
Peak memory 215412 kb
Host smart-2476ca54-ea58-4e35-9db7-18a6fe012574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714615483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.714615483
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3554339670
Short name T490
Test name
Test status
Simulation time 26735827 ps
CPU time 0.91 seconds
Started May 23 02:51:06 PM PDT 24
Finished May 23 02:51:08 PM PDT 24
Peak memory 214800 kb
Host smart-e0f176fd-03d2-48ce-9f40-2c97fe1e3c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554339670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3554339670
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1149200112
Short name T23
Test name
Test status
Simulation time 22322897 ps
CPU time 0.93 seconds
Started May 23 02:51:03 PM PDT 24
Finished May 23 02:51:05 PM PDT 24
Peak memory 216356 kb
Host smart-40008550-d28f-44ad-83f1-3e4861f1b73b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149200112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1149200112
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2107921346
Short name T34
Test name
Test status
Simulation time 59650211 ps
CPU time 1.09 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 229200 kb
Host smart-7a73141f-7f8b-4a09-9816-b218c318ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107921346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2107921346
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.4213415125
Short name T240
Test name
Test status
Simulation time 81610241 ps
CPU time 1.16 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 215088 kb
Host smart-8cb18c27-8593-466b-88ef-bca181026644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213415125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.4213415125
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3682395031
Short name T617
Test name
Test status
Simulation time 89627319 ps
CPU time 0.9 seconds
Started May 23 02:51:07 PM PDT 24
Finished May 23 02:51:10 PM PDT 24
Peak memory 214972 kb
Host smart-482d3d61-d59a-4ab5-af79-f622cec92b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682395031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3682395031
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1729794304
Short name T149
Test name
Test status
Simulation time 41623093 ps
CPU time 0.9 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 215032 kb
Host smart-87c10f48-cc2a-425f-b737-09c2d0dad50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729794304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1729794304
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.519593377
Short name T515
Test name
Test status
Simulation time 365406793 ps
CPU time 3.89 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:16 PM PDT 24
Peak memory 215028 kb
Host smart-492ace59-c360-42ec-a0c9-e23a5343d973
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519593377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.519593377
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.420829977
Short name T328
Test name
Test status
Simulation time 114804224858 ps
CPU time 1492.28 seconds
Started May 23 02:51:06 PM PDT 24
Finished May 23 03:16:00 PM PDT 24
Peak memory 225924 kb
Host smart-026dc41c-8b09-4860-b52c-3b679ab073ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420829977 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.420829977
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1753590489
Short name T736
Test name
Test status
Simulation time 93762191 ps
CPU time 1.62 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218180 kb
Host smart-55803edf-a14b-4252-80b1-51158865fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753590489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1753590489
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1607278829
Short name T783
Test name
Test status
Simulation time 73030362 ps
CPU time 1.41 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 217752 kb
Host smart-97020762-75ff-4490-9b21-c1662528fe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607278829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1607278829
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.271643600
Short name T803
Test name
Test status
Simulation time 37757338 ps
CPU time 1.37 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 216736 kb
Host smart-2811b23f-cadc-4247-bc6b-77902e468c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271643600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.271643600
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1084370663
Short name T512
Test name
Test status
Simulation time 39759143 ps
CPU time 1.43 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 219388 kb
Host smart-27127ecc-2ceb-4844-9615-f8a3bd82a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084370663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1084370663
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1664236110
Short name T337
Test name
Test status
Simulation time 67920245 ps
CPU time 1.52 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 218180 kb
Host smart-7d1a63b5-61b0-4b38-9c3e-ce9e00a765c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664236110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1664236110
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1862793416
Short name T621
Test name
Test status
Simulation time 100936269 ps
CPU time 1.15 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218772 kb
Host smart-291d2e61-a6c7-4a89-aeab-e53a41bfb5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862793416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1862793416
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.290668151
Short name T457
Test name
Test status
Simulation time 109501642 ps
CPU time 1.35 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 218100 kb
Host smart-449611ea-7d1b-4b23-aa6a-7d738532603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290668151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.290668151
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1925269042
Short name T552
Test name
Test status
Simulation time 32076898 ps
CPU time 1.32 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 217924 kb
Host smart-28e04936-d183-4f2b-ac59-dbbf26a5476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925269042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1925269042
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3852062888
Short name T154
Test name
Test status
Simulation time 95286838 ps
CPU time 1.32 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 02:51:07 PM PDT 24
Peak memory 215400 kb
Host smart-4a3faf84-f383-4ef1-a829-ea8b6f750669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852062888 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3852062888
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3906822442
Short name T782
Test name
Test status
Simulation time 49967374 ps
CPU time 1.05 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 206464 kb
Host smart-61bfbcb2-63b5-4db8-b987-45a7cb187e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906822442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3906822442
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2348396963
Short name T24
Test name
Test status
Simulation time 16571752 ps
CPU time 0.91 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 215740 kb
Host smart-502e1aa7-992e-4cc8-908f-214c724dee72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348396963 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2348396963
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.754981582
Short name T812
Test name
Test status
Simulation time 18329102 ps
CPU time 1.2 seconds
Started May 23 02:51:08 PM PDT 24
Finished May 23 02:51:11 PM PDT 24
Peak memory 218236 kb
Host smart-06d1adfa-498b-4720-98c8-344603b51c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754981582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.754981582
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2999118183
Short name T403
Test name
Test status
Simulation time 42716674 ps
CPU time 1.52 seconds
Started May 23 02:51:07 PM PDT 24
Finished May 23 02:51:10 PM PDT 24
Peak memory 216632 kb
Host smart-298d9dbb-cfe1-4109-86eb-29379260596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999118183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2999118183
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.721907551
Short name T509
Test name
Test status
Simulation time 50707396 ps
CPU time 0.89 seconds
Started May 23 02:51:06 PM PDT 24
Finished May 23 02:51:09 PM PDT 24
Peak memory 214972 kb
Host smart-a288790e-7a03-4be6-ae9a-5680ca2d1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721907551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.721907551
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1990214826
Short name T393
Test name
Test status
Simulation time 61259445 ps
CPU time 0.97 seconds
Started May 23 02:51:07 PM PDT 24
Finished May 23 02:51:09 PM PDT 24
Peak memory 214992 kb
Host smart-cb9bbc6f-976b-4b26-9f57-875ff156944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990214826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1990214826
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3515950014
Short name T194
Test name
Test status
Simulation time 268899465 ps
CPU time 5.26 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:17 PM PDT 24
Peak memory 217948 kb
Host smart-7762c40f-26bc-4afa-bc7c-22adcb9d58eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515950014 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3515950014
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3986067895
Short name T804
Test name
Test status
Simulation time 67339728548 ps
CPU time 1510.47 seconds
Started May 23 02:51:03 PM PDT 24
Finished May 23 03:16:14 PM PDT 24
Peak memory 222468 kb
Host smart-3edd430d-72e0-471b-9c24-4b6fcf70e65e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986067895 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3986067895
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1046415444
Short name T795
Test name
Test status
Simulation time 400898482 ps
CPU time 1.26 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:51 PM PDT 24
Peak memory 216820 kb
Host smart-d7b4bed9-f78a-45cd-a5ee-601fa8bb1afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046415444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1046415444
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3322542025
Short name T649
Test name
Test status
Simulation time 32627153 ps
CPU time 1.35 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 219320 kb
Host smart-64d5e69a-58a2-4c94-a312-296f952c2d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322542025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3322542025
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1800615066
Short name T742
Test name
Test status
Simulation time 61956473 ps
CPU time 1.46 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 218080 kb
Host smart-1ae75ff4-5f69-4307-9cc9-a7bc91bc4aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800615066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1800615066
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2255697567
Short name T409
Test name
Test status
Simulation time 76711442 ps
CPU time 1.06 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 216696 kb
Host smart-ecf6d6d6-a9e7-4756-8f02-05ab9b31e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255697567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2255697567
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3725201955
Short name T18
Test name
Test status
Simulation time 160655391 ps
CPU time 2.42 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 219084 kb
Host smart-2dc9eb73-0c7c-44c2-8311-eaf86d850afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725201955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3725201955
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2176671987
Short name T322
Test name
Test status
Simulation time 59830524 ps
CPU time 1.39 seconds
Started May 23 02:53:50 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 218080 kb
Host smart-ddbf6eb3-f063-49e0-8691-ba0a662beeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176671987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2176671987
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.393758271
Short name T420
Test name
Test status
Simulation time 135455990 ps
CPU time 1.29 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:55 PM PDT 24
Peak memory 216796 kb
Host smart-6f11d774-4ea0-4984-8cc7-9fe70c88a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393758271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.393758271
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2844736818
Short name T689
Test name
Test status
Simulation time 32794786 ps
CPU time 1.39 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 218924 kb
Host smart-a131638e-2514-426c-8007-f39208799948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844736818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2844736818
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2793683946
Short name T432
Test name
Test status
Simulation time 155857554 ps
CPU time 1.32 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218144 kb
Host smart-981ec9e6-eefd-42a9-894a-fd70eb6c6a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793683946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2793683946
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.2775018271
Short name T713
Test name
Test status
Simulation time 18326133 ps
CPU time 0.9 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 206332 kb
Host smart-2f5c3991-61e2-48c1-bd76-404cb60b20de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775018271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2775018271
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3268892924
Short name T816
Test name
Test status
Simulation time 41729308 ps
CPU time 0.9 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 216076 kb
Host smart-3a6c2361-872e-4f9c-83e5-fe1577a7a06d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268892924 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3268892924
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3005795064
Short name T55
Test name
Test status
Simulation time 40451452 ps
CPU time 1.27 seconds
Started May 23 02:51:07 PM PDT 24
Finished May 23 02:51:10 PM PDT 24
Peak memory 216588 kb
Host smart-a81ef169-a6b9-4dbd-9f07-eacc2a540c91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005795064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3005795064
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.3452895421
Short name T239
Test name
Test status
Simulation time 44476193 ps
CPU time 1.21 seconds
Started May 23 02:51:11 PM PDT 24
Finished May 23 02:51:15 PM PDT 24
Peak memory 218140 kb
Host smart-2b9c2ad6-9cf7-4fce-ae06-590c097baa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452895421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3452895421
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.192854638
Short name T110
Test name
Test status
Simulation time 25047142 ps
CPU time 0.95 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:13 PM PDT 24
Peak memory 215412 kb
Host smart-a189ee68-c8f0-45db-811d-a19ff17bc755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192854638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.192854638
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3043319839
Short name T498
Test name
Test status
Simulation time 17683400 ps
CPU time 1.02 seconds
Started May 23 02:51:11 PM PDT 24
Finished May 23 02:51:14 PM PDT 24
Peak memory 214884 kb
Host smart-146647f8-b57a-4308-af99-8aca1a115491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043319839 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3043319839
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.964548477
Short name T335
Test name
Test status
Simulation time 426685915 ps
CPU time 1.76 seconds
Started May 23 02:51:11 PM PDT 24
Finished May 23 02:51:15 PM PDT 24
Peak memory 216712 kb
Host smart-d2ce263d-8460-4dc5-95f5-013cf9ba4ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964548477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.964548477
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3957435794
Short name T754
Test name
Test status
Simulation time 398570784866 ps
CPU time 1107.29 seconds
Started May 23 02:51:11 PM PDT 24
Finished May 23 03:09:41 PM PDT 24
Peak memory 230500 kb
Host smart-5352e790-9916-4bdf-81d0-c23669f32e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957435794 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3957435794
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2160738557
Short name T813
Test name
Test status
Simulation time 40610461 ps
CPU time 1.54 seconds
Started May 23 02:53:46 PM PDT 24
Finished May 23 02:53:49 PM PDT 24
Peak memory 219060 kb
Host smart-9d0d50d5-88fd-49e4-a255-b1a86699b0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160738557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2160738557
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1451706725
Short name T577
Test name
Test status
Simulation time 98494990 ps
CPU time 1.01 seconds
Started May 23 02:53:49 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 216884 kb
Host smart-5d00289f-8954-413b-96b3-2129b35492b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451706725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1451706725
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3484173332
Short name T313
Test name
Test status
Simulation time 50502566 ps
CPU time 1.22 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 216700 kb
Host smart-e453879b-c37e-40bc-8e90-b3786693b27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484173332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3484173332
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.976306939
Short name T195
Test name
Test status
Simulation time 108945741 ps
CPU time 1.31 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218432 kb
Host smart-a5a78ebb-d9b3-4047-a4bf-16186e3a45b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976306939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.976306939
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3519576923
Short name T743
Test name
Test status
Simulation time 72877150 ps
CPU time 2.02 seconds
Started May 23 02:53:47 PM PDT 24
Finished May 23 02:53:52 PM PDT 24
Peak memory 218540 kb
Host smart-7bd1c0bf-4b67-4b9c-a988-34af595f4c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519576923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3519576923
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.5617234
Short name T630
Test name
Test status
Simulation time 84268192 ps
CPU time 1.32 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:53 PM PDT 24
Peak memory 217112 kb
Host smart-4d714dfa-81cb-4ba3-b1a8-b3d3fdd3cba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5617234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.5617234
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.809904472
Short name T481
Test name
Test status
Simulation time 39011250 ps
CPU time 1.48 seconds
Started May 23 02:53:48 PM PDT 24
Finished May 23 02:53:54 PM PDT 24
Peak memory 216844 kb
Host smart-b9869b2b-b2b9-421d-8260-4c25aa8a4c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809904472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.809904472
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2594269397
Short name T523
Test name
Test status
Simulation time 55118174 ps
CPU time 2.1 seconds
Started May 23 02:54:00 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 219804 kb
Host smart-d869ad43-ab4b-4d0b-974e-d4cfde76ece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594269397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2594269397
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3787235472
Short name T254
Test name
Test status
Simulation time 101734426 ps
CPU time 1.25 seconds
Started May 23 02:51:04 PM PDT 24
Finished May 23 02:51:06 PM PDT 24
Peak memory 215404 kb
Host smart-484e3d52-8701-4c9d-abbc-2b4a1170585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787235472 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3787235472
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2133524211
Short name T336
Test name
Test status
Simulation time 14892853 ps
CPU time 0.92 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:12 PM PDT 24
Peak memory 214548 kb
Host smart-5b7c3318-56a1-42a7-a542-b3d92dedcc47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133524211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2133524211
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3910520641
Short name T344
Test name
Test status
Simulation time 14541840 ps
CPU time 0.88 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:11 PM PDT 24
Peak memory 215744 kb
Host smart-01ccf682-5937-48ff-a161-bed6572d35f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910520641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3910520641
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.520879110
Short name T84
Test name
Test status
Simulation time 18254182 ps
CPU time 1.05 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:14 PM PDT 24
Peak memory 218084 kb
Host smart-38cf0d80-fe1e-495b-bae1-5c66779d7afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520879110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.520879110
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.138396635
Short name T361
Test name
Test status
Simulation time 123876918 ps
CPU time 1.3 seconds
Started May 23 02:51:05 PM PDT 24
Finished May 23 02:51:08 PM PDT 24
Peak memory 219376 kb
Host smart-f30356af-5b1d-4c21-8555-2ba2b0c13b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138396635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.138396635
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.4004101826
Short name T537
Test name
Test status
Simulation time 20021738 ps
CPU time 1.09 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 02:51:14 PM PDT 24
Peak memory 215420 kb
Host smart-05caf6e8-47ff-4ea2-935f-f89738615675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004101826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.4004101826
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3177619976
Short name T811
Test name
Test status
Simulation time 17304089 ps
CPU time 1.04 seconds
Started May 23 02:51:06 PM PDT 24
Finished May 23 02:51:09 PM PDT 24
Peak memory 214968 kb
Host smart-2582b73e-91a1-4073-a855-4a9f8093af2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177619976 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3177619976
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1384025213
Short name T103
Test name
Test status
Simulation time 850158724 ps
CPU time 4.77 seconds
Started May 23 02:51:09 PM PDT 24
Finished May 23 02:51:16 PM PDT 24
Peak memory 215032 kb
Host smart-a17a3542-18bd-4fba-9ee0-0edbbacf1dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384025213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1384025213
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.966761460
Short name T147
Test name
Test status
Simulation time 72147950651 ps
CPU time 859.34 seconds
Started May 23 02:51:10 PM PDT 24
Finished May 23 03:05:32 PM PDT 24
Peak memory 219148 kb
Host smart-f9cd46ad-7346-4616-bc2c-6ebddd5d8927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966761460 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.966761460
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1011154268
Short name T268
Test name
Test status
Simulation time 40537576 ps
CPU time 1.44 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 218244 kb
Host smart-8fa52a96-9903-49a6-9a44-935299ee49e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011154268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1011154268
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2695415755
Short name T470
Test name
Test status
Simulation time 67300723 ps
CPU time 2.51 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 218748 kb
Host smart-d0e6ce25-a475-4f80-b6e5-d2b95fbe87df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695415755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2695415755
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1229691556
Short name T473
Test name
Test status
Simulation time 48216490 ps
CPU time 1.24 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 218756 kb
Host smart-fd3bab39-6ccf-40b4-98fa-a39a47d8d823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229691556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1229691556
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1945879798
Short name T377
Test name
Test status
Simulation time 57292258 ps
CPU time 1.36 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 216652 kb
Host smart-f4a23df4-eacf-4b5b-b5bb-cfe9360af522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945879798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1945879798
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3523082720
Short name T806
Test name
Test status
Simulation time 82564689 ps
CPU time 1.58 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 217980 kb
Host smart-bd5c6e1c-5ee8-437c-a669-4ed3ec5dba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523082720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3523082720
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3362558500
Short name T318
Test name
Test status
Simulation time 57173379 ps
CPU time 1.63 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218016 kb
Host smart-7e02e800-5ee1-4c5c-b4be-0fd988a12c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362558500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3362558500
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2852472270
Short name T513
Test name
Test status
Simulation time 45941971 ps
CPU time 1.4 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:08 PM PDT 24
Peak memory 216672 kb
Host smart-19da8922-2c21-4b25-b095-d098d6072bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852472270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2852472270
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.851847880
Short name T651
Test name
Test status
Simulation time 46868902 ps
CPU time 1.94 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 215020 kb
Host smart-54f2577c-5b96-4e6b-8b1d-51127f6947f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851847880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.851847880
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2389198424
Short name T532
Test name
Test status
Simulation time 38430133 ps
CPU time 1.39 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 216524 kb
Host smart-e59f72b1-8b61-4433-8809-6df153ce7aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389198424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2389198424
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.4274088873
Short name T542
Test name
Test status
Simulation time 17028593 ps
CPU time 0.9 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 214352 kb
Host smart-8913aea8-8e73-4401-98c2-6e417c72c7bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274088873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4274088873
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2865203443
Short name T685
Test name
Test status
Simulation time 23554999 ps
CPU time 0.89 seconds
Started May 23 02:51:25 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215744 kb
Host smart-fa390360-508c-49ad-94bf-7dad8b665b4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865203443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2865203443
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.113870842
Short name T52
Test name
Test status
Simulation time 57706777 ps
CPU time 1.35 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 216724 kb
Host smart-4408ae7a-869d-4b51-8208-72e3b380892c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113870842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.113870842
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.1331679393
Short name T791
Test name
Test status
Simulation time 23719415 ps
CPU time 1 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 218264 kb
Host smart-faab4d3e-452e-4b57-8de6-a445aa3753a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331679393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1331679393
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.576460482
Short name T453
Test name
Test status
Simulation time 38659333 ps
CPU time 1.58 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:28 PM PDT 24
Peak memory 219508 kb
Host smart-5db4d8d4-81d1-4f91-9335-ef50b88ab35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576460482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.576460482
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1305308882
Short name T142
Test name
Test status
Simulation time 37914412 ps
CPU time 0.83 seconds
Started May 23 02:51:24 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215284 kb
Host smart-b86dba40-e1db-4bc8-9e73-4137368df47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305308882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1305308882
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2119838809
Short name T341
Test name
Test status
Simulation time 30024348 ps
CPU time 1 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 206892 kb
Host smart-ca4732db-4212-4cb2-ba60-9d22460f002d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119838809 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2119838809
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2424416229
Short name T376
Test name
Test status
Simulation time 241260541 ps
CPU time 3.83 seconds
Started May 23 02:51:18 PM PDT 24
Finished May 23 02:51:24 PM PDT 24
Peak memory 215004 kb
Host smart-9c717d74-8428-48b1-854a-feac8b35bf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424416229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2424416229
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4098448479
Short name T585
Test name
Test status
Simulation time 72843636485 ps
CPU time 1491.08 seconds
Started May 23 02:51:23 PM PDT 24
Finished May 23 03:16:18 PM PDT 24
Peak memory 223640 kb
Host smart-e52e0a21-0fb4-4aef-876c-7d46881cdddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098448479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4098448479
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.179496420
Short name T631
Test name
Test status
Simulation time 126615159 ps
CPU time 1.46 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 218072 kb
Host smart-312cd1d1-3bd5-46f9-a92d-5da0b73c81ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179496420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.179496420
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.4149175336
Short name T451
Test name
Test status
Simulation time 189647191 ps
CPU time 1.49 seconds
Started May 23 02:54:00 PM PDT 24
Finished May 23 02:54:04 PM PDT 24
Peak memory 216496 kb
Host smart-d5c19e0a-c584-462b-a013-b18bec1377e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149175336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.4149175336
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4171822606
Short name T126
Test name
Test status
Simulation time 97361096 ps
CPU time 1.57 seconds
Started May 23 02:54:06 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 218388 kb
Host smart-73118217-078c-4f7b-8dfa-50c469a4873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171822606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4171822606
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.890860951
Short name T573
Test name
Test status
Simulation time 55764528 ps
CPU time 1.72 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 216792 kb
Host smart-17b270e9-e182-40c6-9c1a-1a538fb5c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890860951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.890860951
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3504570010
Short name T568
Test name
Test status
Simulation time 36726987 ps
CPU time 1.18 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 216764 kb
Host smart-46b080b1-6ee7-404e-8d2b-94c448ade348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504570010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3504570010
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3424189138
Short name T640
Test name
Test status
Simulation time 77704567 ps
CPU time 2.61 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 218008 kb
Host smart-8fcbfa81-747a-49a5-85cb-eca6ac3491e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424189138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3424189138
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3932365959
Short name T702
Test name
Test status
Simulation time 110237605 ps
CPU time 1.69 seconds
Started May 23 02:54:00 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218220 kb
Host smart-78b259bb-41ad-4bf8-b223-39b087e97589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932365959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3932365959
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2188257614
Short name T302
Test name
Test status
Simulation time 101496615 ps
CPU time 1.61 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:07 PM PDT 24
Peak memory 218336 kb
Host smart-7fff382d-9203-4764-9cc6-0d7f4f932fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188257614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2188257614
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.637481700
Short name T414
Test name
Test status
Simulation time 53673945 ps
CPU time 1.13 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218308 kb
Host smart-bb02eabc-9b83-478f-a61e-0cc5e6064b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637481700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.637481700
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3163178827
Short name T439
Test name
Test status
Simulation time 44359274 ps
CPU time 1.75 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:07 PM PDT 24
Peak memory 216804 kb
Host smart-3cff4771-8d68-49fc-8c74-0fdae5121c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163178827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3163178827
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4025833210
Short name T751
Test name
Test status
Simulation time 51735859 ps
CPU time 1.13 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 215284 kb
Host smart-82b45292-aebc-421c-bb5e-d5f5f168abb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025833210 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4025833210
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.4239427342
Short name T399
Test name
Test status
Simulation time 23451481 ps
CPU time 0.91 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 206216 kb
Host smart-c948af9d-8bb0-40ca-adbb-f1d88e0e5362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239427342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4239427342
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3867806885
Short name T173
Test name
Test status
Simulation time 11572727 ps
CPU time 0.91 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 216244 kb
Host smart-985d3e49-7d22-4a35-b4e8-80a5f5310e20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867806885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3867806885
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1135914685
Short name T57
Test name
Test status
Simulation time 122898760 ps
CPU time 1.02 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 216608 kb
Host smart-b5a3278d-196e-4c1e-ac4c-e041913b4ee2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135914685 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1135914685
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4217505275
Short name T645
Test name
Test status
Simulation time 27053889 ps
CPU time 1.34 seconds
Started May 23 02:50:00 PM PDT 24
Finished May 23 02:50:04 PM PDT 24
Peak memory 225132 kb
Host smart-4575f92f-eb61-422b-b9c2-9756c87316d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217505275 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4217505275
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.820114392
Short name T531
Test name
Test status
Simulation time 24878838 ps
CPU time 1.31 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 216692 kb
Host smart-dc3b644b-1f50-4abb-8288-f95268b282da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820114392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.820114392
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.803488855
Short name T748
Test name
Test status
Simulation time 43763973 ps
CPU time 0.86 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:03 PM PDT 24
Peak memory 215176 kb
Host smart-663d26af-e384-4b23-be99-c00a97f32d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803488855 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.803488855
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2714129058
Short name T109
Test name
Test status
Simulation time 21720294 ps
CPU time 0.99 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:03 PM PDT 24
Peak memory 206848 kb
Host smart-d2a9d151-4f20-4ba0-9b9c-33b8f7ea8f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714129058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2714129058
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3109484954
Short name T130
Test name
Test status
Simulation time 1164312334 ps
CPU time 7.39 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:09 PM PDT 24
Peak memory 239672 kb
Host smart-34a0451c-fa83-41e0-9c7c-76eadbb0c066
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109484954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3109484954
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.4164766454
Short name T394
Test name
Test status
Simulation time 19739975 ps
CPU time 0.98 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 214996 kb
Host smart-789b6a8f-d370-4f5c-8477-af010ed77f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164766454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.4164766454
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3713906778
Short name T618
Test name
Test status
Simulation time 81650901 ps
CPU time 2.04 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:01 PM PDT 24
Peak memory 216488 kb
Host smart-2eac58d4-1d43-49c2-9415-a4cf6d34be22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713906778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3713906778
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1751667759
Short name T758
Test name
Test status
Simulation time 31184149094 ps
CPU time 811.52 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 03:03:33 PM PDT 24
Peak memory 218552 kb
Host smart-c44004f5-6633-4e36-b9de-d255673e4f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751667759 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1751667759
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3560964761
Short name T152
Test name
Test status
Simulation time 27256627 ps
CPU time 1.33 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 215392 kb
Host smart-2cf08a27-613e-45d6-9b5d-3dfc89d17a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560964761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3560964761
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.859775382
Short name T321
Test name
Test status
Simulation time 18329396 ps
CPU time 0.97 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:27 PM PDT 24
Peak memory 206340 kb
Host smart-29a92ac8-b9b8-4650-8259-16785e893211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859775382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.859775382
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1417283826
Short name T641
Test name
Test status
Simulation time 48598876 ps
CPU time 0.87 seconds
Started May 23 02:51:25 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215280 kb
Host smart-4822e131-92be-4805-8cf6-3d6f8915b1e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417283826 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1417283826
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1596213201
Short name T834
Test name
Test status
Simulation time 122953772 ps
CPU time 1.29 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 216572 kb
Host smart-951edbcb-a90a-47bd-a877-f1d8ea3eae1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596213201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1596213201
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.775976912
Short name T60
Test name
Test status
Simulation time 23231841 ps
CPU time 0.97 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:24 PM PDT 24
Peak memory 218080 kb
Host smart-513847fc-b422-43db-9de1-8f2f77ba6b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775976912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.775976912
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2496301807
Short name T774
Test name
Test status
Simulation time 80496833 ps
CPU time 1.69 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 218216 kb
Host smart-875fb9de-31ec-46e0-91ea-6fceb92d3854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496301807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2496301807
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3270927686
Short name T363
Test name
Test status
Simulation time 21225342 ps
CPU time 1.2 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:24 PM PDT 24
Peak memory 223604 kb
Host smart-10a28bb3-41a6-442e-8f11-78a833b0aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270927686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3270927686
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1401061819
Short name T400
Test name
Test status
Simulation time 49461190 ps
CPU time 0.94 seconds
Started May 23 02:51:25 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215052 kb
Host smart-586752b4-e534-4cd6-b2be-336a792ac738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401061819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1401061819
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3905758367
Short name T456
Test name
Test status
Simulation time 97883292 ps
CPU time 2.38 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 218120 kb
Host smart-6ab6bdb9-e462-4438-9c1c-4811c2de230a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905758367 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3905758367
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.563229459
Short name T358
Test name
Test status
Simulation time 94219974135 ps
CPU time 599.02 seconds
Started May 23 02:51:18 PM PDT 24
Finished May 23 03:01:18 PM PDT 24
Peak memory 218972 kb
Host smart-c9b93054-d0e0-4bd7-a507-7a92a8a8a2d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563229459 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.563229459
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3645602830
Short name T327
Test name
Test status
Simulation time 255541098 ps
CPU time 1.61 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218568 kb
Host smart-873727bc-cc6a-4d64-9be4-be652611bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645602830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3645602830
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3091663615
Short name T677
Test name
Test status
Simulation time 49060887 ps
CPU time 1.87 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 217856 kb
Host smart-228ab546-3156-45cc-9e9f-1c6f024595dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091663615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3091663615
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2263696411
Short name T248
Test name
Test status
Simulation time 87469043 ps
CPU time 1.66 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 218292 kb
Host smart-682a33ff-8a00-49b6-af5a-85e9f8b339ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263696411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2263696411
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4252933448
Short name T723
Test name
Test status
Simulation time 45471670 ps
CPU time 1.17 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:08 PM PDT 24
Peak memory 216620 kb
Host smart-18bb2807-031c-4325-a6c9-061f8d7aa183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252933448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4252933448
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1183070107
Short name T562
Test name
Test status
Simulation time 40554951 ps
CPU time 1.48 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 217912 kb
Host smart-be2cf919-cd24-4fd6-85c6-af2f0a62c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183070107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1183070107
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2130492332
Short name T610
Test name
Test status
Simulation time 64988779 ps
CPU time 1.31 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 218032 kb
Host smart-0e40c5bc-3450-4edf-84b0-62cc02145022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130492332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2130492332
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.16337194
Short name T448
Test name
Test status
Simulation time 126881698 ps
CPU time 1.24 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 216844 kb
Host smart-1491c67b-ca0d-4322-9631-d504ab4fe62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16337194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.16337194
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.291565969
Short name T331
Test name
Test status
Simulation time 63297743 ps
CPU time 1.17 seconds
Started May 23 02:54:06 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 218384 kb
Host smart-d9f82964-0c5f-4708-b3b1-bb5d1738f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291565969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.291565969
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1365217356
Short name T728
Test name
Test status
Simulation time 52299638 ps
CPU time 1.37 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:26 PM PDT 24
Peak memory 215388 kb
Host smart-528ea011-72e6-4216-aee2-ee6a60a315db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365217356 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1365217356
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.4237365440
Short name T206
Test name
Test status
Simulation time 59667674 ps
CPU time 0.99 seconds
Started May 23 02:51:24 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 206276 kb
Host smart-ae979de6-f128-425d-abc2-f10040f136b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237365440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.4237365440
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1839361453
Short name T373
Test name
Test status
Simulation time 10819532 ps
CPU time 0.92 seconds
Started May 23 02:51:26 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 216112 kb
Host smart-864195e4-4466-4e14-abd6-001fd8f27db2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839361453 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1839361453
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2303935455
Short name T51
Test name
Test status
Simulation time 340059078 ps
CPU time 1.09 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:26 PM PDT 24
Peak memory 216492 kb
Host smart-6de69cbb-bdd7-4f66-a32a-8747ad7f637d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303935455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2303935455
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.670090551
Short name T534
Test name
Test status
Simulation time 21066430 ps
CPU time 1.07 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 217976 kb
Host smart-bf7718ac-292e-4c23-8edd-a878780b444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670090551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.670090551
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2845780749
Short name T845
Test name
Test status
Simulation time 49737107 ps
CPU time 1.31 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 218136 kb
Host smart-732e148a-15a2-41fb-b6b7-90d05cdf1210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845780749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2845780749
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2599237734
Short name T445
Test name
Test status
Simulation time 28276471 ps
CPU time 1.07 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:28 PM PDT 24
Peak memory 223628 kb
Host smart-2c772fad-8b00-4a81-9609-61d3d1a4d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599237734 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2599237734
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1435452458
Short name T106
Test name
Test status
Simulation time 16844860 ps
CPU time 0.97 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 215048 kb
Host smart-1fee37f5-d641-41fc-8426-c34ead4fd28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435452458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1435452458
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1085209194
Short name T437
Test name
Test status
Simulation time 154805769 ps
CPU time 2.13 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 216600 kb
Host smart-6891c4d5-6380-4e48-9c38-acace6a378cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085209194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1085209194
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.572040332
Short name T191
Test name
Test status
Simulation time 28429755031 ps
CPU time 654.62 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 03:02:21 PM PDT 24
Peak memory 217296 kb
Host smart-617ae874-3ec2-4fce-bddc-0d9724e893c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572040332 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.572040332
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3054781074
Short name T496
Test name
Test status
Simulation time 49215694 ps
CPU time 1.38 seconds
Started May 23 02:54:00 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218188 kb
Host smart-ddaee91a-9898-41f5-8f06-5af3297eff3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054781074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3054781074
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3440136819
Short name T524
Test name
Test status
Simulation time 54163478 ps
CPU time 1.07 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 216660 kb
Host smart-ebeebd6e-bd4a-4c08-8a6a-52be1cb09e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440136819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3440136819
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.78649837
Short name T401
Test name
Test status
Simulation time 255791863 ps
CPU time 1.18 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:08 PM PDT 24
Peak memory 219624 kb
Host smart-64180657-d293-49a0-a16c-04ba34d8cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78649837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.78649837
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2078240547
Short name T536
Test name
Test status
Simulation time 35514621 ps
CPU time 1.39 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 219356 kb
Host smart-14b6fd80-eb9a-4826-8908-7f75488ad18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078240547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2078240547
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.873331116
Short name T755
Test name
Test status
Simulation time 61540221 ps
CPU time 1.28 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 218000 kb
Host smart-d78bbcdd-a3d3-4881-a39f-1c3c54c3e14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873331116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.873331116
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1383134743
Short name T770
Test name
Test status
Simulation time 80762638 ps
CPU time 1.09 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 219260 kb
Host smart-e2692327-cc90-454e-b3cb-a10268af4535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383134743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1383134743
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3267795665
Short name T148
Test name
Test status
Simulation time 48309470 ps
CPU time 1.68 seconds
Started May 23 02:54:06 PM PDT 24
Finished May 23 02:54:13 PM PDT 24
Peak memory 218048 kb
Host smart-9088f4b2-26fc-41b2-b1b7-fcdba1f758cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267795665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3267795665
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3869338008
Short name T567
Test name
Test status
Simulation time 43192293 ps
CPU time 1.55 seconds
Started May 23 02:54:03 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 217716 kb
Host smart-53ce8748-84a6-4e9f-b462-3f6a00f4d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869338008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3869338008
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1456501154
Short name T578
Test name
Test status
Simulation time 38734457 ps
CPU time 1.44 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218032 kb
Host smart-e282ce8a-67b1-439a-9058-f8cc76584373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456501154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1456501154
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2977919700
Short name T744
Test name
Test status
Simulation time 43792995 ps
CPU time 1.17 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 216752 kb
Host smart-3b5692df-da97-4064-8f5b-b3f374751f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977919700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2977919700
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.40436169
Short name T827
Test name
Test status
Simulation time 29012952 ps
CPU time 1.22 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:27 PM PDT 24
Peak memory 215248 kb
Host smart-d873aa00-5fee-48d5-93b4-b82ef349897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40436169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.40436169
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1742035602
Short name T330
Test name
Test status
Simulation time 31976736 ps
CPU time 0.95 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 206320 kb
Host smart-0c00e0d1-5203-417f-8451-6eaefc39dfe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742035602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1742035602
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3452207506
Short name T164
Test name
Test status
Simulation time 38935242 ps
CPU time 1.3 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 216856 kb
Host smart-2f356f22-9a08-4036-8c95-cf3cf7363f99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452207506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3452207506
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2630214826
Short name T47
Test name
Test status
Simulation time 36092850 ps
CPU time 1.08 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:24 PM PDT 24
Peak memory 217960 kb
Host smart-247f8c39-94bc-4adb-a415-5f99b847c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630214826 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2630214826
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1771052654
Short name T287
Test name
Test status
Simulation time 54224715 ps
CPU time 1.33 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:28 PM PDT 24
Peak memory 217896 kb
Host smart-0be18caf-0da3-4165-8c16-56d0f66616e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771052654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1771052654
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2297357642
Short name T662
Test name
Test status
Simulation time 39745519 ps
CPU time 1.03 seconds
Started May 23 02:51:24 PM PDT 24
Finished May 23 02:51:28 PM PDT 24
Peak memory 223412 kb
Host smart-ee55fa5c-775b-4caa-a26a-4ae3ba6448ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297357642 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2297357642
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2431425367
Short name T608
Test name
Test status
Simulation time 56311862 ps
CPU time 0.85 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 214880 kb
Host smart-04144de8-0af4-40ce-845c-fb754a17ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431425367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2431425367
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1105640783
Short name T324
Test name
Test status
Simulation time 418182003 ps
CPU time 2.68 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 215008 kb
Host smart-21a465ff-2dcd-49cc-ad44-398ceef36024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105640783 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1105640783
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3119144547
Short name T118
Test name
Test status
Simulation time 58517683257 ps
CPU time 659.03 seconds
Started May 23 02:51:23 PM PDT 24
Finished May 23 03:02:26 PM PDT 24
Peak memory 218292 kb
Host smart-fbf5bf2e-55e9-479e-b114-ce7934dec5a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119144547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3119144547
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.686512382
Short name T516
Test name
Test status
Simulation time 34852648 ps
CPU time 1.51 seconds
Started May 23 02:54:00 PM PDT 24
Finished May 23 02:54:04 PM PDT 24
Peak memory 218044 kb
Host smart-57e058c5-accd-43f5-b4a1-839b507eb09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686512382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.686512382
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3405119852
Short name T137
Test name
Test status
Simulation time 39779492 ps
CPU time 1.23 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 216608 kb
Host smart-f5e556ee-3656-4354-adef-50186b7892f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405119852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3405119852
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1932732380
Short name T320
Test name
Test status
Simulation time 52952810 ps
CPU time 1.65 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 218112 kb
Host smart-b8dd5f4a-b354-4369-9d9b-e79e3566b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932732380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1932732380
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3935247430
Short name T586
Test name
Test status
Simulation time 24374164 ps
CPU time 1.2 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:07 PM PDT 24
Peak memory 218876 kb
Host smart-3b3d795e-f98a-4c96-9159-72d3563af7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935247430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3935247430
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.249827131
Short name T671
Test name
Test status
Simulation time 756741404 ps
CPU time 5.79 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 219336 kb
Host smart-e6aa882a-0b91-44f2-9b20-4d4031fe7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249827131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.249827131
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2062013600
Short name T666
Test name
Test status
Simulation time 38663950 ps
CPU time 1.41 seconds
Started May 23 02:54:07 PM PDT 24
Finished May 23 02:54:13 PM PDT 24
Peak memory 218104 kb
Host smart-df568994-3afe-4aa8-8efb-bdc18c4ea8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062013600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2062013600
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.751232891
Short name T491
Test name
Test status
Simulation time 66092741 ps
CPU time 1.28 seconds
Started May 23 02:54:02 PM PDT 24
Finished May 23 02:54:07 PM PDT 24
Peak memory 218888 kb
Host smart-15b60025-db29-48ab-854a-16af2eb0ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751232891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.751232891
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1018711606
Short name T769
Test name
Test status
Simulation time 67380641 ps
CPU time 1.48 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:06 PM PDT 24
Peak memory 217832 kb
Host smart-ee301e71-4b68-4fe3-8a45-acd931ba5b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018711606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1018711606
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1830421941
Short name T293
Test name
Test status
Simulation time 75218390 ps
CPU time 1.31 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 217832 kb
Host smart-fe657502-08fb-4f10-ab40-6699838721b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830421941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1830421941
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1853249057
Short name T576
Test name
Test status
Simulation time 66202513 ps
CPU time 1.83 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 218068 kb
Host smart-d17c449f-99e2-4d70-8887-329ad8df7130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853249057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1853249057
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.130462981
Short name T20
Test name
Test status
Simulation time 330958826 ps
CPU time 1.36 seconds
Started May 23 02:51:19 PM PDT 24
Finished May 23 02:51:23 PM PDT 24
Peak memory 215376 kb
Host smart-190f3255-2261-4136-a1b2-01036ce04e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130462981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.130462981
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.4090621532
Short name T819
Test name
Test status
Simulation time 42376042 ps
CPU time 0.83 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 206184 kb
Host smart-9eba0e66-120f-4a0f-9002-5c24c0155e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090621532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4090621532
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1498898697
Short name T454
Test name
Test status
Simulation time 12397514 ps
CPU time 0.91 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 216368 kb
Host smart-44813f13-07d9-4e59-95fc-726dd4bfbccc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498898697 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1498898697
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.591520641
Short name T25
Test name
Test status
Simulation time 54408570 ps
CPU time 1.16 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:27 PM PDT 24
Peak memory 219108 kb
Host smart-a4645b68-cef2-41bb-a9fe-4d8703094401
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591520641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.591520641
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.183649775
Short name T42
Test name
Test status
Simulation time 26616633 ps
CPU time 1.36 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:28 PM PDT 24
Peak memory 229292 kb
Host smart-7d8393d5-8360-47d5-99bb-bb5578acbe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183649775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.183649775
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3829202244
Short name T292
Test name
Test status
Simulation time 40622837 ps
CPU time 1.4 seconds
Started May 23 02:51:20 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 216860 kb
Host smart-acf87920-492f-4331-ba56-901822e4eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829202244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3829202244
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2619918922
Short name T158
Test name
Test status
Simulation time 41595383 ps
CPU time 0.84 seconds
Started May 23 02:51:22 PM PDT 24
Finished May 23 02:51:27 PM PDT 24
Peak memory 215188 kb
Host smart-22636053-4c6b-4ce4-bef9-0881864e6627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619918922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2619918922
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.905422351
Short name T614
Test name
Test status
Simulation time 24903075 ps
CPU time 1.02 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:26 PM PDT 24
Peak memory 215052 kb
Host smart-69470418-7f30-4498-b0ea-9aa52e1078b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905422351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.905422351
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3446488572
Short name T406
Test name
Test status
Simulation time 81727370 ps
CPU time 1.04 seconds
Started May 23 02:51:25 PM PDT 24
Finished May 23 02:51:29 PM PDT 24
Peak memory 206400 kb
Host smart-7749a8d9-cf59-426c-a38c-62556509fd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446488572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3446488572
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2098074753
Short name T615
Test name
Test status
Simulation time 51598182262 ps
CPU time 1321.22 seconds
Started May 23 02:51:24 PM PDT 24
Finished May 23 03:13:29 PM PDT 24
Peak memory 223524 kb
Host smart-b74c91bb-6005-4c12-8588-b6d743dd558b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098074753 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2098074753
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1241092693
Short name T460
Test name
Test status
Simulation time 84337688 ps
CPU time 1.11 seconds
Started May 23 02:54:01 PM PDT 24
Finished May 23 02:54:05 PM PDT 24
Peak memory 216600 kb
Host smart-c83a442d-9b16-4ad0-9790-0db077564ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241092693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1241092693
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1460902954
Short name T296
Test name
Test status
Simulation time 177546275 ps
CPU time 1.2 seconds
Started May 23 02:54:05 PM PDT 24
Finished May 23 02:54:11 PM PDT 24
Peak memory 219160 kb
Host smart-6903e0dd-dc29-40c7-9320-930cf814ed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460902954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1460902954
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3551590293
Short name T281
Test name
Test status
Simulation time 66405878 ps
CPU time 2.67 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 216896 kb
Host smart-af8c87da-8802-428d-b0b0-a0c7be1f7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551590293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3551590293
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3049141843
Short name T391
Test name
Test status
Simulation time 25983301 ps
CPU time 1.23 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 219000 kb
Host smart-1c28ecfe-f1da-4b92-8f8a-25d864e5d713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049141843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3049141843
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.974961257
Short name T310
Test name
Test status
Simulation time 69071330 ps
CPU time 1.21 seconds
Started May 23 02:54:06 PM PDT 24
Finished May 23 02:54:12 PM PDT 24
Peak memory 218200 kb
Host smart-0c9e3967-1c50-4b72-8ea9-54683fcad6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974961257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.974961257
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1244945516
Short name T19
Test name
Test status
Simulation time 231943493 ps
CPU time 1.25 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:10 PM PDT 24
Peak memory 216908 kb
Host smart-97d6d48e-8cf3-4e1e-bd8e-7a352c8ce407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244945516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1244945516
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4069766605
Short name T436
Test name
Test status
Simulation time 33929206 ps
CPU time 1.32 seconds
Started May 23 02:54:04 PM PDT 24
Finished May 23 02:54:09 PM PDT 24
Peak memory 216824 kb
Host smart-d1ed6a36-8576-4ac4-a40e-20657b3301a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069766605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4069766605
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1333557242
Short name T674
Test name
Test status
Simulation time 157937417 ps
CPU time 2.87 seconds
Started May 23 02:54:15 PM PDT 24
Finished May 23 02:54:21 PM PDT 24
Peak memory 219512 kb
Host smart-675af045-0396-409c-a030-496376485226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333557242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1333557242
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2870149505
Short name T824
Test name
Test status
Simulation time 37114360 ps
CPU time 1.11 seconds
Started May 23 02:54:15 PM PDT 24
Finished May 23 02:54:20 PM PDT 24
Peak memory 216668 kb
Host smart-82ad4575-84ea-4716-855c-0457d1c4a22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870149505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2870149505
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.1921403981
Short name T486
Test name
Test status
Simulation time 119158447 ps
CPU time 1 seconds
Started May 23 02:51:32 PM PDT 24
Finished May 23 02:51:34 PM PDT 24
Peak memory 206364 kb
Host smart-9654a609-dbad-4261-a795-ff4aaea92dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921403981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1921403981
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3021798108
Short name T753
Test name
Test status
Simulation time 103873115 ps
CPU time 1.03 seconds
Started May 23 02:51:33 PM PDT 24
Finished May 23 02:51:35 PM PDT 24
Peak memory 216556 kb
Host smart-21fd4c72-30fe-4dfb-80fd-2bc46fe23d04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021798108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3021798108
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2619121091
Short name T104
Test name
Test status
Simulation time 20587356 ps
CPU time 1.07 seconds
Started May 23 02:51:32 PM PDT 24
Finished May 23 02:51:34 PM PDT 24
Peak memory 219168 kb
Host smart-ba63dbfd-b36b-48b4-ab5a-152aaad03d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619121091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2619121091
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2249367869
Short name T277
Test name
Test status
Simulation time 83716491 ps
CPU time 2.21 seconds
Started May 23 02:51:32 PM PDT 24
Finished May 23 02:51:35 PM PDT 24
Peak memory 219744 kb
Host smart-1b633340-07f1-43ca-8d20-9b53557baf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249367869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2249367869
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.1520565758
Short name T143
Test name
Test status
Simulation time 30062980 ps
CPU time 0.93 seconds
Started May 23 02:51:34 PM PDT 24
Finished May 23 02:51:36 PM PDT 24
Peak memory 215440 kb
Host smart-e2845fcc-30f3-4eee-8ca6-71f31236cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520565758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1520565758
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4178929599
Short name T635
Test name
Test status
Simulation time 35710507 ps
CPU time 0.94 seconds
Started May 23 02:51:21 PM PDT 24
Finished May 23 02:51:25 PM PDT 24
Peak memory 214992 kb
Host smart-22e6b6a8-e781-4729-ae85-b4103175e2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178929599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4178929599
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1603356375
Short name T434
Test name
Test status
Simulation time 291304475 ps
CPU time 3.56 seconds
Started May 23 02:51:33 PM PDT 24
Finished May 23 02:51:38 PM PDT 24
Peak memory 215020 kb
Host smart-53195a50-3874-4a01-a9b7-e72b528b448e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603356375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1603356375
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2058849410
Short name T190
Test name
Test status
Simulation time 102016052948 ps
CPU time 2316.43 seconds
Started May 23 02:51:35 PM PDT 24
Finished May 23 03:30:13 PM PDT 24
Peak memory 227064 kb
Host smart-d9a9dc2b-b90d-4e8c-813c-32a0f351120d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058849410 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2058849410
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3878927913
Short name T387
Test name
Test status
Simulation time 47810475 ps
CPU time 1.26 seconds
Started May 23 02:54:12 PM PDT 24
Finished May 23 02:54:17 PM PDT 24
Peak memory 219160 kb
Host smart-a5488ba5-ca7a-4fc8-b37e-8c9b3d46b265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878927913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3878927913
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2213145647
Short name T375
Test name
Test status
Simulation time 61256096 ps
CPU time 1.62 seconds
Started May 23 02:54:13 PM PDT 24
Finished May 23 02:54:18 PM PDT 24
Peak memory 218060 kb
Host smart-6491a377-ce83-42e3-8aa1-84c163fa852c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213145647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2213145647
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2151524674
Short name T711
Test name
Test status
Simulation time 155419398 ps
CPU time 3.38 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:21 PM PDT 24
Peak memory 217856 kb
Host smart-f8f2f77f-bc0c-4cca-b3e6-136b33dc0164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151524674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2151524674
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2415226353
Short name T284
Test name
Test status
Simulation time 78147963 ps
CPU time 2.97 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 219572 kb
Host smart-49f0c14a-7d4c-4b17-b284-cddce0602bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415226353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2415226353
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3738827889
Short name T462
Test name
Test status
Simulation time 92212624 ps
CPU time 1.47 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 216604 kb
Host smart-7823fd01-bef3-487e-846f-fa722ef4e041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738827889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3738827889
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3948504793
Short name T371
Test name
Test status
Simulation time 74661897 ps
CPU time 1.07 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:25 PM PDT 24
Peak memory 216808 kb
Host smart-8b3b82d6-a516-4981-9d47-33c444e1fd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948504793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3948504793
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1757223047
Short name T132
Test name
Test status
Simulation time 41471236 ps
CPU time 1.52 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 217924 kb
Host smart-d225a6ad-c67e-4920-8f81-cc87f53e5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757223047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1757223047
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.821249277
Short name T609
Test name
Test status
Simulation time 320633914 ps
CPU time 1.2 seconds
Started May 23 02:54:17 PM PDT 24
Finished May 23 02:54:22 PM PDT 24
Peak memory 216728 kb
Host smart-a5186fe6-2cc4-4d4e-a863-e6420b8ca33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821249277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.821249277
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2740131431
Short name T340
Test name
Test status
Simulation time 76238669 ps
CPU time 1.63 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 217940 kb
Host smart-8a0abc5e-4c08-4051-b60b-08d8c2904dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740131431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2740131431
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1017328962
Short name T725
Test name
Test status
Simulation time 249294386 ps
CPU time 2.51 seconds
Started May 23 02:54:17 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 218940 kb
Host smart-07b3d46d-464b-46f7-bb81-17e906744f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017328962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1017328962
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1123558861
Short name T838
Test name
Test status
Simulation time 97911671 ps
CPU time 1.35 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 215404 kb
Host smart-a487b9a0-fb4c-4a47-87c5-98d2d14d05eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123558861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1123558861
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2794061455
Short name T155
Test name
Test status
Simulation time 40340028 ps
CPU time 0.85 seconds
Started May 23 02:51:46 PM PDT 24
Finished May 23 02:51:48 PM PDT 24
Peak memory 206612 kb
Host smart-a8ee2031-0700-4aba-b2f0-50a64b9490a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794061455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2794061455
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2578967724
Short name T525
Test name
Test status
Simulation time 22810014 ps
CPU time 0.85 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 215244 kb
Host smart-4a7deef1-6f9e-450f-8883-0f26014723f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578967724 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2578967724
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3448491037
Short name T517
Test name
Test status
Simulation time 139565741 ps
CPU time 1.38 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 216676 kb
Host smart-47bfa751-7007-4219-9762-543deaf3c167
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448491037 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3448491037
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3804493801
Short name T96
Test name
Test status
Simulation time 20104733 ps
CPU time 1.15 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:51 PM PDT 24
Peak memory 217988 kb
Host smart-05c44e95-d23d-49f4-bf3b-0aa9e2c638c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804493801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3804493801
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2444251814
Short name T362
Test name
Test status
Simulation time 89741711 ps
CPU time 1.23 seconds
Started May 23 02:51:33 PM PDT 24
Finished May 23 02:51:35 PM PDT 24
Peak memory 217816 kb
Host smart-1a485307-8f4d-4224-8d3c-d19e32a81e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444251814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2444251814
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1035615859
Short name T115
Test name
Test status
Simulation time 32685230 ps
CPU time 0.92 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:52 PM PDT 24
Peak memory 215340 kb
Host smart-76ea196d-f9e8-4e5e-a977-dde41065983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035615859 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1035615859
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3481709883
Short name T355
Test name
Test status
Simulation time 19789519 ps
CPU time 1.02 seconds
Started May 23 02:51:33 PM PDT 24
Finished May 23 02:51:36 PM PDT 24
Peak memory 215032 kb
Host smart-58b40ac1-0bed-434b-bb7e-a503045e310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481709883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3481709883
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2609815689
Short name T772
Test name
Test status
Simulation time 130471051 ps
CPU time 2.99 seconds
Started May 23 02:51:34 PM PDT 24
Finished May 23 02:51:38 PM PDT 24
Peak memory 215024 kb
Host smart-8ae7e492-ba8e-4d29-8945-1692d8216d40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609815689 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2609815689
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.62756525
Short name T189
Test name
Test status
Simulation time 227675321685 ps
CPU time 1390.43 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 03:15:04 PM PDT 24
Peak memory 222936 kb
Host smart-e516ee0d-2930-4f03-aa1d-b031dd1404b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62756525 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.62756525
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3748106753
Short name T412
Test name
Test status
Simulation time 68591495 ps
CPU time 1.61 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 219184 kb
Host smart-beed527c-233a-41ad-a374-e673ef9e842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748106753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3748106753
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2095299182
Short name T360
Test name
Test status
Simulation time 31961860 ps
CPU time 1.33 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 217844 kb
Host smart-63940bac-a908-42b8-a181-acfae0860f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095299182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2095299182
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2890260785
Short name T201
Test name
Test status
Simulation time 67730104 ps
CPU time 1.08 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 216852 kb
Host smart-c4cc9538-dc9d-4251-801f-6766eab35846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890260785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2890260785
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1779869210
Short name T545
Test name
Test status
Simulation time 36715594 ps
CPU time 1.42 seconds
Started May 23 02:54:11 PM PDT 24
Finished May 23 02:54:16 PM PDT 24
Peak memory 216808 kb
Host smart-fa72469d-b04a-4685-b708-58c6826688b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779869210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1779869210
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.411580198
Short name T289
Test name
Test status
Simulation time 28818279 ps
CPU time 1.49 seconds
Started May 23 02:54:23 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 217940 kb
Host smart-925cc194-de7a-4990-bae3-ec69f38c371b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411580198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.411580198
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1981688606
Short name T475
Test name
Test status
Simulation time 41584817 ps
CPU time 1.19 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:18 PM PDT 24
Peak memory 216704 kb
Host smart-291505a5-c344-48a4-9f8c-575098893378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981688606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1981688606
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3802536599
Short name T367
Test name
Test status
Simulation time 74931169 ps
CPU time 1.32 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 218108 kb
Host smart-e3af2827-51bd-4699-8f25-cfa9955b9c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802536599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3802536599
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3575542438
Short name T443
Test name
Test status
Simulation time 55895637 ps
CPU time 1.38 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 219344 kb
Host smart-63df33ff-bf9c-4478-a644-2a7a3ca5a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575542438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3575542438
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1852246082
Short name T716
Test name
Test status
Simulation time 74909993 ps
CPU time 1.09 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:26 PM PDT 24
Peak memory 216612 kb
Host smart-9f498ca7-5cc6-48fb-b6ea-9183c6b7f942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852246082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1852246082
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2217939753
Short name T120
Test name
Test status
Simulation time 48264408 ps
CPU time 1.66 seconds
Started May 23 02:54:16 PM PDT 24
Finished May 23 02:54:22 PM PDT 24
Peak memory 216616 kb
Host smart-8fc84ca2-21ba-43e3-b62f-bbbb59501311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217939753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2217939753
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.904239738
Short name T715
Test name
Test status
Simulation time 101375462 ps
CPU time 1.34 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:58 PM PDT 24
Peak memory 215396 kb
Host smart-1576c931-7f43-4ae1-8cfe-a326ba07ae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904239738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.904239738
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1926155383
Short name T597
Test name
Test status
Simulation time 14908540 ps
CPU time 0.96 seconds
Started May 23 02:51:46 PM PDT 24
Finished May 23 02:51:48 PM PDT 24
Peak memory 214548 kb
Host smart-5059be80-128f-4aa4-869d-d0f1d8bc825d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926155383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1926155383
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1163764501
Short name T168
Test name
Test status
Simulation time 39501010 ps
CPU time 0.85 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 216096 kb
Host smart-ac29191a-a290-4080-a3fd-9c974d129662
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163764501 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1163764501
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.458660548
Short name T613
Test name
Test status
Simulation time 65898285 ps
CPU time 0.95 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 217836 kb
Host smart-f5ab66d2-8382-4a82-be3f-68b85ca1d023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458660548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.458660548
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3629054172
Short name T93
Test name
Test status
Simulation time 27964758 ps
CPU time 0.89 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 217688 kb
Host smart-7acfe365-82a2-459a-a175-f2d948911e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629054172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3629054172
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1682699015
Short name T347
Test name
Test status
Simulation time 178585123 ps
CPU time 1.14 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:50 PM PDT 24
Peak memory 218560 kb
Host smart-c84f5d08-280a-4112-9cc7-e18202b0d0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682699015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1682699015
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2707922717
Short name T114
Test name
Test status
Simulation time 20871897 ps
CPU time 1.06 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 215428 kb
Host smart-258798d6-fb8d-4852-866b-e95423bf9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707922717 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2707922717
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.72093296
Short name T368
Test name
Test status
Simulation time 39012628 ps
CPU time 0.93 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:53 PM PDT 24
Peak memory 215048 kb
Host smart-7841ae48-e11b-459a-b116-c90e0d170080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72093296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.72093296
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4039945214
Short name T823
Test name
Test status
Simulation time 329101447 ps
CPU time 4.09 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 216768 kb
Host smart-8411d629-d704-4328-847d-5a1ce8c15e05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039945214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4039945214
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1943109398
Short name T150
Test name
Test status
Simulation time 59062822341 ps
CPU time 1414.11 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 03:15:30 PM PDT 24
Peak memory 221992 kb
Host smart-6ee5c44b-0403-456c-9b6a-8a28216dfcb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943109398 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1943109398
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4054340087
Short name T507
Test name
Test status
Simulation time 284966256 ps
CPU time 1.29 seconds
Started May 23 02:54:21 PM PDT 24
Finished May 23 02:54:25 PM PDT 24
Peak memory 216816 kb
Host smart-7324e1ac-3a08-406c-91b9-366100922bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054340087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4054340087
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3288001970
Short name T555
Test name
Test status
Simulation time 59946371 ps
CPU time 1.39 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 217852 kb
Host smart-db3fbe88-abcd-4388-aa16-6e2ce27db0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288001970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3288001970
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3181543515
Short name T595
Test name
Test status
Simulation time 40807372 ps
CPU time 1.43 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 217936 kb
Host smart-1952f886-7c99-47b3-a2e8-54eec03a5668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181543515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3181543515
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3258026421
Short name T829
Test name
Test status
Simulation time 69442679 ps
CPU time 1.48 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 216872 kb
Host smart-1031453a-3606-405d-8d8c-af12d130295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258026421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3258026421
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3641115448
Short name T518
Test name
Test status
Simulation time 151654145 ps
CPU time 3.21 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 218088 kb
Host smart-c9019f5f-22dd-4af9-9074-09925bff0861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641115448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3641115448
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2882563754
Short name T749
Test name
Test status
Simulation time 63535508 ps
CPU time 1.34 seconds
Started May 23 02:54:17 PM PDT 24
Finished May 23 02:54:21 PM PDT 24
Peak memory 219168 kb
Host smart-9ab01e11-6340-4e3e-93d7-a8444f6ca82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882563754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2882563754
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3868747393
Short name T696
Test name
Test status
Simulation time 39794612 ps
CPU time 1.37 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 218148 kb
Host smart-9738aa3c-b7f8-45b8-9f54-e2c429d4a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868747393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3868747393
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.989010026
Short name T423
Test name
Test status
Simulation time 35921019 ps
CPU time 1.44 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:22 PM PDT 24
Peak memory 218020 kb
Host smart-aed23909-3730-45e2-9eb4-39dc4caa70a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989010026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.989010026
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2364687873
Short name T278
Test name
Test status
Simulation time 118091805 ps
CPU time 1.91 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 219096 kb
Host smart-f0b2440a-48b4-435a-b1a9-e12e81e36c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364687873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2364687873
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2420282507
Short name T288
Test name
Test status
Simulation time 41813402 ps
CPU time 1.77 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 217992 kb
Host smart-47887738-089a-407e-adc6-f5047181bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420282507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2420282507
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.1976064881
Short name T333
Test name
Test status
Simulation time 20977362 ps
CPU time 0.83 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 206296 kb
Host smart-0ac81b42-e70b-4f5f-8580-92f278c82715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976064881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1976064881
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3733397251
Short name T61
Test name
Test status
Simulation time 32999969 ps
CPU time 0.86 seconds
Started May 23 02:51:51 PM PDT 24
Finished May 23 02:51:58 PM PDT 24
Peak memory 215252 kb
Host smart-303e1a61-6fda-4a78-84bc-3d55a542d32b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733397251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3733397251
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3056047137
Short name T343
Test name
Test status
Simulation time 29116147 ps
CPU time 0.99 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:51 PM PDT 24
Peak memory 217724 kb
Host smart-865343e2-b209-4cfd-a7e6-ae8158b1171a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056047137 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3056047137
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2968285996
Short name T169
Test name
Test status
Simulation time 33725806 ps
CPU time 0.93 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 218844 kb
Host smart-aaa4ca3c-6420-482f-8323-4e15b90059d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968285996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2968285996
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1156446466
Short name T459
Test name
Test status
Simulation time 70498009 ps
CPU time 1.54 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 218408 kb
Host smart-ee0c60c9-8092-401f-afe1-49de4df36748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156446466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1156446466
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.706093583
Short name T703
Test name
Test status
Simulation time 20958230 ps
CPU time 1.07 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:55 PM PDT 24
Peak memory 215320 kb
Host smart-18656485-05fc-4952-936c-62e16560e290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706093583 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.706093583
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3833665661
Short name T539
Test name
Test status
Simulation time 17973861 ps
CPU time 1.03 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:52 PM PDT 24
Peak memory 215052 kb
Host smart-f2d4494f-d856-43ff-bad0-79bc437c7ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833665661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3833665661
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2710427834
Short name T499
Test name
Test status
Simulation time 166752031 ps
CPU time 2.36 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 216600 kb
Host smart-8fcd429e-d8db-4b95-8f2d-323e3cba5d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710427834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2710427834
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3612866921
Short name T800
Test name
Test status
Simulation time 368324876728 ps
CPU time 2058.88 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 03:26:09 PM PDT 24
Peak memory 225976 kb
Host smart-f78b032a-59cd-476b-9bbf-a64710df0c2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612866921 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3612866921
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4283673920
Short name T648
Test name
Test status
Simulation time 218471117 ps
CPU time 1.34 seconds
Started May 23 02:54:15 PM PDT 24
Finished May 23 02:54:20 PM PDT 24
Peak memory 218292 kb
Host smart-a6d31e32-13a6-42c0-8689-1f921bc701a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283673920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4283673920
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2671902974
Short name T773
Test name
Test status
Simulation time 160458374 ps
CPU time 1.08 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 216896 kb
Host smart-473c17d8-21c8-4a4d-ba55-e6393fc496ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671902974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2671902974
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.153769483
Short name T549
Test name
Test status
Simulation time 60953460 ps
CPU time 1.28 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 216696 kb
Host smart-9ba5b710-bdaf-45bf-98ff-5fc5f6f7bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153769483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.153769483
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1325296921
Short name T345
Test name
Test status
Simulation time 138526854 ps
CPU time 1.35 seconds
Started May 23 02:54:13 PM PDT 24
Finished May 23 02:54:18 PM PDT 24
Peak memory 216844 kb
Host smart-0b49a8b0-60bf-4aa3-98f1-b0ebdf223074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325296921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1325296921
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2369340131
Short name T667
Test name
Test status
Simulation time 26244787 ps
CPU time 1.19 seconds
Started May 23 02:54:13 PM PDT 24
Finished May 23 02:54:17 PM PDT 24
Peak memory 216796 kb
Host smart-2ab16f15-abd6-4a63-af2c-b205aca19156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369340131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2369340131
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2750902826
Short name T832
Test name
Test status
Simulation time 84302403 ps
CPU time 1.24 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 219228 kb
Host smart-d22300c6-7964-4c96-9616-705dd8dc5df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750902826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2750902826
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2719413033
Short name T352
Test name
Test status
Simulation time 51375041 ps
CPU time 1.89 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 217892 kb
Host smart-b54f1690-84d6-4a5e-a3c5-ecf4f80deb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719413033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2719413033
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2900553659
Short name T279
Test name
Test status
Simulation time 59648405 ps
CPU time 2.05 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:25 PM PDT 24
Peak memory 217836 kb
Host smart-fed5ec8a-c075-47bb-a584-881e15a25ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900553659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2900553659
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1935599256
Short name T598
Test name
Test status
Simulation time 51631044 ps
CPU time 1.41 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:25 PM PDT 24
Peak memory 217876 kb
Host smart-521e3962-5496-4eeb-9322-5dac385c599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935599256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1935599256
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2792416890
Short name T564
Test name
Test status
Simulation time 66705357 ps
CPU time 1.38 seconds
Started May 23 02:54:21 PM PDT 24
Finished May 23 02:54:26 PM PDT 24
Peak memory 218276 kb
Host smart-4351dbd9-0c2f-4df3-8699-7a26d889c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792416890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2792416890
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1911799962
Short name T776
Test name
Test status
Simulation time 25228993 ps
CPU time 1.32 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 215424 kb
Host smart-47437518-fbc7-49a4-8e65-7db8b951e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911799962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1911799962
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4185827841
Short name T521
Test name
Test status
Simulation time 73510308 ps
CPU time 1.77 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 206748 kb
Host smart-7ab8ccdd-247f-42e0-8820-448b074a53cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185827841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4185827841
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1394071484
Short name T582
Test name
Test status
Simulation time 42542112 ps
CPU time 0.89 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:55 PM PDT 24
Peak memory 216092 kb
Host smart-fe24a1e7-e24e-40c3-bc76-4f7609f2d620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394071484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1394071484
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3625961516
Short name T36
Test name
Test status
Simulation time 129965936 ps
CPU time 1.26 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 216696 kb
Host smart-0ea51d80-a3b3-4f7b-a84e-70d0a600c73f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625961516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3625961516
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2661640863
Short name T520
Test name
Test status
Simulation time 29077533 ps
CPU time 0.9 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:55 PM PDT 24
Peak memory 217828 kb
Host smart-789a7f68-e0b7-400a-bcf1-8dede8ba40d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661640863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2661640863
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3138914847
Short name T551
Test name
Test status
Simulation time 37760156 ps
CPU time 1.29 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:55 PM PDT 24
Peak memory 216976 kb
Host smart-44c0d781-cfa3-41e6-9086-6f5ee061e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138914847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3138914847
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.385897606
Short name T298
Test name
Test status
Simulation time 24165229 ps
CPU time 0.99 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 215364 kb
Host smart-9b3097a6-3ad0-485a-b7b0-70acb14ffd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385897606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.385897606
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.994608609
Short name T593
Test name
Test status
Simulation time 25401721 ps
CPU time 0.96 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:55 PM PDT 24
Peak memory 215024 kb
Host smart-31d87274-bfd0-440f-a2a9-3d5e2c944182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994608609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.994608609
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.410845694
Short name T788
Test name
Test status
Simulation time 1944535655 ps
CPU time 4.67 seconds
Started May 23 02:51:46 PM PDT 24
Finished May 23 02:51:52 PM PDT 24
Peak memory 216844 kb
Host smart-31806553-af0b-4d24-b9ec-42373b935c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410845694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.410845694
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2875802092
Short name T405
Test name
Test status
Simulation time 111947555300 ps
CPU time 1126.83 seconds
Started May 23 02:51:45 PM PDT 24
Finished May 23 03:10:33 PM PDT 24
Peak memory 221764 kb
Host smart-be4215d7-e348-42b1-92af-70efac316cd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875802092 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2875802092
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1375744524
Short name T125
Test name
Test status
Simulation time 125785933 ps
CPU time 1.61 seconds
Started May 23 02:54:14 PM PDT 24
Finished May 23 02:54:19 PM PDT 24
Peak memory 218300 kb
Host smart-f955aa36-985a-4d7b-bb30-cb9e74f0b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375744524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1375744524
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1501502030
Short name T449
Test name
Test status
Simulation time 140991473 ps
CPU time 1.07 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 216664 kb
Host smart-c4a6734a-0eca-4ed6-a65f-05198de40e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501502030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1501502030
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.540859469
Short name T538
Test name
Test status
Simulation time 39596807 ps
CPU time 1.33 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 218064 kb
Host smart-c2c54227-dcf8-4d7d-9d0b-5562bc9e291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540859469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.540859469
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4208662760
Short name T429
Test name
Test status
Simulation time 126147454 ps
CPU time 1.27 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:22 PM PDT 24
Peak memory 218436 kb
Host smart-78cc9124-72d0-4530-95ac-4bec4d4b2c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208662760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4208662760
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2440270329
Short name T200
Test name
Test status
Simulation time 92828103 ps
CPU time 2.11 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 219492 kb
Host smart-df521eb3-d7ca-4e13-ab19-e00f8d5bc7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440270329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2440270329
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3332292039
Short name T407
Test name
Test status
Simulation time 36407630 ps
CPU time 1.43 seconds
Started May 23 02:54:19 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 217932 kb
Host smart-41b47084-e793-4e58-bbe6-64d9ce303971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332292039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3332292039
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.459299537
Short name T338
Test name
Test status
Simulation time 99215150 ps
CPU time 2.6 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 219624 kb
Host smart-097ed62b-5a37-4be1-9c79-cd9fee75df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459299537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.459299537
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.953931471
Short name T417
Test name
Test status
Simulation time 111702069 ps
CPU time 1.69 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:23 PM PDT 24
Peak memory 218252 kb
Host smart-21a7e930-3248-4f97-8940-501a2e452fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953931471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.953931471
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3768987618
Short name T733
Test name
Test status
Simulation time 54825176 ps
CPU time 1.43 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 216704 kb
Host smart-4d524374-0e03-449e-8685-ae4531e1ffa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768987618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3768987618
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.427332310
Short name T346
Test name
Test status
Simulation time 37421476 ps
CPU time 1.44 seconds
Started May 23 02:54:18 PM PDT 24
Finished May 23 02:54:22 PM PDT 24
Peak memory 216732 kb
Host smart-8c533490-84f3-4516-bc50-f6291187e8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427332310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.427332310
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1231524025
Short name T620
Test name
Test status
Simulation time 68750473 ps
CPU time 1.06 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 215384 kb
Host smart-381b3fc1-7339-4998-b195-34663f5d0dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231524025 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1231524025
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4274902985
Short name T398
Test name
Test status
Simulation time 32940897 ps
CPU time 0.83 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 205352 kb
Host smart-42d55b34-ed89-4bd8-9f18-59b1412a28e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274902985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4274902985
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3270737972
Short name T231
Test name
Test status
Simulation time 55677143 ps
CPU time 1.25 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 216608 kb
Host smart-5a5b3384-cc4a-4365-a225-285a8cf91810
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270737972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3270737972
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3917156991
Short name T90
Test name
Test status
Simulation time 19088867 ps
CPU time 1.2 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 223504 kb
Host smart-5e728746-c748-45e3-8636-b6e3c01b6890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917156991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3917156991
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2958178410
Short name T738
Test name
Test status
Simulation time 32967652 ps
CPU time 1.63 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:50 PM PDT 24
Peak memory 216740 kb
Host smart-9ed023c9-b05f-48e2-9c2c-4eec7e659454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958178410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2958178410
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2422743779
Short name T381
Test name
Test status
Simulation time 34086315 ps
CPU time 0.91 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 214904 kb
Host smart-a11f7234-c287-496b-ba42-a9f3934cee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422743779 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2422743779
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1232044538
Short name T379
Test name
Test status
Simulation time 18166435 ps
CPU time 1.08 seconds
Started May 23 02:51:48 PM PDT 24
Finished May 23 02:51:52 PM PDT 24
Peak memory 215032 kb
Host smart-fdfe4b43-5c33-47f9-9d68-93071acc132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232044538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1232044538
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3281013302
Short name T466
Test name
Test status
Simulation time 201854150 ps
CPU time 4.24 seconds
Started May 23 02:51:47 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 217796 kb
Host smart-4630a3c2-22bb-428b-afb0-7d2022999cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281013302 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3281013302
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4216608319
Short name T207
Test name
Test status
Simulation time 30520867840 ps
CPU time 809.39 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 03:05:22 PM PDT 24
Peak memory 218332 kb
Host smart-6095305c-7f0a-4bbf-828f-8244cd79bf20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216608319 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.4216608319
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2875935697
Short name T624
Test name
Test status
Simulation time 99600301 ps
CPU time 1.24 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:26 PM PDT 24
Peak memory 217920 kb
Host smart-c6bfe1ea-c8d7-4290-b68b-bbd354e8151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875935697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2875935697
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3239583620
Short name T383
Test name
Test status
Simulation time 126245358 ps
CPU time 0.98 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:26 PM PDT 24
Peak memory 216828 kb
Host smart-d455e1b0-47df-4fc3-89df-a15fdf4656a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239583620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3239583620
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4012036351
Short name T442
Test name
Test status
Simulation time 79382169 ps
CPU time 1.08 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:25 PM PDT 24
Peak memory 216708 kb
Host smart-9ef772b0-082c-42a9-8842-6abe896b4949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012036351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4012036351
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1422104346
Short name T767
Test name
Test status
Simulation time 88819452 ps
CPU time 1.21 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 216692 kb
Host smart-24ee6ff5-5da8-4e10-b93b-2e703965cb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422104346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1422104346
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3326471396
Short name T843
Test name
Test status
Simulation time 168552701 ps
CPU time 1.04 seconds
Started May 23 02:54:21 PM PDT 24
Finished May 23 02:54:26 PM PDT 24
Peak memory 217008 kb
Host smart-179cadfb-14f0-4c15-9fcf-7c130df6fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326471396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3326471396
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3893850295
Short name T283
Test name
Test status
Simulation time 52373144 ps
CPU time 1.43 seconds
Started May 23 02:54:20 PM PDT 24
Finished May 23 02:54:24 PM PDT 24
Peak memory 219092 kb
Host smart-e45fb604-99d2-42e4-bd36-b5af8f396a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893850295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3893850295
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2529481322
Short name T607
Test name
Test status
Simulation time 45988000 ps
CPU time 1.45 seconds
Started May 23 02:54:22 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 217840 kb
Host smart-1565483d-0844-498a-bcc5-d3eba7fe15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529481322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2529481322
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3448783146
Short name T732
Test name
Test status
Simulation time 107156507 ps
CPU time 1.47 seconds
Started May 23 02:54:23 PM PDT 24
Finished May 23 02:54:27 PM PDT 24
Peak memory 218460 kb
Host smart-a6c92c6d-18c3-4397-83fa-446f8597834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448783146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3448783146
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1589164553
Short name T771
Test name
Test status
Simulation time 51153170 ps
CPU time 1.33 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:03 PM PDT 24
Peak memory 215432 kb
Host smart-de2b9654-372c-4943-92c3-be376487dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589164553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1589164553
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2630868397
Short name T506
Test name
Test status
Simulation time 25574206 ps
CPU time 0.9 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 206332 kb
Host smart-04e604b7-f4ee-4caa-9b4d-d3f4b9af8992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630868397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2630868397
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.885184431
Short name T167
Test name
Test status
Simulation time 37840673 ps
CPU time 0.88 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 216068 kb
Host smart-fe8e6299-a6dc-4ee7-bbb8-4e3376aea843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885184431 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.885184431
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2918419669
Short name T384
Test name
Test status
Simulation time 84093820 ps
CPU time 1.29 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 219216 kb
Host smart-a24d3528-5d23-4711-be25-2b9b7536f874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918419669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2918419669
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2215860853
Short name T97
Test name
Test status
Simulation time 21118504 ps
CPU time 1.11 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 218072 kb
Host smart-36558571-1306-4861-9289-e71161675f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215860853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2215860853
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2176496481
Short name T820
Test name
Test status
Simulation time 91738420 ps
CPU time 1.2 seconds
Started May 23 02:49:56 PM PDT 24
Finished May 23 02:49:59 PM PDT 24
Peak memory 218236 kb
Host smart-c72696ac-9eb5-4362-af34-4604b870cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176496481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2176496481
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1681191433
Short name T727
Test name
Test status
Simulation time 24786332 ps
CPU time 0.9 seconds
Started May 23 02:49:56 PM PDT 24
Finished May 23 02:49:58 PM PDT 24
Peak memory 215380 kb
Host smart-37110cce-918c-429d-af23-d68acf7f95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681191433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1681191433
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3974635610
Short name T15
Test name
Test status
Simulation time 874473438 ps
CPU time 4.46 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 238588 kb
Host smart-8b07a686-daf7-4b14-a48a-d1e9c2000fe6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974635610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3974635610
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3090192969
Short name T672
Test name
Test status
Simulation time 14635889 ps
CPU time 0.97 seconds
Started May 23 02:49:57 PM PDT 24
Finished May 23 02:50:00 PM PDT 24
Peak memory 214988 kb
Host smart-8e8613b8-2c4e-4686-881e-9caa9f8d7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090192969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3090192969
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.4021164305
Short name T404
Test name
Test status
Simulation time 1238546791 ps
CPU time 5.07 seconds
Started May 23 02:49:59 PM PDT 24
Finished May 23 02:50:07 PM PDT 24
Peak memory 216676 kb
Host smart-17a9ab1b-26d7-4c5d-b4d7-73501a177e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021164305 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.4021164305
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.943954257
Short name T411
Test name
Test status
Simulation time 63351917727 ps
CPU time 772.56 seconds
Started May 23 02:49:58 PM PDT 24
Finished May 23 03:02:54 PM PDT 24
Peak memory 223500 kb
Host smart-8f390312-5df3-41b6-8d38-1dfed87cdf9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943954257 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.943954257
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.25780680
Short name T261
Test name
Test status
Simulation time 45588693 ps
CPU time 1.24 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 215404 kb
Host smart-7cc30f7c-142a-4496-be04-e1a21c946a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25780680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.25780680
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1019870725
Short name T319
Test name
Test status
Simulation time 59589999 ps
CPU time 0.99 seconds
Started May 23 02:51:51 PM PDT 24
Finished May 23 02:51:58 PM PDT 24
Peak memory 206232 kb
Host smart-c19f15eb-f53b-4316-b64c-c31c35281c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019870725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1019870725
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1120594502
Short name T402
Test name
Test status
Simulation time 13061809 ps
CPU time 0.89 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 216228 kb
Host smart-4c6d2a65-bdc4-4e6e-90da-8700811a93f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120594502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1120594502
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3802710315
Short name T43
Test name
Test status
Simulation time 29055319 ps
CPU time 1.06 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 216548 kb
Host smart-a95f2704-bcab-4ff8-933c-454174cc1138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802710315 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3802710315
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.2192418656
Short name T688
Test name
Test status
Simulation time 23574233 ps
CPU time 1.06 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:56 PM PDT 24
Peak memory 223340 kb
Host smart-59b49373-ab5b-4b48-9101-ec605534e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192418656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2192418656
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1817356928
Short name T709
Test name
Test status
Simulation time 42544385 ps
CPU time 1.45 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:51:57 PM PDT 24
Peak memory 216748 kb
Host smart-464de7f2-8a09-4429-9b47-dfb1d9a0b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817356928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1817356928
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2670458615
Short name T349
Test name
Test status
Simulation time 68471667 ps
CPU time 0.87 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 215172 kb
Host smart-56301820-c145-4012-870a-3340cceab997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670458615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2670458615
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.866224428
Short name T301
Test name
Test status
Simulation time 107276660 ps
CPU time 0.9 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 214900 kb
Host smart-58e9bbf8-c53c-4309-b306-a1b55ba88129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866224428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.866224428
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1949996698
Short name T825
Test name
Test status
Simulation time 115535479 ps
CPU time 1.78 seconds
Started May 23 02:51:51 PM PDT 24
Finished May 23 02:51:59 PM PDT 24
Peak memory 219276 kb
Host smart-f2fd6cef-f03a-4bf3-9cd6-8cd6b4abca50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949996698 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1949996698
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2640359028
Short name T840
Test name
Test status
Simulation time 105386842548 ps
CPU time 625.16 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 03:02:18 PM PDT 24
Peak memory 220368 kb
Host smart-291e82d5-1df4-444b-9b92-e3823f5c96c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640359028 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2640359028
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2928484123
Short name T70
Test name
Test status
Simulation time 44250246 ps
CPU time 1.18 seconds
Started May 23 02:52:02 PM PDT 24
Finished May 23 02:52:12 PM PDT 24
Peak memory 215408 kb
Host smart-79e8cd61-e080-4801-b54d-81d536fa0972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928484123 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2928484123
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.995399730
Short name T548
Test name
Test status
Simulation time 30610202 ps
CPU time 0.95 seconds
Started May 23 02:52:02 PM PDT 24
Finished May 23 02:52:12 PM PDT 24
Peak memory 214580 kb
Host smart-0fd5e6dd-f15a-49a7-b060-48f87dd7f4df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995399730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.995399730
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2810178770
Short name T494
Test name
Test status
Simulation time 37813096 ps
CPU time 0.93 seconds
Started May 23 02:52:01 PM PDT 24
Finished May 23 02:52:11 PM PDT 24
Peak memory 216048 kb
Host smart-b17bee2c-f8c1-4774-80ed-e2f3146d0196
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810178770 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2810178770
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.3062127694
Short name T72
Test name
Test status
Simulation time 22003882 ps
CPU time 1.04 seconds
Started May 23 02:52:01 PM PDT 24
Finished May 23 02:52:11 PM PDT 24
Peak memory 223492 kb
Host smart-b5b89d7e-9357-410d-9a2d-6e877f758224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062127694 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3062127694
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2357234377
Short name T29
Test name
Test status
Simulation time 26323096 ps
CPU time 1.23 seconds
Started May 23 02:51:51 PM PDT 24
Finished May 23 02:51:58 PM PDT 24
Peak memory 218156 kb
Host smart-32ff4e91-6207-4f53-bce4-6d99e03b5324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357234377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2357234377
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2256151654
Short name T450
Test name
Test status
Simulation time 23762120 ps
CPU time 1.11 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 215336 kb
Host smart-316bb810-a43f-496c-b581-9d2241a5dee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256151654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2256151654
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3236470653
Short name T299
Test name
Test status
Simulation time 60088842 ps
CPU time 1 seconds
Started May 23 02:51:49 PM PDT 24
Finished May 23 02:51:54 PM PDT 24
Peak memory 215032 kb
Host smart-48b2dda2-40ad-4880-b16e-c50391cbb905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236470653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3236470653
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4074216662
Short name T160
Test name
Test status
Simulation time 589757907 ps
CPU time 7.56 seconds
Started May 23 02:51:51 PM PDT 24
Finished May 23 02:52:04 PM PDT 24
Peak memory 216900 kb
Host smart-9a2c3246-97e2-4d78-9204-b23d09c1ec46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074216662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4074216662
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2980427435
Short name T184
Test name
Test status
Simulation time 72499434833 ps
CPU time 430.19 seconds
Started May 23 02:51:50 PM PDT 24
Finished May 23 02:59:06 PM PDT 24
Peak memory 223428 kb
Host smart-6c6303b3-eee0-423a-b72f-c36f2acd4c19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980427435 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2980427435
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.882194341
Short name T181
Test name
Test status
Simulation time 35491297 ps
CPU time 1.28 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 215368 kb
Host smart-91762476-1b2c-4e59-9f9f-67edd87aad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882194341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.882194341
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3193566360
Short name T334
Test name
Test status
Simulation time 15566569 ps
CPU time 0.82 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 206084 kb
Host smart-e7cf383f-4c9e-43ad-9e52-a5bd4d605303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193566360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3193566360
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1379643375
Short name T669
Test name
Test status
Simulation time 41610428 ps
CPU time 0.89 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 216284 kb
Host smart-5d6c6222-9da9-4871-9953-9fc3d6bae4be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379643375 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1379643375
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1964357831
Short name T706
Test name
Test status
Simulation time 61816309 ps
CPU time 1.26 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 216748 kb
Host smart-9b5fdfd2-5f7a-4d32-9e38-9c149902690e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964357831 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1964357831
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2922700442
Short name T427
Test name
Test status
Simulation time 37236367 ps
CPU time 0.98 seconds
Started May 23 02:52:00 PM PDT 24
Finished May 23 02:52:10 PM PDT 24
Peak memory 223372 kb
Host smart-68d58365-5c47-4439-8df8-dbb93298fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922700442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2922700442
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3079689321
Short name T686
Test name
Test status
Simulation time 53997010 ps
CPU time 1.31 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 218876 kb
Host smart-87e543a2-ed79-4938-a318-13b68d01f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079689321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3079689321
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2299463208
Short name T325
Test name
Test status
Simulation time 63270164 ps
CPU time 0.89 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 215136 kb
Host smart-1abc382f-99d8-4849-a5cf-c81495f8b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299463208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2299463208
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.4093461813
Short name T484
Test name
Test status
Simulation time 19852465 ps
CPU time 1.04 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 215052 kb
Host smart-e5c3a593-6c68-4839-a69e-9d3317298e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093461813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4093461813
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.219036278
Short name T196
Test name
Test status
Simulation time 422677315 ps
CPU time 2.65 seconds
Started May 23 02:52:02 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 219344 kb
Host smart-9b568911-ffa5-498b-9106-a624b2648c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219036278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.219036278
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3528951630
Short name T637
Test name
Test status
Simulation time 632672445721 ps
CPU time 1479.36 seconds
Started May 23 02:52:01 PM PDT 24
Finished May 23 03:16:50 PM PDT 24
Peak memory 222696 kb
Host smart-89dd2b90-2a68-4fed-8fda-27b49ce09bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528951630 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3528951630
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.54601528
Short name T258
Test name
Test status
Simulation time 28690601 ps
CPU time 1.33 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 215416 kb
Host smart-08039af7-8eb4-40a7-8c08-06e05587bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54601528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.54601528
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.3378899613
Short name T440
Test name
Test status
Simulation time 13829772 ps
CPU time 0.87 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 206336 kb
Host smart-2b9cd59e-e913-427a-a05c-5634f6a02d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378899613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3378899613
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1325815621
Short name T438
Test name
Test status
Simulation time 13660544 ps
CPU time 0.94 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 216248 kb
Host smart-1db62b33-5587-4c9a-8f34-6671ab025742
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325815621 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1325815621
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3407384546
Short name T571
Test name
Test status
Simulation time 63552114 ps
CPU time 1.01 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 216736 kb
Host smart-094ceb2a-f6bf-44d1-a5f1-9a8a8502cd86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407384546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3407384546
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1679666035
Short name T162
Test name
Test status
Simulation time 71096221 ps
CPU time 1.09 seconds
Started May 23 02:52:01 PM PDT 24
Finished May 23 02:52:10 PM PDT 24
Peak memory 219268 kb
Host smart-2a6f8dfc-578c-43d4-92a3-b1fc1afb0bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679666035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1679666035
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2539629986
Short name T385
Test name
Test status
Simulation time 43910422 ps
CPU time 1.23 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 216812 kb
Host smart-ac119e48-365d-407e-bb85-22d68991a488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539629986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2539629986
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3567981139
Short name T762
Test name
Test status
Simulation time 40939464 ps
CPU time 0.9 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 215188 kb
Host smart-419f6341-6a2f-40bd-88fc-ecd67b48a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567981139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3567981139
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4142439175
Short name T482
Test name
Test status
Simulation time 18805585 ps
CPU time 1.04 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 215124 kb
Host smart-6c80baff-bb14-473a-8341-a95e57ce762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142439175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4142439175
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.757321609
Short name T504
Test name
Test status
Simulation time 138956535 ps
CPU time 3.04 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 216780 kb
Host smart-e0396c7f-8074-4229-8bbe-9e59ba683196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757321609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.757321609
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.399952479
Short name T446
Test name
Test status
Simulation time 53239341711 ps
CPU time 1017.63 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 03:09:11 PM PDT 24
Peak memory 220796 kb
Host smart-159b7e20-adb2-499f-8477-57918d5a6b49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399952479 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.399952479
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.3205108397
Short name T419
Test name
Test status
Simulation time 31241142 ps
CPU time 0.98 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:15 PM PDT 24
Peak memory 214868 kb
Host smart-648fdb8c-ef97-4225-88f1-9a99d7e38a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205108397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3205108397
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3966022284
Short name T199
Test name
Test status
Simulation time 132635549 ps
CPU time 1.07 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 216748 kb
Host smart-5b79604b-066b-4506-8dc0-e56394e49aaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966022284 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3966022284
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.1368845241
Short name T294
Test name
Test status
Simulation time 32160730 ps
CPU time 0.89 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 218048 kb
Host smart-c6e273b0-281d-47e6-8771-57fe54d3a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368845241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1368845241
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.720554519
Short name T503
Test name
Test status
Simulation time 30875178 ps
CPU time 1.36 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 218100 kb
Host smart-4c7a989c-b6ca-4359-86cd-67be9592cbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720554519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.720554519
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2356477929
Short name T690
Test name
Test status
Simulation time 50186719 ps
CPU time 0.9 seconds
Started May 23 02:52:01 PM PDT 24
Finished May 23 02:52:10 PM PDT 24
Peak memory 214952 kb
Host smart-a9541115-f019-4bf9-852d-8be8352cd282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356477929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2356477929
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1075128405
Short name T489
Test name
Test status
Simulation time 23245193 ps
CPU time 0.89 seconds
Started May 23 02:52:03 PM PDT 24
Finished May 23 02:52:14 PM PDT 24
Peak memory 215024 kb
Host smart-5a89a194-7981-4dc5-94ba-e193c98b66d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075128405 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1075128405
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3633584166
Short name T794
Test name
Test status
Simulation time 196447276 ps
CPU time 1.65 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 216852 kb
Host smart-2d853457-308b-42df-b0e0-eb442b7b84d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633584166 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3633584166
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_alert.1828763932
Short name T252
Test name
Test status
Simulation time 66010865 ps
CPU time 1.29 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 215416 kb
Host smart-68067b2f-3eac-4cc7-a4f0-eb14df34ba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828763932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1828763932
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.670982592
Short name T421
Test name
Test status
Simulation time 19533629 ps
CPU time 1.08 seconds
Started May 23 02:52:08 PM PDT 24
Finished May 23 02:52:20 PM PDT 24
Peak memory 206400 kb
Host smart-91e3f8b4-91b8-4297-a174-7e2ccf7be92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670982592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.670982592
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3028418066
Short name T180
Test name
Test status
Simulation time 30665240 ps
CPU time 0.88 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 215248 kb
Host smart-02b311a6-435b-4928-991c-9480d014ba91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028418066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3028418066
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.3558179325
Short name T165
Test name
Test status
Simulation time 21198606 ps
CPU time 1.1 seconds
Started May 23 02:52:02 PM PDT 24
Finished May 23 02:52:12 PM PDT 24
Peak memory 219528 kb
Host smart-b03696dd-4f31-4783-a37e-f6a575d750eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558179325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3558179325
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2358638371
Short name T658
Test name
Test status
Simulation time 228909553 ps
CPU time 1.39 seconds
Started May 23 02:52:04 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 218256 kb
Host smart-bd9676d7-3ece-4daa-b0d5-c4ea0d67b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358638371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2358638371
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3061825139
Short name T297
Test name
Test status
Simulation time 28762444 ps
CPU time 0.93 seconds
Started May 23 02:52:00 PM PDT 24
Finished May 23 02:52:10 PM PDT 24
Peak memory 214932 kb
Host smart-76d34dd9-93e4-43c6-80db-3e9409e61821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061825139 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3061825139
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1294507487
Short name T650
Test name
Test status
Simulation time 44078759 ps
CPU time 0.94 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:16 PM PDT 24
Peak memory 215032 kb
Host smart-2674bdf7-339b-4c81-869a-0506d4fdc337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294507487 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1294507487
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2690087550
Short name T535
Test name
Test status
Simulation time 1049623669 ps
CPU time 3.23 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 02:52:20 PM PDT 24
Peak memory 216572 kb
Host smart-4d3b4bc1-ee5c-4d59-aa5c-d77f32571f64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690087550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2690087550
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3438613918
Short name T192
Test name
Test status
Simulation time 42762253339 ps
CPU time 986.98 seconds
Started May 23 02:52:06 PM PDT 24
Finished May 23 03:08:44 PM PDT 24
Peak memory 223376 kb
Host smart-3987d6aa-d70d-4c76-a267-46dc3f771a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438613918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3438613918
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2152079664
Short name T572
Test name
Test status
Simulation time 44265048 ps
CPU time 1.2 seconds
Started May 23 02:52:15 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215424 kb
Host smart-49c3dc19-23d3-42b2-8902-aee6ed7eaaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152079664 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2152079664
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3612471622
Short name T584
Test name
Test status
Simulation time 39801022 ps
CPU time 0.87 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 206092 kb
Host smart-b4e94a92-bd09-4f78-8496-b2263023ffab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612471622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3612471622
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1420107678
Short name T83
Test name
Test status
Simulation time 33283589 ps
CPU time 0.88 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 216040 kb
Host smart-bb8841ea-db11-48b4-98d1-f6ccc1dc72f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420107678 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1420107678
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.348604629
Short name T817
Test name
Test status
Simulation time 80545392 ps
CPU time 1.08 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 219060 kb
Host smart-d57a11ad-d7fd-4f2b-b25e-87a0c2ca4d1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348604629 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.348604629
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1907755109
Short name T8
Test name
Test status
Simulation time 87166705 ps
CPU time 1.21 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 219420 kb
Host smart-d8e04177-3435-4813-b4e9-834ae00b84e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907755109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1907755109
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1032123362
Short name T408
Test name
Test status
Simulation time 83099473 ps
CPU time 2.68 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:18 PM PDT 24
Peak memory 218712 kb
Host smart-9c38621f-63b4-41d4-9495-3ede46fcb01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032123362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1032123362
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2973628002
Short name T116
Test name
Test status
Simulation time 27611106 ps
CPU time 0.9 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215172 kb
Host smart-4e0e01a3-7506-41b5-a8ab-924cbd0354fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973628002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2973628002
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.4073116577
Short name T663
Test name
Test status
Simulation time 48864800 ps
CPU time 0.91 seconds
Started May 23 02:52:05 PM PDT 24
Finished May 23 02:52:17 PM PDT 24
Peak memory 215004 kb
Host smart-b6b35dda-5a67-43f0-acc0-441c411a5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073116577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.4073116577
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1823979244
Short name T594
Test name
Test status
Simulation time 263927623 ps
CPU time 1.98 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 216620 kb
Host smart-824c99d2-4779-4b80-94b2-ca7c63f636fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823979244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1823979244
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3268005444
Short name T698
Test name
Test status
Simulation time 84222236675 ps
CPU time 976.95 seconds
Started May 23 02:52:27 PM PDT 24
Finished May 23 03:08:47 PM PDT 24
Peak memory 221564 kb
Host smart-f42a158a-69e7-48d7-bf87-1efa643bea36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268005444 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3268005444
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2978050403
Short name T784
Test name
Test status
Simulation time 87712557 ps
CPU time 1.23 seconds
Started May 23 02:52:23 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 215428 kb
Host smart-102e91c9-3860-434a-aed5-567e1ecd5ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978050403 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2978050403
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.530193902
Short name T500
Test name
Test status
Simulation time 93665447 ps
CPU time 0.97 seconds
Started May 23 02:52:23 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 206352 kb
Host smart-2d7ad56f-d8e0-48d4-a008-962288f5a4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530193902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.530193902
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2634706061
Short name T463
Test name
Test status
Simulation time 40605890 ps
CPU time 0.87 seconds
Started May 23 02:52:23 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 215256 kb
Host smart-bbbc8483-08fe-44dd-91d6-ba245c50a3a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634706061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2634706061
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2912908972
Short name T44
Test name
Test status
Simulation time 25825943 ps
CPU time 1.01 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:26 PM PDT 24
Peak memory 219024 kb
Host smart-d7ebab2d-276c-41c2-a307-84d4a172bf41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912908972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2912908972
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1924540656
Short name T722
Test name
Test status
Simulation time 74665305 ps
CPU time 0.91 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 223116 kb
Host smart-8b452dca-b9e5-4af9-9ccc-c26ed9e33da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924540656 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1924540656
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3877590926
Short name T472
Test name
Test status
Simulation time 48028360 ps
CPU time 1.19 seconds
Started May 23 02:52:27 PM PDT 24
Finished May 23 02:52:31 PM PDT 24
Peak memory 216772 kb
Host smart-a7453a20-014c-4453-9057-e13d2d6be3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877590926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3877590926
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.590964095
Short name T390
Test name
Test status
Simulation time 27322886 ps
CPU time 0.94 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 215092 kb
Host smart-0a8a345d-1f62-4460-ba1f-a493a6f2d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590964095 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.590964095
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.482488676
Short name T365
Test name
Test status
Simulation time 38405650 ps
CPU time 0.88 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215036 kb
Host smart-edd344c5-fa85-4635-96c4-e53ee4bec6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482488676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.482488676
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.218358393
Short name T606
Test name
Test status
Simulation time 672110832 ps
CPU time 2.49 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:27 PM PDT 24
Peak memory 215068 kb
Host smart-7b12d077-968e-4ee1-95df-9487d34a4d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218358393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.218358393
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2725989103
Short name T282
Test name
Test status
Simulation time 55571972341 ps
CPU time 1398.27 seconds
Started May 23 02:52:27 PM PDT 24
Finished May 23 03:15:48 PM PDT 24
Peak memory 223440 kb
Host smart-f2ae51c2-cec2-463f-b70c-ef31c485a8da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725989103 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2725989103
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3218769793
Short name T259
Test name
Test status
Simulation time 95222890 ps
CPU time 1.25 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 215424 kb
Host smart-415eac59-f96c-410c-a7f7-1491f66d158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218769793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3218769793
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3738020612
Short name T818
Test name
Test status
Simulation time 35076706 ps
CPU time 0.87 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 206336 kb
Host smart-aa7e0675-cc0b-4ca5-9065-9eea79a5b143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738020612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3738020612
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1616360556
Short name T808
Test name
Test status
Simulation time 23899865 ps
CPU time 0.9 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 216072 kb
Host smart-7b96efb2-1795-4af4-8995-b8708a3f5803
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616360556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1616360556
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3039624962
Short name T766
Test name
Test status
Simulation time 26318809 ps
CPU time 1.19 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 218024 kb
Host smart-93072e30-a224-4a91-ad21-0c3d3651b3d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039624962 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3039624962
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1587845135
Short name T59
Test name
Test status
Simulation time 23102629 ps
CPU time 1.01 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 217968 kb
Host smart-19e97ff0-847a-4ea3-978b-f0e6b11b4f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587845135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1587845135
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.687753321
Short name T274
Test name
Test status
Simulation time 150381705 ps
CPU time 1.24 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:26 PM PDT 24
Peak memory 218124 kb
Host smart-72e349a8-5d17-4115-8758-ae244c6245e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687753321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.687753321
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2009103020
Short name T354
Test name
Test status
Simulation time 27460919 ps
CPU time 0.98 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215332 kb
Host smart-24dd19fb-49b5-4f49-96dd-d3d347dcef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009103020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2009103020
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4273217509
Short name T389
Test name
Test status
Simulation time 22167640 ps
CPU time 0.92 seconds
Started May 23 02:52:22 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 215036 kb
Host smart-607f4820-c326-4462-9cd6-4d9844834def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273217509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4273217509
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3605522169
Short name T558
Test name
Test status
Simulation time 397227672 ps
CPU time 5.37 seconds
Started May 23 02:52:23 PM PDT 24
Finished May 23 02:52:32 PM PDT 24
Peak memory 216620 kb
Host smart-1b13e706-f384-489b-be7c-8b4e87960bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605522169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3605522169
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3721926582
Short name T204
Test name
Test status
Simulation time 41856289153 ps
CPU time 225.81 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:56:09 PM PDT 24
Peak memory 217568 kb
Host smart-0ebfdff7-fb6b-4641-8586-51bb844610eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721926582 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3721926582
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1281551285
Short name T251
Test name
Test status
Simulation time 79760112 ps
CPU time 1.32 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 215428 kb
Host smart-cad48b35-25d9-4151-83d3-911fed7fc349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281551285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1281551285
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3166932825
Short name T699
Test name
Test status
Simulation time 64093234 ps
CPU time 0.95 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:25 PM PDT 24
Peak memory 206248 kb
Host smart-8b672339-a83c-4156-90cd-3ce4150b90b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166932825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3166932825
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3067278067
Short name T88
Test name
Test status
Simulation time 16513501 ps
CPU time 0.82 seconds
Started May 23 02:52:15 PM PDT 24
Finished May 23 02:52:23 PM PDT 24
Peak memory 216080 kb
Host smart-64430d8e-3e86-4502-a80f-4f10487f136d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067278067 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3067278067
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.392534848
Short name T739
Test name
Test status
Simulation time 73628888 ps
CPU time 1.35 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 216712 kb
Host smart-a694fec4-0f5b-4458-a5e7-a770a00abb22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392534848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.392534848
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1088796477
Short name T413
Test name
Test status
Simulation time 48899049 ps
CPU time 1.01 seconds
Started May 23 02:52:21 PM PDT 24
Finished May 23 02:52:26 PM PDT 24
Peak memory 219656 kb
Host smart-eae01873-84c9-4ac7-874a-a7c9b28e76a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088796477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1088796477
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.4131151966
Short name T841
Test name
Test status
Simulation time 46662694 ps
CPU time 1.12 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 218316 kb
Host smart-b33a8002-c7ef-4bb8-b6e1-a9546728de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131151966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.4131151966
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2299247271
Short name T796
Test name
Test status
Simulation time 29106698 ps
CPU time 0.89 seconds
Started May 23 02:52:16 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215496 kb
Host smart-fafa413c-a15a-46c6-add6-1b9dee0c2a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299247271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2299247271
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2962073270
Short name T314
Test name
Test status
Simulation time 18904991 ps
CPU time 1.09 seconds
Started May 23 02:52:27 PM PDT 24
Finished May 23 02:52:31 PM PDT 24
Peak memory 215052 kb
Host smart-ee0ce98a-1e6e-43a2-98ef-3e6a8ce96234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962073270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2962073270
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2890065398
Short name T198
Test name
Test status
Simulation time 399606328 ps
CPU time 4.23 seconds
Started May 23 02:52:18 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 216696 kb
Host smart-7e308370-e565-4c84-846b-1598456eca14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890065398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2890065398
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.875852027
Short name T681
Test name
Test status
Simulation time 51386772030 ps
CPU time 1180.07 seconds
Started May 23 02:52:24 PM PDT 24
Finished May 23 03:12:08 PM PDT 24
Peak memory 220312 kb
Host smart-4f44fc5a-e44b-4de8-ad33-10df630ab2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875852027 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.875852027
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2733466474
Short name T79
Test name
Test status
Simulation time 40730100 ps
CPU time 1.17 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 215436 kb
Host smart-81f69362-0374-4e88-9079-b18b506ba390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733466474 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2733466474
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3450507173
Short name T479
Test name
Test status
Simulation time 13000931 ps
CPU time 0.94 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 206780 kb
Host smart-45050178-9f7c-4e1b-88f5-64de0d3c478d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450507173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3450507173
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1094782967
Short name T177
Test name
Test status
Simulation time 20236300 ps
CPU time 0.91 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 215388 kb
Host smart-0857d48e-9fa8-4e14-8b67-7c1f0aac39be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094782967 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1094782967
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.694656500
Short name T350
Test name
Test status
Simulation time 42891416 ps
CPU time 1.1 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 219260 kb
Host smart-aeb5d52a-f30b-4d6c-bb67-0e94fd71b19d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694656500 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.694656500
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.829228057
Short name T831
Test name
Test status
Simulation time 45511693 ps
CPU time 1 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 219464 kb
Host smart-28e2d852-0760-4fbe-869a-545547bee7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829228057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.829228057
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2058276638
Short name T316
Test name
Test status
Simulation time 35928803 ps
CPU time 1.57 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 218112 kb
Host smart-b33a897b-9e10-4a8f-b3e7-f46ae28296d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058276638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2058276638
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3751116830
Short name T670
Test name
Test status
Simulation time 22688816 ps
CPU time 1.1 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 215308 kb
Host smart-fad505db-ec4d-4036-8aa3-a1379245e7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751116830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3751116830
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1817708304
Short name T763
Test name
Test status
Simulation time 106025221 ps
CPU time 0.92 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 206808 kb
Host smart-c6bdd3ca-207f-4159-bd5f-cdec8d72442a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817708304 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1817708304
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3619874339
Short name T526
Test name
Test status
Simulation time 48606172 ps
CPU time 1.02 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 215024 kb
Host smart-fffe19b2-bff4-4e04-aa2b-0d733ec6229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619874339 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3619874339
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.3520517176
Short name T315
Test name
Test status
Simulation time 207663916 ps
CPU time 1.83 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 216748 kb
Host smart-02a786d2-0b68-4cf6-a64e-a1d84dac87a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520517176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.3520517176
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.721119481
Short name T805
Test name
Test status
Simulation time 229056117445 ps
CPU time 1497.86 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 03:15:26 PM PDT 24
Peak memory 225900 kb
Host smart-467de4ab-af3f-4705-b93f-71a2d76a04ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721119481 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.721119481
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.1278115160
Short name T801
Test name
Test status
Simulation time 29416972 ps
CPU time 0.96 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:33 PM PDT 24
Peak memory 206292 kb
Host smart-45e1c31b-6458-4354-adb7-9b63527c0233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278115160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1278115160
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2278803600
Short name T87
Test name
Test status
Simulation time 25154112 ps
CPU time 0.85 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:33 PM PDT 24
Peak memory 216240 kb
Host smart-9b1b97e8-3070-4a82-84a9-9d0b6eccd8a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278803600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2278803600
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.319855820
Short name T697
Test name
Test status
Simulation time 78790072 ps
CPU time 1.09 seconds
Started May 23 02:52:29 PM PDT 24
Finished May 23 02:52:32 PM PDT 24
Peak memory 218068 kb
Host smart-98860029-4df9-43a5-985d-d590ce996aa3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319855820 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.319855820
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3173134557
Short name T581
Test name
Test status
Simulation time 47448756 ps
CPU time 0.83 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:33 PM PDT 24
Peak memory 217680 kb
Host smart-32d78b53-32ac-4484-87f2-4a15803200e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173134557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3173134557
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4215893630
Short name T633
Test name
Test status
Simulation time 31637559 ps
CPU time 1.38 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:26 PM PDT 24
Peak memory 216920 kb
Host smart-4d22d750-7268-4f14-acbe-9878d3ba3d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215893630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4215893630
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.755226287
Short name T300
Test name
Test status
Simulation time 22605122 ps
CPU time 1.15 seconds
Started May 23 02:52:19 PM PDT 24
Finished May 23 02:52:26 PM PDT 24
Peak memory 215340 kb
Host smart-32cb75db-e295-4dd4-a1c3-aa8f478bedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755226287 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.755226287
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1203274687
Short name T480
Test name
Test status
Simulation time 43273489 ps
CPU time 0.91 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:24 PM PDT 24
Peak memory 215032 kb
Host smart-657199b2-1974-4bdb-be7d-313108f465e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203274687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1203274687
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1273568368
Short name T424
Test name
Test status
Simulation time 631306486 ps
CPU time 4.95 seconds
Started May 23 02:52:17 PM PDT 24
Finished May 23 02:52:28 PM PDT 24
Peak memory 216708 kb
Host smart-a30501b6-1649-4010-ac21-aa70fe80f450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273568368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1273568368
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2962828527
Short name T830
Test name
Test status
Simulation time 254011180030 ps
CPU time 956.82 seconds
Started May 23 02:52:22 PM PDT 24
Finished May 23 03:08:24 PM PDT 24
Peak memory 220448 kb
Host smart-365e0123-91fd-4a67-8b64-77a06c7fbc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962828527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2962828527
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3668321723
Short name T99
Test name
Test status
Simulation time 28278276 ps
CPU time 1.18 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 215428 kb
Host smart-204e0133-10ef-4a7c-834e-f4918bc8e558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668321723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3668321723
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2459392357
Short name T342
Test name
Test status
Simulation time 18068738 ps
CPU time 1.08 seconds
Started May 23 02:52:29 PM PDT 24
Finished May 23 02:52:33 PM PDT 24
Peak memory 206484 kb
Host smart-fb0cf67c-6e67-4253-96d7-9a28b506313a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459392357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2459392357
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.921751548
Short name T528
Test name
Test status
Simulation time 19586530 ps
CPU time 0.93 seconds
Started May 23 02:52:32 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 215396 kb
Host smart-50ed1347-7640-4bbe-9d38-1b556f5f3da1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921751548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.921751548
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.721324807
Short name T172
Test name
Test status
Simulation time 103960196 ps
CPU time 1.1 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 216584 kb
Host smart-5edb7eaf-771a-44b6-8a71-59966d0bb0c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721324807 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.721324807
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.760526983
Short name T612
Test name
Test status
Simulation time 85947010 ps
CPU time 1.04 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 218016 kb
Host smart-81f91fc6-2a72-4880-a7d3-58de4f307ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760526983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.760526983
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1444858394
Short name T193
Test name
Test status
Simulation time 39258051 ps
CPU time 1.48 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 218008 kb
Host smart-fd006405-3fb2-48d2-83e7-a31bad1b588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444858394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1444858394
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3280640196
Short name T623
Test name
Test status
Simulation time 21296414 ps
CPU time 1.23 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 223620 kb
Host smart-89d2bbe7-5b02-4805-9b1c-a389f613dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280640196 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3280640196
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3491097470
Short name T369
Test name
Test status
Simulation time 27500911 ps
CPU time 0.93 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:34 PM PDT 24
Peak memory 215032 kb
Host smart-63dd293d-391e-4bce-bcd1-48687ef0e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491097470 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3491097470
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.50369478
Short name T444
Test name
Test status
Simulation time 200303596 ps
CPU time 4.25 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 214852 kb
Host smart-68f2a7bb-7d27-4fa4-8a2d-a90b745a2e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50369478 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.50369478
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1205134567
Short name T835
Test name
Test status
Simulation time 52866398016 ps
CPU time 1248.4 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 03:13:21 PM PDT 24
Peak memory 220692 kb
Host smart-5d3a5523-9e0d-444b-a80b-9f4a76386ae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205134567 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1205134567
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.4061505935
Short name T262
Test name
Test status
Simulation time 38085116 ps
CPU time 1.19 seconds
Started May 23 02:52:32 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 215412 kb
Host smart-9685a836-95d1-4466-80ab-daacf640fdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061505935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.4061505935
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.195794211
Short name T643
Test name
Test status
Simulation time 40263455 ps
CPU time 0.84 seconds
Started May 23 02:52:33 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 206068 kb
Host smart-972e7208-3139-4e07-b1b9-fdb510047a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195794211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.195794211
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3411108570
Short name T179
Test name
Test status
Simulation time 39343017 ps
CPU time 0.87 seconds
Started May 23 02:52:34 PM PDT 24
Finished May 23 02:52:37 PM PDT 24
Peak memory 215252 kb
Host smart-24f11d31-0c12-4ef9-a7a5-36c362cb4fc0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411108570 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3411108570
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.1977150765
Short name T98
Test name
Test status
Simulation time 32279764 ps
CPU time 0.94 seconds
Started May 23 02:52:32 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 217960 kb
Host smart-052f3a34-68a5-4fe5-8de1-1362ff9f9d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977150765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1977150765
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2222131703
Short name T122
Test name
Test status
Simulation time 84537665 ps
CPU time 1.5 seconds
Started May 23 02:52:32 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 218372 kb
Host smart-a7860a21-725f-413c-964e-440addb1cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222131703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2222131703
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.2368378370
Short name T465
Test name
Test status
Simulation time 29934271 ps
CPU time 1.03 seconds
Started May 23 02:52:32 PM PDT 24
Finished May 23 02:52:36 PM PDT 24
Peak memory 215068 kb
Host smart-811b1c14-3344-4d8e-a89f-f891d4760167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368378370 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2368378370
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1469736244
Short name T374
Test name
Test status
Simulation time 284522640 ps
CPU time 1.91 seconds
Started May 23 02:52:30 PM PDT 24
Finished May 23 02:52:35 PM PDT 24
Peak memory 216792 kb
Host smart-6e65dc0e-5209-44ff-b11a-f0fb42f5958e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469736244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1469736244
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2771555391
Short name T510
Test name
Test status
Simulation time 101650814331 ps
CPU time 1700.14 seconds
Started May 23 02:52:33 PM PDT 24
Finished May 23 03:20:56 PM PDT 24
Peak memory 224964 kb
Host smart-e3d9aaf5-c13c-497a-834a-8dfa7e18e183
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771555391 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2771555391
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1112045258
Short name T664
Test name
Test status
Simulation time 24242782 ps
CPU time 1.23 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 215420 kb
Host smart-60978d43-5f66-4760-ae5d-6b20e37cd448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112045258 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1112045258
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1653893936
Short name T646
Test name
Test status
Simulation time 20005863 ps
CPU time 1.03 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 206452 kb
Host smart-d70f1dc1-36b9-4799-befb-417f474e1105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653893936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1653893936
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3662030975
Short name T740
Test name
Test status
Simulation time 15512467 ps
CPU time 0.93 seconds
Started May 23 02:52:49 PM PDT 24
Finished May 23 02:52:52 PM PDT 24
Peak memory 216220 kb
Host smart-fc88fe03-cb86-4a4a-a54d-7aa2bd0645df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662030975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3662030975
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.196442283
Short name T750
Test name
Test status
Simulation time 120800273 ps
CPU time 1.19 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 216796 kb
Host smart-a676542c-92ce-4173-9906-5b61af45b3c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196442283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.196442283
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4065724002
Short name T468
Test name
Test status
Simulation time 93132353 ps
CPU time 1.2 seconds
Started May 23 02:52:55 PM PDT 24
Finished May 23 02:53:00 PM PDT 24
Peak memory 219276 kb
Host smart-3ff8d6b5-b4eb-4eac-a53b-99643f584741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065724002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4065724002
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1592242761
Short name T452
Test name
Test status
Simulation time 57632129 ps
CPU time 1.91 seconds
Started May 23 02:52:46 PM PDT 24
Finished May 23 02:52:49 PM PDT 24
Peak memory 217776 kb
Host smart-3ca843ca-e613-4a61-993c-9651e29efaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592242761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1592242761
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.503076061
Short name T5
Test name
Test status
Simulation time 55546838 ps
CPU time 0.83 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 214940 kb
Host smart-286e8493-0bce-4448-aa86-e3f54acaf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503076061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.503076061
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2178647079
Short name T530
Test name
Test status
Simulation time 73470321 ps
CPU time 0.93 seconds
Started May 23 02:52:55 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 214996 kb
Host smart-440c375e-aae7-4da2-9620-4bbdb137b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178647079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2178647079
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1484454373
Short name T837
Test name
Test status
Simulation time 141428045 ps
CPU time 1.95 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 218040 kb
Host smart-f32045a7-d44a-4538-8bef-a3bc2b82752a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484454373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1484454373
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1354738432
Short name T265
Test name
Test status
Simulation time 91539361624 ps
CPU time 1210.77 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 03:13:03 PM PDT 24
Peak memory 224428 kb
Host smart-0e3fd91f-0f32-46db-84d9-6d15642356ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354738432 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1354738432
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3188231006
Short name T644
Test name
Test status
Simulation time 83836904 ps
CPU time 1.2 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:52 PM PDT 24
Peak memory 215308 kb
Host smart-6d1b613f-c28b-4332-bc3c-068be21c7350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188231006 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3188231006
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3544561617
Short name T611
Test name
Test status
Simulation time 117666138 ps
CPU time 1.03 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:54 PM PDT 24
Peak memory 214504 kb
Host smart-d5e3a43a-a875-442e-9263-84efd7503c52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544561617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3544561617
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2338203423
Short name T339
Test name
Test status
Simulation time 158795039 ps
CPU time 0.91 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 215872 kb
Host smart-6f4c57df-f635-47a4-8646-dfa6b39071ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338203423 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2338203423
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.1819935170
Short name T678
Test name
Test status
Simulation time 19675190 ps
CPU time 1.11 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 218244 kb
Host smart-45ec31ed-45f0-4ba3-92cf-16392a656311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819935170 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1819935170
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.310554443
Short name T11
Test name
Test status
Simulation time 35879965 ps
CPU time 1.32 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:55 PM PDT 24
Peak memory 219400 kb
Host smart-e1f9ba2a-bf04-4408-aee3-7f15393f5a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310554443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.310554443
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1973310164
Short name T654
Test name
Test status
Simulation time 39781416 ps
CPU time 0.91 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 215256 kb
Host smart-1428e362-3d21-4104-b64d-e194a19f9ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973310164 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1973310164
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.30809761
Short name T351
Test name
Test status
Simulation time 23016507 ps
CPU time 0.96 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 206636 kb
Host smart-fc2d7eae-162e-49a3-a77e-133b5ec7dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30809761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.30809761
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3133666214
Short name T583
Test name
Test status
Simulation time 28646778 ps
CPU time 1.15 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:54 PM PDT 24
Peak memory 206144 kb
Host smart-38683658-a5e6-4daa-9232-e7b7230bce28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133666214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3133666214
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.491298549
Short name T186
Test name
Test status
Simulation time 359387890421 ps
CPU time 1758 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 03:22:10 PM PDT 24
Peak memory 224016 kb
Host smart-dc57387f-e56b-4007-b8b8-b051d5eae09c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491298549 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.491298549
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1154692178
Short name T257
Test name
Test status
Simulation time 91763723 ps
CPU time 1.23 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 215428 kb
Host smart-d2836f4f-3625-4d45-949f-1181efc5f67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154692178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1154692178
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3429170329
Short name T455
Test name
Test status
Simulation time 17555736 ps
CPU time 0.97 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:57 PM PDT 24
Peak memory 206344 kb
Host smart-c44c4a95-c763-4ee3-83f9-d4eabfa2ef7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429170329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3429170329
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1542849031
Short name T63
Test name
Test status
Simulation time 12612257 ps
CPU time 0.95 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 215412 kb
Host smart-110b8164-d204-4fa3-9ad3-28d1a3926588
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542849031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1542849031
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3182400321
Short name T807
Test name
Test status
Simulation time 31241309 ps
CPU time 1.22 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:55 PM PDT 24
Peak memory 219396 kb
Host smart-6d8d29eb-cdd9-409b-9ca8-b33d2bd3b1af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182400321 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3182400321
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.1984322295
Short name T821
Test name
Test status
Simulation time 18638328 ps
CPU time 1.19 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 223380 kb
Host smart-ca46e6a6-ab5d-4d95-85e5-502eafe42c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984322295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1984322295
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.93043054
Short name T529
Test name
Test status
Simulation time 58429816 ps
CPU time 1.23 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 218152 kb
Host smart-9b399c7a-897b-4bdd-ab4f-b151d669d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93043054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.93043054
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1839391347
Short name T764
Test name
Test status
Simulation time 22314234 ps
CPU time 1.13 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 215124 kb
Host smart-8c38825d-f48a-4742-8ccc-76464b4d09f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839391347 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1839391347
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.840559550
Short name T679
Test name
Test status
Simulation time 18291864 ps
CPU time 1.04 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:57 PM PDT 24
Peak memory 206828 kb
Host smart-c6c617ea-0cfb-4fed-beae-39ca759887c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840559550 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.840559550
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1678370933
Short name T590
Test name
Test status
Simulation time 290796287 ps
CPU time 4.35 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:53:01 PM PDT 24
Peak memory 214844 kb
Host smart-ecc1ddf4-a027-43bb-966e-c4bd51792007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678370933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1678370933
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1058121408
Short name T691
Test name
Test status
Simulation time 39271862391 ps
CPU time 971.26 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 03:09:06 PM PDT 24
Peak memory 218876 kb
Host smart-c8541d50-67b2-423c-9c90-6b7b6d47e9e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058121408 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1058121408
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2218225213
Short name T32
Test name
Test status
Simulation time 26597703 ps
CPU time 1.3 seconds
Started May 23 02:52:49 PM PDT 24
Finished May 23 02:52:52 PM PDT 24
Peak memory 215420 kb
Host smart-d0034d67-ae68-4c27-ab7c-1b79e9e141d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218225213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2218225213
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2301458502
Short name T780
Test name
Test status
Simulation time 29192700 ps
CPU time 0.9 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:54 PM PDT 24
Peak memory 206456 kb
Host smart-c23d2b08-33e7-4a73-b598-bbebabf7bf14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301458502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2301458502
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2309688543
Short name T178
Test name
Test status
Simulation time 41953948 ps
CPU time 0.81 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 215128 kb
Host smart-3d203bc9-176e-40a7-9c25-420dd06d7eff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309688543 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2309688543
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.660385659
Short name T786
Test name
Test status
Simulation time 27513931 ps
CPU time 1.08 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:53 PM PDT 24
Peak memory 217868 kb
Host smart-91121fce-25ee-4a9f-a701-6b6335a7946d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660385659 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_di
sable_auto_req_mode.660385659
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1118920708
Short name T683
Test name
Test status
Simulation time 142213934 ps
CPU time 1.14 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:52 PM PDT 24
Peak memory 229412 kb
Host smart-e5b2d9a7-425b-4725-bec1-0b0afc5c56bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118920708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1118920708
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3002777678
Short name T600
Test name
Test status
Simulation time 58318886 ps
CPU time 1.1 seconds
Started May 23 02:52:55 PM PDT 24
Finished May 23 02:53:00 PM PDT 24
Peak memory 218248 kb
Host smart-757abad9-eabb-4935-b71f-ccba56482884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002777678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3002777678
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_smoke.4276835882
Short name T642
Test name
Test status
Simulation time 46886006 ps
CPU time 0.93 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:54 PM PDT 24
Peak memory 215040 kb
Host smart-40203c58-64c7-4dff-91a4-2878261639fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276835882 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.4276835882
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1915452675
Short name T604
Test name
Test status
Simulation time 262992751 ps
CPU time 3.16 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:53:02 PM PDT 24
Peak memory 218088 kb
Host smart-f97799b9-b7ea-4f58-8bd9-d92ab574af28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915452675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1915452675
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.806562362
Short name T559
Test name
Test status
Simulation time 30715773986 ps
CPU time 404.25 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:59:42 PM PDT 24
Peak memory 223408 kb
Host smart-15c833b7-c4a9-48a7-b099-93873ff3f564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806562362 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.806562362
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1498939154
Short name T665
Test name
Test status
Simulation time 44314517 ps
CPU time 1.21 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:53 PM PDT 24
Peak memory 215424 kb
Host smart-d9de8741-ea47-4a57-8291-a0ee7f0c32f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498939154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1498939154
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.847937108
Short name T431
Test name
Test status
Simulation time 55528702 ps
CPU time 0.96 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 206372 kb
Host smart-df848c13-3087-4574-a6fc-425bb7fc6f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847937108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.847937108
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4087163390
Short name T790
Test name
Test status
Simulation time 34783385 ps
CPU time 0.84 seconds
Started May 23 02:52:49 PM PDT 24
Finished May 23 02:52:51 PM PDT 24
Peak memory 216204 kb
Host smart-3058e58f-b94c-4b26-8fed-d9bcbf888c8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087163390 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4087163390
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2860125280
Short name T203
Test name
Test status
Simulation time 152409488 ps
CPU time 1.16 seconds
Started May 23 02:52:55 PM PDT 24
Finished May 23 02:53:00 PM PDT 24
Peak memory 216696 kb
Host smart-f4e67339-e11d-41f2-8024-8fb2294317d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860125280 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2860125280
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.898557321
Short name T54
Test name
Test status
Simulation time 26883698 ps
CPU time 1.31 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 217004 kb
Host smart-1cff40d5-09f0-4f8d-b74b-0cb11b670ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898557321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.898557321
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2684308534
Short name T388
Test name
Test status
Simulation time 69115946 ps
CPU time 1.05 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:52 PM PDT 24
Peak memory 216612 kb
Host smart-959fac68-c262-467d-9c25-f1be67c8a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684308534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2684308534
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1074679931
Short name T127
Test name
Test status
Simulation time 24707989 ps
CPU time 1.03 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 223628 kb
Host smart-4da2cd05-e344-473a-bd41-892227a8d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074679931 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1074679931
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3403492149
Short name T655
Test name
Test status
Simulation time 24721040 ps
CPU time 0.99 seconds
Started May 23 02:52:51 PM PDT 24
Finished May 23 02:52:55 PM PDT 24
Peak memory 215036 kb
Host smart-96abe519-9e18-4654-a24e-5259093180af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403492149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3403492149
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4254229138
Short name T197
Test name
Test status
Simulation time 863409364 ps
CPU time 2.66 seconds
Started May 23 02:52:50 PM PDT 24
Finished May 23 02:52:54 PM PDT 24
Peak memory 215036 kb
Host smart-8de7daab-2d82-42d2-a1f8-d2530d4737b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254229138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4254229138
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1119082485
Short name T146
Test name
Test status
Simulation time 19089986474 ps
CPU time 431.21 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 03:00:09 PM PDT 24
Peak memory 217464 kb
Host smart-637435f6-8e9e-4a79-9a01-82c2fecb8410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119082485 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1119082485
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.603501723
Short name T260
Test name
Test status
Simulation time 24916198 ps
CPU time 1.26 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:56 PM PDT 24
Peak memory 215304 kb
Host smart-6d308666-2fda-4530-ba47-6921c5f70554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603501723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.603501723
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1955737648
Short name T464
Test name
Test status
Simulation time 34117768 ps
CPU time 0.82 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 206596 kb
Host smart-5f49dbd7-885e-40b6-9382-6f3d1fdf566b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955737648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1955737648
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1321021053
Short name T176
Test name
Test status
Simulation time 13038407 ps
CPU time 0.88 seconds
Started May 23 02:52:52 PM PDT 24
Finished May 23 02:52:55 PM PDT 24
Peak memory 216240 kb
Host smart-cf99685d-64e0-4fdb-84eb-f75c36f4cc72
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321021053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1321021053
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.648007235
Short name T232
Test name
Test status
Simulation time 72125058 ps
CPU time 1.2 seconds
Started May 23 02:52:53 PM PDT 24
Finished May 23 02:52:58 PM PDT 24
Peak memory 218300 kb
Host smart-584fcdfa-f10b-4ac8-bd9b-6f4879ec9dc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648007235 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.648007235
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1110243727
Short name T58
Test name
Test status
Simulation time 38505641 ps
CPU time 0.86 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 217992 kb
Host smart-af8c9263-3877-4032-9371-93cf048277f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110243727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1110243727
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3597849073
Short name T757
Test name
Test status
Simulation time 62930434 ps
CPU time 1.28 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 217800 kb
Host smart-12e308e2-5c9f-425a-8a72-74537ecfa57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597849073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3597849073
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3546817188
Short name T105
Test name
Test status
Simulation time 23156646 ps
CPU time 1.08 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 215320 kb
Host smart-7e5f769b-40e9-42e9-b2ff-10de127c8893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546817188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3546817188
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3306406786
Short name T303
Test name
Test status
Simulation time 66655584 ps
CPU time 0.93 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 214996 kb
Host smart-3b451db6-1a2e-4b18-a1c8-97b3a100face
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306406786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3306406786
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.606689162
Short name T418
Test name
Test status
Simulation time 1058501421 ps
CPU time 5.35 seconds
Started May 23 02:52:54 PM PDT 24
Finished May 23 02:53:04 PM PDT 24
Peak memory 216732 kb
Host smart-ff009be1-bb08-45d6-bcfa-14c77e61fbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606689162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.606689162
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_alert.176483493
Short name T256
Test name
Test status
Simulation time 28623119 ps
CPU time 1.29 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 215416 kb
Host smart-2c54be87-9e52-4657-b6d8-a07bbf31a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176483493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.176483493
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2984568426
Short name T305
Test name
Test status
Simulation time 179737532 ps
CPU time 0.97 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:09 PM PDT 24
Peak memory 214596 kb
Host smart-e2b905b6-bc98-4d96-aca4-f5e2eb549107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984568426 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2984568426
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.589602399
Short name T82
Test name
Test status
Simulation time 99195380 ps
CPU time 0.85 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 216068 kb
Host smart-3380a213-ba5f-4d9f-96e9-f70d0c54a401
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589602399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.589602399
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3651797805
Short name T370
Test name
Test status
Simulation time 61723980 ps
CPU time 1.3 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:09 PM PDT 24
Peak memory 216464 kb
Host smart-a17627f6-e164-4426-8694-cb7c79f363ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651797805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3651797805
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.93429623
Short name T45
Test name
Test status
Simulation time 54117796 ps
CPU time 1.37 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 224992 kb
Host smart-900701c2-87ef-484b-8110-c38269030708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93429623 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.93429623
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3550316077
Short name T544
Test name
Test status
Simulation time 187112837 ps
CPU time 1.34 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 218120 kb
Host smart-d79180d3-e9f5-4e76-8550-4ab55c9536c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550316077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3550316077
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.597864826
Short name T761
Test name
Test status
Simulation time 22001633 ps
CPU time 1.24 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 223580 kb
Host smart-74d959e5-b1bc-4e81-a6d3-d550b15eb350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597864826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.597864826
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2509713658
Short name T306
Test name
Test status
Simulation time 48093851 ps
CPU time 0.94 seconds
Started May 23 02:52:55 PM PDT 24
Finished May 23 02:52:59 PM PDT 24
Peak memory 214996 kb
Host smart-991e307c-d444-4d48-a3cc-8febeaf8176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509713658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2509713658
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2483627813
Short name T574
Test name
Test status
Simulation time 581815110 ps
CPU time 3.54 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:10 PM PDT 24
Peak memory 215044 kb
Host smart-baa7478d-fc0c-4a45-8a4f-2db1e98d29cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483627813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2483627813
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3331359594
Short name T735
Test name
Test status
Simulation time 96609882835 ps
CPU time 2299.31 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 03:31:30 PM PDT 24
Peak memory 227292 kb
Host smart-78128981-b85b-4aee-86cf-62ce44586145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331359594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3331359594
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2185570366
Short name T78
Test name
Test status
Simulation time 76713846 ps
CPU time 1.13 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 215384 kb
Host smart-01ea5eb9-0890-45eb-9642-9e358328ab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185570366 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2185570366
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2827961539
Short name T704
Test name
Test status
Simulation time 18900340 ps
CPU time 1.05 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 206316 kb
Host smart-9d6a23f4-9d1f-45ca-b223-a046147c72e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827961539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2827961539
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.835079680
Short name T844
Test name
Test status
Simulation time 44196281 ps
CPU time 0.86 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:27 PM PDT 24
Peak memory 215232 kb
Host smart-a7ef6bab-7c04-4f5d-a22b-353ea41f6a61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835079680 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.835079680
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.269688262
Short name T822
Test name
Test status
Simulation time 20328882 ps
CPU time 1.13 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 217992 kb
Host smart-ff97d2f5-d19e-411c-bc9a-27825d0cbe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269688262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.269688262
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.4191360233
Short name T348
Test name
Test status
Simulation time 100564960 ps
CPU time 1.21 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 216704 kb
Host smart-52c01810-85d8-4d01-a7a9-7aa69b5222a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191360233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.4191360233
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2792584293
Short name T102
Test name
Test status
Simulation time 26985830 ps
CPU time 1.1 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 223564 kb
Host smart-7f777c56-d0ae-4927-a5b1-462350484015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792584293 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2792584293
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1266503735
Short name T249
Test name
Test status
Simulation time 30597073 ps
CPU time 0.99 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 206816 kb
Host smart-825197c0-9178-4c2a-9ec5-47f3ed78425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266503735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1266503735
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4239083960
Short name T458
Test name
Test status
Simulation time 84358628 ps
CPU time 0.92 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 214712 kb
Host smart-60df77ad-a829-4ca4-b403-9cf24d4f3ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239083960 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4239083960
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3582068968
Short name T474
Test name
Test status
Simulation time 132302576 ps
CPU time 3.08 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 216516 kb
Host smart-9ea658e4-db4f-4221-ac23-8aa190dc25ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582068968 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3582068968
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1343930318
Short name T396
Test name
Test status
Simulation time 122940189698 ps
CPU time 487.22 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:58:35 PM PDT 24
Peak memory 219168 kb
Host smart-d5cb9711-3918-448a-805b-249ff02ebcda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343930318 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1343930318
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1427790836
Short name T547
Test name
Test status
Simulation time 21985089 ps
CPU time 0.95 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:09 PM PDT 24
Peak memory 218356 kb
Host smart-f8cf0b68-ca22-4733-bca4-0c2f84033454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427790836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1427790836
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3864068829
Short name T425
Test name
Test status
Simulation time 91034094 ps
CPU time 1.53 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 217960 kb
Host smart-9e03c0f5-87ff-4bb8-8243-72e932ff1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864068829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3864068829
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2641362731
Short name T693
Test name
Test status
Simulation time 20715531 ps
CPU time 1.07 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:09 PM PDT 24
Peak memory 217996 kb
Host smart-d3879add-b50a-48e1-9481-55c6ca33ed49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641362731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2641362731
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4182506051
Short name T133
Test name
Test status
Simulation time 62711102 ps
CPU time 2.13 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 217944 kb
Host smart-88415b37-31d0-4ea6-aba9-83745b7d5469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182506051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4182506051
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2769987056
Short name T428
Test name
Test status
Simulation time 66326292 ps
CPU time 1.13 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 219252 kb
Host smart-607ee26c-2043-47a7-98eb-d07814790b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769987056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2769987056
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2781862184
Short name T291
Test name
Test status
Simulation time 53630512 ps
CPU time 1.37 seconds
Started May 23 02:53:02 PM PDT 24
Finished May 23 02:53:07 PM PDT 24
Peak memory 219432 kb
Host smart-afc97cdf-ba7f-4058-97f6-48d10ecd7c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781862184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2781862184
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2912000536
Short name T65
Test name
Test status
Simulation time 19890701 ps
CPU time 1.08 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 218012 kb
Host smart-b22d9d90-bcb6-469d-ac5c-a66b689435ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912000536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2912000536
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1542843702
Short name T692
Test name
Test status
Simulation time 60911447 ps
CPU time 1.93 seconds
Started May 23 02:53:02 PM PDT 24
Finished May 23 02:53:07 PM PDT 24
Peak memory 218184 kb
Host smart-95429b32-a5c3-4d55-8a34-9f9427fb6d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542843702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1542843702
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.552712583
Short name T31
Test name
Test status
Simulation time 20560056 ps
CPU time 1.23 seconds
Started May 23 02:53:08 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 229240 kb
Host smart-a7dc9865-f8b3-419f-b49a-aa2758cf978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552712583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.552712583
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2051821175
Short name T485
Test name
Test status
Simulation time 165392650 ps
CPU time 1.38 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 218280 kb
Host smart-f8eed406-af48-450d-9ca8-16c0042f8e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051821175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2051821175
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2345931005
Short name T777
Test name
Test status
Simulation time 35240660 ps
CPU time 0.95 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 219696 kb
Host smart-8f84dd72-c3f6-4ebd-bd61-0f4920f81707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345931005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2345931005
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3844344572
Short name T828
Test name
Test status
Simulation time 93373618 ps
CPU time 1.43 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 218112 kb
Host smart-e8baa750-8021-422a-95d5-822d912973dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844344572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3844344572
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.148071359
Short name T842
Test name
Test status
Simulation time 25336523 ps
CPU time 1 seconds
Started May 23 02:53:09 PM PDT 24
Finished May 23 02:53:14 PM PDT 24
Peak memory 218140 kb
Host smart-a4eeab3f-7a27-45aa-8038-f8c43ed30e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148071359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.148071359
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.509788931
Short name T501
Test name
Test status
Simulation time 57649044 ps
CPU time 1 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 216628 kb
Host smart-f2caf95e-e1cf-4060-aa36-0e5d30216754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509788931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.509788931
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_genbits.2795544349
Short name T625
Test name
Test status
Simulation time 32921626 ps
CPU time 1.3 seconds
Started May 23 02:53:03 PM PDT 24
Finished May 23 02:53:08 PM PDT 24
Peak memory 216704 kb
Host smart-5ce95f86-13eb-44c9-8099-b54452357c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795544349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2795544349
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2909666364
Short name T30
Test name
Test status
Simulation time 54473957 ps
CPU time 1.04 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 220272 kb
Host smart-4f4f1e98-ac52-4169-ad3f-da26f31448b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909666364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2909666364
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2175880213
Short name T579
Test name
Test status
Simulation time 26298923 ps
CPU time 1.34 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 216800 kb
Host smart-e80a1122-8be7-497a-8b99-a8e2974b5280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175880213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2175880213
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3665607775
Short name T74
Test name
Test status
Simulation time 20122502 ps
CPU time 1.02 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 214960 kb
Host smart-791e2739-2726-4ad8-9699-5553e3cd0e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665607775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3665607775
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3111038184
Short name T382
Test name
Test status
Simulation time 43299398 ps
CPU time 1.16 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 216692 kb
Host smart-818769d4-c23a-444e-9228-0af1ea871a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111038184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3111038184
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.453073236
Short name T653
Test name
Test status
Simulation time 40623549 ps
CPU time 1.32 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 215404 kb
Host smart-d927856b-969b-4d36-95e1-4183d6f2a619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453073236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.453073236
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1531480828
Short name T724
Test name
Test status
Simulation time 17551686 ps
CPU time 1.01 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:31 PM PDT 24
Peak memory 214552 kb
Host smart-0c85cf69-1871-46ae-af3f-104f3fef55f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531480828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1531480828
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1848591416
Short name T797
Test name
Test status
Simulation time 23240790 ps
CPU time 0.79 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 216096 kb
Host smart-5d2390a1-7f33-4caa-91b9-e1ec12c24233
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848591416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1848591416
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3012364594
Short name T136
Test name
Test status
Simulation time 43121915 ps
CPU time 1.01 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 216520 kb
Host smart-87e22117-e300-4021-a3ec-c58962e84ce7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012364594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3012364594
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1412181505
Short name T707
Test name
Test status
Simulation time 50500042 ps
CPU time 1.01 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 218240 kb
Host smart-18b93dc5-58d1-43ab-bf4f-fb82c57d5d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412181505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1412181505
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1112830526
Short name T580
Test name
Test status
Simulation time 197711829 ps
CPU time 3.02 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 216896 kb
Host smart-85868893-8fc1-433b-88bd-88ad5211a96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112830526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1112830526
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3618907315
Short name T632
Test name
Test status
Simulation time 21751804 ps
CPU time 1.25 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 223620 kb
Host smart-13559b53-7913-4c55-baea-082f2cf16e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618907315 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3618907315
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.2917009270
Short name T737
Test name
Test status
Simulation time 58659174 ps
CPU time 0.9 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 215044 kb
Host smart-9cee3b18-1cbb-49e9-ac20-b2e8fba94584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917009270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2917009270
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.847538646
Short name T359
Test name
Test status
Simulation time 456045127 ps
CPU time 3.23 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 216584 kb
Host smart-5daf5b6c-62a7-421a-9be1-1f28053684aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847538646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.847538646
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1652606841
Short name T117
Test name
Test status
Simulation time 17409390923 ps
CPU time 424.34 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:57:36 PM PDT 24
Peak memory 223188 kb
Host smart-21eb74e8-4f5c-4d1c-acc0-eb4b186cd1b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652606841 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1652606841
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2008279131
Short name T64
Test name
Test status
Simulation time 22714325 ps
CPU time 1.07 seconds
Started May 23 02:53:08 PM PDT 24
Finished May 23 02:53:14 PM PDT 24
Peak memory 223564 kb
Host smart-b32762f2-575f-41f5-8cbe-6d0a07098378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008279131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2008279131
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.204006896
Short name T264
Test name
Test status
Simulation time 155802511 ps
CPU time 1.11 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 216708 kb
Host smart-b2b1431f-5ce6-46f1-a975-b6ceaf84c57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204006896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.204006896
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3169241885
Short name T175
Test name
Test status
Simulation time 18629727 ps
CPU time 1.05 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 217972 kb
Host smart-195081d5-d9c2-47f7-bc50-e1e9df08755d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169241885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3169241885
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1478265185
Short name T124
Test name
Test status
Simulation time 59347847 ps
CPU time 1.39 seconds
Started May 23 02:53:10 PM PDT 24
Finished May 23 02:53:15 PM PDT 24
Peak memory 216784 kb
Host smart-248efc0d-a4bc-4a0d-9884-93a50ae037e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478265185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1478265185
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.363621891
Short name T675
Test name
Test status
Simulation time 32372853 ps
CPU time 1.09 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 218060 kb
Host smart-836ec9dd-1b77-4a42-ab9f-7cef253c0e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363621891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.363621891
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.181226678
Short name T550
Test name
Test status
Simulation time 120739960 ps
CPU time 2.67 seconds
Started May 23 02:53:04 PM PDT 24
Finished May 23 02:53:10 PM PDT 24
Peak memory 219528 kb
Host smart-83595909-5757-401d-bac6-69d4925ace0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181226678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.181226678
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2342431670
Short name T73
Test name
Test status
Simulation time 20102298 ps
CPU time 1.21 seconds
Started May 23 02:53:09 PM PDT 24
Finished May 23 02:53:14 PM PDT 24
Peak memory 223476 kb
Host smart-465d4933-88a0-4365-8c93-04681995dc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342431670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2342431670
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3418355691
Short name T541
Test name
Test status
Simulation time 91357535 ps
CPU time 1.32 seconds
Started May 23 02:53:08 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 218592 kb
Host smart-93f58d03-e5bd-4491-84f4-9a43ddd5f9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418355691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3418355691
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3499055698
Short name T76
Test name
Test status
Simulation time 28402733 ps
CPU time 0.89 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 217892 kb
Host smart-3fa39e3e-9699-4888-b025-f9881c6f957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499055698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3499055698
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1519008188
Short name T616
Test name
Test status
Simulation time 89849609 ps
CPU time 1.99 seconds
Started May 23 02:53:09 PM PDT 24
Finished May 23 02:53:15 PM PDT 24
Peak memory 218080 kb
Host smart-5a2372ae-1ff5-4b16-891a-855e917c00f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519008188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1519008188
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.80959925
Short name T488
Test name
Test status
Simulation time 18765804 ps
CPU time 1.06 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 217960 kb
Host smart-38d78b90-23dd-4e86-9872-df2a1c317a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80959925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.80959925
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2678704363
Short name T566
Test name
Test status
Simulation time 69947235 ps
CPU time 1.43 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 219428 kb
Host smart-8bba83ac-8373-479e-98a3-2d15efba73b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678704363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2678704363
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.4290518998
Short name T128
Test name
Test status
Simulation time 73792534 ps
CPU time 1.21 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 224980 kb
Host smart-b1106eae-2cea-4f2f-846c-6ded90c38041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290518998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4290518998
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.798389164
Short name T622
Test name
Test status
Simulation time 89521070 ps
CPU time 1.37 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 218184 kb
Host smart-411138c6-9745-4cc5-bd44-8fd4b76dd250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798389164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.798389164
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.4141442722
Short name T680
Test name
Test status
Simulation time 20042964 ps
CPU time 1.17 seconds
Started May 23 02:53:05 PM PDT 24
Finished May 23 02:53:11 PM PDT 24
Peak memory 223416 kb
Host smart-8db049ab-456e-424d-bd5d-f8363825e256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141442722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4141442722
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2781152311
Short name T356
Test name
Test status
Simulation time 171620723 ps
CPU time 1.48 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 218228 kb
Host smart-76869597-ec09-415b-b5a1-812dde3332a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781152311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2781152311
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2337151526
Short name T75
Test name
Test status
Simulation time 22135640 ps
CPU time 1.12 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 223312 kb
Host smart-9443110f-92ce-4329-810a-006bba134bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337151526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2337151526
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.3927526812
Short name T140
Test name
Test status
Simulation time 386287801 ps
CPU time 4.52 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:15 PM PDT 24
Peak memory 219732 kb
Host smart-44388cae-2baa-4320-ba3c-0a31ffb1bb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927526812 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.3927526812
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3499691329
Short name T719
Test name
Test status
Simulation time 30565752 ps
CPU time 0.99 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 219620 kb
Host smart-b1e576c8-e985-4023-bad6-e5c6dd030b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499691329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3499691329
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4023325878
Short name T422
Test name
Test status
Simulation time 141316769 ps
CPU time 2.47 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:14 PM PDT 24
Peak memory 219180 kb
Host smart-3f252bf3-fb5e-4b47-95f9-fabcd0a86b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023325878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4023325878
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3849702420
Short name T809
Test name
Test status
Simulation time 96215423 ps
CPU time 1.04 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:30 PM PDT 24
Peak memory 215480 kb
Host smart-13fbe9ff-f3a4-43ea-8d23-b20575fb96da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849702420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3849702420
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2638096845
Short name T502
Test name
Test status
Simulation time 29630014 ps
CPU time 0.95 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 214584 kb
Host smart-33335285-a2a5-41ad-ae4b-368561ad5b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638096845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2638096845
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2489975290
Short name T477
Test name
Test status
Simulation time 45818891 ps
CPU time 0.89 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 215696 kb
Host smart-9538bee9-e04d-4f06-9f29-f05d6543935b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489975290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2489975290
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2586644903
Short name T39
Test name
Test status
Simulation time 49406821 ps
CPU time 1.11 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:28 PM PDT 24
Peak memory 216540 kb
Host smart-22008514-8f14-447c-a687-9ed1c33d6b42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586644903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2586644903
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.616624376
Short name T705
Test name
Test status
Simulation time 23922563 ps
CPU time 0.94 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:33 PM PDT 24
Peak memory 218060 kb
Host smart-7def2ac7-0adc-4b21-8a92-41aa36602161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616624376 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.616624376
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.161143956
Short name T570
Test name
Test status
Simulation time 141133978 ps
CPU time 1.44 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 218060 kb
Host smart-479e3c68-a498-4bbd-8f84-82afca467e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161143956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.161143956
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.192661150
Short name T469
Test name
Test status
Simulation time 35074966 ps
CPU time 0.99 seconds
Started May 23 02:50:29 PM PDT 24
Finished May 23 02:50:32 PM PDT 24
Peak memory 223460 kb
Host smart-5a46a3fb-7c54-4177-93ab-89f95a6f23da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192661150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.192661150
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.675762656
Short name T253
Test name
Test status
Simulation time 36217224 ps
CPU time 0.97 seconds
Started May 23 02:50:26 PM PDT 24
Finished May 23 02:50:28 PM PDT 24
Peak memory 206888 kb
Host smart-0d837501-74ec-4016-b065-1b343da816c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675762656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.675762656
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3815741499
Short name T810
Test name
Test status
Simulation time 18788660 ps
CPU time 1.04 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:29 PM PDT 24
Peak memory 214912 kb
Host smart-7815ce6b-3590-43b6-9850-d7b969a7e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815741499 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3815741499
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2876384592
Short name T508
Test name
Test status
Simulation time 3148511320 ps
CPU time 4.61 seconds
Started May 23 02:50:27 PM PDT 24
Finished May 23 02:50:34 PM PDT 24
Peak memory 215092 kb
Host smart-62670573-4747-426c-83ca-692bc717e254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876384592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2876384592
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3735936133
Short name T638
Test name
Test status
Simulation time 11302787594 ps
CPU time 304.87 seconds
Started May 23 02:50:28 PM PDT 24
Finished May 23 02:55:36 PM PDT 24
Peak memory 217592 kb
Host smart-6ca414c7-911c-4b45-88fa-878e77b0ab9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735936133 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3735936133
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.690676561
Short name T67
Test name
Test status
Simulation time 32991615 ps
CPU time 0.91 seconds
Started May 23 02:53:08 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 218168 kb
Host smart-43f6da6d-f03c-4d10-9610-9ff71152e9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690676561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.690676561
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1067797885
Short name T311
Test name
Test status
Simulation time 55002468 ps
CPU time 1.58 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:13 PM PDT 24
Peak memory 217828 kb
Host smart-aa36bfd2-93f2-463e-a964-782fcf325c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067797885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1067797885
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3723790236
Short name T708
Test name
Test status
Simulation time 30946925 ps
CPU time 0.92 seconds
Started May 23 02:53:07 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 218056 kb
Host smart-fb715c2a-626b-491c-b41c-fb96e81964ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723790236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3723790236
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1198966248
Short name T627
Test name
Test status
Simulation time 61473484 ps
CPU time 1.44 seconds
Started May 23 02:53:06 PM PDT 24
Finished May 23 02:53:12 PM PDT 24
Peak memory 219064 kb
Host smart-8d6ad212-c35d-47a3-90ee-fdbb3d4c3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198966248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1198966248
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2007962041
Short name T46
Test name
Test status
Simulation time 47208474 ps
CPU time 1.1 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 231796 kb
Host smart-01b5810e-cb03-480f-87b4-7c5eff5f0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007962041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2007962041
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1631718318
Short name T556
Test name
Test status
Simulation time 68319269 ps
CPU time 2.61 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 219520 kb
Host smart-a0ce000c-dfb3-47b8-b53d-0983b8a1dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631718318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1631718318
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.333165114
Short name T589
Test name
Test status
Simulation time 18111820 ps
CPU time 1.16 seconds
Started May 23 02:53:17 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 223472 kb
Host smart-6f32c3b5-5628-43bf-a5ff-c740680ab470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333165114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.333165114
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1733919126
Short name T270
Test name
Test status
Simulation time 38527379 ps
CPU time 1.43 seconds
Started May 23 02:53:19 PM PDT 24
Finished May 23 02:53:23 PM PDT 24
Peak memory 218108 kb
Host smart-b5df5158-70a1-4a19-83b8-f8c598271cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733919126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1733919126
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4059636563
Short name T687
Test name
Test status
Simulation time 19858330 ps
CPU time 1.05 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 218200 kb
Host smart-ab4a8600-543f-4604-9d11-be00ec289d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059636563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4059636563
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4215096088
Short name T639
Test name
Test status
Simulation time 36769383 ps
CPU time 1.36 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 217972 kb
Host smart-bc6bd0a5-3026-46fb-a856-42fa4b9a7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215096088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4215096088
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.494741991
Short name T33
Test name
Test status
Simulation time 49506337 ps
CPU time 1.15 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 229044 kb
Host smart-0709cd12-1e46-4cca-9bdf-51bccd8d95ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494741991 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.494741991
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3987347885
Short name T684
Test name
Test status
Simulation time 35813616 ps
CPU time 1.45 seconds
Started May 23 02:53:19 PM PDT 24
Finished May 23 02:53:23 PM PDT 24
Peak memory 217964 kb
Host smart-f0428644-dccd-496a-92fa-a2b984adc380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987347885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3987347885
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3782667771
Short name T161
Test name
Test status
Simulation time 28498685 ps
CPU time 0.93 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 218380 kb
Host smart-61fd5898-deef-4fbd-b911-88c3fcd0adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782667771 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3782667771
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3750297695
Short name T329
Test name
Test status
Simulation time 100151367 ps
CPU time 2.48 seconds
Started May 23 02:53:19 PM PDT 24
Finished May 23 02:53:24 PM PDT 24
Peak memory 219756 kb
Host smart-938aeee0-24c1-4772-83c6-42cec19c1e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750297695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3750297695
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3856899651
Short name T170
Test name
Test status
Simulation time 25158856 ps
CPU time 1.15 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:24 PM PDT 24
Peak memory 220232 kb
Host smart-fbc67b9c-3864-480b-812f-ef13eaf559cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856899651 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3856899651
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1893675408
Short name T656
Test name
Test status
Simulation time 104000088 ps
CPU time 2.36 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 216816 kb
Host smart-65c50b10-cf43-4b1c-b209-bc558dabc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893675408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1893675408
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.864783548
Short name T92
Test name
Test status
Simulation time 18251330 ps
CPU time 1.14 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 223476 kb
Host smart-29a9c27c-5245-468b-b362-c66130569245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864783548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.864783548
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.376299188
Short name T729
Test name
Test status
Simulation time 90275177 ps
CPU time 1.2 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 216716 kb
Host smart-1cd0fad3-c11f-4494-8e77-42c4be12d384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376299188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.376299188
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1493739415
Short name T628
Test name
Test status
Simulation time 18070293 ps
CPU time 1.07 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 217756 kb
Host smart-a42bc8ae-e9ba-4d07-b61b-f7904e77ae3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493739415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1493739415
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3238907241
Short name T561
Test name
Test status
Simulation time 273806751 ps
CPU time 1.09 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 216860 kb
Host smart-483fcdf1-c15d-4839-9707-c207ffb6809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238907241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3238907241
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1184448531
Short name T71
Test name
Test status
Simulation time 439941925 ps
CPU time 1.33 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 215396 kb
Host smart-755625fd-bdc0-4d2f-ac3a-8d0a4ca12c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184448531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1184448531
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.685366172
Short name T760
Test name
Test status
Simulation time 20716701 ps
CPU time 0.83 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 206616 kb
Host smart-78660fbf-44e0-4ff3-9b59-d14bf89ff3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685366172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.685366172
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1031629617
Short name T565
Test name
Test status
Simulation time 36358690 ps
CPU time 0.82 seconds
Started May 23 02:50:48 PM PDT 24
Finished May 23 02:50:50 PM PDT 24
Peak memory 216220 kb
Host smart-d82488a4-a060-4c46-813f-0a574a0e5197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031629617 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1031629617
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1658839378
Short name T563
Test name
Test status
Simulation time 46242424 ps
CPU time 1.17 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 216564 kb
Host smart-a70d286b-a267-4a73-8253-463263d0d589
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658839378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1658839378
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1171697653
Short name T380
Test name
Test status
Simulation time 38842781 ps
CPU time 0.9 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 217884 kb
Host smart-6c77d8be-5e7e-4f65-b8c7-544c20c64001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171697653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1171697653
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.938237285
Short name T814
Test name
Test status
Simulation time 104750345 ps
CPU time 2.77 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 219668 kb
Host smart-91ec3b45-cb2f-4938-b992-8422db142eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938237285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.938237285
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3938467726
Short name T157
Test name
Test status
Simulation time 20212277 ps
CPU time 1.09 seconds
Started May 23 02:50:53 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 215552 kb
Host smart-ad3f18ff-42d1-4b69-9f0a-5bf91ec10885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938467726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3938467726
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.2446349352
Short name T21
Test name
Test status
Simulation time 35681562 ps
CPU time 0.96 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 214892 kb
Host smart-f5045580-e058-435f-aeca-435438d0a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446349352 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2446349352
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2396274580
Short name T668
Test name
Test status
Simulation time 197730379 ps
CPU time 4.42 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216896 kb
Host smart-6fc183a2-37ce-471d-9e26-5a5d5a0445be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396274580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2396274580
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3407623283
Short name T185
Test name
Test status
Simulation time 26188911153 ps
CPU time 647.05 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 03:01:39 PM PDT 24
Peak memory 217396 kb
Host smart-9e74efcd-a98b-4e0a-845f-a3199c545b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407623283 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3407623283
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.4202002618
Short name T9
Test name
Test status
Simulation time 24019305 ps
CPU time 1.05 seconds
Started May 23 02:53:16 PM PDT 24
Finished May 23 02:53:19 PM PDT 24
Peak memory 218148 kb
Host smart-2feafd0e-1136-44ed-aadd-143f3831ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202002618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.4202002618
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1742868766
Short name T575
Test name
Test status
Simulation time 30919841 ps
CPU time 1.33 seconds
Started May 23 02:53:17 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 217992 kb
Host smart-aa9f594a-1277-4e55-9286-e6e2133d4ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742868766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1742868766
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2219992229
Short name T569
Test name
Test status
Simulation time 23790874 ps
CPU time 1.34 seconds
Started May 23 02:53:21 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 223440 kb
Host smart-bec57da5-7ae8-43ed-a0da-a0672c1d1a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219992229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2219992229
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2177857334
Short name T237
Test name
Test status
Simulation time 45484013 ps
CPU time 1.43 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 216996 kb
Host smart-4623d574-75d5-4829-9399-0a7cc624662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177857334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2177857334
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.756202870
Short name T619
Test name
Test status
Simulation time 26400017 ps
CPU time 1.18 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 217680 kb
Host smart-e2a95e32-ee21-42d3-af23-0db7c66e1763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756202870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.756202870
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3001125749
Short name T478
Test name
Test status
Simulation time 50485343 ps
CPU time 1.4 seconds
Started May 23 02:53:17 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 219764 kb
Host smart-cac73f3f-62ab-4fd4-9082-9e05de9be80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001125749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3001125749
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4013107097
Short name T471
Test name
Test status
Simulation time 24445598 ps
CPU time 1.23 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 218096 kb
Host smart-d028e8d0-69ae-4f64-9c86-764ab89ab126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013107097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4013107097
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3923157189
Short name T476
Test name
Test status
Simulation time 75725187 ps
CPU time 1.5 seconds
Started May 23 02:53:21 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 216720 kb
Host smart-e8405847-acbb-48e7-8d71-98ad1d7d35aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923157189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3923157189
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2618477564
Short name T353
Test name
Test status
Simulation time 70165667 ps
CPU time 1.11 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:24 PM PDT 24
Peak memory 219352 kb
Host smart-6387962d-d246-4185-af42-f6b3b7626dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618477564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2618477564
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1272663280
Short name T734
Test name
Test status
Simulation time 65414895 ps
CPU time 1.13 seconds
Started May 23 02:53:19 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 216816 kb
Host smart-4734e9dc-0c77-48c6-ab42-9e2985472d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272663280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1272663280
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.348737069
Short name T372
Test name
Test status
Simulation time 21562429 ps
CPU time 1.01 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:24 PM PDT 24
Peak memory 223328 kb
Host smart-a08437ca-f59b-4795-b2be-92f48739344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348737069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.348737069
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2758532999
Short name T435
Test name
Test status
Simulation time 21256748 ps
CPU time 1 seconds
Started May 23 02:53:19 PM PDT 24
Finished May 23 02:53:23 PM PDT 24
Peak memory 216824 kb
Host smart-d53a6d98-4947-477c-95b0-0972ac8a2f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758532999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2758532999
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2893546692
Short name T166
Test name
Test status
Simulation time 24049383 ps
CPU time 1.05 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 218304 kb
Host smart-d069fc84-5448-4bea-afd6-66473bb318ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893546692 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2893546692
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.233248323
Short name T802
Test name
Test status
Simulation time 67183429 ps
CPU time 1.03 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:20 PM PDT 24
Peak memory 216656 kb
Host smart-099d9bc1-694b-4e9f-b95e-7c614702bfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233248323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.233248323
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3245795171
Short name T441
Test name
Test status
Simulation time 161206306 ps
CPU time 1.12 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:24 PM PDT 24
Peak memory 219276 kb
Host smart-fabcaa1c-d68a-4700-b384-7fdac82fb0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245795171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3245795171
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1649409160
Short name T592
Test name
Test status
Simulation time 61159370 ps
CPU time 1.35 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:22 PM PDT 24
Peak memory 218140 kb
Host smart-1e80aa44-fb6a-462b-a98e-3942ef802e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649409160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1649409160
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_genbits.564880168
Short name T295
Test name
Test status
Simulation time 40766795 ps
CPU time 1.59 seconds
Started May 23 02:53:21 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 219420 kb
Host smart-038e98f2-c112-476c-8bf1-c20c678362fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564880168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.564880168
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2593835501
Short name T836
Test name
Test status
Simulation time 77960642 ps
CPU time 0.8 seconds
Started May 23 02:53:18 PM PDT 24
Finished May 23 02:53:21 PM PDT 24
Peak memory 217996 kb
Host smart-3fbe5959-5511-4ab9-b884-2196cce930c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593835501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2593835501
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3461809791
Short name T553
Test name
Test status
Simulation time 56118016 ps
CPU time 1.71 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 217748 kb
Host smart-8bc064fb-eebb-42c6-81a9-4c12c38f7d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461809791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3461809791
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.656165975
Short name T514
Test name
Test status
Simulation time 49768092 ps
CPU time 1.23 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:51 PM PDT 24
Peak memory 215432 kb
Host smart-d1e6933e-53bd-4788-b705-9e7c1a6e24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656165975 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.656165975
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.390479220
Short name T787
Test name
Test status
Simulation time 18310809 ps
CPU time 1.07 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 206320 kb
Host smart-14a75074-1780-4e23-a6f6-ad195ecb6562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390479220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.390479220
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.946397664
Short name T557
Test name
Test status
Simulation time 11736266 ps
CPU time 1.07 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:57 PM PDT 24
Peak memory 216336 kb
Host smart-fb703634-746f-4d40-9140-9cc533b11d0c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946397664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.946397664
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3626872348
Short name T695
Test name
Test status
Simulation time 122563338 ps
CPU time 1.19 seconds
Started May 23 02:50:52 PM PDT 24
Finished May 23 02:50:58 PM PDT 24
Peak memory 218020 kb
Host smart-6f28e427-3259-40ef-8558-e12eeba9d4c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626872348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3626872348
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.351962010
Short name T560
Test name
Test status
Simulation time 22729145 ps
CPU time 1.11 seconds
Started May 23 02:50:47 PM PDT 24
Finished May 23 02:50:49 PM PDT 24
Peak memory 218296 kb
Host smart-2f3809ce-b19f-46c4-9e9d-19f91733395b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351962010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.351962010
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3254794990
Short name T731
Test name
Test status
Simulation time 109241612 ps
CPU time 1.4 seconds
Started May 23 02:50:54 PM PDT 24
Finished May 23 02:50:59 PM PDT 24
Peak memory 216700 kb
Host smart-d6b01b78-c1c1-46d6-94ac-290a30a87f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254794990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3254794990
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2920902399
Short name T533
Test name
Test status
Simulation time 22203917 ps
CPU time 1.13 seconds
Started May 23 02:50:51 PM PDT 24
Finished May 23 02:50:56 PM PDT 24
Peak memory 215372 kb
Host smart-1384a6af-9a37-40e2-b4b3-9f9607e8531c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920902399 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2920902399
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.671146497
Short name T250
Test name
Test status
Simulation time 42031228 ps
CPU time 0.87 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 02:50:53 PM PDT 24
Peak memory 206804 kb
Host smart-f39c3040-2acb-4d6e-acbd-90b56476a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671146497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.671146497
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3627940019
Short name T415
Test name
Test status
Simulation time 22597306 ps
CPU time 0.91 seconds
Started May 23 02:50:50 PM PDT 24
Finished May 23 02:50:55 PM PDT 24
Peak memory 215012 kb
Host smart-14ecc765-0e80-4f50-b0c4-9384c91c1324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627940019 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3627940019
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2372185022
Short name T721
Test name
Test status
Simulation time 337306299 ps
CPU time 6.85 seconds
Started May 23 02:50:53 PM PDT 24
Finished May 23 02:51:04 PM PDT 24
Peak memory 216876 kb
Host smart-2c7505cc-be0f-4b45-a45e-26d5498fe9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372185022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2372185022
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1703817366
Short name T785
Test name
Test status
Simulation time 53018877286 ps
CPU time 1237.89 seconds
Started May 23 02:50:49 PM PDT 24
Finished May 23 03:11:30 PM PDT 24
Peak memory 220932 kb
Host smart-abe26e41-fc5e-45b6-8987-c7f4279b538f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703817366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1703817366
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_genbits.2922487325
Short name T123
Test name
Test status
Simulation time 39168323 ps
CPU time 1.47 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 218092 kb
Host smart-a4b71ae7-e34c-45bd-b170-45b6e33a3506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922487325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2922487325
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2161229885
Short name T495
Test name
Test status
Simulation time 20475484 ps
CPU time 0.96 seconds
Started May 23 02:53:20 PM PDT 24
Finished May 23 02:53:23 PM PDT 24
Peak memory 218204 kb
Host smart-b585b165-9c3a-45f5-b457-d67e0372ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161229885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2161229885
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.575860208
Short name T138
Test name
Test status
Simulation time 113369990 ps
CPU time 2.33 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 219432 kb
Host smart-9f46eaf3-a5bd-4792-99c1-9dbce59c5fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575860208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.575860208
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3263824038
Short name T40
Test name
Test status
Simulation time 44504265 ps
CPU time 0.97 seconds
Started May 23 02:53:25 PM PDT 24
Finished May 23 02:53:28 PM PDT 24
Peak memory 219084 kb
Host smart-bf5c7f94-6325-464e-a92f-229a084dff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263824038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3263824038
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3829109860
Short name T540
Test name
Test status
Simulation time 29754265 ps
CPU time 1.23 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 216904 kb
Host smart-e7a91053-93ca-4b1c-a9ab-bae21523edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829109860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3829109860
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2144135713
Short name T48
Test name
Test status
Simulation time 46350223 ps
CPU time 1.03 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 229348 kb
Host smart-c01c6530-a000-4524-ba7e-f17ee024f35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144135713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2144135713
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.236415952
Short name T205
Test name
Test status
Simulation time 51896595 ps
CPU time 1.65 seconds
Started May 23 02:53:21 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 218268 kb
Host smart-9f57ae9b-89c1-4ed5-b67d-43ee9fe36bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236415952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.236415952
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3631159639
Short name T81
Test name
Test status
Simulation time 75103758 ps
CPU time 0.86 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:25 PM PDT 24
Peak memory 217796 kb
Host smart-e348d75c-570f-4e7a-b95c-fd9ff2f580d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631159639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3631159639
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3348657419
Short name T433
Test name
Test status
Simulation time 51781632 ps
CPU time 1.72 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 218036 kb
Host smart-8ebecc23-de8b-49f6-9fdd-ac54e0887931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348657419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3348657419
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2178794537
Short name T80
Test name
Test status
Simulation time 31717257 ps
CPU time 0.89 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 217800 kb
Host smart-85a9f7a2-5413-4453-8a90-14f92ba3bd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178794537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2178794537
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2085913566
Short name T121
Test name
Test status
Simulation time 36049295 ps
CPU time 1.58 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:28 PM PDT 24
Peak memory 217792 kb
Host smart-87ad6f42-9881-4fb5-b95b-e87ee2e7f9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085913566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2085913566
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.504843181
Short name T89
Test name
Test status
Simulation time 21156815 ps
CPU time 1.15 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 223480 kb
Host smart-154d0eba-3131-460d-a3d9-6f37c00c460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504843181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.504843181
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1130664405
Short name T238
Test name
Test status
Simulation time 55881939 ps
CPU time 0.99 seconds
Started May 23 02:53:24 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 216584 kb
Host smart-85fabe02-0681-4c9d-9136-15b4faf585c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130664405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1130664405
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2191381002
Short name T50
Test name
Test status
Simulation time 37299021 ps
CPU time 0.92 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 219156 kb
Host smart-e04b0c3e-c742-445a-9ee9-2d5f3083b642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191381002 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2191381002
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3510170243
Short name T410
Test name
Test status
Simulation time 85545662 ps
CPU time 1.15 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:27 PM PDT 24
Peak memory 218120 kb
Host smart-483c3518-550f-4a3b-b494-ff716bb83757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510170243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3510170243
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3910864881
Short name T467
Test name
Test status
Simulation time 45670015 ps
CPU time 0.95 seconds
Started May 23 02:53:22 PM PDT 24
Finished May 23 02:53:26 PM PDT 24
Peak memory 223296 kb
Host smart-28b05b0e-da5a-4998-84e6-b617ab92c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910864881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3910864881
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.732066111
Short name T652
Test name
Test status
Simulation time 49041111 ps
CPU time 1.61 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:28 PM PDT 24
Peak memory 217904 kb
Host smart-243780f6-fb2b-4475-8cb7-7560d93abf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732066111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.732066111
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1241044825
Short name T49
Test name
Test status
Simulation time 20953580 ps
CPU time 1.12 seconds
Started May 23 02:53:26 PM PDT 24
Finished May 23 02:53:29 PM PDT 24
Peak memory 219252 kb
Host smart-adde922e-df28-4c63-942c-f795a92f9bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241044825 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1241044825
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2645573107
Short name T756
Test name
Test status
Simulation time 64086577 ps
CPU time 1.54 seconds
Started May 23 02:53:23 PM PDT 24
Finished May 23 02:53:28 PM PDT 24
Peak memory 218156 kb
Host smart-f9fe140a-e9d6-437d-8667-8c38af45b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645573107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2645573107
Directory /workspace/99.edn_genbits/latest
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