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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.57 98.24 93.74 97.02 85.47 96.62 99.77 91.12


Total test records in report: 980
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T791 /workspace/coverage/default/41.edn_smoke.1872751038 May 26 01:15:41 PM PDT 24 May 26 01:15:43 PM PDT 24 17425499 ps
T792 /workspace/coverage/default/287.edn_genbits.3632568927 May 26 01:16:37 PM PDT 24 May 26 01:16:40 PM PDT 24 153416224 ps
T793 /workspace/coverage/default/81.edn_err.901317460 May 26 01:16:03 PM PDT 24 May 26 01:16:06 PM PDT 24 19347226 ps
T794 /workspace/coverage/default/83.edn_genbits.2811280663 May 26 01:16:07 PM PDT 24 May 26 01:16:11 PM PDT 24 139625694 ps
T795 /workspace/coverage/default/36.edn_alert_test.2657750914 May 26 01:15:30 PM PDT 24 May 26 01:15:33 PM PDT 24 21020767 ps
T796 /workspace/coverage/default/69.edn_err.1970028613 May 26 01:16:04 PM PDT 24 May 26 01:16:07 PM PDT 24 21617479 ps
T797 /workspace/coverage/default/291.edn_genbits.1372047807 May 26 01:16:41 PM PDT 24 May 26 01:16:45 PM PDT 24 64641763 ps
T798 /workspace/coverage/default/1.edn_smoke.1599574987 May 26 01:14:22 PM PDT 24 May 26 01:14:25 PM PDT 24 18024889 ps
T799 /workspace/coverage/default/21.edn_disable_auto_req_mode.3504385556 May 26 01:15:14 PM PDT 24 May 26 01:15:17 PM PDT 24 43948609 ps
T800 /workspace/coverage/default/220.edn_genbits.2665496884 May 26 01:16:26 PM PDT 24 May 26 01:16:30 PM PDT 24 56262603 ps
T801 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1867938698 May 26 01:15:30 PM PDT 24 May 26 01:28:15 PM PDT 24 65643303414 ps
T802 /workspace/coverage/default/12.edn_alert_test.1150604678 May 26 01:14:53 PM PDT 24 May 26 01:14:55 PM PDT 24 33346310 ps
T803 /workspace/coverage/default/28.edn_alert.1844457216 May 26 01:15:24 PM PDT 24 May 26 01:15:27 PM PDT 24 88118195 ps
T804 /workspace/coverage/default/31.edn_smoke.747651750 May 26 01:15:31 PM PDT 24 May 26 01:15:34 PM PDT 24 46027971 ps
T805 /workspace/coverage/default/0.edn_err.1339389842 May 26 01:14:21 PM PDT 24 May 26 01:14:24 PM PDT 24 21018205 ps
T806 /workspace/coverage/default/79.edn_genbits.3389986466 May 26 01:16:06 PM PDT 24 May 26 01:16:09 PM PDT 24 57174408 ps
T807 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4035076688 May 26 01:14:21 PM PDT 24 May 26 01:23:34 PM PDT 24 24399788027 ps
T808 /workspace/coverage/default/32.edn_disable_auto_req_mode.2210563120 May 26 01:15:28 PM PDT 24 May 26 01:15:30 PM PDT 24 85832322 ps
T809 /workspace/coverage/default/265.edn_genbits.2056143668 May 26 01:16:38 PM PDT 24 May 26 01:16:41 PM PDT 24 66478056 ps
T810 /workspace/coverage/default/16.edn_alert_test.959137613 May 26 01:15:02 PM PDT 24 May 26 01:15:05 PM PDT 24 21219394 ps
T811 /workspace/coverage/default/30.edn_genbits.4203491642 May 26 01:15:30 PM PDT 24 May 26 01:15:33 PM PDT 24 101496753 ps
T812 /workspace/coverage/default/9.edn_alert_test.2314620219 May 26 01:14:42 PM PDT 24 May 26 01:14:44 PM PDT 24 36863691 ps
T813 /workspace/coverage/default/74.edn_genbits.3455733317 May 26 01:16:05 PM PDT 24 May 26 01:16:07 PM PDT 24 55959646 ps
T814 /workspace/coverage/default/23.edn_alert_test.2809057778 May 26 01:15:13 PM PDT 24 May 26 01:15:16 PM PDT 24 45648943 ps
T815 /workspace/coverage/default/3.edn_smoke.3239783489 May 26 01:14:32 PM PDT 24 May 26 01:14:34 PM PDT 24 17653260 ps
T816 /workspace/coverage/default/0.edn_intr.2227263279 May 26 01:14:20 PM PDT 24 May 26 01:14:23 PM PDT 24 33091798 ps
T817 /workspace/coverage/default/216.edn_genbits.528178128 May 26 01:16:24 PM PDT 24 May 26 01:16:28 PM PDT 24 56951279 ps
T818 /workspace/coverage/default/19.edn_smoke.2448044023 May 26 01:15:03 PM PDT 24 May 26 01:15:05 PM PDT 24 15293723 ps
T132 /workspace/coverage/default/84.edn_err.2127156440 May 26 01:16:10 PM PDT 24 May 26 01:16:12 PM PDT 24 19612380 ps
T819 /workspace/coverage/default/207.edn_genbits.2828206090 May 26 01:16:47 PM PDT 24 May 26 01:16:50 PM PDT 24 46051656 ps
T820 /workspace/coverage/default/4.edn_genbits.1830771049 May 26 01:14:31 PM PDT 24 May 26 01:14:33 PM PDT 24 35323182 ps
T821 /workspace/coverage/default/223.edn_genbits.2230987214 May 26 01:16:26 PM PDT 24 May 26 01:16:31 PM PDT 24 111901354 ps
T822 /workspace/coverage/default/274.edn_genbits.3532685647 May 26 01:16:44 PM PDT 24 May 26 01:16:47 PM PDT 24 92124728 ps
T268 /workspace/coverage/default/0.edn_regwen.3614127547 May 26 01:14:19 PM PDT 24 May 26 01:14:21 PM PDT 24 27573315 ps
T823 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4145615501 May 26 01:14:51 PM PDT 24 May 26 01:33:30 PM PDT 24 69264420513 ps
T824 /workspace/coverage/default/151.edn_genbits.479772308 May 26 01:16:18 PM PDT 24 May 26 01:16:21 PM PDT 24 60639522 ps
T825 /workspace/coverage/default/10.edn_disable.2086112778 May 26 01:14:50 PM PDT 24 May 26 01:14:52 PM PDT 24 24571049 ps
T826 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3133306908 May 26 01:14:44 PM PDT 24 May 26 01:36:07 PM PDT 24 223116236948 ps
T827 /workspace/coverage/default/8.edn_alert.2172077340 May 26 01:14:44 PM PDT 24 May 26 01:14:47 PM PDT 24 29096734 ps
T116 /workspace/coverage/default/46.edn_disable_auto_req_mode.1223113268 May 26 01:15:47 PM PDT 24 May 26 01:15:50 PM PDT 24 59475381 ps
T828 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3929833219 May 26 01:15:42 PM PDT 24 May 26 01:23:00 PM PDT 24 19217575977 ps
T829 /workspace/coverage/default/49.edn_stress_all.1489830089 May 26 01:15:55 PM PDT 24 May 26 01:15:59 PM PDT 24 205409578 ps
T830 /workspace/coverage/default/35.edn_disable.4181377514 May 26 01:15:38 PM PDT 24 May 26 01:15:41 PM PDT 24 14956764 ps
T831 /workspace/coverage/default/85.edn_genbits.873290044 May 26 01:16:06 PM PDT 24 May 26 01:16:09 PM PDT 24 28026582 ps
T832 /workspace/coverage/default/46.edn_intr.130119837 May 26 01:15:53 PM PDT 24 May 26 01:15:55 PM PDT 24 27543134 ps
T833 /workspace/coverage/default/40.edn_alert.2887971236 May 26 01:15:44 PM PDT 24 May 26 01:15:46 PM PDT 24 25028827 ps
T122 /workspace/coverage/default/98.edn_err.2602274113 May 26 01:16:21 PM PDT 24 May 26 01:16:24 PM PDT 24 20640132 ps
T834 /workspace/coverage/default/1.edn_err.2689860989 May 26 01:14:20 PM PDT 24 May 26 01:14:24 PM PDT 24 47036829 ps
T835 /workspace/coverage/default/140.edn_genbits.552938003 May 26 01:16:16 PM PDT 24 May 26 01:16:20 PM PDT 24 64069974 ps
T836 /workspace/coverage/default/47.edn_err.1320543238 May 26 01:15:52 PM PDT 24 May 26 01:15:54 PM PDT 24 43643770 ps
T837 /workspace/coverage/default/38.edn_smoke.2151406164 May 26 01:15:39 PM PDT 24 May 26 01:15:42 PM PDT 24 23510472 ps
T838 /workspace/coverage/default/232.edn_genbits.1813938240 May 26 01:16:46 PM PDT 24 May 26 01:16:49 PM PDT 24 62068630 ps
T95 /workspace/coverage/default/62.edn_err.2607171669 May 26 01:16:04 PM PDT 24 May 26 01:16:06 PM PDT 24 25183591 ps
T839 /workspace/coverage/default/229.edn_genbits.1360417777 May 26 01:16:30 PM PDT 24 May 26 01:16:35 PM PDT 24 43133573 ps
T840 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.712040766 May 26 01:15:13 PM PDT 24 May 26 01:39:04 PM PDT 24 83878065579 ps
T104 /workspace/coverage/default/66.edn_err.875283025 May 26 01:16:07 PM PDT 24 May 26 01:16:10 PM PDT 24 60059477 ps
T841 /workspace/coverage/default/30.edn_err.100408999 May 26 01:15:29 PM PDT 24 May 26 01:15:32 PM PDT 24 50201880 ps
T842 /workspace/coverage/default/24.edn_err.1606428280 May 26 01:15:15 PM PDT 24 May 26 01:15:18 PM PDT 24 22894623 ps
T843 /workspace/coverage/default/0.edn_smoke.3209604436 May 26 01:14:20 PM PDT 24 May 26 01:14:23 PM PDT 24 16884842 ps
T844 /workspace/coverage/default/25.edn_intr.3702532897 May 26 01:15:12 PM PDT 24 May 26 01:15:14 PM PDT 24 24963620 ps
T845 /workspace/coverage/default/203.edn_genbits.424683745 May 26 01:16:26 PM PDT 24 May 26 01:16:34 PM PDT 24 355200051 ps
T288 /workspace/coverage/default/31.edn_genbits.1438410738 May 26 01:15:29 PM PDT 24 May 26 01:15:33 PM PDT 24 121583701 ps
T133 /workspace/coverage/default/88.edn_err.1661118393 May 26 01:16:07 PM PDT 24 May 26 01:16:10 PM PDT 24 23168175 ps
T846 /workspace/coverage/default/34.edn_smoke.1055792464 May 26 01:15:27 PM PDT 24 May 26 01:15:29 PM PDT 24 28914597 ps
T847 /workspace/coverage/default/10.edn_intr.1493641717 May 26 01:14:50 PM PDT 24 May 26 01:14:52 PM PDT 24 20441242 ps
T848 /workspace/coverage/cover_reg_top/20.edn_intr_test.3903368162 May 26 02:26:16 PM PDT 24 May 26 02:26:19 PM PDT 24 30000509 ps
T849 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3506060797 May 26 02:26:17 PM PDT 24 May 26 02:26:22 PM PDT 24 198111501 ps
T240 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1756988210 May 26 02:25:56 PM PDT 24 May 26 02:25:58 PM PDT 24 39436802 ps
T850 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4067510143 May 26 02:26:20 PM PDT 24 May 26 02:26:22 PM PDT 24 58052142 ps
T851 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.799814261 May 26 02:26:17 PM PDT 24 May 26 02:26:20 PM PDT 24 23040982 ps
T852 /workspace/coverage/cover_reg_top/38.edn_intr_test.1102913275 May 26 02:26:26 PM PDT 24 May 26 02:26:28 PM PDT 24 25681144 ps
T853 /workspace/coverage/cover_reg_top/29.edn_intr_test.2869154684 May 26 02:26:24 PM PDT 24 May 26 02:26:26 PM PDT 24 17035443 ps
T854 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3235199198 May 26 02:26:17 PM PDT 24 May 26 02:26:20 PM PDT 24 20351296 ps
T230 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2047487946 May 26 02:26:07 PM PDT 24 May 26 02:26:08 PM PDT 24 41122405 ps
T855 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.367940897 May 26 02:26:15 PM PDT 24 May 26 02:26:18 PM PDT 24 22661277 ps
T856 /workspace/coverage/cover_reg_top/21.edn_intr_test.401075637 May 26 02:26:18 PM PDT 24 May 26 02:26:20 PM PDT 24 43848350 ps
T857 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2250290263 May 26 02:26:12 PM PDT 24 May 26 02:26:16 PM PDT 24 140906882 ps
T242 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4208538320 May 26 02:26:15 PM PDT 24 May 26 02:26:18 PM PDT 24 127988995 ps
T243 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1187515165 May 26 02:26:21 PM PDT 24 May 26 02:26:23 PM PDT 24 137336296 ps
T858 /workspace/coverage/cover_reg_top/27.edn_intr_test.1553005789 May 26 02:26:16 PM PDT 24 May 26 02:26:19 PM PDT 24 21190142 ps
T859 /workspace/coverage/cover_reg_top/16.edn_tl_errors.21955461 May 26 02:26:13 PM PDT 24 May 26 02:26:17 PM PDT 24 46407264 ps
T860 /workspace/coverage/cover_reg_top/0.edn_tl_errors.4119842333 May 26 02:26:00 PM PDT 24 May 26 02:26:03 PM PDT 24 81999853 ps
T861 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.114636749 May 26 02:26:15 PM PDT 24 May 26 02:26:17 PM PDT 24 29899830 ps
T862 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3578184894 May 26 02:26:09 PM PDT 24 May 26 02:26:12 PM PDT 24 81734736 ps
T863 /workspace/coverage/cover_reg_top/25.edn_intr_test.1299527322 May 26 02:26:18 PM PDT 24 May 26 02:26:20 PM PDT 24 11838527 ps
T244 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3336207705 May 26 02:26:10 PM PDT 24 May 26 02:26:14 PM PDT 24 219982449 ps
T248 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3099650554 May 26 02:26:04 PM PDT 24 May 26 02:26:06 PM PDT 24 151153753 ps
T241 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2723337588 May 26 02:26:12 PM PDT 24 May 26 02:26:15 PM PDT 24 13983382 ps
T231 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1205687643 May 26 02:26:17 PM PDT 24 May 26 02:26:20 PM PDT 24 19876874 ps
T864 /workspace/coverage/cover_reg_top/11.edn_intr_test.2973969401 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 12174048 ps
T865 /workspace/coverage/cover_reg_top/35.edn_intr_test.1675662991 May 26 02:26:26 PM PDT 24 May 26 02:26:27 PM PDT 24 21599349 ps
T252 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2198064872 May 26 02:26:03 PM PDT 24 May 26 02:26:05 PM PDT 24 69151054 ps
T866 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1390562211 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 206940995 ps
T867 /workspace/coverage/cover_reg_top/48.edn_intr_test.3035692284 May 26 02:26:27 PM PDT 24 May 26 02:26:28 PM PDT 24 21283333 ps
T868 /workspace/coverage/cover_reg_top/34.edn_intr_test.3312657769 May 26 02:26:26 PM PDT 24 May 26 02:26:27 PM PDT 24 12861808 ps
T217 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1300676846 May 26 02:25:54 PM PDT 24 May 26 02:25:55 PM PDT 24 237012236 ps
T869 /workspace/coverage/cover_reg_top/28.edn_intr_test.3035072005 May 26 02:26:18 PM PDT 24 May 26 02:26:20 PM PDT 24 16806459 ps
T870 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2308818025 May 26 02:26:02 PM PDT 24 May 26 02:26:05 PM PDT 24 41639974 ps
T871 /workspace/coverage/cover_reg_top/4.edn_tl_errors.383067206 May 26 02:26:05 PM PDT 24 May 26 02:26:07 PM PDT 24 94941899 ps
T232 /workspace/coverage/cover_reg_top/12.edn_csr_rw.269742517 May 26 02:26:09 PM PDT 24 May 26 02:26:10 PM PDT 24 32330064 ps
T872 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1194051954 May 26 02:26:09 PM PDT 24 May 26 02:26:14 PM PDT 24 79005590 ps
T233 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3171082473 May 26 02:26:16 PM PDT 24 May 26 02:26:20 PM PDT 24 64670880 ps
T234 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2900452258 May 26 02:26:19 PM PDT 24 May 26 02:26:21 PM PDT 24 18307865 ps
T873 /workspace/coverage/cover_reg_top/4.edn_intr_test.3096774024 May 26 02:26:02 PM PDT 24 May 26 02:26:04 PM PDT 24 16596389 ps
T874 /workspace/coverage/cover_reg_top/6.edn_intr_test.2343070139 May 26 02:26:02 PM PDT 24 May 26 02:26:04 PM PDT 24 44937667 ps
T875 /workspace/coverage/cover_reg_top/3.edn_csr_rw.541676635 May 26 02:25:58 PM PDT 24 May 26 02:25:59 PM PDT 24 16069160 ps
T218 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.533339614 May 26 02:26:15 PM PDT 24 May 26 02:26:17 PM PDT 24 30600869 ps
T876 /workspace/coverage/cover_reg_top/2.edn_tl_errors.451086255 May 26 02:25:56 PM PDT 24 May 26 02:26:00 PM PDT 24 271629031 ps
T877 /workspace/coverage/cover_reg_top/8.edn_intr_test.1921993090 May 26 02:26:14 PM PDT 24 May 26 02:26:17 PM PDT 24 16465456 ps
T878 /workspace/coverage/cover_reg_top/14.edn_intr_test.3700070343 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 40358727 ps
T879 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2258735080 May 26 02:26:16 PM PDT 24 May 26 02:26:19 PM PDT 24 128532940 ps
T880 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2973298757 May 26 02:26:12 PM PDT 24 May 26 02:26:17 PM PDT 24 196133295 ps
T881 /workspace/coverage/cover_reg_top/43.edn_intr_test.1635413325 May 26 02:26:25 PM PDT 24 May 26 02:26:27 PM PDT 24 39614113 ps
T882 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2580737356 May 26 02:25:54 PM PDT 24 May 26 02:25:56 PM PDT 24 30782296 ps
T883 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1618821689 May 26 02:26:02 PM PDT 24 May 26 02:26:05 PM PDT 24 19141013 ps
T884 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4020128301 May 26 02:26:11 PM PDT 24 May 26 02:26:14 PM PDT 24 114458957 ps
T253 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3851367468 May 26 02:26:15 PM PDT 24 May 26 02:26:18 PM PDT 24 226383988 ps
T885 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1792406266 May 26 02:25:56 PM PDT 24 May 26 02:25:58 PM PDT 24 53432209 ps
T219 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1973709554 May 26 02:26:03 PM PDT 24 May 26 02:26:05 PM PDT 24 42843285 ps
T249 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3018736555 May 26 02:25:54 PM PDT 24 May 26 02:25:58 PM PDT 24 175992966 ps
T235 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1817175342 May 26 02:26:08 PM PDT 24 May 26 02:26:10 PM PDT 24 30667808 ps
T886 /workspace/coverage/cover_reg_top/3.edn_intr_test.165394462 May 26 02:26:04 PM PDT 24 May 26 02:26:06 PM PDT 24 16802318 ps
T236 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4135513675 May 26 02:26:11 PM PDT 24 May 26 02:26:14 PM PDT 24 44939910 ps
T887 /workspace/coverage/cover_reg_top/49.edn_intr_test.4117609044 May 26 02:26:24 PM PDT 24 May 26 02:26:26 PM PDT 24 38085219 ps
T888 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2407500624 May 26 02:26:03 PM PDT 24 May 26 02:26:06 PM PDT 24 46783617 ps
T889 /workspace/coverage/cover_reg_top/32.edn_intr_test.1432860907 May 26 02:26:28 PM PDT 24 May 26 02:26:29 PM PDT 24 53259534 ps
T220 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3367886629 May 26 02:26:16 PM PDT 24 May 26 02:26:18 PM PDT 24 41871997 ps
T890 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.450650875 May 26 02:26:09 PM PDT 24 May 26 02:26:11 PM PDT 24 91555151 ps
T891 /workspace/coverage/cover_reg_top/33.edn_intr_test.2394667948 May 26 02:26:25 PM PDT 24 May 26 02:26:26 PM PDT 24 17407666 ps
T892 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2389137713 May 26 02:26:11 PM PDT 24 May 26 02:26:13 PM PDT 24 11663365 ps
T250 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.661633263 May 26 02:26:17 PM PDT 24 May 26 02:26:21 PM PDT 24 307505711 ps
T893 /workspace/coverage/cover_reg_top/40.edn_intr_test.821022856 May 26 02:26:26 PM PDT 24 May 26 02:26:28 PM PDT 24 15578829 ps
T894 /workspace/coverage/cover_reg_top/15.edn_intr_test.2438864286 May 26 02:26:13 PM PDT 24 May 26 02:26:16 PM PDT 24 28354532 ps
T254 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1731462810 May 26 02:26:00 PM PDT 24 May 26 02:26:04 PM PDT 24 299812276 ps
T895 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3455499758 May 26 02:26:05 PM PDT 24 May 26 02:26:14 PM PDT 24 438922101 ps
T896 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1618191309 May 26 02:26:14 PM PDT 24 May 26 02:26:17 PM PDT 24 66339123 ps
T897 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3638782123 May 26 02:26:16 PM PDT 24 May 26 02:26:18 PM PDT 24 39952418 ps
T251 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1688801614 May 26 02:26:09 PM PDT 24 May 26 02:26:13 PM PDT 24 71750546 ps
T221 /workspace/coverage/cover_reg_top/6.edn_csr_rw.992245941 May 26 02:26:14 PM PDT 24 May 26 02:26:17 PM PDT 24 30513660 ps
T898 /workspace/coverage/cover_reg_top/19.edn_intr_test.52442626 May 26 02:26:19 PM PDT 24 May 26 02:26:21 PM PDT 24 57334641 ps
T899 /workspace/coverage/cover_reg_top/7.edn_intr_test.2450267828 May 26 02:26:02 PM PDT 24 May 26 02:26:04 PM PDT 24 16386533 ps
T900 /workspace/coverage/cover_reg_top/46.edn_intr_test.1088419848 May 26 02:26:25 PM PDT 24 May 26 02:26:27 PM PDT 24 44719520 ps
T901 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.162559318 May 26 02:26:01 PM PDT 24 May 26 02:26:07 PM PDT 24 1050689241 ps
T902 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1301849736 May 26 02:26:12 PM PDT 24 May 26 02:26:15 PM PDT 24 44735432 ps
T903 /workspace/coverage/cover_reg_top/47.edn_intr_test.2005522306 May 26 02:26:28 PM PDT 24 May 26 02:26:29 PM PDT 24 22487517 ps
T904 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.296507254 May 26 02:26:16 PM PDT 24 May 26 02:26:19 PM PDT 24 23030830 ps
T905 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2714255995 May 26 02:26:02 PM PDT 24 May 26 02:26:04 PM PDT 24 20335551 ps
T906 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.119736260 May 26 02:26:05 PM PDT 24 May 26 02:26:08 PM PDT 24 264232438 ps
T907 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3417346341 May 26 02:26:16 PM PDT 24 May 26 02:26:20 PM PDT 24 137779910 ps
T908 /workspace/coverage/cover_reg_top/13.edn_intr_test.189587091 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 68913566 ps
T909 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1240385298 May 26 02:26:11 PM PDT 24 May 26 02:26:15 PM PDT 24 292844184 ps
T910 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3031955507 May 26 02:25:55 PM PDT 24 May 26 02:26:04 PM PDT 24 3560336570 ps
T911 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1607444043 May 26 02:26:12 PM PDT 24 May 26 02:26:15 PM PDT 24 26310750 ps
T912 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4161117323 May 26 02:26:09 PM PDT 24 May 26 02:26:14 PM PDT 24 89171671 ps
T913 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2736941591 May 26 02:26:20 PM PDT 24 May 26 02:26:22 PM PDT 24 24089408 ps
T914 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1624798585 May 26 02:26:11 PM PDT 24 May 26 02:26:14 PM PDT 24 23296522 ps
T915 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3443637398 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 48834999 ps
T916 /workspace/coverage/cover_reg_top/2.edn_csr_rw.403272211 May 26 02:25:55 PM PDT 24 May 26 02:25:57 PM PDT 24 22197677 ps
T917 /workspace/coverage/cover_reg_top/42.edn_intr_test.4282262104 May 26 02:26:26 PM PDT 24 May 26 02:26:28 PM PDT 24 13895621 ps
T918 /workspace/coverage/cover_reg_top/31.edn_intr_test.14140626 May 26 02:26:27 PM PDT 24 May 26 02:26:29 PM PDT 24 45008357 ps
T222 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2529667344 May 26 02:26:16 PM PDT 24 May 26 02:26:19 PM PDT 24 17834489 ps
T919 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3726488435 May 26 02:25:56 PM PDT 24 May 26 02:25:59 PM PDT 24 41450075 ps
T920 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1405056492 May 26 02:26:10 PM PDT 24 May 26 02:26:14 PM PDT 24 51210001 ps
T921 /workspace/coverage/cover_reg_top/1.edn_intr_test.3340133794 May 26 02:25:53 PM PDT 24 May 26 02:25:54 PM PDT 24 11247583 ps
T922 /workspace/coverage/cover_reg_top/16.edn_intr_test.3981594534 May 26 02:26:18 PM PDT 24 May 26 02:26:20 PM PDT 24 51797139 ps
T923 /workspace/coverage/cover_reg_top/39.edn_intr_test.2146453281 May 26 02:26:24 PM PDT 24 May 26 02:26:26 PM PDT 24 69433447 ps
T924 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1655703337 May 26 02:25:56 PM PDT 24 May 26 02:25:59 PM PDT 24 61421126 ps
T925 /workspace/coverage/cover_reg_top/10.edn_intr_test.7530241 May 26 02:26:13 PM PDT 24 May 26 02:26:16 PM PDT 24 34430182 ps
T926 /workspace/coverage/cover_reg_top/0.edn_intr_test.2445782575 May 26 02:25:55 PM PDT 24 May 26 02:25:57 PM PDT 24 16321728 ps
T927 /workspace/coverage/cover_reg_top/26.edn_intr_test.3096677060 May 26 02:26:19 PM PDT 24 May 26 02:26:21 PM PDT 24 89848744 ps
T928 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4223549817 May 26 02:26:12 PM PDT 24 May 26 02:26:14 PM PDT 24 13976040 ps
T929 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4114280513 May 26 02:26:09 PM PDT 24 May 26 02:26:12 PM PDT 24 239932726 ps
T223 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3657549998 May 26 02:25:55 PM PDT 24 May 26 02:25:57 PM PDT 24 33236319 ps
T930 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1749655823 May 26 02:25:54 PM PDT 24 May 26 02:26:00 PM PDT 24 180740574 ps
T224 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1838263236 May 26 02:25:55 PM PDT 24 May 26 02:26:00 PM PDT 24 135022143 ps
T931 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2420873307 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 52155313 ps
T225 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2100961853 May 26 02:25:56 PM PDT 24 May 26 02:25:58 PM PDT 24 94756270 ps
T932 /workspace/coverage/cover_reg_top/5.edn_intr_test.979776353 May 26 02:26:01 PM PDT 24 May 26 02:26:03 PM PDT 24 14406505 ps
T226 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3380059054 May 26 02:26:14 PM PDT 24 May 26 02:26:17 PM PDT 24 97190504 ps
T933 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.547573937 May 26 02:26:04 PM PDT 24 May 26 02:26:06 PM PDT 24 41310279 ps
T934 /workspace/coverage/cover_reg_top/41.edn_intr_test.3093803956 May 26 02:26:25 PM PDT 24 May 26 02:26:27 PM PDT 24 11775091 ps
T935 /workspace/coverage/cover_reg_top/5.edn_tl_errors.576816381 May 26 02:26:04 PM PDT 24 May 26 02:26:07 PM PDT 24 244084011 ps
T936 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4048828888 May 26 02:26:21 PM PDT 24 May 26 02:26:23 PM PDT 24 212950991 ps
T937 /workspace/coverage/cover_reg_top/0.edn_csr_rw.826787017 May 26 02:26:00 PM PDT 24 May 26 02:26:02 PM PDT 24 25028119 ps
T938 /workspace/coverage/cover_reg_top/45.edn_intr_test.1770767880 May 26 02:26:29 PM PDT 24 May 26 02:26:30 PM PDT 24 28829786 ps
T939 /workspace/coverage/cover_reg_top/44.edn_intr_test.3894667476 May 26 02:26:26 PM PDT 24 May 26 02:26:28 PM PDT 24 13694561 ps
T940 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3884451281 May 26 02:26:18 PM PDT 24 May 26 02:26:20 PM PDT 24 18163737 ps
T227 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2700026989 May 26 02:26:00 PM PDT 24 May 26 02:26:02 PM PDT 24 25023155 ps
T941 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1651171710 May 26 02:25:55 PM PDT 24 May 26 02:26:03 PM PDT 24 263878199 ps
T942 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1623444806 May 26 02:25:55 PM PDT 24 May 26 02:25:57 PM PDT 24 36050580 ps
T943 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1292389224 May 26 02:26:11 PM PDT 24 May 26 02:26:15 PM PDT 24 145676523 ps
T944 /workspace/coverage/cover_reg_top/22.edn_intr_test.4241103783 May 26 02:26:17 PM PDT 24 May 26 02:26:19 PM PDT 24 18388580 ps
T945 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.288699422 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 22751496 ps
T946 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3424070687 May 26 02:25:57 PM PDT 24 May 26 02:25:59 PM PDT 24 27475367 ps
T947 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2634917420 May 26 02:26:09 PM PDT 24 May 26 02:26:12 PM PDT 24 37855330 ps
T948 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.82776146 May 26 02:26:04 PM PDT 24 May 26 02:26:06 PM PDT 24 23304116 ps
T949 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3222606131 May 26 02:26:16 PM PDT 24 May 26 02:26:22 PM PDT 24 130941954 ps
T950 /workspace/coverage/cover_reg_top/37.edn_intr_test.1646882588 May 26 02:26:25 PM PDT 24 May 26 02:26:26 PM PDT 24 32812670 ps
T951 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2679907 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 86835901 ps
T952 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.480308839 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 40750561 ps
T953 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3787873447 May 26 02:26:15 PM PDT 24 May 26 02:26:17 PM PDT 24 46944872 ps
T228 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.795975044 May 26 02:26:02 PM PDT 24 May 26 02:26:05 PM PDT 24 25771956 ps
T954 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3828631177 May 26 02:26:17 PM PDT 24 May 26 02:26:21 PM PDT 24 65943235 ps
T955 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2141445890 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 36356090 ps
T956 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3824262847 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 19083604 ps
T957 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.624496243 May 26 02:26:12 PM PDT 24 May 26 02:26:15 PM PDT 24 28705256 ps
T958 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.437919181 May 26 02:26:15 PM PDT 24 May 26 02:26:18 PM PDT 24 126035199 ps
T959 /workspace/coverage/cover_reg_top/11.edn_tl_errors.4148977553 May 26 02:26:11 PM PDT 24 May 26 02:26:16 PM PDT 24 116203164 ps
T960 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.909454008 May 26 02:26:09 PM PDT 24 May 26 02:26:10 PM PDT 24 103298014 ps
T961 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2580191819 May 26 02:26:18 PM PDT 24 May 26 02:26:23 PM PDT 24 162990572 ps
T962 /workspace/coverage/cover_reg_top/17.edn_intr_test.2186368308 May 26 02:26:16 PM PDT 24 May 26 02:26:18 PM PDT 24 45991712 ps
T963 /workspace/coverage/cover_reg_top/8.edn_csr_rw.924443347 May 26 02:26:03 PM PDT 24 May 26 02:26:05 PM PDT 24 97415841 ps
T964 /workspace/coverage/cover_reg_top/12.edn_intr_test.938332193 May 26 02:26:13 PM PDT 24 May 26 02:26:15 PM PDT 24 12883029 ps
T965 /workspace/coverage/cover_reg_top/18.edn_intr_test.4069960660 May 26 02:26:17 PM PDT 24 May 26 02:26:20 PM PDT 24 20833275 ps
T966 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2155329471 May 26 02:26:06 PM PDT 24 May 26 02:26:08 PM PDT 24 55274326 ps
T967 /workspace/coverage/cover_reg_top/36.edn_intr_test.812582173 May 26 02:26:29 PM PDT 24 May 26 02:26:31 PM PDT 24 19420144 ps
T968 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3880853986 May 26 02:26:05 PM PDT 24 May 26 02:26:10 PM PDT 24 333666507 ps
T969 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1385489616 May 26 02:25:54 PM PDT 24 May 26 02:25:58 PM PDT 24 127890740 ps
T970 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3868511821 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 40517918 ps
T971 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.700452112 May 26 02:26:17 PM PDT 24 May 26 02:26:21 PM PDT 24 125899371 ps
T972 /workspace/coverage/cover_reg_top/9.edn_intr_test.3436870503 May 26 02:26:10 PM PDT 24 May 26 02:26:13 PM PDT 24 12859844 ps
T973 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3453597343 May 26 02:26:21 PM PDT 24 May 26 02:26:23 PM PDT 24 31345149 ps
T974 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1060274550 May 26 02:26:15 PM PDT 24 May 26 02:26:17 PM PDT 24 26803213 ps
T975 /workspace/coverage/cover_reg_top/23.edn_intr_test.2091084268 May 26 02:26:20 PM PDT 24 May 26 02:26:21 PM PDT 24 44531587 ps
T976 /workspace/coverage/cover_reg_top/1.edn_tl_errors.92764932 May 26 02:25:55 PM PDT 24 May 26 02:25:58 PM PDT 24 129845134 ps
T977 /workspace/coverage/cover_reg_top/2.edn_intr_test.1643720359 May 26 02:25:56 PM PDT 24 May 26 02:25:58 PM PDT 24 29169679 ps
T978 /workspace/coverage/cover_reg_top/30.edn_intr_test.1260889622 May 26 02:26:24 PM PDT 24 May 26 02:26:26 PM PDT 24 27532727 ps
T229 /workspace/coverage/cover_reg_top/7.edn_csr_rw.616083108 May 26 02:26:10 PM PDT 24 May 26 02:26:12 PM PDT 24 15531974 ps
T979 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.955077644 May 26 02:26:12 PM PDT 24 May 26 02:26:15 PM PDT 24 36748883 ps
T980 /workspace/coverage/cover_reg_top/24.edn_intr_test.3030877579 May 26 02:26:16 PM PDT 24 May 26 02:26:18 PM PDT 24 13871184 ps

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2734418641
Short name T1
Test name
Test status
Simulation time 24566331774 ps
CPU time 368.65 seconds
Started May 26 01:15:21 PM PDT 24
Finished May 26 01:21:32 PM PDT 24
Peak memory 220416 kb
Host smart-dd15962d-4399-4b1a-882c-9cb45972e20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734418641 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2734418641
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_alert.3964307575
Short name T8
Test name
Test status
Simulation time 62346738 ps
CPU time 1.25 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 215372 kb
Host smart-ab21627a-ebed-4023-8c01-af98dbd4f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964307575 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3964307575
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/68.edn_genbits.1892806480
Short name T45
Test name
Test status
Simulation time 56258696 ps
CPU time 1.32 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 219096 kb
Host smart-b35f2beb-a86b-41b0-9165-8257f6e453c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892806480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1892806480
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4024365834
Short name T14
Test name
Test status
Simulation time 362669074 ps
CPU time 6.21 seconds
Started May 26 01:14:22 PM PDT 24
Finished May 26 01:14:30 PM PDT 24
Peak memory 234708 kb
Host smart-247baa38-c100-4389-9798-70056330c28f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024365834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4024365834
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/94.edn_err.160982293
Short name T3
Test name
Test status
Simulation time 25952809 ps
CPU time 1.33 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 229060 kb
Host smart-b6c3af7d-716d-4776-ad6a-dc1b0c99e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160982293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.160982293
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3995640242
Short name T50
Test name
Test status
Simulation time 84699261 ps
CPU time 1.12 seconds
Started May 26 01:14:33 PM PDT 24
Finished May 26 01:14:36 PM PDT 24
Peak memory 217812 kb
Host smart-d1061859-df7b-4092-abaa-89efeb329e9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995640242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3995640242
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.732749626
Short name T18
Test name
Test status
Simulation time 41151254 ps
CPU time 1.12 seconds
Started May 26 01:14:58 PM PDT 24
Finished May 26 01:15:00 PM PDT 24
Peak memory 217692 kb
Host smart-8cdf808e-d605-428d-a79f-d742c4641f99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732749626 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.732749626
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3291828457
Short name T203
Test name
Test status
Simulation time 46660588961 ps
CPU time 506.46 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:23:52 PM PDT 24
Peak memory 217680 kb
Host smart-b5c05bb0-6db4-4b72-b97c-1e12a7385054
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291828457 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3291828457
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4070513166
Short name T37
Test name
Test status
Simulation time 17983071798 ps
CPU time 248.27 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:19:42 PM PDT 24
Peak memory 216404 kb
Host smart-c899cbab-61c2-4df4-b4c6-b692322fa99b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070513166 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4070513166
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.edn_disable.3822714462
Short name T43
Test name
Test status
Simulation time 18551207 ps
CPU time 0.83 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:43 PM PDT 24
Peak memory 215896 kb
Host smart-70125485-5365-4636-bc93-c78be4a69ba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822714462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3822714462
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/18.edn_alert.3023630759
Short name T123
Test name
Test status
Simulation time 28940279 ps
CPU time 1.29 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 215232 kb
Host smart-e3cd54cb-2846-4ba3-8abf-f35b840605c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023630759 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3023630759
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.2078883925
Short name T262
Test name
Test status
Simulation time 32058870 ps
CPU time 0.98 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 206644 kb
Host smart-9211de3c-a3a2-4b47-a214-6addbe540eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078883925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2078883925
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/17.edn_err.3302241568
Short name T29
Test name
Test status
Simulation time 23576151 ps
CPU time 0.95 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 218900 kb
Host smart-30943be9-60c7-4ece-92e1-f648dbb39d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302241568 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3302241568
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/19.edn_alert.519128440
Short name T541
Test name
Test status
Simulation time 26907663 ps
CPU time 1.18 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 215332 kb
Host smart-b98cc847-8b71-4cc3-b3a2-50cffc1e1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519128440 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.519128440
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.661633263
Short name T250
Test name
Test status
Simulation time 307505711 ps
CPU time 2.59 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206244 kb
Host smart-2b742f66-c948-46f7-b5c9-a5498b8f02b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661633263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.661633263
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/default/267.edn_genbits.4136978370
Short name T84
Test name
Test status
Simulation time 45000064 ps
CPU time 1.24 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:49 PM PDT 24
Peak memory 218072 kb
Host smart-fcc6f01b-cded-445c-99b3-e788d41eb794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136978370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.4136978370
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2100961853
Short name T225
Test name
Test status
Simulation time 94756270 ps
CPU time 1.19 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206236 kb
Host smart-b5cf71cd-f44e-447e-84a1-ca7f7c290a3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100961853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2100961853
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.624044202
Short name T87
Test name
Test status
Simulation time 209468307 ps
CPU time 1.14 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 216476 kb
Host smart-fc74f50e-db5d-401e-8af8-3c194813e8a4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624044202 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.624044202
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_alert.1046972124
Short name T626
Test name
Test status
Simulation time 51028629 ps
CPU time 1.18 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:19 PM PDT 24
Peak memory 215360 kb
Host smart-9a138355-0ddc-4d96-8d9d-1482ab1fa9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046972124 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1046972124
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/33.edn_disable.2603193762
Short name T178
Test name
Test status
Simulation time 20310402 ps
CPU time 0.86 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 215904 kb
Host smart-a48bfa2f-37f5-4b94-bb2c-6f5ffa18820f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603193762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2603193762
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3737565136
Short name T91
Test name
Test status
Simulation time 149882331 ps
CPU time 1.17 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:15:15 PM PDT 24
Peak memory 216364 kb
Host smart-a57e47e1-52fc-4dce-9753-d5e0b0e2c27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737565136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3737565136
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_disable.275028343
Short name T177
Test name
Test status
Simulation time 30337837 ps
CPU time 0.85 seconds
Started May 26 01:15:22 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 215804 kb
Host smart-b0e3456b-1a02-46f1-ae03-e276731d6940
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275028343 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.275028343
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2586133978
Short name T121
Test name
Test status
Simulation time 51340861 ps
CPU time 0.99 seconds
Started May 26 01:14:57 PM PDT 24
Finished May 26 01:14:58 PM PDT 24
Peak memory 223184 kb
Host smart-64cbebfc-7dc9-4273-8395-1f852dbe295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586133978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2586133978
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/24.edn_disable.1681328585
Short name T186
Test name
Test status
Simulation time 54677688 ps
CPU time 0.85 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 216092 kb
Host smart-1834670a-0ca9-42aa-be1d-7cac782b5e80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681328585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1681328585
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/289.edn_genbits.2129148263
Short name T86
Test name
Test status
Simulation time 45608891 ps
CPU time 0.97 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:48 PM PDT 24
Peak memory 216784 kb
Host smart-64fa1433-6d38-480c-a7e3-2c850723b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129148263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2129148263
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.506296570
Short name T30
Test name
Test status
Simulation time 27254401 ps
CPU time 0.94 seconds
Started May 26 01:14:45 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 214964 kb
Host smart-ec5c52e1-2695-4da2-95c8-fadfe5c9e4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506296570 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.506296570
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1686124431
Short name T78
Test name
Test status
Simulation time 41277275 ps
CPU time 1.4 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 216596 kb
Host smart-95783fd5-7429-4c10-882d-49a0b6e0ea9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686124431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1686124431
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.1589287818
Short name T93
Test name
Test status
Simulation time 37797438 ps
CPU time 1.7 seconds
Started May 26 01:15:54 PM PDT 24
Finished May 26 01:15:56 PM PDT 24
Peak memory 219488 kb
Host smart-633eb1a9-200a-47e8-8546-d5ddcd72f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589287818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1589287818
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3219507575
Short name T81
Test name
Test status
Simulation time 59009532 ps
CPU time 2.13 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 219312 kb
Host smart-b7e69075-9d66-40a4-83d6-7c43ea3de9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219507575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3219507575
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.643553516
Short name T747
Test name
Test status
Simulation time 22658567 ps
CPU time 0.93 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 215248 kb
Host smart-a4a23147-e69a-41d3-b64a-73feab0a2cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643553516 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.643553516
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/2.edn_alert_test.1426568838
Short name T237
Test name
Test status
Simulation time 14188184 ps
CPU time 0.95 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:31 PM PDT 24
Peak memory 214460 kb
Host smart-5eb47788-5ab6-4226-b95b-7cc04a4d4038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426568838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1426568838
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2453458239
Short name T483
Test name
Test status
Simulation time 38541979 ps
CPU time 1.13 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 216652 kb
Host smart-726900ca-061a-414f-b8a2-b90c18a58f88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453458239 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2453458239
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_disable.1207814623
Short name T141
Test name
Test status
Simulation time 43390630 ps
CPU time 0.88 seconds
Started May 26 01:14:51 PM PDT 24
Finished May 26 01:14:53 PM PDT 24
Peak memory 216000 kb
Host smart-cefdfbe9-0166-479b-bd43-d6344dfebe7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207814623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1207814623
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3100005211
Short name T189
Test name
Test status
Simulation time 112386739 ps
CPU time 1.34 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 216376 kb
Host smart-d816eef4-a5f6-4b02-b59d-499895c0df32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100005211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3100005211
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable.612229392
Short name T176
Test name
Test status
Simulation time 16757444 ps
CPU time 0.85 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 216008 kb
Host smart-c6cd2ea1-f487-481a-b310-68fd6ef48224
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612229392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.612229392
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.384536753
Short name T193
Test name
Test status
Simulation time 51489144 ps
CPU time 0.78 seconds
Started May 26 01:15:36 PM PDT 24
Finished May 26 01:15:38 PM PDT 24
Peak memory 216084 kb
Host smart-feb5ece7-efab-4ef3-8d86-39d8cca7110f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384536753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.384536753
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3282297369
Short name T183
Test name
Test status
Simulation time 42629584 ps
CPU time 1.39 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 216516 kb
Host smart-0dba617f-8887-4242-a677-f28f5064fa46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282297369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3282297369
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/76.edn_err.4135793301
Short name T147
Test name
Test status
Simulation time 24408174 ps
CPU time 1.04 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 223296 kb
Host smart-85373f19-8d77-4eb8-a165-1ab289b3a577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135793301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4135793301
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.3614127547
Short name T268
Test name
Test status
Simulation time 27573315 ps
CPU time 0.95 seconds
Started May 26 01:14:19 PM PDT 24
Finished May 26 01:14:21 PM PDT 24
Peak memory 206668 kb
Host smart-9d825a7a-8797-4aa5-8958-636be672815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614127547 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3614127547
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/15.edn_alert.3170869259
Short name T173
Test name
Test status
Simulation time 26697631 ps
CPU time 1.26 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 215308 kb
Host smart-92b141ac-5dbe-4e3d-b3f2-d11421460a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170869259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3170869259
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.141544662
Short name T25
Test name
Test status
Simulation time 59099276 ps
CPU time 0.9 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 206732 kb
Host smart-d180971e-1764-4615-8c79-720976c8a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141544662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.141544662
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1300676846
Short name T217
Test name
Test status
Simulation time 237012236 ps
CPU time 1.15 seconds
Started May 26 02:25:54 PM PDT 24
Finished May 26 02:25:55 PM PDT 24
Peak memory 206272 kb
Host smart-f76170b3-2e3a-47a3-a432-8b603e25c18c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300676846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1300676846
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.edn_genbits.887877091
Short name T10
Test name
Test status
Simulation time 61363124 ps
CPU time 1.32 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 219204 kb
Host smart-6e39e9fa-2566-4913-a744-cfb579cbf783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887877091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.887877091
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1248899797
Short name T527
Test name
Test status
Simulation time 214924316388 ps
CPU time 1534.88 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:40:26 PM PDT 24
Peak memory 225064 kb
Host smart-45d18971-f3b3-4cb1-8bdb-ebf4ab20379c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248899797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1248899797
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.edn_genbits.628120658
Short name T286
Test name
Test status
Simulation time 45763858 ps
CPU time 1.77 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 217720 kb
Host smart-e5f61146-f3cd-4b88-a8ec-c84f983c7f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628120658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.628120658
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.310062932
Short name T199
Test name
Test status
Simulation time 38158263 ps
CPU time 1.1 seconds
Started May 26 01:15:25 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 214984 kb
Host smart-69d4e213-40f7-4dc1-85a9-354d7d87997e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310062932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.310062932
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/17.edn_intr.2587336965
Short name T32
Test name
Test status
Simulation time 23668073 ps
CPU time 1 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:04 PM PDT 24
Peak memory 215224 kb
Host smart-f7dabe50-27c5-4c79-88be-76b42409d021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587336965 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.2587336965
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/234.edn_genbits.1831196737
Short name T329
Test name
Test status
Simulation time 1274448967 ps
CPU time 8.73 seconds
Started May 26 01:16:32 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 219552 kb
Host smart-4324f11c-eabe-4ab6-98e6-9ceddbd5c07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831196737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1831196737
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3745116190
Short name T22
Test name
Test status
Simulation time 22222789 ps
CPU time 1.04 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 215280 kb
Host smart-fdc8baf6-a24e-4ca9-96a9-43ffa1b39c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745116190 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3745116190
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1731462810
Short name T254
Test name
Test status
Simulation time 299812276 ps
CPU time 2.26 seconds
Started May 26 02:26:00 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 214384 kb
Host smart-6e3b2a0d-ae14-46a1-8c97-a3b65d42c67f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731462810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1731462810
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1540563303
Short name T293
Test name
Test status
Simulation time 47943984 ps
CPU time 1.32 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 216712 kb
Host smart-0f2d1250-0153-4fad-841c-60045bf59f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540563303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1540563303
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3009717302
Short name T279
Test name
Test status
Simulation time 99526744 ps
CPU time 1.15 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 218080 kb
Host smart-aa436f70-90f1-48f6-a9a6-64368db864ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009717302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3009717302
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3034891611
Short name T82
Test name
Test status
Simulation time 88864226 ps
CPU time 1.4 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 218416 kb
Host smart-eb835b08-8659-4507-a52a-fd49cc7c7953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034891611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3034891611
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1224990055
Short name T287
Test name
Test status
Simulation time 121287927 ps
CPU time 1.32 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 219236 kb
Host smart-34a48b61-1076-4bfd-a725-4763bb723ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224990055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1224990055
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2909407682
Short name T204
Test name
Test status
Simulation time 71373910268 ps
CPU time 1668.91 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:42:53 PM PDT 24
Peak memory 222836 kb
Host smart-87408790-15af-4923-b590-caedfc6ec5f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909407682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2909407682
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.edn_genbits.2947592210
Short name T280
Test name
Test status
Simulation time 26969369 ps
CPU time 1.23 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 218952 kb
Host smart-5caba919-c379-4b93-9303-11f196e70067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947592210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2947592210
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.76807512
Short name T259
Test name
Test status
Simulation time 26292047 ps
CPU time 0.92 seconds
Started May 26 01:14:22 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 206628 kb
Host smart-d8ee581a-af9d-4860-a4ea-ef4d262182da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76807512 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.76807512
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/241.edn_genbits.19225520
Short name T290
Test name
Test status
Simulation time 40063590 ps
CPU time 1.55 seconds
Started May 26 01:16:44 PM PDT 24
Finished May 26 01:16:47 PM PDT 24
Peak memory 217820 kb
Host smart-c29fdf16-2676-4741-b7c2-4ab2149ef99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19225520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.19225520
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1744035308
Short name T296
Test name
Test status
Simulation time 29013866 ps
CPU time 1.31 seconds
Started May 26 01:16:37 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 218060 kb
Host smart-25e775e9-5794-41c1-9d7c-d70ae6910749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744035308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1744035308
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3622243263
Short name T35
Test name
Test status
Simulation time 27462039 ps
CPU time 0.93 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 215332 kb
Host smart-029f6aac-5f06-468c-bc31-b3248c07d0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622243263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3622243263
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/126.edn_genbits.2770019601
Short name T247
Test name
Test status
Simulation time 269023034 ps
CPU time 1.43 seconds
Started May 26 01:16:19 PM PDT 24
Finished May 26 01:16:22 PM PDT 24
Peak memory 218204 kb
Host smart-4b537352-3830-41d6-b8a6-a08859135d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770019601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2770019601
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.3980313011
Short name T172
Test name
Test status
Simulation time 74572581 ps
CPU time 1.18 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 215056 kb
Host smart-53446dd4-3b1f-4b99-b26c-1e53e5693e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980313011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3980313011
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2017653105
Short name T184
Test name
Test status
Simulation time 21798285 ps
CPU time 0.88 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 216020 kb
Host smart-6dc91a5b-16bb-40d8-8784-1aff29238395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017653105 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2017653105
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.354153025
Short name T490
Test name
Test status
Simulation time 76458707 ps
CPU time 1.59 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:56 PM PDT 24
Peak memory 219460 kb
Host smart-ed23555e-0d51-4e43-8986-0df58864017e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354153025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.354153025
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3824262847
Short name T956
Test name
Test status
Simulation time 19083604 ps
CPU time 1.27 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206200 kb
Host smart-493b5eee-a744-4335-ba9a-0f617ad116c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824262847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3824262847
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1838263236
Short name T224
Test name
Test status
Simulation time 135022143 ps
CPU time 3.71 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:26:00 PM PDT 24
Peak memory 206360 kb
Host smart-8ad1672e-e330-4389-963b-eef5dffa1fda
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838263236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1838263236
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1792406266
Short name T885
Test name
Test status
Simulation time 53432209 ps
CPU time 0.93 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206196 kb
Host smart-27eb9d4f-6538-434a-b30c-fe8b9f6f2588
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792406266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1792406266
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1390562211
Short name T866
Test name
Test status
Simulation time 206940995 ps
CPU time 1.04 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206300 kb
Host smart-c47e8ff0-d5bb-41e5-b1b1-9f8e94c5f409
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390562211 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1390562211
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.826787017
Short name T937
Test name
Test status
Simulation time 25028119 ps
CPU time 0.94 seconds
Started May 26 02:26:00 PM PDT 24
Finished May 26 02:26:02 PM PDT 24
Peak memory 206188 kb
Host smart-156b2bd8-38cf-4328-a788-0e95f1bfdb64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826787017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.826787017
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2445782575
Short name T926
Test name
Test status
Simulation time 16321728 ps
CPU time 0.86 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:57 PM PDT 24
Peak memory 206136 kb
Host smart-35af028d-c260-44ea-945d-63c2beda943f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445782575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2445782575
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1655703337
Short name T924
Test name
Test status
Simulation time 61421126 ps
CPU time 1 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:59 PM PDT 24
Peak memory 206328 kb
Host smart-f89573b8-18c3-4dfb-8f57-36c07a7d1fc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655703337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1655703337
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.4119842333
Short name T860
Test name
Test status
Simulation time 81999853 ps
CPU time 2.13 seconds
Started May 26 02:26:00 PM PDT 24
Finished May 26 02:26:03 PM PDT 24
Peak memory 214380 kb
Host smart-3676221c-7987-45da-8586-997f68040a4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119842333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.4119842333
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3018736555
Short name T249
Test name
Test status
Simulation time 175992966 ps
CPU time 2.68 seconds
Started May 26 02:25:54 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206420 kb
Host smart-32945502-0e85-49ca-9c39-43345c4daa92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018736555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3018736555
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3031955507
Short name T910
Test name
Test status
Simulation time 3560336570 ps
CPU time 7.19 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 206296 kb
Host smart-9cab09af-8080-4b9c-b3b3-1cc5e596f1ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031955507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3031955507
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1756988210
Short name T240
Test name
Test status
Simulation time 39436802 ps
CPU time 0.87 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206108 kb
Host smart-e7290c80-90a1-4b1a-9476-86ca0c858e19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756988210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1756988210
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3726488435
Short name T919
Test name
Test status
Simulation time 41450075 ps
CPU time 1.3 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:59 PM PDT 24
Peak memory 214448 kb
Host smart-1da61537-7d79-4aad-83de-1082be4c881e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726488435 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3726488435
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2700026989
Short name T227
Test name
Test status
Simulation time 25023155 ps
CPU time 0.94 seconds
Started May 26 02:26:00 PM PDT 24
Finished May 26 02:26:02 PM PDT 24
Peak memory 206180 kb
Host smart-fc263581-dfc3-4276-848f-c37a500dece8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700026989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2700026989
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3340133794
Short name T921
Test name
Test status
Simulation time 11247583 ps
CPU time 0.87 seconds
Started May 26 02:25:53 PM PDT 24
Finished May 26 02:25:54 PM PDT 24
Peak memory 206104 kb
Host smart-6bee0400-2790-44c1-9130-c36fc96155ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340133794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3340133794
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.92764932
Short name T976
Test name
Test status
Simulation time 129845134 ps
CPU time 2.45 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 214508 kb
Host smart-755edba9-a1ce-4bd6-bf4a-eb23278c686f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92764932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.92764932
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.367940897
Short name T855
Test name
Test status
Simulation time 22661277 ps
CPU time 1.53 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 214448 kb
Host smart-8f474559-ac4a-4533-a98b-f3d821af92a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367940897 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.367940897
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2389137713
Short name T892
Test name
Test status
Simulation time 11663365 ps
CPU time 0.89 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206232 kb
Host smart-88908dd4-4db4-4bf5-bee8-b603ab2387ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389137713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2389137713
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.7530241
Short name T925
Test name
Test status
Simulation time 34430182 ps
CPU time 0.87 seconds
Started May 26 02:26:13 PM PDT 24
Finished May 26 02:26:16 PM PDT 24
Peak memory 206096 kb
Host smart-c7a98db2-5b6e-4efb-b391-d9b0d3439994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7530241 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.7530241
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1607444043
Short name T911
Test name
Test status
Simulation time 26310750 ps
CPU time 1.03 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206284 kb
Host smart-8fbfd6ab-4da8-4e96-91d5-83a633c72118
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607444043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1607444043
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2973298757
Short name T880
Test name
Test status
Simulation time 196133295 ps
CPU time 3.71 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 214400 kb
Host smart-4c2d8b20-3861-4413-9b98-0d7d6da692ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973298757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2973298757
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1240385298
Short name T909
Test name
Test status
Simulation time 292844184 ps
CPU time 2.3 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206212 kb
Host smart-f61899cc-9e5e-4f1f-a4eb-088da65f4a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240385298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1240385298
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.450650875
Short name T890
Test name
Test status
Simulation time 91555151 ps
CPU time 1.04 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:11 PM PDT 24
Peak memory 206312 kb
Host smart-52f0cc9d-396b-42b3-baf4-3ae05008eb12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450650875 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.450650875
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4223549817
Short name T928
Test name
Test status
Simulation time 13976040 ps
CPU time 0.88 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206236 kb
Host smart-8d896d9d-f0ba-4e77-9653-ccbad34c76e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223549817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4223549817
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2973969401
Short name T864
Test name
Test status
Simulation time 12174048 ps
CPU time 0.85 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206040 kb
Host smart-12cbf677-a939-4a5f-801c-68ab0e2ca5a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973969401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2973969401
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1624798585
Short name T914
Test name
Test status
Simulation time 23296522 ps
CPU time 1.19 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206244 kb
Host smart-a27813f9-03d4-4efe-a18e-996bfb9caebd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624798585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1624798585
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4148977553
Short name T959
Test name
Test status
Simulation time 116203164 ps
CPU time 3.87 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:16 PM PDT 24
Peak memory 214420 kb
Host smart-fcb99a6b-1323-4f88-9cf2-cc0574a7cc31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148977553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4148977553
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4161117323
Short name T912
Test name
Test status
Simulation time 89171671 ps
CPU time 2.54 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206452 kb
Host smart-68693a1e-7909-4942-874d-73da07613492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161117323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4161117323
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2258735080
Short name T879
Test name
Test status
Simulation time 128532940 ps
CPU time 1.56 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 214476 kb
Host smart-5bb21980-c488-495d-8b94-73ec32004b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258735080 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2258735080
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.269742517
Short name T232
Test name
Test status
Simulation time 32330064 ps
CPU time 0.83 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:10 PM PDT 24
Peak memory 206132 kb
Host smart-7d2134f5-47d5-47b0-bb22-939fa2e7f663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269742517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.269742517
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.938332193
Short name T964
Test name
Test status
Simulation time 12883029 ps
CPU time 0.88 seconds
Started May 26 02:26:13 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 205940 kb
Host smart-30b01e2c-4a52-4022-8061-7af900c2db3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938332193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.938332193
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3380059054
Short name T226
Test name
Test status
Simulation time 97190504 ps
CPU time 1.25 seconds
Started May 26 02:26:14 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206088 kb
Host smart-ea6edb22-16f6-4842-b3d1-68ce8667cc6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380059054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3380059054
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4114280513
Short name T929
Test name
Test status
Simulation time 239932726 ps
CPU time 2.92 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:12 PM PDT 24
Peak memory 214424 kb
Host smart-9d0112c9-103f-4e32-b416-521ab266fd83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114280513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4114280513
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1292389224
Short name T943
Test name
Test status
Simulation time 145676523 ps
CPU time 1.59 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206216 kb
Host smart-1b69aed7-0e50-4ad6-963d-3ad4002fcaf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292389224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1292389224
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.624496243
Short name T957
Test name
Test status
Simulation time 28705256 ps
CPU time 1.27 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 214396 kb
Host smart-6662ec5d-9eec-498b-83b1-753c3bb78395
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624496243 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.624496243
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3367886629
Short name T220
Test name
Test status
Simulation time 41871997 ps
CPU time 0.87 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 206192 kb
Host smart-5fead13e-50c9-47e4-b1d7-80f43559fee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367886629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3367886629
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.189587091
Short name T908
Test name
Test status
Simulation time 68913566 ps
CPU time 0.86 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206140 kb
Host smart-3812c3a5-cb75-473b-8c23-129cbda78f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189587091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.189587091
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.533339614
Short name T218
Test name
Test status
Simulation time 30600869 ps
CPU time 1.14 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206244 kb
Host smart-96bc09c7-800d-4533-99bc-b5a3aaa10c65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533339614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.533339614
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2420873307
Short name T931
Test name
Test status
Simulation time 52155313 ps
CPU time 2.23 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 214428 kb
Host smart-f19514cf-3799-426c-a73b-4a6ed3ff6e11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420873307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2420873307
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3417346341
Short name T907
Test name
Test status
Simulation time 137779910 ps
CPU time 3.34 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 214392 kb
Host smart-893eda01-e025-465a-ad65-a046f4f19dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417346341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3417346341
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.480308839
Short name T952
Test name
Test status
Simulation time 40750561 ps
CPU time 1.99 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 214444 kb
Host smart-9b1ec67b-c5cf-4075-adc2-4ccf3572a96a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480308839 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.480308839
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3787873447
Short name T953
Test name
Test status
Simulation time 46944872 ps
CPU time 0.95 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206192 kb
Host smart-df4a6bc2-621b-47a6-8b7c-9570c2a26e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787873447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3787873447
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3700070343
Short name T878
Test name
Test status
Simulation time 40358727 ps
CPU time 0.89 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206088 kb
Host smart-fb92bda5-bc0d-4a9b-8741-2ff53e40f225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700070343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3700070343
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4135513675
Short name T236
Test name
Test status
Simulation time 44939910 ps
CPU time 1.16 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206188 kb
Host smart-9991ee51-f4f9-4a6a-b48a-26419982914c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135513675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4135513675
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2250290263
Short name T857
Test name
Test status
Simulation time 140906882 ps
CPU time 2.8 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:16 PM PDT 24
Peak memory 214480 kb
Host smart-82614e01-71b7-4ffb-9a2a-39f432d80e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250290263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2250290263
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1688801614
Short name T251
Test name
Test status
Simulation time 71750546 ps
CPU time 2.22 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206244 kb
Host smart-f5a56d0a-5520-42d2-8b81-8dcdd75ee457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688801614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1688801614
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.288699422
Short name T945
Test name
Test status
Simulation time 22751496 ps
CPU time 1.39 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 214756 kb
Host smart-48ac96de-8c90-4996-aeb4-eafa2e842d9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288699422 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.288699422
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4020128301
Short name T884
Test name
Test status
Simulation time 114458957 ps
CPU time 0.97 seconds
Started May 26 02:26:11 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206196 kb
Host smart-8af2c58b-2a1b-45ed-b87c-c4bd4089b6b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020128301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4020128301
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2438864286
Short name T894
Test name
Test status
Simulation time 28354532 ps
CPU time 0.82 seconds
Started May 26 02:26:13 PM PDT 24
Finished May 26 02:26:16 PM PDT 24
Peak memory 206092 kb
Host smart-ba88ce44-1f2c-4c66-9e6a-9e9f10544c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438864286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2438864286
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1618191309
Short name T896
Test name
Test status
Simulation time 66339123 ps
CPU time 1.02 seconds
Started May 26 02:26:14 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206092 kb
Host smart-40137dfd-ae2f-4241-b0ff-502f847f5c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618191309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1618191309
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1405056492
Short name T920
Test name
Test status
Simulation time 51210001 ps
CPU time 2.07 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 214464 kb
Host smart-d6879d82-865b-4c02-9ccf-ecf4bb55fb43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405056492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1405056492
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3851367468
Short name T253
Test name
Test status
Simulation time 226383988 ps
CPU time 1.67 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 206212 kb
Host smart-e0a5bff0-249e-4714-b226-a4e516654fed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851367468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3851367468
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3638782123
Short name T897
Test name
Test status
Simulation time 39952418 ps
CPU time 1.09 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 216304 kb
Host smart-d292f5a1-36ce-4d83-99f8-a8aaf8ba8e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638782123 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3638782123
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2529667344
Short name T222
Test name
Test status
Simulation time 17834489 ps
CPU time 1 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 206236 kb
Host smart-8d74274c-687b-49ba-958a-7ba2abb3abae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529667344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2529667344
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3981594534
Short name T922
Test name
Test status
Simulation time 51797139 ps
CPU time 0.87 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 205976 kb
Host smart-dfb3fb16-ca5f-465b-b8d8-7c7bcc88173d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981594534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3981594534
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4048828888
Short name T936
Test name
Test status
Simulation time 212950991 ps
CPU time 1.26 seconds
Started May 26 02:26:21 PM PDT 24
Finished May 26 02:26:23 PM PDT 24
Peak memory 206264 kb
Host smart-6cb9b31d-1646-4e61-8568-09e67a2077e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048828888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4048828888
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.21955461
Short name T859
Test name
Test status
Simulation time 46407264 ps
CPU time 1.8 seconds
Started May 26 02:26:13 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 214540 kb
Host smart-45b35119-ee59-4496-9fa7-315afb234643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21955461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.21955461
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.700452112
Short name T971
Test name
Test status
Simulation time 125899371 ps
CPU time 3.06 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206224 kb
Host smart-2cc55d21-ca06-41f7-b6ad-9d67a1a569dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700452112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.700452112
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.4067510143
Short name T850
Test name
Test status
Simulation time 58052142 ps
CPU time 1.34 seconds
Started May 26 02:26:20 PM PDT 24
Finished May 26 02:26:22 PM PDT 24
Peak memory 222636 kb
Host smart-619c36f9-1ea3-4a0c-9f85-8106bb53231a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067510143 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.4067510143
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2900452258
Short name T234
Test name
Test status
Simulation time 18307865 ps
CPU time 0.86 seconds
Started May 26 02:26:19 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206220 kb
Host smart-81caa7f4-eabf-41d1-8fa8-c36125fa14bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900452258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2900452258
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2186368308
Short name T962
Test name
Test status
Simulation time 45991712 ps
CPU time 0.84 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 205988 kb
Host smart-db7afc45-789f-4522-a513-c9a8cf583df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186368308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2186368308
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3171082473
Short name T233
Test name
Test status
Simulation time 64670880 ps
CPU time 1.41 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206212 kb
Host smart-03fb534a-bd3f-44f3-b036-c92bd01b7f89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171082473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3171082473
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3222606131
Short name T949
Test name
Test status
Simulation time 130941954 ps
CPU time 4.26 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:22 PM PDT 24
Peak memory 214396 kb
Host smart-5039cc1e-11d2-4328-8408-f6e9cffc297d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222606131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3222606131
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1187515165
Short name T243
Test name
Test status
Simulation time 137336296 ps
CPU time 1.45 seconds
Started May 26 02:26:21 PM PDT 24
Finished May 26 02:26:23 PM PDT 24
Peak memory 206424 kb
Host smart-39116723-05ab-4820-af79-2c0c74100bb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187515165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1187515165
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.799814261
Short name T851
Test name
Test status
Simulation time 23040982 ps
CPU time 1.23 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 214500 kb
Host smart-6c14c899-1b1a-4473-8f07-00d881d873b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799814261 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.799814261
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2736941591
Short name T913
Test name
Test status
Simulation time 24089408 ps
CPU time 0.88 seconds
Started May 26 02:26:20 PM PDT 24
Finished May 26 02:26:22 PM PDT 24
Peak memory 206232 kb
Host smart-44f757dd-8f4b-40f9-804d-5f0d38032a25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736941591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2736941591
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.4069960660
Short name T965
Test name
Test status
Simulation time 20833275 ps
CPU time 0.88 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206028 kb
Host smart-f899412a-e5b7-408b-82b3-7da87bcb3c4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069960660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.4069960660
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3453597343
Short name T973
Test name
Test status
Simulation time 31345149 ps
CPU time 1.09 seconds
Started May 26 02:26:21 PM PDT 24
Finished May 26 02:26:23 PM PDT 24
Peak memory 206264 kb
Host smart-71e16317-7d8f-43fc-8144-b8032033a112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453597343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3453597343
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3506060797
Short name T849
Test name
Test status
Simulation time 198111501 ps
CPU time 3.41 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:22 PM PDT 24
Peak memory 214440 kb
Host smart-13474629-bdb5-4f1c-99e0-5c7d58516848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506060797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3506060797
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3235199198
Short name T854
Test name
Test status
Simulation time 20351296 ps
CPU time 1.1 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 214436 kb
Host smart-eba78b0b-229e-4dde-8a6d-91c15f47a629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235199198 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3235199198
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3884451281
Short name T940
Test name
Test status
Simulation time 18163737 ps
CPU time 0.86 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206092 kb
Host smart-77583fb9-81bd-4e1a-a0dd-5b66f4ca618e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884451281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3884451281
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.52442626
Short name T898
Test name
Test status
Simulation time 57334641 ps
CPU time 0.88 seconds
Started May 26 02:26:19 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206096 kb
Host smart-1bbe55db-dd1a-4c39-b80b-81f71666e230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52442626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.52442626
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1205687643
Short name T231
Test name
Test status
Simulation time 19876874 ps
CPU time 1.09 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206236 kb
Host smart-5dd12f8d-838a-4a33-9a81-ef8e2240cc36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205687643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1205687643
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2580191819
Short name T961
Test name
Test status
Simulation time 162990572 ps
CPU time 3.09 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:23 PM PDT 24
Peak memory 214444 kb
Host smart-eb9b96bc-e6d9-477a-8398-ed845a3cb513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580191819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2580191819
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3828631177
Short name T954
Test name
Test status
Simulation time 65943235 ps
CPU time 2.2 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206336 kb
Host smart-41ca0a48-8fe0-4637-a1b9-8b0581f83a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828631177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3828631177
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2141445890
Short name T955
Test name
Test status
Simulation time 36356090 ps
CPU time 1.14 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206208 kb
Host smart-cbb3d625-6123-4a08-9686-5a146b1852ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141445890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2141445890
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1651171710
Short name T941
Test name
Test status
Simulation time 263878199 ps
CPU time 6.57 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:26:03 PM PDT 24
Peak memory 206264 kb
Host smart-f0ac7441-b1d9-4e80-8861-a5b845ac8990
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651171710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1651171710
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2580737356
Short name T882
Test name
Test status
Simulation time 30782296 ps
CPU time 0.99 seconds
Started May 26 02:25:54 PM PDT 24
Finished May 26 02:25:56 PM PDT 24
Peak memory 206236 kb
Host smart-63e0335b-8069-4a3a-9796-679d970810e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580737356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2580737356
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2407500624
Short name T888
Test name
Test status
Simulation time 46783617 ps
CPU time 1.33 seconds
Started May 26 02:26:03 PM PDT 24
Finished May 26 02:26:06 PM PDT 24
Peak memory 222660 kb
Host smart-e7fcc678-61a7-425c-884b-b1b8e139b75a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407500624 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2407500624
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.403272211
Short name T916
Test name
Test status
Simulation time 22197677 ps
CPU time 0.87 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:57 PM PDT 24
Peak memory 206232 kb
Host smart-f72093da-68dc-4d7d-98c9-2cd918b92080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403272211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.403272211
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1643720359
Short name T977
Test name
Test status
Simulation time 29169679 ps
CPU time 0.78 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206008 kb
Host smart-e0bf2e6b-d27d-4b7b-8ada-ba1d713fc1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643720359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1643720359
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1623444806
Short name T942
Test name
Test status
Simulation time 36050580 ps
CPU time 1.35 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:57 PM PDT 24
Peak memory 206292 kb
Host smart-bfa512dc-233a-4396-b285-55bf14a3d741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623444806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1623444806
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.451086255
Short name T876
Test name
Test status
Simulation time 271629031 ps
CPU time 2.91 seconds
Started May 26 02:25:56 PM PDT 24
Finished May 26 02:26:00 PM PDT 24
Peak memory 214372 kb
Host smart-91153b5e-a18c-4158-98a9-85f11202750d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451086255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.451086255
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1385489616
Short name T969
Test name
Test status
Simulation time 127890740 ps
CPU time 2.65 seconds
Started May 26 02:25:54 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 214472 kb
Host smart-3f9c58c4-84ea-4bbc-850b-3b2f9b51f34a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385489616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1385489616
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3903368162
Short name T848
Test name
Test status
Simulation time 30000509 ps
CPU time 0.97 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 206344 kb
Host smart-b554c561-36a8-41d4-9cde-b338e3ba89a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903368162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3903368162
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.401075637
Short name T856
Test name
Test status
Simulation time 43848350 ps
CPU time 0.86 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206036 kb
Host smart-f12f1a75-d1d4-432d-a693-46e0bc653656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401075637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.401075637
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4241103783
Short name T944
Test name
Test status
Simulation time 18388580 ps
CPU time 0.9 seconds
Started May 26 02:26:17 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 206116 kb
Host smart-3312a584-d3ec-4c42-b526-33c2711e6039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241103783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4241103783
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2091084268
Short name T975
Test name
Test status
Simulation time 44531587 ps
CPU time 0.89 seconds
Started May 26 02:26:20 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206076 kb
Host smart-33bbc3a0-d1c9-444c-96a5-d15e331a3ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091084268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2091084268
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3030877579
Short name T980
Test name
Test status
Simulation time 13871184 ps
CPU time 0.88 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 206032 kb
Host smart-b55bf223-03c6-4b44-b641-e792462f58fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030877579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3030877579
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1299527322
Short name T863
Test name
Test status
Simulation time 11838527 ps
CPU time 0.86 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206040 kb
Host smart-364b6855-a836-4f6b-8b62-8c909a9a4ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299527322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1299527322
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3096677060
Short name T927
Test name
Test status
Simulation time 89848744 ps
CPU time 0.93 seconds
Started May 26 02:26:19 PM PDT 24
Finished May 26 02:26:21 PM PDT 24
Peak memory 206088 kb
Host smart-497f2f67-db84-41dc-bf72-f634f6c11976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096677060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3096677060
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1553005789
Short name T858
Test name
Test status
Simulation time 21190142 ps
CPU time 0.82 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 206052 kb
Host smart-f6620974-a1b5-45c2-a5d3-ab41fd7dd052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553005789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1553005789
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3035072005
Short name T869
Test name
Test status
Simulation time 16806459 ps
CPU time 0.95 seconds
Started May 26 02:26:18 PM PDT 24
Finished May 26 02:26:20 PM PDT 24
Peak memory 206104 kb
Host smart-d2d8dc44-0901-4828-ac76-7d36c146e6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035072005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3035072005
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2869154684
Short name T853
Test name
Test status
Simulation time 17035443 ps
CPU time 0.91 seconds
Started May 26 02:26:24 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 206068 kb
Host smart-a77bc436-cfe1-4159-9ac8-28056114e821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869154684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2869154684
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3424070687
Short name T946
Test name
Test status
Simulation time 27475367 ps
CPU time 1.29 seconds
Started May 26 02:25:57 PM PDT 24
Finished May 26 02:25:59 PM PDT 24
Peak memory 206200 kb
Host smart-30bb4c7a-9307-4077-acd2-6387cae74de8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424070687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3424070687
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1749655823
Short name T930
Test name
Test status
Simulation time 180740574 ps
CPU time 5.17 seconds
Started May 26 02:25:54 PM PDT 24
Finished May 26 02:26:00 PM PDT 24
Peak memory 206264 kb
Host smart-be817507-d677-470c-9bba-429de403c74a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749655823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1749655823
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3657549998
Short name T223
Test name
Test status
Simulation time 33236319 ps
CPU time 0.81 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:57 PM PDT 24
Peak memory 206020 kb
Host smart-2e8a47fb-0d30-4747-87ae-71a6805064ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657549998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3657549998
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1618821689
Short name T883
Test name
Test status
Simulation time 19141013 ps
CPU time 1.2 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 214432 kb
Host smart-d56004c8-a681-4d0b-9c38-71557beb7264
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618821689 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1618821689
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.541676635
Short name T875
Test name
Test status
Simulation time 16069160 ps
CPU time 1.07 seconds
Started May 26 02:25:58 PM PDT 24
Finished May 26 02:25:59 PM PDT 24
Peak memory 206244 kb
Host smart-b4e6898b-cc24-4dbb-b757-d0e9b5ac3031
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541676635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.541676635
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.165394462
Short name T886
Test name
Test status
Simulation time 16802318 ps
CPU time 0.81 seconds
Started May 26 02:26:04 PM PDT 24
Finished May 26 02:26:06 PM PDT 24
Peak memory 205988 kb
Host smart-844227d0-22e1-405c-92de-286251a2361c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165394462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.165394462
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2047487946
Short name T230
Test name
Test status
Simulation time 41122405 ps
CPU time 1.13 seconds
Started May 26 02:26:07 PM PDT 24
Finished May 26 02:26:08 PM PDT 24
Peak memory 206300 kb
Host smart-bbf91c1d-2502-4928-9ec3-b42dccc4eaa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047487946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2047487946
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2679907
Short name T951
Test name
Test status
Simulation time 86835901 ps
CPU time 1.79 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 218272 kb
Host smart-521da35c-8d65-43a0-b6b8-097230467e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2679907
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3868511821
Short name T970
Test name
Test status
Simulation time 40517918 ps
CPU time 1.58 seconds
Started May 26 02:25:55 PM PDT 24
Finished May 26 02:25:58 PM PDT 24
Peak memory 206300 kb
Host smart-57098906-7087-4a8c-a00d-d7fced07cc0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868511821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3868511821
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1260889622
Short name T978
Test name
Test status
Simulation time 27532727 ps
CPU time 0.9 seconds
Started May 26 02:26:24 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 206156 kb
Host smart-de59499a-253c-40f8-a30d-6bf7e6348934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260889622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1260889622
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.14140626
Short name T918
Test name
Test status
Simulation time 45008357 ps
CPU time 0.91 seconds
Started May 26 02:26:27 PM PDT 24
Finished May 26 02:26:29 PM PDT 24
Peak memory 206128 kb
Host smart-50bff9e5-20da-4dd5-a903-e3d056111983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14140626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.14140626
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1432860907
Short name T889
Test name
Test status
Simulation time 53259534 ps
CPU time 0.81 seconds
Started May 26 02:26:28 PM PDT 24
Finished May 26 02:26:29 PM PDT 24
Peak memory 206016 kb
Host smart-92600f5f-7fea-45ea-8a39-20621cfa89cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432860907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1432860907
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2394667948
Short name T891
Test name
Test status
Simulation time 17407666 ps
CPU time 0.94 seconds
Started May 26 02:26:25 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 206136 kb
Host smart-0b888fdd-aa29-4dfc-99a1-f02d28100c9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394667948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2394667948
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3312657769
Short name T868
Test name
Test status
Simulation time 12861808 ps
CPU time 0.88 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 206056 kb
Host smart-4d2d6fa7-8de9-4811-9028-67bbefdf45f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312657769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3312657769
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1675662991
Short name T865
Test name
Test status
Simulation time 21599349 ps
CPU time 0.92 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 206208 kb
Host smart-03da9a9c-69ea-4e06-97e0-61fa167a6bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675662991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1675662991
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.812582173
Short name T967
Test name
Test status
Simulation time 19420144 ps
CPU time 0.84 seconds
Started May 26 02:26:29 PM PDT 24
Finished May 26 02:26:31 PM PDT 24
Peak memory 206016 kb
Host smart-f84dc53b-d3a6-4ab5-b517-153e8125932c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812582173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.812582173
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1646882588
Short name T950
Test name
Test status
Simulation time 32812670 ps
CPU time 0.84 seconds
Started May 26 02:26:25 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 205996 kb
Host smart-12009b77-eb93-480b-998c-0ccd79760642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646882588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1646882588
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1102913275
Short name T852
Test name
Test status
Simulation time 25681144 ps
CPU time 0.88 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:28 PM PDT 24
Peak memory 206100 kb
Host smart-41543683-548d-4ee0-bba4-831ba645bca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102913275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1102913275
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2146453281
Short name T923
Test name
Test status
Simulation time 69433447 ps
CPU time 0.86 seconds
Started May 26 02:26:24 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 206048 kb
Host smart-57ce6de7-9ee4-4af3-abdd-f08d51942af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146453281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2146453281
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.795975044
Short name T228
Test name
Test status
Simulation time 25771956 ps
CPU time 1.22 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 206296 kb
Host smart-e92e1723-8256-4474-945a-a2e1da4eb04c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795975044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.795975044
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.162559318
Short name T901
Test name
Test status
Simulation time 1050689241 ps
CPU time 5.09 seconds
Started May 26 02:26:01 PM PDT 24
Finished May 26 02:26:07 PM PDT 24
Peak memory 206216 kb
Host smart-fca9a7ad-864b-45d5-abff-c4579ec365ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162559318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.162559318
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.547573937
Short name T933
Test name
Test status
Simulation time 41310279 ps
CPU time 1.02 seconds
Started May 26 02:26:04 PM PDT 24
Finished May 26 02:26:06 PM PDT 24
Peak memory 206220 kb
Host smart-db75fd9f-6e61-43d2-8e0b-8a3ae5e7406b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547573937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.547573937
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1060274550
Short name T974
Test name
Test status
Simulation time 26803213 ps
CPU time 1.27 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 214544 kb
Host smart-187257e0-4094-4566-bf57-5a2115a19efc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060274550 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1060274550
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1973709554
Short name T219
Test name
Test status
Simulation time 42843285 ps
CPU time 0.87 seconds
Started May 26 02:26:03 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 206228 kb
Host smart-0fa3b285-733c-472d-a10b-03fab247de1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973709554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1973709554
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3096774024
Short name T873
Test name
Test status
Simulation time 16596389 ps
CPU time 0.78 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 206000 kb
Host smart-019ef155-d60c-4a38-a166-2bc49752f74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096774024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3096774024
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.909454008
Short name T960
Test name
Test status
Simulation time 103298014 ps
CPU time 1.14 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:10 PM PDT 24
Peak memory 206248 kb
Host smart-89273215-4d8d-4a09-bcb1-a8b9275edf50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909454008 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.909454008
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.383067206
Short name T871
Test name
Test status
Simulation time 94941899 ps
CPU time 1.47 seconds
Started May 26 02:26:05 PM PDT 24
Finished May 26 02:26:07 PM PDT 24
Peak memory 214404 kb
Host smart-5f2f7468-24af-407b-a9c4-3ed3f1d49eae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383067206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.383067206
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2198064872
Short name T252
Test name
Test status
Simulation time 69151054 ps
CPU time 1.57 seconds
Started May 26 02:26:03 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 206260 kb
Host smart-3002c365-b734-4b21-8dae-19cca99ddd77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198064872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2198064872
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.821022856
Short name T893
Test name
Test status
Simulation time 15578829 ps
CPU time 0.96 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:28 PM PDT 24
Peak memory 206032 kb
Host smart-dcf97fb6-4e4d-49d5-91a1-59ff5e6a7176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821022856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.821022856
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3093803956
Short name T934
Test name
Test status
Simulation time 11775091 ps
CPU time 0.83 seconds
Started May 26 02:26:25 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 206080 kb
Host smart-964f68ce-e5d2-4de3-b004-abab18abc5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093803956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3093803956
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4282262104
Short name T917
Test name
Test status
Simulation time 13895621 ps
CPU time 0.91 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:28 PM PDT 24
Peak memory 206092 kb
Host smart-520e4c3e-a9fd-4b24-a333-94ce6b2b2f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282262104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4282262104
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1635413325
Short name T881
Test name
Test status
Simulation time 39614113 ps
CPU time 0.87 seconds
Started May 26 02:26:25 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 206108 kb
Host smart-f7c5a121-0b0d-4d9c-a456-68002f14e1a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635413325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1635413325
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3894667476
Short name T939
Test name
Test status
Simulation time 13694561 ps
CPU time 0.93 seconds
Started May 26 02:26:26 PM PDT 24
Finished May 26 02:26:28 PM PDT 24
Peak memory 206104 kb
Host smart-c49fd790-1ded-4317-8c04-6ed4c0686403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894667476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3894667476
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1770767880
Short name T938
Test name
Test status
Simulation time 28829786 ps
CPU time 0.79 seconds
Started May 26 02:26:29 PM PDT 24
Finished May 26 02:26:30 PM PDT 24
Peak memory 206016 kb
Host smart-d70f4ae0-1af9-4cd2-99fc-400ff1404fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770767880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1770767880
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1088419848
Short name T900
Test name
Test status
Simulation time 44719520 ps
CPU time 0.89 seconds
Started May 26 02:26:25 PM PDT 24
Finished May 26 02:26:27 PM PDT 24
Peak memory 206132 kb
Host smart-92f280c0-5cc0-4db8-bb05-fdd8f3d8c802
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088419848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1088419848
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2005522306
Short name T903
Test name
Test status
Simulation time 22487517 ps
CPU time 0.85 seconds
Started May 26 02:26:28 PM PDT 24
Finished May 26 02:26:29 PM PDT 24
Peak memory 206068 kb
Host smart-a41b48a7-7e82-483a-a7ae-6f0b09daab27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005522306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2005522306
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3035692284
Short name T867
Test name
Test status
Simulation time 21283333 ps
CPU time 0.83 seconds
Started May 26 02:26:27 PM PDT 24
Finished May 26 02:26:28 PM PDT 24
Peak memory 205856 kb
Host smart-4437b0d9-dd88-4df2-abbe-acd5580d67ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035692284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3035692284
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.4117609044
Short name T887
Test name
Test status
Simulation time 38085219 ps
CPU time 0.82 seconds
Started May 26 02:26:24 PM PDT 24
Finished May 26 02:26:26 PM PDT 24
Peak memory 206064 kb
Host smart-18ecbb64-e17d-444e-ab17-48868420607d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117609044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4117609044
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.82776146
Short name T948
Test name
Test status
Simulation time 23304116 ps
CPU time 1.21 seconds
Started May 26 02:26:04 PM PDT 24
Finished May 26 02:26:06 PM PDT 24
Peak memory 214484 kb
Host smart-f7b7fff8-6200-4d19-9eb4-6acb07207b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82776146 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.82776146
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1817175342
Short name T235
Test name
Test status
Simulation time 30667808 ps
CPU time 0.81 seconds
Started May 26 02:26:08 PM PDT 24
Finished May 26 02:26:10 PM PDT 24
Peak memory 206068 kb
Host smart-74303ef7-a2b2-4279-a5c5-2021e58c4d4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817175342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1817175342
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.979776353
Short name T932
Test name
Test status
Simulation time 14406505 ps
CPU time 0.93 seconds
Started May 26 02:26:01 PM PDT 24
Finished May 26 02:26:03 PM PDT 24
Peak memory 206104 kb
Host smart-21401cb6-17c4-4638-bc47-a9ec02ff0239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979776353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.979776353
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.119736260
Short name T906
Test name
Test status
Simulation time 264232438 ps
CPU time 1.36 seconds
Started May 26 02:26:05 PM PDT 24
Finished May 26 02:26:08 PM PDT 24
Peak memory 206240 kb
Host smart-305d44ef-01de-48aa-8b46-c938126d507a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119736260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.119736260
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.576816381
Short name T935
Test name
Test status
Simulation time 244084011 ps
CPU time 2.04 seconds
Started May 26 02:26:04 PM PDT 24
Finished May 26 02:26:07 PM PDT 24
Peak memory 214488 kb
Host smart-a598a96f-cacd-41f6-b801-671f52153a6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576816381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.576816381
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3099650554
Short name T248
Test name
Test status
Simulation time 151153753 ps
CPU time 1.53 seconds
Started May 26 02:26:04 PM PDT 24
Finished May 26 02:26:06 PM PDT 24
Peak memory 206276 kb
Host smart-3e1466e1-3359-479c-8e63-dce5faf97aed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099650554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3099650554
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2634917420
Short name T947
Test name
Test status
Simulation time 37855330 ps
CPU time 1.09 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:12 PM PDT 24
Peak memory 215924 kb
Host smart-5a7165b4-a4ae-41cc-b0b9-d98a444034fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634917420 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2634917420
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.992245941
Short name T221
Test name
Test status
Simulation time 30513660 ps
CPU time 0.89 seconds
Started May 26 02:26:14 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206212 kb
Host smart-4d0c2821-a56c-4403-9c51-ff69347a3242
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992245941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.992245941
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2343070139
Short name T874
Test name
Test status
Simulation time 44937667 ps
CPU time 0.85 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 206004 kb
Host smart-d532a0b1-224b-4237-99da-f45692c82e49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343070139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2343070139
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2714255995
Short name T905
Test name
Test status
Simulation time 20335551 ps
CPU time 1.15 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 206232 kb
Host smart-c727afea-bc84-4732-ac6c-9fb547dbbccc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714255995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2714255995
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2308818025
Short name T870
Test name
Test status
Simulation time 41639974 ps
CPU time 2.8 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 218496 kb
Host smart-be4be2bd-25a0-426a-8208-26e28efef30a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308818025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2308818025
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.437919181
Short name T958
Test name
Test status
Simulation time 126035199 ps
CPU time 2.18 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 206224 kb
Host smart-41f7e67f-1660-4522-8270-50df70f4a9c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437919181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.437919181
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3578184894
Short name T862
Test name
Test status
Simulation time 81734736 ps
CPU time 1.16 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:12 PM PDT 24
Peak memory 214628 kb
Host smart-0a3c413e-fa08-4141-95d8-9aed2d02668f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578184894 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3578184894
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.616083108
Short name T229
Test name
Test status
Simulation time 15531974 ps
CPU time 1 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:12 PM PDT 24
Peak memory 206244 kb
Host smart-b20d44b5-ddb0-4062-b344-69b6f830f2d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616083108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.616083108
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2450267828
Short name T899
Test name
Test status
Simulation time 16386533 ps
CPU time 0.97 seconds
Started May 26 02:26:02 PM PDT 24
Finished May 26 02:26:04 PM PDT 24
Peak memory 206108 kb
Host smart-0ff270af-57e3-4955-9c3e-1968743d7e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450267828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2450267828
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.955077644
Short name T979
Test name
Test status
Simulation time 36748883 ps
CPU time 1.49 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206212 kb
Host smart-b2722d02-fee3-4425-8c40-86e1c75442a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955077644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.955077644
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2155329471
Short name T966
Test name
Test status
Simulation time 55274326 ps
CPU time 1.49 seconds
Started May 26 02:26:06 PM PDT 24
Finished May 26 02:26:08 PM PDT 24
Peak memory 214524 kb
Host smart-ca4f3c9c-db7d-4a0b-a38b-ec584fdb9d96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155329471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2155329471
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3455499758
Short name T895
Test name
Test status
Simulation time 438922101 ps
CPU time 7.88 seconds
Started May 26 02:26:05 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206544 kb
Host smart-adc41787-ca76-4271-9882-d06587e4a2eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455499758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3455499758
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.296507254
Short name T904
Test name
Test status
Simulation time 23030830 ps
CPU time 1.59 seconds
Started May 26 02:26:16 PM PDT 24
Finished May 26 02:26:19 PM PDT 24
Peak memory 214560 kb
Host smart-7e0a5ea3-77c8-4316-bc7b-438328a8be76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296507254 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.296507254
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.924443347
Short name T963
Test name
Test status
Simulation time 97415841 ps
CPU time 0.91 seconds
Started May 26 02:26:03 PM PDT 24
Finished May 26 02:26:05 PM PDT 24
Peak memory 206208 kb
Host smart-dedce55a-749b-44ca-92a6-d3452aae69ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924443347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.924443347
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1921993090
Short name T877
Test name
Test status
Simulation time 16465456 ps
CPU time 0.93 seconds
Started May 26 02:26:14 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 206080 kb
Host smart-65a035d3-21e2-41f6-b2ef-aedd889fe39f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921993090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1921993090
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3443637398
Short name T915
Test name
Test status
Simulation time 48834999 ps
CPU time 1.11 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206240 kb
Host smart-e0813053-230f-4ab6-89f4-f670c0249aee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443637398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3443637398
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3880853986
Short name T968
Test name
Test status
Simulation time 333666507 ps
CPU time 3.46 seconds
Started May 26 02:26:05 PM PDT 24
Finished May 26 02:26:10 PM PDT 24
Peak memory 214404 kb
Host smart-8447bfe8-46c1-4673-bb69-7ee532b4a6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880853986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3880853986
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4208538320
Short name T242
Test name
Test status
Simulation time 127988995 ps
CPU time 1.66 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:18 PM PDT 24
Peak memory 214420 kb
Host smart-b8e53028-36ff-4adc-8191-47d95a6b4f40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208538320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4208538320
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.114636749
Short name T861
Test name
Test status
Simulation time 29899830 ps
CPU time 1.09 seconds
Started May 26 02:26:15 PM PDT 24
Finished May 26 02:26:17 PM PDT 24
Peak memory 214508 kb
Host smart-48145f76-7b0f-4596-8c46-25f267405081
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114636749 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.114636749
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2723337588
Short name T241
Test name
Test status
Simulation time 13983382 ps
CPU time 0.89 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206184 kb
Host smart-b52eb306-d88d-4ab8-a8d1-9d15d2243089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723337588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2723337588
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3436870503
Short name T972
Test name
Test status
Simulation time 12859844 ps
CPU time 0.87 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:13 PM PDT 24
Peak memory 206112 kb
Host smart-972150e2-18ef-4c80-a335-954edb49cd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436870503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3436870503
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1301849736
Short name T902
Test name
Test status
Simulation time 44735432 ps
CPU time 1.21 seconds
Started May 26 02:26:12 PM PDT 24
Finished May 26 02:26:15 PM PDT 24
Peak memory 206240 kb
Host smart-cde0b835-7b88-46da-bcfd-a13debd2e7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301849736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1301849736
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1194051954
Short name T872
Test name
Test status
Simulation time 79005590 ps
CPU time 3.25 seconds
Started May 26 02:26:09 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 218372 kb
Host smart-67a162a6-2c61-4520-bacb-6a12810321bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194051954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1194051954
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3336207705
Short name T244
Test name
Test status
Simulation time 219982449 ps
CPU time 2.51 seconds
Started May 26 02:26:10 PM PDT 24
Finished May 26 02:26:14 PM PDT 24
Peak memory 206244 kb
Host smart-bf3d89d0-2acc-4a30-b829-a191d33be25f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336207705 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3336207705
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.3070690703
Short name T375
Test name
Test status
Simulation time 16635895 ps
CPU time 0.93 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 206140 kb
Host smart-6db76731-f0be-449f-a92f-6289d24ca09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070690703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3070690703
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4027933233
Short name T488
Test name
Test status
Simulation time 38639622 ps
CPU time 0.86 seconds
Started May 26 01:14:19 PM PDT 24
Finished May 26 01:14:21 PM PDT 24
Peak memory 215580 kb
Host smart-2122d4d2-b4f8-4588-b3df-3ff7629210bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027933233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4027933233
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.22590934
Short name T312
Test name
Test status
Simulation time 49811837 ps
CPU time 1.21 seconds
Started May 26 01:14:24 PM PDT 24
Finished May 26 01:14:26 PM PDT 24
Peak memory 216360 kb
Host smart-0987275e-b90f-4eea-802a-bf3ad0e1bc8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22590934 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disa
ble_auto_req_mode.22590934
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1339389842
Short name T805
Test name
Test status
Simulation time 21018205 ps
CPU time 0.92 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 217768 kb
Host smart-526a8635-a5a4-4740-beec-70bfde272a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339389842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1339389842
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2364420514
Short name T46
Test name
Test status
Simulation time 8744447856 ps
CPU time 123.6 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:16:27 PM PDT 24
Peak memory 217908 kb
Host smart-cb2f1437-38de-4ead-b2ef-10b1f6fb1043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364420514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2364420514
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2227263279
Short name T816
Test name
Test status
Simulation time 33091798 ps
CPU time 0.99 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:23 PM PDT 24
Peak memory 223544 kb
Host smart-5f2a10fb-3171-4c8f-a9a3-16541630a4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227263279 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2227263279
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3949750554
Short name T57
Test name
Test status
Simulation time 622738364 ps
CPU time 5.13 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:27 PM PDT 24
Peak memory 238456 kb
Host smart-f0768753-f5d0-4795-a10f-9c83a0cbedd4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949750554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3949750554
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3209604436
Short name T843
Test name
Test status
Simulation time 16884842 ps
CPU time 1.01 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:23 PM PDT 24
Peak memory 214960 kb
Host smart-c25a71cd-58be-4a1a-b0c7-de82523c8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209604436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3209604436
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3741481769
Short name T506
Test name
Test status
Simulation time 584226214 ps
CPU time 6.29 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:29 PM PDT 24
Peak memory 216408 kb
Host smart-29f454a8-05a7-44e5-80c9-fef76e0eaee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741481769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3741481769
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.687120167
Short name T209
Test name
Test status
Simulation time 29820974691 ps
CPU time 324.64 seconds
Started May 26 01:14:22 PM PDT 24
Finished May 26 01:19:48 PM PDT 24
Peak memory 218268 kb
Host smart-5d9fa939-92dd-4c4d-8279-f8685c15bff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687120167 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.687120167
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1586712792
Short name T131
Test name
Test status
Simulation time 28873086 ps
CPU time 1.22 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 215228 kb
Host smart-bf02b683-f6ee-4db9-8924-f3f93f04c8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586712792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1586712792
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.3645786845
Short name T462
Test name
Test status
Simulation time 22069392 ps
CPU time 1.04 seconds
Started May 26 01:14:24 PM PDT 24
Finished May 26 01:14:26 PM PDT 24
Peak memory 214372 kb
Host smart-6654ce6a-c2eb-4017-b9e5-6caea7d422f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645786845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3645786845
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3000197593
Short name T520
Test name
Test status
Simulation time 16692783 ps
CPU time 0.85 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 216144 kb
Host smart-310e0812-4aa4-4266-8d5c-48155ae35242
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000197593 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3000197593
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3897748648
Short name T466
Test name
Test status
Simulation time 30903159 ps
CPU time 1.17 seconds
Started May 26 01:14:25 PM PDT 24
Finished May 26 01:14:27 PM PDT 24
Peak memory 219176 kb
Host smart-c39e5312-8dcd-4e1f-91a0-4f20cca1d3b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897748648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3897748648
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2689860989
Short name T834
Test name
Test status
Simulation time 47036829 ps
CPU time 0.98 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 218360 kb
Host smart-ea3dc3e2-732e-437b-9511-fb9dc3dd9273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689860989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2689860989
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.4080601647
Short name T377
Test name
Test status
Simulation time 35514032 ps
CPU time 1.35 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 216676 kb
Host smart-aabf6f2a-726f-4eed-a6c7-6c8374ab7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080601647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.4080601647
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2285408542
Short name T12
Test name
Test status
Simulation time 25606622 ps
CPU time 1.05 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 223448 kb
Host smart-7c6eb4c3-2b5f-49d5-97d6-a42de278d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285408542 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2285408542
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.3504590215
Short name T24
Test name
Test status
Simulation time 56583736 ps
CPU time 0.95 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 206704 kb
Host smart-312829de-28c8-4573-8ec3-b8efaf2098fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504590215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3504590215
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_smoke.1599574987
Short name T798
Test name
Test status
Simulation time 18024889 ps
CPU time 0.99 seconds
Started May 26 01:14:22 PM PDT 24
Finished May 26 01:14:25 PM PDT 24
Peak memory 214960 kb
Host smart-400af14e-44cf-4124-a0e0-f524dcd7c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599574987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1599574987
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.125328691
Short name T726
Test name
Test status
Simulation time 396607581 ps
CPU time 4.4 seconds
Started May 26 01:14:24 PM PDT 24
Finished May 26 01:14:30 PM PDT 24
Peak memory 216676 kb
Host smart-efc18fdd-89e6-4ba8-8408-79c55c4e56d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125328691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.125328691
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4035076688
Short name T807
Test name
Test status
Simulation time 24399788027 ps
CPU time 551.08 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:23:34 PM PDT 24
Peak memory 223220 kb
Host smart-8e0b9050-70cc-42d4-97ae-dbefbd6c033d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035076688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4035076688
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2089070607
Short name T614
Test name
Test status
Simulation time 42988751 ps
CPU time 1.53 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 215588 kb
Host smart-937d1fed-cde4-4c21-8ae1-10f7baa30dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089070607 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2089070607
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1779184978
Short name T734
Test name
Test status
Simulation time 142659674 ps
CPU time 0.85 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 205964 kb
Host smart-0d947454-1d72-4338-a195-cc69146e5776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779184978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1779184978
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2086112778
Short name T825
Test name
Test status
Simulation time 24571049 ps
CPU time 0.86 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 216164 kb
Host smart-9b2ddb0b-af48-46bc-8e94-9a844f3f5c77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086112778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2086112778
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_genbits.1043699569
Short name T669
Test name
Test status
Simulation time 95285611 ps
CPU time 1.17 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 216636 kb
Host smart-2de322f7-354c-45be-92bb-bf4e5b1c0950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043699569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1043699569
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1493641717
Short name T847
Test name
Test status
Simulation time 20441242 ps
CPU time 1.12 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 215144 kb
Host smart-96b3674b-c8f5-43d2-8690-fa4cc72088df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493641717 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1493641717
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.675690365
Short name T416
Test name
Test status
Simulation time 21503140 ps
CPU time 0.95 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 214952 kb
Host smart-90e2e23e-9994-4aaa-8d4f-1229fed2d79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675690365 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.675690365
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4000693645
Short name T679
Test name
Test status
Simulation time 1085166137 ps
CPU time 2.53 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:53 PM PDT 24
Peak memory 216704 kb
Host smart-36ef1dfb-8bdb-4866-8e7e-b816fcebbf46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000693645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4000693645
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.2385784588
Short name T354
Test name
Test status
Simulation time 39873536 ps
CPU time 1.48 seconds
Started May 26 01:16:13 PM PDT 24
Finished May 26 01:16:15 PM PDT 24
Peak memory 217780 kb
Host smart-37618285-a3f8-410d-8285-8f8bcc9594cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385784588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2385784588
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.568231787
Short name T720
Test name
Test status
Simulation time 61952893 ps
CPU time 1.33 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 216880 kb
Host smart-0e4d5c7a-152e-4616-8183-b729ca9d2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568231787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.568231787
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1846818803
Short name T165
Test name
Test status
Simulation time 86749184 ps
CPU time 3.09 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 219276 kb
Host smart-c0beabb0-3884-47b6-b2d1-0bb1ac2cd72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846818803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1846818803
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3470239244
Short name T338
Test name
Test status
Simulation time 109659019 ps
CPU time 1.13 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 216692 kb
Host smart-7bc541b0-cd05-4bac-ae93-3d368a742080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470239244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3470239244
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1283034037
Short name T315
Test name
Test status
Simulation time 72914382 ps
CPU time 1.01 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 216492 kb
Host smart-7a060a26-5fbe-4750-8fa0-1cd2756403b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283034037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1283034037
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.49003093
Short name T542
Test name
Test status
Simulation time 118470078 ps
CPU time 1.02 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 216760 kb
Host smart-352a2ba9-40ec-468e-a70a-915398045fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49003093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.49003093
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3384191982
Short name T740
Test name
Test status
Simulation time 84256678 ps
CPU time 1.49 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 218220 kb
Host smart-b0e1d950-bfff-48ac-9b87-1e71ad477bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384191982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3384191982
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.298258381
Short name T418
Test name
Test status
Simulation time 69187558 ps
CPU time 1.54 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 217864 kb
Host smart-8d7bd67d-99a6-43d8-a876-c037ccc6a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298258381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.298258381
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3007670572
Short name T389
Test name
Test status
Simulation time 78102002 ps
CPU time 1.21 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 216644 kb
Host smart-45ab9ab1-5a99-47a5-9486-18c6399fc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007670572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3007670572
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.4029262101
Short name T130
Test name
Test status
Simulation time 30146126 ps
CPU time 1.22 seconds
Started May 26 01:14:55 PM PDT 24
Finished May 26 01:14:57 PM PDT 24
Peak memory 215228 kb
Host smart-461f3477-cbec-4988-b598-e6e1acf15aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029262101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.4029262101
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.3848478396
Short name T486
Test name
Test status
Simulation time 27912424 ps
CPU time 0.8 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:51 PM PDT 24
Peak memory 205800 kb
Host smart-aab291ca-a95f-473d-b370-ff95eeae27ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848478396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3848478396
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2469900387
Short name T688
Test name
Test status
Simulation time 42374718 ps
CPU time 1.08 seconds
Started May 26 01:14:51 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 216376 kb
Host smart-69bda030-8b87-442a-ad0b-27cb066cfa24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469900387 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2469900387
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2910490185
Short name T119
Test name
Test status
Simulation time 19775755 ps
CPU time 1.11 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 223340 kb
Host smart-8f977122-4b07-4fb6-82ca-f39fe43dba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910490185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2910490185
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.3981793018
Short name T776
Test name
Test status
Simulation time 53610504 ps
CPU time 0.93 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 214848 kb
Host smart-9509aac6-f7f8-4a68-b22a-98af593dcb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981793018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3981793018
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2986883656
Short name T548
Test name
Test status
Simulation time 279906467 ps
CPU time 3.07 seconds
Started May 26 01:14:55 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 214856 kb
Host smart-cd17203e-769e-4927-9e74-e05b6e4eaf16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986883656 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2986883656
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2076727568
Short name T38
Test name
Test status
Simulation time 45973291274 ps
CPU time 1047.68 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:32:21 PM PDT 24
Peak memory 217732 kb
Host smart-3709ce68-40c3-47b0-9f12-44af5fb08da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076727568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2076727568
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.875933135
Short name T585
Test name
Test status
Simulation time 78333142 ps
CPU time 2.76 seconds
Started May 26 01:16:13 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 219352 kb
Host smart-ed03f675-1727-4d86-8253-6bfdf58dd691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875933135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.875933135
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1027222653
Short name T470
Test name
Test status
Simulation time 36898595 ps
CPU time 1.47 seconds
Started May 26 01:16:17 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 217580 kb
Host smart-34efcd11-7b94-44af-aec6-e119bead3c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027222653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1027222653
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2612108504
Short name T538
Test name
Test status
Simulation time 114628011 ps
CPU time 1.4 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 216668 kb
Host smart-6f8d22df-75e2-4d8f-b371-bfd8d305a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612108504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2612108504
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4208966753
Short name T385
Test name
Test status
Simulation time 52635409 ps
CPU time 1.1 seconds
Started May 26 01:16:23 PM PDT 24
Finished May 26 01:16:25 PM PDT 24
Peak memory 219244 kb
Host smart-06beb27b-3f72-40e2-84c0-cbf783a0bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208966753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4208966753
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1846003611
Short name T729
Test name
Test status
Simulation time 54218433 ps
CPU time 1.15 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 218324 kb
Host smart-008aa5ef-5d65-43ed-9da0-c046e7ece494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846003611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1846003611
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1055883187
Short name T783
Test name
Test status
Simulation time 45010580 ps
CPU time 1.14 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 216536 kb
Host smart-d05f0f09-a8a3-4e8e-9885-6fb72b48ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055883187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1055883187
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1082455696
Short name T492
Test name
Test status
Simulation time 51499354 ps
CPU time 1.32 seconds
Started May 26 01:16:12 PM PDT 24
Finished May 26 01:16:14 PM PDT 24
Peak memory 216560 kb
Host smart-2f2d7bb2-2846-46ae-877a-b12fd34c4176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082455696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1082455696
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.662929501
Short name T661
Test name
Test status
Simulation time 150302844 ps
CPU time 2.83 seconds
Started May 26 01:16:20 PM PDT 24
Finished May 26 01:16:25 PM PDT 24
Peak memory 219428 kb
Host smart-9afb31e4-7991-43e6-9a17-94198c967bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662929501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.662929501
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.1150604678
Short name T802
Test name
Test status
Simulation time 33346310 ps
CPU time 0.9 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 206268 kb
Host smart-e3d0dce7-e778-4961-b2ec-f9b5eee84da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150604678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1150604678
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2413694613
Short name T700
Test name
Test status
Simulation time 30610793 ps
CPU time 0.86 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 215056 kb
Host smart-76e2124f-d538-458d-a456-f9796fbf37fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413694613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2413694613
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3614240998
Short name T187
Test name
Test status
Simulation time 29767341 ps
CPU time 1.22 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 219076 kb
Host smart-ef5c6476-d602-4444-aca1-2f0d5a29c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614240998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3614240998
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.2977919497
Short name T759
Test name
Test status
Simulation time 32004573 ps
CPU time 0.99 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 223444 kb
Host smart-cd16f257-928e-49fa-aae1-c40fefc8af52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977919497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2977919497
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3299980891
Short name T457
Test name
Test status
Simulation time 43978726 ps
CPU time 0.99 seconds
Started May 26 01:14:50 PM PDT 24
Finished May 26 01:14:52 PM PDT 24
Peak memory 214848 kb
Host smart-751a5fdd-4b84-4251-b21e-2729de9979cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299980891 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3299980891
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.748445579
Short name T623
Test name
Test status
Simulation time 491025026 ps
CPU time 5.09 seconds
Started May 26 01:14:56 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 216704 kb
Host smart-d0f57ac4-4ea4-4852-a6ee-0846d778b1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748445579 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.748445579
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4145615501
Short name T823
Test name
Test status
Simulation time 69264420513 ps
CPU time 1117.61 seconds
Started May 26 01:14:51 PM PDT 24
Finished May 26 01:33:30 PM PDT 24
Peak memory 220124 kb
Host smart-4af73714-71b6-4e40-80cd-0f856d82ddad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145615501 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4145615501
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1582499877
Short name T357
Test name
Test status
Simulation time 97066253 ps
CPU time 1.04 seconds
Started May 26 01:16:20 PM PDT 24
Finished May 26 01:16:23 PM PDT 24
Peak memory 216672 kb
Host smart-d5d7a231-24c9-4157-b707-a2a0444d5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582499877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1582499877
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.290509581
Short name T373
Test name
Test status
Simulation time 53728791 ps
CPU time 1.02 seconds
Started May 26 01:16:17 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 219276 kb
Host smart-f8ff9a16-ab82-4712-beec-64d266109031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290509581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.290509581
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1901773409
Short name T782
Test name
Test status
Simulation time 46326600 ps
CPU time 1.16 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:17 PM PDT 24
Peak memory 216464 kb
Host smart-ea9411da-d6b5-4114-b270-511bd94c53e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901773409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1901773409
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.4102657155
Short name T686
Test name
Test status
Simulation time 249588259 ps
CPU time 1.82 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 217068 kb
Host smart-c5c42966-d391-42af-96a6-2a770e54f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102657155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.4102657155
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.68121919
Short name T383
Test name
Test status
Simulation time 30583538 ps
CPU time 1.18 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:17 PM PDT 24
Peak memory 216336 kb
Host smart-95320427-66ee-42b5-9366-2360e6806fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68121919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.68121919
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1035281791
Short name T79
Test name
Test status
Simulation time 49623032 ps
CPU time 1.2 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 217756 kb
Host smart-e5078bcd-4731-426a-b653-74a8e47da3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035281791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1035281791
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3488191569
Short name T530
Test name
Test status
Simulation time 66119732 ps
CPU time 1.66 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 218360 kb
Host smart-0e6de789-88ed-408e-8867-1e1a18db77e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488191569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3488191569
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2238171501
Short name T765
Test name
Test status
Simulation time 40173981 ps
CPU time 1.13 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 216680 kb
Host smart-89b3df09-7ace-46fc-9a99-ba15cb6d1c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238171501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2238171501
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2633961800
Short name T659
Test name
Test status
Simulation time 68297566 ps
CPU time 1.54 seconds
Started May 26 01:16:20 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 218004 kb
Host smart-c3df3385-84b1-4f63-9673-5d8684359ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633961800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2633961800
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2349821531
Short name T265
Test name
Test status
Simulation time 82536981 ps
CPU time 1.27 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 215344 kb
Host smart-3585a089-8265-43cf-90f3-bd3f106bc0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349821531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2349821531
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.4045269003
Short name T656
Test name
Test status
Simulation time 25383891 ps
CPU time 0.92 seconds
Started May 26 01:14:53 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 206292 kb
Host smart-beaf876a-baf1-4251-b2aa-b85ea24cb867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045269003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4045269003
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.1817805653
Short name T737
Test name
Test status
Simulation time 30378515 ps
CPU time 1.36 seconds
Started May 26 01:14:57 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 224928 kb
Host smart-eca701e0-b36a-4c06-ba96-0d825f1287ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817805653 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1817805653
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1303943257
Short name T499
Test name
Test status
Simulation time 92193766 ps
CPU time 1.21 seconds
Started May 26 01:14:51 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 216580 kb
Host smart-411e1f5e-f422-4268-a3cc-ad0c172f7ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303943257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1303943257
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2105590708
Short name T308
Test name
Test status
Simulation time 25219393 ps
CPU time 0.95 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:55 PM PDT 24
Peak memory 214952 kb
Host smart-9e940836-a02f-4f87-91ba-b05212a22f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105590708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2105590708
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1958424901
Short name T163
Test name
Test status
Simulation time 466132133 ps
CPU time 3.31 seconds
Started May 26 01:14:55 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 216560 kb
Host smart-50cd5193-ef6c-4cda-be02-f398a3ac0e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958424901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1958424901
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.299973893
Short name T514
Test name
Test status
Simulation time 38388309529 ps
CPU time 435.09 seconds
Started May 26 01:14:58 PM PDT 24
Finished May 26 01:22:14 PM PDT 24
Peak memory 218552 kb
Host smart-9ef5c367-20f4-4bf3-bc65-742f390313dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299973893 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.299973893
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2507803198
Short name T753
Test name
Test status
Simulation time 26154698 ps
CPU time 1.18 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 216656 kb
Host smart-c4ea83a7-f6d1-4e25-bc8a-c08c6c3aadaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507803198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2507803198
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2911119990
Short name T300
Test name
Test status
Simulation time 67373983 ps
CPU time 1.86 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 218672 kb
Host smart-1d298dea-126f-449c-b82c-e5cbccc4009e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911119990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2911119990
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2557885081
Short name T502
Test name
Test status
Simulation time 34889072 ps
CPU time 1.3 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 216580 kb
Host smart-7d3f9c38-7591-4829-8616-94fd6f23cfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557885081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2557885081
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1511709935
Short name T417
Test name
Test status
Simulation time 67161067 ps
CPU time 1.08 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:17 PM PDT 24
Peak memory 216728 kb
Host smart-da7ab5f7-1b80-43d9-9569-1dcecb7d4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511709935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1511709935
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.934028927
Short name T501
Test name
Test status
Simulation time 39507383 ps
CPU time 1.16 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 216604 kb
Host smart-d8d2e9c7-9fe4-4ad3-8603-ca1528d57fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934028927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.934028927
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3687500748
Short name T403
Test name
Test status
Simulation time 119173111 ps
CPU time 1.46 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 219348 kb
Host smart-f6671f62-ce02-415b-93c0-a3ce30edbf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687500748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3687500748
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.661024594
Short name T503
Test name
Test status
Simulation time 240898226 ps
CPU time 1.44 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:22 PM PDT 24
Peak memory 218256 kb
Host smart-652a9e90-3436-454a-855d-31cc49e6179b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661024594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.661024594
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3414615497
Short name T568
Test name
Test status
Simulation time 54551093 ps
CPU time 1.47 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 218040 kb
Host smart-72ee123b-2727-4d57-a59a-8bc4e704ae55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414615497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3414615497
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.608719704
Short name T716
Test name
Test status
Simulation time 36851553 ps
CPU time 1.58 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 217624 kb
Host smart-3b3c393e-56f5-4c64-8518-c423a6e3f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608719704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.608719704
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3816580530
Short name T379
Test name
Test status
Simulation time 232550064 ps
CPU time 3.34 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 216948 kb
Host smart-33cccbe4-f7e8-4ec3-afc4-23895790723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816580530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3816580530
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2809139772
Short name T28
Test name
Test status
Simulation time 104380311 ps
CPU time 1.27 seconds
Started May 26 01:14:54 PM PDT 24
Finished May 26 01:14:56 PM PDT 24
Peak memory 215348 kb
Host smart-6f53dcdc-6358-4e54-bbf6-e054fb512143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809139772 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2809139772
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1819424594
Short name T742
Test name
Test status
Simulation time 52768504 ps
CPU time 1.42 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 206364 kb
Host smart-dc78bf76-1fb2-4128-9016-f753ef3d8a72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819424594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1819424594
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3334154521
Short name T717
Test name
Test status
Simulation time 45386540 ps
CPU time 0.89 seconds
Started May 26 01:14:57 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 215556 kb
Host smart-e8b770cf-c5f7-49f3-b8ca-3c4143856df9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334154521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3334154521
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3633802698
Short name T663
Test name
Test status
Simulation time 140540936 ps
CPU time 1.12 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:54 PM PDT 24
Peak memory 216528 kb
Host smart-b7ca2b69-72d2-4be8-b3f5-cb50eb9a7f4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633802698 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3633802698
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1413918583
Short name T407
Test name
Test status
Simulation time 68555511 ps
CPU time 0.97 seconds
Started May 26 01:14:57 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 219188 kb
Host smart-413aa99a-249c-4969-b522-f9e97e1d507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413918583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1413918583
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.1374290413
Short name T573
Test name
Test status
Simulation time 53711985 ps
CPU time 0.88 seconds
Started May 26 01:14:58 PM PDT 24
Finished May 26 01:15:00 PM PDT 24
Peak memory 215024 kb
Host smart-48d91e12-c0f9-47b2-8204-ac85262548cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374290413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1374290413
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1356922495
Short name T67
Test name
Test status
Simulation time 38037708 ps
CPU time 0.89 seconds
Started May 26 01:14:58 PM PDT 24
Finished May 26 01:14:59 PM PDT 24
Peak memory 214872 kb
Host smart-5f26b172-c2fa-4578-b4ed-f9170235e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356922495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1356922495
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2779511385
Short name T72
Test name
Test status
Simulation time 346613367 ps
CPU time 4.11 seconds
Started May 26 01:14:52 PM PDT 24
Finished May 26 01:14:57 PM PDT 24
Peak memory 218980 kb
Host smart-a578277a-8bd1-49e6-a901-59130a604bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779511385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2779511385
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1377742579
Short name T211
Test name
Test status
Simulation time 44738248515 ps
CPU time 1017.29 seconds
Started May 26 01:14:51 PM PDT 24
Finished May 26 01:31:49 PM PDT 24
Peak memory 217624 kb
Host smart-ba3d67a7-a03b-4d7c-b6e2-ef668a87587e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377742579 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1377742579
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.552938003
Short name T835
Test name
Test status
Simulation time 64069974 ps
CPU time 1.59 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 218024 kb
Host smart-0bb05a69-6d8a-4b04-bb6a-1a9cd6f6d7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552938003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.552938003
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1080760757
Short name T537
Test name
Test status
Simulation time 143634791 ps
CPU time 1.08 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 214948 kb
Host smart-ea34ba96-27ed-4b81-8357-8abc8443e98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080760757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1080760757
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3120778176
Short name T430
Test name
Test status
Simulation time 97896949 ps
CPU time 1.6 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 218312 kb
Host smart-439bf31d-a5ae-4a47-bf1f-50f1a2591f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120778176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3120778176
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2257529206
Short name T297
Test name
Test status
Simulation time 50838124 ps
CPU time 1.65 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 219364 kb
Host smart-76ac3fb8-2170-43af-b3ea-e0c053ac376d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257529206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2257529206
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1088331274
Short name T52
Test name
Test status
Simulation time 32155838 ps
CPU time 1.33 seconds
Started May 26 01:16:17 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 216856 kb
Host smart-d4165166-66eb-476e-a857-a93bd7f40f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088331274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1088331274
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1870036842
Short name T512
Test name
Test status
Simulation time 214329239 ps
CPU time 1.3 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 218200 kb
Host smart-945284a8-b6b7-48aa-9f2e-58bcb0b3725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870036842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1870036842
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2959230022
Short name T284
Test name
Test status
Simulation time 106971190 ps
CPU time 1.16 seconds
Started May 26 01:16:19 PM PDT 24
Finished May 26 01:16:22 PM PDT 24
Peak memory 218340 kb
Host smart-e9ab361b-b072-4be7-888f-cd783b70097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959230022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2959230022
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1411690510
Short name T544
Test name
Test status
Simulation time 40481230 ps
CPU time 1.47 seconds
Started May 26 01:16:14 PM PDT 24
Finished May 26 01:16:16 PM PDT 24
Peak memory 217780 kb
Host smart-fc3d368b-d421-4679-be81-4be0b650caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411690510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1411690510
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2417892643
Short name T658
Test name
Test status
Simulation time 104855104 ps
CPU time 1.71 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 219532 kb
Host smart-f7de6325-1e0b-4c36-b01a-8a31a42b9dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417892643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2417892643
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.316435894
Short name T785
Test name
Test status
Simulation time 47506490 ps
CPU time 0.96 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 214464 kb
Host smart-a8967a65-5918-4fbd-a217-ed93c8260cb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316435894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.316435894
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1582539119
Short name T775
Test name
Test status
Simulation time 22900217 ps
CPU time 0.97 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:04 PM PDT 24
Peak memory 215384 kb
Host smart-2c49d36e-ab3d-4758-9f93-7d3c8fa48fe0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582539119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1582539119
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3736141577
Short name T655
Test name
Test status
Simulation time 84160059 ps
CPU time 1.07 seconds
Started May 26 01:15:06 PM PDT 24
Finished May 26 01:15:08 PM PDT 24
Peak memory 217968 kb
Host smart-dc24684d-56b8-4263-b255-7699053e61da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736141577 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3736141577
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.1706719708
Short name T778
Test name
Test status
Simulation time 18635838 ps
CPU time 1.05 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:03 PM PDT 24
Peak memory 217916 kb
Host smart-1b8b24b5-5736-4c2f-a18e-082470969916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706719708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.1706719708
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1090476791
Short name T19
Test name
Test status
Simulation time 101151344 ps
CPU time 2.14 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 218768 kb
Host smart-1b366224-568b-454c-8c91-882ffc572b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090476791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1090476791
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.750356822
Short name T431
Test name
Test status
Simulation time 25039534 ps
CPU time 1.19 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 223532 kb
Host smart-54a53ae1-569d-4a09-a2e8-96c4b9f3acc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750356822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.750356822
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.46321298
Short name T487
Test name
Test status
Simulation time 41081957 ps
CPU time 0.92 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 214912 kb
Host smart-20db3114-8ff8-4a93-9b0d-3e7c8ab2686a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46321298 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.46321298
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2608178285
Short name T723
Test name
Test status
Simulation time 84529473 ps
CPU time 2.3 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:03 PM PDT 24
Peak memory 216460 kb
Host smart-4d38a986-ec07-47fc-bbca-a5b69255293e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608178285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2608178285
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.3077042354
Short name T27
Test name
Test status
Simulation time 48663798 ps
CPU time 1.3 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 217932 kb
Host smart-bb8c1b86-86bc-4392-a2b1-39243f181e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077042354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3077042354
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.479772308
Short name T824
Test name
Test status
Simulation time 60639522 ps
CPU time 1.56 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 219548 kb
Host smart-dc4baabb-6e0f-49e3-b809-3434e6df5dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479772308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.479772308
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.362955332
Short name T392
Test name
Test status
Simulation time 36586741 ps
CPU time 1.45 seconds
Started May 26 01:16:23 PM PDT 24
Finished May 26 01:16:26 PM PDT 24
Peak memory 216804 kb
Host smart-188a6efd-a4bb-4177-833d-e6b379406eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362955332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.362955332
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3230234050
Short name T474
Test name
Test status
Simulation time 52480946 ps
CPU time 1.5 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:22 PM PDT 24
Peak memory 217940 kb
Host smart-1b1e897d-266d-4c0b-9cd3-339dfaa63592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230234050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3230234050
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3459291464
Short name T781
Test name
Test status
Simulation time 83204254 ps
CPU time 1.3 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 216564 kb
Host smart-691e7215-a958-4708-9178-57380529d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459291464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3459291464
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1036348619
Short name T298
Test name
Test status
Simulation time 67796875 ps
CPU time 1.32 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 217760 kb
Host smart-15e564e7-6a40-49a1-89f0-99e48bba5f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036348619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1036348619
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4247823805
Short name T66
Test name
Test status
Simulation time 219197136 ps
CPU time 2.76 seconds
Started May 26 01:16:19 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 216792 kb
Host smart-cf7d3b1d-13bf-4e28-9552-25337e5d871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247823805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4247823805
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1255228642
Short name T324
Test name
Test status
Simulation time 37634601 ps
CPU time 1.47 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 217700 kb
Host smart-3b937977-2622-4ff4-b9ae-ab0ee17fa08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255228642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1255228642
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.238731256
Short name T11
Test name
Test status
Simulation time 268055195 ps
CPU time 1.38 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 219460 kb
Host smart-6eafeddc-5e2c-4b7b-9661-6af118abfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238731256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.238731256
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2324394343
Short name T274
Test name
Test status
Simulation time 48602368 ps
CPU time 1.92 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 217976 kb
Host smart-4694e2b8-eb50-460c-b237-2f6aae53e73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324394343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2324394343
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2985755998
Short name T578
Test name
Test status
Simulation time 100567447 ps
CPU time 1.32 seconds
Started May 26 01:15:05 PM PDT 24
Finished May 26 01:15:08 PM PDT 24
Peak memory 215260 kb
Host smart-b464732c-103f-4d9d-b5ef-46aeea8ee8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985755998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2985755998
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.959137613
Short name T810
Test name
Test status
Simulation time 21219394 ps
CPU time 0.87 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 206092 kb
Host smart-d1ac48e2-cb9d-48f0-b156-23a8bc3a2174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959137613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.959137613
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1549503722
Short name T145
Test name
Test status
Simulation time 11570960 ps
CPU time 0.89 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 216020 kb
Host smart-24bdbb95-fa0d-4b92-a589-6ba94066c2a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549503722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1549503722
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1727054932
Short name T722
Test name
Test status
Simulation time 74276397 ps
CPU time 1.02 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 219144 kb
Host smart-25e376e7-4b1e-479f-a020-12c8592948f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727054932 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1727054932
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1383644721
Short name T786
Test name
Test status
Simulation time 87145328 ps
CPU time 1.27 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 225348 kb
Host smart-82909658-e405-4675-b9d2-58e19630e7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383644721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1383644721
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3689138920
Short name T449
Test name
Test status
Simulation time 110769173 ps
CPU time 1.33 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:04 PM PDT 24
Peak memory 218060 kb
Host smart-b303e355-3788-42a1-aa01-4c5cb7d59512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689138920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3689138920
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.390728110
Short name T650
Test name
Test status
Simulation time 60895270 ps
CPU time 0.95 seconds
Started May 26 01:15:07 PM PDT 24
Finished May 26 01:15:08 PM PDT 24
Peak memory 223304 kb
Host smart-19cf3112-d02e-4037-8af5-6894579b90ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390728110 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.390728110
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2271061920
Short name T423
Test name
Test status
Simulation time 54855194 ps
CPU time 0.94 seconds
Started May 26 01:15:00 PM PDT 24
Finished May 26 01:15:01 PM PDT 24
Peak memory 214828 kb
Host smart-8e2de497-648f-407e-903f-ab44c35705ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271061920 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2271061920
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.210502138
Short name T668
Test name
Test status
Simulation time 418696520 ps
CPU time 2.87 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 214848 kb
Host smart-f71a6bc0-806f-4e05-95f6-1e7dbc444f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210502138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.210502138
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.350698456
Short name T460
Test name
Test status
Simulation time 110092368305 ps
CPU time 735 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:27:20 PM PDT 24
Peak memory 220440 kb
Host smart-fc8b428c-c17c-4ae4-8e1a-663eb9dc9efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350698456 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.350698456
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1593221145
Short name T358
Test name
Test status
Simulation time 47998159 ps
CPU time 1.52 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 217740 kb
Host smart-df3f1525-5373-4d0b-bcfd-6466275b9361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593221145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1593221145
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4245901614
Short name T371
Test name
Test status
Simulation time 50379132 ps
CPU time 1.34 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 218020 kb
Host smart-bf46937d-a6bf-4a99-a0a4-67e02165be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245901614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4245901614
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1403486558
Short name T540
Test name
Test status
Simulation time 90828463 ps
CPU time 2.28 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 219496 kb
Host smart-92471bef-be23-4706-b2d0-329dc4ebe76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403486558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1403486558
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1416118324
Short name T745
Test name
Test status
Simulation time 70265874 ps
CPU time 1.01 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 216644 kb
Host smart-05773ca4-a573-415b-a59c-345bd51e2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416118324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1416118324
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1131364940
Short name T40
Test name
Test status
Simulation time 30085667 ps
CPU time 1.52 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 216720 kb
Host smart-ed0c5172-c20c-4226-9216-5868fd6f16ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131364940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1131364940
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.888240961
Short name T321
Test name
Test status
Simulation time 36650579 ps
CPU time 1.1 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:32 PM PDT 24
Peak memory 216704 kb
Host smart-a91bdbf0-b015-48e8-a4d3-8d23b1b0ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888240961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.888240961
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3914432559
Short name T427
Test name
Test status
Simulation time 39682036 ps
CPU time 1.49 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 218020 kb
Host smart-6ec8799f-259a-4853-8aa2-5e3b950df706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914432559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3914432559
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2439504714
Short name T327
Test name
Test status
Simulation time 180723169 ps
CPU time 1.24 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 218056 kb
Host smart-4268a38e-5c8b-44ae-a26e-21c91f7ccb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439504714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2439504714
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3858348642
Short name T467
Test name
Test status
Simulation time 52595433 ps
CPU time 1.61 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 217920 kb
Host smart-48ab5bcd-7e80-4063-bf7b-ea0b30c1819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858348642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3858348642
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.863777719
Short name T587
Test name
Test status
Simulation time 50220285 ps
CPU time 1.31 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:07 PM PDT 24
Peak memory 215240 kb
Host smart-f31981ad-a664-4f47-8a6b-5dcfd04d39d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863777719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.863777719
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3703624516
Short name T620
Test name
Test status
Simulation time 37413121 ps
CPU time 0.99 seconds
Started May 26 01:15:10 PM PDT 24
Finished May 26 01:15:12 PM PDT 24
Peak memory 206280 kb
Host smart-4b0f7987-433b-4e5a-a91d-aabc26192215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703624516 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3703624516
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1777524954
Short name T632
Test name
Test status
Simulation time 34568594 ps
CPU time 0.85 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 214968 kb
Host smart-3a8237da-1ba4-450e-8afa-de084af54dd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777524954 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1777524954
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3844395868
Short name T699
Test name
Test status
Simulation time 48834796 ps
CPU time 1.5 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 216456 kb
Host smart-be2275d3-f7c1-443a-b82b-38277632db8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844395868 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3844395868
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_genbits.1632424671
Short name T301
Test name
Test status
Simulation time 113050945 ps
CPU time 1.14 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:02 PM PDT 24
Peak memory 216656 kb
Host smart-23e86342-e9a3-4f8a-b34b-7c126658e097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632424671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1632424671
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_smoke.1000107372
Short name T524
Test name
Test status
Simulation time 23825158 ps
CPU time 0.93 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 214916 kb
Host smart-6b65e42b-f489-4e37-ae13-e387a9e3f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000107372 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1000107372
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3740351007
Short name T442
Test name
Test status
Simulation time 329787252 ps
CPU time 6.19 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:10 PM PDT 24
Peak memory 216464 kb
Host smart-f93266fe-e080-455c-be09-8049c391a386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740351007 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3740351007
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2237842850
Short name T210
Test name
Test status
Simulation time 205457976504 ps
CPU time 1175.64 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:34:41 PM PDT 24
Peak memory 220976 kb
Host smart-ef3eb31b-c1dc-4f33-b4e6-599c97a680b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237842850 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2237842850
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.2494809700
Short name T603
Test name
Test status
Simulation time 88983175 ps
CPU time 1.15 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 218572 kb
Host smart-f770a308-0391-4f2a-937d-90625e6f31e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494809700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2494809700
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2310088941
Short name T657
Test name
Test status
Simulation time 45096560 ps
CPU time 1.57 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:33 PM PDT 24
Peak memory 216816 kb
Host smart-56ba37a7-9d6d-411c-bc27-cb43c2bebdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310088941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2310088941
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3277335289
Short name T411
Test name
Test status
Simulation time 36792964 ps
CPU time 1.32 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 217804 kb
Host smart-1862aa07-4616-413c-86fd-1bcb873f518e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277335289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3277335289
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2689573507
Short name T735
Test name
Test status
Simulation time 116386162 ps
CPU time 1.79 seconds
Started May 26 01:16:31 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 218036 kb
Host smart-cea7dcf3-7d01-4402-a556-088b2593b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689573507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2689573507
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2396537070
Short name T283
Test name
Test status
Simulation time 95522323 ps
CPU time 1.43 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 218016 kb
Host smart-8c672109-c792-42b7-87f3-7714a0e7f0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396537070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2396537070
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2395139060
Short name T325
Test name
Test status
Simulation time 87048602 ps
CPU time 1.08 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 216588 kb
Host smart-689857f7-0c33-459d-9893-6c7f61dcb786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395139060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2395139060
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.4014308761
Short name T628
Test name
Test status
Simulation time 49607905 ps
CPU time 1.61 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 217844 kb
Host smart-722816bf-8f7c-4bba-98c6-97e0845bade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014308761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4014308761
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1027864360
Short name T276
Test name
Test status
Simulation time 48535718 ps
CPU time 1.2 seconds
Started May 26 01:16:23 PM PDT 24
Finished May 26 01:16:26 PM PDT 24
Peak memory 218760 kb
Host smart-43e450d3-a325-413a-924d-6fc6903381f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027864360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1027864360
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.836713451
Short name T584
Test name
Test status
Simulation time 155107530 ps
CPU time 1.19 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 216756 kb
Host smart-c5211547-c5c3-4343-a157-ecb4f29741ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836713451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.836713451
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1114121130
Short name T495
Test name
Test status
Simulation time 51794123 ps
CPU time 1.51 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 218072 kb
Host smart-4c4abc47-858d-4882-bee1-df474821cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114121130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1114121130
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.970186198
Short name T337
Test name
Test status
Simulation time 43471372 ps
CPU time 0.93 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 214480 kb
Host smart-e13e4514-32e5-45b7-b2c4-206154bb886d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970186198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.970186198
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3786070063
Short name T135
Test name
Test status
Simulation time 18183762 ps
CPU time 0.96 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 216196 kb
Host smart-b74d2d5c-08bd-4240-92e4-15dea048e136
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786070063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3786070063
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.677637995
Short name T731
Test name
Test status
Simulation time 88798153 ps
CPU time 1.08 seconds
Started May 26 01:15:06 PM PDT 24
Finished May 26 01:15:08 PM PDT 24
Peak memory 216440 kb
Host smart-931f04da-3466-4529-ab73-d9ed13c5e6f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677637995 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.677637995
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2674416276
Short name T309
Test name
Test status
Simulation time 22707353 ps
CPU time 0.92 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 218048 kb
Host smart-eac1e09b-8b81-41c6-a985-2111b9c952e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674416276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2674416276
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2667895169
Short name T724
Test name
Test status
Simulation time 73335650 ps
CPU time 1.58 seconds
Started May 26 01:15:02 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 218032 kb
Host smart-c53a3ede-ecfc-47a4-8045-0febfb73f196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667895169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2667895169
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2064602612
Short name T347
Test name
Test status
Simulation time 68106032 ps
CPU time 0.93 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 214868 kb
Host smart-cd233df9-fbaf-43cc-9f22-7f81e3861eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064602612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2064602612
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.638472682
Short name T306
Test name
Test status
Simulation time 15634120 ps
CPU time 1 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 206652 kb
Host smart-a585f414-6058-4f37-b525-0ac0157beebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638472682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.638472682
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2698839633
Short name T433
Test name
Test status
Simulation time 284744912 ps
CPU time 3.48 seconds
Started May 26 01:15:01 PM PDT 24
Finished May 26 01:15:06 PM PDT 24
Peak memory 216596 kb
Host smart-23a31b5c-1ace-4e63-90de-09bada20db36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698839633 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2698839633
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1206057031
Short name T728
Test name
Test status
Simulation time 45031842319 ps
CPU time 1213.91 seconds
Started May 26 01:15:05 PM PDT 24
Finished May 26 01:35:20 PM PDT 24
Peak memory 221216 kb
Host smart-786d5840-0a28-423e-9f30-164144f3b617
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206057031 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1206057031
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.323979
Short name T346
Test name
Test status
Simulation time 24844644 ps
CPU time 1.21 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 216948 kb
Host smart-e0e46361-f860-467a-9226-68de04f78a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.323979
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.894895515
Short name T216
Test name
Test status
Simulation time 288735749 ps
CPU time 1.05 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 216716 kb
Host smart-ff92654f-4d1b-4b83-b9a3-712d6363bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894895515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.894895515
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1517732249
Short name T48
Test name
Test status
Simulation time 259661097 ps
CPU time 3.4 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 218224 kb
Host smart-3abc6c67-7bab-45ad-b89a-2b3c2bb99d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517732249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1517732249
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.701941177
Short name T370
Test name
Test status
Simulation time 56882199 ps
CPU time 1.69 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 218032 kb
Host smart-8a078fdd-ef93-420e-8601-a86140c676c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701941177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.701941177
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2576735008
Short name T49
Test name
Test status
Simulation time 383529733 ps
CPU time 2.29 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:33 PM PDT 24
Peak memory 218068 kb
Host smart-1caeb86a-aa85-4a56-a8c4-1573e7ed69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576735008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2576735008
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3436354837
Short name T215
Test name
Test status
Simulation time 40847073 ps
CPU time 1.51 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 216608 kb
Host smart-7023dab4-69c1-4ed5-96ed-3453ebd68491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436354837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3436354837
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1373294428
Short name T741
Test name
Test status
Simulation time 37934997 ps
CPU time 1.08 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 216660 kb
Host smart-cbbf2082-6267-4a2b-82a7-c87bd1e914d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373294428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1373294428
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2150578361
Short name T359
Test name
Test status
Simulation time 30180791 ps
CPU time 1.31 seconds
Started May 26 01:16:31 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 219104 kb
Host smart-19ddcd67-0512-45cb-8f73-93bf393edc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150578361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2150578361
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3371172397
Short name T534
Test name
Test status
Simulation time 171941828 ps
CPU time 1.15 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 216656 kb
Host smart-c2efbf8d-2dcc-4cb0-84b4-dcccdb62ad0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371172397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3371172397
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.156230038
Short name T505
Test name
Test status
Simulation time 33589314 ps
CPU time 1.32 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 217844 kb
Host smart-53dfd07c-1d3a-47e2-93a8-ee26d70d0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156230038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.156230038
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.2812851772
Short name T387
Test name
Test status
Simulation time 35357843 ps
CPU time 0.97 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:16 PM PDT 24
Peak memory 214340 kb
Host smart-0ea921df-6e2e-4948-a64c-dbea7d609a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812851772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2812851772
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1407258816
Short name T779
Test name
Test status
Simulation time 19235873 ps
CPU time 0.89 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 215492 kb
Host smart-a87c197b-e9a5-4a7f-9763-9ddec5992584
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407258816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1407258816
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1024706695
Short name T55
Test name
Test status
Simulation time 26250120 ps
CPU time 1.1 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:18 PM PDT 24
Peak memory 223484 kb
Host smart-49507875-db2f-4119-ae89-ef2a10c27f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024706695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1024706695
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2880579607
Short name T532
Test name
Test status
Simulation time 50510573 ps
CPU time 1.89 seconds
Started May 26 01:15:05 PM PDT 24
Finished May 26 01:15:08 PM PDT 24
Peak memory 217772 kb
Host smart-06fdf847-4e0a-4d73-a2b1-2055c2536250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880579607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2880579607
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3994605742
Short name T761
Test name
Test status
Simulation time 23133062 ps
CPU time 1.12 seconds
Started May 26 01:15:04 PM PDT 24
Finished May 26 01:15:07 PM PDT 24
Peak memory 214844 kb
Host smart-72fe26c1-8081-4368-8abd-09ef5a240b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994605742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3994605742
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2448044023
Short name T818
Test name
Test status
Simulation time 15293723 ps
CPU time 1.05 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:05 PM PDT 24
Peak memory 214964 kb
Host smart-81ec4831-ab35-4460-bac0-a437c89f064e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448044023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2448044023
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.451322807
Short name T667
Test name
Test status
Simulation time 243794117 ps
CPU time 4.34 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:15:09 PM PDT 24
Peak memory 216632 kb
Host smart-45e71808-c1a0-4ebd-9a18-82979a9d5535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451322807 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.451322807
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2138329479
Short name T774
Test name
Test status
Simulation time 38715688413 ps
CPU time 981.23 seconds
Started May 26 01:15:03 PM PDT 24
Finished May 26 01:31:26 PM PDT 24
Peak memory 223260 kb
Host smart-b5288984-e495-4053-9fb8-efa3ae5897c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138329479 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2138329479
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1774310012
Short name T682
Test name
Test status
Simulation time 51518999 ps
CPU time 1.55 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:33 PM PDT 24
Peak memory 217964 kb
Host smart-8819ff87-b7cd-4689-b72c-327c2c982d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774310012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1774310012
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.888830890
Short name T39
Test name
Test status
Simulation time 52020450 ps
CPU time 1.71 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 219628 kb
Host smart-ed2d059d-39da-440d-90b4-0499509b5512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888830890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.888830890
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4156090150
Short name T694
Test name
Test status
Simulation time 91340450 ps
CPU time 1.36 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 217820 kb
Host smart-50499257-7409-4ce0-a890-a9b96aa59332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156090150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4156090150
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3023609439
Short name T90
Test name
Test status
Simulation time 206675551 ps
CPU time 1.42 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 217876 kb
Host smart-7f03267a-58b9-406b-8301-b48d7c2eb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023609439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3023609439
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1769051258
Short name T674
Test name
Test status
Simulation time 36730797 ps
CPU time 1.48 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 218004 kb
Host smart-54288c1c-f40a-419e-aedc-d20a2e24dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769051258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1769051258
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2498331671
Short name T547
Test name
Test status
Simulation time 50420566 ps
CPU time 1.62 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 217852 kb
Host smart-527634aa-3aae-448c-a98f-44e0d682fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498331671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2498331671
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3985182376
Short name T405
Test name
Test status
Simulation time 66540688 ps
CPU time 1.64 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 217912 kb
Host smart-1a74da8a-1242-4a08-90c3-b814008bcb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985182376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3985182376
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1082364059
Short name T762
Test name
Test status
Simulation time 195276638 ps
CPU time 1.73 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 218392 kb
Host smart-146c8425-3b5f-4d9f-b1eb-6edd71089b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082364059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1082364059
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2739155063
Short name T468
Test name
Test status
Simulation time 56851762 ps
CPU time 1.34 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 216844 kb
Host smart-9f135fc1-a8a9-421f-b8f0-68063263469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739155063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2739155063
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.977511445
Short name T196
Test name
Test status
Simulation time 25851322 ps
CPU time 1.21 seconds
Started May 26 01:14:36 PM PDT 24
Finished May 26 01:14:38 PM PDT 24
Peak memory 215320 kb
Host smart-7319e226-1595-4f0f-99e4-0006e94808aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977511445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.977511445
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_disable.750387333
Short name T635
Test name
Test status
Simulation time 37857036 ps
CPU time 0.83 seconds
Started May 26 01:14:34 PM PDT 24
Finished May 26 01:14:36 PM PDT 24
Peak memory 215672 kb
Host smart-54b515a1-cfd7-44da-bbe6-7bc4f3fa2c53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750387333 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.750387333
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.176573162
Short name T114
Test name
Test status
Simulation time 26566302 ps
CPU time 1.05 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:32 PM PDT 24
Peak memory 219236 kb
Host smart-00e1938b-f573-4e37-aa0e-0c8aa402b334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176573162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.176573162
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.40010172
Short name T654
Test name
Test status
Simulation time 242028328 ps
CPU time 2.79 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:26 PM PDT 24
Peak memory 219364 kb
Host smart-b2d79fcb-631e-4e9c-b6d9-2703f74a0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40010172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.40010172
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4073123484
Short name T33
Test name
Test status
Simulation time 21286250 ps
CPU time 1.07 seconds
Started May 26 01:14:20 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 215420 kb
Host smart-31916f7b-d9ef-44ec-8424-7cd49bfa14c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073123484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4073123484
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3800215622
Short name T13
Test name
Test status
Simulation time 6093799043 ps
CPU time 7.29 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:37 PM PDT 24
Peak memory 237788 kb
Host smart-1258a62f-c336-4a30-b9ca-7b8dd7cfd2b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800215622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3800215622
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3970971258
Short name T60
Test name
Test status
Simulation time 34283809 ps
CPU time 0.92 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:24 PM PDT 24
Peak memory 214924 kb
Host smart-32598c1f-71aa-414b-8694-068c96b9d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970971258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3970971258
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2109952496
Short name T645
Test name
Test status
Simulation time 151692312 ps
CPU time 2.09 seconds
Started May 26 01:14:21 PM PDT 24
Finished May 26 01:14:25 PM PDT 24
Peak memory 217888 kb
Host smart-1478ce30-423a-4aa3-8335-d163cca2a2d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109952496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2109952496
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3579946694
Short name T713
Test name
Test status
Simulation time 114386293058 ps
CPU time 1256.82 seconds
Started May 26 01:14:19 PM PDT 24
Finished May 26 01:35:18 PM PDT 24
Peak memory 221940 kb
Host smart-f7a2cedc-6d9d-4515-8d88-19596776ae30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579946694 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3579946694
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1855340917
Short name T264
Test name
Test status
Simulation time 47841099 ps
CPU time 1.27 seconds
Started May 26 01:15:11 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 215224 kb
Host smart-3b52f7d2-8cc5-4fb3-bbdc-4724f6e25bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855340917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1855340917
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2495095690
Short name T361
Test name
Test status
Simulation time 57394671 ps
CPU time 0.91 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 206152 kb
Host smart-87f93098-af0d-4270-88af-16e49b64e787
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495095690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2495095690
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1869237411
Short name T393
Test name
Test status
Simulation time 30605412 ps
CPU time 0.81 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 215540 kb
Host smart-0d5f2b8e-ff3f-4f7f-8754-933f7b1cb30b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869237411 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1869237411
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4208276254
Short name T625
Test name
Test status
Simulation time 377450656 ps
CPU time 1.3 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 216396 kb
Host smart-b3de3364-4abc-4029-871b-fbfca25838c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208276254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4208276254
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3148192592
Short name T109
Test name
Test status
Simulation time 32175888 ps
CPU time 1.14 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 219172 kb
Host smart-fa9b239c-66a7-4bd1-a559-6f3593a49fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148192592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3148192592
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2776216477
Short name T570
Test name
Test status
Simulation time 199900853 ps
CPU time 1.3 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:15 PM PDT 24
Peak memory 216584 kb
Host smart-d5a3aca1-8a83-46c7-9a3c-14c9fe4bdc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776216477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2776216477
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1080743554
Short name T31
Test name
Test status
Simulation time 19727303 ps
CPU time 1.08 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:16 PM PDT 24
Peak memory 215336 kb
Host smart-6bc3b5d9-1d2a-46b0-af71-795ba81b575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080743554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1080743554
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1657492609
Short name T328
Test name
Test status
Simulation time 22475174 ps
CPU time 0.94 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 214960 kb
Host smart-7e8222af-e980-4c81-802f-2db7156977f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657492609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1657492609
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3047201412
Short name T518
Test name
Test status
Simulation time 45267108 ps
CPU time 1.39 seconds
Started May 26 01:15:11 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 216520 kb
Host smart-f6349c62-ca0b-4f54-8f4a-c1ef07a81fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047201412 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3047201412
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.206590044
Short name T566
Test name
Test status
Simulation time 58430016127 ps
CPU time 839.66 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:29:15 PM PDT 24
Peak memory 218584 kb
Host smart-3bdbe1d3-a5c3-4c87-a687-8950a35fcd50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206590044 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.206590044
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2011976538
Short name T582
Test name
Test status
Simulation time 92072915 ps
CPU time 1.21 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 216832 kb
Host smart-988f2e76-5301-4b9a-a9d5-f6fa301c410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011976538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2011976538
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1917524375
Short name T409
Test name
Test status
Simulation time 56642882 ps
CPU time 1.23 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 218120 kb
Host smart-9d77fd11-b647-40f8-962b-20db0e9b939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917524375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1917524375
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.389635451
Short name T607
Test name
Test status
Simulation time 125112741 ps
CPU time 1.41 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 219492 kb
Host smart-5893c07f-c18f-472c-a7fd-99262e2994ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389635451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.389635451
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.424683745
Short name T845
Test name
Test status
Simulation time 355200051 ps
CPU time 4.52 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 216696 kb
Host smart-b0858c5b-257c-4095-b037-3b5a1805267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424683745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.424683745
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2162617127
Short name T281
Test name
Test status
Simulation time 121182267 ps
CPU time 1.61 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 217820 kb
Host smart-63012e60-6ea7-4feb-a684-809e5b0c63db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162617127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2162617127
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1619124017
Short name T551
Test name
Test status
Simulation time 35129910 ps
CPU time 1.43 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:32 PM PDT 24
Peak memory 216804 kb
Host smart-9f18b6a4-786b-4475-a312-83a11b90d164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619124017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1619124017
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2141837108
Short name T529
Test name
Test status
Simulation time 86056057 ps
CPU time 1.18 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 216740 kb
Host smart-391e3b6e-267d-42a5-9395-6f9e3cacb503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141837108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2141837108
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2828206090
Short name T819
Test name
Test status
Simulation time 46051656 ps
CPU time 1.74 seconds
Started May 26 01:16:47 PM PDT 24
Finished May 26 01:16:50 PM PDT 24
Peak memory 218192 kb
Host smart-e0cd1608-7464-44ab-a341-725d8b77a831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828206090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2828206090
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1630267112
Short name T7
Test name
Test status
Simulation time 134634167 ps
CPU time 1.34 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 219040 kb
Host smart-71451f8d-a7f6-48ef-8859-b7481f3adb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630267112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1630267112
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.4038449361
Short name T425
Test name
Test status
Simulation time 117803025 ps
CPU time 1.32 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:32 PM PDT 24
Peak memory 216664 kb
Host smart-41c0770b-4447-4c2f-ac8e-99812cb573e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038449361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.4038449361
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2593396999
Short name T197
Test name
Test status
Simulation time 105704015 ps
CPU time 1.24 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 215344 kb
Host smart-9347a594-4203-4e1c-a929-3f1935cf5fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593396999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2593396999
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3853607191
Short name T588
Test name
Test status
Simulation time 17776731 ps
CPU time 0.89 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 206240 kb
Host smart-99f60c50-316b-448f-97e4-0e992eae48f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853607191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3853607191
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3111768268
Short name T497
Test name
Test status
Simulation time 36104441 ps
CPU time 0.85 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 216024 kb
Host smart-30eef97d-5465-4d9f-8588-e558109a5295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111768268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3111768268
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3504385556
Short name T799
Test name
Test status
Simulation time 43948609 ps
CPU time 1.32 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 216596 kb
Host smart-a1a14448-41de-411c-9ced-31e9f9c6f283
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504385556 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3504385556
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4091628161
Short name T117
Test name
Test status
Simulation time 23607399 ps
CPU time 0.96 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 217916 kb
Host smart-2c7d0577-b157-4e81-ae8a-cdf613448d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091628161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4091628161
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3980545446
Short name T313
Test name
Test status
Simulation time 54726577 ps
CPU time 0.97 seconds
Started May 26 01:15:11 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 216452 kb
Host smart-7af6baf5-ea5d-4a53-bcbb-4c51142c3aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980545446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3980545446
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4011708286
Short name T451
Test name
Test status
Simulation time 27716992 ps
CPU time 1.11 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 223468 kb
Host smart-5d23a9e8-f99d-43d4-8f3d-4eecb96e1e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011708286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4011708286
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3151537855
Short name T350
Test name
Test status
Simulation time 32062851 ps
CPU time 1.01 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:16 PM PDT 24
Peak memory 214960 kb
Host smart-19780e3d-9f69-4899-aa19-96d4caaeefba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151537855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3151537855
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1259489707
Short name T454
Test name
Test status
Simulation time 134422857 ps
CPU time 1.94 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:18 PM PDT 24
Peak memory 218528 kb
Host smart-375ac088-a363-4cd4-8504-f27ba3443813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259489707 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1259489707
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.712040766
Short name T840
Test name
Test status
Simulation time 83878065579 ps
CPU time 1428.47 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:39:04 PM PDT 24
Peak memory 221592 kb
Host smart-65a7a9e7-36fe-4c17-86b2-5159540159e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712040766 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.712040766
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2639823891
Short name T522
Test name
Test status
Simulation time 58687393 ps
CPU time 1.56 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 218072 kb
Host smart-1190fc20-f2c5-4bf7-b4d0-711935e403ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639823891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2639823891
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.483485017
Short name T510
Test name
Test status
Simulation time 300765513 ps
CPU time 1.45 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:32 PM PDT 24
Peak memory 218180 kb
Host smart-2372ee58-4c1c-401d-9283-78cb2d7ae7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483485017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.483485017
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1494365983
Short name T496
Test name
Test status
Simulation time 36132153 ps
CPU time 1.35 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 217960 kb
Host smart-5b451864-cb0d-40b8-a6f1-da1ba018e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494365983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1494365983
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2557638343
Short name T644
Test name
Test status
Simulation time 29473454 ps
CPU time 1.29 seconds
Started May 26 01:16:24 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 219236 kb
Host smart-1e210400-c770-4327-b49c-2de1ab0485a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557638343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2557638343
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1602335456
Short name T703
Test name
Test status
Simulation time 44422746 ps
CPU time 1.6 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:29 PM PDT 24
Peak memory 217704 kb
Host smart-1c3b410c-fa32-408c-892d-40a3bc84a31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602335456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1602335456
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.692049800
Short name T444
Test name
Test status
Simulation time 270573106 ps
CPU time 3.76 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 217940 kb
Host smart-a603afe2-ec67-4fec-885f-61925e0c40dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692049800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.692049800
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.528178128
Short name T817
Test name
Test status
Simulation time 56951279 ps
CPU time 1.75 seconds
Started May 26 01:16:24 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 217880 kb
Host smart-8134bfe7-29b5-4ba2-8bb3-16f07f20d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528178128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.528178128
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.516577965
Short name T493
Test name
Test status
Simulation time 51562565 ps
CPU time 1.84 seconds
Started May 26 01:16:27 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 218120 kb
Host smart-baf3d847-710c-4c10-83fa-45e78a3cee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516577965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.516577965
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.348108092
Short name T670
Test name
Test status
Simulation time 53969885 ps
CPU time 1.32 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 217892 kb
Host smart-d2bb61dc-8ef1-48da-ac14-1a1065dc53b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348108092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.348108092
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3122150820
Short name T482
Test name
Test status
Simulation time 99152419 ps
CPU time 1.42 seconds
Started May 26 01:16:25 PM PDT 24
Finished May 26 01:16:28 PM PDT 24
Peak memory 217932 kb
Host smart-c6788b80-c112-497a-b543-b6e1d823161c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122150820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3122150820
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.2434814570
Short name T739
Test name
Test status
Simulation time 223443301 ps
CPU time 0.94 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 206252 kb
Host smart-295c807f-8810-4b10-ad66-b65d27b0254c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434814570 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2434814570
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.2852634319
Short name T200
Test name
Test status
Simulation time 14040704 ps
CPU time 0.94 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 216136 kb
Host smart-cea6d79e-057c-4866-b961-891aca1d653a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852634319 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2852634319
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.4194476743
Short name T513
Test name
Test status
Simulation time 19580353 ps
CPU time 1.02 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 216500 kb
Host smart-009271fd-5ed2-4d5e-b670-8666a0d9f0ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194476743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.4194476743
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3848824392
Short name T4
Test name
Test status
Simulation time 30632652 ps
CPU time 1.41 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:19 PM PDT 24
Peak memory 225104 kb
Host smart-b40c3eb1-3ca1-4137-9479-78ab03ec49fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848824392 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3848824392
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2333316215
Short name T349
Test name
Test status
Simulation time 102348867 ps
CPU time 1.16 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 218960 kb
Host smart-6c91004a-d115-4a89-bb53-a219543d5ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333316215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2333316215
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1747483751
Short name T478
Test name
Test status
Simulation time 22203385 ps
CPU time 1.18 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 223456 kb
Host smart-a0a00d45-821b-453e-a409-4d6534354c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747483751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1747483751
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.4166708465
Short name T687
Test name
Test status
Simulation time 17472242 ps
CPU time 0.98 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 214844 kb
Host smart-266f1891-1b9b-40d2-aaba-012426310409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166708465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.4166708465
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.170923805
Short name T382
Test name
Test status
Simulation time 871512301 ps
CPU time 5.94 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 216600 kb
Host smart-5b40fec0-2951-4fa7-bf30-b6fd1c25566b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170923805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.170923805
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4248979055
Short name T161
Test name
Test status
Simulation time 406546556060 ps
CPU time 2317.88 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:53:57 PM PDT 24
Peak memory 227732 kb
Host smart-a705b4e5-9a91-43c6-b165-0b72ca5a9324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248979055 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4248979055
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2665496884
Short name T800
Test name
Test status
Simulation time 56262603 ps
CPU time 1.54 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:30 PM PDT 24
Peak memory 218028 kb
Host smart-20e4b443-c6e9-4464-b9f5-1e814e8bcabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665496884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2665496884
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3196647670
Short name T275
Test name
Test status
Simulation time 69187749 ps
CPU time 2.47 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 219548 kb
Host smart-b8d89a2d-5d05-4c1c-a19f-6757cc075052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196647670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3196647670
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3271778836
Short name T333
Test name
Test status
Simulation time 91008514 ps
CPU time 1.3 seconds
Started May 26 01:16:28 PM PDT 24
Finished May 26 01:16:32 PM PDT 24
Peak memory 216892 kb
Host smart-2ddb335d-0ef9-4fb3-8db4-24c0d4895877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271778836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3271778836
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2230987214
Short name T821
Test name
Test status
Simulation time 111901354 ps
CPU time 1.55 seconds
Started May 26 01:16:26 PM PDT 24
Finished May 26 01:16:31 PM PDT 24
Peak memory 218408 kb
Host smart-cfc4aa02-97e3-44eb-8f78-f0fc91a870c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230987214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2230987214
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2411089925
Short name T622
Test name
Test status
Simulation time 79886128 ps
CPU time 2.76 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 219272 kb
Host smart-f7741a3c-546b-4a1c-9790-ded8ffc75ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411089925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2411089925
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2873037075
Short name T278
Test name
Test status
Simulation time 63185167 ps
CPU time 1.57 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 217624 kb
Host smart-abd2005a-84f1-4a9a-b58d-5cc34446caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873037075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2873037075
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3395832010
Short name T285
Test name
Test status
Simulation time 45148070 ps
CPU time 1.54 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 217936 kb
Host smart-dbb5c14e-e2ef-400a-bfa3-d492c76aeb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395832010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3395832010
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2630401229
Short name T649
Test name
Test status
Simulation time 22491073 ps
CPU time 1.28 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 216572 kb
Host smart-b915acb7-8ed2-45fd-8ecd-d461bc2f88c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630401229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2630401229
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1864521633
Short name T421
Test name
Test status
Simulation time 59776190 ps
CPU time 1.04 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 217964 kb
Host smart-73afc4a6-8c5f-4bf1-a380-b3b0bcacdf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864521633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1864521633
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1360417777
Short name T839
Test name
Test status
Simulation time 43133573 ps
CPU time 1.22 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:35 PM PDT 24
Peak memory 216964 kb
Host smart-ab01ff2a-a693-4532-b841-6f95b99f6874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360417777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1360417777
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3012196312
Short name T589
Test name
Test status
Simulation time 25936782 ps
CPU time 1.33 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 215200 kb
Host smart-136bb9da-d0b3-4690-bb9d-c10db0d8160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012196312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3012196312
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2809057778
Short name T814
Test name
Test status
Simulation time 45648943 ps
CPU time 0.9 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:16 PM PDT 24
Peak memory 206220 kb
Host smart-192ce49a-4313-4a91-9902-2b7a28ff2f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809057778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2809057778
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3854471485
Short name T662
Test name
Test status
Simulation time 25763900 ps
CPU time 0.92 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 215512 kb
Host smart-b4d699a1-36bb-4ec4-a0f6-4fce380cd909
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854471485 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3854471485
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.53244210
Short name T106
Test name
Test status
Simulation time 103149682 ps
CPU time 1.16 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 216416 kb
Host smart-f09c493f-bc15-44c8-a1c3-1e97500fa24f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53244210 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_dis
able_auto_req_mode.53244210
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3883515803
Short name T195
Test name
Test status
Simulation time 20443995 ps
CPU time 1.07 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 218256 kb
Host smart-6f5eb5bb-2bbb-467a-9dda-2d528bccd2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883515803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3883515803
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1560943294
Short name T331
Test name
Test status
Simulation time 53243505 ps
CPU time 1.33 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 214968 kb
Host smart-4ac40bcf-4228-4465-99fa-f254e0f12e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560943294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1560943294
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1381565096
Short name T594
Test name
Test status
Simulation time 42557180 ps
CPU time 0.84 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 214776 kb
Host smart-17230c93-5e83-44e7-90ea-5cc594dd84b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381565096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1381565096
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2738856719
Short name T721
Test name
Test status
Simulation time 17312688 ps
CPU time 1.02 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:19 PM PDT 24
Peak memory 206628 kb
Host smart-43f94288-97a6-4fb2-a95e-900e7e4f5ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738856719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2738856719
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2171530187
Short name T292
Test name
Test status
Simulation time 230407013 ps
CPU time 5.19 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 219496 kb
Host smart-eb951cd8-ebe0-4453-9f3f-7697471a34e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171530187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2171530187
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3445784416
Short name T714
Test name
Test status
Simulation time 48653640015 ps
CPU time 1104.17 seconds
Started May 26 01:15:18 PM PDT 24
Finished May 26 01:33:46 PM PDT 24
Peak memory 218232 kb
Host smart-9f52da8a-9df3-4b3d-b452-ed82249afd0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445784416 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3445784416
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.544205859
Short name T320
Test name
Test status
Simulation time 81475111 ps
CPU time 2.36 seconds
Started May 26 01:16:35 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 217920 kb
Host smart-49c173ae-badc-4777-8e0d-8ecb3eb0e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544205859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.544205859
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.202964215
Short name T166
Test name
Test status
Simulation time 60176660 ps
CPU time 1.46 seconds
Started May 26 01:16:40 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 219688 kb
Host smart-52ac5b8c-501c-492e-b9ba-3be7ae99925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202964215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.202964215
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1813938240
Short name T838
Test name
Test status
Simulation time 62068630 ps
CPU time 2.23 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:49 PM PDT 24
Peak memory 219452 kb
Host smart-7a6f86c5-8bec-4cd8-960b-8808b3f5a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813938240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1813938240
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2043438041
Short name T446
Test name
Test status
Simulation time 28387521 ps
CPU time 1.36 seconds
Started May 26 01:16:31 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 219036 kb
Host smart-a83dacbe-8e77-4170-b36c-9f46648420c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043438041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2043438041
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3560168246
Short name T546
Test name
Test status
Simulation time 73321115 ps
CPU time 1.28 seconds
Started May 26 01:16:33 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 218108 kb
Host smart-bebd8cc5-b73e-41dd-977a-c1af8b16dd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560168246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3560168246
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.463371107
Short name T638
Test name
Test status
Simulation time 64809849 ps
CPU time 1.54 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 218000 kb
Host smart-a364025c-bd84-4824-8c8e-f04ce9ca1c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463371107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.463371107
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1729381734
Short name T44
Test name
Test status
Simulation time 162970414 ps
CPU time 1.66 seconds
Started May 26 01:16:51 PM PDT 24
Finished May 26 01:16:53 PM PDT 24
Peak memory 218104 kb
Host smart-e77e4dfb-66fb-4b2c-ab9c-487adb3fa943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729381734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1729381734
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3670882242
Short name T557
Test name
Test status
Simulation time 53076250 ps
CPU time 1.82 seconds
Started May 26 01:16:35 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 216884 kb
Host smart-ddc54b8b-df6d-4150-886e-0d069c0297fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670882242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3670882242
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.327130649
Short name T549
Test name
Test status
Simulation time 54979298 ps
CPU time 1.26 seconds
Started May 26 01:16:42 PM PDT 24
Finished May 26 01:16:45 PM PDT 24
Peak memory 216540 kb
Host smart-0133570a-5e62-466c-aa99-7c783fcb8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327130649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.327130649
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.141274788
Short name T124
Test name
Test status
Simulation time 25672919 ps
CPU time 1.19 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:19 PM PDT 24
Peak memory 215236 kb
Host smart-4440e870-6885-4b5a-9634-84c514e321d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141274788 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.141274788
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3607398442
Short name T366
Test name
Test status
Simulation time 29814968 ps
CPU time 0.9 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:15 PM PDT 24
Peak memory 206496 kb
Host smart-4e46e03d-56ef-4329-84c6-57e8f7b94e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607398442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3607398442
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.527936623
Short name T42
Test name
Test status
Simulation time 64087001 ps
CPU time 1.19 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 216588 kb
Host smart-b93ca445-319e-429d-aa2a-477018ec0260
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527936623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.527936623
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1606428280
Short name T842
Test name
Test status
Simulation time 22894623 ps
CPU time 0.94 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:18 PM PDT 24
Peak memory 218868 kb
Host smart-726094ae-9f2b-40df-bb02-135fd5f13314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606428280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1606428280
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2994633773
Short name T575
Test name
Test status
Simulation time 40282443 ps
CPU time 1.42 seconds
Started May 26 01:15:16 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 218764 kb
Host smart-b369512a-d7e7-4441-a2f3-00a2badca34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994633773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2994633773
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2107642790
Short name T175
Test name
Test status
Simulation time 20801433 ps
CPU time 1.1 seconds
Started May 26 01:15:15 PM PDT 24
Finished May 26 01:15:20 PM PDT 24
Peak memory 215276 kb
Host smart-6f2417b0-96d8-4bac-8019-e0459a707c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107642790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2107642790
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.21571364
Short name T432
Test name
Test status
Simulation time 44907236 ps
CPU time 0.93 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:22 PM PDT 24
Peak memory 214852 kb
Host smart-edb06361-9c70-4fad-93ce-846f4746cef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21571364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.21571364
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.79894122
Short name T558
Test name
Test status
Simulation time 1376999822 ps
CPU time 5.74 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:21 PM PDT 24
Peak memory 214952 kb
Host smart-2eed8255-7346-4aee-af2f-e9820489556d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79894122 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.79894122
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.107955214
Short name T206
Test name
Test status
Simulation time 308930809076 ps
CPU time 1140.6 seconds
Started May 26 01:15:18 PM PDT 24
Finished May 26 01:34:22 PM PDT 24
Peak memory 221696 kb
Host smart-39189a94-e4e2-47d1-994b-7ecec609e5a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107955214 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.107955214
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2874261516
Short name T627
Test name
Test status
Simulation time 48747310 ps
CPU time 1.53 seconds
Started May 26 01:16:35 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 219520 kb
Host smart-a8f013ef-41f5-4632-ab0b-471184c497a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874261516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2874261516
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2421802228
Short name T602
Test name
Test status
Simulation time 97900958 ps
CPU time 3.11 seconds
Started May 26 01:16:29 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 219168 kb
Host smart-76f88308-e498-4491-8f6a-1966d7bbd53a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421802228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2421802228
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3924412307
Short name T9
Test name
Test status
Simulation time 44191004 ps
CPU time 1.21 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:49 PM PDT 24
Peak memory 219280 kb
Host smart-c6f96cd0-a70d-405d-8fc5-cff4dac0a80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924412307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3924412307
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.63303540
Short name T339
Test name
Test status
Simulation time 30802496 ps
CPU time 1.11 seconds
Started May 26 01:16:30 PM PDT 24
Finished May 26 01:16:34 PM PDT 24
Peak memory 216632 kb
Host smart-cacd5858-b669-4751-8bb7-a3f025f5487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63303540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.63303540
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4276566094
Short name T413
Test name
Test status
Simulation time 74840501 ps
CPU time 1.28 seconds
Started May 26 01:16:38 PM PDT 24
Finished May 26 01:16:41 PM PDT 24
Peak memory 219572 kb
Host smart-a233f524-d816-480b-99a7-7972da1a3fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276566094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4276566094
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3202292379
Short name T484
Test name
Test status
Simulation time 26762824 ps
CPU time 1.18 seconds
Started May 26 01:16:32 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 214956 kb
Host smart-9ee6e308-77d6-4f03-a554-8719f1074e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202292379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3202292379
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3723947337
Short name T434
Test name
Test status
Simulation time 184175794 ps
CPU time 1.07 seconds
Started May 26 01:16:40 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 216796 kb
Host smart-c55c993b-4fa6-4fc6-aa88-584dec05bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723947337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3723947337
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3053031457
Short name T608
Test name
Test status
Simulation time 45538284 ps
CPU time 1.37 seconds
Started May 26 01:16:35 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 219288 kb
Host smart-0eac9374-65a6-411e-9660-05cd9dcc3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053031457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3053031457
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3653089067
Short name T606
Test name
Test status
Simulation time 89095989 ps
CPU time 1.42 seconds
Started May 26 01:16:31 PM PDT 24
Finished May 26 01:16:36 PM PDT 24
Peak memory 217744 kb
Host smart-5087979e-438f-4b39-9439-2764b262bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653089067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3653089067
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2124896136
Short name T77
Test name
Test status
Simulation time 48406884 ps
CPU time 1.2 seconds
Started May 26 01:15:14 PM PDT 24
Finished May 26 01:15:17 PM PDT 24
Peak memory 215344 kb
Host smart-001da486-c464-4a43-9b21-9f262bf34c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124896136 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2124896136
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3097828023
Short name T68
Test name
Test status
Simulation time 16478124 ps
CPU time 0.99 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 214460 kb
Host smart-fbc21e09-4ddf-4b3b-a52f-2038c92f1d05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097828023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3097828023
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.134266839
Short name T136
Test name
Test status
Simulation time 24581682 ps
CPU time 0.89 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 216000 kb
Host smart-6350f204-f284-4fe4-bd1e-c848268fe154
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134266839 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.134266839
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2135064836
Short name T112
Test name
Test status
Simulation time 81219484 ps
CPU time 1.32 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 216540 kb
Host smart-94a16371-baa9-41d0-a3ad-42e199d972f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135064836 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2135064836
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1931829838
Short name T54
Test name
Test status
Simulation time 28062265 ps
CPU time 1.31 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 229176 kb
Host smart-58116975-09c0-4e37-ac34-65b8195cfb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931829838 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1931829838
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3909715056
Short name T342
Test name
Test status
Simulation time 85948487 ps
CPU time 1.29 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:15:15 PM PDT 24
Peak memory 218016 kb
Host smart-93da035a-4c58-4e36-a43f-2986fe816a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909715056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3909715056
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3702532897
Short name T844
Test name
Test status
Simulation time 24963620 ps
CPU time 1 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:15:14 PM PDT 24
Peak memory 215100 kb
Host smart-c1f2ebcf-50b4-4596-90e3-4115f9c4a90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702532897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3702532897
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4100674787
Short name T386
Test name
Test status
Simulation time 15930605 ps
CPU time 1 seconds
Started May 26 01:15:13 PM PDT 24
Finished May 26 01:15:16 PM PDT 24
Peak memory 214812 kb
Host smart-215fa782-b54d-4bdb-97f4-ae2329c45410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100674787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4100674787
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.904690250
Short name T213
Test name
Test status
Simulation time 591988546 ps
CPU time 2.71 seconds
Started May 26 01:15:17 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 214868 kb
Host smart-370a7666-aaed-417d-9ac7-c729e0c16e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904690250 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.904690250
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3714044732
Short name T164
Test name
Test status
Simulation time 1345286316756 ps
CPU time 2247.94 seconds
Started May 26 01:15:12 PM PDT 24
Finished May 26 01:52:41 PM PDT 24
Peak memory 226268 kb
Host smart-636df5aa-1c04-48d9-909f-3f7c763f49c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714044732 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3714044732
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3412937266
Short name T319
Test name
Test status
Simulation time 44168516 ps
CPU time 1.62 seconds
Started May 26 01:16:42 PM PDT 24
Finished May 26 01:16:45 PM PDT 24
Peak memory 218116 kb
Host smart-c2a8d1a5-1f95-47b2-97fb-292d6d5c1385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412937266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3412937266
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2440499193
Short name T559
Test name
Test status
Simulation time 59487988 ps
CPU time 1.21 seconds
Started May 26 01:16:49 PM PDT 24
Finished May 26 01:16:51 PM PDT 24
Peak memory 216828 kb
Host smart-788c2684-4b7f-4dcd-a8e3-ead943fb6ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440499193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2440499193
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3196142621
Short name T494
Test name
Test status
Simulation time 59932329 ps
CPU time 1.48 seconds
Started May 26 01:16:32 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 216452 kb
Host smart-e8c27d6f-c3d5-4062-8c39-2b06796e538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196142621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3196142621
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.2063622867
Short name T630
Test name
Test status
Simulation time 54198799 ps
CPU time 1.22 seconds
Started May 26 01:16:41 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 216684 kb
Host smart-fd6943bd-ae42-4f16-952b-90f35d3499b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063622867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2063622867
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.860052141
Short name T550
Test name
Test status
Simulation time 79634355 ps
CPU time 1.14 seconds
Started May 26 01:16:35 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 216920 kb
Host smart-44e58d86-4b91-4fa7-99a7-0872f6a2e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860052141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.860052141
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.30730220
Short name T291
Test name
Test status
Simulation time 26627049 ps
CPU time 1.48 seconds
Started May 26 01:16:43 PM PDT 24
Finished May 26 01:16:46 PM PDT 24
Peak memory 217832 kb
Host smart-d0519b59-5c9b-4e4e-bf76-35aaf3641728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30730220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.30730220
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4099008540
Short name T92
Test name
Test status
Simulation time 63073267 ps
CPU time 1.43 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:42 PM PDT 24
Peak memory 217956 kb
Host smart-bf6f0021-73af-49c5-ab7a-fe10b3879f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099008540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4099008540
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3550412279
Short name T706
Test name
Test status
Simulation time 34168179 ps
CPU time 1.31 seconds
Started May 26 01:16:36 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 217808 kb
Host smart-d4e65341-069f-4b42-9b63-90f0ddbe2c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550412279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3550412279
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.456342901
Short name T591
Test name
Test status
Simulation time 56822046 ps
CPU time 1.23 seconds
Started May 26 01:16:45 PM PDT 24
Finished May 26 01:16:48 PM PDT 24
Peak memory 216664 kb
Host smart-b45c6617-3771-4169-8744-07c77a55199a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456342901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.456342901
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.283713827
Short name T611
Test name
Test status
Simulation time 23850446 ps
CPU time 1.11 seconds
Started May 26 01:15:26 PM PDT 24
Finished May 26 01:15:28 PM PDT 24
Peak memory 215068 kb
Host smart-b8ce8ed9-cc44-4dae-9a28-ae36819647ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283713827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.283713827
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.971699206
Short name T450
Test name
Test status
Simulation time 32453671 ps
CPU time 0.89 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 206160 kb
Host smart-e946452d-8a88-446c-9f76-ef7203316154
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971699206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.971699206
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.4140725890
Short name T146
Test name
Test status
Simulation time 23015503 ps
CPU time 0.87 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:26 PM PDT 24
Peak memory 215212 kb
Host smart-e45e941e-14a0-4cd3-a12b-2c55de6a2b41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140725890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4140725890
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.183676305
Short name T98
Test name
Test status
Simulation time 75068271 ps
CPU time 1.04 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 216668 kb
Host smart-97b90230-2a16-4065-b346-08d89fbf6054
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183676305 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.183676305
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1300163563
Short name T760
Test name
Test status
Simulation time 33304783 ps
CPU time 1.06 seconds
Started May 26 01:15:21 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 223292 kb
Host smart-72d0af73-f389-463b-829f-a829f40d2c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300163563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1300163563
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.98650426
Short name T750
Test name
Test status
Simulation time 40859374 ps
CPU time 1.43 seconds
Started May 26 01:15:18 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 217800 kb
Host smart-0b425dda-c51d-4989-874d-45f000e61b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98650426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.98650426
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.4033998574
Short name T155
Test name
Test status
Simulation time 21813303 ps
CPU time 1.11 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 215232 kb
Host smart-cf68e7ac-c0ed-4fe0-b2ed-d6e11737b1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033998574 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.4033998574
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.680423148
Short name T391
Test name
Test status
Simulation time 22556285 ps
CPU time 0.89 seconds
Started May 26 01:15:26 PM PDT 24
Finished May 26 01:15:28 PM PDT 24
Peak memory 214724 kb
Host smart-d5a06834-fff9-4aab-962e-75170c762fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680423148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.680423148
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2450256932
Short name T780
Test name
Test status
Simulation time 319415289 ps
CPU time 2.21 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 214912 kb
Host smart-04cc1f01-e40e-4052-abf7-2f08ecb532dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450256932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2450256932
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3039214140
Short name T749
Test name
Test status
Simulation time 493479049242 ps
CPU time 812.74 seconds
Started May 26 01:15:18 PM PDT 24
Finished May 26 01:28:55 PM PDT 24
Peak memory 222136 kb
Host smart-442361bc-24b1-4c8a-a4bd-cdb9c2103ee1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039214140 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3039214140
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4167840716
Short name T498
Test name
Test status
Simulation time 52890768 ps
CPU time 1.71 seconds
Started May 26 01:16:36 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 214860 kb
Host smart-11008094-f443-4ebd-8f53-4f37b1dbc524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167840716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4167840716
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4255650013
Short name T364
Test name
Test status
Simulation time 42576773 ps
CPU time 1.12 seconds
Started May 26 01:16:32 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 219416 kb
Host smart-532c913f-bc8a-4cd0-be41-546ee4e4c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255650013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4255650013
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3520172885
Short name T576
Test name
Test status
Simulation time 34762184 ps
CPU time 1.39 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 216576 kb
Host smart-5641ca92-c72c-46c7-9091-c77014a880db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520172885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3520172885
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2687970613
Short name T330
Test name
Test status
Simulation time 62308926 ps
CPU time 1.32 seconds
Started May 26 01:16:41 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 219212 kb
Host smart-56a702fb-73f2-4d57-bb02-8c31a6c945c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687970613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2687970613
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3439314645
Short name T472
Test name
Test status
Simulation time 49625598 ps
CPU time 1.96 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:50 PM PDT 24
Peak memory 219460 kb
Host smart-e835a185-5493-418c-9069-9a97511498f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439314645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3439314645
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2056143668
Short name T809
Test name
Test status
Simulation time 66478056 ps
CPU time 1.18 seconds
Started May 26 01:16:38 PM PDT 24
Finished May 26 01:16:41 PM PDT 24
Peak memory 216784 kb
Host smart-f0b3899b-9eee-43ca-9259-7ce4cf13518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056143668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2056143668
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1437080678
Short name T396
Test name
Test status
Simulation time 52748163 ps
CPU time 1.76 seconds
Started May 26 01:16:36 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 219524 kb
Host smart-6963a560-038f-4d9d-a0fd-a21fcd908338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437080678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1437080678
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1728857633
Short name T310
Test name
Test status
Simulation time 84705405 ps
CPU time 1.11 seconds
Started May 26 01:16:36 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 216460 kb
Host smart-98250433-baa9-497d-bcea-6e7a919cc6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728857633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1728857633
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4242004491
Short name T475
Test name
Test status
Simulation time 36182562 ps
CPU time 1.4 seconds
Started May 26 01:16:38 PM PDT 24
Finished May 26 01:16:41 PM PDT 24
Peak memory 216904 kb
Host smart-861ec457-c2fb-4328-abd6-b803341b619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242004491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4242004491
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3477047595
Short name T560
Test name
Test status
Simulation time 133777422 ps
CPU time 1.22 seconds
Started May 26 01:15:26 PM PDT 24
Finished May 26 01:15:28 PM PDT 24
Peak memory 214924 kb
Host smart-9d24bf91-3d35-4425-8844-ab405523e657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477047595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3477047595
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2026250113
Short name T311
Test name
Test status
Simulation time 12799447 ps
CPU time 0.9 seconds
Started May 26 01:15:22 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 206064 kb
Host smart-38d662b2-a07a-4233-8e53-e77572cedade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026250113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2026250113
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1559468675
Short name T672
Test name
Test status
Simulation time 34815675 ps
CPU time 0.84 seconds
Started May 26 01:15:18 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 216028 kb
Host smart-15bc5d8f-c20a-46d7-9916-69da1c2c5119
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559468675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1559468675
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4078859911
Short name T179
Test name
Test status
Simulation time 28716055 ps
CPU time 1.11 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 217532 kb
Host smart-4f0830d4-438d-4cd0-9631-ca4770e6c193
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078859911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4078859911
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3061186928
Short name T113
Test name
Test status
Simulation time 21095429 ps
CPU time 1.14 seconds
Started May 26 01:15:21 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 219392 kb
Host smart-7d7c9e1d-2d9c-48f7-ae92-32af08d15a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061186928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3061186928
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3603264937
Short name T465
Test name
Test status
Simulation time 32474981 ps
CPU time 1.52 seconds
Started May 26 01:15:21 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 218052 kb
Host smart-e0dc8458-2cd1-4508-a8c9-ca1e67d8a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603264937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3603264937
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1449337004
Short name T412
Test name
Test status
Simulation time 32818424 ps
CPU time 0.88 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 214960 kb
Host smart-177bb15d-ef2a-4526-852e-3be1e9a9b86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449337004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1449337004
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3074997559
Short name T322
Test name
Test status
Simulation time 63090186 ps
CPU time 0.96 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 214928 kb
Host smart-41d196dd-61dc-4e30-bb45-91dce59c77b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074997559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3074997559
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1627650730
Short name T536
Test name
Test status
Simulation time 476094344 ps
CPU time 4.88 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 216704 kb
Host smart-3364a306-182c-4194-a61a-4e2678e556e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627650730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1627650730
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.4124048920
Short name T567
Test name
Test status
Simulation time 32130783 ps
CPU time 1.47 seconds
Started May 26 01:16:42 PM PDT 24
Finished May 26 01:16:45 PM PDT 24
Peak memory 217864 kb
Host smart-97f08fb5-4560-4039-8a5d-ff2745202a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124048920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4124048920
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2716657586
Short name T399
Test name
Test status
Simulation time 42608517 ps
CPU time 1.75 seconds
Started May 26 01:16:38 PM PDT 24
Finished May 26 01:16:41 PM PDT 24
Peak memory 217636 kb
Host smart-4212159b-036d-4027-aa41-1ae6c1e501e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716657586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2716657586
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3203768070
Short name T378
Test name
Test status
Simulation time 44855313 ps
CPU time 1.36 seconds
Started May 26 01:16:47 PM PDT 24
Finished May 26 01:16:50 PM PDT 24
Peak memory 219168 kb
Host smart-0c30b01b-235e-4f41-875c-ba2f7ce8596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203768070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3203768070
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3515961818
Short name T89
Test name
Test status
Simulation time 85139085 ps
CPU time 1.72 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 219656 kb
Host smart-de2b2759-f6a9-4eff-8bcf-c3b60fdb4dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515961818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3515961818
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3532685647
Short name T822
Test name
Test status
Simulation time 92124728 ps
CPU time 1.41 seconds
Started May 26 01:16:44 PM PDT 24
Finished May 26 01:16:47 PM PDT 24
Peak memory 218232 kb
Host smart-144bb9bd-37db-44b7-a51a-d61d7544c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532685647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3532685647
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3411534114
Short name T481
Test name
Test status
Simulation time 303455209 ps
CPU time 2.85 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 219236 kb
Host smart-43d80f2d-41e1-41c0-9834-dbf004a4e901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411534114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3411534114
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3645698035
Short name T683
Test name
Test status
Simulation time 110561980 ps
CPU time 1.31 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 216620 kb
Host smart-bdf1e37c-1a4b-4b63-bf11-79c0c478b788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645698035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3645698035
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.375785300
Short name T764
Test name
Test status
Simulation time 222752507 ps
CPU time 1.99 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 218276 kb
Host smart-71361c0c-47af-46af-9f86-27301a7cc85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375785300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.375785300
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1006231699
Short name T555
Test name
Test status
Simulation time 99666690 ps
CPU time 1.48 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 217884 kb
Host smart-e9a6259c-003d-4129-abc3-770576b8b756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006231699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1006231699
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3755696641
Short name T561
Test name
Test status
Simulation time 25112475 ps
CPU time 1.18 seconds
Started May 26 01:16:40 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 216676 kb
Host smart-8aa50ab6-4a29-4982-9505-2378ba630e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755696641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3755696641
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1844457216
Short name T803
Test name
Test status
Simulation time 88118195 ps
CPU time 1.14 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 215192 kb
Host smart-ef191dd6-4919-47dd-81ee-3085ecfae4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844457216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1844457216
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.46320075
Short name T20
Test name
Test status
Simulation time 15452439 ps
CPU time 0.93 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 206072 kb
Host smart-ba155caa-96ce-4ad3-aeb3-d1e85b060580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46320075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.46320075
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2117112592
Short name T748
Test name
Test status
Simulation time 12285435 ps
CPU time 0.89 seconds
Started May 26 01:15:26 PM PDT 24
Finished May 26 01:15:28 PM PDT 24
Peak memory 215824 kb
Host smart-d36a84fb-2661-4112-8d45-a0cb5e3a82b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117112592 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2117112592
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2913806737
Short name T424
Test name
Test status
Simulation time 71265607 ps
CPU time 0.97 seconds
Started May 26 01:15:25 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 217644 kb
Host smart-e6b63f8a-e160-49d6-8ea7-be67154eae3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913806737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2913806737
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2579547295
Short name T6
Test name
Test status
Simulation time 35924473 ps
CPU time 1.02 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 229072 kb
Host smart-796d88aa-4cec-4c92-b62b-d0514f3de24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579547295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2579547295
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3020430473
Short name T340
Test name
Test status
Simulation time 38169902 ps
CPU time 1.14 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 217764 kb
Host smart-83cdd124-8d2c-4241-bb11-b9ed53e98456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020430473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3020430473
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3767681561
Short name T631
Test name
Test status
Simulation time 20889741 ps
CPU time 1.14 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 215164 kb
Host smart-1ae5e5de-2326-46e4-9470-0e1b58eccbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767681561 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3767681561
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.382336932
Short name T360
Test name
Test status
Simulation time 15581310 ps
CPU time 1.02 seconds
Started May 26 01:15:22 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 214856 kb
Host smart-ad9828b9-899f-466e-bc0c-d219aedd67d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382336932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.382336932
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2715810404
Short name T469
Test name
Test status
Simulation time 172822285 ps
CPU time 2.36 seconds
Started May 26 01:15:20 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 216388 kb
Host smart-0d7ba563-9eef-424a-881b-12ac831021bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715810404 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2715810404
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/280.edn_genbits.410142788
Short name T552
Test name
Test status
Simulation time 45712290 ps
CPU time 1.35 seconds
Started May 26 01:16:33 PM PDT 24
Finished May 26 01:16:37 PM PDT 24
Peak memory 216744 kb
Host smart-b86f7a3a-92bc-4855-88ff-84f5ef8dbb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410142788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.410142788
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1382312416
Short name T621
Test name
Test status
Simulation time 100345509 ps
CPU time 1.31 seconds
Started May 26 01:16:40 PM PDT 24
Finished May 26 01:16:43 PM PDT 24
Peak memory 216720 kb
Host smart-9601f880-56da-49b1-a7f3-41df750e5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382312416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1382312416
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.749618282
Short name T351
Test name
Test status
Simulation time 38854392 ps
CPU time 1.35 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:42 PM PDT 24
Peak memory 216636 kb
Host smart-10f888a6-5e5b-4773-ad46-4bd8fb19676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749618282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.749618282
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2627125576
Short name T21
Test name
Test status
Simulation time 32105607 ps
CPU time 1.57 seconds
Started May 26 01:16:44 PM PDT 24
Finished May 26 01:16:47 PM PDT 24
Peak memory 217800 kb
Host smart-b1c44c12-4ce0-4c3b-81c2-41ced533f617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627125576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2627125576
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.4282373044
Short name T707
Test name
Test status
Simulation time 63508131 ps
CPU time 1.37 seconds
Started May 26 01:16:39 PM PDT 24
Finished May 26 01:16:42 PM PDT 24
Peak memory 217692 kb
Host smart-dd856bf9-8010-4612-b473-69d678f15186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282373044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.4282373044
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3979060352
Short name T639
Test name
Test status
Simulation time 153491621 ps
CPU time 1.3 seconds
Started May 26 01:16:41 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 216624 kb
Host smart-380b5ea5-29f0-430e-b3d4-0ca56d5d76db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979060352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3979060352
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2832149265
Short name T212
Test name
Test status
Simulation time 66402728 ps
CPU time 1.35 seconds
Started May 26 01:16:38 PM PDT 24
Finished May 26 01:16:41 PM PDT 24
Peak memory 214848 kb
Host smart-4ed26e2e-366a-4b75-b027-3d4cedf1d27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832149265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2832149265
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3632568927
Short name T792
Test name
Test status
Simulation time 153416224 ps
CPU time 0.95 seconds
Started May 26 01:16:37 PM PDT 24
Finished May 26 01:16:40 PM PDT 24
Peak memory 216732 kb
Host smart-1821b96c-61bc-4c48-a638-7db4e5e28e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632568927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3632568927
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.207416662
Short name T480
Test name
Test status
Simulation time 186601745 ps
CPU time 2.2 seconds
Started May 26 01:16:40 PM PDT 24
Finished May 26 01:16:44 PM PDT 24
Peak memory 219896 kb
Host smart-abd293b6-d151-4a34-b034-e4cdd76bf457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207416662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.207416662
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3500717588
Short name T634
Test name
Test status
Simulation time 20973520 ps
CPU time 0.87 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 206100 kb
Host smart-32b532c6-c8d9-41af-895d-7504770e3a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500717588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3500717588
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3004927318
Short name T773
Test name
Test status
Simulation time 91737135 ps
CPU time 1 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 216344 kb
Host smart-3e7e4e2e-62e0-4f75-9ff8-fb06b4445770
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004927318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3004927318
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2775623709
Short name T152
Test name
Test status
Simulation time 19800186 ps
CPU time 1.17 seconds
Started May 26 01:15:24 PM PDT 24
Finished May 26 01:15:27 PM PDT 24
Peak memory 228948 kb
Host smart-deec1bf9-8419-4a10-857a-168cc09482e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775623709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2775623709
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3737398100
Short name T318
Test name
Test status
Simulation time 87570224 ps
CPU time 1.45 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:24 PM PDT 24
Peak memory 218096 kb
Host smart-7dc065aa-f32e-4d03-924b-4233d147b82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737398100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3737398100
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.4085368791
Short name T401
Test name
Test status
Simulation time 74126838 ps
CPU time 0.98 seconds
Started May 26 01:15:22 PM PDT 24
Finished May 26 01:15:25 PM PDT 24
Peak memory 223300 kb
Host smart-2174f478-7254-449d-b099-078c8a3698be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085368791 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4085368791
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.724325851
Short name T304
Test name
Test status
Simulation time 37843132 ps
CPU time 0.93 seconds
Started May 26 01:15:19 PM PDT 24
Finished May 26 01:15:23 PM PDT 24
Peak memory 214812 kb
Host smart-c842b61f-d8f8-4c3e-830c-c32b8f06c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724325851 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.724325851
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1777347176
Short name T563
Test name
Test status
Simulation time 635814335 ps
CPU time 2.42 seconds
Started May 26 01:15:25 PM PDT 24
Finished May 26 01:15:29 PM PDT 24
Peak memory 216596 kb
Host smart-7b0d3dd6-15a4-46b5-a3a5-ce4cb56e7dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777347176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1777347176
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.317778294
Short name T289
Test name
Test status
Simulation time 86118732920 ps
CPU time 1957.52 seconds
Started May 26 01:15:22 PM PDT 24
Finished May 26 01:48:02 PM PDT 24
Peak memory 228124 kb
Host smart-40ca898b-0628-405b-ab79-1a99a6911f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317778294 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.317778294
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.341841682
Short name T368
Test name
Test status
Simulation time 148229990 ps
CPU time 2.19 seconds
Started May 26 01:16:43 PM PDT 24
Finished May 26 01:16:47 PM PDT 24
Peak memory 219704 kb
Host smart-8a1fdf83-3588-400e-a409-5608f3da530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341841682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.341841682
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1372047807
Short name T797
Test name
Test status
Simulation time 64641763 ps
CPU time 2.11 seconds
Started May 26 01:16:41 PM PDT 24
Finished May 26 01:16:45 PM PDT 24
Peak memory 219096 kb
Host smart-54109401-8c7d-4c3d-8ef8-1997eb348bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372047807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1372047807
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2327934387
Short name T648
Test name
Test status
Simulation time 38414061 ps
CPU time 1.33 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:38 PM PDT 24
Peak memory 216752 kb
Host smart-ac1acbad-fe24-4615-9d22-c28f5d51da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327934387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2327934387
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.961811305
Short name T73
Test name
Test status
Simulation time 66262694 ps
CPU time 1.37 seconds
Started May 26 01:16:42 PM PDT 24
Finished May 26 01:16:45 PM PDT 24
Peak memory 218236 kb
Host smart-b24d699a-fc67-4e38-96f6-0a5e5304740a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961811305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.961811305
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3599753682
Short name T696
Test name
Test status
Simulation time 54349976 ps
CPU time 1.94 seconds
Started May 26 01:16:34 PM PDT 24
Finished May 26 01:16:39 PM PDT 24
Peak memory 219532 kb
Host smart-a887d8da-3214-44c5-b23c-49ddf7056036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599753682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3599753682
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3654565482
Short name T598
Test name
Test status
Simulation time 54143589 ps
CPU time 2.01 seconds
Started May 26 01:16:42 PM PDT 24
Finished May 26 01:16:46 PM PDT 24
Peak memory 219376 kb
Host smart-84c76030-c43c-42ff-a6ee-b908b8d90f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654565482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3654565482
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1510865311
Short name T372
Test name
Test status
Simulation time 82479481 ps
CPU time 1.15 seconds
Started May 26 01:16:43 PM PDT 24
Finished May 26 01:16:46 PM PDT 24
Peak memory 216488 kb
Host smart-95d4521a-29ae-41c9-844d-1f5eac8b9de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510865311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1510865311
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2682977203
Short name T355
Test name
Test status
Simulation time 48156288 ps
CPU time 1.16 seconds
Started May 26 01:16:52 PM PDT 24
Finished May 26 01:16:54 PM PDT 24
Peak memory 219236 kb
Host smart-3f52b2b9-5a09-4c54-b5d3-9e3cc5012d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682977203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2682977203
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2091492452
Short name T788
Test name
Test status
Simulation time 48017692 ps
CPU time 1.2 seconds
Started May 26 01:16:46 PM PDT 24
Finished May 26 01:16:49 PM PDT 24
Peak memory 216576 kb
Host smart-3f48fb46-42ad-4f2d-9c7a-d16b101a1360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091492452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2091492452
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3474113438
Short name T443
Test name
Test status
Simulation time 334880926 ps
CPU time 3.88 seconds
Started May 26 01:16:44 PM PDT 24
Finished May 26 01:16:49 PM PDT 24
Peak memory 216988 kb
Host smart-fd44b160-741f-4ef6-80fd-821a7871db33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474113438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3474113438
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1760448597
Short name T174
Test name
Test status
Simulation time 80096927 ps
CPU time 1.19 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:32 PM PDT 24
Peak memory 215336 kb
Host smart-2c835866-d93c-4a47-92e4-136143f82f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760448597 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1760448597
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.794002817
Short name T428
Test name
Test status
Simulation time 27837100 ps
CPU time 0.93 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:34 PM PDT 24
Peak memory 214432 kb
Host smart-d6f6587a-01f9-46ee-affe-e21844fe0361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794002817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.794002817
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2284849337
Short name T653
Test name
Test status
Simulation time 12423844 ps
CPU time 0.91 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:30 PM PDT 24
Peak memory 216188 kb
Host smart-557e304e-4e04-489f-9ff1-be7549a8c7d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284849337 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2284849337
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.902011214
Short name T64
Test name
Test status
Simulation time 40186410 ps
CPU time 1.36 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:34 PM PDT 24
Peak memory 216304 kb
Host smart-c00ea4ca-8710-4c6d-b860-e899b59c5aca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902011214 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.902011214
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1784782486
Short name T727
Test name
Test status
Simulation time 21169837 ps
CPU time 1.02 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 219200 kb
Host smart-e5f4390f-d3bc-411d-92c6-00408fb7726e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784782486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1784782486
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1800867125
Short name T543
Test name
Test status
Simulation time 69959937 ps
CPU time 1.07 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:31 PM PDT 24
Peak memory 217992 kb
Host smart-95b58617-59cb-4dc8-a908-ca01aa0b6528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800867125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1800867125
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3463542494
Short name T388
Test name
Test status
Simulation time 21118061 ps
CPU time 1.11 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:32 PM PDT 24
Peak memory 215220 kb
Host smart-f65cbb6c-0685-407e-a09a-d58b2bfcb6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463542494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3463542494
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1123824951
Short name T15
Test name
Test status
Simulation time 244048848 ps
CPU time 4.38 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:38 PM PDT 24
Peak memory 235036 kb
Host smart-1dbf1b29-996c-466f-a103-65b2f9fcba53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123824951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1123824951
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3239783489
Short name T815
Test name
Test status
Simulation time 17653260 ps
CPU time 0.98 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:34 PM PDT 24
Peak memory 214724 kb
Host smart-629eda83-4be9-4aa5-b01e-25a730efcd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239783489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3239783489
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1363538960
Short name T453
Test name
Test status
Simulation time 340763282 ps
CPU time 6.48 seconds
Started May 26 01:14:35 PM PDT 24
Finished May 26 01:14:43 PM PDT 24
Peak memory 216476 kb
Host smart-d389bd93-7bc8-4265-9551-e0f81c168018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363538960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1363538960
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3197206425
Short name T617
Test name
Test status
Simulation time 92448140271 ps
CPU time 593.07 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:24:27 PM PDT 24
Peak memory 220024 kb
Host smart-a1875bf8-dee1-4d59-aed6-fc574c16c105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197206425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3197206425
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1990153314
Short name T266
Test name
Test status
Simulation time 32389806 ps
CPU time 1.24 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:30 PM PDT 24
Peak memory 215352 kb
Host smart-1ca26585-89ae-46b7-8001-ac0aa8372af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990153314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1990153314
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3855307475
Short name T384
Test name
Test status
Simulation time 24628336 ps
CPU time 0.88 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 206260 kb
Host smart-66634161-5ba7-48fa-928a-ba1ba99124d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855307475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3855307475
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.564244389
Short name T380
Test name
Test status
Simulation time 12274959 ps
CPU time 0.95 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 215660 kb
Host smart-521fd592-623f-415f-9d0f-a991e097db0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564244389 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.564244389
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3603106768
Short name T17
Test name
Test status
Simulation time 39591978 ps
CPU time 1.23 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 219164 kb
Host smart-d9b8d7cb-86a3-40d9-8f96-f6928a5da3ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603106768 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3603106768
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.100408999
Short name T841
Test name
Test status
Simulation time 50201880 ps
CPU time 1 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:32 PM PDT 24
Peak memory 219300 kb
Host smart-6b4a9bfe-cab5-4115-a7dd-7172efb2dcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100408999 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.100408999
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.4203491642
Short name T811
Test name
Test status
Simulation time 101496753 ps
CPU time 0.95 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 216648 kb
Host smart-9e40eab0-84dc-4950-be00-ec097cbeea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203491642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4203491642
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1265976275
Short name T489
Test name
Test status
Simulation time 22489773 ps
CPU time 1.08 seconds
Started May 26 01:15:27 PM PDT 24
Finished May 26 01:15:29 PM PDT 24
Peak memory 215064 kb
Host smart-94b81c72-6d8b-4ac8-aac3-4a89a9422869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265976275 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1265976275
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4027098601
Short name T400
Test name
Test status
Simulation time 179146178 ps
CPU time 0.88 seconds
Started May 26 01:15:26 PM PDT 24
Finished May 26 01:15:28 PM PDT 24
Peak memory 214348 kb
Host smart-755915a2-a1d3-4804-89aa-b3f0f5c3e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027098601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4027098601
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4146158253
Short name T574
Test name
Test status
Simulation time 253912469 ps
CPU time 3.81 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:32 PM PDT 24
Peak memory 219612 kb
Host smart-e88ac68a-d429-4b30-bf25-3558220ab31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146158253 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4146158253
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2583945871
Short name T526
Test name
Test status
Simulation time 126742433494 ps
CPU time 783.93 seconds
Started May 26 01:15:44 PM PDT 24
Finished May 26 01:28:49 PM PDT 24
Peak memory 221288 kb
Host smart-6892e1b6-c234-4504-af85-f9f75beb468c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583945871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2583945871
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1821306844
Short name T263
Test name
Test status
Simulation time 27778486 ps
CPU time 1.3 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 215240 kb
Host smart-70b6abe3-85d0-4214-aa09-1c86a2e977ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821306844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1821306844
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1942141681
Short name T554
Test name
Test status
Simulation time 43025848 ps
CPU time 0.87 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 206520 kb
Host smart-da6bd711-b241-4cd1-8611-0d79d7c1ab5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942141681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1942141681
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.847468780
Short name T134
Test name
Test status
Simulation time 20019288 ps
CPU time 0.86 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 216008 kb
Host smart-3696c827-591c-499e-be3c-ea7e408f7147
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847468780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.847468780
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1909615448
Short name T181
Test name
Test status
Simulation time 100475408 ps
CPU time 1.07 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 219324 kb
Host smart-610bf813-cca6-4fd5-8f65-4823efe8212b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909615448 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1909615448
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4264139488
Short name T107
Test name
Test status
Simulation time 48854321 ps
CPU time 0.98 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 217940 kb
Host smart-fed1c8c6-ec8f-45c2-b19f-4ce2737e3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264139488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4264139488
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1438410738
Short name T288
Test name
Test status
Simulation time 121583701 ps
CPU time 1.77 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 219656 kb
Host smart-5cc9eea2-a51c-41cb-90cd-c313c3f2a513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438410738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1438410738
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.49558003
Short name T771
Test name
Test status
Simulation time 60671847 ps
CPU time 0.96 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 214832 kb
Host smart-0267e51b-24e0-4175-b5c5-0e888665bb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49558003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.49558003
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.747651750
Short name T804
Test name
Test status
Simulation time 46027971 ps
CPU time 0.93 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 214980 kb
Host smart-fd8bfce8-aa6d-4935-9d7e-ce1285057c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747651750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.747651750
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3230127044
Short name T317
Test name
Test status
Simulation time 66514370 ps
CPU time 1.77 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 217724 kb
Host smart-7588b495-4e07-444c-8d88-f06558493c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230127044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3230127044
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3760100136
Short name T664
Test name
Test status
Simulation time 678992968403 ps
CPU time 1755.64 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:44:48 PM PDT 24
Peak memory 223764 kb
Host smart-28e809eb-f877-47df-bc69-dad9414832f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760100136 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3760100136
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1766502850
Short name T743
Test name
Test status
Simulation time 235377868 ps
CPU time 1.15 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 215308 kb
Host smart-149ce81d-0446-4d2b-b0ba-14d7c96ce25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766502850 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1766502850
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1667966847
Short name T303
Test name
Test status
Simulation time 16676298 ps
CPU time 0.96 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 206168 kb
Host smart-f0ff9dcf-cc66-4fe9-b272-eefd4390c33b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667966847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1667966847
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.4149748715
Short name T94
Test name
Test status
Simulation time 19550513 ps
CPU time 0.91 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 215908 kb
Host smart-6d8dbeb3-6392-4119-b0cb-a5932f3cfcfd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149748715 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4149748715
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2210563120
Short name T808
Test name
Test status
Simulation time 85832322 ps
CPU time 1.09 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:30 PM PDT 24
Peak memory 219324 kb
Host smart-5eefd4db-c5af-4298-b4fd-48af76768e86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210563120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2210563120
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2561300448
Short name T738
Test name
Test status
Simulation time 41272473 ps
CPU time 1.05 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 218360 kb
Host smart-c6bd7c67-b095-429a-8404-5199b072ee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561300448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2561300448
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.4246531281
Short name T415
Test name
Test status
Simulation time 70350755 ps
CPU time 1.43 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 219196 kb
Host smart-035d40a8-7517-4851-8815-3128b12469c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246531281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4246531281
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.155205253
Short name T572
Test name
Test status
Simulation time 95939872 ps
CPU time 0.88 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:29 PM PDT 24
Peak memory 214792 kb
Host smart-711e766b-f13e-40b9-9a66-ccf35afdb807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155205253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.155205253
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1189372166
Short name T473
Test name
Test status
Simulation time 19667305 ps
CPU time 0.98 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:32 PM PDT 24
Peak memory 214952 kb
Host smart-02141e2d-5065-4cee-bc88-f0ddc94eef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189372166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1189372166
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3526667837
Short name T580
Test name
Test status
Simulation time 598046081 ps
CPU time 3.57 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 216744 kb
Host smart-bd13e169-a7ab-4051-90d1-b681a6963f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526667837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3526667837
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2400874666
Short name T208
Test name
Test status
Simulation time 124415561575 ps
CPU time 657.86 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:26:27 PM PDT 24
Peak memory 219004 kb
Host smart-00da5c9f-ba94-4884-b607-72d28b41f84c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400874666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2400874666
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2783271767
Short name T129
Test name
Test status
Simulation time 72855196 ps
CPU time 1.08 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 215192 kb
Host smart-3f33b6db-4355-44bf-9cf9-f7b2a90d7753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783271767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2783271767
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.789804172
Short name T583
Test name
Test status
Simulation time 19898210 ps
CPU time 0.92 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 206116 kb
Host smart-3c9102e3-e344-400a-86cb-463e7f4a5dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789804172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.789804172
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1298957389
Short name T70
Test name
Test status
Simulation time 69379692 ps
CPU time 1.27 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 217032 kb
Host smart-c5a8c4b9-174b-4f0c-8bf7-8aa0f6dc95ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298957389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1298957389
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.3529716572
Short name T192
Test name
Test status
Simulation time 29685900 ps
CPU time 0.87 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 218984 kb
Host smart-b92ef32c-250a-40f8-be1d-eb903be65493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529716572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3529716572
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.763841164
Short name T690
Test name
Test status
Simulation time 55659945 ps
CPU time 1.27 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:32 PM PDT 24
Peak memory 219528 kb
Host smart-7a588285-35cf-4309-ba9e-9bb77d79e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763841164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.763841164
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.411995918
Short name T528
Test name
Test status
Simulation time 22996624 ps
CPU time 1.18 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:31 PM PDT 24
Peak memory 223488 kb
Host smart-75c0ddda-2a19-4275-ba1e-cf8e1f46fac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411995918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.411995918
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2724662067
Short name T711
Test name
Test status
Simulation time 14103796 ps
CPU time 0.94 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:15:32 PM PDT 24
Peak memory 214944 kb
Host smart-7ef45663-8236-4d05-b1b6-b1bad4b7304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724662067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2724662067
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3492847607
Short name T463
Test name
Test status
Simulation time 1137198406 ps
CPU time 5.02 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:38 PM PDT 24
Peak memory 216584 kb
Host smart-63d5975a-c789-4852-8695-841962a82683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492847607 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3492847607
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_alert.3501518591
Short name T719
Test name
Test status
Simulation time 34455480 ps
CPU time 1.27 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 215348 kb
Host smart-7763ea31-2810-4182-92b7-41390a15d519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501518591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3501518591
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2056056138
Short name T689
Test name
Test status
Simulation time 115975269 ps
CPU time 0.91 seconds
Started May 26 01:15:33 PM PDT 24
Finished May 26 01:15:36 PM PDT 24
Peak memory 206236 kb
Host smart-1f2b89b7-5e31-4563-8b33-6a1b341e06ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056056138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2056056138
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3419854914
Short name T758
Test name
Test status
Simulation time 22197194 ps
CPU time 0.94 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 216168 kb
Host smart-3d1e0b6b-5a73-4f5b-816e-64166ce02d98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419854914 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3419854914
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2726530301
Short name T651
Test name
Test status
Simulation time 91442534 ps
CPU time 0.94 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 223288 kb
Host smart-01ef06d6-2270-419a-bf0f-e394515b9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726530301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2726530301
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.356482496
Short name T439
Test name
Test status
Simulation time 43004008 ps
CPU time 1.41 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 217592 kb
Host smart-c4757564-2c8b-41f4-8103-26be79a3fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356482496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.356482496
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.485896261
Short name T154
Test name
Test status
Simulation time 20314582 ps
CPU time 1.11 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 215460 kb
Host smart-0702d621-a54b-47b1-8856-3b66ba03d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485896261 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.485896261
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1055792464
Short name T846
Test name
Test status
Simulation time 28914597 ps
CPU time 0.95 seconds
Started May 26 01:15:27 PM PDT 24
Finished May 26 01:15:29 PM PDT 24
Peak memory 214832 kb
Host smart-f4e675bf-b7c1-4218-9bd7-df411d9c7175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055792464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1055792464
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1495010486
Short name T162
Test name
Test status
Simulation time 231111337 ps
CPU time 3.49 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:37 PM PDT 24
Peak memory 214068 kb
Host smart-9d1e71a3-772f-45d0-8859-bf503fc88d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495010486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1495010486
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2347304913
Short name T768
Test name
Test status
Simulation time 27623684442 ps
CPU time 173.38 seconds
Started May 26 01:15:29 PM PDT 24
Finished May 26 01:18:23 PM PDT 24
Peak memory 217844 kb
Host smart-b20a6198-bcd2-4487-bdd5-36b2015b08e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347304913 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2347304913
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.4237190640
Short name T736
Test name
Test status
Simulation time 117251990 ps
CPU time 1.29 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 215120 kb
Host smart-4b534ffb-b79e-4daf-85b9-5fb7e19da8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237190640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.4237190640
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1150435748
Short name T571
Test name
Test status
Simulation time 61025778 ps
CPU time 0.89 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 206084 kb
Host smart-e94e981e-a1c4-4555-9c91-e9b293d2dadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150435748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1150435748
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4181377514
Short name T830
Test name
Test status
Simulation time 14956764 ps
CPU time 0.83 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 215000 kb
Host smart-b3afe7ea-432b-4adc-8201-15da70845208
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181377514 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4181377514
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2570133844
Short name T345
Test name
Test status
Simulation time 237531200 ps
CPU time 1.23 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 215652 kb
Host smart-bfec9c18-3ed4-4a9e-88da-687b62f04e66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570133844 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2570133844
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1522776003
Short name T99
Test name
Test status
Simulation time 26255305 ps
CPU time 1.33 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:36 PM PDT 24
Peak memory 229052 kb
Host smart-e5d9526f-e552-4702-a6ec-c6810663721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522776003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1522776003
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.69249142
Short name T62
Test name
Test status
Simulation time 36961341 ps
CPU time 1.32 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:35 PM PDT 24
Peak memory 216728 kb
Host smart-e4e13e3f-cc6c-4765-802b-6f2fe24fceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69249142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.69249142
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4082758558
Short name T414
Test name
Test status
Simulation time 61684760 ps
CPU time 0.97 seconds
Started May 26 01:15:31 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 223336 kb
Host smart-f68bf3ff-47a7-488b-ae81-15682fd604f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082758558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4082758558
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2362445031
Short name T238
Test name
Test status
Simulation time 20843700 ps
CPU time 0.99 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 214980 kb
Host smart-6a9c81ee-4197-4622-8f9b-fa41c2046bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362445031 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2362445031
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4065987868
Short name T452
Test name
Test status
Simulation time 313754576 ps
CPU time 5.92 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:46 PM PDT 24
Peak memory 216456 kb
Host smart-40bfedc3-2cc3-4fbb-9042-4daa578cd242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065987868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4065987868
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3006202132
Short name T363
Test name
Test status
Simulation time 51602265968 ps
CPU time 531.94 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:24:32 PM PDT 24
Peak memory 218260 kb
Host smart-a0922dc4-d322-4260-9202-795655992309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006202132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3006202132
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.559093962
Short name T169
Test name
Test status
Simulation time 48050431 ps
CPU time 1.21 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 215232 kb
Host smart-0c4dfac9-acc8-4b63-8992-abaeb4866926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559093962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.559093962
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2657750914
Short name T795
Test name
Test status
Simulation time 21020767 ps
CPU time 0.92 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 206144 kb
Host smart-84732662-89ef-43eb-9dc8-ad6683aa31ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657750914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2657750914
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3839735412
Short name T390
Test name
Test status
Simulation time 37278674 ps
CPU time 1.26 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 216360 kb
Host smart-454dec0c-8ad9-4470-b35a-52e1dcbaea20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839735412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3839735412
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.764154820
Short name T595
Test name
Test status
Simulation time 25664305 ps
CPU time 0.91 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:36 PM PDT 24
Peak memory 217996 kb
Host smart-6394c579-aeb6-4c47-9b8c-167e90ad2e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764154820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.764154820
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.623035502
Short name T88
Test name
Test status
Simulation time 94714648 ps
CPU time 1.49 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:33 PM PDT 24
Peak memory 218040 kb
Host smart-4e27c7cc-31e0-44e9-811c-66dbbc00c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623035502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.623035502
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.111037511
Short name T732
Test name
Test status
Simulation time 19945983 ps
CPU time 1.06 seconds
Started May 26 01:15:28 PM PDT 24
Finished May 26 01:15:30 PM PDT 24
Peak memory 215492 kb
Host smart-554e30ed-bc34-4792-a0c4-c691e367b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111037511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.111037511
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2455237581
Short name T305
Test name
Test status
Simulation time 16698669 ps
CPU time 1 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:34 PM PDT 24
Peak memory 214960 kb
Host smart-f8f9931d-74ca-42c4-bc83-f043fba83428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455237581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2455237581
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.66951098
Short name T504
Test name
Test status
Simulation time 578977162 ps
CPU time 6.03 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:15:39 PM PDT 24
Peak memory 215184 kb
Host smart-e131acd7-72f6-460b-8146-fb45d5cad21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66951098 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.66951098
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1867938698
Short name T801
Test name
Test status
Simulation time 65643303414 ps
CPU time 762.64 seconds
Started May 26 01:15:30 PM PDT 24
Finished May 26 01:28:15 PM PDT 24
Peak memory 223228 kb
Host smart-baf0bfb8-1fcc-4413-8b4c-3d66c82cfbe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867938698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1867938698
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1229234248
Short name T673
Test name
Test status
Simulation time 76058415 ps
CPU time 1.2 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 215232 kb
Host smart-8806a175-53a9-4ab0-836a-8abf220780c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229234248 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1229234248
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.538084220
Short name T770
Test name
Test status
Simulation time 60554175 ps
CPU time 0.98 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 206244 kb
Host smart-81316160-05c8-4a31-9b79-5de90a7bfcfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538084220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.538084220
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4132858167
Short name T80
Test name
Test status
Simulation time 18338829 ps
CPU time 0.88 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 215168 kb
Host smart-85bf271d-793d-49ef-82b3-a49f20b5f109
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132858167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4132858167
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3055446993
Short name T239
Test name
Test status
Simulation time 76509596 ps
CPU time 1.01 seconds
Started May 26 01:15:41 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 215336 kb
Host smart-5720f244-2efc-4314-ad1c-871f6284f620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055446993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3055446993
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3569131319
Short name T757
Test name
Test status
Simulation time 18720404 ps
CPU time 1.03 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 218112 kb
Host smart-50d95260-a90e-4ec9-b0c5-50aee86f72dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569131319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3569131319
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3521401953
Short name T685
Test name
Test status
Simulation time 45917336 ps
CPU time 1.54 seconds
Started May 26 01:15:32 PM PDT 24
Finished May 26 01:15:36 PM PDT 24
Peak memory 218076 kb
Host smart-e13ce243-5f2d-43ea-bc18-e922521f623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521401953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3521401953
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1477829887
Short name T341
Test name
Test status
Simulation time 21812585 ps
CPU time 1.04 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 215028 kb
Host smart-a54981f4-a6c7-4e92-a3c8-ec92156c13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477829887 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1477829887
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1502910537
Short name T642
Test name
Test status
Simulation time 43667302 ps
CPU time 0.88 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 214864 kb
Host smart-76435bf2-98e2-44b7-9f9a-39feff0823a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502910537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1502910537
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1470732723
Short name T459
Test name
Test status
Simulation time 970745838 ps
CPU time 1.66 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 214904 kb
Host smart-7e482bad-c346-4326-881b-c7b2d3558ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470732723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1470732723
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.469310623
Short name T613
Test name
Test status
Simulation time 204189276105 ps
CPU time 1446.85 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:39:50 PM PDT 24
Peak memory 232976 kb
Host smart-654a73cd-bc7c-427a-97c5-04b1ce97af8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469310623 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.469310623
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.774302553
Short name T171
Test name
Test status
Simulation time 26767579 ps
CPU time 1.23 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:15:45 PM PDT 24
Peak memory 215312 kb
Host smart-672aba25-3153-45b8-ba89-b6b28043667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774302553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.774302553
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1200358815
Short name T307
Test name
Test status
Simulation time 37847600 ps
CPU time 1.03 seconds
Started May 26 01:15:39 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 214604 kb
Host smart-941bc0c0-6469-4d13-92f2-e51878d2d740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200358815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1200358815
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3694583480
Short name T190
Test name
Test status
Simulation time 14133755 ps
CPU time 0.92 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 216156 kb
Host smart-db261582-434f-4bf0-bfe1-175093db3bdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694583480 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3694583480
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1852709264
Short name T517
Test name
Test status
Simulation time 39854687 ps
CPU time 1.4 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 216704 kb
Host smart-97d28a8c-51f3-4a9c-a9be-f1c910b08ed3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852709264 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1852709264
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3149759243
Short name T435
Test name
Test status
Simulation time 20721568 ps
CPU time 1.02 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 218080 kb
Host smart-95aab8d1-6385-4c40-aecd-eb7669beabec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149759243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3149759243
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4103463866
Short name T2
Test name
Test status
Simulation time 54502662 ps
CPU time 1.25 seconds
Started May 26 01:15:36 PM PDT 24
Finished May 26 01:15:38 PM PDT 24
Peak memory 216612 kb
Host smart-bded7a8a-1097-441e-8c47-8093fd7f71be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103463866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4103463866
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1585039084
Short name T680
Test name
Test status
Simulation time 22127613 ps
CPU time 1.12 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 215040 kb
Host smart-d30537f1-8bc7-4c0a-a117-ea62cd4cec06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585039084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1585039084
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2151406164
Short name T837
Test name
Test status
Simulation time 23510472 ps
CPU time 0.97 seconds
Started May 26 01:15:39 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 214816 kb
Host smart-56d56d84-7d18-447f-8ccd-247b71218c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151406164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2151406164
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.982249446
Short name T471
Test name
Test status
Simulation time 144702917 ps
CPU time 2.56 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 214820 kb
Host smart-cae0cf3b-b58c-48c0-8d61-93fdaa167ced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982249446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.982249446
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1856042709
Short name T202
Test name
Test status
Simulation time 42529511720 ps
CPU time 576.35 seconds
Started May 26 01:15:42 PM PDT 24
Finished May 26 01:25:19 PM PDT 24
Peak memory 220776 kb
Host smart-8508f889-a0ed-424d-9c8d-ee80597052cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856042709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1856042709
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3487198988
Short name T148
Test name
Test status
Simulation time 30393891 ps
CPU time 1.28 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 215404 kb
Host smart-c05ec890-e692-4961-aa2b-9ed7399dde60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487198988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3487198988
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.31816962
Short name T69
Test name
Test status
Simulation time 23185313 ps
CPU time 0.88 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 206104 kb
Host smart-8b21daa2-7535-499b-ab6e-b055beda87b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31816962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.31816962
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1689715623
Short name T332
Test name
Test status
Simulation time 50586142 ps
CPU time 1.58 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 216380 kb
Host smart-3df058de-fc95-4e92-a8d4-689b9c0b1124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689715623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1689715623
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2659667292
Short name T100
Test name
Test status
Simulation time 25122964 ps
CPU time 1 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:39 PM PDT 24
Peak memory 219236 kb
Host smart-18875594-a6ee-4150-ac7c-bbc3899c359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659667292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2659667292
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3841462260
Short name T429
Test name
Test status
Simulation time 41449008 ps
CPU time 1.55 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 217848 kb
Host smart-6d349f8a-8915-4905-a59f-e761846967ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841462260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3841462260
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.600147342
Short name T790
Test name
Test status
Simulation time 32516287 ps
CPU time 0.86 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:41 PM PDT 24
Peak memory 215112 kb
Host smart-d016007d-65be-4b52-8aac-019e2156e379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600147342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.600147342
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.164207962
Short name T516
Test name
Test status
Simulation time 53286471 ps
CPU time 0.94 seconds
Started May 26 01:15:42 PM PDT 24
Finished May 26 01:15:44 PM PDT 24
Peak memory 214960 kb
Host smart-053bcca2-1f34-47cb-960d-3791fe10e96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164207962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.164207962
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2535774780
Short name T665
Test name
Test status
Simulation time 150832979 ps
CPU time 2.46 seconds
Started May 26 01:15:41 PM PDT 24
Finished May 26 01:15:45 PM PDT 24
Peak memory 216256 kb
Host smart-80a3df1b-c060-41fb-87eb-377c4d12a80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535774780 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2535774780
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.319520886
Short name T641
Test name
Test status
Simulation time 29316987512 ps
CPU time 383.46 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:22:01 PM PDT 24
Peak memory 218540 kb
Host smart-294307a3-d8f2-413d-a1aa-c6a8f11a145c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319520886 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.319520886
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1803634695
Short name T150
Test name
Test status
Simulation time 63484239 ps
CPU time 1.19 seconds
Started May 26 01:14:33 PM PDT 24
Finished May 26 01:14:36 PM PDT 24
Peak memory 215432 kb
Host smart-6b6247c2-fdd5-4b36-93f5-16940b7cd46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803634695 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1803634695
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2673501635
Short name T553
Test name
Test status
Simulation time 28806667 ps
CPU time 0.96 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 214368 kb
Host smart-4255a567-891b-4590-99b0-3103f96f9171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673501635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2673501635
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.863795855
Short name T198
Test name
Test status
Simulation time 79847017 ps
CPU time 0.9 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:30 PM PDT 24
Peak memory 215152 kb
Host smart-1e69a39b-8ed1-4071-b2dd-cb4c6ed72b3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863795855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.863795855
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3786989045
Short name T41
Test name
Test status
Simulation time 48623297 ps
CPU time 1.24 seconds
Started May 26 01:14:33 PM PDT 24
Finished May 26 01:14:35 PM PDT 24
Peak memory 216424 kb
Host smart-0fca9d1a-985f-4035-95e0-800b82637432
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786989045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3786989045
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.868563390
Short name T56
Test name
Test status
Simulation time 25645731 ps
CPU time 1.05 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:35 PM PDT 24
Peak memory 223364 kb
Host smart-ac45a6dc-fc2b-44c6-a9c5-30c9330d734a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868563390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.868563390
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1830771049
Short name T820
Test name
Test status
Simulation time 35323182 ps
CPU time 1.3 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 216844 kb
Host smart-9696c92f-43e9-460a-a162-27d2727450f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830771049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1830771049
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1437501946
Short name T53
Test name
Test status
Simulation time 36782892 ps
CPU time 0.97 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 223444 kb
Host smart-184f4f53-3caa-4c23-9b09-89286cd6e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437501946 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1437501946
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2710244433
Short name T267
Test name
Test status
Simulation time 35668373 ps
CPU time 0.95 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:34 PM PDT 24
Peak memory 206716 kb
Host smart-7da9b8a1-c0c4-4dd6-8447-510537ea4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710244433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2710244433
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1394293735
Short name T58
Test name
Test status
Simulation time 875480351 ps
CPU time 7.33 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:38 PM PDT 24
Peak memory 235408 kb
Host smart-bbfdfc80-6192-4a8a-b32e-9626455d8c46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394293735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1394293735
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.193180423
Short name T756
Test name
Test status
Simulation time 35281796 ps
CPU time 0.88 seconds
Started May 26 01:14:36 PM PDT 24
Finished May 26 01:14:38 PM PDT 24
Peak memory 214936 kb
Host smart-836ba77e-0bd1-467e-a385-c8ec3c6de2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193180423 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.193180423
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1267448885
Short name T601
Test name
Test status
Simulation time 287804186 ps
CPU time 4.78 seconds
Started May 26 01:14:34 PM PDT 24
Finished May 26 01:14:40 PM PDT 24
Peak memory 216500 kb
Host smart-75f6d1d4-dc2b-41b5-bd12-2b9c1ae9d361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267448885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1267448885
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3154996844
Short name T207
Test name
Test status
Simulation time 141300123713 ps
CPU time 1627.91 seconds
Started May 26 01:14:31 PM PDT 24
Finished May 26 01:41:40 PM PDT 24
Peak memory 224064 kb
Host smart-b68d2cf8-878b-4813-8eb3-58aeb7aed7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154996844 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3154996844
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2887971236
Short name T833
Test name
Test status
Simulation time 25028827 ps
CPU time 1.21 seconds
Started May 26 01:15:44 PM PDT 24
Finished May 26 01:15:46 PM PDT 24
Peak memory 215260 kb
Host smart-1fa0468f-b5ef-4b31-8c78-4b54fd8064ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887971236 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2887971236
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.580150953
Short name T344
Test name
Test status
Simulation time 81299050 ps
CPU time 0.87 seconds
Started May 26 01:15:44 PM PDT 24
Finished May 26 01:15:46 PM PDT 24
Peak memory 206176 kb
Host smart-c33cb65c-a3a9-41e5-a669-dfff77efdb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580150953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.580150953
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.172599437
Short name T140
Test name
Test status
Simulation time 11372863 ps
CPU time 0.88 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:15:44 PM PDT 24
Peak memory 215924 kb
Host smart-55c91d66-6a24-41c2-8ee0-e7fafcf20eb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172599437 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.172599437
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1364685138
Short name T97
Test name
Test status
Simulation time 46235666 ps
CPU time 1.12 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 216708 kb
Host smart-681f7e06-61af-44c0-a7ff-a2c70b1a3071
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364685138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1364685138
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1128280937
Short name T180
Test name
Test status
Simulation time 39913261 ps
CPU time 0.95 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 218292 kb
Host smart-c7c8c5a3-3b8a-4170-838e-f777c93807a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128280937 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1128280937
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.138469494
Short name T521
Test name
Test status
Simulation time 109016296 ps
CPU time 1.69 seconds
Started May 26 01:15:41 PM PDT 24
Finished May 26 01:15:44 PM PDT 24
Peak memory 218444 kb
Host smart-14d7e0c2-6463-4be9-83b2-e6274b2b3ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138469494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.138469494
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1835773607
Short name T712
Test name
Test status
Simulation time 24786367 ps
CPU time 0.94 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 215132 kb
Host smart-2fd084d7-4ac6-4899-97e5-93ca39f35d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835773607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1835773607
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3661407155
Short name T365
Test name
Test status
Simulation time 29429500 ps
CPU time 0.9 seconds
Started May 26 01:15:39 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 215196 kb
Host smart-e1c060ad-95d1-43a0-96c6-a90066e7dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661407155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3661407155
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1073639541
Short name T214
Test name
Test status
Simulation time 289935134 ps
CPU time 2.14 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:15:44 PM PDT 24
Peak memory 215020 kb
Host smart-d07de655-00e6-4e02-a78f-14b8345ec1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073639541 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1073639541
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1937646292
Short name T282
Test name
Test status
Simulation time 161843841085 ps
CPU time 760.94 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:28:19 PM PDT 24
Peak memory 221764 kb
Host smart-d32c7c55-1850-4750-90ad-939cbc8e3712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937646292 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1937646292
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.484465015
Short name T270
Test name
Test status
Simulation time 117875097 ps
CPU time 1.26 seconds
Started May 26 01:15:39 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 215260 kb
Host smart-8e090782-53db-4386-97e8-0dda8b3e8576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484465015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.484465015
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3002109986
Short name T302
Test name
Test status
Simulation time 18652004 ps
CPU time 0.93 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:15:45 PM PDT 24
Peak memory 214376 kb
Host smart-669e47ea-5891-4380-ab05-2cf43c5c1e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002109986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3002109986
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3866052257
Short name T715
Test name
Test status
Simulation time 37292747 ps
CPU time 0.88 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 216048 kb
Host smart-4d204a08-ceb5-4535-8d7d-36d8cb90ee05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866052257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3866052257
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1881005672
Short name T102
Test name
Test status
Simulation time 126375869 ps
CPU time 1.25 seconds
Started May 26 01:15:37 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 216624 kb
Host smart-f6cd66d9-ba03-483c-91d0-02bd2f1ab085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881005672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1881005672
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.350775238
Short name T191
Test name
Test status
Simulation time 23995713 ps
CPU time 0.94 seconds
Started May 26 01:15:36 PM PDT 24
Finished May 26 01:15:37 PM PDT 24
Peak memory 218072 kb
Host smart-910ad453-b390-4a9a-9215-c28db58854c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350775238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.350775238
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1990575306
Short name T295
Test name
Test status
Simulation time 64411860 ps
CPU time 1.98 seconds
Started May 26 01:15:41 PM PDT 24
Finished May 26 01:15:44 PM PDT 24
Peak memory 217956 kb
Host smart-c16997fc-c3e4-4e9d-b32b-20d6bcfc4f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990575306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1990575306
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2068198401
Short name T767
Test name
Test status
Simulation time 27226469 ps
CPU time 0.97 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:15:45 PM PDT 24
Peak memory 215096 kb
Host smart-2b3038c4-b3a9-410e-8926-8f94a0778922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068198401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2068198401
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1872751038
Short name T791
Test name
Test status
Simulation time 17425499 ps
CPU time 1 seconds
Started May 26 01:15:41 PM PDT 24
Finished May 26 01:15:43 PM PDT 24
Peak memory 206644 kb
Host smart-50066c24-294a-43f2-8c74-dfc99e2a691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872751038 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1872751038
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2935379401
Short name T612
Test name
Test status
Simulation time 754040339 ps
CPU time 4.31 seconds
Started May 26 01:15:43 PM PDT 24
Finished May 26 01:15:48 PM PDT 24
Peak memory 216572 kb
Host smart-106f5452-d9bb-4e68-b221-e348aaae3a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935379401 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2935379401
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2748193329
Short name T666
Test name
Test status
Simulation time 7736779464 ps
CPU time 190.24 seconds
Started May 26 01:15:40 PM PDT 24
Finished May 26 01:18:52 PM PDT 24
Peak memory 221572 kb
Host smart-d6c2087c-1d11-4470-9f27-4f4fd3881e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748193329 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2748193329
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2664233820
Short name T170
Test name
Test status
Simulation time 27300216 ps
CPU time 1.32 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:48 PM PDT 24
Peak memory 215224 kb
Host smart-362d984f-242e-445a-927c-0b4a7ef0a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664233820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2664233820
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3827772504
Short name T455
Test name
Test status
Simulation time 37713180 ps
CPU time 1.01 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 206272 kb
Host smart-6374a18c-1bcb-4a48-9937-173c80043740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827772504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3827772504
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3127936859
Short name T593
Test name
Test status
Simulation time 15643312 ps
CPU time 0.91 seconds
Started May 26 01:15:44 PM PDT 24
Finished May 26 01:15:46 PM PDT 24
Peak memory 216036 kb
Host smart-d065e84b-4b6d-4b55-824d-ed25d288f8b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127936859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3127936859
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.2927780645
Short name T151
Test name
Test status
Simulation time 22703658 ps
CPU time 1.08 seconds
Started May 26 01:15:50 PM PDT 24
Finished May 26 01:15:52 PM PDT 24
Peak memory 229016 kb
Host smart-1c7b9ce9-bdd7-424d-a3b4-8c65a40d974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927780645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2927780645
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1549890113
Short name T676
Test name
Test status
Simulation time 66431130 ps
CPU time 1.24 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 216808 kb
Host smart-dfa95852-da6c-48ed-afbb-8f1051601232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549890113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1549890113
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_smoke.1984519868
Short name T437
Test name
Test status
Simulation time 121637496 ps
CPU time 0.92 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:40 PM PDT 24
Peak memory 214832 kb
Host smart-eab0e451-d051-4384-b9a6-bbf8128b43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984519868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1984519868
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.171877400
Short name T271
Test name
Test status
Simulation time 162050855 ps
CPU time 1.23 seconds
Started May 26 01:15:38 PM PDT 24
Finished May 26 01:15:42 PM PDT 24
Peak memory 214820 kb
Host smart-b129b6c4-95f3-4362-ac6d-84839edbef4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171877400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.171877400
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3929833219
Short name T828
Test name
Test status
Simulation time 19217575977 ps
CPU time 437.63 seconds
Started May 26 01:15:42 PM PDT 24
Finished May 26 01:23:00 PM PDT 24
Peak memory 218408 kb
Host smart-d699c0b2-c40e-44bb-8706-80fe7739601f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929833219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3929833219
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2445200026
Short name T604
Test name
Test status
Simulation time 27819276 ps
CPU time 1.23 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:48 PM PDT 24
Peak memory 215224 kb
Host smart-c80e3509-3866-4a6d-aa08-1c2086439e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445200026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2445200026
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.522771459
Short name T564
Test name
Test status
Simulation time 14274622 ps
CPU time 0.9 seconds
Started May 26 01:15:45 PM PDT 24
Finished May 26 01:15:47 PM PDT 24
Peak memory 206216 kb
Host smart-593e8873-ad38-4071-96bf-588025db52c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522771459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.522771459
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1330844271
Short name T577
Test name
Test status
Simulation time 43250316 ps
CPU time 0.89 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 215984 kb
Host smart-22c803d1-7fc2-4b7e-875e-51f93c0d8315
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330844271 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1330844271
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1328966156
Short name T643
Test name
Test status
Simulation time 39779889 ps
CPU time 1.29 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 216532 kb
Host smart-cbd9fae4-6dd1-4f96-9d49-3a496d43f0d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328966156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1328966156
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1899460774
Short name T127
Test name
Test status
Simulation time 27715665 ps
CPU time 0.92 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 215024 kb
Host smart-f1e0061d-3214-410a-bcb2-0ba37e4648a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899460774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1899460774
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2446435411
Short name T640
Test name
Test status
Simulation time 57083931 ps
CPU time 1.33 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 218024 kb
Host smart-6e4a8465-8511-4326-9560-5c76181bf80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446435411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2446435411
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2120229364
Short name T34
Test name
Test status
Simulation time 19954083 ps
CPU time 1.06 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 215208 kb
Host smart-29b128e0-f6e1-498f-b556-793058bc69a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120229364 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2120229364
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.551459086
Short name T619
Test name
Test status
Simulation time 129753931 ps
CPU time 0.96 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 215000 kb
Host smart-53cb2653-cd02-43a6-a030-ec89f96a7997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551459086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.551459086
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1755795115
Short name T464
Test name
Test status
Simulation time 451553595 ps
CPU time 3.22 seconds
Started May 26 01:15:45 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 216512 kb
Host smart-b4ab1bf9-4124-4e78-90d0-cc8475194fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755795115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1755795115
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2446810908
Short name T201
Test name
Test status
Simulation time 202180054066 ps
CPU time 936.63 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:31:24 PM PDT 24
Peak memory 231400 kb
Host smart-d75d178c-e593-4090-81ae-7f882c4baa51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446810908 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2446810908
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3483666894
Short name T149
Test name
Test status
Simulation time 69741443 ps
CPU time 1.13 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:52 PM PDT 24
Peak memory 215236 kb
Host smart-98228d3c-591f-476b-9ab7-20c3086d5d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483666894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3483666894
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3882703295
Short name T23
Test name
Test status
Simulation time 43034084 ps
CPU time 0.88 seconds
Started May 26 01:15:51 PM PDT 24
Finished May 26 01:15:53 PM PDT 24
Peak memory 206160 kb
Host smart-bebe464b-8ce0-4339-ab96-b859ad063231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882703295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3882703295
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2245319182
Short name T120
Test name
Test status
Simulation time 20013050 ps
CPU time 0.83 seconds
Started May 26 01:15:45 PM PDT 24
Finished May 26 01:15:47 PM PDT 24
Peak memory 215092 kb
Host smart-b300ac2e-3aba-4166-820d-9d24609ebb1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245319182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2245319182
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1509560897
Short name T343
Test name
Test status
Simulation time 36823849 ps
CPU time 1.19 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 216464 kb
Host smart-4dec3712-f8d6-48be-bda2-0cc40d217b70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509560897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1509560897
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2927893731
Short name T185
Test name
Test status
Simulation time 89076743 ps
CPU time 1.19 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 224112 kb
Host smart-4cecce8f-9e52-43fa-ace8-730514de15f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927893731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2927893731
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1137103317
Short name T592
Test name
Test status
Simulation time 68892994 ps
CPU time 1.32 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:15:55 PM PDT 24
Peak memory 218196 kb
Host smart-dc1fd6dd-0f7a-4003-b0c4-d8b929d59463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137103317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1137103317
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3768016273
Short name T476
Test name
Test status
Simulation time 31164685 ps
CPU time 0.97 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:48 PM PDT 24
Peak memory 223468 kb
Host smart-8cd0bb6a-8a05-4de6-8790-233dc529a3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768016273 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3768016273
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1162149191
Short name T523
Test name
Test status
Simulation time 23842973 ps
CPU time 0.95 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 214868 kb
Host smart-b1d0da11-446f-4181-9e0c-dbf78a53ffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162149191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1162149191
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2200593072
Short name T246
Test name
Test status
Simulation time 226155348 ps
CPU time 3.08 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 214964 kb
Host smart-d5e8d5d3-06cb-48e4-9244-73358093a275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200593072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2200593072
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3203816484
Short name T334
Test name
Test status
Simulation time 89466089148 ps
CPU time 1157.16 seconds
Started May 26 01:15:50 PM PDT 24
Finished May 26 01:35:08 PM PDT 24
Peak memory 223812 kb
Host smart-7d999dfe-3819-4b70-9064-985514e64d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203816484 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3203816484
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2595523654
Short name T255
Test name
Test status
Simulation time 181637088 ps
CPU time 1.28 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 215356 kb
Host smart-6d2fc72e-04e9-4ff2-a8b0-e83de5438c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595523654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2595523654
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.456490222
Short name T569
Test name
Test status
Simulation time 13505360 ps
CPU time 0.92 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 206772 kb
Host smart-8de8e974-6a57-4acf-9417-6d6b13ed8c28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456490222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.456490222
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2673991538
Short name T139
Test name
Test status
Simulation time 11892921 ps
CPU time 0.9 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 216204 kb
Host smart-6b62375b-9aa5-4ff7-9540-828c2de45add
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673991538 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2673991538
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2413788028
Short name T754
Test name
Test status
Simulation time 38409059 ps
CPU time 1.33 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 216580 kb
Host smart-3083fedb-2bac-4bd2-9094-624de7b9f487
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413788028 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2413788028
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.4097954736
Short name T675
Test name
Test status
Simulation time 21843421 ps
CPU time 0.93 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 217904 kb
Host smart-0bd43e50-3a00-471c-85cc-af8f26f8263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097954736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.4097954736
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.574480968
Short name T461
Test name
Test status
Simulation time 39068833 ps
CPU time 1.04 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 218008 kb
Host smart-2c0a7f20-b427-438b-b169-7c98af8bd3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574480968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.574480968
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4160241545
Short name T36
Test name
Test status
Simulation time 37095448 ps
CPU time 0.88 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:48 PM PDT 24
Peak memory 215180 kb
Host smart-12080306-d47d-4017-b6e5-5f7cc452557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160241545 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4160241545
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1850083938
Short name T691
Test name
Test status
Simulation time 18085982 ps
CPU time 0.99 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 214892 kb
Host smart-594a20ec-3f3d-4b50-8f2d-feb33bee3872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850083938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1850083938
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3136849089
Short name T500
Test name
Test status
Simulation time 930488941 ps
CPU time 4.71 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 216672 kb
Host smart-38a96f13-b2fc-4293-b93f-b8275f007663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136849089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3136849089
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1484407381
Short name T646
Test name
Test status
Simulation time 83103088935 ps
CPU time 491.82 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:24:00 PM PDT 24
Peak memory 218016 kb
Host smart-8b8c9336-aa12-4caf-a440-d1b29894b3bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484407381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1484407381
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2125057608
Short name T710
Test name
Test status
Simulation time 28137696 ps
CPU time 1.28 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:15:56 PM PDT 24
Peak memory 215340 kb
Host smart-20ec4f30-bfa0-4ecb-bcc6-4b95fa8a668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125057608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2125057608
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2444934178
Short name T323
Test name
Test status
Simulation time 15578450 ps
CPU time 0.97 seconds
Started May 26 01:15:51 PM PDT 24
Finished May 26 01:15:53 PM PDT 24
Peak memory 206152 kb
Host smart-d91ba3a7-2a44-4473-aeb3-ed6498a1a539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444934178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2444934178
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3936672976
Short name T51
Test name
Test status
Simulation time 45667702 ps
CPU time 0.86 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 215628 kb
Host smart-2553e3e8-bb3d-443b-8d91-5c25fdb9a6e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936672976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3936672976
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1223113268
Short name T116
Test name
Test status
Simulation time 59475381 ps
CPU time 1.32 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 216552 kb
Host smart-1aa6f405-14f6-414e-b1cf-d8eeec775379
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223113268 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1223113268
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3924313200
Short name T5
Test name
Test status
Simulation time 58879918 ps
CPU time 1.02 seconds
Started May 26 01:15:51 PM PDT 24
Finished May 26 01:15:53 PM PDT 24
Peak memory 217952 kb
Host smart-91eb45fe-b2bd-433f-a9da-6fbf23d47cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924313200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3924313200
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.4272726429
Short name T426
Test name
Test status
Simulation time 115958486 ps
CPU time 1.27 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:50 PM PDT 24
Peak memory 217916 kb
Host smart-82679dd0-bc5a-4a35-ac5f-276c5cdb8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272726429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.4272726429
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.130119837
Short name T832
Test name
Test status
Simulation time 27543134 ps
CPU time 1.11 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:15:55 PM PDT 24
Peak memory 223528 kb
Host smart-a8c68ddf-a354-4762-9f4c-ea4d5b2c1047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130119837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.130119837
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1056224157
Short name T695
Test name
Test status
Simulation time 36993255 ps
CPU time 0.93 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 214904 kb
Host smart-1bd7668d-f14f-495f-8377-62206b64c32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056224157 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1056224157
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1820268226
Short name T167
Test name
Test status
Simulation time 459383431 ps
CPU time 2.68 seconds
Started May 26 01:15:47 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 214952 kb
Host smart-24066d78-485b-4c72-aa38-23341048e510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820268226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1820268226
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3496481915
Short name T581
Test name
Test status
Simulation time 447255194044 ps
CPU time 960.66 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:31:55 PM PDT 24
Peak memory 220548 kb
Host smart-a4b2ed92-d32f-47f0-8c45-3e78545086b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496481915 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3496481915
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2528627353
Short name T730
Test name
Test status
Simulation time 161835760 ps
CPU time 1.37 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:52 PM PDT 24
Peak memory 215408 kb
Host smart-3a7fda1f-67b5-42d4-a4f2-925346433003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528627353 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2528627353
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.281843355
Short name T605
Test name
Test status
Simulation time 26516807 ps
CPU time 0.92 seconds
Started May 26 01:15:58 PM PDT 24
Finished May 26 01:16:01 PM PDT 24
Peak memory 206252 kb
Host smart-23a68187-bda6-47df-9c11-d7857a1465d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281843355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.281843355
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4058237676
Short name T539
Test name
Test status
Simulation time 48928417 ps
CPU time 0.85 seconds
Started May 26 01:15:52 PM PDT 24
Finished May 26 01:15:54 PM PDT 24
Peak memory 215996 kb
Host smart-0591459a-aa73-49e5-9e1f-92481ecbaa32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058237676 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4058237676
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3493660516
Short name T369
Test name
Test status
Simulation time 48749168 ps
CPU time 1.28 seconds
Started May 26 01:15:46 PM PDT 24
Finished May 26 01:15:49 PM PDT 24
Peak memory 219012 kb
Host smart-58069cca-5501-4a0a-8131-f2999003bef1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493660516 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3493660516
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1320543238
Short name T836
Test name
Test status
Simulation time 43643770 ps
CPU time 1.22 seconds
Started May 26 01:15:52 PM PDT 24
Finished May 26 01:15:54 PM PDT 24
Peak memory 224916 kb
Host smart-2af5560e-7b3d-4650-906a-7adf58b450a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320543238 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1320543238
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3182092706
Short name T335
Test name
Test status
Simulation time 34805414 ps
CPU time 1.42 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:52 PM PDT 24
Peak memory 216808 kb
Host smart-e9e903cb-de9f-49e5-8c6a-f169ff2c84ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182092706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3182092706
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1230643374
Short name T525
Test name
Test status
Simulation time 22057798 ps
CPU time 1.12 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:52 PM PDT 24
Peak memory 215036 kb
Host smart-506aa284-881c-46c4-90a5-1f541789b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230643374 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1230643374
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.19784963
Short name T408
Test name
Test status
Simulation time 22062171 ps
CPU time 0.99 seconds
Started May 26 01:15:48 PM PDT 24
Finished May 26 01:15:51 PM PDT 24
Peak memory 214968 kb
Host smart-49b30e0d-3742-47cd-a2a6-cf5c29a96752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19784963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.19784963
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.4048340695
Short name T692
Test name
Test status
Simulation time 416232143 ps
CPU time 7.32 seconds
Started May 26 01:15:49 PM PDT 24
Finished May 26 01:15:58 PM PDT 24
Peak memory 216608 kb
Host smart-da427aa0-48ad-4757-957b-3fb1c72f62a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048340695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.4048340695
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2100009237
Short name T533
Test name
Test status
Simulation time 25053871051 ps
CPU time 420.3 seconds
Started May 26 01:15:52 PM PDT 24
Finished May 26 01:22:53 PM PDT 24
Peak memory 218036 kb
Host smart-0888618e-92ab-43ef-ade7-ef3e8a0b40ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100009237 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2100009237
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2863867407
Short name T85
Test name
Test status
Simulation time 92691981 ps
CPU time 1.19 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:57 PM PDT 24
Peak memory 215588 kb
Host smart-16479503-3994-4688-b226-bbeaf30a57d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863867407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2863867407
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2652718980
Short name T314
Test name
Test status
Simulation time 24365971 ps
CPU time 0.98 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 206180 kb
Host smart-bf6522d1-9ce1-496e-8c4a-69155600435c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652718980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2652718980
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.582719758
Short name T144
Test name
Test status
Simulation time 18132570 ps
CPU time 0.95 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 216028 kb
Host smart-8efcc5a2-d06b-4514-b877-036d514d3d86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582719758 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.582719758
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3854276236
Short name T616
Test name
Test status
Simulation time 44032545 ps
CPU time 1.31 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:57 PM PDT 24
Peak memory 216516 kb
Host smart-2096a9d9-35a0-40aa-a50e-adf6a4c1f426
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854276236 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3854276236
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2199062968
Short name T110
Test name
Test status
Simulation time 25697691 ps
CPU time 1.26 seconds
Started May 26 01:15:54 PM PDT 24
Finished May 26 01:15:56 PM PDT 24
Peak memory 220160 kb
Host smart-8f0dddf4-dfd7-40f5-a56b-581f98d331bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199062968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2199062968
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_intr.3401486232
Short name T156
Test name
Test status
Simulation time 27221972 ps
CPU time 1.04 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:15:58 PM PDT 24
Peak memory 215212 kb
Host smart-18f1bb31-c368-4b5d-9e93-53c88a5f072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401486232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3401486232
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.876577658
Short name T769
Test name
Test status
Simulation time 18084494 ps
CPU time 0.89 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:58 PM PDT 24
Peak memory 214940 kb
Host smart-631a8f45-d293-42ff-97f0-0a0ff35b8b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876577658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.876577658
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2416116868
Short name T610
Test name
Test status
Simulation time 221577757 ps
CPU time 4.17 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:16:02 PM PDT 24
Peak memory 219848 kb
Host smart-db203d16-590b-4947-a3ef-41fa9f9e451e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416116868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2416116868
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.8075606
Short name T660
Test name
Test status
Simulation time 57934657854 ps
CPU time 742.29 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:28:21 PM PDT 24
Peak memory 223304 kb
Host smart-ac2ece46-026b-4c71-b93b-05134102383a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8075606 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.8075606
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2543249396
Short name T16
Test name
Test status
Simulation time 250295639 ps
CPU time 1.48 seconds
Started May 26 01:15:53 PM PDT 24
Finished May 26 01:15:55 PM PDT 24
Peak memory 215304 kb
Host smart-40a3528c-f143-4767-8843-621e9194a816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543249396 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2543249396
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2529598586
Short name T586
Test name
Test status
Simulation time 24399805 ps
CPU time 0.86 seconds
Started May 26 01:15:54 PM PDT 24
Finished May 26 01:15:56 PM PDT 24
Peak memory 206128 kb
Host smart-7adbe628-c297-440b-a0af-97aab7741809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529598586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2529598586
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.4282349030
Short name T194
Test name
Test status
Simulation time 10685210 ps
CPU time 0.98 seconds
Started May 26 01:15:54 PM PDT 24
Finished May 26 01:15:56 PM PDT 24
Peak memory 215852 kb
Host smart-ab81d573-bb1b-4f97-87fb-6ccc6033efec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282349030 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4282349030
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2496895669
Short name T83
Test name
Test status
Simulation time 30811954 ps
CPU time 1.13 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:57 PM PDT 24
Peak memory 216524 kb
Host smart-3fe28f18-bb17-49bb-8deb-de43600c7bce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496895669 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2496895669
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2680919790
Short name T508
Test name
Test status
Simulation time 18682000 ps
CPU time 1.09 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:57 PM PDT 24
Peak memory 218084 kb
Host smart-f47d06e6-6a23-4a90-a114-fa36b5908996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680919790 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2680919790
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2872378298
Short name T352
Test name
Test status
Simulation time 88773141 ps
CPU time 2 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 219400 kb
Host smart-19f0c351-7947-4a93-9c76-c64a87a37f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872378298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2872378298
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.107786419
Short name T752
Test name
Test status
Simulation time 39811030 ps
CPU time 0.93 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 215172 kb
Host smart-e2904ed7-0a6c-4359-a13c-74fe5512e1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107786419 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.107786419
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3156013511
Short name T684
Test name
Test status
Simulation time 27948294 ps
CPU time 0.96 seconds
Started May 26 01:16:00 PM PDT 24
Finished May 26 01:16:02 PM PDT 24
Peak memory 214956 kb
Host smart-aaea7838-4c16-4481-8212-0c92c7c4f30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156013511 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3156013511
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1489830089
Short name T829
Test name
Test status
Simulation time 205409578 ps
CPU time 2.75 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 216612 kb
Host smart-51da51f5-6cd2-4917-9db9-6d0305d4b816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489830089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1489830089
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1222903690
Short name T160
Test name
Test status
Simulation time 21828789589 ps
CPU time 515.17 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:24:33 PM PDT 24
Peak memory 217404 kb
Host smart-2c99b6df-4cfd-4407-aab7-a07f8cac6044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222903690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1222903690
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.375874730
Short name T168
Test name
Test status
Simulation time 237430157 ps
CPU time 1.46 seconds
Started May 26 01:14:33 PM PDT 24
Finished May 26 01:14:36 PM PDT 24
Peak memory 215228 kb
Host smart-f3041f10-6480-431d-9d8b-71f5106d9164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375874730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.375874730
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3772072582
Short name T545
Test name
Test status
Simulation time 15494129 ps
CPU time 0.97 seconds
Started May 26 01:14:46 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 206236 kb
Host smart-e68aef57-b019-43ab-8c29-4032182f358b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772072582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3772072582
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2054418366
Short name T704
Test name
Test status
Simulation time 12706428 ps
CPU time 0.88 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 216292 kb
Host smart-eee62d81-2362-4be4-b505-16a100769197
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054418366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2054418366
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.456566687
Short name T787
Test name
Test status
Simulation time 34405116 ps
CPU time 1.05 seconds
Started May 26 01:14:30 PM PDT 24
Finished May 26 01:14:32 PM PDT 24
Peak memory 223256 kb
Host smart-8469255f-8b22-4e24-91a7-23f27010b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456566687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.456566687
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.795357336
Short name T157
Test name
Test status
Simulation time 25823765 ps
CPU time 1.18 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:35 PM PDT 24
Peak memory 217848 kb
Host smart-b85d4884-8054-4e1e-8833-b74c4152df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795357336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.795357336
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2124543148
Short name T158
Test name
Test status
Simulation time 20253470 ps
CPU time 1.24 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:31 PM PDT 24
Peak memory 215212 kb
Host smart-e5e7c3f0-e536-41a1-9481-b43670d4a980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124543148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2124543148
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3603063555
Short name T257
Test name
Test status
Simulation time 19419871 ps
CPU time 1.11 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:14:34 PM PDT 24
Peak memory 206768 kb
Host smart-cb312d0d-0714-42d6-9478-871df2e00d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603063555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3603063555
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2730196197
Short name T367
Test name
Test status
Simulation time 47777117 ps
CPU time 1 seconds
Started May 26 01:14:33 PM PDT 24
Finished May 26 01:14:36 PM PDT 24
Peak memory 214844 kb
Host smart-5b8d5c21-54b2-4fa6-9f56-e84ce7ed81dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730196197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2730196197
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3529386028
Short name T159
Test name
Test status
Simulation time 1046610484 ps
CPU time 3.5 seconds
Started May 26 01:14:29 PM PDT 24
Finished May 26 01:14:33 PM PDT 24
Peak memory 214812 kb
Host smart-c0502f90-2b75-4804-8f51-73f3f35dcbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529386028 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3529386028
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1910518339
Short name T61
Test name
Test status
Simulation time 559086893431 ps
CPU time 1477.64 seconds
Started May 26 01:14:32 PM PDT 24
Finished May 26 01:39:11 PM PDT 24
Peak memory 224220 kb
Host smart-9570ab0c-5492-4f3e-9f73-d9d61e6eca10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910518339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1910518339
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1367596006
Short name T647
Test name
Test status
Simulation time 53537181 ps
CPU time 0.91 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 217800 kb
Host smart-8d6f2a7d-10f8-499d-8a57-2d045382cf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367596006 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1367596006
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3469887592
Short name T678
Test name
Test status
Simulation time 53608696 ps
CPU time 1.51 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:01 PM PDT 24
Peak memory 217724 kb
Host smart-63b67bab-7561-4226-b442-c3cd0225a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469887592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3469887592
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1103572480
Short name T96
Test name
Test status
Simulation time 25560481 ps
CPU time 1.02 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 219120 kb
Host smart-f68d698d-be8b-4a6f-a633-73507cfa967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103572480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1103572480
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1574314438
Short name T374
Test name
Test status
Simulation time 143122802 ps
CPU time 2.25 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:01 PM PDT 24
Peak memory 219580 kb
Host smart-4ebbdb6d-5d61-47f7-8dd4-ce3ad5b3326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574314438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1574314438
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.925323399
Short name T789
Test name
Test status
Simulation time 25149725 ps
CPU time 0.86 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 217848 kb
Host smart-d09ffc99-b6b3-4349-b924-02b4890c2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925323399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.925323399
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1054997595
Short name T394
Test name
Test status
Simulation time 101844860 ps
CPU time 1.17 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 216880 kb
Host smart-915d3288-e4b3-4b8e-b6b4-1ba8950c2b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054997595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1054997595
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3362537372
Short name T448
Test name
Test status
Simulation time 25616161 ps
CPU time 0.99 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 218076 kb
Host smart-7c0556ba-215e-4f68-ae06-205b1d892678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362537372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3362537372
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.354994155
Short name T705
Test name
Test status
Simulation time 117344173 ps
CPU time 1.33 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:15:59 PM PDT 24
Peak memory 216732 kb
Host smart-c960b991-c76d-4477-ad5d-382cc58ba4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354994155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.354994155
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1732681317
Short name T733
Test name
Test status
Simulation time 38157886 ps
CPU time 1.11 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:15:58 PM PDT 24
Peak memory 220460 kb
Host smart-24d29646-1b2f-42a8-b18a-1f0f9b3248d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732681317 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1732681317
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2313634551
Short name T562
Test name
Test status
Simulation time 77322154 ps
CPU time 1.36 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 217724 kb
Host smart-0aab184a-b97e-4d38-9dd2-d28175a2a8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313634551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2313634551
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3754890629
Short name T744
Test name
Test status
Simulation time 39659949 ps
CPU time 0.94 seconds
Started May 26 01:15:55 PM PDT 24
Finished May 26 01:15:57 PM PDT 24
Peak memory 223136 kb
Host smart-1c7852fb-4e31-488d-835e-c39ed18e49d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754890629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3754890629
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3272945437
Short name T701
Test name
Test status
Simulation time 58133700 ps
CPU time 1.43 seconds
Started May 26 01:15:56 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 219476 kb
Host smart-832ce6d9-2ac3-45f7-83dd-21350984251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272945437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3272945437
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2860567331
Short name T126
Test name
Test status
Simulation time 23519093 ps
CPU time 0.97 seconds
Started May 26 01:15:58 PM PDT 24
Finished May 26 01:16:01 PM PDT 24
Peak memory 217892 kb
Host smart-63f1a2be-b098-422f-a209-338858c7a888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860567331 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2860567331
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.2503643117
Short name T511
Test name
Test status
Simulation time 65579384 ps
CPU time 1.01 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 216668 kb
Host smart-5073229c-4a45-489a-80b8-f93667b7c2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503643117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2503643117
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2403425087
Short name T118
Test name
Test status
Simulation time 19723848 ps
CPU time 1.17 seconds
Started May 26 01:16:00 PM PDT 24
Finished May 26 01:16:02 PM PDT 24
Peak memory 223328 kb
Host smart-5e08554c-5278-482b-a65a-a3205d4928e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403425087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2403425087
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3935111416
Short name T596
Test name
Test status
Simulation time 33322483 ps
CPU time 1.1 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 218220 kb
Host smart-ec7c747c-9611-4608-8103-abc523d96fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935111416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3935111416
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1343374800
Short name T445
Test name
Test status
Simulation time 21049411 ps
CPU time 0.98 seconds
Started May 26 01:16:00 PM PDT 24
Finished May 26 01:16:02 PM PDT 24
Peak memory 217928 kb
Host smart-f9bc0a3e-3b12-4c56-bdb9-b74ad927978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343374800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1343374800
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.434011316
Short name T772
Test name
Test status
Simulation time 97465329 ps
CPU time 1.43 seconds
Started May 26 01:16:01 PM PDT 24
Finished May 26 01:16:03 PM PDT 24
Peak memory 219176 kb
Host smart-07a98600-74f4-43bb-bee7-8b1954052aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434011316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.434011316
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.914499544
Short name T579
Test name
Test status
Simulation time 20782743 ps
CPU time 1.19 seconds
Started May 26 01:15:57 PM PDT 24
Finished May 26 01:16:00 PM PDT 24
Peak memory 223380 kb
Host smart-0bdd2d2d-e2a9-4a35-b800-66fa0841ee12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914499544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.914499544
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2677411608
Short name T65
Test name
Test status
Simulation time 128412496 ps
CPU time 1.39 seconds
Started May 26 01:15:58 PM PDT 24
Finished May 26 01:16:01 PM PDT 24
Peak memory 216712 kb
Host smart-1d7d8067-a3fc-4c17-9999-58b4a3b81481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677411608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2677411608
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2268736640
Short name T261
Test name
Test status
Simulation time 32121072 ps
CPU time 1.37 seconds
Started May 26 01:14:45 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 214992 kb
Host smart-2a054df6-34bb-40f3-bb7b-593d88bcdf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268736640 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2268736640
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2284758732
Short name T441
Test name
Test status
Simulation time 34548609 ps
CPU time 0.91 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 206512 kb
Host smart-5ea19747-052c-41e4-821e-db5c195dd361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284758732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2284758732
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.588399748
Short name T182
Test name
Test status
Simulation time 33285168 ps
CPU time 0.85 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 215072 kb
Host smart-3602f06d-7f8f-419e-82dc-9f244a354fa5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588399748 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.588399748
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2070680493
Short name T188
Test name
Test status
Simulation time 48850711 ps
CPU time 1.2 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 217952 kb
Host smart-2eed2215-9e6e-490e-996a-c4dd76e61750
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070680493 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2070680493
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2677241244
Short name T125
Test name
Test status
Simulation time 35037915 ps
CPU time 0.89 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 217860 kb
Host smart-72818c63-2b06-4bd5-b23d-c4de10c3ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677241244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2677241244
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3126342163
Short name T718
Test name
Test status
Simulation time 32371663 ps
CPU time 1 seconds
Started May 26 01:14:49 PM PDT 24
Finished May 26 01:14:50 PM PDT 24
Peak memory 216752 kb
Host smart-10cb196d-0dc8-4785-a4d3-1fe8309ba0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126342163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3126342163
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.2198948661
Short name T260
Test name
Test status
Simulation time 51907988 ps
CPU time 0.95 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 206656 kb
Host smart-1f37d133-ee3a-41aa-9423-957a012910a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198948661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2198948661
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2706533147
Short name T404
Test name
Test status
Simulation time 44333951 ps
CPU time 0.97 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:43 PM PDT 24
Peak memory 214904 kb
Host smart-d0f1e181-82da-4d4a-adbf-d135b4c2f41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706533147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2706533147
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3815002409
Short name T316
Test name
Test status
Simulation time 284082600 ps
CPU time 1.54 seconds
Started May 26 01:14:48 PM PDT 24
Finished May 26 01:14:50 PM PDT 24
Peak memory 215052 kb
Host smart-ef5e7f89-3f84-4f67-9c11-67ec0da31d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815002409 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3815002409
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3133306908
Short name T826
Test name
Test status
Simulation time 223116236948 ps
CPU time 1280.13 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:36:07 PM PDT 24
Peak memory 224552 kb
Host smart-69c050be-c0e4-46aa-b539-4a408da0f514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133306908 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3133306908
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2932702571
Short name T105
Test name
Test status
Simulation time 50720646 ps
CPU time 1.05 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 219076 kb
Host smart-19a99e5a-f629-41c1-a04e-367c8d2e3b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932702571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2932702571
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3632372686
Short name T698
Test name
Test status
Simulation time 34427454 ps
CPU time 1.3 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 219352 kb
Host smart-9e9a67ce-ac83-433c-a6ef-4d380d59acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632372686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3632372686
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.479217869
Short name T458
Test name
Test status
Simulation time 23197549 ps
CPU time 1.1 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:04 PM PDT 24
Peak memory 217768 kb
Host smart-b23a3b3c-a08d-4da9-9aa8-07c88f547cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479217869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.479217869
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1507514231
Short name T477
Test name
Test status
Simulation time 77363377 ps
CPU time 1.04 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 216668 kb
Host smart-3dcae432-1267-42f0-8ee4-1166e2d1e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507514231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1507514231
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2607171669
Short name T95
Test name
Test status
Simulation time 25183591 ps
CPU time 1.12 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 229124 kb
Host smart-d710e494-e27f-4bd4-9e12-30e9d31e6a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607171669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2607171669
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.45411983
Short name T565
Test name
Test status
Simulation time 62746304 ps
CPU time 1.58 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 217760 kb
Host smart-807cb708-3d23-4992-be29-5484bdfc1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45411983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.45411983
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.3900644509
Short name T693
Test name
Test status
Simulation time 45174808 ps
CPU time 1.14 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 219112 kb
Host smart-0ea494de-f643-4bfb-bad9-37ecd291c82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900644509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.3900644509
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3717861231
Short name T381
Test name
Test status
Simulation time 69902590 ps
CPU time 1.17 seconds
Started May 26 01:16:08 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 218144 kb
Host smart-f359bdfc-270e-4fc1-a789-80fa4009a717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717861231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3717861231
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2071694288
Short name T766
Test name
Test status
Simulation time 45478748 ps
CPU time 1.21 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:05 PM PDT 24
Peak memory 218956 kb
Host smart-93abc03e-0e7a-4dd3-9d51-866833774bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071694288 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2071694288
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.609824142
Short name T725
Test name
Test status
Simulation time 39750227 ps
CPU time 1.51 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 217832 kb
Host smart-f3141164-ee2d-4a9b-b32e-cab508b45da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609824142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.609824142
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2870517070
Short name T103
Test name
Test status
Simulation time 33167245 ps
CPU time 1.08 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 218804 kb
Host smart-1c383bb1-36a6-48a6-a791-eac0cf6fd779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870517070 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2870517070
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3990562678
Short name T277
Test name
Test status
Simulation time 110957899 ps
CPU time 1.35 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 218500 kb
Host smart-fdf4dd74-e473-4052-a26e-d88122adc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990562678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3990562678
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.875283025
Short name T104
Test name
Test status
Simulation time 60059477 ps
CPU time 1.04 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 219952 kb
Host smart-26c6934a-c176-4d83-b942-33547d683293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875283025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.875283025
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.754063655
Short name T273
Test name
Test status
Simulation time 31293221 ps
CPU time 1.5 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 217848 kb
Host smart-fc63bfce-4da3-4f7f-99fd-03b6fe661ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754063655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.754063655
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3769832660
Short name T618
Test name
Test status
Simulation time 18385854 ps
CPU time 1.07 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 217956 kb
Host smart-b261d368-bfbf-4d64-a155-69e20bbdf6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769832660 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3769832660
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3273621119
Short name T456
Test name
Test status
Simulation time 96355454 ps
CPU time 1.23 seconds
Started May 26 01:16:02 PM PDT 24
Finished May 26 01:16:04 PM PDT 24
Peak memory 216532 kb
Host smart-b700701d-603d-4605-bce4-5bc28cd66990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273621119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3273621119
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1358598870
Short name T509
Test name
Test status
Simulation time 25486216 ps
CPU time 1.16 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 218000 kb
Host smart-a57d35f2-118b-4fca-a1c0-5d657f7fb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358598870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1358598870
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/69.edn_err.1970028613
Short name T796
Test name
Test status
Simulation time 21617479 ps
CPU time 1.14 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 219088 kb
Host smart-9b73e241-bd69-485f-9f86-2a74d9ee7627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970028613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1970028613
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2429794719
Short name T479
Test name
Test status
Simulation time 115012183 ps
CPU time 1.31 seconds
Started May 26 01:16:08 PM PDT 24
Finished May 26 01:16:11 PM PDT 24
Peak memory 216632 kb
Host smart-10f1e3e2-071a-4035-aa99-8f11db0dbbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429794719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2429794719
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3933449719
Short name T269
Test name
Test status
Simulation time 26097713 ps
CPU time 1.2 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 215236 kb
Host smart-5ce640df-9af9-417d-bc66-8b5d68756fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933449719 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3933449719
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1132718284
Short name T671
Test name
Test status
Simulation time 23836886 ps
CPU time 1.02 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:43 PM PDT 24
Peak memory 206152 kb
Host smart-d794e363-fd1e-4000-9dab-e540c63264e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132718284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1132718284
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3778662167
Short name T111
Test name
Test status
Simulation time 92842323 ps
CPU time 1.11 seconds
Started May 26 01:14:41 PM PDT 24
Finished May 26 01:14:43 PM PDT 24
Peak memory 216388 kb
Host smart-5de7da12-4424-4498-8874-387fd57d8063
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778662167 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3778662167
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.232368345
Short name T75
Test name
Test status
Simulation time 24003975 ps
CPU time 0.91 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 217996 kb
Host smart-298793f3-d9df-4944-a63e-2aaea3127985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232368345 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.232368345
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3544791158
Short name T71
Test name
Test status
Simulation time 76273727 ps
CPU time 1.04 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 216644 kb
Host smart-79983dd7-293f-4885-aa42-3c295152fd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544791158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3544791158
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1641954039
Short name T436
Test name
Test status
Simulation time 32289004 ps
CPU time 0.9 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 214740 kb
Host smart-33ff965c-0efd-41fb-a699-866ab3a9edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641954039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1641954039
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3309838516
Short name T26
Test name
Test status
Simulation time 19463290 ps
CPU time 1.07 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 206644 kb
Host smart-15f02795-8bf7-454d-ab3a-7dedfeaef56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309838516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3309838516
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1692377805
Short name T406
Test name
Test status
Simulation time 19485861 ps
CPU time 1.02 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 214948 kb
Host smart-60fdec08-b365-4621-8a2f-7e48027767b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692377805 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1692377805
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4154201822
Short name T600
Test name
Test status
Simulation time 200744579 ps
CPU time 1.63 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 216664 kb
Host smart-e4c70d47-f3cb-4645-ae5d-ef4d79c438b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154201822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4154201822
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2105137449
Short name T205
Test name
Test status
Simulation time 317665666021 ps
CPU time 1777.65 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:44:23 PM PDT 24
Peak memory 224740 kb
Host smart-0dfe827c-16f0-4c18-901e-849230cbddaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105137449 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2105137449
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2690980553
Short name T402
Test name
Test status
Simulation time 34898196 ps
CPU time 0.96 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 219368 kb
Host smart-a6c689a1-5d7a-45a7-959a-d3dd0919dc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690980553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2690980553
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2181221746
Short name T440
Test name
Test status
Simulation time 67398681 ps
CPU time 2.31 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 214964 kb
Host smart-231812c9-2755-4091-85ae-2d3a351227c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181221746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2181221746
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2431308887
Short name T420
Test name
Test status
Simulation time 197237371 ps
CPU time 1.03 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:04 PM PDT 24
Peak memory 219476 kb
Host smart-72f46e9b-1188-4ec1-a232-ad173183ff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431308887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2431308887
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3299065506
Short name T326
Test name
Test status
Simulation time 109273229 ps
CPU time 1.09 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:05 PM PDT 24
Peak memory 216524 kb
Host smart-bd09e27b-94cb-4038-b54b-6cf3fb125f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299065506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3299065506
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1618604474
Short name T137
Test name
Test status
Simulation time 30724039 ps
CPU time 0.96 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 223284 kb
Host smart-13224eb4-aaa5-4f5f-8fec-64db1c0cd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618604474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1618604474
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1641059759
Short name T755
Test name
Test status
Simulation time 50091837 ps
CPU time 2.25 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 219516 kb
Host smart-c04816dc-e606-4e3e-a89b-53f6fc0a9bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641059759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1641059759
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.13888946
Short name T128
Test name
Test status
Simulation time 18485389 ps
CPU time 1.03 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 217856 kb
Host smart-a74c6f15-3207-42b4-afe8-612a5fd09662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13888946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.13888946
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.131201243
Short name T763
Test name
Test status
Simulation time 36894681 ps
CPU time 1.36 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 219192 kb
Host smart-bc18c141-f8b4-4e38-8051-f4938dbb338e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131201243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.131201243
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3331223035
Short name T108
Test name
Test status
Simulation time 84073168 ps
CPU time 1.08 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 231548 kb
Host smart-65d12a48-3d2e-41ff-ada4-ff7569f85a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331223035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3331223035
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3455733317
Short name T813
Test name
Test status
Simulation time 55959646 ps
CPU time 1.16 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 216496 kb
Host smart-fa447882-2006-426d-a74b-d3dc75c96ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455733317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3455733317
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.112371632
Short name T59
Test name
Test status
Simulation time 50760080 ps
CPU time 1 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 219256 kb
Host smart-604dccb0-4688-4bb5-bcd2-5b1071217084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112371632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.112371632
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1179564531
Short name T531
Test name
Test status
Simulation time 176456936 ps
CPU time 3.44 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:15 PM PDT 24
Peak memory 214852 kb
Host smart-d3edca34-2032-4793-ba6d-86252d50d9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179564531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1179564531
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_genbits.3557737840
Short name T294
Test name
Test status
Simulation time 37831642 ps
CPU time 1.45 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 216608 kb
Host smart-a190dcad-62df-4031-805e-152f4e103b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557737840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3557737840
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.505144573
Short name T535
Test name
Test status
Simulation time 21717606 ps
CPU time 0.93 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 218100 kb
Host smart-61b3dcae-be67-4e7e-948e-f4a7cab71952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505144573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.505144573
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.231422569
Short name T348
Test name
Test status
Simulation time 134407902 ps
CPU time 1.43 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 219272 kb
Host smart-21b06878-fb84-42f2-a7ef-0657b5451aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231422569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.231422569
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1490114146
Short name T751
Test name
Test status
Simulation time 24414146 ps
CPU time 1.05 seconds
Started May 26 01:16:09 PM PDT 24
Finished May 26 01:16:11 PM PDT 24
Peak memory 218696 kb
Host smart-9b78361c-c769-4926-9519-a7d7d610d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490114146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1490114146
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2366609576
Short name T515
Test name
Test status
Simulation time 80231886 ps
CPU time 1.88 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 219480 kb
Host smart-a9949133-43b4-4c99-a043-9e1bd4fe4347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366609576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2366609576
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2254429576
Short name T398
Test name
Test status
Simulation time 19898036 ps
CPU time 1.18 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 223300 kb
Host smart-e360666a-508f-4749-9797-1cb6135efbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254429576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2254429576
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3389986466
Short name T806
Test name
Test status
Simulation time 57174408 ps
CPU time 1.39 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 218056 kb
Host smart-daab3acf-86cd-4aa9-8b36-ebeac187b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389986466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3389986466
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2172077340
Short name T827
Test name
Test status
Simulation time 29096734 ps
CPU time 1.29 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 215356 kb
Host smart-9fa08248-71e1-4b3c-8c09-56f792411da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172077340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2172077340
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1432097200
Short name T652
Test name
Test status
Simulation time 24245756 ps
CPU time 0.88 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 214348 kb
Host smart-e1b8cc67-d5b9-4fdd-8584-21735182a9d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432097200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1432097200
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1355250366
Short name T556
Test name
Test status
Simulation time 11202111 ps
CPU time 0.84 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 214636 kb
Host smart-a91f4394-5534-42f5-b2ea-2ec136b1ee3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355250366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1355250366
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3794888890
Short name T115
Test name
Test status
Simulation time 49775077 ps
CPU time 1.12 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 216584 kb
Host smart-20d0a4ea-e6a9-4473-81fa-460242447816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794888890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3794888890
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.4131431263
Short name T376
Test name
Test status
Simulation time 34946455 ps
CPU time 1.17 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 219164 kb
Host smart-1c700a52-9260-4395-be88-536aa03b77b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131431263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.4131431263
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2435237238
Short name T777
Test name
Test status
Simulation time 43398361 ps
CPU time 1.15 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 216564 kb
Host smart-b4f83c6f-c164-4a50-aed5-cc93115622b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435237238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2435237238
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2504696797
Short name T709
Test name
Test status
Simulation time 41105019 ps
CPU time 0.86 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 215380 kb
Host smart-bc7eb35d-1a06-40de-abeb-2539d06c9cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504696797 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2504696797
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.125532496
Short name T615
Test name
Test status
Simulation time 103852786 ps
CPU time 0.92 seconds
Started May 26 01:14:46 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 214808 kb
Host smart-5250ad30-a2c9-4dcc-96a6-dce5094716fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125532496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.125532496
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1827941204
Short name T485
Test name
Test status
Simulation time 549811605 ps
CPU time 3.13 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 216712 kb
Host smart-24a0f0a3-c0ce-4af5-861c-58f3bfcca837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827941204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1827941204
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3122598187
Short name T336
Test name
Test status
Simulation time 363334765666 ps
CPU time 934.15 seconds
Started May 26 01:14:48 PM PDT 24
Finished May 26 01:30:23 PM PDT 24
Peak memory 221040 kb
Host smart-2a60525c-1cdc-4b29-85f3-88ff180a5ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122598187 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3122598187
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1207985446
Short name T143
Test name
Test status
Simulation time 34302765 ps
CPU time 0.91 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 217700 kb
Host smart-f59bfc82-19c2-4421-943d-7464a6e6d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207985446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1207985446
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3736011189
Short name T519
Test name
Test status
Simulation time 47437474 ps
CPU time 1.31 seconds
Started May 26 01:16:04 PM PDT 24
Finished May 26 01:16:07 PM PDT 24
Peak memory 217996 kb
Host smart-3aa1f1c8-ca9b-4049-a953-e6fda6b97bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736011189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3736011189
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.901317460
Short name T793
Test name
Test status
Simulation time 19347226 ps
CPU time 1.18 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:06 PM PDT 24
Peak memory 223280 kb
Host smart-d095351e-e41a-44fa-b32e-397bb99d2ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901317460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.901317460
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3350928186
Short name T636
Test name
Test status
Simulation time 72083999 ps
CPU time 1.43 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 216588 kb
Host smart-598291e6-ad47-4af1-85de-bb8c19f13d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350928186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3350928186
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.703444730
Short name T590
Test name
Test status
Simulation time 29231689 ps
CPU time 1.25 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:08 PM PDT 24
Peak memory 219112 kb
Host smart-070a4891-bcf7-4bc2-8b26-19169de0d130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703444730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.703444730
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3780511144
Short name T256
Test name
Test status
Simulation time 34657423 ps
CPU time 1.35 seconds
Started May 26 01:16:08 PM PDT 24
Finished May 26 01:16:11 PM PDT 24
Peak memory 214900 kb
Host smart-9b6ceed0-ec23-4c1d-b377-a1e434c634e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780511144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3780511144
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3393260959
Short name T609
Test name
Test status
Simulation time 19072559 ps
CPU time 1.23 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 223296 kb
Host smart-c21a0105-bf78-4e5b-8813-2f3d37b34249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393260959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3393260959
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2811280663
Short name T794
Test name
Test status
Simulation time 139625694 ps
CPU time 2.76 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:11 PM PDT 24
Peak memory 218200 kb
Host smart-2decab4e-317c-4d8b-b702-b3e0f0bd00f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811280663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2811280663
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2127156440
Short name T132
Test name
Test status
Simulation time 19612380 ps
CPU time 1.2 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 223416 kb
Host smart-fb89fe24-c462-4efa-b996-a01635d79e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127156440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2127156440
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1438135544
Short name T637
Test name
Test status
Simulation time 189280974 ps
CPU time 1.6 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:14 PM PDT 24
Peak memory 218896 kb
Host smart-444fd42b-91d2-4502-bb93-5845ee2c378f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438135544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1438135544
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3698382072
Short name T599
Test name
Test status
Simulation time 30743007 ps
CPU time 1.1 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 223376 kb
Host smart-0ec0de06-d9ed-4ce3-9268-aca517741844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698382072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3698382072
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.873290044
Short name T831
Test name
Test status
Simulation time 28026582 ps
CPU time 1.29 seconds
Started May 26 01:16:06 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 216640 kb
Host smart-d0da268e-c810-4dfa-8e8f-e1b261fca9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873290044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.873290044
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3460851647
Short name T138
Test name
Test status
Simulation time 19470758 ps
CPU time 1.17 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 223412 kb
Host smart-eea5e1c8-1b92-4e1c-8943-42cd74514eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460851647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3460851647
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4055394439
Short name T447
Test name
Test status
Simulation time 56851989 ps
CPU time 1.45 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 218040 kb
Host smart-17bc6122-7142-4b62-ae5c-4cd49dee49c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055394439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4055394439
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2362711733
Short name T491
Test name
Test status
Simulation time 27307035 ps
CPU time 1.27 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 217092 kb
Host smart-2fea65ce-bec4-4f39-95ef-423d770a20b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362711733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2362711733
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4122468262
Short name T597
Test name
Test status
Simulation time 72641232 ps
CPU time 2.76 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 218096 kb
Host smart-476507a1-ee1e-466a-988e-f1e9996ec2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122468262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4122468262
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1661118393
Short name T133
Test name
Test status
Simulation time 23168175 ps
CPU time 0.95 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 217688 kb
Host smart-9576418a-753b-486f-ae6a-ef1da58ba07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661118393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1661118393
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3067763749
Short name T299
Test name
Test status
Simulation time 43537015 ps
CPU time 1.84 seconds
Started May 26 01:16:05 PM PDT 24
Finished May 26 01:16:09 PM PDT 24
Peak memory 217880 kb
Host smart-55ec7d65-270e-4994-b320-190cc77870b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067763749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3067763749
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.282777319
Short name T142
Test name
Test status
Simulation time 37817758 ps
CPU time 0.85 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 217828 kb
Host smart-c3b7c2ff-dd6a-4603-bfe9-2f9bc062813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282777319 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.282777319
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.563316337
Short name T272
Test name
Test status
Simulation time 323160805 ps
CPU time 4 seconds
Started May 26 01:16:08 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 219612 kb
Host smart-2bd1e408-9b69-459e-bb74-f70983a35b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563316337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.563316337
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4268471621
Short name T746
Test name
Test status
Simulation time 75050966 ps
CPU time 1.22 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 215336 kb
Host smart-eba2320f-44fb-44a4-a49f-1ba167a1b5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268471621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4268471621
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2314620219
Short name T812
Test name
Test status
Simulation time 36863691 ps
CPU time 0.89 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 206160 kb
Host smart-6324e12a-8ec3-4f85-bae7-34452c16cb94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314620219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2314620219
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2728397944
Short name T681
Test name
Test status
Simulation time 26395295 ps
CPU time 0.86 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:45 PM PDT 24
Peak memory 215916 kb
Host smart-48f0cc73-f5a2-4f4f-a2e7-db5da4e536a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728397944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2728397944
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4237705456
Short name T507
Test name
Test status
Simulation time 32136011 ps
CPU time 1.2 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 216568 kb
Host smart-68698e2d-184f-45b8-b388-c83e1060eee5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237705456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4237705456
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1135977270
Short name T702
Test name
Test status
Simulation time 28849948 ps
CPU time 1.25 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:14:44 PM PDT 24
Peak memory 219204 kb
Host smart-e4f98f9f-0922-4423-a363-513ece01e4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135977270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1135977270
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.140747235
Short name T362
Test name
Test status
Simulation time 53199011 ps
CPU time 1.49 seconds
Started May 26 01:14:44 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 218428 kb
Host smart-430e1adc-4860-4015-ba78-91e6b81f87dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140747235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.140747235
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.4218698773
Short name T633
Test name
Test status
Simulation time 35007350 ps
CPU time 0.98 seconds
Started May 26 01:14:45 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 215320 kb
Host smart-619217ac-3b63-4cf3-994d-7573fa1456a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218698773 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.4218698773
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1198643035
Short name T258
Test name
Test status
Simulation time 43723948 ps
CPU time 0.95 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:46 PM PDT 24
Peak memory 206980 kb
Host smart-2cedfd0e-bfa3-495a-947f-4bd569fde969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198643035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1198643035
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2824839326
Short name T63
Test name
Test status
Simulation time 15456175 ps
CPU time 0.97 seconds
Started May 26 01:14:45 PM PDT 24
Finished May 26 01:14:48 PM PDT 24
Peak memory 214932 kb
Host smart-b4c93235-7f57-4e5b-b8d9-6a7e259f4e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824839326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2824839326
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1449046085
Short name T245
Test name
Test status
Simulation time 240109085 ps
CPU time 1.93 seconds
Started May 26 01:14:43 PM PDT 24
Finished May 26 01:14:47 PM PDT 24
Peak memory 216760 kb
Host smart-89d2fe94-ed14-45e1-8eba-feb0665b2a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449046085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1449046085
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.571090877
Short name T397
Test name
Test status
Simulation time 80983502768 ps
CPU time 471.84 seconds
Started May 26 01:14:42 PM PDT 24
Finished May 26 01:22:34 PM PDT 24
Peak memory 218796 kb
Host smart-4907681c-ee06-47de-a2ff-ec234242b39a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571090877 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.571090877
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3511493172
Short name T153
Test name
Test status
Simulation time 21473455 ps
CPU time 0.97 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 219204 kb
Host smart-6a5ea8d0-4dad-49b9-a654-c9abebf12351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511493172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3511493172
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3336990711
Short name T438
Test name
Test status
Simulation time 41492384 ps
CPU time 1.88 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:14 PM PDT 24
Peak memory 217932 kb
Host smart-026f66c6-f041-4b32-a356-8ef9fa8329e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336990711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3336990711
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.1232123773
Short name T395
Test name
Test status
Simulation time 19308197 ps
CPU time 1.07 seconds
Started May 26 01:16:09 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 217820 kb
Host smart-e130400e-f280-4eca-8cd6-a9b4cca6ffb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232123773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.1232123773
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3294916673
Short name T356
Test name
Test status
Simulation time 62455883 ps
CPU time 1.25 seconds
Started May 26 01:16:09 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 218268 kb
Host smart-a2f7c1c1-e2cc-4f09-a235-ff7bad6660dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294916673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3294916673
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1816876912
Short name T422
Test name
Test status
Simulation time 31561853 ps
CPU time 1.3 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 220300 kb
Host smart-f800ba96-5c41-48d1-a353-c1c8b8923dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816876912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1816876912
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.4240225280
Short name T419
Test name
Test status
Simulation time 33554283 ps
CPU time 1.34 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 217620 kb
Host smart-ac077d24-6282-4ce9-bbea-4f9a8610bffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240225280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.4240225280
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1453402851
Short name T410
Test name
Test status
Simulation time 60037481 ps
CPU time 0.88 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 217488 kb
Host smart-4a45409b-2489-4491-986d-5857a49a9013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453402851 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1453402851
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.348558518
Short name T677
Test name
Test status
Simulation time 104160248 ps
CPU time 1.38 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 219168 kb
Host smart-320ea69a-05f9-44b1-8399-cd39a683e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348558518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.348558518
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_genbits.1436371967
Short name T784
Test name
Test status
Simulation time 64180073 ps
CPU time 2.4 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:11 PM PDT 24
Peak memory 218048 kb
Host smart-ce726718-4dd1-47e0-9263-596415938848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436371967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1436371967
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4162211983
Short name T697
Test name
Test status
Simulation time 23673447 ps
CPU time 0.93 seconds
Started May 26 01:16:09 PM PDT 24
Finished May 26 01:16:12 PM PDT 24
Peak memory 217800 kb
Host smart-36ba2b6c-9bee-43f1-9aa0-dc7111086fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162211983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4162211983
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.690200257
Short name T624
Test name
Test status
Simulation time 154031265 ps
CPU time 1.21 seconds
Started May 26 01:16:10 PM PDT 24
Finished May 26 01:16:13 PM PDT 24
Peak memory 216676 kb
Host smart-c7bad566-026c-42d3-994b-f5545c8e0959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690200257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.690200257
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3860089977
Short name T76
Test name
Test status
Simulation time 31415024 ps
CPU time 0.88 seconds
Started May 26 01:16:03 PM PDT 24
Finished May 26 01:16:05 PM PDT 24
Peak memory 217768 kb
Host smart-96c0828f-e696-4482-a18b-7ced87f78ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860089977 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3860089977
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2580795885
Short name T629
Test name
Test status
Simulation time 112595696 ps
CPU time 1.01 seconds
Started May 26 01:16:07 PM PDT 24
Finished May 26 01:16:10 PM PDT 24
Peak memory 216672 kb
Host smart-19b36f7d-8835-4c09-abf5-9209c128fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580795885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2580795885
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.333112807
Short name T101
Test name
Test status
Simulation time 37234155 ps
CPU time 1.09 seconds
Started May 26 01:16:15 PM PDT 24
Finished May 26 01:16:18 PM PDT 24
Peak memory 229064 kb
Host smart-5a54f0f2-9ed2-4628-88bc-269d85f23ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333112807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.333112807
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2755980831
Short name T708
Test name
Test status
Simulation time 39744969 ps
CPU time 1.6 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:19 PM PDT 24
Peak memory 219420 kb
Host smart-1ed6e911-7591-4f29-938d-31abd1291785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755980831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2755980831
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2602274113
Short name T122
Test name
Test status
Simulation time 20640132 ps
CPU time 0.95 seconds
Started May 26 01:16:21 PM PDT 24
Finished May 26 01:16:24 PM PDT 24
Peak memory 217904 kb
Host smart-2eff2dfa-5ded-4b7f-9346-40bcd292258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602274113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2602274113
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3379833826
Short name T47
Test name
Test status
Simulation time 35643093 ps
CPU time 1.32 seconds
Started May 26 01:16:13 PM PDT 24
Finished May 26 01:16:15 PM PDT 24
Peak memory 217944 kb
Host smart-6568ed5e-82c6-491f-adbb-cbe4d434e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379833826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3379833826
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2248534905
Short name T74
Test name
Test status
Simulation time 22470467 ps
CPU time 0.9 seconds
Started May 26 01:16:18 PM PDT 24
Finished May 26 01:16:21 PM PDT 24
Peak memory 217880 kb
Host smart-271ab813-3232-40f0-9619-2e0211444529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248534905 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2248534905
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.789015168
Short name T353
Test name
Test status
Simulation time 39415308 ps
CPU time 1.29 seconds
Started May 26 01:16:16 PM PDT 24
Finished May 26 01:16:20 PM PDT 24
Peak memory 216836 kb
Host smart-5741b65a-86d3-448f-8654-92d205010213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789015168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.789015168
Directory /workspace/99.edn_genbits/latest
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