Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.42 98.24 93.80 97.07 84.30 96.62 99.77 91.12


Total test records in report: 980
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T793 /workspace/coverage/default/41.edn_alert_test.1634757479 May 28 02:11:42 PM PDT 24 May 28 02:11:44 PM PDT 24 16536808 ps
T794 /workspace/coverage/default/29.edn_disable_auto_req_mode.1042354471 May 28 02:11:19 PM PDT 24 May 28 02:11:23 PM PDT 24 59381431 ps
T795 /workspace/coverage/default/104.edn_genbits.2393268914 May 28 02:12:35 PM PDT 24 May 28 02:12:39 PM PDT 24 53681937 ps
T796 /workspace/coverage/default/38.edn_genbits.719638803 May 28 02:11:42 PM PDT 24 May 28 02:11:44 PM PDT 24 126025123 ps
T797 /workspace/coverage/default/80.edn_genbits.4270724532 May 28 02:12:22 PM PDT 24 May 28 02:12:25 PM PDT 24 72449172 ps
T798 /workspace/coverage/default/4.edn_genbits.203581094 May 28 02:10:07 PM PDT 24 May 28 02:10:11 PM PDT 24 51214467 ps
T799 /workspace/coverage/default/16.edn_smoke.2715347921 May 28 02:10:54 PM PDT 24 May 28 02:10:56 PM PDT 24 46456143 ps
T800 /workspace/coverage/default/277.edn_genbits.2248836325 May 28 02:12:59 PM PDT 24 May 28 02:13:03 PM PDT 24 53603809 ps
T801 /workspace/coverage/default/43.edn_disable_auto_req_mode.1434474855 May 28 02:11:52 PM PDT 24 May 28 02:11:56 PM PDT 24 180143068 ps
T802 /workspace/coverage/default/30.edn_err.469823542 May 28 02:11:27 PM PDT 24 May 28 02:11:31 PM PDT 24 19811019 ps
T803 /workspace/coverage/default/13.edn_err.3911436983 May 28 02:10:48 PM PDT 24 May 28 02:10:51 PM PDT 24 73189745 ps
T109 /workspace/coverage/default/97.edn_err.429019927 May 28 02:12:37 PM PDT 24 May 28 02:12:42 PM PDT 24 122152722 ps
T804 /workspace/coverage/default/21.edn_disable.2685579294 May 28 02:11:08 PM PDT 24 May 28 02:11:13 PM PDT 24 34759904 ps
T805 /workspace/coverage/default/8.edn_genbits.184353014 May 28 02:10:18 PM PDT 24 May 28 02:10:20 PM PDT 24 113316467 ps
T806 /workspace/coverage/default/23.edn_disable_auto_req_mode.269347887 May 28 02:11:11 PM PDT 24 May 28 02:11:15 PM PDT 24 27770918 ps
T807 /workspace/coverage/default/26.edn_alert_test.1262893108 May 28 02:11:16 PM PDT 24 May 28 02:11:19 PM PDT 24 24347480 ps
T808 /workspace/coverage/default/242.edn_genbits.3125333730 May 28 02:13:03 PM PDT 24 May 28 02:13:07 PM PDT 24 201170471 ps
T809 /workspace/coverage/default/47.edn_disable.3509141816 May 28 02:11:52 PM PDT 24 May 28 02:11:55 PM PDT 24 11528407 ps
T810 /workspace/coverage/default/6.edn_smoke.2729491542 May 28 02:10:21 PM PDT 24 May 28 02:10:24 PM PDT 24 75641908 ps
T811 /workspace/coverage/default/38.edn_smoke.1019309702 May 28 02:11:43 PM PDT 24 May 28 02:11:45 PM PDT 24 16302867 ps
T812 /workspace/coverage/default/25.edn_err.720475379 May 28 02:11:10 PM PDT 24 May 28 02:11:15 PM PDT 24 29569824 ps
T813 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3367351157 May 28 02:10:48 PM PDT 24 May 28 02:21:04 PM PDT 24 48651580930 ps
T814 /workspace/coverage/default/148.edn_genbits.2082735181 May 28 02:12:40 PM PDT 24 May 28 02:12:45 PM PDT 24 52134254 ps
T815 /workspace/coverage/default/299.edn_genbits.3944810491 May 28 02:13:15 PM PDT 24 May 28 02:13:18 PM PDT 24 153476121 ps
T816 /workspace/coverage/default/267.edn_genbits.2187756546 May 28 02:12:58 PM PDT 24 May 28 02:13:02 PM PDT 24 44542578 ps
T817 /workspace/coverage/default/49.edn_alert.3348945181 May 28 02:12:03 PM PDT 24 May 28 02:12:06 PM PDT 24 27698098 ps
T114 /workspace/coverage/default/90.edn_err.3406890206 May 28 02:12:22 PM PDT 24 May 28 02:12:24 PM PDT 24 25464855 ps
T818 /workspace/coverage/default/33.edn_alert_test.2249819774 May 28 02:11:26 PM PDT 24 May 28 02:11:28 PM PDT 24 45871102 ps
T819 /workspace/coverage/default/274.edn_genbits.2479008521 May 28 02:13:04 PM PDT 24 May 28 02:13:06 PM PDT 24 40524835 ps
T820 /workspace/coverage/default/72.edn_genbits.3265036442 May 28 02:12:02 PM PDT 24 May 28 02:12:06 PM PDT 24 253434588 ps
T821 /workspace/coverage/default/145.edn_genbits.1259996630 May 28 02:12:39 PM PDT 24 May 28 02:12:45 PM PDT 24 20308304 ps
T822 /workspace/coverage/default/71.edn_err.1218058069 May 28 02:12:04 PM PDT 24 May 28 02:12:07 PM PDT 24 18985863 ps
T146 /workspace/coverage/default/50.edn_err.462504940 May 28 02:12:06 PM PDT 24 May 28 02:12:10 PM PDT 24 18301377 ps
T823 /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4075304048 May 28 02:11:54 PM PDT 24 May 28 02:23:19 PM PDT 24 25251565408 ps
T824 /workspace/coverage/default/29.edn_genbits.456122482 May 28 02:11:18 PM PDT 24 May 28 02:11:21 PM PDT 24 101099637 ps
T825 /workspace/coverage/default/64.edn_err.3063250458 May 28 02:12:06 PM PDT 24 May 28 02:12:10 PM PDT 24 20755740 ps
T826 /workspace/coverage/default/44.edn_alert_test.2551562751 May 28 02:11:53 PM PDT 24 May 28 02:11:59 PM PDT 24 70081266 ps
T827 /workspace/coverage/default/27.edn_genbits.938525801 May 28 02:11:17 PM PDT 24 May 28 02:11:20 PM PDT 24 46886079 ps
T828 /workspace/coverage/default/91.edn_err.3537192992 May 28 02:12:25 PM PDT 24 May 28 02:12:28 PM PDT 24 19307629 ps
T829 /workspace/coverage/default/281.edn_genbits.3946439076 May 28 02:13:00 PM PDT 24 May 28 02:13:03 PM PDT 24 27262750 ps
T830 /workspace/coverage/default/163.edn_genbits.2571730863 May 28 02:12:48 PM PDT 24 May 28 02:12:51 PM PDT 24 22673576 ps
T831 /workspace/coverage/default/142.edn_genbits.3384908258 May 28 02:12:37 PM PDT 24 May 28 02:12:42 PM PDT 24 77923460 ps
T832 /workspace/coverage/default/47.edn_stress_all.3596821190 May 28 02:11:56 PM PDT 24 May 28 02:12:03 PM PDT 24 77254364 ps
T833 /workspace/coverage/default/37.edn_disable.4252328314 May 28 02:11:51 PM PDT 24 May 28 02:11:53 PM PDT 24 56544703 ps
T834 /workspace/coverage/default/14.edn_genbits.455825702 May 28 02:10:47 PM PDT 24 May 28 02:10:51 PM PDT 24 48189132 ps
T835 /workspace/coverage/default/7.edn_genbits.646682391 May 28 02:10:17 PM PDT 24 May 28 02:10:20 PM PDT 24 86288437 ps
T836 /workspace/coverage/default/106.edn_genbits.4260121131 May 28 02:12:36 PM PDT 24 May 28 02:12:40 PM PDT 24 43340735 ps
T837 /workspace/coverage/default/121.edn_genbits.320850208 May 28 02:12:37 PM PDT 24 May 28 02:12:43 PM PDT 24 56549110 ps
T838 /workspace/coverage/default/6.edn_genbits.3571605419 May 28 02:10:18 PM PDT 24 May 28 02:10:21 PM PDT 24 107527347 ps
T839 /workspace/coverage/default/48.edn_alert_test.3940393918 May 28 02:12:05 PM PDT 24 May 28 02:12:09 PM PDT 24 16843616 ps
T121 /workspace/coverage/default/35.edn_disable_auto_req_mode.2746560952 May 28 02:11:30 PM PDT 24 May 28 02:11:36 PM PDT 24 35730653 ps
T840 /workspace/coverage/default/4.edn_smoke.3638722988 May 28 02:10:07 PM PDT 24 May 28 02:10:11 PM PDT 24 24497102 ps
T117 /workspace/coverage/default/32.edn_disable_auto_req_mode.2779996379 May 28 02:11:27 PM PDT 24 May 28 02:11:32 PM PDT 24 47895164 ps
T841 /workspace/coverage/default/6.edn_stress_all.2422805088 May 28 02:10:20 PM PDT 24 May 28 02:10:25 PM PDT 24 95062319 ps
T842 /workspace/coverage/default/11.edn_disable.621895440 May 28 02:10:32 PM PDT 24 May 28 02:10:36 PM PDT 24 34030720 ps
T843 /workspace/coverage/default/118.edn_genbits.3327534080 May 28 02:12:36 PM PDT 24 May 28 02:12:39 PM PDT 24 39493691 ps
T844 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3534546376 May 28 02:11:30 PM PDT 24 May 28 02:35:11 PM PDT 24 534123575122 ps
T845 /workspace/coverage/default/76.edn_err.2405763420 May 28 02:12:24 PM PDT 24 May 28 02:12:28 PM PDT 24 22369316 ps
T128 /workspace/coverage/default/8.edn_err.2593516293 May 28 02:10:17 PM PDT 24 May 28 02:10:20 PM PDT 24 21267303 ps
T846 /workspace/coverage/default/44.edn_intr.72607495 May 28 02:11:55 PM PDT 24 May 28 02:12:01 PM PDT 24 45135139 ps
T847 /workspace/coverage/default/21.edn_genbits.482877118 May 28 02:11:05 PM PDT 24 May 28 02:11:08 PM PDT 24 146923353 ps
T848 /workspace/coverage/default/55.edn_genbits.1287080308 May 28 02:12:05 PM PDT 24 May 28 02:12:10 PM PDT 24 58217914 ps
T849 /workspace/coverage/default/217.edn_genbits.226664621 May 28 02:12:53 PM PDT 24 May 28 02:12:58 PM PDT 24 66976288 ps
T850 /workspace/coverage/default/210.edn_genbits.493087325 May 28 02:12:53 PM PDT 24 May 28 02:12:58 PM PDT 24 246905375 ps
T851 /workspace/coverage/default/26.edn_disable_auto_req_mode.2536218771 May 28 02:11:17 PM PDT 24 May 28 02:11:20 PM PDT 24 76882852 ps
T852 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.281188055 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 19608079 ps
T237 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2975620549 May 28 01:19:30 PM PDT 24 May 28 01:19:32 PM PDT 24 62501284 ps
T853 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2479595658 May 28 01:19:37 PM PDT 24 May 28 01:19:40 PM PDT 24 77494253 ps
T204 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.520054166 May 28 01:19:58 PM PDT 24 May 28 01:20:00 PM PDT 24 17432480 ps
T854 /workspace/coverage/cover_reg_top/17.edn_intr_test.3351073050 May 28 01:20:22 PM PDT 24 May 28 01:20:26 PM PDT 24 23289944 ps
T855 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4225493443 May 28 01:19:25 PM PDT 24 May 28 01:19:28 PM PDT 24 221130353 ps
T856 /workspace/coverage/cover_reg_top/4.edn_intr_test.2556551654 May 28 01:19:38 PM PDT 24 May 28 01:19:40 PM PDT 24 24907769 ps
T857 /workspace/coverage/cover_reg_top/46.edn_intr_test.4127062967 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 46898384 ps
T858 /workspace/coverage/cover_reg_top/28.edn_intr_test.2613999327 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 31056677 ps
T859 /workspace/coverage/cover_reg_top/20.edn_intr_test.1378352567 May 28 01:20:22 PM PDT 24 May 28 01:20:25 PM PDT 24 14121030 ps
T860 /workspace/coverage/cover_reg_top/7.edn_intr_test.496722083 May 28 01:19:38 PM PDT 24 May 28 01:19:41 PM PDT 24 141938942 ps
T861 /workspace/coverage/cover_reg_top/32.edn_intr_test.2059714217 May 28 01:20:22 PM PDT 24 May 28 01:20:24 PM PDT 24 19265239 ps
T862 /workspace/coverage/cover_reg_top/2.edn_tl_errors.235290469 May 28 01:19:25 PM PDT 24 May 28 01:19:29 PM PDT 24 174460858 ps
T863 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2760925771 May 28 01:20:23 PM PDT 24 May 28 01:20:29 PM PDT 24 64248858 ps
T203 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1899916351 May 28 01:19:39 PM PDT 24 May 28 01:19:41 PM PDT 24 21838657 ps
T864 /workspace/coverage/cover_reg_top/22.edn_intr_test.4094648415 May 28 01:20:21 PM PDT 24 May 28 01:20:22 PM PDT 24 66144219 ps
T213 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2538249137 May 28 01:19:28 PM PDT 24 May 28 01:19:31 PM PDT 24 19134747 ps
T865 /workspace/coverage/cover_reg_top/26.edn_intr_test.1850452411 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 35633358 ps
T214 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2622716198 May 28 01:20:08 PM PDT 24 May 28 01:20:11 PM PDT 24 40358947 ps
T866 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1164957101 May 28 01:20:09 PM PDT 24 May 28 01:20:12 PM PDT 24 54129558 ps
T867 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.249263234 May 28 01:19:55 PM PDT 24 May 28 01:19:57 PM PDT 24 19028400 ps
T238 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3447851083 May 28 01:19:26 PM PDT 24 May 28 01:19:30 PM PDT 24 396109055 ps
T868 /workspace/coverage/cover_reg_top/30.edn_intr_test.3798690240 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 35113716 ps
T215 /workspace/coverage/cover_reg_top/8.edn_csr_rw.664507424 May 28 01:19:53 PM PDT 24 May 28 01:19:56 PM PDT 24 30961045 ps
T233 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1929754238 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 39337208 ps
T241 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2524474011 May 28 01:20:07 PM PDT 24 May 28 01:20:10 PM PDT 24 43008125 ps
T239 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2290697374 May 28 01:19:26 PM PDT 24 May 28 01:19:33 PM PDT 24 176267962 ps
T869 /workspace/coverage/cover_reg_top/0.edn_intr_test.3183675912 May 28 01:19:26 PM PDT 24 May 28 01:19:29 PM PDT 24 14953783 ps
T242 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3539128955 May 28 01:19:26 PM PDT 24 May 28 01:19:30 PM PDT 24 49668717 ps
T216 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3550981040 May 28 01:19:38 PM PDT 24 May 28 01:19:42 PM PDT 24 98248596 ps
T240 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2615954228 May 28 01:19:25 PM PDT 24 May 28 01:19:27 PM PDT 24 48342159 ps
T870 /workspace/coverage/cover_reg_top/45.edn_intr_test.4034857756 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 24650141 ps
T234 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.85670762 May 28 01:19:52 PM PDT 24 May 28 01:19:55 PM PDT 24 18288018 ps
T217 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2452062530 May 28 01:20:09 PM PDT 24 May 28 01:20:11 PM PDT 24 13291751 ps
T871 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2717401391 May 28 01:20:09 PM PDT 24 May 28 01:20:11 PM PDT 24 53486335 ps
T872 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1682757663 May 28 01:20:25 PM PDT 24 May 28 01:20:32 PM PDT 24 27677373 ps
T873 /workspace/coverage/cover_reg_top/1.edn_intr_test.3832121477 May 28 01:19:28 PM PDT 24 May 28 01:19:31 PM PDT 24 15055368 ps
T235 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.534626359 May 28 01:19:52 PM PDT 24 May 28 01:19:54 PM PDT 24 36950209 ps
T218 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2594061230 May 28 01:19:27 PM PDT 24 May 28 01:19:29 PM PDT 24 24780805 ps
T219 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.781705033 May 28 01:19:25 PM PDT 24 May 28 01:19:27 PM PDT 24 28728994 ps
T220 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3804351052 May 28 01:19:40 PM PDT 24 May 28 01:19:43 PM PDT 24 13126213 ps
T874 /workspace/coverage/cover_reg_top/8.edn_intr_test.1877793846 May 28 01:19:54 PM PDT 24 May 28 01:19:56 PM PDT 24 20160948 ps
T875 /workspace/coverage/cover_reg_top/6.edn_intr_test.1529093739 May 28 01:19:46 PM PDT 24 May 28 01:19:49 PM PDT 24 41893646 ps
T243 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4198570903 May 28 01:20:26 PM PDT 24 May 28 01:20:32 PM PDT 24 158328260 ps
T876 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.40527504 May 28 01:20:07 PM PDT 24 May 28 01:20:10 PM PDT 24 229155790 ps
T221 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1048995627 May 28 01:19:48 PM PDT 24 May 28 01:19:50 PM PDT 24 11471974 ps
T877 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2317747366 May 28 01:19:53 PM PDT 24 May 28 01:19:56 PM PDT 24 26772031 ps
T878 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2351884100 May 28 01:19:51 PM PDT 24 May 28 01:19:54 PM PDT 24 36519998 ps
T236 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.431374184 May 28 01:20:07 PM PDT 24 May 28 01:20:09 PM PDT 24 25967880 ps
T879 /workspace/coverage/cover_reg_top/4.edn_tl_errors.584435306 May 28 01:19:37 PM PDT 24 May 28 01:19:39 PM PDT 24 29479741 ps
T222 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3238772531 May 28 01:19:41 PM PDT 24 May 28 01:19:44 PM PDT 24 33526521 ps
T880 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3154041455 May 28 01:19:52 PM PDT 24 May 28 01:19:55 PM PDT 24 26798281 ps
T881 /workspace/coverage/cover_reg_top/19.edn_intr_test.2849383615 May 28 01:20:22 PM PDT 24 May 28 01:20:24 PM PDT 24 36373153 ps
T882 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3188156668 May 28 01:19:25 PM PDT 24 May 28 01:19:28 PM PDT 24 90329824 ps
T223 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1724096884 May 28 01:20:22 PM PDT 24 May 28 01:20:25 PM PDT 24 92642120 ps
T224 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1855210958 May 28 01:19:38 PM PDT 24 May 28 01:19:41 PM PDT 24 20353567 ps
T225 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3729845890 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 15068179 ps
T883 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3253623916 May 28 01:20:11 PM PDT 24 May 28 01:20:15 PM PDT 24 266637587 ps
T884 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3412866996 May 28 01:19:53 PM PDT 24 May 28 01:19:57 PM PDT 24 69160688 ps
T885 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3127961412 May 28 01:19:40 PM PDT 24 May 28 01:19:43 PM PDT 24 38050872 ps
T886 /workspace/coverage/cover_reg_top/21.edn_intr_test.169463696 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 58259961 ps
T887 /workspace/coverage/cover_reg_top/49.edn_intr_test.234408873 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 21095036 ps
T888 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2198508811 May 28 01:19:54 PM PDT 24 May 28 01:19:57 PM PDT 24 28757407 ps
T226 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3462964945 May 28 01:19:37 PM PDT 24 May 28 01:19:39 PM PDT 24 15053839 ps
T227 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1539009186 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 41028244 ps
T889 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2746308733 May 28 01:19:40 PM PDT 24 May 28 01:19:42 PM PDT 24 17333185 ps
T890 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3426342594 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 52673439 ps
T230 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1813945459 May 28 01:19:28 PM PDT 24 May 28 01:19:33 PM PDT 24 471018782 ps
T891 /workspace/coverage/cover_reg_top/41.edn_intr_test.1832208253 May 28 01:20:24 PM PDT 24 May 28 01:20:30 PM PDT 24 37980801 ps
T892 /workspace/coverage/cover_reg_top/15.edn_intr_test.3877141465 May 28 01:20:25 PM PDT 24 May 28 01:20:30 PM PDT 24 14625465 ps
T893 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2263876216 May 28 01:19:51 PM PDT 24 May 28 01:19:53 PM PDT 24 46098876 ps
T894 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3338684796 May 28 01:20:08 PM PDT 24 May 28 01:20:10 PM PDT 24 31946789 ps
T895 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1812842533 May 28 01:20:26 PM PDT 24 May 28 01:20:32 PM PDT 24 111113703 ps
T896 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2696159219 May 28 01:20:23 PM PDT 24 May 28 01:20:28 PM PDT 24 281877712 ps
T897 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3831140104 May 28 01:19:52 PM PDT 24 May 28 01:19:56 PM PDT 24 58120741 ps
T898 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2441578816 May 28 01:19:28 PM PDT 24 May 28 01:19:31 PM PDT 24 70749111 ps
T899 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3031204309 May 28 01:20:22 PM PDT 24 May 28 01:20:26 PM PDT 24 151508815 ps
T900 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2743717292 May 28 01:19:24 PM PDT 24 May 28 01:19:26 PM PDT 24 24816629 ps
T901 /workspace/coverage/cover_reg_top/13.edn_intr_test.2212399276 May 28 01:20:08 PM PDT 24 May 28 01:20:11 PM PDT 24 13729889 ps
T249 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1878333339 May 28 01:19:26 PM PDT 24 May 28 01:19:30 PM PDT 24 75811837 ps
T228 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2471361440 May 28 01:19:41 PM PDT 24 May 28 01:19:43 PM PDT 24 37394149 ps
T902 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1459706320 May 28 01:19:54 PM PDT 24 May 28 01:19:57 PM PDT 24 28474158 ps
T250 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2099511242 May 28 01:19:42 PM PDT 24 May 28 01:19:45 PM PDT 24 268655669 ps
T903 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1728465057 May 28 01:19:38 PM PDT 24 May 28 01:19:43 PM PDT 24 1374252057 ps
T904 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2134741281 May 28 01:19:10 PM PDT 24 May 28 01:19:14 PM PDT 24 72847392 ps
T905 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2267261459 May 28 01:19:37 PM PDT 24 May 28 01:19:39 PM PDT 24 30412781 ps
T906 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3989525620 May 28 01:19:54 PM PDT 24 May 28 01:19:58 PM PDT 24 266757817 ps
T907 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.873585460 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 20909792 ps
T908 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1663841947 May 28 01:20:25 PM PDT 24 May 28 01:20:32 PM PDT 24 815531199 ps
T909 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3281234525 May 28 01:19:38 PM PDT 24 May 28 01:19:41 PM PDT 24 120475839 ps
T910 /workspace/coverage/cover_reg_top/38.edn_intr_test.906720709 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 36064990 ps
T911 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2093569274 May 28 01:20:07 PM PDT 24 May 28 01:20:10 PM PDT 24 62420984 ps
T912 /workspace/coverage/cover_reg_top/47.edn_intr_test.571900327 May 28 01:20:25 PM PDT 24 May 28 01:20:30 PM PDT 24 13549333 ps
T913 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4285224511 May 28 01:19:26 PM PDT 24 May 28 01:19:28 PM PDT 24 70646465 ps
T914 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4292600972 May 28 01:19:48 PM PDT 24 May 28 01:19:51 PM PDT 24 213790228 ps
T915 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2092278464 May 28 01:20:25 PM PDT 24 May 28 01:20:31 PM PDT 24 17274796 ps
T916 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.468409989 May 28 01:19:30 PM PDT 24 May 28 01:19:32 PM PDT 24 21265220 ps
T917 /workspace/coverage/cover_reg_top/18.edn_intr_test.1253700688 May 28 01:20:22 PM PDT 24 May 28 01:20:24 PM PDT 24 18855248 ps
T918 /workspace/coverage/cover_reg_top/39.edn_intr_test.4127273091 May 28 01:20:25 PM PDT 24 May 28 01:20:31 PM PDT 24 14795726 ps
T251 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2279070266 May 28 01:20:24 PM PDT 24 May 28 01:20:30 PM PDT 24 131905845 ps
T919 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2324107555 May 28 01:19:48 PM PDT 24 May 28 01:19:50 PM PDT 24 131953290 ps
T920 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2175762250 May 28 01:19:51 PM PDT 24 May 28 01:19:53 PM PDT 24 584068017 ps
T921 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1721894182 May 28 01:20:07 PM PDT 24 May 28 01:20:09 PM PDT 24 116571827 ps
T922 /workspace/coverage/cover_reg_top/15.edn_tl_errors.348295961 May 28 01:20:08 PM PDT 24 May 28 01:20:10 PM PDT 24 40250719 ps
T923 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2852607166 May 28 01:19:53 PM PDT 24 May 28 01:19:57 PM PDT 24 57470331 ps
T924 /workspace/coverage/cover_reg_top/37.edn_intr_test.438326824 May 28 01:20:25 PM PDT 24 May 28 01:20:31 PM PDT 24 12432820 ps
T925 /workspace/coverage/cover_reg_top/31.edn_intr_test.3466132543 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 20536789 ps
T926 /workspace/coverage/cover_reg_top/29.edn_intr_test.1023407965 May 28 01:20:23 PM PDT 24 May 28 01:20:26 PM PDT 24 37146533 ps
T927 /workspace/coverage/cover_reg_top/42.edn_intr_test.3633201647 May 28 01:20:25 PM PDT 24 May 28 01:20:31 PM PDT 24 14290800 ps
T928 /workspace/coverage/cover_reg_top/44.edn_intr_test.2707853357 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 14787890 ps
T929 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.89202032 May 28 01:20:21 PM PDT 24 May 28 01:20:24 PM PDT 24 184150625 ps
T930 /workspace/coverage/cover_reg_top/35.edn_intr_test.3189692012 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 53933664 ps
T931 /workspace/coverage/cover_reg_top/25.edn_intr_test.4137223391 May 28 01:20:21 PM PDT 24 May 28 01:20:22 PM PDT 24 21490211 ps
T932 /workspace/coverage/cover_reg_top/9.edn_intr_test.3474168445 May 28 01:19:57 PM PDT 24 May 28 01:19:59 PM PDT 24 14333785 ps
T933 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2177704471 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 70899268 ps
T934 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2866493853 May 28 01:19:26 PM PDT 24 May 28 01:19:29 PM PDT 24 12656073 ps
T935 /workspace/coverage/cover_reg_top/2.edn_intr_test.281379786 May 28 01:19:26 PM PDT 24 May 28 01:19:28 PM PDT 24 32762603 ps
T936 /workspace/coverage/cover_reg_top/10.edn_intr_test.3210881207 May 28 01:19:53 PM PDT 24 May 28 01:19:55 PM PDT 24 55271280 ps
T937 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2432410856 May 28 01:19:52 PM PDT 24 May 28 01:19:56 PM PDT 24 146816604 ps
T938 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1913130611 May 28 01:19:27 PM PDT 24 May 28 01:19:30 PM PDT 24 77707924 ps
T939 /workspace/coverage/cover_reg_top/33.edn_intr_test.997591292 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 22635418 ps
T940 /workspace/coverage/cover_reg_top/3.edn_intr_test.790000482 May 28 01:19:26 PM PDT 24 May 28 01:19:29 PM PDT 24 24982866 ps
T941 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3558711307 May 28 01:20:07 PM PDT 24 May 28 01:20:09 PM PDT 24 67779311 ps
T942 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2963068829 May 28 01:20:22 PM PDT 24 May 28 01:20:26 PM PDT 24 25398185 ps
T229 /workspace/coverage/cover_reg_top/15.edn_csr_rw.4119447636 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 14712393 ps
T943 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4022299464 May 28 01:19:52 PM PDT 24 May 28 01:19:55 PM PDT 24 31805248 ps
T944 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.836078671 May 28 01:19:28 PM PDT 24 May 28 01:19:35 PM PDT 24 358291461 ps
T945 /workspace/coverage/cover_reg_top/23.edn_intr_test.2457086614 May 28 01:20:21 PM PDT 24 May 28 01:20:24 PM PDT 24 14339266 ps
T946 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2123681974 May 28 01:19:27 PM PDT 24 May 28 01:19:32 PM PDT 24 689130360 ps
T947 /workspace/coverage/cover_reg_top/11.edn_intr_test.1192645285 May 28 01:19:52 PM PDT 24 May 28 01:19:55 PM PDT 24 32434207 ps
T948 /workspace/coverage/cover_reg_top/36.edn_intr_test.2869106988 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 84424296 ps
T949 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3398464537 May 28 01:19:48 PM PDT 24 May 28 01:19:51 PM PDT 24 76585289 ps
T950 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2360895427 May 28 01:20:24 PM PDT 24 May 28 01:20:32 PM PDT 24 101464500 ps
T951 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3720241966 May 28 01:19:46 PM PDT 24 May 28 01:19:50 PM PDT 24 97971472 ps
T952 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.627859391 May 28 01:19:40 PM PDT 24 May 28 01:19:42 PM PDT 24 72746328 ps
T953 /workspace/coverage/cover_reg_top/43.edn_intr_test.2304292605 May 28 01:20:23 PM PDT 24 May 28 01:20:28 PM PDT 24 41488523 ps
T954 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1969680793 May 28 01:19:39 PM PDT 24 May 28 01:19:42 PM PDT 24 101635442 ps
T955 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2189080309 May 28 01:19:39 PM PDT 24 May 28 01:19:42 PM PDT 24 203349398 ps
T956 /workspace/coverage/cover_reg_top/40.edn_intr_test.1325016778 May 28 01:20:25 PM PDT 24 May 28 01:20:30 PM PDT 24 16557177 ps
T957 /workspace/coverage/cover_reg_top/16.edn_intr_test.3603085704 May 28 01:20:23 PM PDT 24 May 28 01:20:27 PM PDT 24 27737021 ps
T958 /workspace/coverage/cover_reg_top/5.edn_intr_test.3547111038 May 28 01:19:39 PM PDT 24 May 28 01:19:41 PM PDT 24 10928566 ps
T959 /workspace/coverage/cover_reg_top/14.edn_intr_test.2617870807 May 28 01:20:08 PM PDT 24 May 28 01:20:10 PM PDT 24 15055538 ps
T960 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3100051158 May 28 01:20:22 PM PDT 24 May 28 01:20:28 PM PDT 24 454233205 ps
T961 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1570216803 May 28 01:20:11 PM PDT 24 May 28 01:20:13 PM PDT 24 47509014 ps
T962 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3166104666 May 28 01:19:25 PM PDT 24 May 28 01:19:28 PM PDT 24 101322566 ps
T963 /workspace/coverage/cover_reg_top/12.edn_intr_test.2444140076 May 28 01:20:09 PM PDT 24 May 28 01:20:11 PM PDT 24 19901418 ps
T964 /workspace/coverage/cover_reg_top/24.edn_intr_test.880841432 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 31714883 ps
T965 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.447930471 May 28 01:19:57 PM PDT 24 May 28 01:20:00 PM PDT 24 293486831 ps
T966 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3677584959 May 28 01:19:51 PM PDT 24 May 28 01:19:53 PM PDT 24 16328766 ps
T967 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3053544867 May 28 01:19:26 PM PDT 24 May 28 01:19:28 PM PDT 24 13981092 ps
T231 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3487823646 May 28 01:19:29 PM PDT 24 May 28 01:19:32 PM PDT 24 30883223 ps
T968 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3664838765 May 28 01:19:25 PM PDT 24 May 28 01:19:27 PM PDT 24 60561432 ps
T969 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2818646316 May 28 01:19:25 PM PDT 24 May 28 01:19:28 PM PDT 24 354350800 ps
T970 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.205109679 May 28 01:19:24 PM PDT 24 May 28 01:19:27 PM PDT 24 92503402 ps
T971 /workspace/coverage/cover_reg_top/48.edn_intr_test.4049654376 May 28 01:20:26 PM PDT 24 May 28 01:20:31 PM PDT 24 26729681 ps
T972 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.674873924 May 28 01:19:54 PM PDT 24 May 28 01:19:59 PM PDT 24 130016654 ps
T973 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2815371290 May 28 01:19:54 PM PDT 24 May 28 01:19:57 PM PDT 24 55563169 ps
T974 /workspace/coverage/cover_reg_top/27.edn_intr_test.3209972966 May 28 01:20:24 PM PDT 24 May 28 01:20:29 PM PDT 24 30884108 ps
T975 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.150499933 May 28 01:20:21 PM PDT 24 May 28 01:20:25 PM PDT 24 42956116 ps
T976 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2122881379 May 28 01:20:22 PM PDT 24 May 28 01:20:26 PM PDT 24 57684426 ps
T977 /workspace/coverage/cover_reg_top/34.edn_intr_test.160959586 May 28 01:20:25 PM PDT 24 May 28 01:20:31 PM PDT 24 44022512 ps
T978 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.249668682 May 28 01:19:39 PM PDT 24 May 28 01:19:42 PM PDT 24 141370948 ps
T232 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.770496514 May 28 01:19:37 PM PDT 24 May 28 01:19:39 PM PDT 24 40186479 ps
T979 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1072540107 May 28 01:19:52 PM PDT 24 May 28 01:19:56 PM PDT 24 35925618 ps
T980 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.58010519 May 28 01:19:28 PM PDT 24 May 28 01:19:32 PM PDT 24 63955767 ps

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.259276384
Short name T24
Test name
Test status
Simulation time 57987023324 ps
CPU time 1043.92 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:28:18 PM PDT 24
Peak memory 220236 kb
Host smart-e48b2481-2dcf-4636-b3ec-71c7d3745b3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259276384 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.259276384
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.edn_genbits.938419878
Short name T44
Test name
Test status
Simulation time 30563977 ps
CPU time 1.36 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 218088 kb
Host smart-c9a3191e-0fe9-4823-be08-7626cd7dd8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938419878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.938419878
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert.4266527194
Short name T30
Test name
Test status
Simulation time 29275465 ps
CPU time 1.28 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:35 PM PDT 24
Peak memory 215412 kb
Host smart-13b8f47e-359f-46a9-96d6-b23512e1d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266527194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.4266527194
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2818016652
Short name T16
Test name
Test status
Simulation time 5167773766 ps
CPU time 8.25 seconds
Started May 28 02:10:05 PM PDT 24
Finished May 28 02:10:15 PM PDT 24
Peak memory 237640 kb
Host smart-3ca22bc3-51b7-41c2-b7f6-b6248b1dda23
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818016652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2818016652
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/73.edn_err.1252064463
Short name T6
Test name
Test status
Simulation time 24833604 ps
CPU time 1.18 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:24 PM PDT 24
Peak memory 218188 kb
Host smart-d57ffcbf-8a13-44fc-8ae1-c77b1ad3aeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252064463 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1252064463
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/235.edn_genbits.1281486596
Short name T19
Test name
Test status
Simulation time 76077368 ps
CPU time 1.18 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:12 PM PDT 24
Peak memory 219620 kb
Host smart-707e85f2-85a0-4051-94af-a6b684275058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281486596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1281486596
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1706109246
Short name T169
Test name
Test status
Simulation time 20221934 ps
CPU time 1.09 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 217864 kb
Host smart-4735f168-612a-4bc4-af19-2a7497dd42de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706109246 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1706109246
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_alert.572227058
Short name T253
Test name
Test status
Simulation time 25657698 ps
CPU time 1.22 seconds
Started May 28 02:10:00 PM PDT 24
Finished May 28 02:10:03 PM PDT 24
Peak memory 215352 kb
Host smart-08ec9bc3-c925-4da5-934e-61dc0ecc26f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572227058 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.572227058
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.859138936
Short name T4
Test name
Test status
Simulation time 209375995556 ps
CPU time 2243.97 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 225628 kb
Host smart-66c666d4-c797-41d0-ac1c-f7bb07cadfee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859138936 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.859138936
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_regwen.1027974603
Short name T738
Test name
Test status
Simulation time 17850039 ps
CPU time 1.04 seconds
Started May 28 02:09:56 PM PDT 24
Finished May 28 02:09:59 PM PDT 24
Peak memory 206836 kb
Host smart-b1e26f4a-1c28-487d-94b5-09c661bdb8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027974603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1027974603
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_disable.1246118938
Short name T43
Test name
Test status
Simulation time 16304890 ps
CPU time 0.86 seconds
Started May 28 02:11:23 PM PDT 24
Finished May 28 02:11:26 PM PDT 24
Peak memory 216432 kb
Host smart-8d7e9c57-e97b-4d09-be84-c6dac77b6d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246118938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1246118938
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1878333339
Short name T249
Test name
Test status
Simulation time 75811837 ps
CPU time 2.42 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:30 PM PDT 24
Peak memory 206364 kb
Host smart-11f9d042-8b43-4ddb-b43b-39fbb26cd6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878333339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1878333339
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2575861607
Short name T99
Test name
Test status
Simulation time 154244830 ps
CPU time 1.05 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:07 PM PDT 24
Peak memory 216760 kb
Host smart-67b44896-3e8d-43a9-80d9-36de86385455
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575861607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2575861607
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.664507424
Short name T215
Test name
Test status
Simulation time 30961045 ps
CPU time 1 seconds
Started May 28 01:19:53 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 206220 kb
Host smart-ebf29ef4-8c70-40ce-af9b-11aaca8829ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664507424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.664507424
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/default/35.edn_alert.1548702899
Short name T132
Test name
Test status
Simulation time 52897030 ps
CPU time 1.24 seconds
Started May 28 02:11:32 PM PDT 24
Finished May 28 02:11:38 PM PDT 24
Peak memory 215420 kb
Host smart-f08a62f2-5dac-4782-8a68-2feffa942899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548702899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1548702899
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/44.edn_err.357847737
Short name T53
Test name
Test status
Simulation time 42546480 ps
CPU time 0.97 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:57 PM PDT 24
Peak memory 228884 kb
Host smart-9a9c32bd-2f12-4a8f-8316-1e151711731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357847737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.357847737
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/45.edn_err.72854856
Short name T179
Test name
Test status
Simulation time 19742170 ps
CPU time 1.11 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:53 PM PDT 24
Peak memory 214884 kb
Host smart-1209c10d-0d56-464f-8841-1e9f6a15f38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72854856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.72854856
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/253.edn_genbits.3186373711
Short name T9
Test name
Test status
Simulation time 50052325 ps
CPU time 1.9 seconds
Started May 28 02:12:58 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 219728 kb
Host smart-fc88a749-d3be-40b1-8b24-991f19a6fe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186373711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3186373711
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.887563804
Short name T115
Test name
Test status
Simulation time 85900875 ps
CPU time 1.13 seconds
Started May 28 02:10:51 PM PDT 24
Finished May 28 02:10:54 PM PDT 24
Peak memory 216684 kb
Host smart-15eb3cda-e5c6-4c0e-bb1b-cdffcc8f9db9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887563804 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.887563804
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_disable.3141563359
Short name T129
Test name
Test status
Simulation time 16650842 ps
CPU time 0.84 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 216032 kb
Host smart-e9f93bf3-b5b0-40ea-8eb5-059acd62689f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141563359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3141563359
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable.2888334597
Short name T165
Test name
Test status
Simulation time 12302035 ps
CPU time 0.9 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:10:23 PM PDT 24
Peak memory 216192 kb
Host smart-5305881c-f6e5-43fd-9cfb-d04e753cf68b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888334597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2888334597
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3644198382
Short name T37
Test name
Test status
Simulation time 21754103 ps
CPU time 1.14 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 218124 kb
Host smart-939a098b-1695-40f8-ade0-1bb391f9782f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644198382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3644198382
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/6.edn_alert.4118265149
Short name T162
Test name
Test status
Simulation time 92056556 ps
CPU time 1.25 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:10:23 PM PDT 24
Peak memory 215420 kb
Host smart-ebbda79a-96a9-4129-9f8d-c7813d85b71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118265149 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.4118265149
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/140.edn_genbits.3255375040
Short name T47
Test name
Test status
Simulation time 28276803 ps
CPU time 1.26 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 216604 kb
Host smart-567b243d-1b0a-4f09-bccb-aa298addc369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255375040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3255375040
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1955219290
Short name T33
Test name
Test status
Simulation time 23433184 ps
CPU time 1.12 seconds
Started May 28 02:10:00 PM PDT 24
Finished May 28 02:10:02 PM PDT 24
Peak memory 215408 kb
Host smart-90b53965-c1bf-436a-9b69-71c921839b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955219290 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1955219290
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/159.edn_genbits.3436173294
Short name T11
Test name
Test status
Simulation time 48434063 ps
CPU time 1.31 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 219424 kb
Host smart-35fe4919-d744-498a-bece-10137265def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436173294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3436173294
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/240.edn_genbits.1207872547
Short name T267
Test name
Test status
Simulation time 23237749 ps
CPU time 1.23 seconds
Started May 28 02:13:00 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 219108 kb
Host smart-fab82da5-5a52-44a3-ad4b-5f4abe63319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207872547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1207872547
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.1853352581
Short name T259
Test name
Test status
Simulation time 80736809 ps
CPU time 0.92 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 206820 kb
Host smart-41464656-7307-4388-953b-1f47a0e29fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853352581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1853352581
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/27.edn_disable.3778459362
Short name T176
Test name
Test status
Simulation time 13646732 ps
CPU time 0.93 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 216396 kb
Host smart-06d050ba-765d-46f3-9847-c4ab61280ec6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778459362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3778459362
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/34.edn_intr.3983478314
Short name T41
Test name
Test status
Simulation time 22862684 ps
CPU time 0.99 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 215372 kb
Host smart-884855ad-39d0-4fa9-9dba-6467e3835f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983478314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3983478314
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.989657857
Short name T655
Test name
Test status
Simulation time 101330114 ps
CPU time 1.11 seconds
Started May 28 02:09:54 PM PDT 24
Finished May 28 02:09:58 PM PDT 24
Peak memory 219208 kb
Host smart-f79df61a-b736-4b7e-94c9-2feed4e4e11b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989657857 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.989657857
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_disable.1289921933
Short name T143
Test name
Test status
Simulation time 15257947 ps
CPU time 0.94 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 216224 kb
Host smart-2a699da7-7d50-49c7-abf0-f60a9e9b4295
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289921933 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1289921933
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable.1965986234
Short name T180
Test name
Test status
Simulation time 14168447 ps
CPU time 0.96 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:49 PM PDT 24
Peak memory 216240 kb
Host smart-263099e9-0130-424c-9244-20f85364a405
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965986234 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1965986234
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable.3456160173
Short name T173
Test name
Test status
Simulation time 43960891 ps
CPU time 0.84 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 216236 kb
Host smart-3eeb3cb9-f367-4082-9116-1ed6129af77b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456160173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3456160173
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/22.edn_alert.1457980310
Short name T135
Test name
Test status
Simulation time 71803202 ps
CPU time 1.14 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 215424 kb
Host smart-b9ba88f9-419c-4ef6-a868-9c6d446b4c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457980310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1457980310
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1042354471
Short name T794
Test name
Test status
Simulation time 59381431 ps
CPU time 1.64 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:23 PM PDT 24
Peak memory 216656 kb
Host smart-d229dccf-9617-4ffe-ba74-a6470d4aea0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042354471 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1042354471
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1222290285
Short name T120
Test name
Test status
Simulation time 99555503 ps
CPU time 1.22 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:33 PM PDT 24
Peak memory 216652 kb
Host smart-8fcff043-db60-487b-bdb9-ed3d68e2242f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222290285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1222290285
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert_test.3631582992
Short name T22
Test name
Test status
Simulation time 132431093 ps
CPU time 0.9 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:35 PM PDT 24
Peak memory 206296 kb
Host smart-d16c2ad1-d159-4bb5-8476-2f665bb8e15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631582992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3631582992
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_genbits.1776507186
Short name T46
Test name
Test status
Simulation time 45130362 ps
CPU time 1.52 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:49 PM PDT 24
Peak memory 217992 kb
Host smart-29935949-d4d5-4446-9f23-2e901d7da38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776507186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1776507186
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.4060873384
Short name T190
Test name
Test status
Simulation time 74588727 ps
CPU time 1.22 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 215408 kb
Host smart-ae240d40-10f5-44a9-b217-ca345aa8eea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060873384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4060873384
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/127.edn_genbits.3513435572
Short name T285
Test name
Test status
Simulation time 60598220 ps
CPU time 1.33 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 219432 kb
Host smart-1fc9a0c4-827f-4afc-84da-6114401333df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513435572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3513435572
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.835211091
Short name T270
Test name
Test status
Simulation time 44221121 ps
CPU time 1.43 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 217764 kb
Host smart-77cbfb89-0c1a-44f3-8d9c-a6a155a8415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835211091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.835211091
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all.3003726235
Short name T272
Test name
Test status
Simulation time 387382188 ps
CPU time 4.37 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:10:59 PM PDT 24
Peak memory 216496 kb
Host smart-bb0d2fdf-b2a0-48bf-98c9-b65366a44f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003726235 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3003726235
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_intr.2788228601
Short name T158
Test name
Test status
Simulation time 35224817 ps
CPU time 0.88 seconds
Started May 28 02:10:45 PM PDT 24
Finished May 28 02:10:47 PM PDT 24
Peak memory 215280 kb
Host smart-040b3175-dd8b-4484-a2dd-642dca11bb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788228601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2788228601
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3487823646
Short name T231
Test name
Test status
Simulation time 30883223 ps
CPU time 1.24 seconds
Started May 28 01:19:29 PM PDT 24
Finished May 28 01:19:32 PM PDT 24
Peak memory 206208 kb
Host smart-b10faa3b-63e6-4106-a24b-bd5bf0ad2194
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487823646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3487823646
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.883073726
Short name T402
Test name
Test status
Simulation time 119235342940 ps
CPU time 2131.88 seconds
Started May 28 02:09:54 PM PDT 24
Finished May 28 02:45:28 PM PDT 24
Peak memory 227368 kb
Host smart-e875bbd3-5abe-4fc3-9846-b2773f89cd75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883073726 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.883073726
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.36122032
Short name T257
Test name
Test status
Simulation time 38755591 ps
CPU time 0.92 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 206820 kb
Host smart-c2594d90-7265-4b37-b1dd-b524ec2ea201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36122032 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.36122032
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/100.edn_genbits.4283522495
Short name T273
Test name
Test status
Simulation time 62169688 ps
CPU time 1.52 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 216780 kb
Host smart-41c538e1-a008-4089-b13d-9a57cd2d51b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283522495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.4283522495
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/120.edn_genbits.717403811
Short name T276
Test name
Test status
Simulation time 97284382 ps
CPU time 1.08 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:41 PM PDT 24
Peak memory 215056 kb
Host smart-52af160c-768f-4912-8c0b-994b089d015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717403811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.717403811
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.154106365
Short name T264
Test name
Test status
Simulation time 30872489 ps
CPU time 1.35 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:49 PM PDT 24
Peak memory 215432 kb
Host smart-b4f84422-e217-48d2-9faf-42f87c9ccadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154106365 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.154106365
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/156.edn_genbits.2821938361
Short name T290
Test name
Test status
Simulation time 37313833 ps
CPU time 1.34 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:49 PM PDT 24
Peak memory 219492 kb
Host smart-86534ce1-b7f4-4257-b58a-5389999e33c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821938361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2821938361
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.4089985744
Short name T271
Test name
Test status
Simulation time 158614590 ps
CPU time 3.35 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 218676 kb
Host smart-1d930e4e-26f5-456b-9486-561ece86fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089985744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4089985744
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3517220478
Short name T777
Test name
Test status
Simulation time 113607216 ps
CPU time 1.56 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 218520 kb
Host smart-2e4772f3-84bc-4979-b5bb-5cdcf293f9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517220478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3517220478
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.949301343
Short name T292
Test name
Test status
Simulation time 122652245 ps
CPU time 1.51 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 217984 kb
Host smart-eb5c21b3-6d97-4fc3-9450-0651dc4d3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949301343 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.949301343
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2057545573
Short name T262
Test name
Test status
Simulation time 78588247 ps
CPU time 1.21 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 215424 kb
Host smart-405a8c0b-2b98-4487-92f7-e97dcb99cb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057545573 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2057545573
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/289.edn_genbits.161078458
Short name T287
Test name
Test status
Simulation time 181067565 ps
CPU time 1.36 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:12 PM PDT 24
Peak memory 218140 kb
Host smart-1050103c-53e4-420c-bddb-793fb6a031b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161078458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.161078458
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3568380998
Short name T40
Test name
Test status
Simulation time 24888302 ps
CPU time 1.01 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:33 PM PDT 24
Peak memory 215444 kb
Host smart-9cd84aa3-e258-4eec-a8a2-37d7a126fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568380998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3568380998
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/17.edn_alert.939477998
Short name T87
Test name
Test status
Simulation time 56908559 ps
CPU time 1.27 seconds
Started May 28 02:10:51 PM PDT 24
Finished May 28 02:10:54 PM PDT 24
Peak memory 215420 kb
Host smart-773d1bbf-d11b-4a49-a66a-7848d7637e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939477998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.939477998
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/290.edn_genbits.1052208976
Short name T358
Test name
Test status
Simulation time 341787829 ps
CPU time 1.58 seconds
Started May 28 02:13:16 PM PDT 24
Finished May 28 02:13:19 PM PDT 24
Peak memory 219844 kb
Host smart-63869642-a057-4fe9-9148-50baf284f042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052208976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1052208976
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_genbits.646682391
Short name T835
Test name
Test status
Simulation time 86288437 ps
CPU time 1.61 seconds
Started May 28 02:10:17 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 216988 kb
Host smart-dca6a79e-fc31-44b2-b1c2-10db4e90d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646682391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.646682391
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2743717292
Short name T900
Test name
Test status
Simulation time 24816629 ps
CPU time 1.16 seconds
Started May 28 01:19:24 PM PDT 24
Finished May 28 01:19:26 PM PDT 24
Peak memory 206108 kb
Host smart-b74fc2bb-6e0a-4c6e-a896-a074e5f9efca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743717292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2743717292
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.836078671
Short name T944
Test name
Test status
Simulation time 358291461 ps
CPU time 5.08 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:35 PM PDT 24
Peak memory 206092 kb
Host smart-e7615a48-a1d7-42f9-8f67-ef8ea7108111
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836078671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.836078671
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2594061230
Short name T218
Test name
Test status
Simulation time 24780805 ps
CPU time 0.88 seconds
Started May 28 01:19:27 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 206212 kb
Host smart-7e826b07-63c2-4c08-8e7d-e282d89f3934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594061230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2594061230
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.205109679
Short name T970
Test name
Test status
Simulation time 92503402 ps
CPU time 1.3 seconds
Started May 28 01:19:24 PM PDT 24
Finished May 28 01:19:27 PM PDT 24
Peak memory 214324 kb
Host smart-0ccd3d3a-6fbb-4230-809a-283151085d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205109679 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.205109679
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2866493853
Short name T934
Test name
Test status
Simulation time 12656073 ps
CPU time 0.91 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 206092 kb
Host smart-a187d698-8630-4705-b614-539b9897240f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866493853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2866493853
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3183675912
Short name T869
Test name
Test status
Simulation time 14953783 ps
CPU time 0.87 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 205968 kb
Host smart-b48273fb-9d42-4cc1-83f8-a3f3f2a89b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183675912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3183675912
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2441578816
Short name T898
Test name
Test status
Simulation time 70749111 ps
CPU time 1.1 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:31 PM PDT 24
Peak memory 206132 kb
Host smart-07c461f5-cebd-4002-a2bc-83bb4073f257
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441578816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2441578816
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2134741281
Short name T904
Test name
Test status
Simulation time 72847392 ps
CPU time 1.46 seconds
Started May 28 01:19:10 PM PDT 24
Finished May 28 01:19:14 PM PDT 24
Peak memory 214512 kb
Host smart-19ee7c10-780c-44d6-b028-999f94326966
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134741281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2134741281
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3188156668
Short name T882
Test name
Test status
Simulation time 90329824 ps
CPU time 1.57 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 206160 kb
Host smart-3c829ee3-124d-4596-9bb8-68b372ce38f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188156668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3188156668
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1813945459
Short name T230
Test name
Test status
Simulation time 471018782 ps
CPU time 3.57 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:33 PM PDT 24
Peak memory 206308 kb
Host smart-ece6c256-8483-44c3-a2a3-036ed323000d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813945459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1813945459
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3664838765
Short name T968
Test name
Test status
Simulation time 60561432 ps
CPU time 0.98 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:27 PM PDT 24
Peak memory 206128 kb
Host smart-fc3a9df7-1f6e-4cfc-bf54-4213a2d1872d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664838765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3664838765
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4225493443
Short name T855
Test name
Test status
Simulation time 221130353 ps
CPU time 2.09 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 214544 kb
Host smart-a12387cc-d388-4027-ba58-6928e09e7398
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225493443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4225493443
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4285224511
Short name T913
Test name
Test status
Simulation time 70646465 ps
CPU time 0.84 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 206104 kb
Host smart-14cdd3c7-4a8a-4da9-8932-ea2f5c77ca8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285224511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4285224511
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3832121477
Short name T873
Test name
Test status
Simulation time 15055368 ps
CPU time 0.94 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:31 PM PDT 24
Peak memory 206084 kb
Host smart-b4cbd363-b79e-4ca9-933f-c3f8d8503897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832121477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3832121477
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.781705033
Short name T219
Test name
Test status
Simulation time 28728994 ps
CPU time 1.33 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:27 PM PDT 24
Peak memory 206284 kb
Host smart-027a0244-9794-4549-8d79-c4cca23e83ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781705033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.781705033
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2123681974
Short name T946
Test name
Test status
Simulation time 689130360 ps
CPU time 3.57 seconds
Started May 28 01:19:27 PM PDT 24
Finished May 28 01:19:32 PM PDT 24
Peak memory 214336 kb
Host smart-76d19962-a416-4d4f-aa80-47595287ae5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123681974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2123681974
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.249263234
Short name T867
Test name
Test status
Simulation time 19028400 ps
CPU time 0.96 seconds
Started May 28 01:19:55 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 206060 kb
Host smart-e728e5c6-0f50-4532-a12a-7538db5b7181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249263234 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.249263234
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2263876216
Short name T893
Test name
Test status
Simulation time 46098876 ps
CPU time 0.86 seconds
Started May 28 01:19:51 PM PDT 24
Finished May 28 01:19:53 PM PDT 24
Peak memory 206216 kb
Host smart-aca8440a-5271-49fe-bb87-e13e95c8b3f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263876216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2263876216
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3210881207
Short name T936
Test name
Test status
Simulation time 55271280 ps
CPU time 0.85 seconds
Started May 28 01:19:53 PM PDT 24
Finished May 28 01:19:55 PM PDT 24
Peak memory 206076 kb
Host smart-85cb4e8c-54ff-46e7-aa44-f1318f6929f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210881207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3210881207
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2815371290
Short name T973
Test name
Test status
Simulation time 55563169 ps
CPU time 0.97 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 206116 kb
Host smart-38bfe324-66e0-4362-9892-8a3cd44f5463
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815371290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2815371290
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3412866996
Short name T884
Test name
Test status
Simulation time 69160688 ps
CPU time 2.34 seconds
Started May 28 01:19:53 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 214464 kb
Host smart-03d281ef-ea0d-42be-b491-6d5cc1e00dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412866996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3412866996
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.674873924
Short name T972
Test name
Test status
Simulation time 130016654 ps
CPU time 3.05 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:59 PM PDT 24
Peak memory 206220 kb
Host smart-6b1c8d0d-9bfe-4f68-a165-54db88604ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674873924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.674873924
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.520054166
Short name T204
Test name
Test status
Simulation time 17432480 ps
CPU time 1 seconds
Started May 28 01:19:58 PM PDT 24
Finished May 28 01:20:00 PM PDT 24
Peak memory 206276 kb
Host smart-fdaf373e-4677-4325-ba5d-94f94bbcb910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520054166 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.520054166
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1459706320
Short name T902
Test name
Test status
Simulation time 28474158 ps
CPU time 0.8 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 206104 kb
Host smart-6807e426-0954-423f-97d5-e3ea23160f3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459706320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1459706320
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1192645285
Short name T947
Test name
Test status
Simulation time 32434207 ps
CPU time 0.89 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:55 PM PDT 24
Peak memory 206184 kb
Host smart-8375ae01-0328-475e-9706-736e9922ee23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192645285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1192645285
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.85670762
Short name T234
Test name
Test status
Simulation time 18288018 ps
CPU time 1.14 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:55 PM PDT 24
Peak memory 206288 kb
Host smart-56d267b4-30b7-4739-8a2b-36263d9b5a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85670762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_out
standing.85670762
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3831140104
Short name T897
Test name
Test status
Simulation time 58120741 ps
CPU time 2.2 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 214528 kb
Host smart-bf094b15-95b2-47ab-98c0-e93ffdecfec4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831140104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3831140104
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3989525620
Short name T906
Test name
Test status
Simulation time 266757817 ps
CPU time 2.12 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:58 PM PDT 24
Peak memory 206240 kb
Host smart-46393eb5-479b-4505-a86e-b115d41bee70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989525620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3989525620
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1570216803
Short name T961
Test name
Test status
Simulation time 47509014 ps
CPU time 1.26 seconds
Started May 28 01:20:11 PM PDT 24
Finished May 28 01:20:13 PM PDT 24
Peak memory 214684 kb
Host smart-825f3cf7-af32-4e3c-b156-2cbae9530eaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570216803 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1570216803
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3338684796
Short name T894
Test name
Test status
Simulation time 31946789 ps
CPU time 0.8 seconds
Started May 28 01:20:08 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 206124 kb
Host smart-75dfd37b-fa71-40e9-a208-f92442fa47cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338684796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3338684796
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2444140076
Short name T963
Test name
Test status
Simulation time 19901418 ps
CPU time 0.89 seconds
Started May 28 01:20:09 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 206088 kb
Host smart-de9e1546-58e5-45db-b0f5-92d2d444e3ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444140076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2444140076
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.431374184
Short name T236
Test name
Test status
Simulation time 25967880 ps
CPU time 1.2 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:09 PM PDT 24
Peak memory 206140 kb
Host smart-a4eead72-efc7-4221-85c6-2ad0ef0c554d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431374184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.431374184
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1072540107
Short name T979
Test name
Test status
Simulation time 35925618 ps
CPU time 2.34 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 214288 kb
Host smart-2fd34411-0b0a-4cde-93bb-d5526ee993a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072540107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1072540107
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2175762250
Short name T920
Test name
Test status
Simulation time 584068017 ps
CPU time 1.71 seconds
Started May 28 01:19:51 PM PDT 24
Finished May 28 01:19:53 PM PDT 24
Peak memory 214396 kb
Host smart-8ee617ef-e7d9-4a6b-95db-6186669bdfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175762250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2175762250
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2093569274
Short name T911
Test name
Test status
Simulation time 62420984 ps
CPU time 1.24 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 214484 kb
Host smart-8c1d494a-d824-4a69-9bb8-78464e826cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093569274 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2093569274
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2452062530
Short name T217
Test name
Test status
Simulation time 13291751 ps
CPU time 0.89 seconds
Started May 28 01:20:09 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 206148 kb
Host smart-cc4cc869-ade6-4eba-9617-0e12b7274b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452062530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2452062530
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2212399276
Short name T901
Test name
Test status
Simulation time 13729889 ps
CPU time 0.91 seconds
Started May 28 01:20:08 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 205972 kb
Host smart-afc6a98b-d4ff-45f0-90d5-7db0f300b282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212399276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2212399276
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3558711307
Short name T941
Test name
Test status
Simulation time 67779311 ps
CPU time 1.34 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:09 PM PDT 24
Peak memory 206108 kb
Host smart-1f54521e-44a4-4af0-9f38-10ad72b6c219
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558711307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3558711307
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3253623916
Short name T883
Test name
Test status
Simulation time 266637587 ps
CPU time 2.87 seconds
Started May 28 01:20:11 PM PDT 24
Finished May 28 01:20:15 PM PDT 24
Peak memory 214636 kb
Host smart-51c1e263-25dc-4733-b517-009a1e3046d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253623916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3253623916
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2524474011
Short name T241
Test name
Test status
Simulation time 43008125 ps
CPU time 1.59 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 206256 kb
Host smart-23989f81-d2f8-47f9-84cc-d4aca304c075
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524474011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2524474011
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2717401391
Short name T871
Test name
Test status
Simulation time 53486335 ps
CPU time 1.34 seconds
Started May 28 01:20:09 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 216688 kb
Host smart-a4c21720-13e6-4a80-8540-2b416a89c5dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717401391 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2717401391
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2622716198
Short name T214
Test name
Test status
Simulation time 40358947 ps
CPU time 0.87 seconds
Started May 28 01:20:08 PM PDT 24
Finished May 28 01:20:11 PM PDT 24
Peak memory 206056 kb
Host smart-388e6eb3-5294-425a-8b02-999409e3bbb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622716198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2622716198
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2617870807
Short name T959
Test name
Test status
Simulation time 15055538 ps
CPU time 0.9 seconds
Started May 28 01:20:08 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 206056 kb
Host smart-f2f08348-5c41-42b0-b26c-7b2cc9ffa5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617870807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2617870807
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1721894182
Short name T921
Test name
Test status
Simulation time 116571827 ps
CPU time 1.05 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:09 PM PDT 24
Peak memory 206068 kb
Host smart-11e29820-60d4-46eb-8623-b40024cd65a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721894182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1721894182
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1164957101
Short name T866
Test name
Test status
Simulation time 54129558 ps
CPU time 2.22 seconds
Started May 28 01:20:09 PM PDT 24
Finished May 28 01:20:12 PM PDT 24
Peak memory 222412 kb
Host smart-b2f290c2-857e-4c80-98cb-4b7112db978b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164957101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1164957101
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.40527504
Short name T876
Test name
Test status
Simulation time 229155790 ps
CPU time 1.6 seconds
Started May 28 01:20:07 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 214396 kb
Host smart-e486fcbc-08d2-426c-8852-297f537ae82e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.40527504
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.150499933
Short name T975
Test name
Test status
Simulation time 42956116 ps
CPU time 1.28 seconds
Started May 28 01:20:21 PM PDT 24
Finished May 28 01:20:25 PM PDT 24
Peak memory 214384 kb
Host smart-6aa81b7f-280f-43f3-a41c-7f1b5acecc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150499933 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.150499933
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.4119447636
Short name T229
Test name
Test status
Simulation time 14712393 ps
CPU time 0.93 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206216 kb
Host smart-1ead6225-6a0a-418c-aaba-0703adbacac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119447636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.4119447636
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3877141465
Short name T892
Test name
Test status
Simulation time 14625465 ps
CPU time 0.9 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:30 PM PDT 24
Peak memory 206092 kb
Host smart-9105f161-4185-494d-8f1f-22eed4637a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877141465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3877141465
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2177704471
Short name T933
Test name
Test status
Simulation time 70899268 ps
CPU time 1.14 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206224 kb
Host smart-06f425ef-1fca-4bca-9a1a-4baa9cf1e941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177704471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2177704471
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.348295961
Short name T922
Test name
Test status
Simulation time 40250719 ps
CPU time 1.71 seconds
Started May 28 01:20:08 PM PDT 24
Finished May 28 01:20:10 PM PDT 24
Peak memory 214328 kb
Host smart-4c72d9e1-21c3-4e66-add1-93f55e023ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348295961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.348295961
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.89202032
Short name T929
Test name
Test status
Simulation time 184150625 ps
CPU time 1.71 seconds
Started May 28 01:20:21 PM PDT 24
Finished May 28 01:20:24 PM PDT 24
Peak memory 206144 kb
Host smart-6a6829ca-6e9a-4429-bb92-fae1fdae0262
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89202032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.89202032
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2963068829
Short name T942
Test name
Test status
Simulation time 25398185 ps
CPU time 1.22 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:26 PM PDT 24
Peak memory 216164 kb
Host smart-bf8b50e4-f9a2-4ac6-ad7d-1651118ad88c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963068829 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2963068829
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3729845890
Short name T225
Test name
Test status
Simulation time 15068179 ps
CPU time 0.9 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 206112 kb
Host smart-c835181e-d306-43cf-abfe-30a84262166e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729845890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3729845890
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3603085704
Short name T957
Test name
Test status
Simulation time 27737021 ps
CPU time 0.77 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 205892 kb
Host smart-4f5e4e5e-8679-478d-acbd-666db7d3426e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603085704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3603085704
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.873585460
Short name T907
Test name
Test status
Simulation time 20909792 ps
CPU time 1.14 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 206180 kb
Host smart-5d7c4a1e-86a5-4b15-8532-793487baf793
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873585460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.873585460
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1682757663
Short name T872
Test name
Test status
Simulation time 27677373 ps
CPU time 1.99 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 214380 kb
Host smart-dee1af50-cc5a-412d-880f-5c608fe200eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682757663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1682757663
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2279070266
Short name T251
Test name
Test status
Simulation time 131905845 ps
CPU time 2.27 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:30 PM PDT 24
Peak memory 206144 kb
Host smart-569a8f42-42f6-4035-a27c-2a1a64a8d958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279070266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2279070266
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2760925771
Short name T863
Test name
Test status
Simulation time 64248858 ps
CPU time 1.56 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 214564 kb
Host smart-73c15ea2-9f45-4a41-91c1-5cef2d2260a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760925771 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2760925771
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1539009186
Short name T227
Test name
Test status
Simulation time 41028244 ps
CPU time 0.82 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 205956 kb
Host smart-2acd276b-823a-401f-9128-a80e7d191614
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539009186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1539009186
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3351073050
Short name T854
Test name
Test status
Simulation time 23289944 ps
CPU time 0.81 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:26 PM PDT 24
Peak memory 206044 kb
Host smart-0e1556ed-6090-4c17-bd9a-103232d88c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351073050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3351073050
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2696159219
Short name T896
Test name
Test status
Simulation time 281877712 ps
CPU time 1.54 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:28 PM PDT 24
Peak memory 206420 kb
Host smart-da607ef3-3db1-4533-a372-26549a7835df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696159219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2696159219
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3031204309
Short name T899
Test name
Test status
Simulation time 151508815 ps
CPU time 2.87 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:26 PM PDT 24
Peak memory 214504 kb
Host smart-9153af7d-0c9f-43dc-aec2-39e44cbcd49d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031204309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3031204309
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4198570903
Short name T243
Test name
Test status
Simulation time 158328260 ps
CPU time 1.55 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 206216 kb
Host smart-cbcb30dd-175d-4e65-ab4e-4e2c92df3172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198570903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4198570903
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1812842533
Short name T895
Test name
Test status
Simulation time 111113703 ps
CPU time 1.42 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 214468 kb
Host smart-22e66353-e74d-472f-8a1e-3fef55e741fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812842533 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1812842533
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1724096884
Short name T223
Test name
Test status
Simulation time 92642120 ps
CPU time 0.89 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:25 PM PDT 24
Peak memory 206216 kb
Host smart-56500277-f720-4438-96e9-2d2d520f7650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724096884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1724096884
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1253700688
Short name T917
Test name
Test status
Simulation time 18855248 ps
CPU time 0.82 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:24 PM PDT 24
Peak memory 205976 kb
Host smart-626024a3-e697-4047-9e17-4b07e2edb82e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253700688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1253700688
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1929754238
Short name T233
Test name
Test status
Simulation time 39337208 ps
CPU time 1.01 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 206076 kb
Host smart-cdf00890-739e-4fd6-873b-acfa8689c3ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929754238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1929754238
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2360895427
Short name T950
Test name
Test status
Simulation time 101464500 ps
CPU time 4.06 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 214416 kb
Host smart-7216414b-38ee-436e-a8e5-03dea24b0a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360895427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2360895427
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2122881379
Short name T976
Test name
Test status
Simulation time 57684426 ps
CPU time 1.75 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:26 PM PDT 24
Peak memory 206220 kb
Host smart-94bf8d92-deea-4e90-bf41-fd52bf8a2cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122881379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2122881379
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.281188055
Short name T852
Test name
Test status
Simulation time 19608079 ps
CPU time 1.07 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206304 kb
Host smart-b0fd69c7-01fa-4026-9e34-5b5c01cd1b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281188055 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.281188055
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2092278464
Short name T915
Test name
Test status
Simulation time 17274796 ps
CPU time 0.91 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 206108 kb
Host smart-142ceaf4-c305-48b5-8f7b-3d2cdbcc1b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092278464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2092278464
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2849383615
Short name T881
Test name
Test status
Simulation time 36373153 ps
CPU time 0.79 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:24 PM PDT 24
Peak memory 205864 kb
Host smart-6586b305-0e21-45a1-a2a7-1a2ee6a4ae8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849383615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2849383615
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3426342594
Short name T890
Test name
Test status
Simulation time 52673439 ps
CPU time 1.35 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 206120 kb
Host smart-69ab2da4-90e7-40f8-9224-80fed452c238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426342594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3426342594
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1663841947
Short name T908
Test name
Test status
Simulation time 815531199 ps
CPU time 2.67 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:32 PM PDT 24
Peak memory 214304 kb
Host smart-ebb34d16-fe33-4bf9-b3ba-de572fc9e9b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663841947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1663841947
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3100051158
Short name T960
Test name
Test status
Simulation time 454233205 ps
CPU time 2.22 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:28 PM PDT 24
Peak memory 206112 kb
Host smart-1b9bbc85-b2b2-4cf3-b0bc-669980849bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100051158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3100051158
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2538249137
Short name T213
Test name
Test status
Simulation time 19134747 ps
CPU time 1.28 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:31 PM PDT 24
Peak memory 206124 kb
Host smart-15b9a086-74c3-4173-b071-65146034f3f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538249137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2538249137
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3447851083
Short name T238
Test name
Test status
Simulation time 396109055 ps
CPU time 2.2 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:30 PM PDT 24
Peak memory 206320 kb
Host smart-645c38a8-06fb-469d-9f08-fdccef10db7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447851083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3447851083
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2615954228
Short name T240
Test name
Test status
Simulation time 48342159 ps
CPU time 0.87 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:27 PM PDT 24
Peak memory 206116 kb
Host smart-0209afb9-894b-4a78-8bab-2384be43a63c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615954228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2615954228
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1913130611
Short name T938
Test name
Test status
Simulation time 77707924 ps
CPU time 1.18 seconds
Started May 28 01:19:27 PM PDT 24
Finished May 28 01:19:30 PM PDT 24
Peak memory 214780 kb
Host smart-b11c5fe0-cc3c-44bf-8eb9-6b186e286256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913130611 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1913130611
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2975620549
Short name T237
Test name
Test status
Simulation time 62501284 ps
CPU time 0.85 seconds
Started May 28 01:19:30 PM PDT 24
Finished May 28 01:19:32 PM PDT 24
Peak memory 206016 kb
Host smart-95b44d3a-893b-4e12-a52c-75665ea814d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975620549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2975620549
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.281379786
Short name T935
Test name
Test status
Simulation time 32762603 ps
CPU time 0.8 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 205996 kb
Host smart-158b337d-369b-4464-b0cb-4e9cf6e53708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281379786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.281379786
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.58010519
Short name T980
Test name
Test status
Simulation time 63955767 ps
CPU time 1.57 seconds
Started May 28 01:19:28 PM PDT 24
Finished May 28 01:19:32 PM PDT 24
Peak memory 206220 kb
Host smart-5eb07a93-07c7-4863-a09a-69b6c9636d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58010519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_outs
tanding.58010519
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.235290469
Short name T862
Test name
Test status
Simulation time 174460858 ps
CPU time 3.07 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 214300 kb
Host smart-3a174a13-25c8-4055-b0ca-f38286129605
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235290469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.235290469
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3539128955
Short name T242
Test name
Test status
Simulation time 49668717 ps
CPU time 1.67 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:30 PM PDT 24
Peak memory 206084 kb
Host smart-c6befae5-d7bc-4811-9419-f4972082ad5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539128955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3539128955
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1378352567
Short name T859
Test name
Test status
Simulation time 14121030 ps
CPU time 0.85 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:25 PM PDT 24
Peak memory 206092 kb
Host smart-191c8392-cd26-48cf-a02e-3589cda11149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378352567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1378352567
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.169463696
Short name T886
Test name
Test status
Simulation time 58259961 ps
CPU time 0.87 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 205968 kb
Host smart-4dd96503-d224-4823-b072-3d3b24a081d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169463696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.169463696
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.4094648415
Short name T864
Test name
Test status
Simulation time 66144219 ps
CPU time 0.84 seconds
Started May 28 01:20:21 PM PDT 24
Finished May 28 01:20:22 PM PDT 24
Peak memory 206088 kb
Host smart-a884db3f-b34f-4e71-85ee-8631cfac9e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094648415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.4094648415
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2457086614
Short name T945
Test name
Test status
Simulation time 14339266 ps
CPU time 0.91 seconds
Started May 28 01:20:21 PM PDT 24
Finished May 28 01:20:24 PM PDT 24
Peak memory 206100 kb
Host smart-0965684a-ffda-4b19-8b12-23d6b0914025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457086614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2457086614
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.880841432
Short name T964
Test name
Test status
Simulation time 31714883 ps
CPU time 0.89 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206012 kb
Host smart-32b67eb1-3b25-4118-807d-a0c41116e8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880841432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.880841432
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4137223391
Short name T931
Test name
Test status
Simulation time 21490211 ps
CPU time 0.8 seconds
Started May 28 01:20:21 PM PDT 24
Finished May 28 01:20:22 PM PDT 24
Peak memory 205984 kb
Host smart-c6fd8bbd-879e-476e-bd30-5ce9f5453790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137223391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4137223391
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1850452411
Short name T865
Test name
Test status
Simulation time 35633358 ps
CPU time 0.8 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206084 kb
Host smart-de8ed1fc-8234-4a06-9a4e-fe3228073a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850452411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1850452411
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3209972966
Short name T974
Test name
Test status
Simulation time 30884108 ps
CPU time 0.82 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 205912 kb
Host smart-9411b684-961a-4927-8660-a2e6ed627961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209972966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3209972966
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2613999327
Short name T858
Test name
Test status
Simulation time 31056677 ps
CPU time 0.86 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205984 kb
Host smart-8b8ab4e7-c72b-4fd7-a51d-bbe847a3cb32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613999327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2613999327
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1023407965
Short name T926
Test name
Test status
Simulation time 37146533 ps
CPU time 0.85 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:26 PM PDT 24
Peak memory 205896 kb
Host smart-8874f606-33f1-4e84-b42d-12dc6b3d96c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023407965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1023407965
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.770496514
Short name T232
Test name
Test status
Simulation time 40186479 ps
CPU time 1.17 seconds
Started May 28 01:19:37 PM PDT 24
Finished May 28 01:19:39 PM PDT 24
Peak memory 206040 kb
Host smart-0b8b559e-b4b9-41c5-bf35-99bb449d67e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770496514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.770496514
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2290697374
Short name T239
Test name
Test status
Simulation time 176267962 ps
CPU time 5.41 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:33 PM PDT 24
Peak memory 206108 kb
Host smart-00c45c04-24df-4e8b-b300-5d3b424256b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290697374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2290697374
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.468409989
Short name T916
Test name
Test status
Simulation time 21265220 ps
CPU time 0.91 seconds
Started May 28 01:19:30 PM PDT 24
Finished May 28 01:19:32 PM PDT 24
Peak memory 206108 kb
Host smart-a41f0424-7ef8-4ca3-b259-b61e506fc20f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468409989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.468409989
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2479595658
Short name T853
Test name
Test status
Simulation time 77494253 ps
CPU time 1.61 seconds
Started May 28 01:19:37 PM PDT 24
Finished May 28 01:19:40 PM PDT 24
Peak memory 214384 kb
Host smart-c0a6d395-33d8-4427-929c-c78bac97b1d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479595658 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2479595658
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3053544867
Short name T967
Test name
Test status
Simulation time 13981092 ps
CPU time 0.83 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 206040 kb
Host smart-2b2f7283-147b-4e6c-8687-7e12b42440fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053544867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3053544867
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.790000482
Short name T940
Test name
Test status
Simulation time 24982866 ps
CPU time 0.9 seconds
Started May 28 01:19:26 PM PDT 24
Finished May 28 01:19:29 PM PDT 24
Peak memory 205980 kb
Host smart-121c204d-d11a-4111-89cb-cdb55240b980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790000482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.790000482
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.249668682
Short name T978
Test name
Test status
Simulation time 141370948 ps
CPU time 1.34 seconds
Started May 28 01:19:39 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 206112 kb
Host smart-09eb17a3-e7de-4e71-8acf-82793a54028c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249668682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.249668682
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3166104666
Short name T962
Test name
Test status
Simulation time 101322566 ps
CPU time 2.29 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 214412 kb
Host smart-68a5c65b-54b2-4a98-8a5c-f9a546cee5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166104666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3166104666
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2818646316
Short name T969
Test name
Test status
Simulation time 354350800 ps
CPU time 1.65 seconds
Started May 28 01:19:25 PM PDT 24
Finished May 28 01:19:28 PM PDT 24
Peak memory 206216 kb
Host smart-ede1c1e4-7dbd-46c6-90f4-8383757a2a32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818646316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2818646316
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3798690240
Short name T868
Test name
Test status
Simulation time 35113716 ps
CPU time 0.8 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 205912 kb
Host smart-4fad6cf7-7e00-49d2-b93e-c6dbe4b39e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798690240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3798690240
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3466132543
Short name T925
Test name
Test status
Simulation time 20536789 ps
CPU time 0.81 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205984 kb
Host smart-007f123f-56df-43bf-b92e-b80a4afc7b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466132543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3466132543
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2059714217
Short name T861
Test name
Test status
Simulation time 19265239 ps
CPU time 0.86 seconds
Started May 28 01:20:22 PM PDT 24
Finished May 28 01:20:24 PM PDT 24
Peak memory 206092 kb
Host smart-233c11c1-4e65-444c-a427-7a94ba2d5f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059714217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2059714217
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.997591292
Short name T939
Test name
Test status
Simulation time 22635418 ps
CPU time 0.87 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 205968 kb
Host smart-9c70247e-d158-4601-aca5-5b09830f23be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997591292 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.997591292
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.160959586
Short name T977
Test name
Test status
Simulation time 44022512 ps
CPU time 0.77 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205880 kb
Host smart-b916361f-bd06-4ac2-adf2-85b37503b8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160959586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.160959586
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3189692012
Short name T930
Test name
Test status
Simulation time 53933664 ps
CPU time 0.78 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 205996 kb
Host smart-6d7bd397-a28c-4b7c-abeb-4da2e662ef17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189692012 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3189692012
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2869106988
Short name T948
Test name
Test status
Simulation time 84424296 ps
CPU time 0.91 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:27 PM PDT 24
Peak memory 206084 kb
Host smart-0410ccbc-d3d4-4182-954b-a71146c7fc9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869106988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2869106988
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.438326824
Short name T924
Test name
Test status
Simulation time 12432820 ps
CPU time 0.92 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205980 kb
Host smart-dff7a31d-9acf-478f-8cc5-2c80fa4fc64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438326824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.438326824
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.906720709
Short name T910
Test name
Test status
Simulation time 36064990 ps
CPU time 0.84 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205872 kb
Host smart-6274b9f5-ac80-4602-adc8-193966697e33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906720709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.906720709
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4127273091
Short name T918
Test name
Test status
Simulation time 14795726 ps
CPU time 0.89 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205980 kb
Host smart-5a4d79b4-4516-4d70-8eb2-370863f761ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127273091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4127273091
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2471361440
Short name T228
Test name
Test status
Simulation time 37394149 ps
CPU time 1.26 seconds
Started May 28 01:19:41 PM PDT 24
Finished May 28 01:19:43 PM PDT 24
Peak memory 206256 kb
Host smart-3989d177-0a89-4893-9b6f-d424e696f698
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471361440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2471361440
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3550981040
Short name T216
Test name
Test status
Simulation time 98248596 ps
CPU time 3.1 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 206152 kb
Host smart-22b8e645-0e97-49a9-bb33-d47b691bb0dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550981040 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3550981040
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1855210958
Short name T224
Test name
Test status
Simulation time 20353567 ps
CPU time 1.03 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 206216 kb
Host smart-3f3ed2ef-92c2-47c0-bb95-80c358e7739e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855210958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1855210958
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1899916351
Short name T203
Test name
Test status
Simulation time 21838657 ps
CPU time 1.13 seconds
Started May 28 01:19:39 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 214400 kb
Host smart-bd516a0e-2346-4656-83c0-ac98e5ba0973
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899916351 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1899916351
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2746308733
Short name T889
Test name
Test status
Simulation time 17333185 ps
CPU time 0.83 seconds
Started May 28 01:19:40 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 206152 kb
Host smart-2cdeec13-0d4e-431d-9899-496053954830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746308733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2746308733
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2556551654
Short name T856
Test name
Test status
Simulation time 24907769 ps
CPU time 0.82 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:40 PM PDT 24
Peak memory 205964 kb
Host smart-428a665f-88f1-4648-9f34-14c98a7631d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556551654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2556551654
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3238772531
Short name T222
Test name
Test status
Simulation time 33526521 ps
CPU time 1.51 seconds
Started May 28 01:19:41 PM PDT 24
Finished May 28 01:19:44 PM PDT 24
Peak memory 206220 kb
Host smart-ddf13fa8-0343-47f2-8612-9d84f2274aea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238772531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3238772531
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.584435306
Short name T879
Test name
Test status
Simulation time 29479741 ps
CPU time 1.98 seconds
Started May 28 01:19:37 PM PDT 24
Finished May 28 01:19:39 PM PDT 24
Peak memory 214480 kb
Host smart-cd6c1f8c-b653-42fa-9955-39c07e012961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584435306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.584435306
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2099511242
Short name T250
Test name
Test status
Simulation time 268655669 ps
CPU time 2.25 seconds
Started May 28 01:19:42 PM PDT 24
Finished May 28 01:19:45 PM PDT 24
Peak memory 206280 kb
Host smart-19b3ebef-8874-4bb7-91ae-6c15c17ff9e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099511242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2099511242
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1325016778
Short name T956
Test name
Test status
Simulation time 16557177 ps
CPU time 0.74 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:30 PM PDT 24
Peak memory 205884 kb
Host smart-44bcbcd1-78ad-49b0-9840-84e4fb01ad9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325016778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1325016778
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1832208253
Short name T891
Test name
Test status
Simulation time 37980801 ps
CPU time 0.84 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:30 PM PDT 24
Peak memory 205996 kb
Host smart-b9155749-b9d3-494b-b6ae-3597ce24cf15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832208253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1832208253
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3633201647
Short name T927
Test name
Test status
Simulation time 14290800 ps
CPU time 0.91 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 206088 kb
Host smart-db0458ca-969e-4ae0-8dc6-5086ae9ff0fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633201647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3633201647
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2304292605
Short name T953
Test name
Test status
Simulation time 41488523 ps
CPU time 0.84 seconds
Started May 28 01:20:23 PM PDT 24
Finished May 28 01:20:28 PM PDT 24
Peak memory 206088 kb
Host smart-644e8cc8-325a-4751-b41b-dda1146aba66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304292605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2304292605
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2707853357
Short name T928
Test name
Test status
Simulation time 14787890 ps
CPU time 0.9 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206092 kb
Host smart-ec5b190d-0acc-4335-a847-f19d7c192901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707853357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2707853357
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4034857756
Short name T870
Test name
Test status
Simulation time 24650141 ps
CPU time 0.85 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 206004 kb
Host smart-2dd58b37-c03c-4f16-bc2c-aa9b9534e29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034857756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4034857756
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4127062967
Short name T857
Test name
Test status
Simulation time 46898384 ps
CPU time 0.84 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 205996 kb
Host smart-0a2b6662-016b-462f-ba39-7df6f14bf9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127062967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4127062967
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.571900327
Short name T912
Test name
Test status
Simulation time 13549333 ps
CPU time 0.77 seconds
Started May 28 01:20:25 PM PDT 24
Finished May 28 01:20:30 PM PDT 24
Peak memory 205976 kb
Host smart-823cb1d0-77f5-4398-a700-3ddb65570198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571900327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.571900327
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4049654376
Short name T971
Test name
Test status
Simulation time 26729681 ps
CPU time 0.83 seconds
Started May 28 01:20:26 PM PDT 24
Finished May 28 01:20:31 PM PDT 24
Peak memory 206088 kb
Host smart-b2b0cb31-feae-4980-a75c-a1e945cab4c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049654376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4049654376
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.234408873
Short name T887
Test name
Test status
Simulation time 21095036 ps
CPU time 0.8 seconds
Started May 28 01:20:24 PM PDT 24
Finished May 28 01:20:29 PM PDT 24
Peak memory 205992 kb
Host smart-0ffb235a-d260-4bd0-a756-99de41bdee99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234408873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.234408873
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1969680793
Short name T954
Test name
Test status
Simulation time 101635442 ps
CPU time 1.41 seconds
Started May 28 01:19:39 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 214488 kb
Host smart-1a7b0cae-ac8a-4140-9428-30b40f0e7556
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969680793 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1969680793
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3462964945
Short name T226
Test name
Test status
Simulation time 15053839 ps
CPU time 0.88 seconds
Started May 28 01:19:37 PM PDT 24
Finished May 28 01:19:39 PM PDT 24
Peak memory 206144 kb
Host smart-4213cd57-3e5c-4666-84bb-a02ad33f5f37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462964945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3462964945
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3547111038
Short name T958
Test name
Test status
Simulation time 10928566 ps
CPU time 0.84 seconds
Started May 28 01:19:39 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 205908 kb
Host smart-df707ffb-7295-41ab-b2a9-576c57d19d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547111038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3547111038
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.627859391
Short name T952
Test name
Test status
Simulation time 72746328 ps
CPU time 1.04 seconds
Started May 28 01:19:40 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 206156 kb
Host smart-7a3bf0a1-c665-44ea-b008-0534fe3c37b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627859391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.627859391
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4292600972
Short name T914
Test name
Test status
Simulation time 213790228 ps
CPU time 2.35 seconds
Started May 28 01:19:48 PM PDT 24
Finished May 28 01:19:51 PM PDT 24
Peak memory 213940 kb
Host smart-a922220c-07b9-470c-afcb-d30f85c2e355
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292600972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4292600972
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3398464537
Short name T949
Test name
Test status
Simulation time 76585289 ps
CPU time 2.23 seconds
Started May 28 01:19:48 PM PDT 24
Finished May 28 01:19:51 PM PDT 24
Peak memory 206268 kb
Host smart-b5e8bf16-f40d-416b-a2ec-c84a6b6c545e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398464537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3398464537
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2267261459
Short name T905
Test name
Test status
Simulation time 30412781 ps
CPU time 0.99 seconds
Started May 28 01:19:37 PM PDT 24
Finished May 28 01:19:39 PM PDT 24
Peak memory 206188 kb
Host smart-23d7d212-dd56-41af-8021-253831799648
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267261459 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2267261459
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1048995627
Short name T221
Test name
Test status
Simulation time 11471974 ps
CPU time 0.86 seconds
Started May 28 01:19:48 PM PDT 24
Finished May 28 01:19:50 PM PDT 24
Peak memory 206200 kb
Host smart-f09fc401-1148-4876-bf5d-de820c95db9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048995627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1048995627
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1529093739
Short name T875
Test name
Test status
Simulation time 41893646 ps
CPU time 0.79 seconds
Started May 28 01:19:46 PM PDT 24
Finished May 28 01:19:49 PM PDT 24
Peak memory 205976 kb
Host smart-ba0b0256-61d3-4a1d-8d83-6cbc141ee582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529093739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1529093739
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2324107555
Short name T919
Test name
Test status
Simulation time 131953290 ps
CPU time 1.35 seconds
Started May 28 01:19:48 PM PDT 24
Finished May 28 01:19:50 PM PDT 24
Peak memory 205892 kb
Host smart-4192999d-3662-448f-a171-f9a4b55a1e7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324107555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2324107555
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3127961412
Short name T885
Test name
Test status
Simulation time 38050872 ps
CPU time 1.7 seconds
Started May 28 01:19:40 PM PDT 24
Finished May 28 01:19:43 PM PDT 24
Peak memory 214304 kb
Host smart-ed2791c9-672e-4ef1-968c-666f5d9880a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127961412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3127961412
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3720241966
Short name T951
Test name
Test status
Simulation time 97971472 ps
CPU time 2.18 seconds
Started May 28 01:19:46 PM PDT 24
Finished May 28 01:19:50 PM PDT 24
Peak memory 214460 kb
Host smart-a44dc5bf-2680-4dff-beb1-e0ba5e2dd946
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720241966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3720241966
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2317747366
Short name T877
Test name
Test status
Simulation time 26772031 ps
CPU time 1.31 seconds
Started May 28 01:19:53 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 214380 kb
Host smart-2dd73740-f0c7-4470-bb92-7fae05d4edfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317747366 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2317747366
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3804351052
Short name T220
Test name
Test status
Simulation time 13126213 ps
CPU time 0.9 seconds
Started May 28 01:19:40 PM PDT 24
Finished May 28 01:19:43 PM PDT 24
Peak memory 206216 kb
Host smart-ce034642-078a-4709-981c-cc1d3d4b0888
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804351052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3804351052
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.496722083
Short name T860
Test name
Test status
Simulation time 141938942 ps
CPU time 0.94 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 206068 kb
Host smart-79cec0b8-de85-47ce-a7ec-1f0c20e0be9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496722083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.496722083
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3281234525
Short name T909
Test name
Test status
Simulation time 120475839 ps
CPU time 1.32 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:41 PM PDT 24
Peak memory 206312 kb
Host smart-750f35f4-2216-4782-891b-1b87f926004d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281234525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3281234525
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1728465057
Short name T903
Test name
Test status
Simulation time 1374252057 ps
CPU time 3.69 seconds
Started May 28 01:19:38 PM PDT 24
Finished May 28 01:19:43 PM PDT 24
Peak memory 214340 kb
Host smart-1a88f57d-0c87-431b-8da8-83e9c850edf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728465057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1728465057
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2189080309
Short name T955
Test name
Test status
Simulation time 203349398 ps
CPU time 2.1 seconds
Started May 28 01:19:39 PM PDT 24
Finished May 28 01:19:42 PM PDT 24
Peak memory 206220 kb
Host smart-6ddf8acb-5441-4798-bad3-5588b7aebb3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189080309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2189080309
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2198508811
Short name T888
Test name
Test status
Simulation time 28757407 ps
CPU time 1.01 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 206436 kb
Host smart-b2c81948-4f9b-43bb-997a-ba976d0f17de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198508811 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2198508811
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1877793846
Short name T874
Test name
Test status
Simulation time 20160948 ps
CPU time 0.92 seconds
Started May 28 01:19:54 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 206080 kb
Host smart-1123b1bd-b7dd-485f-80d5-c38aafa60603
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877793846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1877793846
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4022299464
Short name T943
Test name
Test status
Simulation time 31805248 ps
CPU time 1.31 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:55 PM PDT 24
Peak memory 206176 kb
Host smart-7b33e232-4e34-4a0f-b418-433401e50057
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022299464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4022299464
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2351884100
Short name T878
Test name
Test status
Simulation time 36519998 ps
CPU time 1.82 seconds
Started May 28 01:19:51 PM PDT 24
Finished May 28 01:19:54 PM PDT 24
Peak memory 214416 kb
Host smart-9faa347f-5035-43f7-9e5a-a80dd4b6d168
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351884100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2351884100
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2432410856
Short name T937
Test name
Test status
Simulation time 146816604 ps
CPU time 3.43 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:56 PM PDT 24
Peak memory 206328 kb
Host smart-84050ce3-4f3a-4990-bd79-797217fa7ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432410856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2432410856
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3154041455
Short name T880
Test name
Test status
Simulation time 26798281 ps
CPU time 1.5 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:55 PM PDT 24
Peak memory 214464 kb
Host smart-0ca5bb79-4180-4f1e-8999-7651bb843fb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154041455 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3154041455
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3677584959
Short name T966
Test name
Test status
Simulation time 16328766 ps
CPU time 0.94 seconds
Started May 28 01:19:51 PM PDT 24
Finished May 28 01:19:53 PM PDT 24
Peak memory 206136 kb
Host smart-ac4c2abe-4e7f-4242-bf8a-2b0206810f27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677584959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3677584959
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3474168445
Short name T932
Test name
Test status
Simulation time 14333785 ps
CPU time 0.9 seconds
Started May 28 01:19:57 PM PDT 24
Finished May 28 01:19:59 PM PDT 24
Peak memory 206060 kb
Host smart-77b91a15-b0f1-44cb-ad76-e976c993b88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474168445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3474168445
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.534626359
Short name T235
Test name
Test status
Simulation time 36950209 ps
CPU time 1.09 seconds
Started May 28 01:19:52 PM PDT 24
Finished May 28 01:19:54 PM PDT 24
Peak memory 206232 kb
Host smart-332322f3-10a6-4fe1-87b7-c42957e03e3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534626359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.534626359
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2852607166
Short name T923
Test name
Test status
Simulation time 57470331 ps
CPU time 2.25 seconds
Started May 28 01:19:53 PM PDT 24
Finished May 28 01:19:57 PM PDT 24
Peak memory 217948 kb
Host smart-1182b93e-7d9f-4722-a5b8-c45eee7309d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852607166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2852607166
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.447930471
Short name T965
Test name
Test status
Simulation time 293486831 ps
CPU time 2.19 seconds
Started May 28 01:19:57 PM PDT 24
Finished May 28 01:20:00 PM PDT 24
Peak memory 206240 kb
Host smart-83e4f270-fdff-4206-aabd-6830ecc72536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447930471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.447930471
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2378187234
Short name T664
Test name
Test status
Simulation time 15958813 ps
CPU time 0.92 seconds
Started May 28 02:09:55 PM PDT 24
Finished May 28 02:09:59 PM PDT 24
Peak memory 206324 kb
Host smart-b76c8110-c70f-4b3a-816a-09a6710b3ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378187234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2378187234
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1701135614
Short name T413
Test name
Test status
Simulation time 41154832 ps
CPU time 0.92 seconds
Started May 28 02:09:56 PM PDT 24
Finished May 28 02:09:59 PM PDT 24
Peak memory 215184 kb
Host smart-896c5367-edeb-4a76-9bea-a781d0295856
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701135614 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1701135614
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.3753748521
Short name T498
Test name
Test status
Simulation time 18292959 ps
CPU time 1.07 seconds
Started May 28 02:09:55 PM PDT 24
Finished May 28 02:09:58 PM PDT 24
Peak memory 218000 kb
Host smart-cf5fd5c8-e535-4310-ab0c-6a09588ce5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753748521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3753748521
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.494702545
Short name T575
Test name
Test status
Simulation time 58467881 ps
CPU time 1.55 seconds
Started May 28 02:10:01 PM PDT 24
Finished May 28 02:10:04 PM PDT 24
Peak memory 219260 kb
Host smart-7098dd15-60d2-4ae9-b682-bd40431207fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494702545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.494702545
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2316483818
Short name T17
Test name
Test status
Simulation time 1105542482 ps
CPU time 8.5 seconds
Started May 28 02:09:58 PM PDT 24
Finished May 28 02:10:08 PM PDT 24
Peak memory 237036 kb
Host smart-2f7904e1-3372-4539-81d9-2dfe75f4c227
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316483818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2316483818
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.698486002
Short name T749
Test name
Test status
Simulation time 176525696 ps
CPU time 0.93 seconds
Started May 28 02:09:54 PM PDT 24
Finished May 28 02:09:57 PM PDT 24
Peak memory 214892 kb
Host smart-5715e3e8-1ffe-4f7b-b908-f1bfa5f959a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698486002 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.698486002
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1333682708
Short name T310
Test name
Test status
Simulation time 255322023 ps
CPU time 4.53 seconds
Started May 28 02:10:01 PM PDT 24
Finished May 28 02:10:06 PM PDT 24
Peak memory 219360 kb
Host smart-0008fecb-90c3-430b-8f1c-208c05494220
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333682708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1333682708
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.2885931925
Short name T574
Test name
Test status
Simulation time 48732645 ps
CPU time 1.23 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 215372 kb
Host smart-ec4a5d4c-9e2f-4353-b185-5e6fb6388751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885931925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2885931925
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.192227322
Short name T743
Test name
Test status
Simulation time 13913222 ps
CPU time 0.82 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 206568 kb
Host smart-2bf14db4-83bb-47b1-8592-4222baebcd28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192227322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.192227322
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.4174688367
Short name T790
Test name
Test status
Simulation time 11340761 ps
CPU time 0.91 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 215856 kb
Host smart-93b89a18-5bca-4e8a-bbe3-d81f6cffa06d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174688367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.4174688367
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.203983647
Short name T467
Test name
Test status
Simulation time 72932775 ps
CPU time 1.08 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 217956 kb
Host smart-cbefa155-61eb-4f0f-a256-ab125d11d726
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203983647 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.203983647
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.4091413728
Short name T542
Test name
Test status
Simulation time 44207656 ps
CPU time 1.13 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 219384 kb
Host smart-2cf05302-6000-4137-b347-facd816f55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091413728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.4091413728
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2956209527
Short name T448
Test name
Test status
Simulation time 88349681 ps
CPU time 1.18 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 219336 kb
Host smart-4b4f004d-fb7e-42ce-a24f-a8d4ad2868e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956209527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2956209527
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1924534743
Short name T770
Test name
Test status
Simulation time 19782398 ps
CPU time 1.12 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 215380 kb
Host smart-47ce5241-009f-431e-b82a-3257324215ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924534743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1924534743
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.672075091
Short name T18
Test name
Test status
Simulation time 320318978 ps
CPU time 5.25 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:10:16 PM PDT 24
Peak memory 234824 kb
Host smart-1c5d759e-9a3d-4056-912b-6f03925ca059
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672075091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.672075091
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2387994866
Short name T514
Test name
Test status
Simulation time 44749406 ps
CPU time 0.98 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:10:12 PM PDT 24
Peak memory 215340 kb
Host smart-35300c2a-77a4-4403-a1b7-46687d59ba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387994866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2387994866
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3197699771
Short name T690
Test name
Test status
Simulation time 2238089982 ps
CPU time 4.15 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:10:15 PM PDT 24
Peak memory 216836 kb
Host smart-3a1e00eb-75bf-4329-9526-415ea7278980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197699771 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3197699771
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3045214062
Short name T709
Test name
Test status
Simulation time 133175751466 ps
CPU time 879.99 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:24:52 PM PDT 24
Peak memory 223448 kb
Host smart-c5195d1a-899e-4d6f-90aa-1dd1f525c7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045214062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3045214062
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable.535662825
Short name T148
Test name
Test status
Simulation time 35949168 ps
CPU time 0.89 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 215908 kb
Host smart-63caba7b-9406-4720-ac1f-66419af6ff2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535662825 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.535662825
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.643029627
Short name T488
Test name
Test status
Simulation time 90211847 ps
CPU time 1.16 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:36 PM PDT 24
Peak memory 216760 kb
Host smart-eec0aeff-87a9-4fb5-975d-ef5078b1bf28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643029627 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.643029627
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1108009192
Short name T381
Test name
Test status
Simulation time 26123758 ps
CPU time 1.04 seconds
Started May 28 02:10:35 PM PDT 24
Finished May 28 02:10:40 PM PDT 24
Peak memory 219328 kb
Host smart-c912f623-aca7-45ad-b167-92b82fbda0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108009192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1108009192
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3236440968
Short name T789
Test name
Test status
Simulation time 64490541 ps
CPU time 1.5 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 216760 kb
Host smart-7da8d5fd-43c8-4abd-bcd4-094a7eefbc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236440968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3236440968
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1957879320
Short name T640
Test name
Test status
Simulation time 22599866 ps
CPU time 1.27 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:36 PM PDT 24
Peak memory 223584 kb
Host smart-72255e1a-4969-4efa-8f43-f2f267b7a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957879320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1957879320
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.286437251
Short name T384
Test name
Test status
Simulation time 20577612 ps
CPU time 0.96 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 215028 kb
Host smart-006258c4-c8ce-4f86-8860-da840116195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286437251 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.286437251
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3829935090
Short name T502
Test name
Test status
Simulation time 386905543 ps
CPU time 4.51 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:41 PM PDT 24
Peak memory 216648 kb
Host smart-e62a18ab-7257-44b0-900c-60884ba9b380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829935090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3829935090
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3427358147
Short name T461
Test name
Test status
Simulation time 20252806085 ps
CPU time 113.79 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:12:31 PM PDT 24
Peak memory 218408 kb
Host smart-034d0714-171f-4ced-a48d-0035c54b8f35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427358147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3427358147
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.1778369410
Short name T382
Test name
Test status
Simulation time 52961675 ps
CPU time 1.35 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 217988 kb
Host smart-e50e812a-fe22-4287-b7f9-2634ea718bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778369410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1778369410
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3457282595
Short name T307
Test name
Test status
Simulation time 143096052 ps
CPU time 1.32 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 219548 kb
Host smart-88d74a58-2f7a-413b-b7fc-4edaabf20cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457282595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3457282595
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.990420407
Short name T598
Test name
Test status
Simulation time 87202960 ps
CPU time 1.18 seconds
Started May 28 02:12:35 PM PDT 24
Finished May 28 02:12:37 PM PDT 24
Peak memory 216800 kb
Host smart-dd4e6084-41cb-47d5-b171-a7a93abb9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990420407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.990420407
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2393268914
Short name T795
Test name
Test status
Simulation time 53681937 ps
CPU time 1.43 seconds
Started May 28 02:12:35 PM PDT 24
Finished May 28 02:12:39 PM PDT 24
Peak memory 216944 kb
Host smart-7fbf2463-462b-4045-94e0-1d3dfc7e0b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393268914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2393268914
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1749514367
Short name T592
Test name
Test status
Simulation time 141064768 ps
CPU time 1.37 seconds
Started May 28 02:12:35 PM PDT 24
Finished May 28 02:12:37 PM PDT 24
Peak memory 216900 kb
Host smart-1f923ded-9fec-4c3d-8eb6-575db40a4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749514367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1749514367
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.4260121131
Short name T836
Test name
Test status
Simulation time 43340735 ps
CPU time 1.83 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 218032 kb
Host smart-47aedd29-ec6a-4d79-b032-eb79706231f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260121131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4260121131
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3893445988
Short name T762
Test name
Test status
Simulation time 56041225 ps
CPU time 1.37 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:41 PM PDT 24
Peak memory 217936 kb
Host smart-320f49b9-c158-4ca6-915f-ec7b8bf33911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893445988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3893445988
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.224953365
Short name T666
Test name
Test status
Simulation time 78232355 ps
CPU time 1.34 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:39 PM PDT 24
Peak memory 218488 kb
Host smart-5914acd7-86e6-401b-ab4e-4cae9b4eb5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224953365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.224953365
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2355141454
Short name T594
Test name
Test status
Simulation time 157712504 ps
CPU time 1.23 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 215456 kb
Host smart-6f8e9d45-f81b-438c-a686-58bfb34b0e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355141454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2355141454
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1557626564
Short name T473
Test name
Test status
Simulation time 37059090 ps
CPU time 1 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:37 PM PDT 24
Peak memory 206336 kb
Host smart-128da119-e0d4-4940-8d50-b3f70d010974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557626564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1557626564
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.621895440
Short name T842
Test name
Test status
Simulation time 34030720 ps
CPU time 0.87 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:36 PM PDT 24
Peak memory 215860 kb
Host smart-eee7256b-48dd-46f7-8073-e84a5de83d34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621895440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.621895440
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3077766283
Short name T620
Test name
Test status
Simulation time 104363152 ps
CPU time 1.06 seconds
Started May 28 02:10:30 PM PDT 24
Finished May 28 02:10:32 PM PDT 24
Peak memory 218136 kb
Host smart-0ffbc85f-ea21-4671-a95b-afbadfa20b19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077766283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3077766283
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3401391584
Short name T187
Test name
Test status
Simulation time 84296471 ps
CPU time 0.93 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:36 PM PDT 24
Peak memory 228796 kb
Host smart-7a917872-a7d7-40d9-9399-eb32d5c0432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401391584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3401391584
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.3246441614
Short name T274
Test name
Test status
Simulation time 62511540 ps
CPU time 1.51 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 216864 kb
Host smart-66d0264c-01b4-4b7a-be6e-14ff0c09f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246441614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3246441614
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2961638065
Short name T728
Test name
Test status
Simulation time 21522529 ps
CPU time 1.16 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:35 PM PDT 24
Peak memory 215340 kb
Host smart-f9249aeb-1687-44f3-ae59-488899ada8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961638065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2961638065
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.451443995
Short name T325
Test name
Test status
Simulation time 65482169 ps
CPU time 0.94 seconds
Started May 28 02:10:31 PM PDT 24
Finished May 28 02:10:33 PM PDT 24
Peak memory 215012 kb
Host smart-c0420895-7b7a-4353-84cd-a162c9d0e07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451443995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.451443995
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.708466662
Short name T596
Test name
Test status
Simulation time 300934774 ps
CPU time 3.38 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 216500 kb
Host smart-0ed5459b-99ad-4693-a071-b5ecd63f350c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708466662 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.708466662
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.271154159
Short name T669
Test name
Test status
Simulation time 61327301 ps
CPU time 1.07 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:41 PM PDT 24
Peak memory 216696 kb
Host smart-6501045c-30b1-4dd4-8a64-abf31172974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271154159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.271154159
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3702670330
Short name T354
Test name
Test status
Simulation time 50609427 ps
CPU time 1.24 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 215032 kb
Host smart-e6a002b9-4e40-4c64-a3e6-50e06c8197c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702670330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3702670330
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2426093490
Short name T538
Test name
Test status
Simulation time 63020447 ps
CPU time 1.13 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 218472 kb
Host smart-4b14c187-6c81-4503-8941-0082c8808533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426093490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2426093490
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1399149910
Short name T89
Test name
Test status
Simulation time 44816708 ps
CPU time 1.55 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 217776 kb
Host smart-bd77f8cf-b936-4893-901c-d14ea2210ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399149910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1399149910
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4225788703
Short name T562
Test name
Test status
Simulation time 158309825 ps
CPU time 2.42 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 218000 kb
Host smart-ae539b5b-f05d-4c58-a4a9-74a97bb91eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225788703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4225788703
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.326652286
Short name T246
Test name
Test status
Simulation time 56185245 ps
CPU time 1.88 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 219360 kb
Host smart-02272a0e-3ccf-4252-970e-baf87bd83669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326652286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.326652286
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4083624915
Short name T493
Test name
Test status
Simulation time 42821895 ps
CPU time 1.21 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 218060 kb
Host smart-50142a6b-e821-4145-af8d-ce03598e2458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083624915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4083624915
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3192782041
Short name T372
Test name
Test status
Simulation time 63842890 ps
CPU time 1.41 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 218316 kb
Host smart-ccc479ab-f48b-488e-be23-2a5a5aef1f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192782041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3192782041
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3327534080
Short name T843
Test name
Test status
Simulation time 39493691 ps
CPU time 1.34 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:39 PM PDT 24
Peak memory 217824 kb
Host smart-bc0ba815-9ea1-4b00-bab3-46b2aea8e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327534080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3327534080
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3783486757
Short name T647
Test name
Test status
Simulation time 398182699 ps
CPU time 1.12 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:39 PM PDT 24
Peak memory 216652 kb
Host smart-cd067673-9c9a-4301-9368-0c2dbe467193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783486757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3783486757
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2324334545
Short name T133
Test name
Test status
Simulation time 70984379 ps
CPU time 1.14 seconds
Started May 28 02:10:30 PM PDT 24
Finished May 28 02:10:32 PM PDT 24
Peak memory 215408 kb
Host smart-f786519e-9ce8-4a54-ae72-ca5738aefa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324334545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2324334545
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2077488000
Short name T552
Test name
Test status
Simulation time 31259138 ps
CPU time 0.93 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 214960 kb
Host smart-373193f4-57d2-476d-ac74-4ab08dff4b1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077488000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2077488000
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2666786238
Short name T604
Test name
Test status
Simulation time 23577193 ps
CPU time 1.04 seconds
Started May 28 02:10:47 PM PDT 24
Finished May 28 02:10:50 PM PDT 24
Peak memory 217808 kb
Host smart-ab4caa7e-6c68-4c33-be0b-e2c732d2de2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666786238 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2666786238
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3242679120
Short name T350
Test name
Test status
Simulation time 33996781 ps
CPU time 1.07 seconds
Started May 28 02:10:42 PM PDT 24
Finished May 28 02:10:44 PM PDT 24
Peak memory 218208 kb
Host smart-e33319af-7a62-4443-bd27-1c5e21989787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242679120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3242679120
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.3468937534
Short name T470
Test name
Test status
Simulation time 53566760 ps
CPU time 1.43 seconds
Started May 28 02:10:42 PM PDT 24
Finished May 28 02:10:44 PM PDT 24
Peak memory 216888 kb
Host smart-465bb3cf-c8a1-43ef-83be-63e24edf82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468937534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3468937534
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3591868379
Short name T507
Test name
Test status
Simulation time 30809470 ps
CPU time 1.04 seconds
Started May 28 02:10:41 PM PDT 24
Finished May 28 02:10:43 PM PDT 24
Peak memory 215124 kb
Host smart-f7b2c63b-4dc9-48f6-9d01-5881ca7537c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591868379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3591868379
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1031319249
Short name T764
Test name
Test status
Simulation time 38995005 ps
CPU time 0.91 seconds
Started May 28 02:10:42 PM PDT 24
Finished May 28 02:10:43 PM PDT 24
Peak memory 215028 kb
Host smart-a5c8d746-2053-40b0-9004-5c80e7545b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031319249 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1031319249
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1174521601
Short name T589
Test name
Test status
Simulation time 528526546 ps
CPU time 3.7 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 216584 kb
Host smart-aea6a92f-7c25-4c2f-938d-876e9b800e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174521601 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1174521601
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1921942900
Short name T447
Test name
Test status
Simulation time 318363539601 ps
CPU time 504.47 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:19:02 PM PDT 24
Peak memory 218476 kb
Host smart-23a7f538-19bc-4208-905d-f518c784ffa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921942900 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1921942900
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_genbits.320850208
Short name T837
Test name
Test status
Simulation time 56549110 ps
CPU time 1.43 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 217876 kb
Host smart-1c6fcb2a-1b60-4e35-a447-cd30593263d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320850208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.320850208
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1105118161
Short name T653
Test name
Test status
Simulation time 64930627 ps
CPU time 2.25 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 218048 kb
Host smart-2672e800-6287-402a-970e-a38ef9c64c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105118161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1105118161
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3149548501
Short name T64
Test name
Test status
Simulation time 38795588 ps
CPU time 1.18 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 217944 kb
Host smart-f5f55091-7587-4c50-9b7d-4f28111a35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149548501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3149548501
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2492817251
Short name T362
Test name
Test status
Simulation time 33851155 ps
CPU time 1.39 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 216688 kb
Host smart-44ced941-6e93-4188-8eee-9955e37da854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492817251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2492817251
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2463981763
Short name T415
Test name
Test status
Simulation time 78640898 ps
CPU time 1.17 seconds
Started May 28 02:12:35 PM PDT 24
Finished May 28 02:12:37 PM PDT 24
Peak memory 218012 kb
Host smart-7ebf558e-d907-4811-8917-3594266c2806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463981763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2463981763
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.526387391
Short name T77
Test name
Test status
Simulation time 60323813 ps
CPU time 1.38 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 217960 kb
Host smart-c1277cc7-e27a-455f-b0aa-29aee7783f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526387391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.526387391
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1270845974
Short name T386
Test name
Test status
Simulation time 51655385 ps
CPU time 2.03 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:47 PM PDT 24
Peak memory 218084 kb
Host smart-803b9935-4a61-4f77-a5f8-07c0d7189196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270845974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1270845974
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3926807640
Short name T67
Test name
Test status
Simulation time 52761727 ps
CPU time 1.63 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 217876 kb
Host smart-e1519436-b52b-452f-92c7-210cb243696b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926807640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3926807640
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.4110027861
Short name T456
Test name
Test status
Simulation time 14585062 ps
CPU time 0.98 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 206272 kb
Host smart-44b5cbe8-3155-41d8-9711-a5e83a7ddaf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110027861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4110027861
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.848082127
Short name T393
Test name
Test status
Simulation time 65191231 ps
CPU time 1.22 seconds
Started May 28 02:10:47 PM PDT 24
Finished May 28 02:10:50 PM PDT 24
Peak memory 216692 kb
Host smart-416a435e-6f80-4421-929d-2d747821c61e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848082127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.848082127
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3911436983
Short name T803
Test name
Test status
Simulation time 73189745 ps
CPU time 1.12 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 219432 kb
Host smart-dc79e5d0-4e9a-44b6-91a1-04f5a5d58ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911436983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3911436983
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.250180894
Short name T353
Test name
Test status
Simulation time 67343552 ps
CPU time 1.38 seconds
Started May 28 02:10:45 PM PDT 24
Finished May 28 02:10:47 PM PDT 24
Peak memory 217920 kb
Host smart-8b9fc92d-72dc-44b0-bc80-154d30e578f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250180894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.250180894
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.2986303046
Short name T425
Test name
Test status
Simulation time 23749691 ps
CPU time 0.99 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:48 PM PDT 24
Peak memory 215028 kb
Host smart-16ac8b66-a1f9-4dc6-b497-2ad94c330ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986303046 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2986303046
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2260857769
Short name T551
Test name
Test status
Simulation time 470172288 ps
CPU time 4 seconds
Started May 28 02:10:47 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 216616 kb
Host smart-f6e5f128-eff9-4b6a-9b4d-db02c85a8106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260857769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2260857769
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2861712816
Short name T194
Test name
Test status
Simulation time 170531234409 ps
CPU time 2177.15 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 230224 kb
Host smart-b489b511-21cd-4bb8-abeb-1f25e898dbcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861712816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2861712816
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1765108189
Short name T455
Test name
Test status
Simulation time 46785370 ps
CPU time 1.12 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 218124 kb
Host smart-66e0646a-442b-4700-ac49-ba7c32749c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765108189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1765108189
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3118961086
Short name T300
Test name
Test status
Simulation time 33729415 ps
CPU time 1.47 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 219564 kb
Host smart-cd94de45-12d6-4fdd-a377-c7f43443879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118961086 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3118961086
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.253806138
Short name T784
Test name
Test status
Simulation time 136280002 ps
CPU time 1.79 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 216916 kb
Host smart-a7331cf8-d890-48f0-8910-4d8543f65cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253806138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.253806138
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3151252654
Short name T494
Test name
Test status
Simulation time 127438512 ps
CPU time 1.82 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 219344 kb
Host smart-bc3a1b4d-d2f8-44c9-ac85-f3c34ca6af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151252654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3151252654
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3258174912
Short name T546
Test name
Test status
Simulation time 68866529 ps
CPU time 1.66 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 219460 kb
Host smart-9f33d9fe-79c6-487c-8a2d-9cc2b575223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258174912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3258174912
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.129298373
Short name T766
Test name
Test status
Simulation time 54750042 ps
CPU time 1.47 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 218020 kb
Host smart-bfdb38cc-d455-4747-82b0-b135e74d0a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129298373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.129298373
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2844855272
Short name T677
Test name
Test status
Simulation time 47041033 ps
CPU time 1.59 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 218132 kb
Host smart-c385364d-d723-4370-83ca-e8a4c9bff2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844855272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2844855272
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2982771004
Short name T291
Test name
Test status
Simulation time 38328642 ps
CPU time 1.03 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 216612 kb
Host smart-67d5f968-7070-4fb5-b755-8bd7ee8546f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982771004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2982771004
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.771423289
Short name T633
Test name
Test status
Simulation time 47308226 ps
CPU time 1.54 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 218088 kb
Host smart-2402ffc5-20c1-4c1d-8112-f4ace3b234cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771423289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.771423289
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.412122394
Short name T593
Test name
Test status
Simulation time 136600146 ps
CPU time 2.44 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 218008 kb
Host smart-4c68c5cd-77d3-4d65-b286-83b23e0ecdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412122394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.412122394
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1853660139
Short name T705
Test name
Test status
Simulation time 79719282 ps
CPU time 1.21 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 215420 kb
Host smart-f87aff12-1818-451f-a736-04d598df6554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853660139 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1853660139
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3925748809
Short name T584
Test name
Test status
Simulation time 51528230 ps
CPU time 0.9 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 206284 kb
Host smart-9d31b253-f0ca-4ebf-bc34-b51c4c82641a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925748809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3925748809
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.2348978807
Short name T699
Test name
Test status
Simulation time 115565418 ps
CPU time 0.81 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 215124 kb
Host smart-7607b9c7-f9d0-4f84-8577-4214e8dd6c52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348978807 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2348978807
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2716043227
Short name T528
Test name
Test status
Simulation time 65179075 ps
CPU time 1.2 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:54 PM PDT 24
Peak memory 216612 kb
Host smart-d6c33ef7-6969-4e60-a898-e130d23119b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716043227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2716043227
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4183828624
Short name T127
Test name
Test status
Simulation time 34781238 ps
CPU time 1.02 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 223356 kb
Host smart-a7fab30c-1cb9-40f9-ac22-e42783706d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183828624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4183828624
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.455825702
Short name T834
Test name
Test status
Simulation time 48189132 ps
CPU time 1.59 seconds
Started May 28 02:10:47 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 217964 kb
Host smart-a5dc838a-3290-4a60-8747-9359471433a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455825702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.455825702
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2542060091
Short name T667
Test name
Test status
Simulation time 25105079 ps
CPU time 1 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 215092 kb
Host smart-bb9e2427-bbf1-40c4-85fc-f28da9e9ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542060091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2542060091
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1102244143
Short name T501
Test name
Test status
Simulation time 81341933 ps
CPU time 0.91 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 214976 kb
Host smart-2adeb1cd-33af-48ee-a236-fb0da3a21d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102244143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1102244143
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.339506994
Short name T631
Test name
Test status
Simulation time 513248350 ps
CPU time 5.23 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:57 PM PDT 24
Peak memory 216628 kb
Host smart-aa72d539-8701-4bdc-9adb-f50a5d5cb518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339506994 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.339506994
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3367351157
Short name T813
Test name
Test status
Simulation time 48651580930 ps
CPU time 614.8 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:21:04 PM PDT 24
Peak memory 218780 kb
Host smart-6f10f9aa-152b-43bf-98e2-0cfd552d3541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367351157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3367351157
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.1662700196
Short name T383
Test name
Test status
Simulation time 102823653 ps
CPU time 1.27 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 216900 kb
Host smart-b6a2f1a4-e1f3-4c89-84bf-9bbd6e054209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662700196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1662700196
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3384908258
Short name T831
Test name
Test status
Simulation time 77923460 ps
CPU time 1.22 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 219436 kb
Host smart-2ca6e26b-8a8c-48e1-ab6d-1863dec299e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384908258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3384908258
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2057810768
Short name T397
Test name
Test status
Simulation time 76108566 ps
CPU time 1.26 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 216912 kb
Host smart-ea412dee-36b4-4efc-9971-7bea3afe9f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057810768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2057810768
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1259996630
Short name T821
Test name
Test status
Simulation time 20308304 ps
CPU time 1.17 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 216648 kb
Host smart-e631daef-cf47-480c-af45-23cc9c982caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259996630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1259996630
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3739112651
Short name T614
Test name
Test status
Simulation time 60752435 ps
CPU time 1.16 seconds
Started May 28 02:12:39 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 216800 kb
Host smart-31e8e6d6-9835-4856-8d9b-838e98f07c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739112651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3739112651
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.232366545
Short name T522
Test name
Test status
Simulation time 88577610 ps
CPU time 2.27 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:47 PM PDT 24
Peak memory 216920 kb
Host smart-7a34b4e2-a607-49ec-a704-9d7d859a338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232366545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.232366545
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2082735181
Short name T814
Test name
Test status
Simulation time 52134254 ps
CPU time 1.47 seconds
Started May 28 02:12:40 PM PDT 24
Finished May 28 02:12:45 PM PDT 24
Peak memory 217984 kb
Host smart-e9d61ca4-97ca-4eec-a279-52aff7b1b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082735181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2082735181
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1858102127
Short name T394
Test name
Test status
Simulation time 76941456 ps
CPU time 1.18 seconds
Started May 28 02:12:41 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 216828 kb
Host smart-a2ff3b4b-dfde-42c1-b337-79334becf391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858102127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1858102127
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.4110588319
Short name T692
Test name
Test status
Simulation time 283134512 ps
CPU time 1.57 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 215300 kb
Host smart-51533d1b-471f-411e-8e38-df987fd3c75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110588319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4110588319
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.4097279919
Short name T439
Test name
Test status
Simulation time 32548141 ps
CPU time 0.92 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 214504 kb
Host smart-b186d08f-3621-4437-a6ef-3408fd0c4465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097279919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4097279919
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2161009689
Short name T517
Test name
Test status
Simulation time 34485478 ps
CPU time 1.19 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 217920 kb
Host smart-47997161-be77-4de1-b224-2388adc2856f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161009689 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2161009689
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.82840742
Short name T395
Test name
Test status
Simulation time 27786907 ps
CPU time 0.88 seconds
Started May 28 02:10:54 PM PDT 24
Finished May 28 02:10:57 PM PDT 24
Peak memory 217988 kb
Host smart-0418ace5-9b3a-421c-96c6-30ae8997aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82840742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.82840742
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.893640607
Short name T500
Test name
Test status
Simulation time 34110374 ps
CPU time 1.4 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:54 PM PDT 24
Peak memory 216744 kb
Host smart-f113ee13-ce18-4fa6-a8e2-b68eae17e8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893640607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.893640607
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.940838743
Short name T484
Test name
Test status
Simulation time 20473532 ps
CPU time 1.16 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 223612 kb
Host smart-e93ed716-a763-43f6-8ec9-af2d585ffab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940838743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.940838743
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2039430111
Short name T480
Test name
Test status
Simulation time 122577489 ps
CPU time 0.99 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 214980 kb
Host smart-d9d805cd-556a-4619-b3ea-fd710ae7fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039430111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2039430111
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4116700064
Short name T662
Test name
Test status
Simulation time 376131779 ps
CPU time 2.37 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 216760 kb
Host smart-5d1b28a5-084b-4fb3-9a5d-20a9e558c8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116700064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4116700064
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1958976812
Short name T193
Test name
Test status
Simulation time 122507047098 ps
CPU time 709.72 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:22:40 PM PDT 24
Peak memory 219468 kb
Host smart-908975b2-c60a-4ee5-bbb0-d4f1678b510d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958976812 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1958976812
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.708158147
Short name T2
Test name
Test status
Simulation time 151711001 ps
CPU time 2.39 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 219068 kb
Host smart-fe4ab462-24af-466e-8771-9eae8de1a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708158147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.708158147
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.88478084
Short name T410
Test name
Test status
Simulation time 54850325 ps
CPU time 1.36 seconds
Started May 28 02:12:46 PM PDT 24
Finished May 28 02:12:48 PM PDT 24
Peak memory 217856 kb
Host smart-753cc4e4-0fd6-4b37-819b-9db37042e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88478084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.88478084
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3559176482
Short name T712
Test name
Test status
Simulation time 67333249 ps
CPU time 1.44 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 218420 kb
Host smart-92ad74a8-6865-46fe-9ec3-03e6728c4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559176482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3559176482
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.70323351
Short name T495
Test name
Test status
Simulation time 97560064 ps
CPU time 1.46 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:51 PM PDT 24
Peak memory 218160 kb
Host smart-f34f2f2b-0973-462a-9dc5-5fe2da023342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70323351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.70323351
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2610174974
Short name T537
Test name
Test status
Simulation time 70261064 ps
CPU time 1.31 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 218004 kb
Host smart-576b2e22-3ab2-4ea8-b48d-5a3ea90be2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610174974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2610174974
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3653643296
Short name T279
Test name
Test status
Simulation time 460775445 ps
CPU time 2.85 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 219288 kb
Host smart-c50a4a9b-5986-40a3-97d4-789e7872a019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653643296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3653643296
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2517418359
Short name T244
Test name
Test status
Simulation time 21489169 ps
CPU time 1.12 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 216892 kb
Host smart-994c7a10-b5a7-4819-ac8c-f04a6a2185db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517418359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2517418359
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2565376567
Short name T247
Test name
Test status
Simulation time 48360036 ps
CPU time 1.6 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 217804 kb
Host smart-c2185926-36f3-4d01-bebc-27015e695641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565376567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2565376567
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4162310182
Short name T516
Test name
Test status
Simulation time 23414739 ps
CPU time 1.22 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 215460 kb
Host smart-24f39840-9a15-40b0-99f7-38df870a0735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162310182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4162310182
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.719785607
Short name T351
Test name
Test status
Simulation time 37041803 ps
CPU time 0.82 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 206164 kb
Host smart-80038821-6abc-4847-a323-5f67e0d67221
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719785607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.719785607
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.832503763
Short name T711
Test name
Test status
Simulation time 17093886 ps
CPU time 0.91 seconds
Started May 28 02:10:50 PM PDT 24
Finished May 28 02:10:53 PM PDT 24
Peak memory 216164 kb
Host smart-db0e09af-522c-4d4a-b45a-b9c0b857bb41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832503763 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.832503763
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.81924801
Short name T178
Test name
Test status
Simulation time 71533159 ps
CPU time 1.26 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 219304 kb
Host smart-7bd7798b-a469-44ec-88fd-c4d72e2eec65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81924801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_dis
able_auto_req_mode.81924801
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1029455622
Short name T106
Test name
Test status
Simulation time 36518975 ps
CPU time 1.13 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 219272 kb
Host smart-d32cd309-028e-434f-9df2-ecd930ee312d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029455622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1029455622
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.826614837
Short name T722
Test name
Test status
Simulation time 47019754 ps
CPU time 1.63 seconds
Started May 28 02:10:53 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 217828 kb
Host smart-144a1d4c-daf6-4fe5-90d7-35387a058842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826614837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.826614837
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.769341912
Short name T674
Test name
Test status
Simulation time 33981982 ps
CPU time 0.86 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 215192 kb
Host smart-dc1e1110-8c7c-43db-b905-000cad9b2cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769341912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.769341912
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2715347921
Short name T799
Test name
Test status
Simulation time 46456143 ps
CPU time 0.94 seconds
Started May 28 02:10:54 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 214996 kb
Host smart-13750a4f-3493-4c0e-8fe7-7e5dbc6dc955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715347921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2715347921
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.351595980
Short name T786
Test name
Test status
Simulation time 262677669363 ps
CPU time 3570.54 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 03:10:25 PM PDT 24
Peak memory 233032 kb
Host smart-0fbf60c7-ab43-4599-b5dc-a2c51b1eec16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351595980 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.351595980
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.4274073657
Short name T442
Test name
Test status
Simulation time 29437313 ps
CPU time 1.27 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 219428 kb
Host smart-e4547dc5-54c7-4b88-baca-88c465f2992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274073657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4274073657
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3712218006
Short name T25
Test name
Test status
Simulation time 84508926 ps
CPU time 1.41 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 218200 kb
Host smart-4aa2d8b0-cd35-47fd-ad0a-da1c1828c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712218006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3712218006
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2241044847
Short name T576
Test name
Test status
Simulation time 34948366 ps
CPU time 1.36 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 216860 kb
Host smart-f8af5385-31db-487f-b76d-dfb966386056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241044847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2241044847
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2571730863
Short name T830
Test name
Test status
Simulation time 22673576 ps
CPU time 1.15 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:51 PM PDT 24
Peak memory 219028 kb
Host smart-41a24ed4-efba-4871-83cb-94fd702d430f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571730863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2571730863
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.742724071
Short name T671
Test name
Test status
Simulation time 54970710 ps
CPU time 1.23 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 219064 kb
Host smart-29a372c4-79a2-45bb-9288-0c683cd5a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742724071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.742724071
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.178404072
Short name T733
Test name
Test status
Simulation time 36771232 ps
CPU time 1.19 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:51 PM PDT 24
Peak memory 217012 kb
Host smart-17d55dbc-e857-4beb-9cf7-1bfa7ff7760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178404072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.178404072
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3571697905
Short name T779
Test name
Test status
Simulation time 33258368 ps
CPU time 1.62 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 216952 kb
Host smart-c2147a37-634b-4535-a545-a01d9af968b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571697905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3571697905
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3162687032
Short name T646
Test name
Test status
Simulation time 104900777 ps
CPU time 1.08 seconds
Started May 28 02:12:50 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 216948 kb
Host smart-472eedd0-505d-43e9-ab2d-178bc951a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162687032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3162687032
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3930187645
Short name T618
Test name
Test status
Simulation time 47141634 ps
CPU time 1.39 seconds
Started May 28 02:12:45 PM PDT 24
Finished May 28 02:12:48 PM PDT 24
Peak memory 216864 kb
Host smart-35e6b897-cd11-42d5-9abf-07f0c7d5c051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930187645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3930187645
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.141850819
Short name T553
Test name
Test status
Simulation time 43446651 ps
CPU time 0.88 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 206328 kb
Host smart-bd473afb-4e40-423e-a250-f38b94f6c81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141850819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.141850819
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1665296257
Short name T364
Test name
Test status
Simulation time 10901375 ps
CPU time 0.89 seconds
Started May 28 02:10:54 PM PDT 24
Finished May 28 02:10:56 PM PDT 24
Peak memory 215676 kb
Host smart-e4c0030e-b989-4861-9ca1-f79399826909
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665296257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1665296257
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.354239912
Short name T112
Test name
Test status
Simulation time 58154305 ps
CPU time 1.06 seconds
Started May 28 02:10:51 PM PDT 24
Finished May 28 02:10:54 PM PDT 24
Peak memory 218248 kb
Host smart-4979b6c6-5b00-44b8-b947-2783060c8a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354239912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.354239912
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.508989322
Short name T563
Test name
Test status
Simulation time 22730126 ps
CPU time 1.16 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 216876 kb
Host smart-bf1b9e8a-cb4b-4fd2-8519-8e4c605d3f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508989322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.508989322
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.725370836
Short name T625
Test name
Test status
Simulation time 49729238 ps
CPU time 0.85 seconds
Started May 28 02:10:52 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 215188 kb
Host smart-8e1c0911-1615-474f-9995-ee355554432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725370836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.725370836
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.735099572
Short name T315
Test name
Test status
Simulation time 14349500 ps
CPU time 0.96 seconds
Started May 28 02:10:49 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 214988 kb
Host smart-0d91c289-b817-47ed-9748-08a5d7518e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735099572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.735099572
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.189681180
Short name T434
Test name
Test status
Simulation time 210464311 ps
CPU time 2.33 seconds
Started May 28 02:10:51 PM PDT 24
Finished May 28 02:10:55 PM PDT 24
Peak memory 216656 kb
Host smart-cde664dd-78ef-461a-9457-a4ac35986232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189681180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.189681180
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_genbits.2629013054
Short name T720
Test name
Test status
Simulation time 58521070 ps
CPU time 1.51 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 218148 kb
Host smart-b42a4ced-2221-4d68-8092-095437af8b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629013054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2629013054
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.191351846
Short name T713
Test name
Test status
Simulation time 38975028 ps
CPU time 1.15 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 216872 kb
Host smart-caabe957-672a-4774-b1c5-d09908fc08ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191351846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.191351846
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.975578295
Short name T328
Test name
Test status
Simulation time 261061157 ps
CPU time 1.5 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 218204 kb
Host smart-5de423eb-6790-44d0-b9e3-15adf2d52595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975578295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.975578295
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1277605258
Short name T486
Test name
Test status
Simulation time 36348846 ps
CPU time 1.36 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 217976 kb
Host smart-8ae9ad42-6048-49fd-a59a-bc6a6040bc47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277605258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1277605258
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3863952280
Short name T1
Test name
Test status
Simulation time 95886806 ps
CPU time 1.26 seconds
Started May 28 02:12:50 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 216684 kb
Host smart-040e0f47-306e-4f58-9c97-bb70b35d59e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863952280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3863952280
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.4264374298
Short name T248
Test name
Test status
Simulation time 44537732 ps
CPU time 1.27 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 216620 kb
Host smart-8e3a201a-f17b-43b6-9f01-ef0ffb93352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264374298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4264374298
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2133576146
Short name T564
Test name
Test status
Simulation time 41535105 ps
CPU time 1.07 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 217792 kb
Host smart-1ac02f72-4248-4f4c-a87c-a8d6af39aa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133576146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2133576146
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.3143613845
Short name T341
Test name
Test status
Simulation time 106101841 ps
CPU time 2.42 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 219004 kb
Host smart-b0ad5e18-8200-4082-90d1-60b4d7fe352f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143613845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3143613845
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1354561632
Short name T422
Test name
Test status
Simulation time 77393267 ps
CPU time 1.47 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:51 PM PDT 24
Peak memory 218232 kb
Host smart-8a454f91-11ff-40e5-8281-568888d3797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354561632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1354561632
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1310112381
Short name T443
Test name
Test status
Simulation time 112349508 ps
CPU time 1.08 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:49 PM PDT 24
Peak memory 215416 kb
Host smart-deba9a1b-6784-46c3-a897-4a7bfa5d091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310112381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1310112381
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1657208004
Short name T660
Test name
Test status
Simulation time 20973153 ps
CPU time 1.04 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 214680 kb
Host smart-d8820122-9ccd-495f-b525-2d9dade1c5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657208004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1657208004
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1640000356
Short name T670
Test name
Test status
Simulation time 46484181 ps
CPU time 0.85 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:48 PM PDT 24
Peak memory 216092 kb
Host smart-a69be40c-0bfc-45f7-bf13-c21007be2716
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640000356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1640000356
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3864320587
Short name T642
Test name
Test status
Simulation time 35560963 ps
CPU time 1.4 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:52 PM PDT 24
Peak memory 219388 kb
Host smart-e81ac592-80cb-451d-9d5c-858b456542d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864320587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3864320587
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_intr.2453077380
Short name T79
Test name
Test status
Simulation time 96319337 ps
CPU time 0.91 seconds
Started May 28 02:10:44 PM PDT 24
Finished May 28 02:10:46 PM PDT 24
Peak memory 215200 kb
Host smart-78e5affd-8aee-4031-9dea-d362d24d6917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453077380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2453077380
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1424806425
Short name T606
Test name
Test status
Simulation time 28349319 ps
CPU time 0.99 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:10:49 PM PDT 24
Peak memory 214968 kb
Host smart-c62ceb14-62b5-4bdf-8108-59f915d6b68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424806425 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1424806425
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3743419695
Short name T586
Test name
Test status
Simulation time 107600854 ps
CPU time 1.57 seconds
Started May 28 02:10:48 PM PDT 24
Finished May 28 02:10:51 PM PDT 24
Peak memory 214996 kb
Host smart-eb91c963-17f6-45b8-a02c-2f63a7a69149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743419695 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3743419695
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2779260869
Short name T632
Test name
Test status
Simulation time 58296106669 ps
CPU time 1498.38 seconds
Started May 28 02:10:46 PM PDT 24
Finished May 28 02:35:46 PM PDT 24
Peak memory 224156 kb
Host smart-de98c54e-4263-4de9-bc19-a3a3526786cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779260869 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2779260869
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.4034239005
Short name T778
Test name
Test status
Simulation time 335189176 ps
CPU time 3.38 seconds
Started May 28 02:12:46 PM PDT 24
Finished May 28 02:12:51 PM PDT 24
Peak memory 217072 kb
Host smart-bf85f866-d9fb-49d2-a2fc-af4283f46ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034239005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4034239005
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1832056193
Short name T523
Test name
Test status
Simulation time 41390206 ps
CPU time 1.41 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 218032 kb
Host smart-4605cd91-db8b-4760-975e-cd61789a1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832056193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1832056193
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.245089407
Short name T511
Test name
Test status
Simulation time 32090168 ps
CPU time 1.21 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 216820 kb
Host smart-86a018f0-4fc4-428d-89dd-56f5676c4e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245089407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.245089407
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2318922325
Short name T284
Test name
Test status
Simulation time 39642969 ps
CPU time 1.53 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 219408 kb
Host smart-5fc54df6-f176-44fd-8ed0-443febfe8922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318922325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2318922325
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1315505062
Short name T438
Test name
Test status
Simulation time 57577441 ps
CPU time 2.17 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 218008 kb
Host smart-d8dbb9a3-3073-4620-b790-fe3a40cc41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315505062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1315505062
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1552891385
Short name T754
Test name
Test status
Simulation time 75225907 ps
CPU time 1.08 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 216764 kb
Host smart-95c89779-717d-4456-9d28-dabbcf378921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552891385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1552891385
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4290502038
Short name T719
Test name
Test status
Simulation time 100361865 ps
CPU time 2.4 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 219096 kb
Host smart-871e55b7-fea0-49e4-b123-389bedbd89e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290502038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4290502038
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4176686545
Short name T650
Test name
Test status
Simulation time 267877736 ps
CPU time 1.97 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 218796 kb
Host smart-9654e127-4476-4a33-a87d-67ba2c6387e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176686545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4176686545
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.478874466
Short name T302
Test name
Test status
Simulation time 44913936 ps
CPU time 1.11 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:55 PM PDT 24
Peak memory 218040 kb
Host smart-2f52491a-3c7f-4085-b3b6-d054ecf99008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478874466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.478874466
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.635907593
Short name T623
Test name
Test status
Simulation time 40794889 ps
CPU time 1.5 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 219368 kb
Host smart-35103d72-f64d-4fad-8b79-e8732ee94c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635907593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.635907593
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.362078790
Short name T191
Test name
Test status
Simulation time 26524166 ps
CPU time 1.18 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 215420 kb
Host smart-6343ba1f-540b-4152-9df6-88376f1b9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362078790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.362078790
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4071038971
Short name T630
Test name
Test status
Simulation time 18046113 ps
CPU time 0.96 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 206336 kb
Host smart-ae5cd73d-8dd1-41c8-a40d-e60a0606696e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071038971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4071038971
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.755760937
Short name T745
Test name
Test status
Simulation time 15611705 ps
CPU time 0.91 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:07 PM PDT 24
Peak memory 216232 kb
Host smart-eb33de94-5749-4ab7-8ed8-863789f0a599
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755760937 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.755760937
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2308029975
Short name T359
Test name
Test status
Simulation time 38078953 ps
CPU time 1.42 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 217772 kb
Host smart-18b32532-6c6b-4099-bca6-0e27b2632483
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308029975 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2308029975
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2157559287
Short name T14
Test name
Test status
Simulation time 20211675 ps
CPU time 1.21 seconds
Started May 28 02:11:09 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 223716 kb
Host smart-bbc53dff-1f70-4536-8f8c-39535d2b0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157559287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2157559287
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.528618462
Short name T207
Test name
Test status
Simulation time 41382679 ps
CPU time 1.5 seconds
Started May 28 02:11:03 PM PDT 24
Finished May 28 02:11:05 PM PDT 24
Peak memory 215040 kb
Host smart-3124c5a7-77f5-4adf-a507-444cacf495a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528618462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.528618462
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.748430850
Short name T338
Test name
Test status
Simulation time 27293080 ps
CPU time 1.07 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:08 PM PDT 24
Peak memory 215128 kb
Host smart-d83f2b1c-8260-41af-811d-82269034bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748430850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.748430850
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3149993795
Short name T432
Test name
Test status
Simulation time 15729849 ps
CPU time 1.04 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 215028 kb
Host smart-7cf33b22-1973-4250-89db-8114dbd995f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149993795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3149993795
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3293882176
Short name T212
Test name
Test status
Simulation time 307945297 ps
CPU time 2.17 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 216660 kb
Host smart-8e07aeaa-f140-4df2-827c-ea33e81f912f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293882176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3293882176
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.544636236
Short name T519
Test name
Test status
Simulation time 143458494868 ps
CPU time 742.42 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:23:29 PM PDT 24
Peak memory 219496 kb
Host smart-a9b13e3e-1d45-4f94-a725-85d1c6298fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544636236 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.544636236
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1865559475
Short name T673
Test name
Test status
Simulation time 40393719 ps
CPU time 1.09 seconds
Started May 28 02:12:47 PM PDT 24
Finished May 28 02:12:50 PM PDT 24
Peak memory 216808 kb
Host smart-c9dad8da-8251-4a80-ad86-e20b6671fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865559475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1865559475
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1633783778
Short name T748
Test name
Test status
Simulation time 47858918 ps
CPU time 0.99 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 216804 kb
Host smart-5b71f364-22cb-4a47-bfc4-6b64ec82c5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633783778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1633783778
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.848176716
Short name T510
Test name
Test status
Simulation time 79031791 ps
CPU time 1.45 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 218232 kb
Host smart-bc3db96a-3d21-4dd5-bb24-c441fe025d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848176716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.848176716
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1983176217
Short name T585
Test name
Test status
Simulation time 29482327 ps
CPU time 1.29 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:55 PM PDT 24
Peak memory 218080 kb
Host smart-e7357dde-bf2f-46a2-85a9-ae845fab7556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983176217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1983176217
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2856051758
Short name T547
Test name
Test status
Simulation time 100206092 ps
CPU time 1.19 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 216772 kb
Host smart-e56056e9-7be7-4870-9759-443eb5dc6d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856051758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2856051758
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3908637791
Short name T735
Test name
Test status
Simulation time 116475076 ps
CPU time 1.47 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 217988 kb
Host smart-4379d9ee-1142-4dca-aa7d-d7efe6b6d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908637791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3908637791
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1123237613
Short name T320
Test name
Test status
Simulation time 72376143 ps
CPU time 1.18 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 216696 kb
Host smart-77e7c6c5-b105-4599-8195-8448fafffca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123237613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1123237613
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.295716717
Short name T531
Test name
Test status
Simulation time 70697618 ps
CPU time 1.39 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 217956 kb
Host smart-4a5c2576-fc35-4b7b-863e-f256f0257aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295716717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.295716717
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2955758239
Short name T487
Test name
Test status
Simulation time 57884652 ps
CPU time 1.3 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 218188 kb
Host smart-d305cacc-d92e-4856-80a6-08fe5de0593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955758239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2955758239
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.169412323
Short name T91
Test name
Test status
Simulation time 85206119 ps
CPU time 1.13 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 215440 kb
Host smart-706769d7-4f19-40e2-868f-bd03c28ab842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169412323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.169412323
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1138359724
Short name T608
Test name
Test status
Simulation time 111515885 ps
CPU time 0.86 seconds
Started May 28 02:10:05 PM PDT 24
Finished May 28 02:10:07 PM PDT 24
Peak memory 214416 kb
Host smart-7bd1724e-616f-464e-9572-46abdccf9c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138359724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1138359724
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3203201054
Short name T676
Test name
Test status
Simulation time 17360614 ps
CPU time 0.88 seconds
Started May 28 02:10:05 PM PDT 24
Finished May 28 02:10:08 PM PDT 24
Peak memory 215708 kb
Host smart-dff73f16-c1e1-4b1a-a639-dec9c03a83aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203201054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3203201054
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1250212257
Short name T116
Test name
Test status
Simulation time 40352811 ps
CPU time 1.36 seconds
Started May 28 02:10:05 PM PDT 24
Finished May 28 02:10:08 PM PDT 24
Peak memory 216640 kb
Host smart-2bcb6b75-b9f1-4db1-83ab-49d5d3d88abe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250212257 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1250212257
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3255398716
Short name T208
Test name
Test status
Simulation time 20004072 ps
CPU time 1.16 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 223428 kb
Host smart-58ba70f6-6af3-45ff-bc51-a3720a0f3342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255398716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3255398716
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1237435626
Short name T601
Test name
Test status
Simulation time 44657712 ps
CPU time 1.32 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 216864 kb
Host smart-9c077a24-fba4-4e44-bd4a-aa1284cf8b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237435626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1237435626
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4294149601
Short name T390
Test name
Test status
Simulation time 22796858 ps
CPU time 0.93 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 215408 kb
Host smart-f69cb152-8c5b-4640-a29a-d3bbaab397b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294149601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4294149601
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.296189379
Short name T28
Test name
Test status
Simulation time 94642015 ps
CPU time 0.96 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 207044 kb
Host smart-dfe40b52-5ce4-48b8-a0a1-bb977d18df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296189379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.296189379
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.267325228
Short name T374
Test name
Test status
Simulation time 51652097 ps
CPU time 0.88 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 214892 kb
Host smart-89fc2572-cc13-4067-8aa9-177363b9b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267325228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.267325228
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1049945344
Short name T587
Test name
Test status
Simulation time 710637830 ps
CPU time 2.19 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 219732 kb
Host smart-ff65f2b3-022a-43b9-be8c-ab3ea5c013a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049945344 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1049945344
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3378051689
Short name T389
Test name
Test status
Simulation time 142175737871 ps
CPU time 887.34 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:24:58 PM PDT 24
Peak memory 222804 kb
Host smart-70c2f94c-2998-4839-a046-15d2b5f4b072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378051689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3378051689
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3186238692
Short name T265
Test name
Test status
Simulation time 66339365 ps
CPU time 1.21 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:08 PM PDT 24
Peak memory 215408 kb
Host smart-200d3122-ad16-4d17-a037-fe41adc96352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186238692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3186238692
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3583040637
Short name T326
Test name
Test status
Simulation time 69688148 ps
CPU time 1.01 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:06 PM PDT 24
Peak memory 206328 kb
Host smart-c382ef0b-2592-48e3-b4c9-a21b5576a24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583040637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3583040637
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1688421750
Short name T63
Test name
Test status
Simulation time 19613339 ps
CPU time 0.85 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 216096 kb
Host smart-b7a1cb04-5a19-4d82-8bce-4e74e67b3d62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688421750 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1688421750
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.985901433
Short name T544
Test name
Test status
Simulation time 50525156 ps
CPU time 1.13 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 216656 kb
Host smart-8f213adb-5e1f-4ca1-8189-e6980cb6b9e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985901433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.985901433
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3778271327
Short name T130
Test name
Test status
Simulation time 28243876 ps
CPU time 0.93 seconds
Started May 28 02:11:00 PM PDT 24
Finished May 28 02:11:02 PM PDT 24
Peak memory 217916 kb
Host smart-98705d42-70a1-4075-93ac-2710614c8c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778271327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3778271327
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1414272124
Short name T760
Test name
Test status
Simulation time 44653013 ps
CPU time 1.6 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 219396 kb
Host smart-424c86e8-34f6-441b-97d2-79564682a642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414272124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1414272124
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1043909420
Short name T696
Test name
Test status
Simulation time 22980351 ps
CPU time 1.08 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 215108 kb
Host smart-d4aa0a7c-b310-496c-8149-7189d65f2803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043909420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1043909420
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1712267463
Short name T333
Test name
Test status
Simulation time 17664962 ps
CPU time 1.09 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 215008 kb
Host smart-ea76ca87-e8c8-484a-954a-7c26448734e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712267463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1712267463
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3551292070
Short name T211
Test name
Test status
Simulation time 279257890 ps
CPU time 5.58 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:16 PM PDT 24
Peak memory 215084 kb
Host smart-2074511d-7031-4cc9-97eb-2b8cdc9a03f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551292070 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3551292070
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.177115745
Short name T407
Test name
Test status
Simulation time 37915104540 ps
CPU time 1012.07 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:27:57 PM PDT 24
Peak memory 220228 kb
Host smart-484ea4d2-1b10-40b3-a328-8b20da4dcd24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177115745 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.177115745
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2653278088
Short name T370
Test name
Test status
Simulation time 82539133 ps
CPU time 1.14 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 216828 kb
Host smart-4d13278d-5995-4354-b54e-e85ab7a62639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653278088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2653278088
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3620405901
Short name T483
Test name
Test status
Simulation time 50727195 ps
CPU time 2.02 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 219948 kb
Host smart-7dd64726-b32c-4910-bbdf-d6b0df83e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620405901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3620405901
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1185913105
Short name T378
Test name
Test status
Simulation time 56757558 ps
CPU time 1.53 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 218116 kb
Host smart-d1bf271d-cddf-4fbf-aca8-12981e26c771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185913105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1185913105
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1323111610
Short name T81
Test name
Test status
Simulation time 53762586 ps
CPU time 1.46 seconds
Started May 28 02:12:54 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 216796 kb
Host smart-cddd6434-a63e-4657-b228-2be3eb15f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323111610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1323111610
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.449423047
Short name T88
Test name
Test status
Simulation time 58717339 ps
CPU time 1.35 seconds
Started May 28 02:12:50 PM PDT 24
Finished May 28 02:12:54 PM PDT 24
Peak memory 219440 kb
Host smart-c0bef28f-beaa-4e33-919f-b491a65c6ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449423047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.449423047
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3507667917
Short name T781
Test name
Test status
Simulation time 45934828 ps
CPU time 1.28 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 218312 kb
Host smart-10e867ca-d400-4d10-80e3-d459d2bf82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507667917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3507667917
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3630913227
Short name T476
Test name
Test status
Simulation time 102777856 ps
CPU time 1.2 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 216804 kb
Host smart-97049acc-fc2c-406f-9546-ce0864548682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630913227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3630913227
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.595006307
Short name T245
Test name
Test status
Simulation time 171392219 ps
CPU time 1.18 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 219568 kb
Host smart-5a4de545-35d4-4a10-8d3a-b5430e945541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595006307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.595006307
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1416232256
Short name T700
Test name
Test status
Simulation time 41606178 ps
CPU time 1.14 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 219312 kb
Host smart-bbcb7275-f9ae-4de1-920c-262a86de1ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416232256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1416232256
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.727240457
Short name T412
Test name
Test status
Simulation time 50003499 ps
CPU time 1.17 seconds
Started May 28 02:12:49 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 216728 kb
Host smart-98a71c7f-2027-49d0-b97d-101740d88047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727240457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.727240457
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3183092512
Short name T706
Test name
Test status
Simulation time 77892031 ps
CPU time 1.25 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:08 PM PDT 24
Peak memory 215404 kb
Host smart-39472189-ef7c-4bff-acfb-a5b85d40260a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183092512 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3183092512
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2199749094
Short name T360
Test name
Test status
Simulation time 25064045 ps
CPU time 0.91 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 206352 kb
Host smart-d96cc7b6-c255-4a9b-8056-0e60b0200945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199749094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2199749094
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2685579294
Short name T804
Test name
Test status
Simulation time 34759904 ps
CPU time 0.85 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:13 PM PDT 24
Peak memory 215256 kb
Host smart-6c9d5775-f07f-493a-a3c7-9cafd437a9d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685579294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2685579294
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3487067344
Short name T591
Test name
Test status
Simulation time 47613434 ps
CPU time 1.02 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 216684 kb
Host smart-52b6c66c-6d50-45c7-abd7-84014aa3abe6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487067344 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3487067344
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.881488364
Short name T513
Test name
Test status
Simulation time 19564070 ps
CPU time 1.03 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 218148 kb
Host smart-baa65bbc-abc1-45d7-8a6f-a86481184313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881488364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.881488364
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.482877118
Short name T847
Test name
Test status
Simulation time 146923353 ps
CPU time 1.24 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:08 PM PDT 24
Peak memory 216668 kb
Host smart-d1c7cda2-51ff-4115-b8fe-3174bbfcce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482877118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.482877118
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2045429076
Short name T373
Test name
Test status
Simulation time 85891778 ps
CPU time 1.02 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:06 PM PDT 24
Peak memory 223460 kb
Host smart-82cf7088-b60e-46fa-887b-93570e6781bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045429076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2045429076
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2924454648
Short name T687
Test name
Test status
Simulation time 22701339 ps
CPU time 0.95 seconds
Started May 28 02:11:03 PM PDT 24
Finished May 28 02:11:05 PM PDT 24
Peak memory 214972 kb
Host smart-4800a4ae-5674-40c4-b87e-023b7880982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924454648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2924454648
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.872027897
Short name T404
Test name
Test status
Simulation time 2232950797 ps
CPU time 5.32 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:16 PM PDT 24
Peak memory 216860 kb
Host smart-de453c42-ca06-4f1e-85b6-efe020ce5e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872027897 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.872027897
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1146744969
Short name T446
Test name
Test status
Simulation time 111861827224 ps
CPU time 1388.04 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:34:13 PM PDT 24
Peak memory 225972 kb
Host smart-737e4ac8-b059-4896-97aa-fcced30b00d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146744969 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1146744969
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.493087325
Short name T850
Test name
Test status
Simulation time 246905375 ps
CPU time 1.86 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 218528 kb
Host smart-0d8511dc-7d8a-4667-81ef-c9bfc1196621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493087325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.493087325
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1399150312
Short name T329
Test name
Test status
Simulation time 75388656 ps
CPU time 1.37 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 217760 kb
Host smart-40a9d775-bb45-40e9-8aa8-a5911dee14fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399150312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1399150312
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.4254810500
Short name T449
Test name
Test status
Simulation time 71215120 ps
CPU time 1.33 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:52 PM PDT 24
Peak memory 216768 kb
Host smart-511fac91-a121-4460-8a1c-e2cce8156020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254810500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.4254810500
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2459563904
Short name T453
Test name
Test status
Simulation time 61138592 ps
CPU time 1.32 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 216832 kb
Host smart-ed5c0da9-0310-40bf-9a7b-154259a6c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459563904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2459563904
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1989419587
Short name T298
Test name
Test status
Simulation time 40308551 ps
CPU time 1.15 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 219352 kb
Host smart-4c404b07-8971-4146-b6f9-639caffb36ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989419587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1989419587
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1006317971
Short name T603
Test name
Test status
Simulation time 247810672 ps
CPU time 3.81 seconds
Started May 28 02:12:55 PM PDT 24
Finished May 28 02:13:01 PM PDT 24
Peak memory 219552 kb
Host smart-debfd5d8-48fe-407f-82c9-c0d152fd759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006317971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1006317971
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1449515673
Short name T684
Test name
Test status
Simulation time 106369602 ps
CPU time 1.28 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 219228 kb
Host smart-8a2d6bac-214f-47fb-a571-8e9b71593244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449515673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1449515673
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.226664621
Short name T849
Test name
Test status
Simulation time 66976288 ps
CPU time 1.37 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 216944 kb
Host smart-e1518a77-5500-4ff7-bf2f-e808fe511e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226664621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.226664621
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1864407175
Short name T751
Test name
Test status
Simulation time 214761126 ps
CPU time 1.12 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 216820 kb
Host smart-298578d7-c302-499c-aeb5-e9bd6270b71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864407175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1864407175
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3821438490
Short name T45
Test name
Test status
Simulation time 189227067 ps
CPU time 1.52 seconds
Started May 28 02:12:57 PM PDT 24
Finished May 28 02:13:01 PM PDT 24
Peak memory 219552 kb
Host smart-f1d856bf-ddd5-4cd8-b2ce-68dfa629faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821438490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3821438490
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.1867467464
Short name T526
Test name
Test status
Simulation time 80510992 ps
CPU time 0.86 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:13 PM PDT 24
Peak memory 206172 kb
Host smart-cebb316a-ea00-4a10-b476-a056971a02a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867467464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1867467464
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3859207918
Short name T343
Test name
Test status
Simulation time 136917118 ps
CPU time 0.9 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 215736 kb
Host smart-dd4b7187-9642-4577-bdb8-c7b57cf671f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859207918 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3859207918
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3523172576
Short name T423
Test name
Test status
Simulation time 91026065 ps
CPU time 1.05 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 216780 kb
Host smart-5910f337-babe-48bd-b083-87df1965746a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523172576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3523172576
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.854479050
Short name T680
Test name
Test status
Simulation time 21362497 ps
CPU time 0.95 seconds
Started May 28 02:11:05 PM PDT 24
Finished May 28 02:11:08 PM PDT 24
Peak memory 218332 kb
Host smart-5fac89cd-4f49-47b9-8b39-2f3fe509dfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854479050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.854479050
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.803328014
Short name T450
Test name
Test status
Simulation time 28161861 ps
CPU time 1.23 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 219016 kb
Host smart-3dbf2c82-0823-4450-9224-dbe73a7df533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803328014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.803328014
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1974121784
Short name T419
Test name
Test status
Simulation time 30207719 ps
CPU time 0.96 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 215120 kb
Host smart-b64ade12-0ecb-4830-9e68-4c554a4e1c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974121784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1974121784
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2227447861
Short name T792
Test name
Test status
Simulation time 24044840 ps
CPU time 0.93 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 215028 kb
Host smart-a3fbcc1d-7171-4585-8244-b15e104d0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227447861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2227447861
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1959623912
Short name T693
Test name
Test status
Simulation time 130507987 ps
CPU time 1.31 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:07 PM PDT 24
Peak memory 215028 kb
Host smart-90a8ec0b-eaf3-408c-ae76-2062ee997ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959623912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1959623912
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.309579148
Short name T409
Test name
Test status
Simulation time 25165553743 ps
CPU time 663.71 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:22:09 PM PDT 24
Peak memory 217212 kb
Host smart-d0c00c0e-7167-42b8-9fea-a3ff3887a0be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309579148 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.309579148
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.2786402220
Short name T283
Test name
Test status
Simulation time 118584982 ps
CPU time 1.52 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 218100 kb
Host smart-ccdbc272-f015-4a14-9406-1e4b3f0820f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786402220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.2786402220
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2841982015
Short name T616
Test name
Test status
Simulation time 48213268 ps
CPU time 1.51 seconds
Started May 28 02:12:55 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 217792 kb
Host smart-ae4bc37c-c474-4eb1-aa95-4ec62c534f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841982015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2841982015
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2129054149
Short name T317
Test name
Test status
Simulation time 50106593 ps
CPU time 1.11 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 216824 kb
Host smart-28e5ced4-aa48-4150-a9eb-372057b9acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129054149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2129054149
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2682281741
Short name T403
Test name
Test status
Simulation time 41839858 ps
CPU time 1.3 seconds
Started May 28 02:12:52 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 218296 kb
Host smart-6f106768-e46a-4dcf-8351-0862e1f339ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682281741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2682281741
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4173839033
Short name T721
Test name
Test status
Simulation time 270283015 ps
CPU time 3.33 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 219016 kb
Host smart-6b0556c4-e369-4dbc-9174-58f0efec7b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173839033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4173839033
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.232880877
Short name T729
Test name
Test status
Simulation time 38591746 ps
CPU time 1.21 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:55 PM PDT 24
Peak memory 218116 kb
Host smart-18dfd14d-7423-49de-86f3-ddfc372411d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232880877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.232880877
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3467945624
Short name T297
Test name
Test status
Simulation time 41958301 ps
CPU time 1.43 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 217968 kb
Host smart-bd65a22d-c817-4033-b9ab-8a86dc9443a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467945624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3467945624
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2583778960
Short name T557
Test name
Test status
Simulation time 72126989 ps
CPU time 1.13 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:55 PM PDT 24
Peak memory 216624 kb
Host smart-d7c97846-2dac-4605-8195-3143a317e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583778960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2583778960
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2258946425
Short name T83
Test name
Test status
Simulation time 44581081 ps
CPU time 1.19 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:57 PM PDT 24
Peak memory 218164 kb
Host smart-2e4ddcce-4e07-45ff-b856-b134f9664834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258946425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2258946425
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4214250882
Short name T656
Test name
Test status
Simulation time 253839548 ps
CPU time 2.02 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 219776 kb
Host smart-ceb8f7cc-4241-4e01-b60d-854b7a3dfb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214250882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4214250882
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4144702846
Short name T252
Test name
Test status
Simulation time 189066742 ps
CPU time 1.31 seconds
Started May 28 02:11:04 PM PDT 24
Finished May 28 02:11:06 PM PDT 24
Peak memory 215388 kb
Host smart-bb9d8233-4f15-4e83-aaaa-5596077a1f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144702846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4144702846
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1695797901
Short name T772
Test name
Test status
Simulation time 15357366 ps
CPU time 0.93 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 214556 kb
Host smart-3a938f09-cd92-4a98-806c-17891132cfdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695797901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1695797901
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.216839213
Short name T172
Test name
Test status
Simulation time 86323624 ps
CPU time 0.8 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 215208 kb
Host smart-59e34d64-c01c-404f-89b2-33697046fec5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216839213 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.216839213
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.269347887
Short name T806
Test name
Test status
Simulation time 27770918 ps
CPU time 0.98 seconds
Started May 28 02:11:11 PM PDT 24
Finished May 28 02:11:15 PM PDT 24
Peak memory 215408 kb
Host smart-395aef20-25e7-47c8-a696-4de6bb493e80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269347887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.269347887
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2663341051
Short name T492
Test name
Test status
Simulation time 36863477 ps
CPU time 0.89 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 218096 kb
Host smart-36bfb07f-2d42-4b8a-887c-27503825c6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663341051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2663341051
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1845196976
Short name T668
Test name
Test status
Simulation time 77703676 ps
CPU time 1.43 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 218384 kb
Host smart-6f2a3b1f-eef9-4d54-b007-5caeef57d786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845196976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1845196976
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2418695602
Short name T545
Test name
Test status
Simulation time 41976778 ps
CPU time 0.93 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 215108 kb
Host smart-c4e538c8-110a-4761-a366-2bc1c647359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418695602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2418695602
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3019632737
Short name T732
Test name
Test status
Simulation time 16241887 ps
CPU time 1.05 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 215008 kb
Host smart-1d54214a-0e60-49e4-9e4f-3662afe180bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019632737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3019632737
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1616610548
Short name T72
Test name
Test status
Simulation time 151379336 ps
CPU time 2.92 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 217928 kb
Host smart-d21281ed-5d0c-480e-8a66-6959b9f6ff54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616610548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1616610548
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1536900932
Short name T196
Test name
Test status
Simulation time 142138874693 ps
CPU time 326.45 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:16:38 PM PDT 24
Peak memory 218280 kb
Host smart-b51442d4-f3b3-4a41-83c8-8573b16cac1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536900932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1536900932
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2299568142
Short name T565
Test name
Test status
Simulation time 99046863 ps
CPU time 1.48 seconds
Started May 28 02:12:53 PM PDT 24
Finished May 28 02:12:58 PM PDT 24
Peak memory 217944 kb
Host smart-a2ca14ed-7759-4a86-afb5-ab28fea67c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299568142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2299568142
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2428380038
Short name T29
Test name
Test status
Simulation time 63176451 ps
CPU time 1.31 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:13:00 PM PDT 24
Peak memory 218480 kb
Host smart-9a269663-b323-43a1-a487-e64cd9411a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428380038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2428380038
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4191907032
Short name T462
Test name
Test status
Simulation time 68653015 ps
CPU time 0.95 seconds
Started May 28 02:12:56 PM PDT 24
Finished May 28 02:12:59 PM PDT 24
Peak memory 216880 kb
Host smart-1497e609-b99e-482d-925d-6f0322153be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191907032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4191907032
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.110532706
Short name T682
Test name
Test status
Simulation time 64285698 ps
CPU time 1.86 seconds
Started May 28 02:12:48 PM PDT 24
Finished May 28 02:12:53 PM PDT 24
Peak memory 218192 kb
Host smart-570c7ce0-cc2b-48db-a1b3-3e4f59193ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110532706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.110532706
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3623458507
Short name T791
Test name
Test status
Simulation time 28600413 ps
CPU time 1.02 seconds
Started May 28 02:12:51 PM PDT 24
Finished May 28 02:12:56 PM PDT 24
Peak memory 217100 kb
Host smart-7d55ca5a-6c30-4384-9a47-b218a8d75d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623458507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3623458507
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.375703779
Short name T497
Test name
Test status
Simulation time 79258517 ps
CPU time 1.43 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 215036 kb
Host smart-7bb18eb6-20e1-42ab-bb1c-441fe9edd6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375703779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.375703779
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3762776879
Short name T48
Test name
Test status
Simulation time 41609243 ps
CPU time 1.63 seconds
Started May 28 02:12:58 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 217864 kb
Host smart-709a3aa4-e880-443e-a4a8-f21e8e251406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762776879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3762776879
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2834376351
Short name T725
Test name
Test status
Simulation time 38230365 ps
CPU time 1.44 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 218072 kb
Host smart-9acebbd8-f699-4427-b1d8-b42a8d324bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834376351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2834376351
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2355092299
Short name T746
Test name
Test status
Simulation time 63015895 ps
CPU time 1.14 seconds
Started May 28 02:12:59 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 216736 kb
Host smart-49b5c4e2-f0df-4554-bdbf-7bcbb8c736ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355092299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2355092299
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.3257541749
Short name T556
Test name
Test status
Simulation time 21025303 ps
CPU time 1.08 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:11 PM PDT 24
Peak memory 206456 kb
Host smart-9149f01e-66a9-42bd-a60e-dec1cc6e8609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257541749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3257541749
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.159600666
Short name T571
Test name
Test status
Simulation time 45475103 ps
CPU time 0.83 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 214852 kb
Host smart-693bee37-4567-4331-9858-8c691ddfbb8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159600666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.159600666
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2371398281
Short name T78
Test name
Test status
Simulation time 49102767 ps
CPU time 1.1 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:09 PM PDT 24
Peak memory 216668 kb
Host smart-824f7f7b-71fa-483c-96cd-4e22e0edc2ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371398281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2371398281
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3150370348
Short name T118
Test name
Test status
Simulation time 48514737 ps
CPU time 1.12 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:13 PM PDT 24
Peak memory 229236 kb
Host smart-d82bcc49-1de2-4c78-a827-5844a7512394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150370348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3150370348
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2505618227
Short name T595
Test name
Test status
Simulation time 66389340 ps
CPU time 1.61 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 217928 kb
Host smart-4df33162-725d-4bf5-a6f0-6c6905f3f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505618227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2505618227
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.208646163
Short name T379
Test name
Test status
Simulation time 22042370 ps
CPU time 1.2 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 223644 kb
Host smart-3fc8601a-8a8d-46b9-835e-26340ff4f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208646163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.208646163
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.230489727
Short name T400
Test name
Test status
Simulation time 27834861 ps
CPU time 0.95 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:10 PM PDT 24
Peak memory 215028 kb
Host smart-d874a037-56a2-41e9-b3cf-9a91e1e691d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230489727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.230489727
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.298920348
Short name T167
Test name
Test status
Simulation time 725027656 ps
CPU time 2.49 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:13 PM PDT 24
Peak memory 215112 kb
Host smart-5364fab0-c748-4746-adfa-e82fa11c51c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298920348 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.298920348
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1470745733
Short name T201
Test name
Test status
Simulation time 169414849981 ps
CPU time 1449.85 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:35:22 PM PDT 24
Peak memory 222760 kb
Host smart-9effc332-331c-4d69-9d7d-7cdb57353541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470745733 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1470745733
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/241.edn_genbits.1881178986
Short name T597
Test name
Test status
Simulation time 47023762 ps
CPU time 1.66 seconds
Started May 28 02:13:02 PM PDT 24
Finished May 28 02:13:05 PM PDT 24
Peak memory 219600 kb
Host smart-b27b7201-9990-435f-8644-3482c51f7ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881178986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1881178986
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3125333730
Short name T808
Test name
Test status
Simulation time 201170471 ps
CPU time 2.57 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:07 PM PDT 24
Peak memory 216996 kb
Host smart-7fdd971c-1316-4a1f-a468-92e29b69108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125333730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3125333730
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3476413313
Short name T569
Test name
Test status
Simulation time 44195058 ps
CPU time 1.76 seconds
Started May 28 02:13:04 PM PDT 24
Finished May 28 02:13:07 PM PDT 24
Peak memory 216872 kb
Host smart-f97e9179-e733-44d6-a0c0-f59b8e80a9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476413313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3476413313
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3404511396
Short name T344
Test name
Test status
Simulation time 67477231 ps
CPU time 1.36 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:12 PM PDT 24
Peak memory 216788 kb
Host smart-3dfcdf2c-10c9-4de0-afcb-e8beaf2caa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404511396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3404511396
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1066466236
Short name T464
Test name
Test status
Simulation time 91154102 ps
CPU time 1.16 seconds
Started May 28 02:13:05 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 216800 kb
Host smart-018fa90e-4ad1-47d2-9d72-2c2b6a6e2c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066466236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1066466236
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.167325743
Short name T465
Test name
Test status
Simulation time 50746180 ps
CPU time 1.26 seconds
Started May 28 02:12:59 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 216644 kb
Host smart-294ac8ca-6ab5-4d61-9d10-13618d42e125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167325743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.167325743
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3816558697
Short name T535
Test name
Test status
Simulation time 29247052 ps
CPU time 1.3 seconds
Started May 28 02:13:04 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 217984 kb
Host smart-d2ec374a-e87b-4d01-a612-181676111c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816558697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3816558697
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3989079815
Short name T50
Test name
Test status
Simulation time 60665787 ps
CPU time 1.12 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 216832 kb
Host smart-c057e6ad-058a-455d-8ba8-e151b09add3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989079815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3989079815
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.260657462
Short name T322
Test name
Test status
Simulation time 44353507 ps
CPU time 1.7 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 217980 kb
Host smart-08746dc4-35a0-4a39-9d01-253bb7710565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260657462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.260657462
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.4287463776
Short name T731
Test name
Test status
Simulation time 23869152 ps
CPU time 0.86 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 206320 kb
Host smart-e769991e-a0c5-48ac-baa3-19be93fb1ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287463776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.4287463776
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2210956118
Short name T750
Test name
Test status
Simulation time 56496191 ps
CPU time 0.94 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 216296 kb
Host smart-be061090-7e19-41a7-bf14-bdb4421d8374
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210956118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2210956118
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.822419042
Short name T177
Test name
Test status
Simulation time 40791010 ps
CPU time 1.36 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:14 PM PDT 24
Peak memory 216572 kb
Host smart-400be1ea-348b-4c15-8f26-d045be75e566
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822419042 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.822419042
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.720475379
Short name T812
Test name
Test status
Simulation time 29569824 ps
CPU time 1.31 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:15 PM PDT 24
Peak memory 219116 kb
Host smart-5602737e-46ed-4a90-b3db-6ff5ba849ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720475379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.720475379
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.599073435
Short name T406
Test name
Test status
Simulation time 57916209 ps
CPU time 1.64 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 217820 kb
Host smart-b7003726-d0ad-4660-86bc-aee25624919d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599073435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.599073435
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3728095136
Short name T35
Test name
Test status
Simulation time 27132900 ps
CPU time 0.98 seconds
Started May 28 02:11:11 PM PDT 24
Finished May 28 02:11:15 PM PDT 24
Peak memory 215592 kb
Host smart-6d4996af-8294-48b4-8ff5-a7fbeb01c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728095136 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3728095136
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.485952618
Short name T727
Test name
Test status
Simulation time 17545186 ps
CPU time 0.98 seconds
Started May 28 02:11:10 PM PDT 24
Finished May 28 02:11:15 PM PDT 24
Peak memory 215048 kb
Host smart-861566fb-ce08-4fb3-9e98-a43459bea74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485952618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.485952618
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2114273764
Short name T649
Test name
Test status
Simulation time 38211015 ps
CPU time 1.35 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 206196 kb
Host smart-ca13c8f9-0ae4-49a5-ae34-d2994f3a98ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114273764 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2114273764
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2567464508
Short name T57
Test name
Test status
Simulation time 182618130545 ps
CPU time 1303.33 seconds
Started May 28 02:11:07 PM PDT 24
Finished May 28 02:32:54 PM PDT 24
Peak memory 223968 kb
Host smart-10a0a9f2-1f11-4afe-866e-83e2313b1a98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567464508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2567464508
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3910760028
Short name T619
Test name
Test status
Simulation time 36480307 ps
CPU time 1.3 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 216696 kb
Host smart-cae3bf25-8267-4cf6-b6c4-c9aeede3463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910760028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3910760028
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1482377938
Short name T694
Test name
Test status
Simulation time 40325198 ps
CPU time 1.2 seconds
Started May 28 02:13:05 PM PDT 24
Finished May 28 02:13:07 PM PDT 24
Peak memory 218040 kb
Host smart-ead44139-e49b-4fe8-8708-ae84ab24b721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482377938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1482377938
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.4153860384
Short name T49
Test name
Test status
Simulation time 51003666 ps
CPU time 1.91 seconds
Started May 28 02:13:01 PM PDT 24
Finished May 28 02:13:05 PM PDT 24
Peak memory 219576 kb
Host smart-c4afeca4-de1d-4a83-beb8-9d88a2343a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153860384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.4153860384
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1753342675
Short name T489
Test name
Test status
Simulation time 41207407 ps
CPU time 1.53 seconds
Started May 28 02:13:05 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 217956 kb
Host smart-03901cad-0a85-4c77-83cb-5ceeb98373e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753342675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1753342675
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.469233576
Short name T12
Test name
Test status
Simulation time 86559561 ps
CPU time 1.2 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 219220 kb
Host smart-3d8f6275-14da-4930-9d0b-5bc7b07e972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469233576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.469233576
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1274618606
Short name T726
Test name
Test status
Simulation time 31184323 ps
CPU time 1.29 seconds
Started May 28 02:13:08 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 216816 kb
Host smart-9318db7e-5a58-4deb-98a8-a5bd89362401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274618606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1274618606
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.264173264
Short name T312
Test name
Test status
Simulation time 98281593 ps
CPU time 1.58 seconds
Started May 28 02:12:58 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 218400 kb
Host smart-d3a19438-8b64-475c-84ad-d727f305ca8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264173264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.264173264
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.520117052
Short name T330
Test name
Test status
Simulation time 41913971 ps
CPU time 1.22 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:12 PM PDT 24
Peak memory 218160 kb
Host smart-2fbdc416-8a76-40c2-b38b-c16b3060a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520117052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.520117052
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3346024459
Short name T723
Test name
Test status
Simulation time 26483030 ps
CPU time 1.41 seconds
Started May 28 02:13:06 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 216660 kb
Host smart-018bb3b1-8935-4044-8efe-6c7619f0d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346024459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3346024459
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.381357973
Short name T136
Test name
Test status
Simulation time 142442558 ps
CPU time 1.2 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:18 PM PDT 24
Peak memory 215372 kb
Host smart-2173c2fb-43c6-45c8-a609-17872e541c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381357973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.381357973
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1262893108
Short name T807
Test name
Test status
Simulation time 24347480 ps
CPU time 0.92 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:19 PM PDT 24
Peak memory 206328 kb
Host smart-79c5c0c3-511b-4a7c-b432-4c5faa66f8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262893108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1262893108
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2494191877
Short name T175
Test name
Test status
Simulation time 17214764 ps
CPU time 0.86 seconds
Started May 28 02:11:20 PM PDT 24
Finished May 28 02:11:23 PM PDT 24
Peak memory 216056 kb
Host smart-bd1e5741-1a26-454c-88d7-f2f946ebb427
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494191877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2494191877
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2536218771
Short name T851
Test name
Test status
Simulation time 76882852 ps
CPU time 1.02 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 217864 kb
Host smart-d957878e-3ab5-47d4-aea6-a2383bfbde98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536218771 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2536218771
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.3675332067
Short name T459
Test name
Test status
Simulation time 25361345 ps
CPU time 1.29 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 223468 kb
Host smart-1559309d-514e-4f6e-9501-7af2f2b85a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675332067 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.3675332067
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3689473634
Short name T157
Test name
Test status
Simulation time 545003657 ps
CPU time 5.3 seconds
Started May 28 02:11:06 PM PDT 24
Finished May 28 02:11:15 PM PDT 24
Peak memory 219624 kb
Host smart-d81790b3-1bfa-4310-89af-d47dfb89a52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689473634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3689473634
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3499697920
Short name T34
Test name
Test status
Simulation time 19856826 ps
CPU time 1.1 seconds
Started May 28 02:11:24 PM PDT 24
Finished May 28 02:11:26 PM PDT 24
Peak memory 215632 kb
Host smart-5f2cb813-86d5-4d41-aa68-ffdca40dcdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499697920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3499697920
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3447986714
Short name T23
Test name
Test status
Simulation time 18170562 ps
CPU time 1.03 seconds
Started May 28 02:11:08 PM PDT 24
Finished May 28 02:11:12 PM PDT 24
Peak memory 215020 kb
Host smart-ad1724ce-90d2-4fc0-ae5c-d6a6b1850516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447986714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3447986714
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2662110434
Short name T763
Test name
Test status
Simulation time 541638289 ps
CPU time 5.69 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 215008 kb
Host smart-0b8fef13-cf34-4e81-abf7-afbd3c4e4ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662110434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2662110434
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3700877156
Short name T356
Test name
Test status
Simulation time 38686713952 ps
CPU time 248.51 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:15:30 PM PDT 24
Peak memory 217636 kb
Host smart-8a35729d-ea7b-4734-94f3-2cb72771044a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700877156 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3700877156
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1064230637
Short name T704
Test name
Test status
Simulation time 87894748 ps
CPU time 1.22 seconds
Started May 28 02:12:59 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 216772 kb
Host smart-29658575-cbcf-4419-ad73-367bbf4ea963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064230637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1064230637
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3038192749
Short name T431
Test name
Test status
Simulation time 82152809 ps
CPU time 1.2 seconds
Started May 28 02:13:05 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 216712 kb
Host smart-d4280b09-22f5-46c2-bfe0-6e1db3fc2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038192749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3038192749
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1711649644
Short name T570
Test name
Test status
Simulation time 142621776 ps
CPU time 1.59 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:13 PM PDT 24
Peak memory 218152 kb
Host smart-36ad6dc8-ca56-4fa5-8177-e20b86429140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711649644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1711649644
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1149641592
Short name T280
Test name
Test status
Simulation time 38933959 ps
CPU time 1.43 seconds
Started May 28 02:13:00 PM PDT 24
Finished May 28 02:13:04 PM PDT 24
Peak memory 218004 kb
Host smart-e0d560aa-1ebc-42a3-ad0c-e2b1b2f17e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149641592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1149641592
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.594805602
Short name T739
Test name
Test status
Simulation time 63551032 ps
CPU time 1.19 seconds
Started May 28 02:13:06 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 218132 kb
Host smart-e137a273-2a9b-4441-b957-1c2803f35867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594805602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.594805602
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3191926654
Short name T93
Test name
Test status
Simulation time 58952329 ps
CPU time 1.35 seconds
Started May 28 02:13:07 PM PDT 24
Finished May 28 02:13:10 PM PDT 24
Peak memory 216816 kb
Host smart-b763e95b-c03d-4c15-8111-a2e71d7b7f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191926654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3191926654
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4198660924
Short name T82
Test name
Test status
Simulation time 49207436 ps
CPU time 1.35 seconds
Started May 28 02:13:01 PM PDT 24
Finished May 28 02:13:04 PM PDT 24
Peak memory 217880 kb
Host smart-88f993ab-8d66-45ff-8ab5-21cb9ccf8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198660924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4198660924
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2187756546
Short name T816
Test name
Test status
Simulation time 44542578 ps
CPU time 1.25 seconds
Started May 28 02:12:58 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 216784 kb
Host smart-e6322a33-a1d4-4d98-889d-61cc0d05198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187756546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2187756546
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2210426807
Short name T346
Test name
Test status
Simulation time 65448115 ps
CPU time 2.02 seconds
Started May 28 02:13:08 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 219188 kb
Host smart-30dba905-405a-480c-988a-0ebd3710c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210426807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2210426807
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3393965683
Short name T327
Test name
Test status
Simulation time 28454402 ps
CPU time 1.29 seconds
Started May 28 02:12:59 PM PDT 24
Finished May 28 02:13:02 PM PDT 24
Peak memory 219476 kb
Host smart-5816d4fb-75a7-4a9b-a9dc-1276924fc156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393965683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3393965683
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.3858940606
Short name T479
Test name
Test status
Simulation time 43764856 ps
CPU time 1.2 seconds
Started May 28 02:11:14 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 215416 kb
Host smart-3cf4f95b-c342-476a-8116-e02b40940f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858940606 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3858940606
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2259628306
Short name T303
Test name
Test status
Simulation time 49134143 ps
CPU time 0.85 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:18 PM PDT 24
Peak memory 206184 kb
Host smart-e14c908e-ec91-4065-8545-66687560b24f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259628306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2259628306
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1143055842
Short name T773
Test name
Test status
Simulation time 59470014 ps
CPU time 1.12 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:19 PM PDT 24
Peak memory 219296 kb
Host smart-0e19f7f1-8478-4ce2-a69f-427a8ded0b5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143055842 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1143055842
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.785877443
Short name T454
Test name
Test status
Simulation time 24074069 ps
CPU time 1 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:19 PM PDT 24
Peak memory 218320 kb
Host smart-ce549b2e-3a83-42ed-beac-28512ad32ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785877443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.785877443
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.938525801
Short name T827
Test name
Test status
Simulation time 46886079 ps
CPU time 1.64 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 218240 kb
Host smart-c14c8b44-893e-4fd7-a304-5a39ab937379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938525801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.938525801
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1714760706
Short name T524
Test name
Test status
Simulation time 26699430 ps
CPU time 0.96 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:11:18 PM PDT 24
Peak memory 215084 kb
Host smart-e88b5496-e533-4b2a-a7b4-b7436cec881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714760706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1714760706
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3837749906
Short name T505
Test name
Test status
Simulation time 21938828 ps
CPU time 0.88 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 214972 kb
Host smart-7af4c794-af9c-4aa7-9df4-bb56ec950ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837749906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3837749906
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1668899953
Short name T581
Test name
Test status
Simulation time 535747580 ps
CPU time 5.73 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 216652 kb
Host smart-9b991ab5-a3da-40e2-a4e8-32fb803896cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668899953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1668899953
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1147000665
Short name T195
Test name
Test status
Simulation time 71253555871 ps
CPU time 1837.47 seconds
Started May 28 02:11:16 PM PDT 24
Finished May 28 02:41:56 PM PDT 24
Peak memory 227036 kb
Host smart-3471cc7a-5d5c-46f4-abb8-c9c620f34d64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147000665 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1147000665
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3160584511
Short name T282
Test name
Test status
Simulation time 39950588 ps
CPU time 1.43 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:11 PM PDT 24
Peak memory 217000 kb
Host smart-917469ed-d6b3-4ac1-940c-21435605021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160584511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3160584511
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3824521348
Short name T366
Test name
Test status
Simulation time 51826701 ps
CPU time 1.45 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 218256 kb
Host smart-e938f8a1-5f56-4743-b978-5dc8d7df7aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824521348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3824521348
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.3829508662
Short name T460
Test name
Test status
Simulation time 146734561 ps
CPU time 3.2 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:13 PM PDT 24
Peak memory 218104 kb
Host smart-a1bd3324-093f-499a-b9b7-b2b0424074aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829508662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.3829508662
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3944728108
Short name T469
Test name
Test status
Simulation time 43364430 ps
CPU time 1.18 seconds
Started May 28 02:13:07 PM PDT 24
Finished May 28 02:13:09 PM PDT 24
Peak memory 219000 kb
Host smart-68d0ebba-135c-4f82-87f3-88e30d357bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944728108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3944728108
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2479008521
Short name T819
Test name
Test status
Simulation time 40524835 ps
CPU time 1.3 seconds
Started May 28 02:13:04 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 219440 kb
Host smart-706aa559-6496-4943-a444-81b26bab38f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479008521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2479008521
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.31087090
Short name T73
Test name
Test status
Simulation time 52474724 ps
CPU time 1.02 seconds
Started May 28 02:13:07 PM PDT 24
Finished May 28 02:13:09 PM PDT 24
Peak memory 216712 kb
Host smart-03bdca74-cbbf-492d-9714-31ef92d20347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31087090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.31087090
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4149275545
Short name T703
Test name
Test status
Simulation time 106166294 ps
CPU time 1.83 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:13 PM PDT 24
Peak memory 218348 kb
Host smart-c05372c4-2354-4b0f-952e-7a6077c2c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149275545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4149275545
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2248836325
Short name T800
Test name
Test status
Simulation time 53603809 ps
CPU time 1.8 seconds
Started May 28 02:12:59 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 218060 kb
Host smart-73340c16-e71f-4445-b94b-9e80ef739de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248836325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2248836325
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3501457761
Short name T717
Test name
Test status
Simulation time 153806374 ps
CPU time 1.37 seconds
Started May 28 02:13:07 PM PDT 24
Finished May 28 02:13:09 PM PDT 24
Peak memory 219448 kb
Host smart-5886f82f-59af-4728-b2ee-e39f5c2258bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501457761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3501457761
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3829857459
Short name T771
Test name
Test status
Simulation time 43818964 ps
CPU time 1.31 seconds
Started May 28 02:13:03 PM PDT 24
Finished May 28 02:13:06 PM PDT 24
Peak memory 217992 kb
Host smart-e5b5f589-18b3-4ce8-a3ab-173b20ddb3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829857459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3829857459
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.4099519270
Short name T188
Test name
Test status
Simulation time 94537436 ps
CPU time 1.24 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 215424 kb
Host smart-e57db89a-bea1-4b46-847d-7416d1d31978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099519270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.4099519270
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2499135594
Short name T628
Test name
Test status
Simulation time 121054166 ps
CPU time 0.96 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 214548 kb
Host smart-96ce91cc-166f-4903-a16d-e0f38b339aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499135594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2499135594
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2055691049
Short name T541
Test name
Test status
Simulation time 19811956 ps
CPU time 0.87 seconds
Started May 28 02:11:20 PM PDT 24
Finished May 28 02:11:23 PM PDT 24
Peak memory 215812 kb
Host smart-d6f028ce-919c-4a86-ad64-e36a1050ebd9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055691049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2055691049
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3362046163
Short name T166
Test name
Test status
Simulation time 90483719 ps
CPU time 1.05 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 216408 kb
Host smart-3250261c-b173-46b2-8ff5-44a10fcbe7e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362046163 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3362046163
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.765108076
Short name T102
Test name
Test status
Simulation time 25097542 ps
CPU time 1.23 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:21 PM PDT 24
Peak memory 220288 kb
Host smart-c963edc0-2e14-41c7-ae4c-3f0c29014e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765108076 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.765108076
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3910567875
Short name T689
Test name
Test status
Simulation time 34407714 ps
CPU time 1.3 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 216644 kb
Host smart-e72cd5ef-5363-4f31-bed3-c66c6abcc5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910567875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3910567875
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1424625790
Short name T156
Test name
Test status
Simulation time 36268552 ps
CPU time 0.88 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 214976 kb
Host smart-bddc3163-6548-4479-bd51-7f3bd32fddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424625790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1424625790
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1035637402
Short name T416
Test name
Test status
Simulation time 49401514 ps
CPU time 0.96 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:11:17 PM PDT 24
Peak memory 206716 kb
Host smart-e1011c04-55ec-4e4d-b3e2-477acbf10c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035637402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1035637402
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3135936229
Short name T641
Test name
Test status
Simulation time 296244629 ps
CPU time 5.44 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 218008 kb
Host smart-7dea1c71-50b8-41cb-b59a-066ec9b82097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135936229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3135936229
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.374480257
Short name T530
Test name
Test status
Simulation time 123556548311 ps
CPU time 1371.84 seconds
Started May 28 02:11:15 PM PDT 24
Finished May 28 02:34:08 PM PDT 24
Peak memory 222556 kb
Host smart-e656af7b-df43-4202-9d01-0b8ba4169357
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374480257 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.374480257
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.80723541
Short name T678
Test name
Test status
Simulation time 65350164 ps
CPU time 1.06 seconds
Started May 28 02:12:57 PM PDT 24
Finished May 28 02:13:01 PM PDT 24
Peak memory 216808 kb
Host smart-350e8e15-a2e7-4679-84ab-c3ee1b80dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80723541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.80723541
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3946439076
Short name T829
Test name
Test status
Simulation time 27262750 ps
CPU time 1.44 seconds
Started May 28 02:13:00 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 217980 kb
Host smart-714ffd5d-1507-413a-a4df-622929d35fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946439076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3946439076
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3590620148
Short name T572
Test name
Test status
Simulation time 33275679 ps
CPU time 1.32 seconds
Started May 28 02:13:10 PM PDT 24
Finished May 28 02:13:13 PM PDT 24
Peak memory 215108 kb
Host smart-31388a36-acb4-401b-9335-167a1f05a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590620148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3590620148
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3717775178
Short name T654
Test name
Test status
Simulation time 41274699 ps
CPU time 1.42 seconds
Started May 28 02:13:00 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 217988 kb
Host smart-3f731d6e-2565-4704-86af-af8cd24fc203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717775178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3717775178
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.123864388
Short name T345
Test name
Test status
Simulation time 121221940 ps
CPU time 1.4 seconds
Started May 28 02:13:08 PM PDT 24
Finished May 28 02:13:10 PM PDT 24
Peak memory 216928 kb
Host smart-345f8667-fb35-4186-90a3-a83aea1a64a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123864388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.123864388
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2500123183
Short name T426
Test name
Test status
Simulation time 65926774 ps
CPU time 1.15 seconds
Started May 28 02:13:00 PM PDT 24
Finished May 28 02:13:03 PM PDT 24
Peak memory 219392 kb
Host smart-565935c0-dcb1-4558-99e4-ebe1568fa213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500123183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2500123183
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.186323136
Short name T549
Test name
Test status
Simulation time 52821271 ps
CPU time 1.76 seconds
Started May 28 02:13:07 PM PDT 24
Finished May 28 02:13:10 PM PDT 24
Peak memory 218096 kb
Host smart-21fb337d-119a-4b6d-b281-dd265ecbfa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186323136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.186323136
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3731210224
Short name T657
Test name
Test status
Simulation time 96545861 ps
CPU time 1.19 seconds
Started May 28 02:13:06 PM PDT 24
Finished May 28 02:13:08 PM PDT 24
Peak memory 216724 kb
Host smart-a3330fcc-69ce-445e-9ef3-c5b0888ae330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731210224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3731210224
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2066544743
Short name T611
Test name
Test status
Simulation time 39344628 ps
CPU time 1.52 seconds
Started May 28 02:13:09 PM PDT 24
Finished May 28 02:13:12 PM PDT 24
Peak memory 218516 kb
Host smart-8569293f-2108-4d46-aa84-1b9dd6fc0966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066544743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2066544743
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1269940200
Short name T154
Test name
Test status
Simulation time 46844631 ps
CPU time 1.23 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 215428 kb
Host smart-46ca7efb-a442-447e-9339-0027f7266013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269940200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1269940200
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1220160341
Short name T331
Test name
Test status
Simulation time 11133225 ps
CPU time 0.9 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:21 PM PDT 24
Peak memory 206556 kb
Host smart-71c0d7eb-038b-419f-ad86-d5cf92eab4f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220160341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1220160341
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_err.350739710
Short name T151
Test name
Test status
Simulation time 34432537 ps
CPU time 0.88 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 217824 kb
Host smart-b5ca7519-ac69-41cf-a3ed-1dad0e3abbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350739710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.350739710
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.456122482
Short name T824
Test name
Test status
Simulation time 101099637 ps
CPU time 1.42 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:21 PM PDT 24
Peak memory 218392 kb
Host smart-b7f60779-78ea-46ec-b3bf-a24119424765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456122482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.456122482
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1351666066
Short name T561
Test name
Test status
Simulation time 27342091 ps
CPU time 0.92 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:21 PM PDT 24
Peak memory 215340 kb
Host smart-aac3a9fc-de1b-41af-ae0d-89b719d280c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351666066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1351666066
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.30182457
Short name T318
Test name
Test status
Simulation time 66759782 ps
CPU time 0.95 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 215044 kb
Host smart-6e5e1c4e-cab8-44e0-9a63-d3f5a5d79e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30182457 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.30182457
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.254999159
Short name T741
Test name
Test status
Simulation time 290490455 ps
CPU time 5.12 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:25 PM PDT 24
Peak memory 219632 kb
Host smart-25c3db3a-c359-43ae-9d79-b52dae27c797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254999159 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.254999159
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2798436153
Short name T69
Test name
Test status
Simulation time 212196498845 ps
CPU time 1415.97 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:34:55 PM PDT 24
Peak memory 223564 kb
Host smart-734d0de8-c1f3-4b11-9a31-bcd8123ae74d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798436153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2798436153
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.3293672414
Short name T313
Test name
Test status
Simulation time 34728368 ps
CPU time 1.32 seconds
Started May 28 02:13:14 PM PDT 24
Finished May 28 02:13:17 PM PDT 24
Peak memory 216552 kb
Host smart-42536e24-0d35-4457-a01a-da3a2c3afe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293672414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3293672414
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3498323382
Short name T430
Test name
Test status
Simulation time 257937970 ps
CPU time 3.72 seconds
Started May 28 02:13:14 PM PDT 24
Finished May 28 02:13:18 PM PDT 24
Peak memory 219532 kb
Host smart-f4fe7159-b4a4-4493-81e2-3b62405ca4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498323382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3498323382
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2454722882
Short name T629
Test name
Test status
Simulation time 130206905 ps
CPU time 1.55 seconds
Started May 28 02:13:15 PM PDT 24
Finished May 28 02:13:18 PM PDT 24
Peak memory 218084 kb
Host smart-565c3e39-7374-443c-83ea-a175a2cd0cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454722882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2454722882
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.667508391
Short name T308
Test name
Test status
Simulation time 32249525 ps
CPU time 1.25 seconds
Started May 28 02:13:16 PM PDT 24
Finished May 28 02:13:19 PM PDT 24
Peak memory 216468 kb
Host smart-740bb879-319e-4296-8bf7-775c2e15c380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667508391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.667508391
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.682526387
Short name T367
Test name
Test status
Simulation time 68475745 ps
CPU time 1.3 seconds
Started May 28 02:13:16 PM PDT 24
Finished May 28 02:13:19 PM PDT 24
Peak memory 217840 kb
Host smart-5fd69710-7f0e-401b-b343-1d67de38044d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682526387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.682526387
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3691196513
Short name T512
Test name
Test status
Simulation time 91571190 ps
CPU time 1.07 seconds
Started May 28 02:13:16 PM PDT 24
Finished May 28 02:13:18 PM PDT 24
Peak memory 216836 kb
Host smart-e4ce37af-2f64-4cd9-8163-a73b2dc2b025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691196513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3691196513
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1961279147
Short name T293
Test name
Test status
Simulation time 37515110 ps
CPU time 1.13 seconds
Started May 28 02:13:16 PM PDT 24
Finished May 28 02:13:19 PM PDT 24
Peak memory 217892 kb
Host smart-7f0409e4-644c-46f3-adf8-56665a1fc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961279147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1961279147
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1261431377
Short name T269
Test name
Test status
Simulation time 69664281 ps
CPU time 1.33 seconds
Started May 28 02:13:20 PM PDT 24
Finished May 28 02:13:23 PM PDT 24
Peak memory 218536 kb
Host smart-47f9ded4-6c2c-45a4-9f15-9e9e228ef01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261431377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1261431377
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3944810491
Short name T815
Test name
Test status
Simulation time 153476121 ps
CPU time 1.36 seconds
Started May 28 02:13:15 PM PDT 24
Finished May 28 02:13:18 PM PDT 24
Peak memory 217972 kb
Host smart-82ec9419-0600-4888-9ba8-d24318ed9fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944810491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3944810491
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1490462846
Short name T84
Test name
Test status
Simulation time 93344441 ps
CPU time 1.22 seconds
Started May 28 02:10:11 PM PDT 24
Finished May 28 02:10:14 PM PDT 24
Peak memory 215412 kb
Host smart-0e20c9d2-c455-4b75-8bec-bb749b155044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490462846 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1490462846
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2160766418
Short name T644
Test name
Test status
Simulation time 36248444 ps
CPU time 0.83 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 206156 kb
Host smart-7fe7f7b5-d7e3-4630-912a-dbf9b0057e19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160766418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2160766418
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3560630230
Short name T752
Test name
Test status
Simulation time 34771550 ps
CPU time 0.83 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:10:12 PM PDT 24
Peak memory 215200 kb
Host smart-24310f08-b10c-4912-8bc5-bb906d98fce0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560630230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3560630230
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2825223681
Short name T105
Test name
Test status
Simulation time 111873593 ps
CPU time 1.21 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 219056 kb
Host smart-7e90cb58-e4e3-40d1-8292-e36fc2d86011
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825223681 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2825223681
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.3812193800
Short name T639
Test name
Test status
Simulation time 18840174 ps
CPU time 1.1 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 218892 kb
Host smart-40eacc4d-e3a5-449d-ba21-25bd2e9f3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812193800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3812193800
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2202745020
Short name T686
Test name
Test status
Simulation time 86712022 ps
CPU time 1.41 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 216912 kb
Host smart-2adc7b0a-4a70-41c6-8358-f124fd6e2e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202745020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2202745020
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2397939937
Short name T36
Test name
Test status
Simulation time 29099260 ps
CPU time 0.84 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 215256 kb
Host smart-521612fe-201a-47ae-8e0c-7efdbb4740c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397939937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2397939937
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1735221585
Short name T258
Test name
Test status
Simulation time 43208298 ps
CPU time 0.95 seconds
Started May 28 02:10:10 PM PDT 24
Finished May 28 02:10:14 PM PDT 24
Peak memory 206800 kb
Host smart-b965e894-1008-4a7a-81b8-fa69f4ff62de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735221585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1735221585
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.115899629
Short name T59
Test name
Test status
Simulation time 594741464 ps
CPU time 5.1 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:14 PM PDT 24
Peak memory 235288 kb
Host smart-185e816d-74f2-4826-b587-d5216249ba67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115899629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.115899629
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1293560798
Short name T496
Test name
Test status
Simulation time 52764492 ps
CPU time 0.92 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:09 PM PDT 24
Peak memory 215040 kb
Host smart-c54c145d-77bb-4f53-a1a1-55a4ce740cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293560798 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1293560798
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3542568317
Short name T281
Test name
Test status
Simulation time 239685263 ps
CPU time 3.44 seconds
Started May 28 02:10:06 PM PDT 24
Finished May 28 02:10:12 PM PDT 24
Peak memory 216660 kb
Host smart-95dcde34-ded0-4176-be66-bf548a74f5e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542568317 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3542568317
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3730055729
Short name T198
Test name
Test status
Simulation time 319661843522 ps
CPU time 2937.09 seconds
Started May 28 02:10:08 PM PDT 24
Finished May 28 02:59:08 PM PDT 24
Peak memory 229568 kb
Host smart-1369011c-e185-49a4-98b6-8d6c21853fa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730055729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3730055729
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2507579589
Short name T263
Test name
Test status
Simulation time 103553340 ps
CPU time 1.23 seconds
Started May 28 02:11:20 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 215364 kb
Host smart-3f996228-cbcf-47ee-85c2-1657c0f25e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507579589 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2507579589
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1525091039
Short name T316
Test name
Test status
Simulation time 96171661 ps
CPU time 0.9 seconds
Started May 28 02:11:22 PM PDT 24
Finished May 28 02:11:25 PM PDT 24
Peak memory 206176 kb
Host smart-04c4d4a2-44ea-49e7-ab6f-d304bbed0cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525091039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1525091039
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4159607792
Short name T124
Test name
Test status
Simulation time 10752190 ps
CPU time 0.87 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 215180 kb
Host smart-dd8f4c49-59dd-42b1-9def-e700315edfa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159607792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4159607792
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2735438511
Short name T645
Test name
Test status
Simulation time 37213885 ps
CPU time 1.33 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:34 PM PDT 24
Peak memory 217864 kb
Host smart-ea6df16b-c528-4a61-a1c2-4e0c2a932a81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735438511 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2735438511
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.469823542
Short name T802
Test name
Test status
Simulation time 19811019 ps
CPU time 1.2 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:31 PM PDT 24
Peak memory 223456 kb
Host smart-c1b165eb-abcf-47ba-99f7-7e20ce5b2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469823542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.469823542
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.349176204
Short name T691
Test name
Test status
Simulation time 52504366 ps
CPU time 1.21 seconds
Started May 28 02:11:20 PM PDT 24
Finished May 28 02:11:23 PM PDT 24
Peak memory 216584 kb
Host smart-9759bbc3-8c0e-46e5-9875-602c32ab681f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349176204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.349176204
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1182726424
Short name T652
Test name
Test status
Simulation time 20627342 ps
CPU time 1.16 seconds
Started May 28 02:11:24 PM PDT 24
Finished May 28 02:11:26 PM PDT 24
Peak memory 215304 kb
Host smart-0118a7fc-6b2e-4fd3-91d3-394e9bd59b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182726424 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1182726424
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3337685230
Short name T767
Test name
Test status
Simulation time 79341479 ps
CPU time 0.97 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:23 PM PDT 24
Peak memory 214972 kb
Host smart-f2316663-0436-4635-b84d-c89398a80b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337685230 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3337685230
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3400250057
Short name T306
Test name
Test status
Simulation time 168315444 ps
CPU time 2.25 seconds
Started May 28 02:11:20 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 216640 kb
Host smart-07ab81fd-4314-4a12-a477-9950a26c7727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400250057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3400250057
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2697366955
Short name T61
Test name
Test status
Simulation time 19810821386 ps
CPU time 253.49 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:15:34 PM PDT 24
Peak memory 217284 kb
Host smart-58ff3f60-b647-4e01-9309-989b9fcbe994
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697366955 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2697366955
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1704569473
Short name T515
Test name
Test status
Simulation time 26758791 ps
CPU time 1.23 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 215388 kb
Host smart-3f1626ca-8f64-4fb4-ad3a-8ac734b510d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704569473 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1704569473
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3710741081
Short name T753
Test name
Test status
Simulation time 15738516 ps
CPU time 0.89 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:11:21 PM PDT 24
Peak memory 214532 kb
Host smart-d650ce56-2d0d-4be8-a415-0bfb85b8edaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710741081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3710741081
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.627983081
Short name T142
Test name
Test status
Simulation time 41347533 ps
CPU time 0.88 seconds
Started May 28 02:11:21 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 216080 kb
Host smart-600d46c7-a9ca-4f46-93be-4dfd360828c3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627983081 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.627983081
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2427616496
Short name T111
Test name
Test status
Simulation time 36902641 ps
CPU time 1.32 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:33 PM PDT 24
Peak memory 219100 kb
Host smart-df8a651a-d4a9-415f-b47b-024c48451aee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427616496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2427616496
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4051145182
Short name T559
Test name
Test status
Simulation time 25099184 ps
CPU time 0.95 seconds
Started May 28 02:11:22 PM PDT 24
Finished May 28 02:11:24 PM PDT 24
Peak memory 219368 kb
Host smart-8089b201-1ff6-43b9-98d6-bc1e1d6f75f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051145182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4051145182
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2649909849
Short name T736
Test name
Test status
Simulation time 93193806 ps
CPU time 1.31 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:32 PM PDT 24
Peak memory 218160 kb
Host smart-c4a144a7-1543-47db-a58d-6029f3819e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649909849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2649909849
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2396301380
Short name T452
Test name
Test status
Simulation time 23117927 ps
CPU time 0.89 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:31 PM PDT 24
Peak memory 215380 kb
Host smart-e2f3c231-d95b-4e29-987c-06b9ddf52553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396301380 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2396301380
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2497007027
Short name T420
Test name
Test status
Simulation time 21833449 ps
CPU time 1.08 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:34 PM PDT 24
Peak memory 215000 kb
Host smart-83f3b6f6-7bac-4683-a206-36036f824524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497007027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2497007027
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1091518866
Short name T314
Test name
Test status
Simulation time 288010462 ps
CPU time 6.08 seconds
Started May 28 02:11:21 PM PDT 24
Finished May 28 02:11:29 PM PDT 24
Peak memory 215092 kb
Host smart-f2e6d225-a3fc-4ab5-a5a9-dffbaa41abb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091518866 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1091518866
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3392314005
Short name T458
Test name
Test status
Simulation time 35076641627 ps
CPU time 787.98 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:24:40 PM PDT 24
Peak memory 217024 kb
Host smart-733ee11b-6f8c-4663-8039-9265e3b44552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392314005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3392314005
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.176745475
Short name T429
Test name
Test status
Simulation time 31989623 ps
CPU time 1.37 seconds
Started May 28 02:11:24 PM PDT 24
Finished May 28 02:11:27 PM PDT 24
Peak memory 215424 kb
Host smart-e87c403d-26f7-42dc-a69a-5fbb7b7989b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176745475 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.176745475
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2496939161
Short name T399
Test name
Test status
Simulation time 18272437 ps
CPU time 1.03 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 214880 kb
Host smart-4339b2ce-d056-4ea5-9d5d-9f43d305ff57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496939161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2496939161
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.477276395
Short name T189
Test name
Test status
Simulation time 23296445 ps
CPU time 0.86 seconds
Started May 28 02:11:24 PM PDT 24
Finished May 28 02:11:26 PM PDT 24
Peak memory 216092 kb
Host smart-1448c94b-d4bc-4cf3-bd4b-3be7b534b1fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477276395 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.477276395
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2779996379
Short name T117
Test name
Test status
Simulation time 47895164 ps
CPU time 1.47 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:32 PM PDT 24
Peak memory 216664 kb
Host smart-ae302513-4dcc-49ff-afcc-4f00de1c80f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779996379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2779996379
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.732431204
Short name T137
Test name
Test status
Simulation time 25972928 ps
CPU time 1.13 seconds
Started May 28 02:11:17 PM PDT 24
Finished May 28 02:11:20 PM PDT 24
Peak memory 223500 kb
Host smart-0cb79334-62bd-4701-8c2d-1623300d50eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732431204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.732431204
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3907242391
Short name T567
Test name
Test status
Simulation time 33034688 ps
CPU time 1.46 seconds
Started May 28 02:11:23 PM PDT 24
Finished May 28 02:11:26 PM PDT 24
Peak memory 218008 kb
Host smart-cbecec09-9f7f-408f-a515-5d2bea7fbc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907242391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3907242391
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3536814784
Short name T613
Test name
Test status
Simulation time 40465326 ps
CPU time 0.96 seconds
Started May 28 02:11:19 PM PDT 24
Finished May 28 02:11:22 PM PDT 24
Peak memory 223496 kb
Host smart-c1f93a2b-3da1-44bb-9bad-c39d65172bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536814784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3536814784
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.284324610
Short name T651
Test name
Test status
Simulation time 89057023 ps
CPU time 0.97 seconds
Started May 28 02:11:23 PM PDT 24
Finished May 28 02:11:25 PM PDT 24
Peak memory 215024 kb
Host smart-ed242802-c297-48a6-b01a-1e48d4c0432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284324610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.284324610
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.4020290605
Short name T369
Test name
Test status
Simulation time 640497811 ps
CPU time 4.05 seconds
Started May 28 02:11:24 PM PDT 24
Finished May 28 02:11:29 PM PDT 24
Peak memory 215040 kb
Host smart-cb1d6cba-151d-427e-84fb-1a9582a533bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020290605 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.4020290605
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2527834293
Short name T757
Test name
Test status
Simulation time 31532532718 ps
CPU time 714.2 seconds
Started May 28 02:11:18 PM PDT 24
Finished May 28 02:23:15 PM PDT 24
Peak memory 219652 kb
Host smart-5247050a-5eeb-4dfc-8c3f-7fc2b95f93e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527834293 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2527834293
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4292829903
Short name T260
Test name
Test status
Simulation time 24823700 ps
CPU time 1.28 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:11:38 PM PDT 24
Peak memory 215424 kb
Host smart-cd46b531-a524-45c4-b229-d900e9915f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292829903 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4292829903
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2249819774
Short name T818
Test name
Test status
Simulation time 45871102 ps
CPU time 0.83 seconds
Started May 28 02:11:26 PM PDT 24
Finished May 28 02:11:28 PM PDT 24
Peak memory 206312 kb
Host smart-ac819c34-208f-461b-a44e-fc540fe07c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249819774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2249819774
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.235045361
Short name T171
Test name
Test status
Simulation time 19684052 ps
CPU time 0.87 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 216180 kb
Host smart-b35aeee7-3e4f-479b-95f2-6e8ac6aca007
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235045361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.235045361
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.2948345440
Short name T321
Test name
Test status
Simulation time 27268542 ps
CPU time 0.84 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 217916 kb
Host smart-1aa13947-063b-428a-ae01-b5ff8e5e99bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948345440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2948345440
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1657072763
Short name T627
Test name
Test status
Simulation time 71407248 ps
CPU time 1.3 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 218196 kb
Host smart-c5361f1c-2254-4041-be45-b56bbe63fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657072763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1657072763
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1613871711
Short name T560
Test name
Test status
Simulation time 39631644 ps
CPU time 1.02 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 223644 kb
Host smart-729b2f4b-9145-4faf-ab43-ec2e26f63038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613871711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1613871711
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4265345496
Short name T342
Test name
Test status
Simulation time 126009521 ps
CPU time 0.91 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:34 PM PDT 24
Peak memory 214996 kb
Host smart-dfc076fc-2e6a-4106-b0f2-74b0cd600849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265345496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4265345496
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.10790835
Short name T506
Test name
Test status
Simulation time 151833096 ps
CPU time 2.09 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:11:38 PM PDT 24
Peak memory 215008 kb
Host smart-6fb6e4fc-290e-4ef1-a534-1783bb8747a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790835 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.10790835
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3534546376
Short name T844
Test name
Test status
Simulation time 534123575122 ps
CPU time 1415.89 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:35:11 PM PDT 24
Peak memory 224856 kb
Host smart-76182c16-97e1-48b3-b914-b3278bb15f30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534546376 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3534546376
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1856975427
Short name T740
Test name
Test status
Simulation time 28101348 ps
CPU time 1.27 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:31 PM PDT 24
Peak memory 215416 kb
Host smart-42282639-c15f-4081-b241-27e1214f7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856975427 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1856975427
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1802818955
Short name T554
Test name
Test status
Simulation time 23640791 ps
CPU time 0.9 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:29 PM PDT 24
Peak memory 206216 kb
Host smart-7e0fab52-084c-4072-a81c-40bb207e8be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802818955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1802818955
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2711644780
Short name T427
Test name
Test status
Simulation time 20570167 ps
CPU time 0.92 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:34 PM PDT 24
Peak memory 215224 kb
Host smart-7ca13158-1395-41eb-b202-5384a70a8ca7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711644780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2711644780
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2285843470
Short name T539
Test name
Test status
Simulation time 109515270 ps
CPU time 1.17 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:31 PM PDT 24
Peak memory 218184 kb
Host smart-e0c6bf7c-b26e-4668-bf11-74a483037666
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285843470 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2285843470
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3430852462
Short name T349
Test name
Test status
Simulation time 21548894 ps
CPU time 0.92 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 218096 kb
Host smart-91502eeb-c85b-4b6c-98ae-b3597cb21980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430852462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3430852462
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3209246305
Short name T266
Test name
Test status
Simulation time 135255735 ps
CPU time 2.17 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:30 PM PDT 24
Peak memory 219476 kb
Host smart-db0a3686-1790-4885-899c-9d63c06cd80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209246305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3209246305
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.1454819099
Short name T685
Test name
Test status
Simulation time 21449472 ps
CPU time 0.94 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:31 PM PDT 24
Peak memory 215028 kb
Host smart-11899006-9dd0-4222-b63d-47c00fd5550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454819099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1454819099
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1014701642
Short name T540
Test name
Test status
Simulation time 328439313 ps
CPU time 6.33 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:39 PM PDT 24
Peak memory 215036 kb
Host smart-5b0ef44b-4c1c-4e88-98c3-5e5e5940487e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014701642 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1014701642
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.4162066541
Short name T197
Test name
Test status
Simulation time 35733912365 ps
CPU time 210.33 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:15:07 PM PDT 24
Peak memory 223152 kb
Host smart-9ed6aac4-b5b8-4831-8611-5f0d24ed9ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162066541 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.4162066541
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.93768198
Short name T499
Test name
Test status
Simulation time 13292668 ps
CPU time 0.93 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:34 PM PDT 24
Peak memory 206316 kb
Host smart-92f566fa-0d0b-4373-9aa4-2da544c96f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93768198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.93768198
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2418666568
Short name T708
Test name
Test status
Simulation time 20944928 ps
CPU time 0.93 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:11:37 PM PDT 24
Peak memory 215680 kb
Host smart-d6a7b11b-e097-4868-9b88-e1737b8374a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418666568 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2418666568
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2746560952
Short name T121
Test name
Test status
Simulation time 35730653 ps
CPU time 1.1 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 216744 kb
Host smart-c44514ff-8a41-4589-8373-b0df8873bec3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746560952 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2746560952
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.928549761
Short name T615
Test name
Test status
Simulation time 21242832 ps
CPU time 1.11 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 219640 kb
Host smart-73e90f42-5f5c-4530-8caf-26c812c9b193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928549761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.928549761
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.992190777
Short name T478
Test name
Test status
Simulation time 89741756 ps
CPU time 1.34 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:30 PM PDT 24
Peak memory 218168 kb
Host smart-5299b124-1bbe-4ab9-b57a-9ebbec4c22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992190777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.992190777
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_smoke.3103187228
Short name T759
Test name
Test status
Simulation time 128057791 ps
CPU time 0.94 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 214972 kb
Host smart-f923047d-190f-4f57-a742-869e9a3777aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103187228 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3103187228
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1274606499
Short name T566
Test name
Test status
Simulation time 569251463 ps
CPU time 6.16 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:38 PM PDT 24
Peak memory 217928 kb
Host smart-0058895b-eef5-43e4-8b62-4668452fe313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274606499 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1274606499
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3092765663
Short name T199
Test name
Test status
Simulation time 50205605809 ps
CPU time 1125.77 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:30:22 PM PDT 24
Peak memory 218596 kb
Host smart-b4334812-992a-499e-adfe-49df1897bf5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092765663 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3092765663
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3701608023
Short name T368
Test name
Test status
Simulation time 102566464 ps
CPU time 1.29 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:36 PM PDT 24
Peak memory 215416 kb
Host smart-e8c57669-6c74-4c67-b6e0-335893ab41a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701608023 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3701608023
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.488306597
Short name T335
Test name
Test status
Simulation time 17843387 ps
CPU time 0.98 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:35 PM PDT 24
Peak memory 206312 kb
Host smart-9dfd3417-a4ea-41fc-a02a-d387636c6ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488306597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.488306597
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.50592528
Short name T103
Test name
Test status
Simulation time 214405226 ps
CPU time 1.21 seconds
Started May 28 02:11:27 PM PDT 24
Finished May 28 02:11:32 PM PDT 24
Peak memory 217952 kb
Host smart-3f175669-f485-4025-9731-451e29541214
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50592528 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_dis
able_auto_req_mode.50592528
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.366968644
Short name T185
Test name
Test status
Simulation time 86787379 ps
CPU time 1.1 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:11:37 PM PDT 24
Peak memory 219004 kb
Host smart-c169da7b-f833-40aa-ae58-7bcc2f5babac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366968644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.366968644
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1703454056
Short name T451
Test name
Test status
Simulation time 29019868 ps
CPU time 1.21 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:33 PM PDT 24
Peak memory 216568 kb
Host smart-9d775b34-17d0-4395-ac99-65c2e46c0ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703454056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1703454056
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2834617149
Short name T782
Test name
Test status
Simulation time 21329184 ps
CPU time 1.14 seconds
Started May 28 02:11:31 PM PDT 24
Finished May 28 02:11:37 PM PDT 24
Peak memory 215344 kb
Host smart-2ad2c4af-d25f-4856-a69b-4ed1d96454fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834617149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2834617149
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2843469119
Short name T622
Test name
Test status
Simulation time 17140787 ps
CPU time 0.98 seconds
Started May 28 02:11:28 PM PDT 24
Finished May 28 02:11:33 PM PDT 24
Peak memory 215028 kb
Host smart-31915498-f5b2-432e-9b64-942f664a680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843469119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2843469119
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.717914407
Short name T788
Test name
Test status
Simulation time 109245192 ps
CPU time 2.73 seconds
Started May 28 02:11:29 PM PDT 24
Finished May 28 02:11:37 PM PDT 24
Peak memory 214916 kb
Host smart-e5262b88-1a5a-442e-b4bd-9f21a7db08d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717914407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.717914407
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3305229316
Short name T481
Test name
Test status
Simulation time 26827377244 ps
CPU time 593.84 seconds
Started May 28 02:11:30 PM PDT 24
Finished May 28 02:21:29 PM PDT 24
Peak memory 223408 kb
Host smart-6791e685-a7b5-4733-8b51-d9f86b2e3c70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305229316 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3305229316
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1980058437
Short name T10
Test name
Test status
Simulation time 81968630 ps
CPU time 1.25 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 215420 kb
Host smart-40e82526-ecb8-4bea-b51e-51788ab45ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980058437 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1980058437
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3240875564
Short name T377
Test name
Test status
Simulation time 29449064 ps
CPU time 0.93 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 214552 kb
Host smart-8b52c594-5e9e-47f3-a903-cb69c8de4603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240875564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3240875564
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.4252328314
Short name T833
Test name
Test status
Simulation time 56544703 ps
CPU time 0.87 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:53 PM PDT 24
Peak memory 215260 kb
Host smart-a272106a-d8af-434c-a880-63f2cefd3bb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252328314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.4252328314
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.111954148
Short name T21
Test name
Test status
Simulation time 41159500 ps
CPU time 1.13 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 217936 kb
Host smart-aecf2466-9e89-4d1b-acae-39f328fcfdb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111954148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.111954148
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2788112306
Short name T435
Test name
Test status
Simulation time 18658741 ps
CPU time 1 seconds
Started May 28 02:11:45 PM PDT 24
Finished May 28 02:11:48 PM PDT 24
Peak memory 218240 kb
Host smart-268a0280-b522-47fa-aace-8add49456859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788112306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2788112306
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2824950745
Short name T85
Test name
Test status
Simulation time 69485773 ps
CPU time 1.62 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 218272 kb
Host smart-4172ac0a-3061-44c3-a15d-b2bac1754bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824950745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2824950745
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.4131401392
Short name T548
Test name
Test status
Simulation time 21097553 ps
CPU time 1.12 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 02:11:44 PM PDT 24
Peak memory 215336 kb
Host smart-9c2ada16-4d43-4731-8831-4a0f3cf6a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131401392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4131401392
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1755918828
Short name T376
Test name
Test status
Simulation time 35229663 ps
CPU time 0.98 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 215044 kb
Host smart-d3bb4b12-5de4-4888-8045-8ed9d37e31b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755918828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1755918828
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2576663668
Short name T744
Test name
Test status
Simulation time 580632077 ps
CPU time 3.67 seconds
Started May 28 02:11:41 PM PDT 24
Finished May 28 02:11:47 PM PDT 24
Peak memory 216504 kb
Host smart-77f3a389-bafe-4b87-9b97-1f0f0d69fb0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576663668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2576663668
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2140882958
Short name T202
Test name
Test status
Simulation time 48807382528 ps
CPU time 1033.98 seconds
Started May 28 02:11:41 PM PDT 24
Finished May 28 02:28:57 PM PDT 24
Peak memory 218516 kb
Host smart-3cb0f26d-cde1-46e8-a335-89658899f685
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140882958 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2140882958
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3906801175
Short name T76
Test name
Test status
Simulation time 80783356 ps
CPU time 1.24 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:47 PM PDT 24
Peak memory 215416 kb
Host smart-c90e2e70-010a-4088-ae7d-951003881ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906801175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3906801175
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2737256898
Short name T319
Test name
Test status
Simulation time 47064876 ps
CPU time 0.88 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 02:11:44 PM PDT 24
Peak memory 214520 kb
Host smart-c5f22d11-7644-4dbb-8a2e-c5eacad63137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737256898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2737256898
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3762443625
Short name T139
Test name
Test status
Simulation time 19692871 ps
CPU time 0.85 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 216096 kb
Host smart-bda914de-d913-4f7f-b952-53f36e90b74c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762443625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3762443625
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1792801171
Short name T104
Test name
Test status
Simulation time 101196465 ps
CPU time 1.13 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:45 PM PDT 24
Peak memory 216664 kb
Host smart-e8ca1105-3702-4219-a45d-4287322be790
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792801171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1792801171
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_genbits.719638803
Short name T796
Test name
Test status
Simulation time 126025123 ps
CPU time 1.1 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 02:11:44 PM PDT 24
Peak memory 216708 kb
Host smart-5cde7959-6bcb-4188-bd03-12411013f729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719638803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.719638803
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.391509661
Short name T508
Test name
Test status
Simulation time 22693440 ps
CPU time 1.09 seconds
Started May 28 02:11:46 PM PDT 24
Finished May 28 02:11:48 PM PDT 24
Peak memory 215124 kb
Host smart-9d1aca52-a20e-441e-8cf9-7d69c7496b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391509661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.391509661
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1019309702
Short name T811
Test name
Test status
Simulation time 16302867 ps
CPU time 0.99 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:45 PM PDT 24
Peak memory 215032 kb
Host smart-a91ad71e-10b7-486b-bb33-fd3518ab0f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019309702 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1019309702
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2917987520
Short name T659
Test name
Test status
Simulation time 347798911 ps
CPU time 2.52 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215096 kb
Host smart-d03551ce-de9b-4c01-8c23-700d030571b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917987520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2917987520
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1727026098
Short name T5
Test name
Test status
Simulation time 56282763727 ps
CPU time 1286.81 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:33:24 PM PDT 24
Peak memory 220276 kb
Host smart-47348f3a-cd71-471b-a883-6e7c224e82dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727026098 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1727026098
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.548860993
Short name T134
Test name
Test status
Simulation time 23246186 ps
CPU time 1.13 seconds
Started May 28 02:11:49 PM PDT 24
Finished May 28 02:11:51 PM PDT 24
Peak memory 215420 kb
Host smart-a48c2d8f-90be-46d9-aaa9-33313b4186cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548860993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.548860993
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3411184519
Short name T477
Test name
Test status
Simulation time 17680655 ps
CPU time 0.97 seconds
Started May 28 02:11:45 PM PDT 24
Finished May 28 02:11:47 PM PDT 24
Peak memory 214500 kb
Host smart-adfb2fc2-13cf-4794-ae9c-7af20b4873f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411184519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3411184519
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.342919580
Short name T149
Test name
Test status
Simulation time 82838208 ps
CPU time 0.88 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:54 PM PDT 24
Peak memory 216048 kb
Host smart-df8a4336-896d-482a-b8b3-642c52023de7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342919580 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.342919580
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2042282327
Short name T783
Test name
Test status
Simulation time 102940388 ps
CPU time 1.12 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 216832 kb
Host smart-9e3ff0d9-da65-4722-9059-ce1fc1a09b5a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042282327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2042282327
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2174048595
Short name T54
Test name
Test status
Simulation time 29032783 ps
CPU time 1.34 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 225096 kb
Host smart-47ad6972-a906-467b-8778-7663aeab7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174048595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2174048595
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2216686575
Short name T756
Test name
Test status
Simulation time 93294452 ps
CPU time 1.17 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 216764 kb
Host smart-43a472c4-bf61-433c-a372-3655f79e9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216686575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2216686575
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2352304271
Short name T417
Test name
Test status
Simulation time 80570957 ps
CPU time 0.86 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:53 PM PDT 24
Peak memory 215208 kb
Host smart-9fb6149f-aed1-4098-a54b-5d152d59ca26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352304271 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2352304271
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.224145903
Short name T339
Test name
Test status
Simulation time 21092471 ps
CPU time 0.98 seconds
Started May 28 02:11:49 PM PDT 24
Finished May 28 02:11:51 PM PDT 24
Peak memory 215024 kb
Host smart-b81f785b-cadb-4076-8284-1b8a2ee0722b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224145903 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.224145903
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2218677799
Short name T209
Test name
Test status
Simulation time 326358392 ps
CPU time 2.99 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 216676 kb
Host smart-4d40095c-a5e2-41ef-bed5-b09e05a46cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218677799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2218677799
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1974457294
Short name T672
Test name
Test status
Simulation time 98589180479 ps
CPU time 1320.61 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:34:02 PM PDT 24
Peak memory 225160 kb
Host smart-93f2abc5-2fea-4259-a2ae-fef44acaaaa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974457294 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1974457294
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.119215534
Short name T256
Test name
Test status
Simulation time 72565368 ps
CPU time 1.22 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 215428 kb
Host smart-b872fe65-47dd-402a-a697-dd9e6693c50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119215534 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.119215534
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3266601538
Short name T466
Test name
Test status
Simulation time 20196676 ps
CPU time 1.04 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 214544 kb
Host smart-751d7f1a-cf82-4055-ab0a-09fc680fd5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266601538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3266601538
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3041394391
Short name T141
Test name
Test status
Simulation time 29422678 ps
CPU time 0.88 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 216228 kb
Host smart-89b413c2-7be1-41e0-adf6-1805d219942c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041394391 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3041394391
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3382120260
Short name T100
Test name
Test status
Simulation time 40428741 ps
CPU time 1.18 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 216692 kb
Host smart-b41711c4-23f0-45cd-a707-3c6e25024945
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382120260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3382120260
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1385363204
Short name T418
Test name
Test status
Simulation time 44691716 ps
CPU time 1.05 seconds
Started May 28 02:10:12 PM PDT 24
Finished May 28 02:10:14 PM PDT 24
Peak memory 223504 kb
Host smart-54ac4b34-4bf1-44f4-8c36-06b354c93664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385363204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1385363204
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.203581094
Short name T798
Test name
Test status
Simulation time 51214467 ps
CPU time 1.38 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 216792 kb
Host smart-b56f3771-30fe-47ec-b3f5-7891a7c196fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203581094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.203581094
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3151771533
Short name T428
Test name
Test status
Simulation time 22531433 ps
CPU time 1.13 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 215236 kb
Host smart-531ef0bd-984d-4897-8769-42dd37a51a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151771533 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3151771533
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3737176291
Short name T26
Test name
Test status
Simulation time 139763447 ps
CPU time 0.94 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:13 PM PDT 24
Peak memory 206832 kb
Host smart-838e950a-c61a-46f5-8438-861aaf682cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737176291 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3737176291
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2927683364
Short name T60
Test name
Test status
Simulation time 231904763 ps
CPU time 4.59 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:10:17 PM PDT 24
Peak memory 239372 kb
Host smart-731c22c4-ac75-45dc-9cb6-a49afc0be76a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927683364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2927683364
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3638722988
Short name T840
Test name
Test status
Simulation time 24497102 ps
CPU time 0.94 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:11 PM PDT 24
Peak memory 215020 kb
Host smart-965f2663-b9c9-49eb-ab0c-68f9cb338288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638722988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3638722988
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.710131100
Short name T590
Test name
Test status
Simulation time 1438550914 ps
CPU time 2.29 seconds
Started May 28 02:10:11 PM PDT 24
Finished May 28 02:10:15 PM PDT 24
Peak memory 216716 kb
Host smart-eeca0248-d9d9-4caa-8090-dd9f0dde71f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710131100 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.710131100
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2942499841
Short name T277
Test name
Test status
Simulation time 40167717196 ps
CPU time 975.83 seconds
Started May 28 02:10:09 PM PDT 24
Finished May 28 02:26:28 PM PDT 24
Peak memory 218684 kb
Host smart-cfa5ba8b-ef94-49cf-879b-41df7fcd4b51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942499841 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2942499841
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.124865862
Short name T617
Test name
Test status
Simulation time 97151214 ps
CPU time 1.25 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 215404 kb
Host smart-d698441e-f51c-4ab1-89ee-4eeb293f5f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124865862 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.124865862
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3192127613
Short name T730
Test name
Test status
Simulation time 109235447 ps
CPU time 0.85 seconds
Started May 28 02:11:50 PM PDT 24
Finished May 28 02:11:52 PM PDT 24
Peak memory 206116 kb
Host smart-9d84421e-4755-42a1-9532-3ed9d6be7a31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192127613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3192127613
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3864912283
Short name T181
Test name
Test status
Simulation time 14652800 ps
CPU time 0.94 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 216328 kb
Host smart-8d213afc-53f9-4e56-8d5a-aa9f19b56ba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864912283 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3864912283
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2765411718
Short name T599
Test name
Test status
Simulation time 33637075 ps
CPU time 1.06 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 216584 kb
Host smart-6ffd75ef-9692-46cd-8ff4-1c9b423416a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765411718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2765411718
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1153273534
Short name T152
Test name
Test status
Simulation time 20167822 ps
CPU time 1.05 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 218168 kb
Host smart-8b9a875a-9457-4144-bba1-3bd90460db1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153273534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1153273534
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.705341743
Short name T635
Test name
Test status
Simulation time 61422980 ps
CPU time 1.87 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 219800 kb
Host smart-90edac65-8d8d-4317-9446-ea489cab035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705341743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.705341743
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1203766612
Short name T32
Test name
Test status
Simulation time 31643117 ps
CPU time 0.84 seconds
Started May 28 02:11:41 PM PDT 24
Finished May 28 02:11:44 PM PDT 24
Peak memory 215204 kb
Host smart-33ab21e6-5b54-4928-8b82-9c3057e02fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203766612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1203766612
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.196235279
Short name T463
Test name
Test status
Simulation time 45576374 ps
CPU time 0.94 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 215288 kb
Host smart-e6ae18d1-e40c-46cc-9477-03221f07a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196235279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.196235279
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2592447991
Short name T755
Test name
Test status
Simulation time 257476412 ps
CPU time 4.57 seconds
Started May 28 02:11:50 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 218108 kb
Host smart-c9e1149a-1a82-4b15-8ed0-d346ecd0370d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592447991 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2592447991
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1968356920
Short name T161
Test name
Test status
Simulation time 487587143987 ps
CPU time 3046.21 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 03:02:30 PM PDT 24
Peak memory 234868 kb
Host smart-83b99047-64f1-46b2-9957-b28392dd0d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968356920 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1968356920
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1217903181
Short name T747
Test name
Test status
Simulation time 44081958 ps
CPU time 1.13 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 214788 kb
Host smart-582d52ad-f8ed-4a82-8a1b-e9e93260831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217903181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1217903181
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1634757479
Short name T793
Test name
Test status
Simulation time 16536808 ps
CPU time 0.97 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 02:11:44 PM PDT 24
Peak memory 206344 kb
Host smart-ce0980d9-b53f-4122-95d3-3ade776b2670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634757479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1634757479
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3157167949
Short name T126
Test name
Test status
Simulation time 40197540 ps
CPU time 0.88 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 215244 kb
Host smart-1b68ae85-d4c3-4e17-8011-f97233459e2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157167949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3157167949
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3459834149
Short name T184
Test name
Test status
Simulation time 36341103 ps
CPU time 1.31 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 216748 kb
Host smart-3b253ae0-d39f-4c20-a97a-140d2f07e62a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459834149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3459834149
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.584517001
Short name T363
Test name
Test status
Simulation time 19343083 ps
CPU time 1.12 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 218072 kb
Host smart-1dc75e8f-0b76-45d8-b2a8-b0d4844be354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584517001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.584517001
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.28203236
Short name T679
Test name
Test status
Simulation time 53656637 ps
CPU time 1.27 seconds
Started May 28 02:11:43 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 215028 kb
Host smart-9b4cf79b-eec5-4d93-adba-74c669e15964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28203236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.28203236
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4128127433
Short name T164
Test name
Test status
Simulation time 55157826 ps
CPU time 0.84 seconds
Started May 28 02:11:44 PM PDT 24
Finished May 28 02:11:46 PM PDT 24
Peak memory 215468 kb
Host smart-0e000af1-9831-4127-90a3-7d5fff982048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128127433 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4128127433
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3233115454
Short name T695
Test name
Test status
Simulation time 17122458 ps
CPU time 0.97 seconds
Started May 28 02:11:49 PM PDT 24
Finished May 28 02:11:51 PM PDT 24
Peak memory 214976 kb
Host smart-d5a14440-c158-40a1-9670-991d50ff8cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233115454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3233115454
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3781193163
Short name T714
Test name
Test status
Simulation time 371049446 ps
CPU time 2.2 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 216640 kb
Host smart-31bf5d92-d981-450a-ac90-239c544375c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781193163 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3781193163
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1777713828
Short name T471
Test name
Test status
Simulation time 87088209813 ps
CPU time 2185.88 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 230192 kb
Host smart-4c158d98-2dfc-4df6-8bd4-d5ef4ad1ab59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777713828 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1777713828
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1654277405
Short name T261
Test name
Test status
Simulation time 37272643 ps
CPU time 1.12 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 215420 kb
Host smart-7a375353-0a40-48be-97cd-7b6da3744023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654277405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1654277405
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.64774208
Short name T509
Test name
Test status
Simulation time 31619329 ps
CPU time 0.93 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:57 PM PDT 24
Peak memory 206328 kb
Host smart-7fa897d6-04d0-45a7-87a3-1df1f63a51b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64774208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.64774208
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.4078625857
Short name T90
Test name
Test status
Simulation time 19681992 ps
CPU time 0.84 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:53 PM PDT 24
Peak memory 216040 kb
Host smart-aeca749c-c55a-4913-9f49-1a08bc84f998
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078625857 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4078625857
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3561251966
Short name T96
Test name
Test status
Simulation time 40769525 ps
CPU time 1.02 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:57 PM PDT 24
Peak memory 218008 kb
Host smart-aa8b4118-1777-4288-b7d6-e7d85a23374b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561251966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3561251966
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3867350383
Short name T97
Test name
Test status
Simulation time 65041014 ps
CPU time 1.11 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 228984 kb
Host smart-1e8b7fe1-374d-4a62-9af4-aca3d89b21f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867350383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3867350383
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3677003650
Short name T758
Test name
Test status
Simulation time 35051911 ps
CPU time 1.3 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 218016 kb
Host smart-dfe0456d-5bea-4bfc-b3be-f7f6e6071fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677003650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3677003650
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3973469018
Short name T159
Test name
Test status
Simulation time 36191332 ps
CPU time 0.87 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215300 kb
Host smart-ae5f3208-1334-4ccf-a077-d16fae14f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973469018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3973469018
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4179946177
Short name T332
Test name
Test status
Simulation time 28417792 ps
CPU time 0.92 seconds
Started May 28 02:11:42 PM PDT 24
Finished May 28 02:11:45 PM PDT 24
Peak memory 215036 kb
Host smart-c633aa79-ad76-4ffe-9b18-6d1ba396058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179946177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4179946177
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1847946090
Short name T68
Test name
Test status
Simulation time 1957013830 ps
CPU time 5.19 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 216816 kb
Host smart-95d103db-01a3-4aeb-be57-fd6913f98369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847946090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1847946090
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.443437433
Short name T445
Test name
Test status
Simulation time 189758142856 ps
CPU time 1441.45 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:36:02 PM PDT 24
Peak memory 225520 kb
Host smart-24f87b32-11fa-40be-bc89-d35d24872393
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443437433 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.443437433
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1706478195
Short name T163
Test name
Test status
Simulation time 31477271 ps
CPU time 1.33 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:57 PM PDT 24
Peak memory 215388 kb
Host smart-f21eb57a-31b5-44dd-bc92-00422c2db8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706478195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1706478195
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2514812291
Short name T414
Test name
Test status
Simulation time 54301634 ps
CPU time 0.82 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 206196 kb
Host smart-3610a206-fc4b-4737-8fe7-7bd4f783efff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514812291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2514812291
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4006745049
Short name T205
Test name
Test status
Simulation time 13028754 ps
CPU time 0.92 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 216028 kb
Host smart-b32cc0cc-3cfa-4257-8a51-8086b32ae0f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006745049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4006745049
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1434474855
Short name T801
Test name
Test status
Simulation time 180143068 ps
CPU time 1.13 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:56 PM PDT 24
Peak memory 216544 kb
Host smart-7510b2c1-8c07-4772-85e7-adcbf00bbc44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434474855 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1434474855
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.4092000629
Short name T150
Test name
Test status
Simulation time 23040481 ps
CPU time 0.93 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 218068 kb
Host smart-4e37168f-00c3-4905-a80a-f938b304a415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092000629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.4092000629
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1063955603
Short name T444
Test name
Test status
Simulation time 32611428 ps
CPU time 1.35 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 217936 kb
Host smart-74db35a9-2303-42a8-98c1-ce44ad4621fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063955603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1063955603
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2889223244
Short name T734
Test name
Test status
Simulation time 23765303 ps
CPU time 1.14 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 215340 kb
Host smart-791128a6-7838-4984-a1ba-68be8932ce45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889223244 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2889223244
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.416641145
Short name T74
Test name
Test status
Simulation time 40951960 ps
CPU time 0.91 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:56 PM PDT 24
Peak memory 215028 kb
Host smart-9b56b02c-c12e-4697-9d5b-5c2f111cc949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416641145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.416641145
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1748205978
Short name T336
Test name
Test status
Simulation time 244845572 ps
CPU time 2.82 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 214992 kb
Host smart-24ba1c94-03bc-4a00-b23f-700ea90fba06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748205978 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1748205978
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.4021983565
Short name T768
Test name
Test status
Simulation time 36020157505 ps
CPU time 902.94 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:26:57 PM PDT 24
Peak memory 219424 kb
Host smart-90859d87-621d-47b1-bb08-12cefc88ce69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021983565 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.4021983565
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2970147885
Short name T31
Test name
Test status
Simulation time 79732418 ps
CPU time 1.29 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215420 kb
Host smart-24a5de31-553d-4afc-8220-32bd0a9df04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970147885 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2970147885
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2551562751
Short name T826
Test name
Test status
Simulation time 70081266 ps
CPU time 1.04 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 206372 kb
Host smart-fa26a570-7433-4390-8164-eb96bf980f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551562751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2551562751
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3734693382
Short name T775
Test name
Test status
Simulation time 11282458 ps
CPU time 0.9 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:56 PM PDT 24
Peak memory 216244 kb
Host smart-7fa8c244-b835-4c82-ae86-bbaee9e7637a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734693382 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3734693382
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3545252325
Short name T411
Test name
Test status
Simulation time 45589708 ps
CPU time 1.14 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 218196 kb
Host smart-05c7d4af-c276-4e87-a3b8-0a773a16b054
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545252325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3545252325
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_genbits.383938657
Short name T474
Test name
Test status
Simulation time 55662911 ps
CPU time 1.44 seconds
Started May 28 02:11:51 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 219320 kb
Host smart-534a6ef6-f9ec-4f7d-957f-3a797d5cc2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383938657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.383938657
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.72607495
Short name T846
Test name
Test status
Simulation time 45135139 ps
CPU time 0.85 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 214904 kb
Host smart-c1bd5a21-3c8d-499c-9147-d7a6f0094199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72607495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.72607495
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1042458708
Short name T65
Test name
Test status
Simulation time 41639173 ps
CPU time 0.98 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215028 kb
Host smart-da22f095-b742-4327-bdce-2a507446e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042458708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1042458708
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2321273694
Short name T663
Test name
Test status
Simulation time 366178311 ps
CPU time 1.95 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 215016 kb
Host smart-9df16cb7-c1a5-43a3-88bc-d52d89c597fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321273694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2321273694
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1968121245
Short name T472
Test name
Test status
Simulation time 20263105182 ps
CPU time 463.44 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:19:45 PM PDT 24
Peak memory 223364 kb
Host smart-490d81f8-9bf9-459e-85cb-e0c7578714c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968121245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1968121245
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2626784953
Short name T774
Test name
Test status
Simulation time 50995902 ps
CPU time 1.23 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 215372 kb
Host smart-f13e4df3-61ef-4b36-90f4-9324611295ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626784953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2626784953
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.443309946
Short name T70
Test name
Test status
Simulation time 52765139 ps
CPU time 0.96 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 206360 kb
Host smart-fabec056-3fba-4262-a7f5-4549ccfcd8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443309946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.443309946
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.871101042
Short name T543
Test name
Test status
Simulation time 16733082 ps
CPU time 0.87 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 216032 kb
Host smart-1b92c606-37ff-4983-9251-7d30781ad4d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871101042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.871101042
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1689706384
Short name T110
Test name
Test status
Simulation time 66565162 ps
CPU time 1.2 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 219236 kb
Host smart-1d843fca-e509-4a47-8e1c-77ec04d9c656
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689706384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1689706384
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_genbits.4244858605
Short name T337
Test name
Test status
Simulation time 53119557 ps
CPU time 1.44 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 217892 kb
Host smart-95d266d1-6fe5-4ee6-adf0-577bf1185fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244858605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4244858605
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1554846546
Short name T636
Test name
Test status
Simulation time 24606007 ps
CPU time 1.21 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:56 PM PDT 24
Peak memory 223716 kb
Host smart-c7cc5915-69d3-48c7-82c3-f558e6955d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554846546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1554846546
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2982582581
Short name T658
Test name
Test status
Simulation time 14142914 ps
CPU time 0.97 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 215044 kb
Host smart-d8a419a4-872f-4306-afc7-d1762ef334dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982582581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2982582581
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.487854688
Short name T210
Test name
Test status
Simulation time 244201962 ps
CPU time 4.62 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 216664 kb
Host smart-b792282d-51d4-47e3-8e49-16e0f51fb55e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487854688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.487854688
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3935179613
Short name T485
Test name
Test status
Simulation time 166119994078 ps
CPU time 1020.51 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:29:03 PM PDT 24
Peak memory 221796 kb
Host smart-b200f87a-6ab5-42c1-8279-1d3164c87c3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935179613 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3935179613
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2582816821
Short name T521
Test name
Test status
Simulation time 97499773 ps
CPU time 1.3 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 215420 kb
Host smart-b225dbdb-8d76-4f6d-b086-1b5ebb34f5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582816821 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2582816821
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2878385549
Short name T309
Test name
Test status
Simulation time 17133975 ps
CPU time 0.95 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 206384 kb
Host smart-61f8511f-b293-47be-aa6c-c719f2e77ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878385549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2878385549
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.451313674
Short name T527
Test name
Test status
Simulation time 11890543 ps
CPU time 0.9 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 216028 kb
Host smart-6737a45f-f214-494f-8529-bb5d4100426a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451313674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.451313674
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3610013331
Short name T119
Test name
Test status
Simulation time 19845908 ps
CPU time 1.02 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 219024 kb
Host smart-5ed38693-62a5-489e-be09-fa6aeace80b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610013331 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3610013331
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3607146256
Short name T780
Test name
Test status
Simulation time 85534266 ps
CPU time 1.03 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:02 PM PDT 24
Peak memory 223352 kb
Host smart-aa86a47e-da6a-4a4c-af89-83d71f8c419c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607146256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3607146256
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2206452227
Short name T391
Test name
Test status
Simulation time 44570599 ps
CPU time 1.56 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:57 PM PDT 24
Peak memory 217992 kb
Host smart-fcfb94ad-f34a-494d-abd9-7785f731a2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206452227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2206452227
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1811093569
Short name T605
Test name
Test status
Simulation time 22032602 ps
CPU time 1.1 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 215352 kb
Host smart-2028e738-1b1f-4902-aa69-b677e82261f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811093569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1811093569
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3134995589
Short name T661
Test name
Test status
Simulation time 105933917 ps
CPU time 0.97 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:58 PM PDT 24
Peak memory 215028 kb
Host smart-b6d31c46-bf55-4c72-88aa-882e60d4a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134995589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3134995589
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2431967276
Short name T457
Test name
Test status
Simulation time 145327738 ps
CPU time 3.22 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 218800 kb
Host smart-eaa65f23-038b-46c2-8d25-85fa64452146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431967276 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2431967276
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4075304048
Short name T823
Test name
Test status
Simulation time 25251565408 ps
CPU time 679.49 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:23:19 PM PDT 24
Peak memory 217628 kb
Host smart-9e872a58-b210-467c-9264-ad8a414489f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075304048 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4075304048
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1374156052
Short name T153
Test name
Test status
Simulation time 37039919 ps
CPU time 1.16 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215428 kb
Host smart-41771afb-6ecf-45c2-bcbf-06d16f2eaf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374156052 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1374156052
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2265168531
Short name T600
Test name
Test status
Simulation time 28353608 ps
CPU time 0.98 seconds
Started May 28 02:11:57 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 214568 kb
Host smart-f92e9aa2-a929-4210-b879-5fb77088330a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265168531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2265168531
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.3509141816
Short name T809
Test name
Test status
Simulation time 11528407 ps
CPU time 0.92 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:11:55 PM PDT 24
Peak memory 216220 kb
Host smart-cf12451c-cc6e-4a63-824b-669702abcc42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509141816 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3509141816
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.1173962798
Short name T186
Test name
Test status
Simulation time 31828656 ps
CPU time 0.9 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 219140 kb
Host smart-f373b8e6-81b1-4659-99b0-ce0de47fe273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173962798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1173962798
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.945027243
Short name T80
Test name
Test status
Simulation time 95788985 ps
CPU time 1.5 seconds
Started May 28 02:11:54 PM PDT 24
Finished May 28 02:12:00 PM PDT 24
Peak memory 218324 kb
Host smart-8663177d-5ae7-43c0-afe6-94a29c810e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945027243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.945027243
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2584806611
Short name T529
Test name
Test status
Simulation time 25717176 ps
CPU time 1.08 seconds
Started May 28 02:11:55 PM PDT 24
Finished May 28 02:12:01 PM PDT 24
Peak memory 223704 kb
Host smart-d97104e1-23c2-46ab-86bb-d5d264dec103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584806611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2584806611
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1341362822
Short name T334
Test name
Test status
Simulation time 50600626 ps
CPU time 0.93 seconds
Started May 28 02:11:53 PM PDT 24
Finished May 28 02:11:59 PM PDT 24
Peak memory 215024 kb
Host smart-43afaf1b-fb9b-4fd1-ad34-cbe1ee15b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341362822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1341362822
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3596821190
Short name T832
Test name
Test status
Simulation time 77254364 ps
CPU time 2.04 seconds
Started May 28 02:11:56 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215036 kb
Host smart-13a5766f-3c01-4430-8187-63d5df9a13bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596821190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3596821190
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3200599839
Short name T710
Test name
Test status
Simulation time 265516719144 ps
CPU time 1427.77 seconds
Started May 28 02:11:52 PM PDT 24
Finished May 28 02:35:43 PM PDT 24
Peak memory 223028 kb
Host smart-e3efc2b9-fcd5-4aec-aa82-377110b3356f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200599839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3200599839
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2822660771
Short name T761
Test name
Test status
Simulation time 252424396 ps
CPU time 1.5 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 215420 kb
Host smart-251d6f3c-d215-4543-b972-340116bd8e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822660771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2822660771
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3940393918
Short name T839
Test name
Test status
Simulation time 16843616 ps
CPU time 0.94 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 206268 kb
Host smart-1d35d0c7-691d-48fd-9e21-1627325a72bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940393918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3940393918
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2664709037
Short name T192
Test name
Test status
Simulation time 34100128 ps
CPU time 0.84 seconds
Started May 28 02:12:03 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 216216 kb
Host smart-d4e522ff-2402-443f-a23a-2e4e8e071749
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664709037 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2664709037
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.4034737525
Short name T550
Test name
Test status
Simulation time 38002722 ps
CPU time 1.16 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 216536 kb
Host smart-9ba7537f-fff7-4bd6-a054-0148e36ba0f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034737525 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.4034737525
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.691107436
Short name T405
Test name
Test status
Simulation time 91446323 ps
CPU time 1.26 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 224952 kb
Host smart-fd5c43ca-ca43-4c50-90ff-8316533d3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691107436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.691107436
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1208042581
Short name T718
Test name
Test status
Simulation time 195567966 ps
CPU time 2.58 seconds
Started May 28 02:11:58 PM PDT 24
Finished May 28 02:12:05 PM PDT 24
Peak memory 219868 kb
Host smart-9afa5993-bd3d-43dc-a1ac-9fde32db5a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208042581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1208042581
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.623447498
Short name T39
Test name
Test status
Simulation time 21376793 ps
CPU time 1.14 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:08 PM PDT 24
Peak memory 215248 kb
Host smart-e0ccb684-faf8-44cf-9fa1-cffe8c580c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623447498 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.623447498
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1467329135
Short name T301
Test name
Test status
Simulation time 57670126 ps
CPU time 0.96 seconds
Started May 28 02:11:58 PM PDT 24
Finished May 28 02:12:03 PM PDT 24
Peak memory 215040 kb
Host smart-8dce98d6-5422-4d44-84ab-39e9a5413463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467329135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1467329135
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.517985548
Short name T491
Test name
Test status
Simulation time 122487201 ps
CPU time 1.16 seconds
Started May 28 02:12:08 PM PDT 24
Finished May 28 02:12:12 PM PDT 24
Peak memory 206284 kb
Host smart-73e47d52-9eff-4809-80e6-0be5286da7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517985548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.517985548
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1160406376
Short name T715
Test name
Test status
Simulation time 187195973634 ps
CPU time 1669.6 seconds
Started May 28 02:12:03 PM PDT 24
Finished May 28 02:39:55 PM PDT 24
Peak memory 227348 kb
Host smart-4bab2a83-2149-4c36-a8d3-9939764008d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160406376 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1160406376
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3348945181
Short name T817
Test name
Test status
Simulation time 27698098 ps
CPU time 1.27 seconds
Started May 28 02:12:03 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 215424 kb
Host smart-7d85493e-5dfe-4cf2-88fc-69efd5247814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348945181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3348945181
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.381159233
Short name T401
Test name
Test status
Simulation time 74112883 ps
CPU time 0.91 seconds
Started May 28 02:12:10 PM PDT 24
Finished May 28 02:12:12 PM PDT 24
Peak memory 206132 kb
Host smart-d1aad8c7-a6d9-474c-a1e2-9735ba0a60ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381159233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.381159233
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2647521646
Short name T568
Test name
Test status
Simulation time 68018289 ps
CPU time 0.85 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 215700 kb
Host smart-7e4ed52b-4d6c-410c-aa5a-e27dbe8627d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647521646 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2647521646
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3906962291
Short name T482
Test name
Test status
Simulation time 57652502 ps
CPU time 1.02 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 219392 kb
Host smart-51739293-33fa-4b65-9363-5d86ba2d1aa1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906962291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3906962291
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.4055263248
Short name T588
Test name
Test status
Simulation time 22108185 ps
CPU time 1.12 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 229016 kb
Host smart-211941b0-0d18-4c64-9b23-e8aa9039f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055263248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4055263248
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.929910230
Short name T392
Test name
Test status
Simulation time 109584935 ps
CPU time 1.65 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:08 PM PDT 24
Peak memory 218288 kb
Host smart-99c1feae-9749-46a7-bfd2-0274887dabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929910230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.929910230
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3492761510
Short name T436
Test name
Test status
Simulation time 60914525 ps
CPU time 0.84 seconds
Started May 28 02:12:09 PM PDT 24
Finished May 28 02:12:12 PM PDT 24
Peak memory 214960 kb
Host smart-8426302f-f58d-4110-ab0f-13611b24b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492761510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3492761510
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2075251938
Short name T490
Test name
Test status
Simulation time 26272427 ps
CPU time 0.98 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 215072 kb
Host smart-230a4357-9129-449a-8da8-25685605e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075251938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2075251938
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3161259257
Short name T58
Test name
Test status
Simulation time 600327376 ps
CPU time 3.96 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 216656 kb
Host smart-cdeb8db4-ae1a-4a1b-8783-b91dc820a620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161259257 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3161259257
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3343229131
Short name T533
Test name
Test status
Simulation time 173648691911 ps
CPU time 1110.75 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:30:39 PM PDT 24
Peak memory 221444 kb
Host smart-35747faf-0747-4586-930c-0c2a086c0e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343229131 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3343229131
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1646516508
Short name T607
Test name
Test status
Simulation time 49293738 ps
CPU time 1.23 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 215372 kb
Host smart-4c71c490-0721-4832-96ae-66b805913256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646516508 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1646516508
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1234327236
Short name T304
Test name
Test status
Simulation time 16171870 ps
CPU time 0.94 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 206356 kb
Host smart-2de208f0-5d2a-4117-abd2-8c676eed925a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234327236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1234327236
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.605248474
Short name T147
Test name
Test status
Simulation time 17277809 ps
CPU time 0.85 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 216216 kb
Host smart-529ff3a8-fb52-418d-99ef-d8165c83240e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605248474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.605248474
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2036378857
Short name T98
Test name
Test status
Simulation time 56207033 ps
CPU time 1.14 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 216252 kb
Host smart-8e05cf85-e709-4b92-a34b-f59d8577c6e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036378857 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2036378857
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.711006026
Short name T380
Test name
Test status
Simulation time 18978817 ps
CPU time 1.03 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 218136 kb
Host smart-95898c39-121d-4b33-bd9b-dbfd5cacd44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711006026 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.711006026
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.167461883
Short name T365
Test name
Test status
Simulation time 86344564 ps
CPU time 1.21 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 216852 kb
Host smart-026b91b4-8374-4c6a-b106-ab62cdba2b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167461883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.167461883
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1602539351
Short name T579
Test name
Test status
Simulation time 21248107 ps
CPU time 1.1 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:10:23 PM PDT 24
Peak memory 215440 kb
Host smart-a9b8b28b-f62c-4745-ab34-0f9c46eeb52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602539351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1602539351
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3357492402
Short name T254
Test name
Test status
Simulation time 48840939 ps
CPU time 0.94 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 206800 kb
Host smart-84bb0601-397e-43c6-b71f-4c8b11ff8245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357492402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3357492402
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1005200342
Short name T424
Test name
Test status
Simulation time 20803661 ps
CPU time 0.99 seconds
Started May 28 02:10:07 PM PDT 24
Finished May 28 02:10:10 PM PDT 24
Peak memory 215072 kb
Host smart-22bcab75-0367-48c9-bb8b-bb65a3718eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005200342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1005200342
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.418252722
Short name T440
Test name
Test status
Simulation time 154814508 ps
CPU time 3.67 seconds
Started May 28 02:10:17 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 216748 kb
Host smart-238aba45-e915-47c4-82f1-747ae02e6036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418252722 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.418252722
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2374327657
Short name T200
Test name
Test status
Simulation time 25207000643 ps
CPU time 256.88 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:14:39 PM PDT 24
Peak memory 217364 kb
Host smart-056712d6-efca-4383-92ca-74cbfaf16220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374327657 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2374327657
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.462504940
Short name T146
Test name
Test status
Simulation time 18301377 ps
CPU time 1.06 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 217952 kb
Host smart-15f65f33-209a-44ad-847a-8ae70b1eef5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462504940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.462504940
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1050154007
Short name T375
Test name
Test status
Simulation time 126027169 ps
CPU time 1.75 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 219744 kb
Host smart-da6313d5-d8bd-403d-94b3-495e1a5c83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050154007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1050154007
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3913005529
Short name T688
Test name
Test status
Simulation time 28723401 ps
CPU time 0.93 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 218144 kb
Host smart-dce728ec-117a-461d-bf30-343aef206bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913005529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3913005529
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.515157263
Short name T275
Test name
Test status
Simulation time 61942311 ps
CPU time 1.43 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 219540 kb
Host smart-fc10fc42-bd58-4baa-9243-88d70aba17b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515157263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.515157263
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.483353294
Short name T518
Test name
Test status
Simulation time 54168209 ps
CPU time 1.03 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 218016 kb
Host smart-f09546d1-7285-4cdc-8f07-2bcb496d04f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483353294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.483353294
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1702358562
Short name T299
Test name
Test status
Simulation time 43586549 ps
CPU time 1.21 seconds
Started May 28 02:12:07 PM PDT 24
Finished May 28 02:12:11 PM PDT 24
Peak memory 218940 kb
Host smart-f5f5d622-e9af-43f1-9e6a-6d443384f386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702358562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1702358562
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3839190859
Short name T170
Test name
Test status
Simulation time 25022084 ps
CPU time 1.03 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 218572 kb
Host smart-3e7be464-9dc7-48d7-8300-a214b65e7579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839190859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3839190859
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3293190839
Short name T278
Test name
Test status
Simulation time 105282793 ps
CPU time 1.47 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 218228 kb
Host smart-4908f664-4833-4e28-a326-1badf66f7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293190839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3293190839
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.460693367
Short name T123
Test name
Test status
Simulation time 19226000 ps
CPU time 1.21 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 223704 kb
Host smart-6b9d7edb-d84a-4218-b82a-6e783374c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460693367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.460693367
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.125126979
Short name T13
Test name
Test status
Simulation time 38682105 ps
CPU time 1.2 seconds
Started May 28 02:12:07 PM PDT 24
Finished May 28 02:12:11 PM PDT 24
Peak memory 217104 kb
Host smart-38e7c02b-651d-4bc5-aeeb-11a0ab709c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125126979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.125126979
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3896433639
Short name T138
Test name
Test status
Simulation time 20625535 ps
CPU time 1.21 seconds
Started May 28 02:12:07 PM PDT 24
Finished May 28 02:12:11 PM PDT 24
Peak memory 223468 kb
Host smart-cc6dfc6d-683e-40e5-92fe-4f72a8d82d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896433639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3896433639
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1287080308
Short name T848
Test name
Test status
Simulation time 58217914 ps
CPU time 1.19 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 218100 kb
Host smart-4c862c4d-63fb-48cd-aa8a-d607e179ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287080308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1287080308
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3424117078
Short name T113
Test name
Test status
Simulation time 61515662 ps
CPU time 1.34 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 220504 kb
Host smart-4ac25ee5-c79d-41e6-9f4d-c8d2e4540876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424117078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3424117078
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1501423781
Short name T776
Test name
Test status
Simulation time 64894408 ps
CPU time 1.25 seconds
Started May 28 02:12:10 PM PDT 24
Finished May 28 02:12:13 PM PDT 24
Peak memory 218008 kb
Host smart-1a8b1826-43a5-45bd-8a81-9da76a2b0f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501423781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1501423781
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3552879745
Short name T125
Test name
Test status
Simulation time 46286750 ps
CPU time 1.22 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 219252 kb
Host smart-8b71d7c6-bbf9-4ce1-9c02-edfa85d7230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552879745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3552879745
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2482795689
Short name T503
Test name
Test status
Simulation time 58806615 ps
CPU time 1.75 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 217996 kb
Host smart-cbe4d94a-4ac3-42f3-8325-64133d51bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482795689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2482795689
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2623634608
Short name T183
Test name
Test status
Simulation time 179289687 ps
CPU time 1.35 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 219216 kb
Host smart-6bc808c9-d493-4fa2-9791-2f202faf6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623634608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2623634608
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.404059315
Short name T323
Test name
Test status
Simulation time 49433446 ps
CPU time 1.4 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 218952 kb
Host smart-8f84f28c-aa5e-4e51-9e40-8fa3311958c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404059315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.404059315
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3307716269
Short name T75
Test name
Test status
Simulation time 22369815 ps
CPU time 0.94 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 217812 kb
Host smart-860d1efa-cf10-41da-b44e-b66e9a5a17bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307716269 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3307716269
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1741905309
Short name T371
Test name
Test status
Simulation time 25179125 ps
CPU time 1.15 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 215028 kb
Host smart-12fd4cf4-372e-4a82-a7d8-afb2732c4614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741905309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1741905309
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.1735118654
Short name T398
Test name
Test status
Simulation time 20521326 ps
CPU time 1 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 213992 kb
Host smart-a9d10f0d-9944-43e4-a545-75f191e2abaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735118654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1735118654
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.303134425
Short name T675
Test name
Test status
Simulation time 14579654 ps
CPU time 0.95 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 215388 kb
Host smart-ddbeb498-7687-48f4-9309-ae50f4ed928c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303134425 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.303134425
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1382398682
Short name T206
Test name
Test status
Simulation time 26771782 ps
CPU time 1.12 seconds
Started May 28 02:10:17 PM PDT 24
Finished May 28 02:10:19 PM PDT 24
Peak memory 217816 kb
Host smart-8a8b2a19-f633-4c5b-a04c-c638b8e44e05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382398682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1382398682
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3964727700
Short name T433
Test name
Test status
Simulation time 18380320 ps
CPU time 1.07 seconds
Started May 28 02:10:21 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 218300 kb
Host smart-09165f46-91bd-448d-8a2f-9862e04daade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964727700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3964727700
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3571605419
Short name T838
Test name
Test status
Simulation time 107527347 ps
CPU time 1.69 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 218216 kb
Host smart-9356f6ad-9477-477a-9386-d76c3c2ad36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571605419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3571605419
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.727911454
Short name T155
Test name
Test status
Simulation time 25077029 ps
CPU time 0.99 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 215072 kb
Host smart-c78aa861-8981-4b53-bedf-66419ef8a684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727911454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.727911454
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1392879433
Short name T255
Test name
Test status
Simulation time 16681094 ps
CPU time 1.04 seconds
Started May 28 02:10:25 PM PDT 24
Finished May 28 02:10:26 PM PDT 24
Peak memory 206840 kb
Host smart-eb28a1eb-5e0e-400a-9c77-c4b7a8d9a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392879433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1392879433
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2729491542
Short name T810
Test name
Test status
Simulation time 75641908 ps
CPU time 1.03 seconds
Started May 28 02:10:21 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 215060 kb
Host smart-55eca84f-c358-48d7-9746-d2f9fb90dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729491542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2729491542
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2422805088
Short name T841
Test name
Test status
Simulation time 95062319 ps
CPU time 2.28 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:10:25 PM PDT 24
Peak memory 216812 kb
Host smart-7e8a0998-f3e0-4127-b134-b52c66c35d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422805088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2422805088
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4129752695
Short name T532
Test name
Test status
Simulation time 54661152655 ps
CPU time 1526.65 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:35:49 PM PDT 24
Peak memory 224052 kb
Host smart-2215e875-9bc1-4c5a-82c3-7a6243121be8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129752695 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4129752695
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1333536753
Short name T602
Test name
Test status
Simulation time 30471446 ps
CPU time 0.89 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 218428 kb
Host smart-3a9fc550-e010-45f7-ada1-89a3fe3926c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333536753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1333536753
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.4011818801
Short name T441
Test name
Test status
Simulation time 81496501 ps
CPU time 1.12 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 216856 kb
Host smart-3ad7385d-8616-42a3-8c13-0c8b68a551ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011818801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.4011818801
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1784432265
Short name T145
Test name
Test status
Simulation time 29760504 ps
CPU time 0.97 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:13 PM PDT 24
Peak memory 223304 kb
Host smart-a1b256d3-2225-4939-8dc4-2e70251c3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784432265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1784432265
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1522533476
Short name T92
Test name
Test status
Simulation time 57913729 ps
CPU time 2.02 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 217864 kb
Host smart-c8a5a34b-fa4d-4b16-9b62-d9189b3c4aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522533476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1522533476
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.931803873
Short name T107
Test name
Test status
Simulation time 27135487 ps
CPU time 0.99 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:14 PM PDT 24
Peak memory 219288 kb
Host smart-56ee4d64-3665-42dc-8b10-ac227bae8ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931803873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.931803873
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2652259612
Short name T785
Test name
Test status
Simulation time 93862972 ps
CPU time 3.06 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:16 PM PDT 24
Peak memory 215052 kb
Host smart-aedfc98f-adaa-40d0-845c-cbda4b3651e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652259612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2652259612
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4107656172
Short name T558
Test name
Test status
Simulation time 83682204 ps
CPU time 0.98 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 218336 kb
Host smart-20236696-9480-431f-b081-db4808e0d317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107656172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4107656172
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.55218908
Short name T475
Test name
Test status
Simulation time 43832210 ps
CPU time 1.09 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:08 PM PDT 24
Peak memory 216796 kb
Host smart-f45efbf5-169a-47cc-99ae-49303cc96417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55218908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.55218908
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3063250458
Short name T825
Test name
Test status
Simulation time 20755740 ps
CPU time 0.95 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 218380 kb
Host smart-1b236e54-dc72-434e-98f4-22eff5e8d70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063250458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3063250458
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2231919158
Short name T536
Test name
Test status
Simulation time 979005635 ps
CPU time 7.72 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:21 PM PDT 24
Peak memory 218012 kb
Host smart-c8678dde-caea-4b91-95db-6598e4da5198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231919158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2231919158
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2958900386
Short name T3
Test name
Test status
Simulation time 22711490 ps
CPU time 1.05 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 223452 kb
Host smart-c894b0ce-5f07-4853-9b5e-c975cdbc1250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958900386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2958900386
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3070999577
Short name T737
Test name
Test status
Simulation time 102416216 ps
CPU time 2.4 seconds
Started May 28 02:12:11 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 219756 kb
Host smart-1cde9b17-a42f-4d0b-a08c-ea35755b834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070999577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3070999577
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.4243850223
Short name T51
Test name
Test status
Simulation time 75203682 ps
CPU time 0.97 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:08 PM PDT 24
Peak memory 223352 kb
Host smart-d5883c25-6e48-4c1e-a00a-7bb6613d3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243850223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4243850223
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3810790418
Short name T294
Test name
Test status
Simulation time 48009840 ps
CPU time 1.26 seconds
Started May 28 02:12:07 PM PDT 24
Finished May 28 02:12:12 PM PDT 24
Peak memory 219064 kb
Host smart-b1897237-f153-40a7-b04c-f461ae95df6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810790418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3810790418
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.92249793
Short name T122
Test name
Test status
Simulation time 57927686 ps
CPU time 1.16 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 225124 kb
Host smart-7a1dbe7b-d814-44a3-a67c-58191211c3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92249793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.92249793
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1121926594
Short name T289
Test name
Test status
Simulation time 111464329 ps
CPU time 2.61 seconds
Started May 28 02:12:01 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 219552 kb
Host smart-e36a1a33-2e2c-43d8-8bc7-b924943102cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121926594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1121926594
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1751217029
Short name T15
Test name
Test status
Simulation time 22911253 ps
CPU time 1.04 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:05 PM PDT 24
Peak memory 229072 kb
Host smart-bbe743e1-5c6d-41a4-89ad-748c0809d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751217029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1751217029
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2685891893
Short name T626
Test name
Test status
Simulation time 56539717 ps
CPU time 1.08 seconds
Started May 28 02:12:06 PM PDT 24
Finished May 28 02:12:10 PM PDT 24
Peak memory 219496 kb
Host smart-312727a1-d9db-44c4-a5ae-474c04edd8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685891893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2685891893
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3254686126
Short name T665
Test name
Test status
Simulation time 33445428 ps
CPU time 0.93 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 218312 kb
Host smart-df68c4d7-7c99-4ad1-924d-4d4d2698b9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254686126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3254686126
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4269655516
Short name T681
Test name
Test status
Simulation time 59518620 ps
CPU time 1.53 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 216876 kb
Host smart-7095aae7-6cff-4aa1-9903-10fd96a62c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269655516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4269655516
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.2698048702
Short name T131
Test name
Test status
Simulation time 24005353 ps
CPU time 1.24 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 215404 kb
Host smart-844b1b8e-1072-475a-a386-09a96b6224a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698048702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2698048702
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2524184595
Short name T71
Test name
Test status
Simulation time 13120146 ps
CPU time 0.9 seconds
Started May 28 02:10:22 PM PDT 24
Finished May 28 02:10:25 PM PDT 24
Peak memory 206352 kb
Host smart-5bf6152e-3366-450c-b1e9-c22dcb87975f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524184595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2524184595
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.976449905
Short name T182
Test name
Test status
Simulation time 44083826 ps
CPU time 0.87 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 216200 kb
Host smart-80bb00f4-3f5c-4bb3-9b41-00a18c9fca03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976449905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.976449905
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3373912274
Short name T504
Test name
Test status
Simulation time 98427572 ps
CPU time 1.15 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 218060 kb
Host smart-2057557a-4edf-4fe3-901d-2042c3ec48b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373912274 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3373912274
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2337834750
Short name T101
Test name
Test status
Simulation time 24570536 ps
CPU time 1.12 seconds
Started May 28 02:10:21 PM PDT 24
Finished May 28 02:10:24 PM PDT 24
Peak memory 219364 kb
Host smart-684f1c63-da06-4d62-aef7-d9d76cf9d20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337834750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2337834750
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_intr.3334951701
Short name T612
Test name
Test status
Simulation time 27555509 ps
CPU time 1 seconds
Started May 28 02:10:24 PM PDT 24
Finished May 28 02:10:26 PM PDT 24
Peak memory 215120 kb
Host smart-cd853dfb-9f60-4878-9572-4e7e170f9d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334951701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3334951701
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.3255511784
Short name T573
Test name
Test status
Simulation time 48877059 ps
CPU time 0.91 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 215040 kb
Host smart-262dab77-2e0c-429b-a9eb-f3db2d755b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255511784 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3255511784
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2918690355
Short name T168
Test name
Test status
Simulation time 288502234 ps
CPU time 0.97 seconds
Started May 28 02:10:22 PM PDT 24
Finished May 28 02:10:25 PM PDT 24
Peak memory 206244 kb
Host smart-d4b4f062-85e0-48b1-b6c0-d8ecfe7db7ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918690355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2918690355
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1571364245
Short name T577
Test name
Test status
Simulation time 50524892982 ps
CPU time 1292.85 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:31:55 PM PDT 24
Peak memory 223448 kb
Host smart-5a97b8a5-951e-44d5-8bf3-2a61d2b38ae5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571364245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1571364245
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1054192955
Short name T55
Test name
Test status
Simulation time 22685838 ps
CPU time 1.33 seconds
Started May 28 02:12:09 PM PDT 24
Finished May 28 02:12:12 PM PDT 24
Peak memory 223540 kb
Host smart-b0a4b0c4-11f3-4767-99df-1cca8b18be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054192955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1054192955
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.4237816714
Short name T347
Test name
Test status
Simulation time 78155393 ps
CPU time 1.14 seconds
Started May 28 02:12:05 PM PDT 24
Finished May 28 02:12:09 PM PDT 24
Peak memory 215060 kb
Host smart-56558157-0ccb-4336-b402-298b5bb9d6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237816714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.4237816714
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1218058069
Short name T822
Test name
Test status
Simulation time 18985863 ps
CPU time 1.04 seconds
Started May 28 02:12:04 PM PDT 24
Finished May 28 02:12:07 PM PDT 24
Peak memory 218092 kb
Host smart-a493d3bf-5bf1-42c5-8674-ef18742b4a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218058069 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1218058069
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.4264582308
Short name T396
Test name
Test status
Simulation time 101006943 ps
CPU time 1.18 seconds
Started May 28 02:12:07 PM PDT 24
Finished May 28 02:12:11 PM PDT 24
Peak memory 219520 kb
Host smart-bae84b21-60cf-4a77-be7b-99ab4ca57033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264582308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.4264582308
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2433133547
Short name T140
Test name
Test status
Simulation time 29806052 ps
CPU time 0.84 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 217584 kb
Host smart-15b7c6d4-4b7a-437c-9c39-acfa827ca57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433133547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2433133547
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3265036442
Short name T820
Test name
Test status
Simulation time 253434588 ps
CPU time 1.36 seconds
Started May 28 02:12:02 PM PDT 24
Finished May 28 02:12:06 PM PDT 24
Peak memory 218304 kb
Host smart-b4b55a57-e19d-4992-ae0b-9620c9cecd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265036442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3265036442
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_genbits.2672169381
Short name T286
Test name
Test status
Simulation time 90671767 ps
CPU time 1.34 seconds
Started May 28 02:12:26 PM PDT 24
Finished May 28 02:12:29 PM PDT 24
Peak memory 219180 kb
Host smart-a4138814-2b5a-48d4-b234-63e61e2c34ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672169381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2672169381
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1038160374
Short name T86
Test name
Test status
Simulation time 142239052 ps
CPU time 1.04 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:27 PM PDT 24
Peak memory 220296 kb
Host smart-1a233385-6941-4def-928e-49d96283b2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038160374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1038160374
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.3417845872
Short name T408
Test name
Test status
Simulation time 42668086 ps
CPU time 1.57 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:27 PM PDT 24
Peak memory 217972 kb
Host smart-2cba4376-5903-4548-9e3e-5cbec01cc4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417845872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3417845872
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.159984061
Short name T38
Test name
Test status
Simulation time 18781599 ps
CPU time 1.11 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 218132 kb
Host smart-f43bb1de-ae8b-47b6-be53-8777b309b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159984061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.159984061
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2275521021
Short name T648
Test name
Test status
Simulation time 44587236 ps
CPU time 1.72 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218064 kb
Host smart-63fb390b-0c85-47f9-90f0-e087e16d0494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275521021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2275521021
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2405763420
Short name T845
Test name
Test status
Simulation time 22369316 ps
CPU time 0.99 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218536 kb
Host smart-57c51abc-4da0-4743-855b-f6b4a7ebbf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405763420 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2405763420
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3624723656
Short name T268
Test name
Test status
Simulation time 28747240 ps
CPU time 1.26 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 216828 kb
Host smart-b4987bab-0e36-4cea-9708-cd5ebdfd9858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624723656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3624723656
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3219843048
Short name T388
Test name
Test status
Simulation time 18788287 ps
CPU time 1.21 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:25 PM PDT 24
Peak memory 218008 kb
Host smart-2a545696-cdc3-4890-8464-ac2b8825a8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219843048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3219843048
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2946402941
Short name T525
Test name
Test status
Simulation time 47829072 ps
CPU time 1.11 seconds
Started May 28 02:12:21 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 216664 kb
Host smart-1941d66c-e981-4961-b51c-de37a91f9368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946402941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2946402941
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2605068230
Short name T361
Test name
Test status
Simulation time 26237883 ps
CPU time 1.24 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218284 kb
Host smart-952eb471-a2d8-44f4-8fee-844f0bde5b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605068230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2605068230
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.84218700
Short name T707
Test name
Test status
Simulation time 54329964 ps
CPU time 1.51 seconds
Started May 28 02:12:25 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218196 kb
Host smart-00affff9-3bf9-4106-96ad-44c3b3869bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84218700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.84218700
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.591915089
Short name T144
Test name
Test status
Simulation time 23690245 ps
CPU time 0.95 seconds
Started May 28 02:12:18 PM PDT 24
Finished May 28 02:12:19 PM PDT 24
Peak memory 217920 kb
Host smart-334cdf07-6689-43ed-b7c9-7a30d8385836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591915089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.591915089
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3252446890
Short name T324
Test name
Test status
Simulation time 136516404 ps
CPU time 1.03 seconds
Started May 28 02:12:21 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 216796 kb
Host smart-51794408-a567-4716-bc89-fb9d8dd5ea20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252446890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3252446890
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3155939558
Short name T638
Test name
Test status
Simulation time 75137251 ps
CPU time 1.15 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:10:23 PM PDT 24
Peak memory 215396 kb
Host smart-8e1a1fa5-86e4-4f16-813f-f81ecc434ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155939558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3155939558
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1884336447
Short name T437
Test name
Test status
Simulation time 56554358 ps
CPU time 0.95 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:37 PM PDT 24
Peak memory 206344 kb
Host smart-d4789dd5-486f-4237-bdc5-753f62726719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884336447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1884336447
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1493543833
Short name T468
Test name
Test status
Simulation time 34049947 ps
CPU time 1.15 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 219004 kb
Host smart-329c5a4f-8e9b-43f4-ae42-3df8a62d8e80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493543833 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1493543833
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2593516293
Short name T128
Test name
Test status
Simulation time 21267303 ps
CPU time 1.02 seconds
Started May 28 02:10:17 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 223484 kb
Host smart-d2f1775e-1ceb-47ff-bf3d-6738bf1275ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593516293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2593516293
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.184353014
Short name T805
Test name
Test status
Simulation time 113316467 ps
CPU time 1.15 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:20 PM PDT 24
Peak memory 216872 kb
Host smart-4007d715-b868-471c-99f0-54916f76cbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184353014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.184353014
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2473806502
Short name T610
Test name
Test status
Simulation time 34896459 ps
CPU time 0.96 seconds
Started May 28 02:10:25 PM PDT 24
Finished May 28 02:10:27 PM PDT 24
Peak memory 215336 kb
Host smart-74e58189-83ac-4aa1-be31-d203a0e1f2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473806502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2473806502
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.909330675
Short name T555
Test name
Test status
Simulation time 64951175 ps
CPU time 0.95 seconds
Started May 28 02:10:19 PM PDT 24
Finished May 28 02:10:22 PM PDT 24
Peak memory 206836 kb
Host smart-35391a79-4dd0-4f52-88e0-8461c54f9176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909330675 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.909330675
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2804875796
Short name T340
Test name
Test status
Simulation time 24720639 ps
CPU time 0.87 seconds
Started May 28 02:10:18 PM PDT 24
Finished May 28 02:10:21 PM PDT 24
Peak memory 215016 kb
Host smart-c82574a2-e960-4209-a4e5-16e43f33b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804875796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2804875796
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1360523377
Short name T520
Test name
Test status
Simulation time 173124994 ps
CPU time 3.62 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:10:26 PM PDT 24
Peak memory 217940 kb
Host smart-b61919b4-9a8d-4265-93bb-1f98a34726c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360523377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1360523377
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3732682168
Short name T787
Test name
Test status
Simulation time 58281171327 ps
CPU time 801.64 seconds
Started May 28 02:10:20 PM PDT 24
Finished May 28 02:23:45 PM PDT 24
Peak memory 223464 kb
Host smart-df904019-8765-4fd9-85b7-4164b30936be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732682168 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3732682168
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1047592671
Short name T609
Test name
Test status
Simulation time 18949706 ps
CPU time 1.1 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 218368 kb
Host smart-a414ea89-2a2f-4fa0-8c93-3e03fbad16ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047592671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1047592671
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4270724532
Short name T797
Test name
Test status
Simulation time 72449172 ps
CPU time 1.45 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:25 PM PDT 24
Peak memory 218112 kb
Host smart-4ad53cc5-e600-4d40-b61b-0213788e412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270724532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4270724532
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.352743910
Short name T534
Test name
Test status
Simulation time 99599952 ps
CPU time 0.94 seconds
Started May 28 02:12:21 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 218216 kb
Host smart-c10751a5-8ccd-4326-944b-5c82ba6935ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352743910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.352743910
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2938769761
Short name T701
Test name
Test status
Simulation time 38147659 ps
CPU time 1.51 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 217000 kb
Host smart-35bc5468-d748-499e-a28e-fe4e06300946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938769761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2938769761
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.510283059
Short name T385
Test name
Test status
Simulation time 23746096 ps
CPU time 1.26 seconds
Started May 28 02:12:21 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 223476 kb
Host smart-e05c3fe2-98b2-4099-b9e3-58548f78ad9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510283059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.510283059
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3704779737
Short name T296
Test name
Test status
Simulation time 49310884 ps
CPU time 1.44 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:27 PM PDT 24
Peak memory 216776 kb
Host smart-21c1d711-e22b-41af-8167-deff60445486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704779737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3704779737
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2502109644
Short name T716
Test name
Test status
Simulation time 32158428 ps
CPU time 0.97 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 219432 kb
Host smart-0c4180a0-6ccd-4dd1-982a-6e0d109a5d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502109644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2502109644
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.810690881
Short name T387
Test name
Test status
Simulation time 42173144 ps
CPU time 1.48 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 217936 kb
Host smart-3be3ec88-00e4-4775-b3f3-21130207995b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810690881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.810690881
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1014623410
Short name T52
Test name
Test status
Simulation time 35927167 ps
CPU time 1.27 seconds
Started May 28 02:12:25 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 225208 kb
Host smart-9fece649-bdf1-4091-8e0e-c8f3193d0611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014623410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1014623410
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1447739303
Short name T295
Test name
Test status
Simulation time 126916924 ps
CPU time 1.38 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 219624 kb
Host smart-d0591dd3-1b04-4da7-b4cc-2a0b8bb8dfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447739303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1447739303
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3202585785
Short name T582
Test name
Test status
Simulation time 20742529 ps
CPU time 1.08 seconds
Started May 28 02:12:12 PM PDT 24
Finished May 28 02:12:15 PM PDT 24
Peak memory 218120 kb
Host smart-164797fa-4150-4886-9d05-3f767d80e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202585785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3202585785
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1472750520
Short name T355
Test name
Test status
Simulation time 42602079 ps
CPU time 1.25 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:24 PM PDT 24
Peak memory 219028 kb
Host smart-80e7efca-c290-4ad7-ba22-4d630a5d496e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472750520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1472750520
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.4229150206
Short name T56
Test name
Test status
Simulation time 19125831 ps
CPU time 1.24 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 229088 kb
Host smart-e6a37565-6c14-4983-8ccd-7c2adbbc9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229150206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.4229150206
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3668838130
Short name T621
Test name
Test status
Simulation time 88136163 ps
CPU time 1.43 seconds
Started May 28 02:12:15 PM PDT 24
Finished May 28 02:12:17 PM PDT 24
Peak memory 216784 kb
Host smart-ec3e20ce-4d4f-459c-b03b-5dd99756653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668838130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3668838130
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2359257812
Short name T94
Test name
Test status
Simulation time 21190636 ps
CPU time 1.12 seconds
Started May 28 02:12:25 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 219372 kb
Host smart-e76a172e-9a8b-45bd-b384-831a0b2edef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359257812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2359257812
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.559545690
Short name T348
Test name
Test status
Simulation time 349122607 ps
CPU time 2.86 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 217236 kb
Host smart-c61a2561-0030-467a-a15b-84582a941784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559545690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.559545690
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.4228652878
Short name T95
Test name
Test status
Simulation time 32797008 ps
CPU time 1.08 seconds
Started May 28 02:12:20 PM PDT 24
Finished May 28 02:12:22 PM PDT 24
Peak memory 220140 kb
Host smart-a811d8a9-3837-46d6-b45e-d873302ff0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228652878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.4228652878
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3897767385
Short name T580
Test name
Test status
Simulation time 59697155 ps
CPU time 1.3 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:26 PM PDT 24
Peak memory 219224 kb
Host smart-acf33c15-588b-468a-b482-4ffeb58630d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897767385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3897767385
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1645357998
Short name T583
Test name
Test status
Simulation time 23756898 ps
CPU time 0.91 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:27 PM PDT 24
Peak memory 218256 kb
Host smart-597f3d9a-320f-4e2e-9835-a3111f3dba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645357998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1645357998
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.232699179
Short name T311
Test name
Test status
Simulation time 39733539 ps
CPU time 1.24 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 216764 kb
Host smart-c0e531fc-67b7-4213-939a-94db0f7f1a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232699179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.232699179
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1292952326
Short name T724
Test name
Test status
Simulation time 37564078 ps
CPU time 1.22 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 215364 kb
Host smart-ebcc2803-9619-48fc-ad39-93950c1aa87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292952326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1292952326
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.975195359
Short name T305
Test name
Test status
Simulation time 16070889 ps
CPU time 0.98 seconds
Started May 28 02:10:31 PM PDT 24
Finished May 28 02:10:34 PM PDT 24
Peak memory 206196 kb
Host smart-23db2387-656e-4eb4-a46a-851f981585d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975195359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.975195359
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2629016619
Short name T765
Test name
Test status
Simulation time 58527945 ps
CPU time 0.85 seconds
Started May 28 02:10:32 PM PDT 24
Finished May 28 02:10:35 PM PDT 24
Peak memory 215716 kb
Host smart-3fe95e78-01ae-4cd5-858e-547ec53e7593
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629016619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2629016619
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1091627291
Short name T634
Test name
Test status
Simulation time 54883622 ps
CPU time 1.17 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 216624 kb
Host smart-f94b5abf-5712-4253-85a0-aa44b76fd8b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091627291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1091627291
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2962285709
Short name T769
Test name
Test status
Simulation time 30594707 ps
CPU time 0.97 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 228916 kb
Host smart-281eb1af-0710-4218-bc5e-e73ea7fa45f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962285709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2962285709
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1344329942
Short name T624
Test name
Test status
Simulation time 37273481 ps
CPU time 1.42 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:39 PM PDT 24
Peak memory 215036 kb
Host smart-3a542411-4d53-4ec0-ab22-9597caabb3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344329942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1344329942
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.912665266
Short name T160
Test name
Test status
Simulation time 22836169 ps
CPU time 0.96 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:37 PM PDT 24
Peak memory 215348 kb
Host smart-f1e90d94-a69a-4f60-a199-84478e86b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912665266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.912665266
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1406474751
Short name T27
Test name
Test status
Simulation time 15245485 ps
CPU time 0.94 seconds
Started May 28 02:10:33 PM PDT 24
Finished May 28 02:10:38 PM PDT 24
Peak memory 206840 kb
Host smart-7fe30ca4-e2e7-44ae-9cee-c9b460788a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406474751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1406474751
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3898667355
Short name T742
Test name
Test status
Simulation time 15321763 ps
CPU time 0.98 seconds
Started May 28 02:10:30 PM PDT 24
Finished May 28 02:10:32 PM PDT 24
Peak memory 215100 kb
Host smart-1d6f4dca-9279-489b-b51b-2e0c8d93089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898667355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3898667355
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3888113224
Short name T683
Test name
Test status
Simulation time 102660861 ps
CPU time 2.59 seconds
Started May 28 02:10:34 PM PDT 24
Finished May 28 02:10:41 PM PDT 24
Peak memory 216620 kb
Host smart-23b140bc-2025-47c9-81b2-74bc2523c317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888113224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3888113224
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.593557256
Short name T66
Test name
Test status
Simulation time 4003123628 ps
CPU time 67.61 seconds
Started May 28 02:10:42 PM PDT 24
Finished May 28 02:11:50 PM PDT 24
Peak memory 219844 kb
Host smart-c642d9ea-91f4-4b5d-a973-f45eaab84fd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593557256 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.593557256
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3406890206
Short name T114
Test name
Test status
Simulation time 25464855 ps
CPU time 1.1 seconds
Started May 28 02:12:22 PM PDT 24
Finished May 28 02:12:24 PM PDT 24
Peak memory 229296 kb
Host smart-14300174-c8a0-4a6d-878a-a88e9c611fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406890206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3406890206
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3287673031
Short name T578
Test name
Test status
Simulation time 66014292 ps
CPU time 1.31 seconds
Started May 28 02:12:21 PM PDT 24
Finished May 28 02:12:23 PM PDT 24
Peak memory 217940 kb
Host smart-1168c43b-dd28-47fa-a9f8-d62a682eec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287673031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3287673031
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3537192992
Short name T828
Test name
Test status
Simulation time 19307629 ps
CPU time 1.08 seconds
Started May 28 02:12:25 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218340 kb
Host smart-ceca0e79-eccf-4863-930b-6e3d3dbc0a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537192992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3537192992
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.147755325
Short name T421
Test name
Test status
Simulation time 162559536 ps
CPU time 3.07 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218440 kb
Host smart-e7fd7f9d-c7ab-4527-8d51-26deac29a403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147755325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.147755325
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.364376132
Short name T108
Test name
Test status
Simulation time 48436913 ps
CPU time 0.93 seconds
Started May 28 02:12:25 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 219420 kb
Host smart-ca3e1214-b5b2-4b05-aa7f-f21804f0f60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364376132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.364376132
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1602178104
Short name T288
Test name
Test status
Simulation time 34682657 ps
CPU time 1.54 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:27 PM PDT 24
Peak memory 218104 kb
Host smart-0a0a0da0-13d3-4abb-abe5-0e9700337af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602178104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1602178104
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3239356133
Short name T7
Test name
Test status
Simulation time 30384715 ps
CPU time 1.04 seconds
Started May 28 02:12:23 PM PDT 24
Finished May 28 02:12:25 PM PDT 24
Peak memory 219272 kb
Host smart-69c4623e-c064-4e2b-944f-9a51ba9fe790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239356133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3239356133
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.923650998
Short name T62
Test name
Test status
Simulation time 43186103 ps
CPU time 1.75 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 218040 kb
Host smart-d9f26920-d9cb-4d29-9da1-fee4e77790d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923650998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.923650998
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4073099828
Short name T174
Test name
Test status
Simulation time 99687010 ps
CPU time 1.06 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 219560 kb
Host smart-80b9e5d0-f7e2-4c68-b380-8a2045dd255b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073099828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4073099828
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3127115171
Short name T698
Test name
Test status
Simulation time 115271757 ps
CPU time 1.33 seconds
Started May 28 02:12:24 PM PDT 24
Finished May 28 02:12:28 PM PDT 24
Peak memory 216668 kb
Host smart-9b57edc7-a332-4f79-8ea7-ba5cd3c8433b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127115171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3127115171
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4100778514
Short name T637
Test name
Test status
Simulation time 21376517 ps
CPU time 1.06 seconds
Started May 28 02:12:41 PM PDT 24
Finished May 28 02:12:46 PM PDT 24
Peak memory 218204 kb
Host smart-9a19a55e-0aa0-4909-81c3-00fb47f99013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100778514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4100778514
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.608983946
Short name T702
Test name
Test status
Simulation time 56168474 ps
CPU time 1 seconds
Started May 28 02:12:35 PM PDT 24
Finished May 28 02:12:38 PM PDT 24
Peak memory 216912 kb
Host smart-00e4116f-4b2e-4115-a65d-2b281c572980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608983946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.608983946
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3517120272
Short name T8
Test name
Test status
Simulation time 20022825 ps
CPU time 1.11 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:44 PM PDT 24
Peak memory 218260 kb
Host smart-5b1c45d7-a903-4e34-b072-e24d6c4ab9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517120272 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3517120272
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.71422496
Short name T42
Test name
Test status
Simulation time 47009063 ps
CPU time 1.71 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 216884 kb
Host smart-8f295cca-d481-4ade-8adf-ba1317af4197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71422496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.71422496
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.429019927
Short name T109
Test name
Test status
Simulation time 122152722 ps
CPU time 1.09 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:42 PM PDT 24
Peak memory 229092 kb
Host smart-004b975a-5470-4ac9-93ba-746568756905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429019927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.429019927
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1135105508
Short name T20
Test name
Test status
Simulation time 75827384 ps
CPU time 2.14 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 219580 kb
Host smart-6b0f0d0a-ee86-4436-b139-064c918b949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135105508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1135105508
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2871741142
Short name T352
Test name
Test status
Simulation time 75350904 ps
CPU time 1.03 seconds
Started May 28 02:12:38 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 219564 kb
Host smart-9e3ada08-ec38-458a-93a6-f7a299148996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871741142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2871741142
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4174398610
Short name T643
Test name
Test status
Simulation time 110178799 ps
CPU time 1.33 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:43 PM PDT 24
Peak memory 218376 kb
Host smart-e3c9fa2f-0631-45d9-a686-1f037b0e7770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174398610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4174398610
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.864229109
Short name T357
Test name
Test status
Simulation time 36011920 ps
CPU time 0.91 seconds
Started May 28 02:12:37 PM PDT 24
Finished May 28 02:12:41 PM PDT 24
Peak memory 218260 kb
Host smart-4fa5c357-2aa2-4ceb-a9e7-4b66e969a71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864229109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.864229109
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.107436073
Short name T697
Test name
Test status
Simulation time 68526209 ps
CPU time 1.22 seconds
Started May 28 02:12:36 PM PDT 24
Finished May 28 02:12:40 PM PDT 24
Peak memory 216752 kb
Host smart-f6cf4251-7dad-46da-8c11-1d2e3538d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107436073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.107436073
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%