Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.52 98.24 93.80 97.02 84.88 96.62 99.77 91.31


Total test records in report: 980
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T794 /workspace/coverage/default/15.edn_err.440483229 May 30 02:02:13 PM PDT 24 May 30 02:02:15 PM PDT 24 19548519 ps
T795 /workspace/coverage/default/51.edn_genbits.4266369043 May 30 02:04:23 PM PDT 24 May 30 02:04:26 PM PDT 24 66889326 ps
T796 /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3592134075 May 30 02:02:06 PM PDT 24 May 30 02:26:19 PM PDT 24 133514490694 ps
T797 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1373778459 May 30 02:02:13 PM PDT 24 May 30 02:25:14 PM PDT 24 199645517348 ps
T798 /workspace/coverage/default/33.edn_stress_all.102876660 May 30 02:03:21 PM PDT 24 May 30 02:03:29 PM PDT 24 433465467 ps
T799 /workspace/coverage/default/34.edn_smoke.3335993207 May 30 02:03:23 PM PDT 24 May 30 02:03:27 PM PDT 24 17020777 ps
T800 /workspace/coverage/default/20.edn_alert_test.155697859 May 30 02:02:30 PM PDT 24 May 30 02:02:32 PM PDT 24 24568748 ps
T138 /workspace/coverage/default/1.edn_sec_cm.4168314630 May 30 02:01:27 PM PDT 24 May 30 02:01:34 PM PDT 24 330734896 ps
T801 /workspace/coverage/default/262.edn_genbits.329330852 May 30 02:05:11 PM PDT 24 May 30 02:05:14 PM PDT 24 71015049 ps
T802 /workspace/coverage/default/33.edn_smoke.823164065 May 30 02:03:20 PM PDT 24 May 30 02:03:24 PM PDT 24 35167813 ps
T803 /workspace/coverage/default/36.edn_stress_all.3393148041 May 30 02:03:22 PM PDT 24 May 30 02:03:32 PM PDT 24 327676482 ps
T804 /workspace/coverage/default/153.edn_genbits.3146896019 May 30 02:04:38 PM PDT 24 May 30 02:04:41 PM PDT 24 48325471 ps
T805 /workspace/coverage/default/32.edn_alert.3544791233 May 30 02:03:21 PM PDT 24 May 30 02:03:25 PM PDT 24 49291088 ps
T806 /workspace/coverage/default/47.edn_disable_auto_req_mode.4206908591 May 30 02:04:24 PM PDT 24 May 30 02:04:27 PM PDT 24 34017603 ps
T807 /workspace/coverage/default/48.edn_alert.3521598951 May 30 02:04:25 PM PDT 24 May 30 02:04:28 PM PDT 24 48761963 ps
T96 /workspace/coverage/default/30.edn_err.3753869794 May 30 02:03:23 PM PDT 24 May 30 02:03:27 PM PDT 24 18514651 ps
T808 /workspace/coverage/default/242.edn_genbits.2720490685 May 30 02:05:12 PM PDT 24 May 30 02:05:15 PM PDT 24 45667629 ps
T185 /workspace/coverage/default/39.edn_disable.2009284049 May 30 02:03:27 PM PDT 24 May 30 02:03:30 PM PDT 24 40098460 ps
T809 /workspace/coverage/default/47.edn_alert_test.2165978860 May 30 02:04:21 PM PDT 24 May 30 02:04:23 PM PDT 24 31461078 ps
T810 /workspace/coverage/default/94.edn_err.2428346678 May 30 02:04:36 PM PDT 24 May 30 02:04:38 PM PDT 24 33963193 ps
T811 /workspace/coverage/default/28.edn_stress_all.3768458516 May 30 02:03:22 PM PDT 24 May 30 02:03:29 PM PDT 24 205167097 ps
T812 /workspace/coverage/default/31.edn_genbits.855876536 May 30 02:03:22 PM PDT 24 May 30 02:03:25 PM PDT 24 106974031 ps
T813 /workspace/coverage/default/187.edn_genbits.1379507885 May 30 02:04:48 PM PDT 24 May 30 02:04:51 PM PDT 24 89888312 ps
T814 /workspace/coverage/default/95.edn_genbits.1883000043 May 30 02:04:26 PM PDT 24 May 30 02:04:29 PM PDT 24 68856069 ps
T815 /workspace/coverage/default/8.edn_intr.2911663450 May 30 02:02:05 PM PDT 24 May 30 02:02:08 PM PDT 24 27004472 ps
T816 /workspace/coverage/default/0.edn_disable_auto_req_mode.2324129837 May 30 02:01:13 PM PDT 24 May 30 02:01:15 PM PDT 24 80843019 ps
T817 /workspace/coverage/default/173.edn_genbits.4064557167 May 30 02:04:39 PM PDT 24 May 30 02:04:43 PM PDT 24 42560012 ps
T818 /workspace/coverage/default/217.edn_genbits.4033295530 May 30 02:04:53 PM PDT 24 May 30 02:04:57 PM PDT 24 135413748 ps
T819 /workspace/coverage/default/252.edn_genbits.1733423316 May 30 02:05:13 PM PDT 24 May 30 02:05:16 PM PDT 24 50133640 ps
T820 /workspace/coverage/default/157.edn_genbits.75549379 May 30 02:04:34 PM PDT 24 May 30 02:04:37 PM PDT 24 44854684 ps
T821 /workspace/coverage/default/240.edn_genbits.2437045638 May 30 02:05:12 PM PDT 24 May 30 02:05:15 PM PDT 24 82931673 ps
T822 /workspace/coverage/default/171.edn_genbits.236682929 May 30 02:04:38 PM PDT 24 May 30 02:04:41 PM PDT 24 37446306 ps
T297 /workspace/coverage/default/131.edn_genbits.1175336815 May 30 02:04:29 PM PDT 24 May 30 02:04:33 PM PDT 24 92752931 ps
T94 /workspace/coverage/default/23.edn_err.1872857592 May 30 02:03:06 PM PDT 24 May 30 02:03:09 PM PDT 24 38426162 ps
T823 /workspace/coverage/default/16.edn_err.2402972671 May 30 02:02:12 PM PDT 24 May 30 02:02:14 PM PDT 24 42982126 ps
T824 /workspace/coverage/default/43.edn_smoke.2168250110 May 30 02:03:30 PM PDT 24 May 30 02:03:32 PM PDT 24 19074251 ps
T825 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.820373687 May 30 02:02:14 PM PDT 24 May 30 02:24:08 PM PDT 24 132454503572 ps
T826 /workspace/coverage/default/114.edn_genbits.4078747093 May 30 02:04:29 PM PDT 24 May 30 02:04:34 PM PDT 24 118830807 ps
T827 /workspace/coverage/default/160.edn_genbits.4277181992 May 30 02:04:34 PM PDT 24 May 30 02:04:36 PM PDT 24 57266822 ps
T159 /workspace/coverage/default/11.edn_intr.1017853145 May 30 02:02:04 PM PDT 24 May 30 02:02:06 PM PDT 24 40861587 ps
T828 /workspace/coverage/default/126.edn_genbits.2203349213 May 30 02:04:29 PM PDT 24 May 30 02:04:32 PM PDT 24 124417357 ps
T829 /workspace/coverage/default/149.edn_genbits.597137222 May 30 02:04:38 PM PDT 24 May 30 02:04:41 PM PDT 24 59233684 ps
T830 /workspace/coverage/default/68.edn_genbits.1341581019 May 30 02:04:23 PM PDT 24 May 30 02:04:26 PM PDT 24 33297607 ps
T831 /workspace/coverage/default/229.edn_genbits.1134223578 May 30 02:04:57 PM PDT 24 May 30 02:04:59 PM PDT 24 97662343 ps
T298 /workspace/coverage/default/75.edn_genbits.2244189773 May 30 02:04:30 PM PDT 24 May 30 02:04:33 PM PDT 24 121133665 ps
T832 /workspace/coverage/default/38.edn_genbits.3671363643 May 30 02:03:33 PM PDT 24 May 30 02:03:35 PM PDT 24 136345690 ps
T139 /workspace/coverage/default/3.edn_sec_cm.4012162653 May 30 02:01:36 PM PDT 24 May 30 02:01:41 PM PDT 24 1141504199 ps
T833 /workspace/coverage/default/15.edn_alert.1882248394 May 30 02:02:17 PM PDT 24 May 30 02:02:20 PM PDT 24 61637544 ps
T834 /workspace/coverage/default/24.edn_disable.475218215 May 30 02:03:06 PM PDT 24 May 30 02:03:10 PM PDT 24 11374739 ps
T835 /workspace/coverage/default/33.edn_genbits.1578513484 May 30 02:03:21 PM PDT 24 May 30 02:03:24 PM PDT 24 353570618 ps
T836 /workspace/coverage/default/45.edn_alert_test.1708680827 May 30 02:03:54 PM PDT 24 May 30 02:03:56 PM PDT 24 14406233 ps
T837 /workspace/coverage/default/29.edn_err.2367388874 May 30 02:03:16 PM PDT 24 May 30 02:03:19 PM PDT 24 25861366 ps
T838 /workspace/coverage/default/19.edn_alert_test.3264481466 May 30 02:02:30 PM PDT 24 May 30 02:02:32 PM PDT 24 28630745 ps
T839 /workspace/coverage/default/127.edn_genbits.2537460330 May 30 02:04:29 PM PDT 24 May 30 02:04:32 PM PDT 24 110764270 ps
T294 /workspace/coverage/default/260.edn_genbits.3033121989 May 30 02:05:12 PM PDT 24 May 30 02:05:15 PM PDT 24 34399259 ps
T840 /workspace/coverage/default/7.edn_intr.2396035987 May 30 02:01:48 PM PDT 24 May 30 02:01:50 PM PDT 24 29542054 ps
T841 /workspace/coverage/default/144.edn_genbits.1549850670 May 30 02:04:39 PM PDT 24 May 30 02:04:42 PM PDT 24 45138609 ps
T842 /workspace/coverage/default/8.edn_disable.2613474316 May 30 02:02:06 PM PDT 24 May 30 02:02:08 PM PDT 24 113899299 ps
T843 /workspace/coverage/default/24.edn_alert_test.675506958 May 30 02:03:07 PM PDT 24 May 30 02:03:11 PM PDT 24 16473749 ps
T844 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3607956832 May 30 02:03:22 PM PDT 24 May 30 02:15:09 PM PDT 24 30076766949 ps
T845 /workspace/coverage/default/69.edn_genbits.588471082 May 30 02:04:28 PM PDT 24 May 30 02:04:31 PM PDT 24 32832664 ps
T846 /workspace/coverage/default/59.edn_err.1477342406 May 30 02:04:23 PM PDT 24 May 30 02:04:25 PM PDT 24 19192766 ps
T847 /workspace/coverage/default/134.edn_genbits.2543592243 May 30 02:04:29 PM PDT 24 May 30 02:04:33 PM PDT 24 26281043 ps
T848 /workspace/coverage/default/7.edn_stress_all.4002578509 May 30 02:01:48 PM PDT 24 May 30 02:01:50 PM PDT 24 56948983 ps
T849 /workspace/coverage/default/280.edn_genbits.1602398752 May 30 02:05:10 PM PDT 24 May 30 02:05:12 PM PDT 24 43829751 ps
T850 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1141947328 May 30 03:35:06 PM PDT 24 May 30 03:35:09 PM PDT 24 86390836 ps
T216 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3557764718 May 30 03:35:32 PM PDT 24 May 30 03:35:35 PM PDT 24 43463244 ps
T851 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1553126214 May 30 03:35:10 PM PDT 24 May 30 03:35:12 PM PDT 24 107852783 ps
T852 /workspace/coverage/cover_reg_top/27.edn_intr_test.1726091395 May 30 03:36:17 PM PDT 24 May 30 03:36:21 PM PDT 24 16604585 ps
T247 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.166249346 May 30 03:35:38 PM PDT 24 May 30 03:35:44 PM PDT 24 113672982 ps
T248 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1984985108 May 30 03:35:39 PM PDT 24 May 30 03:35:43 PM PDT 24 112504695 ps
T853 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2779522723 May 30 03:35:41 PM PDT 24 May 30 03:35:47 PM PDT 24 112881053 ps
T854 /workspace/coverage/cover_reg_top/29.edn_intr_test.669123826 May 30 03:36:13 PM PDT 24 May 30 03:36:15 PM PDT 24 24989587 ps
T236 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2358436900 May 30 03:35:31 PM PDT 24 May 30 03:35:34 PM PDT 24 101914639 ps
T217 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3130222011 May 30 03:35:21 PM PDT 24 May 30 03:35:24 PM PDT 24 63529958 ps
T855 /workspace/coverage/cover_reg_top/41.edn_intr_test.969850943 May 30 03:36:12 PM PDT 24 May 30 03:36:14 PM PDT 24 11634310 ps
T856 /workspace/coverage/cover_reg_top/4.edn_tl_errors.51823242 May 30 03:35:18 PM PDT 24 May 30 03:35:24 PM PDT 24 274668019 ps
T218 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2561145962 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 20987227 ps
T857 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1628158607 May 30 03:35:41 PM PDT 24 May 30 03:35:43 PM PDT 24 15609479 ps
T858 /workspace/coverage/cover_reg_top/18.edn_intr_test.2801225841 May 30 03:35:37 PM PDT 24 May 30 03:35:39 PM PDT 24 44734896 ps
T249 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3028439515 May 30 03:35:39 PM PDT 24 May 30 03:35:42 PM PDT 24 93121170 ps
T859 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1563621616 May 30 03:35:37 PM PDT 24 May 30 03:35:41 PM PDT 24 89022142 ps
T246 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1956437282 May 30 03:35:06 PM PDT 24 May 30 03:35:09 PM PDT 24 15015469 ps
T860 /workspace/coverage/cover_reg_top/22.edn_intr_test.1210046987 May 30 03:35:38 PM PDT 24 May 30 03:35:40 PM PDT 24 29866073 ps
T219 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3483392521 May 30 03:35:09 PM PDT 24 May 30 03:35:12 PM PDT 24 13689848 ps
T237 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2756785622 May 30 03:35:20 PM PDT 24 May 30 03:35:22 PM PDT 24 39588858 ps
T258 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1163471943 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 90632383 ps
T220 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2191799000 May 30 03:35:39 PM PDT 24 May 30 03:35:42 PM PDT 24 23589260 ps
T861 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3268874265 May 30 03:35:08 PM PDT 24 May 30 03:35:11 PM PDT 24 18155324 ps
T862 /workspace/coverage/cover_reg_top/37.edn_intr_test.1584494559 May 30 03:36:15 PM PDT 24 May 30 03:36:18 PM PDT 24 54639806 ps
T863 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3382249264 May 30 03:35:24 PM PDT 24 May 30 03:35:26 PM PDT 24 56469816 ps
T864 /workspace/coverage/cover_reg_top/0.edn_tl_errors.666383242 May 30 03:35:09 PM PDT 24 May 30 03:35:14 PM PDT 24 252476237 ps
T865 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1077245193 May 30 03:35:38 PM PDT 24 May 30 03:35:45 PM PDT 24 123761606 ps
T866 /workspace/coverage/cover_reg_top/1.edn_intr_test.2431823216 May 30 03:35:07 PM PDT 24 May 30 03:35:10 PM PDT 24 16932720 ps
T867 /workspace/coverage/cover_reg_top/38.edn_intr_test.1824412785 May 30 03:36:13 PM PDT 24 May 30 03:36:15 PM PDT 24 10860062 ps
T256 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4213163213 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 63666015 ps
T868 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.909090890 May 30 03:35:41 PM PDT 24 May 30 03:35:44 PM PDT 24 23375450 ps
T238 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3111777340 May 30 03:35:31 PM PDT 24 May 30 03:35:33 PM PDT 24 73405861 ps
T221 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3868851612 May 30 03:35:31 PM PDT 24 May 30 03:35:33 PM PDT 24 14350361 ps
T239 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2221094243 May 30 03:35:16 PM PDT 24 May 30 03:35:18 PM PDT 24 34757232 ps
T869 /workspace/coverage/cover_reg_top/11.edn_intr_test.3647378421 May 30 03:35:31 PM PDT 24 May 30 03:35:33 PM PDT 24 19498147 ps
T870 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.662734606 May 30 03:35:40 PM PDT 24 May 30 03:35:43 PM PDT 24 29442180 ps
T871 /workspace/coverage/cover_reg_top/46.edn_intr_test.1964475502 May 30 03:36:13 PM PDT 24 May 30 03:36:16 PM PDT 24 87342716 ps
T254 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1805934756 May 30 03:35:23 PM PDT 24 May 30 03:35:26 PM PDT 24 151528789 ps
T872 /workspace/coverage/cover_reg_top/24.edn_intr_test.166453797 May 30 03:35:36 PM PDT 24 May 30 03:35:38 PM PDT 24 23459879 ps
T222 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1523177772 May 30 03:35:18 PM PDT 24 May 30 03:35:20 PM PDT 24 56892197 ps
T873 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3700582206 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 444881166 ps
T240 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.546326101 May 30 03:35:09 PM PDT 24 May 30 03:35:11 PM PDT 24 39482867 ps
T874 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3235876053 May 30 03:35:39 PM PDT 24 May 30 03:35:42 PM PDT 24 29067395 ps
T223 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2656090994 May 30 03:35:36 PM PDT 24 May 30 03:35:38 PM PDT 24 56124711 ps
T875 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4031601629 May 30 03:35:30 PM PDT 24 May 30 03:35:33 PM PDT 24 22359957 ps
T876 /workspace/coverage/cover_reg_top/26.edn_intr_test.2488335215 May 30 03:36:16 PM PDT 24 May 30 03:36:19 PM PDT 24 15627526 ps
T224 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3494820569 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 103031057 ps
T877 /workspace/coverage/cover_reg_top/0.edn_intr_test.3734676625 May 30 03:35:07 PM PDT 24 May 30 03:35:09 PM PDT 24 13620432 ps
T878 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3459513804 May 30 03:35:16 PM PDT 24 May 30 03:35:24 PM PDT 24 1083675805 ps
T879 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2532017500 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 38673738 ps
T225 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1767933472 May 30 03:35:32 PM PDT 24 May 30 03:35:34 PM PDT 24 14487084 ps
T880 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3335508752 May 30 03:35:20 PM PDT 24 May 30 03:35:23 PM PDT 24 33907830 ps
T232 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.542241977 May 30 03:35:10 PM PDT 24 May 30 03:35:15 PM PDT 24 543373910 ps
T881 /workspace/coverage/cover_reg_top/42.edn_intr_test.2863726548 May 30 03:36:18 PM PDT 24 May 30 03:36:22 PM PDT 24 16076978 ps
T255 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1679599097 May 30 03:35:15 PM PDT 24 May 30 03:35:19 PM PDT 24 102703625 ps
T882 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3975861630 May 30 03:35:37 PM PDT 24 May 30 03:35:42 PM PDT 24 253519317 ps
T883 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.38339364 May 30 03:35:17 PM PDT 24 May 30 03:35:20 PM PDT 24 349723398 ps
T884 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1115706251 May 30 03:35:32 PM PDT 24 May 30 03:35:35 PM PDT 24 179676978 ps
T226 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2357789347 May 30 03:35:17 PM PDT 24 May 30 03:35:20 PM PDT 24 18365338 ps
T885 /workspace/coverage/cover_reg_top/39.edn_intr_test.1649669338 May 30 03:36:13 PM PDT 24 May 30 03:36:15 PM PDT 24 38714733 ps
T886 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3959464058 May 30 03:35:31 PM PDT 24 May 30 03:35:33 PM PDT 24 20027243 ps
T887 /workspace/coverage/cover_reg_top/34.edn_intr_test.1662967399 May 30 03:36:12 PM PDT 24 May 30 03:36:14 PM PDT 24 35416156 ps
T888 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1221240881 May 30 03:35:36 PM PDT 24 May 30 03:35:39 PM PDT 24 86316506 ps
T889 /workspace/coverage/cover_reg_top/14.edn_intr_test.2237784954 May 30 03:35:38 PM PDT 24 May 30 03:35:42 PM PDT 24 14491092 ps
T890 /workspace/coverage/cover_reg_top/43.edn_intr_test.696755104 May 30 03:36:19 PM PDT 24 May 30 03:36:22 PM PDT 24 11338126 ps
T227 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3237600619 May 30 03:35:08 PM PDT 24 May 30 03:35:11 PM PDT 24 14903112 ps
T891 /workspace/coverage/cover_reg_top/45.edn_intr_test.994547260 May 30 03:36:14 PM PDT 24 May 30 03:36:17 PM PDT 24 20526971 ps
T892 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2370431956 May 30 03:35:34 PM PDT 24 May 30 03:35:36 PM PDT 24 14866675 ps
T893 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3116118205 May 30 03:35:38 PM PDT 24 May 30 03:35:41 PM PDT 24 12978728 ps
T894 /workspace/coverage/cover_reg_top/16.edn_intr_test.3664414492 May 30 03:35:39 PM PDT 24 May 30 03:35:42 PM PDT 24 15068936 ps
T895 /workspace/coverage/cover_reg_top/10.edn_tl_errors.687997326 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 42519195 ps
T228 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3636005464 May 30 03:35:19 PM PDT 24 May 30 03:35:22 PM PDT 24 65135201 ps
T896 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1933562331 May 30 03:35:19 PM PDT 24 May 30 03:35:22 PM PDT 24 214263660 ps
T897 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2090107145 May 30 03:35:36 PM PDT 24 May 30 03:35:38 PM PDT 24 49554891 ps
T898 /workspace/coverage/cover_reg_top/20.edn_intr_test.2031772568 May 30 03:35:37 PM PDT 24 May 30 03:35:40 PM PDT 24 23721685 ps
T899 /workspace/coverage/cover_reg_top/10.edn_intr_test.3985196913 May 30 03:35:33 PM PDT 24 May 30 03:35:35 PM PDT 24 38734117 ps
T900 /workspace/coverage/cover_reg_top/13.edn_tl_errors.982347027 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 47981016 ps
T901 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3505683309 May 30 03:35:08 PM PDT 24 May 30 03:35:13 PM PDT 24 133023359 ps
T902 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4084047255 May 30 03:35:20 PM PDT 24 May 30 03:35:22 PM PDT 24 36039322 ps
T903 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1019102643 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 40853633 ps
T904 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3353843482 May 30 03:35:08 PM PDT 24 May 30 03:35:11 PM PDT 24 40727457 ps
T905 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2776285244 May 30 03:35:35 PM PDT 24 May 30 03:35:38 PM PDT 24 21230458 ps
T906 /workspace/coverage/cover_reg_top/15.edn_tl_errors.888843487 May 30 03:35:37 PM PDT 24 May 30 03:35:41 PM PDT 24 244125985 ps
T907 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2602156497 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 287287486 ps
T908 /workspace/coverage/cover_reg_top/31.edn_intr_test.3234384122 May 30 03:36:17 PM PDT 24 May 30 03:36:21 PM PDT 24 165596381 ps
T909 /workspace/coverage/cover_reg_top/25.edn_intr_test.3985871274 May 30 03:35:38 PM PDT 24 May 30 03:35:42 PM PDT 24 15687603 ps
T910 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.454923677 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 75683314 ps
T911 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4210510488 May 30 03:35:32 PM PDT 24 May 30 03:35:35 PM PDT 24 31237055 ps
T912 /workspace/coverage/cover_reg_top/48.edn_intr_test.3512219322 May 30 03:36:12 PM PDT 24 May 30 03:36:14 PM PDT 24 44873090 ps
T229 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2503732957 May 30 03:35:37 PM PDT 24 May 30 03:35:39 PM PDT 24 16317959 ps
T913 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1820871067 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 46695275 ps
T914 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3769718969 May 30 03:35:37 PM PDT 24 May 30 03:35:42 PM PDT 24 130692915 ps
T915 /workspace/coverage/cover_reg_top/19.edn_intr_test.4142624999 May 30 03:35:38 PM PDT 24 May 30 03:35:41 PM PDT 24 54594182 ps
T916 /workspace/coverage/cover_reg_top/21.edn_intr_test.3087653968 May 30 03:35:38 PM PDT 24 May 30 03:35:41 PM PDT 24 34658865 ps
T917 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2302404207 May 30 03:35:08 PM PDT 24 May 30 03:35:12 PM PDT 24 58187560 ps
T918 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1759909556 May 30 03:35:38 PM PDT 24 May 30 03:35:41 PM PDT 24 36667220 ps
T919 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3190883089 May 30 03:35:37 PM PDT 24 May 30 03:35:39 PM PDT 24 14473598 ps
T920 /workspace/coverage/cover_reg_top/1.edn_csr_rw.45277202 May 30 03:35:07 PM PDT 24 May 30 03:35:10 PM PDT 24 14510506 ps
T921 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2348218033 May 30 03:35:18 PM PDT 24 May 30 03:35:22 PM PDT 24 69661228 ps
T230 /workspace/coverage/cover_reg_top/9.edn_csr_rw.702423547 May 30 03:35:30 PM PDT 24 May 30 03:35:32 PM PDT 24 43903430 ps
T922 /workspace/coverage/cover_reg_top/33.edn_intr_test.139650823 May 30 03:36:13 PM PDT 24 May 30 03:36:16 PM PDT 24 22896475 ps
T231 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4175397830 May 30 03:35:10 PM PDT 24 May 30 03:35:12 PM PDT 24 89774216 ps
T923 /workspace/coverage/cover_reg_top/35.edn_intr_test.1396825515 May 30 03:36:18 PM PDT 24 May 30 03:36:21 PM PDT 24 20357218 ps
T924 /workspace/coverage/cover_reg_top/49.edn_intr_test.428247124 May 30 03:36:15 PM PDT 24 May 30 03:36:18 PM PDT 24 18686344 ps
T925 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3873304317 May 30 03:35:08 PM PDT 24 May 30 03:35:11 PM PDT 24 103094879 ps
T926 /workspace/coverage/cover_reg_top/2.edn_intr_test.1073200102 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 38125827 ps
T927 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2407099804 May 30 03:35:31 PM PDT 24 May 30 03:35:34 PM PDT 24 128467625 ps
T928 /workspace/coverage/cover_reg_top/30.edn_intr_test.2679664702 May 30 03:36:14 PM PDT 24 May 30 03:36:16 PM PDT 24 40244620 ps
T929 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4249865923 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 17767235 ps
T233 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2751958630 May 30 03:35:17 PM PDT 24 May 30 03:35:22 PM PDT 24 135543142 ps
T930 /workspace/coverage/cover_reg_top/7.edn_intr_test.2591792042 May 30 03:35:20 PM PDT 24 May 30 03:35:22 PM PDT 24 71994370 ps
T931 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3463696187 May 30 03:35:08 PM PDT 24 May 30 03:35:10 PM PDT 24 59090223 ps
T257 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3981945685 May 30 03:35:17 PM PDT 24 May 30 03:35:21 PM PDT 24 363803733 ps
T932 /workspace/coverage/cover_reg_top/36.edn_intr_test.390674647 May 30 03:36:18 PM PDT 24 May 30 03:36:21 PM PDT 24 24279364 ps
T933 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4141552801 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 66052124 ps
T234 /workspace/coverage/cover_reg_top/19.edn_csr_rw.680437980 May 30 03:35:36 PM PDT 24 May 30 03:35:38 PM PDT 24 14411511 ps
T934 /workspace/coverage/cover_reg_top/6.edn_intr_test.1621798456 May 30 03:35:17 PM PDT 24 May 30 03:35:19 PM PDT 24 20230646 ps
T935 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3842316740 May 30 03:35:43 PM PDT 24 May 30 03:35:45 PM PDT 24 52447592 ps
T936 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2265125536 May 30 03:35:40 PM PDT 24 May 30 03:35:43 PM PDT 24 55049929 ps
T235 /workspace/coverage/cover_reg_top/18.edn_csr_rw.490050836 May 30 03:35:38 PM PDT 24 May 30 03:35:41 PM PDT 24 19659151 ps
T937 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1200696925 May 30 03:35:22 PM PDT 24 May 30 03:35:25 PM PDT 24 108335487 ps
T938 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3696192257 May 30 03:35:35 PM PDT 24 May 30 03:35:40 PM PDT 24 556916747 ps
T939 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2586252490 May 30 03:35:34 PM PDT 24 May 30 03:35:40 PM PDT 24 155963797 ps
T940 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4144718102 May 30 03:35:11 PM PDT 24 May 30 03:35:13 PM PDT 24 91493329 ps
T941 /workspace/coverage/cover_reg_top/15.edn_intr_test.1202299423 May 30 03:35:38 PM PDT 24 May 30 03:35:42 PM PDT 24 15328579 ps
T942 /workspace/coverage/cover_reg_top/40.edn_intr_test.3046442906 May 30 03:36:15 PM PDT 24 May 30 03:36:18 PM PDT 24 67975212 ps
T943 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2418443998 May 30 03:35:18 PM PDT 24 May 30 03:35:21 PM PDT 24 24834381 ps
T944 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2478329786 May 30 03:35:08 PM PDT 24 May 30 03:35:11 PM PDT 24 21478733 ps
T945 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1449801715 May 30 03:35:20 PM PDT 24 May 30 03:35:23 PM PDT 24 11811775 ps
T946 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.88993126 May 30 03:35:07 PM PDT 24 May 30 03:35:10 PM PDT 24 25496296 ps
T947 /workspace/coverage/cover_reg_top/13.edn_intr_test.2227221880 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 18301978 ps
T948 /workspace/coverage/cover_reg_top/4.edn_intr_test.1882041932 May 30 03:35:20 PM PDT 24 May 30 03:35:23 PM PDT 24 103739081 ps
T949 /workspace/coverage/cover_reg_top/9.edn_intr_test.3704729871 May 30 03:35:31 PM PDT 24 May 30 03:35:33 PM PDT 24 31358814 ps
T950 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.179322805 May 30 03:35:18 PM PDT 24 May 30 03:35:20 PM PDT 24 17398581 ps
T951 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2141363984 May 30 03:35:20 PM PDT 24 May 30 03:35:25 PM PDT 24 204713189 ps
T952 /workspace/coverage/cover_reg_top/44.edn_intr_test.3863638602 May 30 03:36:18 PM PDT 24 May 30 03:36:22 PM PDT 24 40015359 ps
T953 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3658083771 May 30 03:35:10 PM PDT 24 May 30 03:35:14 PM PDT 24 306457384 ps
T954 /workspace/coverage/cover_reg_top/5.edn_intr_test.957807756 May 30 03:35:20 PM PDT 24 May 30 03:35:23 PM PDT 24 66374081 ps
T955 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1794764127 May 30 03:35:37 PM PDT 24 May 30 03:35:39 PM PDT 24 67717066 ps
T956 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1782411729 May 30 03:35:17 PM PDT 24 May 30 03:35:21 PM PDT 24 816642458 ps
T957 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2500498751 May 30 03:35:18 PM PDT 24 May 30 03:35:20 PM PDT 24 17718956 ps
T958 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3823310470 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 27869851 ps
T959 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3006194351 May 30 03:35:07 PM PDT 24 May 30 03:35:09 PM PDT 24 22512500 ps
T960 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2354571481 May 30 03:35:36 PM PDT 24 May 30 03:35:39 PM PDT 24 127692260 ps
T961 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2738421816 May 30 03:35:33 PM PDT 24 May 30 03:35:38 PM PDT 24 745853120 ps
T962 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1595625461 May 30 03:35:34 PM PDT 24 May 30 03:35:37 PM PDT 24 27438183 ps
T963 /workspace/coverage/cover_reg_top/17.edn_intr_test.1573697288 May 30 03:35:37 PM PDT 24 May 30 03:35:40 PM PDT 24 27521990 ps
T964 /workspace/coverage/cover_reg_top/12.edn_intr_test.2871444982 May 30 03:35:33 PM PDT 24 May 30 03:35:36 PM PDT 24 106644045 ps
T965 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.208106443 May 30 03:35:32 PM PDT 24 May 30 03:35:36 PM PDT 24 99828596 ps
T966 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2602932870 May 30 03:35:07 PM PDT 24 May 30 03:35:11 PM PDT 24 355201479 ps
T967 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3958925720 May 30 03:35:32 PM PDT 24 May 30 03:35:35 PM PDT 24 142333740 ps
T968 /workspace/coverage/cover_reg_top/11.edn_csr_rw.795944458 May 30 03:35:32 PM PDT 24 May 30 03:35:34 PM PDT 24 23852630 ps
T969 /workspace/coverage/cover_reg_top/47.edn_intr_test.1974199202 May 30 03:36:15 PM PDT 24 May 30 03:36:18 PM PDT 24 23048894 ps
T970 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.13703525 May 30 03:35:34 PM PDT 24 May 30 03:35:36 PM PDT 24 27574492 ps
T971 /workspace/coverage/cover_reg_top/8.edn_intr_test.524159657 May 30 03:35:32 PM PDT 24 May 30 03:35:34 PM PDT 24 15184517 ps
T972 /workspace/coverage/cover_reg_top/32.edn_intr_test.241327822 May 30 03:36:15 PM PDT 24 May 30 03:36:18 PM PDT 24 27530108 ps
T973 /workspace/coverage/cover_reg_top/23.edn_intr_test.4175676964 May 30 03:35:36 PM PDT 24 May 30 03:35:39 PM PDT 24 14660626 ps
T974 /workspace/coverage/cover_reg_top/3.edn_intr_test.1359315377 May 30 03:35:09 PM PDT 24 May 30 03:35:12 PM PDT 24 32677011 ps
T975 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.906958698 May 30 03:35:09 PM PDT 24 May 30 03:35:13 PM PDT 24 482143051 ps
T976 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2109320197 May 30 03:35:06 PM PDT 24 May 30 03:35:12 PM PDT 24 281064441 ps
T977 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1059360889 May 30 03:35:36 PM PDT 24 May 30 03:35:39 PM PDT 24 290944655 ps
T978 /workspace/coverage/cover_reg_top/28.edn_intr_test.2007713954 May 30 03:36:20 PM PDT 24 May 30 03:36:24 PM PDT 24 21261176 ps
T979 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3553392820 May 30 03:35:30 PM PDT 24 May 30 03:35:32 PM PDT 24 32196619 ps
T980 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1193887971 May 30 03:35:31 PM PDT 24 May 30 03:35:36 PM PDT 24 254864985 ps

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.582113109
Short name T1
Test name
Test status
Simulation time 25684712845 ps
CPU time 310.19 seconds
Started May 30 02:02:28 PM PDT 24
Finished May 30 02:07:39 PM PDT 24
Peak memory 223148 kb
Host smart-3204ff0e-adc2-4a24-9d39-7225b9c4beab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582113109 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.582113109
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/211.edn_genbits.1239964412
Short name T127
Test name
Test status
Simulation time 76423197 ps
CPU time 1.74 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 218212 kb
Host smart-2fa9697c-c548-4c12-a70f-e8edce4d0b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239964412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1239964412
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2293914816
Short name T21
Test name
Test status
Simulation time 68598241 ps
CPU time 1.06 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:17 PM PDT 24
Peak memory 217796 kb
Host smart-c2088134-da05-4261-9eeb-499acc1ef611
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293914816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2293914816
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1854598799
Short name T18
Test name
Test status
Simulation time 1001860916 ps
CPU time 4.38 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:30 PM PDT 24
Peak memory 234828 kb
Host smart-d1251bce-9d91-45de-ab02-04a4fd5c14d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854598799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1854598799
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/28.edn_err.3681577760
Short name T15
Test name
Test status
Simulation time 29165009 ps
CPU time 0.97 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:17 PM PDT 24
Peak memory 223232 kb
Host smart-855d7c37-c8b3-4418-ba59-df6d434c4d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681577760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3681577760
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/34.edn_alert.575871676
Short name T34
Test name
Test status
Simulation time 98535244 ps
CPU time 1.33 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 215392 kb
Host smart-5b70de04-64ee-4649-aae5-0856ecbf2a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575871676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.575871676
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3996606072
Short name T10
Test name
Test status
Simulation time 130868018 ps
CPU time 1.41 seconds
Started May 30 02:03:42 PM PDT 24
Finished May 30 02:03:44 PM PDT 24
Peak memory 216820 kb
Host smart-5872fe0c-a1bb-4de3-b3a6-12a35d12c473
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996606072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3996606072
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3182815780
Short name T160
Test name
Test status
Simulation time 87083417558 ps
CPU time 999.95 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:20:07 PM PDT 24
Peak memory 221856 kb
Host smart-eeaf4f56-f634-4634-89eb-8b797fb5a20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182815780 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3182815780
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.edn_alert.413180384
Short name T75
Test name
Test status
Simulation time 31932144 ps
CPU time 1.34 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:21 PM PDT 24
Peak memory 215348 kb
Host smart-2b309030-cf11-4ce8-923e-127f9fa907ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413180384 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.413180384
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/206.edn_genbits.3103875029
Short name T148
Test name
Test status
Simulation time 48118490 ps
CPU time 1.39 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 219428 kb
Host smart-c2032b9b-83b0-45af-830f-2f09f6a6f7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103875029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3103875029
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.3866590160
Short name T116
Test name
Test status
Simulation time 30092095 ps
CPU time 0.96 seconds
Started May 30 02:01:16 PM PDT 24
Finished May 30 02:01:18 PM PDT 24
Peak memory 206776 kb
Host smart-cc8525b8-b4bd-41b5-b8fb-a6afcfdde554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866590160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.3866590160
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/40.edn_alert.3709767325
Short name T166
Test name
Test status
Simulation time 21952989 ps
CPU time 1.12 seconds
Started May 30 02:03:40 PM PDT 24
Finished May 30 02:03:41 PM PDT 24
Peak memory 215392 kb
Host smart-3b71fe8f-18ae-44c9-b3df-e9082376b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709767325 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3709767325
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/48.edn_err.2828575731
Short name T102
Test name
Test status
Simulation time 23611284 ps
CPU time 1.02 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 229064 kb
Host smart-51b2b4fa-13e3-4dc5-a752-0dddb159900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828575731 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2828575731
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3557764718
Short name T216
Test name
Test status
Simulation time 43463244 ps
CPU time 0.84 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:35 PM PDT 24
Peak memory 206184 kb
Host smart-41390837-ed0f-417e-99c8-5d5834d338ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557764718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3557764718
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_disable.3428562853
Short name T87
Test name
Test status
Simulation time 10246954 ps
CPU time 0.91 seconds
Started May 30 02:01:16 PM PDT 24
Finished May 30 02:01:18 PM PDT 24
Peak memory 216104 kb
Host smart-c8f6844c-c5b1-4e20-bb9b-c08c2d098a3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428562853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3428562853
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/29.edn_alert.3262145737
Short name T570
Test name
Test status
Simulation time 24543870 ps
CPU time 1.22 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 215340 kb
Host smart-f3210e77-3458-45da-b8b5-aca5d0811616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262145737 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3262145737
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1163471943
Short name T258
Test name
Test status
Simulation time 90632383 ps
CPU time 1.69 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206236 kb
Host smart-4643b9ea-76f1-459f-868e-4d3ef7de82ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163471943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1163471943
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/4.edn_disable.4157091793
Short name T177
Test name
Test status
Simulation time 42039431 ps
CPU time 0.89 seconds
Started May 30 02:01:37 PM PDT 24
Finished May 30 02:01:39 PM PDT 24
Peak memory 216212 kb
Host smart-45394390-a51b-412b-bb4a-31fbf6a3c5a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157091793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.4157091793
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.871575739
Short name T190
Test name
Test status
Simulation time 23253694 ps
CPU time 0.87 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 216080 kb
Host smart-065c8fd1-bebd-48d0-913c-fa9e87ffcd10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871575739 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.871575739
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2475872104
Short name T187
Test name
Test status
Simulation time 39618838 ps
CPU time 1.12 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:15 PM PDT 24
Peak memory 216576 kb
Host smart-78e835e6-caa5-415a-bf95-28fd208981e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475872104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2475872104
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3487449192
Short name T9
Test name
Test status
Simulation time 56183991 ps
CPU time 1.1 seconds
Started May 30 02:01:26 PM PDT 24
Finished May 30 02:01:28 PM PDT 24
Peak memory 216680 kb
Host smart-abb0b000-099e-46fd-876c-1e9f452f436e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487449192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3487449192
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/82.edn_genbits.2358032536
Short name T12
Test name
Test status
Simulation time 274914152 ps
CPU time 1.62 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 219600 kb
Host smart-953542d8-eac7-4c6c-a434-c2c84f5df7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358032536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2358032536
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.3684300049
Short name T288
Test name
Test status
Simulation time 115941302 ps
CPU time 1.29 seconds
Started May 30 02:04:49 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 218352 kb
Host smart-47e1a676-65a3-4b7f-9d1f-45e49607a96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684300049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3684300049
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.955561674
Short name T120
Test name
Test status
Simulation time 21027307 ps
CPU time 1.08 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215280 kb
Host smart-d5a1688c-559d-42f1-acb7-a5477fd94b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955561674 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.955561674
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/12.edn_disable.1429771625
Short name T26
Test name
Test status
Simulation time 15964470 ps
CPU time 0.82 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:17 PM PDT 24
Peak memory 215240 kb
Host smart-4ed3152e-6cb6-44f6-bcbc-8560726eda2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429771625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1429771625
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable.1141469855
Short name T97
Test name
Test status
Simulation time 10988562 ps
CPU time 0.9 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 215704 kb
Host smart-495f8124-e0dc-4461-98c2-8a34497f8c28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141469855 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1141469855
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/15.edn_intr.385836592
Short name T123
Test name
Test status
Simulation time 20528745 ps
CPU time 1.12 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 215352 kb
Host smart-8c90403f-4fa3-4535-908d-917e63340b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385836592 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.385836592
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/10.edn_disable.1674263404
Short name T92
Test name
Test status
Simulation time 28864625 ps
CPU time 0.81 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 216052 kb
Host smart-59ff60a3-2228-4661-b451-0f24ad70c546
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674263404 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1674263404
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2666954583
Short name T479
Test name
Test status
Simulation time 101926616 ps
CPU time 1.19 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 219028 kb
Host smart-463371fd-2099-4da3-96a0-5d3b8388e137
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666954583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2666954583
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2261824850
Short name T463
Test name
Test status
Simulation time 75468234 ps
CPU time 1.13 seconds
Started May 30 02:02:18 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 219252 kb
Host smart-90ef98b5-9764-4edc-8ca3-f13a08b7c395
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261824850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2261824850
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2819560455
Short name T180
Test name
Test status
Simulation time 55029321 ps
CPU time 1.2 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 216528 kb
Host smart-a41bb8da-e17d-4e62-9fd8-ea81c7132fb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819560455 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2819560455
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2092592361
Short name T191
Test name
Test status
Simulation time 27753805 ps
CPU time 1.15 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 216684 kb
Host smart-4d67541e-a5e1-4f50-9ba4-7cda8e3bbf41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092592361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2092592361
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.1056472864
Short name T195
Test name
Test status
Simulation time 28399714 ps
CPU time 0.83 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:08 PM PDT 24
Peak memory 216008 kb
Host smart-5af4758a-e197-4ec8-8b14-93992b46fd96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056472864 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1056472864
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.1872857592
Short name T94
Test name
Test status
Simulation time 38426162 ps
CPU time 0.88 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 218032 kb
Host smart-390aa103-3921-4b02-82ec-18c0eba55529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872857592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1872857592
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2617281898
Short name T22
Test name
Test status
Simulation time 48548273 ps
CPU time 1.49 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 216520 kb
Host smart-4c93c70a-933b-41b1-8c5c-5c87f3e3bf03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617281898 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2617281898
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3344798648
Short name T100
Test name
Test status
Simulation time 45270315 ps
CPU time 0.97 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 223364 kb
Host smart-05a16b08-890d-4b9b-b802-a6e36312fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344798648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3344798648
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/23.edn_alert_test.3060855551
Short name T317
Test name
Test status
Simulation time 17374148 ps
CPU time 0.98 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 206232 kb
Host smart-3dbad025-9234-401d-8efc-1c56da943f19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060855551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3060855551
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_regwen.2489197072
Short name T262
Test name
Test status
Simulation time 17150365 ps
CPU time 1.02 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 206820 kb
Host smart-3bfc4b5d-759f-4a66-9bdc-c998fc06a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489197072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2489197072
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/154.edn_genbits.3300938648
Short name T517
Test name
Test status
Simulation time 512257058 ps
CPU time 4.7 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:46 PM PDT 24
Peak memory 215028 kb
Host smart-ef25e307-fa90-4e52-b666-0f3f20ba7440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300938648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3300938648
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3981945685
Short name T257
Test name
Test status
Simulation time 363803733 ps
CPU time 2.5 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:21 PM PDT 24
Peak memory 214392 kb
Host smart-8537eb91-d7e0-4dd1-8e7e-5518a3a0e0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981945685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3981945685
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_stress_all.3877980319
Short name T761
Test name
Test status
Simulation time 786281752 ps
CPU time 5.14 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:19 PM PDT 24
Peak memory 216628 kb
Host smart-2480db13-1459-4f0e-9670-e905c31013bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877980319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3877980319
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_alert.1042950690
Short name T31
Test name
Test status
Simulation time 63988777 ps
CPU time 1.23 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:09 PM PDT 24
Peak memory 215408 kb
Host smart-d9264af2-6d27-4371-86b2-71cc506cf04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042950690 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1042950690
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/151.edn_genbits.581593687
Short name T161
Test name
Test status
Simulation time 44962531 ps
CPU time 1.51 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 217952 kb
Host smart-98ae78de-47ed-4e64-bc5e-d8fbe4976a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581593687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.581593687
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1015143734
Short name T154
Test name
Test status
Simulation time 78889212 ps
CPU time 1.2 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 217052 kb
Host smart-c50b7a9f-9d56-4c16-a5cd-4d16a71426cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015143734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1015143734
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1145961285
Short name T393
Test name
Test status
Simulation time 39591709 ps
CPU time 1.12 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:30 PM PDT 24
Peak memory 215388 kb
Host smart-87572a36-95d9-46a0-8274-37c9b473beaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145961285 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1145961285
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/5.edn_regwen.1849581348
Short name T266
Test name
Test status
Simulation time 24562985 ps
CPU time 0.98 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:48 PM PDT 24
Peak memory 206816 kb
Host smart-72880e01-bae4-4350-b81c-086c0743f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849581348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1849581348
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1220679655
Short name T126
Test name
Test status
Simulation time 255477021867 ps
CPU time 1446.37 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:27:23 PM PDT 24
Peak memory 224212 kb
Host smart-93602983-d06b-43fa-9cf2-20e1a3610b9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220679655 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1220679655
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.edn_intr.3868278626
Short name T117
Test name
Test status
Simulation time 21778251 ps
CPU time 1.04 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215440 kb
Host smart-dca8315e-17b8-40f8-9d34-3b3b2c0873e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868278626 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3868278626
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/1.edn_genbits.2374166973
Short name T372
Test name
Test status
Simulation time 113884162 ps
CPU time 1.29 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:16 PM PDT 24
Peak memory 216696 kb
Host smart-0add8643-1ef3-4f0d-874a-d80a67696460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374166973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2374166973
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3592134075
Short name T796
Test name
Test status
Simulation time 133514490694 ps
CPU time 1451.8 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:26:19 PM PDT 24
Peak memory 234320 kb
Host smart-1ad463a6-472b-4ee0-b0a7-b14a2b7edab6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592134075 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3592134075
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.1175336815
Short name T297
Test name
Test status
Simulation time 92752931 ps
CPU time 1.85 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 218112 kb
Host smart-c48a58c5-ac5a-4d0e-b74c-2384a97082a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175336815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1175336815
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2942416720
Short name T290
Test name
Test status
Simulation time 33899252 ps
CPU time 1.43 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 219360 kb
Host smart-cc8537f7-d122-4053-9916-3d7a85611c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942416720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2942416720
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2576484281
Short name T285
Test name
Test status
Simulation time 83706872 ps
CPU time 1.51 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 218108 kb
Host smart-f7bd6077-a564-4d4d-8296-be4ff238ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576484281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2576484281
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4000100523
Short name T578
Test name
Test status
Simulation time 41911040 ps
CPU time 1.45 seconds
Started May 30 02:04:37 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 216720 kb
Host smart-0781eef4-3065-4f5c-b189-4c8c4f539283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000100523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4000100523
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1379507885
Short name T813
Test name
Test status
Simulation time 89888312 ps
CPU time 1.21 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 218244 kb
Host smart-a7230f15-e690-4632-8518-43a743abd03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379507885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1379507885
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.2508656957
Short name T264
Test name
Test status
Simulation time 49017954 ps
CPU time 0.92 seconds
Started May 30 02:01:24 PM PDT 24
Finished May 30 02:01:26 PM PDT 24
Peak memory 206796 kb
Host smart-e987c420-b864-425a-aa89-8393bb97851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508656957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2508656957
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1305979784
Short name T253
Test name
Test status
Simulation time 71453127 ps
CPU time 1.24 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 216636 kb
Host smart-f80bc533-4d92-479b-87be-7b1cc2393e97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305979784 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1305979784
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.1710262772
Short name T242
Test name
Test status
Simulation time 75496478 ps
CPU time 1.43 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:12 PM PDT 24
Peak memory 217464 kb
Host smart-892430cd-9569-4392-85d3-31f881318fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710262772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1710262772
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_genbits.732225399
Short name T299
Test name
Test status
Simulation time 96729375 ps
CPU time 1.29 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 219328 kb
Host smart-156599b8-b198-4733-9b6c-01ec7bf089be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732225399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.732225399
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.4198968988
Short name T158
Test name
Test status
Simulation time 34039316 ps
CPU time 0.87 seconds
Started May 30 02:02:28 PM PDT 24
Finished May 30 02:02:29 PM PDT 24
Peak memory 215272 kb
Host smart-fa0c6f99-43f6-4158-a43d-611ad555e5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198968988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4198968988
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.2808361382
Short name T73
Test name
Test status
Simulation time 176071370 ps
CPU time 1.2 seconds
Started May 30 02:01:15 PM PDT 24
Finished May 30 02:01:17 PM PDT 24
Peak memory 215412 kb
Host smart-5c1ac2ab-932c-4a19-887d-bea4764a8295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808361382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2808361382
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/12.edn_err.1955856046
Short name T41
Test name
Test status
Simulation time 34402895 ps
CPU time 1.19 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:17 PM PDT 24
Peak memory 229180 kb
Host smart-143bae62-5e1b-4859-9e32-9376d6cc0c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955856046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1955856046
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/122.edn_genbits.472219354
Short name T441
Test name
Test status
Simulation time 52678668 ps
CPU time 1.7 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 218148 kb
Host smart-4caca714-73f2-4bc7-9adf-6b66867049e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472219354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.472219354
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3268874265
Short name T861
Test name
Test status
Simulation time 18155324 ps
CPU time 0.98 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206232 kb
Host smart-2ca338cb-2f74-4364-9c61-305a0f0fd415
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268874265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3268874265
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2109320197
Short name T976
Test name
Test status
Simulation time 281064441 ps
CPU time 5.11 seconds
Started May 30 03:35:06 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 206376 kb
Host smart-20186c96-a334-4658-a57f-2f3554ba9e66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109320197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2109320197
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3483392521
Short name T219
Test name
Test status
Simulation time 13689848 ps
CPU time 0.89 seconds
Started May 30 03:35:09 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 206212 kb
Host smart-0330c084-9852-47a7-b1c5-a43be80e0d86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483392521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3483392521
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4144718102
Short name T940
Test name
Test status
Simulation time 91493329 ps
CPU time 1.27 seconds
Started May 30 03:35:11 PM PDT 24
Finished May 30 03:35:13 PM PDT 24
Peak memory 214600 kb
Host smart-253f4ac4-bf1e-4450-af6c-a4c4559077dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144718102 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4144718102
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3237600619
Short name T227
Test name
Test status
Simulation time 14903112 ps
CPU time 0.95 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206124 kb
Host smart-ba1d76f3-82d0-492d-8eca-3b1994309656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237600619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3237600619
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3734676625
Short name T877
Test name
Test status
Simulation time 13620432 ps
CPU time 0.86 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:09 PM PDT 24
Peak memory 206076 kb
Host smart-68a534a3-ae8e-45ef-b432-630feeb83733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734676625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3734676625
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.2478329786
Short name T944
Test name
Test status
Simulation time 21478733 ps
CPU time 1.11 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206300 kb
Host smart-2f2f10b0-1cf4-4c7f-8bf3-ba0d93ac1710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478329786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.2478329786
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.666383242
Short name T864
Test name
Test status
Simulation time 252476237 ps
CPU time 3.84 seconds
Started May 30 03:35:09 PM PDT 24
Finished May 30 03:35:14 PM PDT 24
Peak memory 214404 kb
Host smart-1b0dd73a-4c66-404f-8454-472225c9391d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666383242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.666383242
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.906958698
Short name T975
Test name
Test status
Simulation time 482143051 ps
CPU time 2.46 seconds
Started May 30 03:35:09 PM PDT 24
Finished May 30 03:35:13 PM PDT 24
Peak memory 206180 kb
Host smart-94a486ce-05c3-4c6f-a80a-5cf363e80cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906958698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.906958698
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4175397830
Short name T231
Test name
Test status
Simulation time 89774216 ps
CPU time 1 seconds
Started May 30 03:35:10 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 206132 kb
Host smart-7503c954-cd7c-4bf3-b875-22d04ec9b70b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175397830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4175397830
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3353843482
Short name T904
Test name
Test status
Simulation time 40727457 ps
CPU time 2.11 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206148 kb
Host smart-fd47bf19-6019-4d7e-97e2-a27b9bb16c25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353843482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3353843482
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3006194351
Short name T959
Test name
Test status
Simulation time 22512500 ps
CPU time 0.86 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:09 PM PDT 24
Peak memory 206212 kb
Host smart-2420676a-24b1-446c-a3fa-cd16f6ca73cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006194351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3006194351
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.88993126
Short name T946
Test name
Test status
Simulation time 25496296 ps
CPU time 1.4 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 214444 kb
Host smart-084eb0d4-d838-476f-813d-35646df9346d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88993126 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.88993126
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.45277202
Short name T920
Test name
Test status
Simulation time 14510506 ps
CPU time 0.9 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206192 kb
Host smart-29bd237f-a6af-4a34-9f6a-ae1fdc24f7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45277202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.45277202
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2431823216
Short name T866
Test name
Test status
Simulation time 16932720 ps
CPU time 0.88 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206084 kb
Host smart-94f641cb-7801-464d-9658-a47cb6b04af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431823216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2431823216
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.546326101
Short name T240
Test name
Test status
Simulation time 39482867 ps
CPU time 1.09 seconds
Started May 30 03:35:09 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206216 kb
Host smart-e9272a2f-599d-4a3c-ae58-e8034587de71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546326101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.546326101
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1141947328
Short name T850
Test name
Test status
Simulation time 86390836 ps
CPU time 1.72 seconds
Started May 30 03:35:06 PM PDT 24
Finished May 30 03:35:09 PM PDT 24
Peak memory 218188 kb
Host smart-ba5a5c87-8f26-41f7-a7c0-ed352fac1924
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141947328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1141947328
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3873304317
Short name T925
Test name
Test status
Simulation time 103094879 ps
CPU time 1.45 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 214388 kb
Host smart-cf5f3a4c-7717-4411-861b-23a15a702e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873304317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3873304317
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3823310470
Short name T958
Test name
Test status
Simulation time 27869851 ps
CPU time 0.96 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206352 kb
Host smart-ba5d0e29-54f1-44ea-b6c1-93f0f1a90b78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823310470 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3823310470
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3868851612
Short name T221
Test name
Test status
Simulation time 14350361 ps
CPU time 0.95 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 206196 kb
Host smart-40860550-06d9-4b27-9a5e-cffdba41d84a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868851612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3868851612
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3985196913
Short name T899
Test name
Test status
Simulation time 38734117 ps
CPU time 0.84 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:35 PM PDT 24
Peak memory 206076 kb
Host smart-46b97015-4777-4e24-ae59-75dd3eaab521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985196913 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3985196913
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.4210510488
Short name T911
Test name
Test status
Simulation time 31237055 ps
CPU time 1.37 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:35 PM PDT 24
Peak memory 206256 kb
Host smart-26edc406-927b-41c8-8f6a-b8025ef761cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210510488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.4210510488
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.687997326
Short name T895
Test name
Test status
Simulation time 42519195 ps
CPU time 1.62 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214412 kb
Host smart-c6cb0aeb-d12f-4947-a7ab-6472f5d3b883
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687997326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.687997326
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1820871067
Short name T913
Test name
Test status
Simulation time 46695275 ps
CPU time 1.6 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214420 kb
Host smart-5bb2ce39-8e5c-4308-8ef4-7674ff33a661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820871067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1820871067
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.13703525
Short name T970
Test name
Test status
Simulation time 27574492 ps
CPU time 0.95 seconds
Started May 30 03:35:34 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206240 kb
Host smart-2ba32b17-7eee-40bb-a1d4-72163264a2d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13703525 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.13703525
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.795944458
Short name T968
Test name
Test status
Simulation time 23852630 ps
CPU time 0.9 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:34 PM PDT 24
Peak memory 206204 kb
Host smart-86dc568c-155b-452c-8cc7-25e5ce99ac55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795944458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.795944458
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3647378421
Short name T869
Test name
Test status
Simulation time 19498147 ps
CPU time 0.93 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 206056 kb
Host smart-b2be070f-cd45-494d-a8fc-4e3451769784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647378421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3647378421
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2358436900
Short name T236
Test name
Test status
Simulation time 101914639 ps
CPU time 1.35 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:34 PM PDT 24
Peak memory 206228 kb
Host smart-62104aa7-4f06-4313-aefb-59d0ed25bff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358436900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2358436900
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2586252490
Short name T939
Test name
Test status
Simulation time 155963797 ps
CPU time 5.29 seconds
Started May 30 03:35:34 PM PDT 24
Finished May 30 03:35:40 PM PDT 24
Peak memory 214516 kb
Host smart-94a5e0de-27f7-4dd4-ad97-b0ed0cc0bba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586252490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2586252490
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2738421816
Short name T961
Test name
Test status
Simulation time 745853120 ps
CPU time 2.66 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206296 kb
Host smart-0fdb708f-0a5a-48c1-a7dd-8e595ce19f41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738421816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2738421816
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.4141552801
Short name T933
Test name
Test status
Simulation time 66052124 ps
CPU time 1.44 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214436 kb
Host smart-4ea77f86-c3a1-41cc-97d3-b8fcf5efc108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141552801 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.4141552801
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2370431956
Short name T892
Test name
Test status
Simulation time 14866675 ps
CPU time 0.9 seconds
Started May 30 03:35:34 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206204 kb
Host smart-67b3c578-f038-42c5-90d2-9ddd2131d902
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370431956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2370431956
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2871444982
Short name T964
Test name
Test status
Simulation time 106644045 ps
CPU time 0.84 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206000 kb
Host smart-5bbdc161-c976-487a-9367-611a3f980d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871444982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2871444982
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2090107145
Short name T897
Test name
Test status
Simulation time 49554891 ps
CPU time 1.22 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206192 kb
Host smart-589a9076-0ca5-48ed-b386-922c1894af11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090107145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2090107145
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1193887971
Short name T980
Test name
Test status
Simulation time 254864985 ps
CPU time 3.64 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214476 kb
Host smart-b7c40d8d-a080-48fe-85fc-a5334dc210c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193887971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1193887971
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1019102643
Short name T903
Test name
Test status
Simulation time 40853633 ps
CPU time 1.18 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214484 kb
Host smart-dff82fec-cdcd-4cbe-8a8f-7bee60b506c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019102643 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1019102643
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2227221880
Short name T947
Test name
Test status
Simulation time 18301978 ps
CPU time 0.87 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206068 kb
Host smart-dbeb08b6-e2cd-4c77-bc38-3401daa2cb6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227221880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2227221880
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3959464058
Short name T886
Test name
Test status
Simulation time 20027243 ps
CPU time 1.14 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 206180 kb
Host smart-2e0e42ef-bed5-49e6-80fe-e6f38c61cb88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959464058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3959464058
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.982347027
Short name T900
Test name
Test status
Simulation time 47981016 ps
CPU time 1.76 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214428 kb
Host smart-3f6d5d69-0bea-4cd0-a075-3be3331a7b30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982347027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.982347027
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.454923677
Short name T910
Test name
Test status
Simulation time 75683314 ps
CPU time 2.01 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206188 kb
Host smart-14516556-acb1-4609-95e1-b6596b3ad110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454923677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.454923677
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1221240881
Short name T888
Test name
Test status
Simulation time 86316506 ps
CPU time 1.89 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 214492 kb
Host smart-6ce991f4-c2ab-47dc-bbb2-bb277588a8dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221240881 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1221240881
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3116118205
Short name T893
Test name
Test status
Simulation time 12978728 ps
CPU time 0.92 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 206156 kb
Host smart-3f852f0a-d101-4abe-a807-0a69db341918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116118205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3116118205
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2237784954
Short name T889
Test name
Test status
Simulation time 14491092 ps
CPU time 0.86 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206128 kb
Host smart-d90771bc-ba72-4305-845c-525f01ca6440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237784954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2237784954
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2656090994
Short name T223
Test name
Test status
Simulation time 56124711 ps
CPU time 1.26 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206184 kb
Host smart-fd9969a4-99f4-4dad-8b40-60f638a296dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656090994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2656090994
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3700582206
Short name T873
Test name
Test status
Simulation time 444881166 ps
CPU time 2.5 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214420 kb
Host smart-050b9a75-6e6a-4808-af1c-a183baa2a6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700582206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3700582206
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4213163213
Short name T256
Test name
Test status
Simulation time 63666015 ps
CPU time 1.82 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206480 kb
Host smart-792f1f3a-a63b-471c-8aa7-310f5d8ab1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213163213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4213163213
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.909090890
Short name T868
Test name
Test status
Simulation time 23375450 ps
CPU time 1.57 seconds
Started May 30 03:35:41 PM PDT 24
Finished May 30 03:35:44 PM PDT 24
Peak memory 214484 kb
Host smart-5a85e60a-8735-4274-9057-c9185ee005c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909090890 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.909090890
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2776285244
Short name T905
Test name
Test status
Simulation time 21230458 ps
CPU time 0.88 seconds
Started May 30 03:35:35 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206144 kb
Host smart-911b3252-b44e-458f-b8e7-0273c873edb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776285244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2776285244
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1202299423
Short name T941
Test name
Test status
Simulation time 15328579 ps
CPU time 0.91 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206036 kb
Host smart-941479fc-68c4-4994-9bb3-ab008c189b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202299423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1202299423
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1059360889
Short name T977
Test name
Test status
Simulation time 290944655 ps
CPU time 1.35 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206204 kb
Host smart-e574b52b-7f32-4c41-b11d-1a95731f587b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059360889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1059360889
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.888843487
Short name T906
Test name
Test status
Simulation time 244125985 ps
CPU time 2.53 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 214444 kb
Host smart-8c7fcb95-13ce-4beb-bc3f-7a10d6130ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888843487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.888843487
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3028439515
Short name T249
Test name
Test status
Simulation time 93121170 ps
CPU time 1.45 seconds
Started May 30 03:35:39 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206136 kb
Host smart-499347e5-d4d9-48e9-ba22-7c429f474e62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028439515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3028439515
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1563621616
Short name T859
Test name
Test status
Simulation time 89022142 ps
CPU time 1.72 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 214492 kb
Host smart-58da01e2-2a6d-4de2-b02c-fb88eda6d30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563621616 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1563621616
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2503732957
Short name T229
Test name
Test status
Simulation time 16317959 ps
CPU time 0.91 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206208 kb
Host smart-eb8f270d-654c-4221-ba84-e51e1686532a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503732957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2503732957
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3664414492
Short name T894
Test name
Test status
Simulation time 15068936 ps
CPU time 0.91 seconds
Started May 30 03:35:39 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206064 kb
Host smart-5ce6a103-27f2-41d4-9a43-a895bfeaa512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664414492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3664414492
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2191799000
Short name T220
Test name
Test status
Simulation time 23589260 ps
CPU time 0.97 seconds
Started May 30 03:35:39 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206232 kb
Host smart-a7e65b6c-cb1b-457b-9678-4afa8337d4d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191799000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2191799000
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1077245193
Short name T865
Test name
Test status
Simulation time 123761606 ps
CPU time 4.22 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:45 PM PDT 24
Peak memory 214456 kb
Host smart-bb94ad05-f29b-4da7-af59-64454c2771d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077245193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1077245193
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.166249346
Short name T247
Test name
Test status
Simulation time 113672982 ps
CPU time 2.68 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:44 PM PDT 24
Peak memory 206256 kb
Host smart-32862c04-ff90-4075-b195-fd2216d425d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166249346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.166249346
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3842316740
Short name T935
Test name
Test status
Simulation time 52447592 ps
CPU time 1.32 seconds
Started May 30 03:35:43 PM PDT 24
Finished May 30 03:35:45 PM PDT 24
Peak memory 214420 kb
Host smart-e15c3341-17c4-4ddb-8482-a194488c160a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842316740 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3842316740
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1628158607
Short name T857
Test name
Test status
Simulation time 15609479 ps
CPU time 0.92 seconds
Started May 30 03:35:41 PM PDT 24
Finished May 30 03:35:43 PM PDT 24
Peak memory 206188 kb
Host smart-153e3a63-9e2a-4fb1-bf72-de257779f42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628158607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1628158607
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1573697288
Short name T963
Test name
Test status
Simulation time 27521990 ps
CPU time 0.77 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:40 PM PDT 24
Peak memory 206000 kb
Host smart-92edf855-3581-4252-a95e-9cf06806020c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573697288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1573697288
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2265125536
Short name T936
Test name
Test status
Simulation time 55049929 ps
CPU time 1.33 seconds
Started May 30 03:35:40 PM PDT 24
Finished May 30 03:35:43 PM PDT 24
Peak memory 206140 kb
Host smart-653f65de-7031-48cb-b322-70021d21f27c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265125536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2265125536
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3975861630
Short name T882
Test name
Test status
Simulation time 253519317 ps
CPU time 3.36 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 218740 kb
Host smart-4cce64bd-5d6a-4e32-864b-ce8f1b299d94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975861630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3975861630
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1794764127
Short name T955
Test name
Test status
Simulation time 67717066 ps
CPU time 1.45 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206228 kb
Host smart-7e3a2a1a-e3d3-47c7-b34b-befbd240581b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794764127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1794764127
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3190883089
Short name T919
Test name
Test status
Simulation time 14473598 ps
CPU time 1.08 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 214488 kb
Host smart-b0a16abd-eab1-4d23-ac96-59fb9365f22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190883089 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3190883089
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.490050836
Short name T235
Test name
Test status
Simulation time 19659151 ps
CPU time 0.82 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 206024 kb
Host smart-b3af588a-8a3e-4ef0-af7d-32654081a3d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490050836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.490050836
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2801225841
Short name T858
Test name
Test status
Simulation time 44734896 ps
CPU time 0.82 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206036 kb
Host smart-f8d0bc53-b121-4a14-ad92-23e1a07a04a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801225841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2801225841
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3235876053
Short name T874
Test name
Test status
Simulation time 29067395 ps
CPU time 1.18 seconds
Started May 30 03:35:39 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206240 kb
Host smart-808e407c-64f2-4cc7-a05a-e79c726ad743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235876053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3235876053
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2779522723
Short name T853
Test name
Test status
Simulation time 112881053 ps
CPU time 4.02 seconds
Started May 30 03:35:41 PM PDT 24
Finished May 30 03:35:47 PM PDT 24
Peak memory 214384 kb
Host smart-e4d874e0-9731-4ec5-88db-ba797d6d59a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779522723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2779522723
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2354571481
Short name T960
Test name
Test status
Simulation time 127692260 ps
CPU time 1.41 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206216 kb
Host smart-b8a4531b-5de0-4a13-9d56-eec1923e26aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354571481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2354571481
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.662734606
Short name T870
Test name
Test status
Simulation time 29442180 ps
CPU time 1.95 seconds
Started May 30 03:35:40 PM PDT 24
Finished May 30 03:35:43 PM PDT 24
Peak memory 214348 kb
Host smart-e7a10348-5424-4e54-b217-13216f772097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662734606 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.662734606
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.680437980
Short name T234
Test name
Test status
Simulation time 14411511 ps
CPU time 0.9 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206132 kb
Host smart-08f94520-c982-4fa3-ad25-1abedd96caf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680437980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.680437980
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4142624999
Short name T915
Test name
Test status
Simulation time 54594182 ps
CPU time 0.82 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 205944 kb
Host smart-a41ead5a-8b15-4a15-8ac4-537c7ea4f96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142624999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4142624999
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1759909556
Short name T918
Test name
Test status
Simulation time 36667220 ps
CPU time 1.44 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 206212 kb
Host smart-10711c72-f382-4789-82c4-de2821424bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759909556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1759909556
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3769718969
Short name T914
Test name
Test status
Simulation time 130692915 ps
CPU time 2.19 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 214424 kb
Host smart-961f6021-bb44-45ae-b079-ac943b05a5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769718969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3769718969
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1984985108
Short name T248
Test name
Test status
Simulation time 112504695 ps
CPU time 1.45 seconds
Started May 30 03:35:39 PM PDT 24
Finished May 30 03:35:43 PM PDT 24
Peak memory 206172 kb
Host smart-22b94985-d48d-4777-ae13-58d4d0099152
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984985108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1984985108
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3463696187
Short name T931
Test name
Test status
Simulation time 59090223 ps
CPU time 1.25 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206232 kb
Host smart-34d09424-8486-4b9f-a39e-1680a4275c9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463696187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3463696187
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.542241977
Short name T232
Test name
Test status
Simulation time 543373910 ps
CPU time 3.54 seconds
Started May 30 03:35:10 PM PDT 24
Finished May 30 03:35:15 PM PDT 24
Peak memory 206308 kb
Host smart-4bf729ef-d331-4310-a10a-c9c6328381e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542241977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.542241977
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1956437282
Short name T246
Test name
Test status
Simulation time 15015469 ps
CPU time 0.94 seconds
Started May 30 03:35:06 PM PDT 24
Finished May 30 03:35:09 PM PDT 24
Peak memory 206192 kb
Host smart-44757033-6120-459f-9ae6-ea7a1fe00ad5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956437282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1956437282
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1553126214
Short name T851
Test name
Test status
Simulation time 107852783 ps
CPU time 0.95 seconds
Started May 30 03:35:10 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 206208 kb
Host smart-fbf2a878-fb2c-4658-9a66-51a33b8fa87f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553126214 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1553126214
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4249865923
Short name T929
Test name
Test status
Simulation time 17767235 ps
CPU time 0.94 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206212 kb
Host smart-6b1785bb-f326-4d11-8ada-4b93180c6fd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249865923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4249865923
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1073200102
Short name T926
Test name
Test status
Simulation time 38125827 ps
CPU time 0.82 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 205904 kb
Host smart-9c094e0e-e9ac-4c93-b264-bf31f64dc6c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073200102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1073200102
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2532017500
Short name T879
Test name
Test status
Simulation time 38673738 ps
CPU time 0.94 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206156 kb
Host smart-8b867049-99ed-4862-993c-46f4e3c3cce2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532017500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2532017500
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3658083771
Short name T953
Test name
Test status
Simulation time 306457384 ps
CPU time 3.1 seconds
Started May 30 03:35:10 PM PDT 24
Finished May 30 03:35:14 PM PDT 24
Peak memory 214484 kb
Host smart-d41b2309-2f3a-4708-a1a9-ca86f78d9cf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658083771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3658083771
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2302404207
Short name T917
Test name
Test status
Simulation time 58187560 ps
CPU time 1.81 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 206200 kb
Host smart-bb66d4ff-eec3-4556-8287-256310c09a71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302404207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2302404207
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2031772568
Short name T898
Test name
Test status
Simulation time 23721685 ps
CPU time 0.85 seconds
Started May 30 03:35:37 PM PDT 24
Finished May 30 03:35:40 PM PDT 24
Peak memory 206176 kb
Host smart-745a8ad1-3031-47dd-a9c0-0cc30287a84d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031772568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2031772568
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3087653968
Short name T916
Test name
Test status
Simulation time 34658865 ps
CPU time 0.81 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:41 PM PDT 24
Peak memory 205996 kb
Host smart-925f4508-fce4-45c7-b4f9-f0a86e07df98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087653968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3087653968
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1210046987
Short name T860
Test name
Test status
Simulation time 29866073 ps
CPU time 0.79 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:40 PM PDT 24
Peak memory 205976 kb
Host smart-5d83ac82-609a-4fab-9a2f-2e9e57eca367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210046987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1210046987
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4175676964
Short name T973
Test name
Test status
Simulation time 14660626 ps
CPU time 0.9 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:39 PM PDT 24
Peak memory 206184 kb
Host smart-ff0f0d18-49f9-4844-b0f1-e5ddff64bf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175676964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4175676964
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.166453797
Short name T872
Test name
Test status
Simulation time 23459879 ps
CPU time 0.86 seconds
Started May 30 03:35:36 PM PDT 24
Finished May 30 03:35:38 PM PDT 24
Peak memory 206084 kb
Host smart-2563d519-e339-4549-b2a7-04d33138c7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166453797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.166453797
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3985871274
Short name T909
Test name
Test status
Simulation time 15687603 ps
CPU time 0.9 seconds
Started May 30 03:35:38 PM PDT 24
Finished May 30 03:35:42 PM PDT 24
Peak memory 206160 kb
Host smart-c52a274d-0af4-47e8-8a69-b81637b74c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985871274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3985871274
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2488335215
Short name T876
Test name
Test status
Simulation time 15627526 ps
CPU time 0.87 seconds
Started May 30 03:36:16 PM PDT 24
Finished May 30 03:36:19 PM PDT 24
Peak memory 206060 kb
Host smart-55d015d9-29bd-4fe1-a2f2-c4122df364a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488335215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2488335215
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1726091395
Short name T852
Test name
Test status
Simulation time 16604585 ps
CPU time 0.94 seconds
Started May 30 03:36:17 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 206072 kb
Host smart-05c7441c-8886-4d42-a13c-526e6d10502e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726091395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1726091395
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2007713954
Short name T978
Test name
Test status
Simulation time 21261176 ps
CPU time 0.87 seconds
Started May 30 03:36:20 PM PDT 24
Finished May 30 03:36:24 PM PDT 24
Peak memory 206068 kb
Host smart-a4e818e1-306f-44bd-adb2-8a86edf9efae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007713954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2007713954
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.669123826
Short name T854
Test name
Test status
Simulation time 24989587 ps
CPU time 0.84 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:15 PM PDT 24
Peak memory 206060 kb
Host smart-6be86cd8-77b3-4281-abc3-abb7a8d7b45d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669123826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.669123826
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3636005464
Short name T228
Test name
Test status
Simulation time 65135201 ps
CPU time 1.49 seconds
Started May 30 03:35:19 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 206228 kb
Host smart-d0894f11-39c4-40b6-a699-b9c44888b39f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636005464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3636005464
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3459513804
Short name T878
Test name
Test status
Simulation time 1083675805 ps
CPU time 6.54 seconds
Started May 30 03:35:16 PM PDT 24
Finished May 30 03:35:24 PM PDT 24
Peak memory 206212 kb
Host smart-5b49516e-72a4-4f87-86f5-40728046ba79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459513804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3459513804
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2561145962
Short name T218
Test name
Test status
Simulation time 20987227 ps
CPU time 0.89 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:10 PM PDT 24
Peak memory 206200 kb
Host smart-55f9eda2-f026-4a67-aa49-55a7b8c2ede1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561145962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2561145962
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1200696925
Short name T937
Test name
Test status
Simulation time 108335487 ps
CPU time 1.58 seconds
Started May 30 03:35:22 PM PDT 24
Finished May 30 03:35:25 PM PDT 24
Peak memory 214492 kb
Host smart-85525bfc-9b8c-426f-b34b-c19996d21467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200696925 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1200696925
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2500498751
Short name T957
Test name
Test status
Simulation time 17718956 ps
CPU time 0.83 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:20 PM PDT 24
Peak memory 206100 kb
Host smart-8fac238e-739c-489d-9f17-648b5b05fdf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500498751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2500498751
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1359315377
Short name T974
Test name
Test status
Simulation time 32677011 ps
CPU time 0.75 seconds
Started May 30 03:35:09 PM PDT 24
Finished May 30 03:35:12 PM PDT 24
Peak memory 205996 kb
Host smart-eef6e86b-8de6-4046-9988-2f6de2a4e264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359315377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1359315377
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3130222011
Short name T217
Test name
Test status
Simulation time 63529958 ps
CPU time 1.35 seconds
Started May 30 03:35:21 PM PDT 24
Finished May 30 03:35:24 PM PDT 24
Peak memory 206200 kb
Host smart-28f8e6b7-2de9-443c-9e29-8d06c091c296
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130222011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3130222011
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3505683309
Short name T901
Test name
Test status
Simulation time 133023359 ps
CPU time 2.6 seconds
Started May 30 03:35:08 PM PDT 24
Finished May 30 03:35:13 PM PDT 24
Peak memory 214412 kb
Host smart-624fd6a0-05cd-4fb9-91c6-25332a294527
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505683309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3505683309
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2602932870
Short name T966
Test name
Test status
Simulation time 355201479 ps
CPU time 2.49 seconds
Started May 30 03:35:07 PM PDT 24
Finished May 30 03:35:11 PM PDT 24
Peak memory 206308 kb
Host smart-edeb355c-b2b1-463f-87fa-dc08cc4bae07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602932870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2602932870
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2679664702
Short name T928
Test name
Test status
Simulation time 40244620 ps
CPU time 0.82 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:16 PM PDT 24
Peak memory 206080 kb
Host smart-a597f9e2-ab30-42ed-8f99-01a957f1a62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679664702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2679664702
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3234384122
Short name T908
Test name
Test status
Simulation time 165596381 ps
CPU time 0.82 seconds
Started May 30 03:36:17 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 206128 kb
Host smart-dc6bee53-d8e1-48f0-b84c-4088a720810a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234384122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3234384122
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.241327822
Short name T972
Test name
Test status
Simulation time 27530108 ps
CPU time 0.9 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206060 kb
Host smart-e8c3676e-992c-400b-a33e-83de557826fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241327822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.241327822
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.139650823
Short name T922
Test name
Test status
Simulation time 22896475 ps
CPU time 0.87 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:16 PM PDT 24
Peak memory 205996 kb
Host smart-78a417c5-3417-41ae-9951-b7cb61b702ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139650823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.139650823
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.1662967399
Short name T887
Test name
Test status
Simulation time 35416156 ps
CPU time 0.86 seconds
Started May 30 03:36:12 PM PDT 24
Finished May 30 03:36:14 PM PDT 24
Peak memory 206084 kb
Host smart-465a648c-08af-4069-a6b7-b09066adae3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662967399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1662967399
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1396825515
Short name T923
Test name
Test status
Simulation time 20357218 ps
CPU time 0.83 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 205944 kb
Host smart-ed285584-b6dc-406e-8806-4d4af2656e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396825515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1396825515
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.390674647
Short name T932
Test name
Test status
Simulation time 24279364 ps
CPU time 0.86 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:21 PM PDT 24
Peak memory 206028 kb
Host smart-23022b29-8da6-4ab3-8463-d2572972433d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390674647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.390674647
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1584494559
Short name T862
Test name
Test status
Simulation time 54639806 ps
CPU time 0.88 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206092 kb
Host smart-a9d04abd-b638-409d-9930-8e9886c440cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584494559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1584494559
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1824412785
Short name T867
Test name
Test status
Simulation time 10860062 ps
CPU time 0.84 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:15 PM PDT 24
Peak memory 206088 kb
Host smart-8492d26c-a54a-47e4-8335-74a29236f908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824412785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1824412785
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1649669338
Short name T885
Test name
Test status
Simulation time 38714733 ps
CPU time 0.8 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:15 PM PDT 24
Peak memory 206032 kb
Host smart-1856660c-7acd-4497-bddd-9c9436dc7098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649669338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1649669338
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3335508752
Short name T880
Test name
Test status
Simulation time 33907830 ps
CPU time 1.59 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:23 PM PDT 24
Peak memory 206204 kb
Host smart-9cbe119d-07ef-41ad-8ee2-16e2179c55c8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335508752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3335508752
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2751958630
Short name T233
Test name
Test status
Simulation time 135543142 ps
CPU time 3.55 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 206200 kb
Host smart-c95018de-64b0-47c1-a721-355fa4ba56c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751958630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2751958630
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.4084047255
Short name T902
Test name
Test status
Simulation time 36039322 ps
CPU time 0.95 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 205940 kb
Host smart-1beef3ef-e089-4c48-9991-9087d7d77dac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084047255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.4084047255
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.179322805
Short name T950
Test name
Test status
Simulation time 17398581 ps
CPU time 1.01 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:20 PM PDT 24
Peak memory 206196 kb
Host smart-7a4c2de8-f412-420e-9c60-3bceab943d41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179322805 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.179322805
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2357789347
Short name T226
Test name
Test status
Simulation time 18365338 ps
CPU time 1.01 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:20 PM PDT 24
Peak memory 206284 kb
Host smart-0b2f403e-b00b-405b-9ee3-51bff999dcbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357789347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2357789347
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1882041932
Short name T948
Test name
Test status
Simulation time 103739081 ps
CPU time 0.85 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:23 PM PDT 24
Peak memory 205964 kb
Host smart-49443ed1-d69d-4258-bed4-03acdcafbc23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882041932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1882041932
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2756785622
Short name T237
Test name
Test status
Simulation time 39588858 ps
CPU time 0.87 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 206168 kb
Host smart-67a9851b-c494-44c6-9988-eb849495bb75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756785622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2756785622
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.51823242
Short name T856
Test name
Test status
Simulation time 274668019 ps
CPU time 4.58 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:24 PM PDT 24
Peak memory 214428 kb
Host smart-0879141f-7a9e-479b-aff4-bb2fe38d6a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51823242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.51823242
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1679599097
Short name T255
Test name
Test status
Simulation time 102703625 ps
CPU time 2.52 seconds
Started May 30 03:35:15 PM PDT 24
Finished May 30 03:35:19 PM PDT 24
Peak memory 206300 kb
Host smart-ed75ed4b-6e90-4258-83c6-c425d9fd7159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679599097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1679599097
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3046442906
Short name T942
Test name
Test status
Simulation time 67975212 ps
CPU time 0.85 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206032 kb
Host smart-ab548288-55fd-4a15-b55d-29f9d49c1655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046442906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3046442906
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.969850943
Short name T855
Test name
Test status
Simulation time 11634310 ps
CPU time 0.82 seconds
Started May 30 03:36:12 PM PDT 24
Finished May 30 03:36:14 PM PDT 24
Peak memory 206084 kb
Host smart-93ac8467-c181-4fd6-98fc-da56a8b5eaf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969850943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.969850943
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2863726548
Short name T881
Test name
Test status
Simulation time 16076978 ps
CPU time 0.81 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:22 PM PDT 24
Peak memory 206064 kb
Host smart-7e186535-78f7-4656-b700-b0a572891de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863726548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2863726548
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.696755104
Short name T890
Test name
Test status
Simulation time 11338126 ps
CPU time 0.87 seconds
Started May 30 03:36:19 PM PDT 24
Finished May 30 03:36:22 PM PDT 24
Peak memory 206056 kb
Host smart-521d216d-7fa4-43dd-b26d-0b9dd2c961ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696755104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.696755104
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3863638602
Short name T952
Test name
Test status
Simulation time 40015359 ps
CPU time 0.8 seconds
Started May 30 03:36:18 PM PDT 24
Finished May 30 03:36:22 PM PDT 24
Peak memory 205944 kb
Host smart-1a8940bd-a4b0-47dc-b5eb-317a9ee32df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863638602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3863638602
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.994547260
Short name T891
Test name
Test status
Simulation time 20526971 ps
CPU time 0.85 seconds
Started May 30 03:36:14 PM PDT 24
Finished May 30 03:36:17 PM PDT 24
Peak memory 205996 kb
Host smart-c91b6934-a480-4214-a74e-a2cb4ddde97e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994547260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.994547260
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1964475502
Short name T871
Test name
Test status
Simulation time 87342716 ps
CPU time 0.84 seconds
Started May 30 03:36:13 PM PDT 24
Finished May 30 03:36:16 PM PDT 24
Peak memory 206156 kb
Host smart-a46505e4-88be-47fb-8d98-8a443ef90359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964475502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1964475502
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1974199202
Short name T969
Test name
Test status
Simulation time 23048894 ps
CPU time 0.84 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206152 kb
Host smart-13630c99-dc72-43f2-aa83-15049515b681
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974199202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1974199202
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3512219322
Short name T912
Test name
Test status
Simulation time 44873090 ps
CPU time 0.84 seconds
Started May 30 03:36:12 PM PDT 24
Finished May 30 03:36:14 PM PDT 24
Peak memory 206080 kb
Host smart-1b4e0fdb-261d-4b84-88f3-05880b2bf7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512219322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3512219322
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.428247124
Short name T924
Test name
Test status
Simulation time 18686344 ps
CPU time 0.81 seconds
Started May 30 03:36:15 PM PDT 24
Finished May 30 03:36:18 PM PDT 24
Peak memory 206084 kb
Host smart-4cc8e0fa-a150-4bfe-a318-b947b3f98295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428247124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.428247124
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3382249264
Short name T863
Test name
Test status
Simulation time 56469816 ps
CPU time 1.05 seconds
Started May 30 03:35:24 PM PDT 24
Finished May 30 03:35:26 PM PDT 24
Peak memory 214536 kb
Host smart-76e7c708-d0f8-4614-b7d8-962a85af4027
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382249264 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3382249264
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1449801715
Short name T945
Test name
Test status
Simulation time 11811775 ps
CPU time 0.84 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:23 PM PDT 24
Peak memory 206168 kb
Host smart-57412fd0-6932-4890-b117-d603c296e325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449801715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1449801715
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.957807756
Short name T954
Test name
Test status
Simulation time 66374081 ps
CPU time 0.86 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:23 PM PDT 24
Peak memory 206064 kb
Host smart-38b1394d-1d9c-47b5-a213-1327a1377e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957807756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.957807756
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1933562331
Short name T896
Test name
Test status
Simulation time 214263660 ps
CPU time 1.28 seconds
Started May 30 03:35:19 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 206244 kb
Host smart-95d20bd2-f7db-4e27-b2c1-3e3471657233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933562331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1933562331
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1782411729
Short name T956
Test name
Test status
Simulation time 816642458 ps
CPU time 2.51 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:21 PM PDT 24
Peak memory 214404 kb
Host smart-fe3b0b20-7f8f-4829-b000-0ea47ef55ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782411729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1782411729
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2418443998
Short name T943
Test name
Test status
Simulation time 24834381 ps
CPU time 1.12 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:21 PM PDT 24
Peak memory 214560 kb
Host smart-b10162c8-a24e-4036-afc6-8531e58073c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418443998 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2418443998
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2221094243
Short name T239
Test name
Test status
Simulation time 34757232 ps
CPU time 0.89 seconds
Started May 30 03:35:16 PM PDT 24
Finished May 30 03:35:18 PM PDT 24
Peak memory 206204 kb
Host smart-2abc5ac2-c1b0-4b8f-84b2-f093f008882b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221094243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2221094243
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1621798456
Short name T934
Test name
Test status
Simulation time 20230646 ps
CPU time 0.95 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:19 PM PDT 24
Peak memory 206084 kb
Host smart-9ea7d7a9-6275-43c6-bf7c-7d582c2b7d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621798456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1621798456
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1523177772
Short name T222
Test name
Test status
Simulation time 56892197 ps
CPU time 1.1 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:20 PM PDT 24
Peak memory 206208 kb
Host smart-9b0bf5da-de54-4038-83ef-f3e25bc967da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523177772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1523177772
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2348218033
Short name T921
Test name
Test status
Simulation time 69661228 ps
CPU time 2.49 seconds
Started May 30 03:35:18 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 222568 kb
Host smart-6a75478b-5f89-4564-bdaf-9bc05b69aea2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348218033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2348218033
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.38339364
Short name T883
Test name
Test status
Simulation time 349723398 ps
CPU time 1.59 seconds
Started May 30 03:35:17 PM PDT 24
Finished May 30 03:35:20 PM PDT 24
Peak memory 206172 kb
Host smart-10dc4c01-362e-4b3b-be09-f644ae245b17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38339364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.38339364
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.208106443
Short name T965
Test name
Test status
Simulation time 99828596 ps
CPU time 1.35 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 214556 kb
Host smart-278f2901-1a83-4ca6-ad10-612c536c80a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208106443 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.208106443
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1767933472
Short name T225
Test name
Test status
Simulation time 14487084 ps
CPU time 0.92 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:34 PM PDT 24
Peak memory 206192 kb
Host smart-ce74af60-c16f-4e3c-a646-544954b7783b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767933472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1767933472
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2591792042
Short name T930
Test name
Test status
Simulation time 71994370 ps
CPU time 0.83 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:22 PM PDT 24
Peak memory 205848 kb
Host smart-2a07ff48-99bf-478a-a5cb-5c19f0315974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591792042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2591792042
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3553392820
Short name T979
Test name
Test status
Simulation time 32196619 ps
CPU time 1.34 seconds
Started May 30 03:35:30 PM PDT 24
Finished May 30 03:35:32 PM PDT 24
Peak memory 206184 kb
Host smart-65b0de97-1b8e-4853-be92-ee624822c36b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553392820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3553392820
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2141363984
Short name T951
Test name
Test status
Simulation time 204713189 ps
CPU time 3.5 seconds
Started May 30 03:35:20 PM PDT 24
Finished May 30 03:35:25 PM PDT 24
Peak memory 214368 kb
Host smart-6fbbb032-ec70-467a-b451-d1a8c3e9592d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141363984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2141363984
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1805934756
Short name T254
Test name
Test status
Simulation time 151528789 ps
CPU time 1.63 seconds
Started May 30 03:35:23 PM PDT 24
Finished May 30 03:35:26 PM PDT 24
Peak memory 206384 kb
Host smart-494377cf-9ab8-40b3-bbb4-224f242cdeec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805934756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1805934756
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3958925720
Short name T967
Test name
Test status
Simulation time 142333740 ps
CPU time 1.55 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:35 PM PDT 24
Peak memory 214488 kb
Host smart-fe9f4da2-0ce1-48df-82b2-26bb7252c827
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958925720 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3958925720
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3111777340
Short name T238
Test name
Test status
Simulation time 73405861 ps
CPU time 0.93 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 206200 kb
Host smart-a53d7145-5c82-403b-8ca4-f9c74c1f6fba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111777340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3111777340
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.524159657
Short name T971
Test name
Test status
Simulation time 15184517 ps
CPU time 0.88 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:34 PM PDT 24
Peak memory 206020 kb
Host smart-4984d090-43f1-4ec7-9832-e9307ab6f2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524159657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.524159657
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3494820569
Short name T224
Test name
Test status
Simulation time 103031057 ps
CPU time 1.19 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206212 kb
Host smart-35c830d8-bf5d-4fa9-bb8a-55702dc193a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494820569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3494820569
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3696192257
Short name T938
Test name
Test status
Simulation time 556916747 ps
CPU time 3.78 seconds
Started May 30 03:35:35 PM PDT 24
Finished May 30 03:35:40 PM PDT 24
Peak memory 214456 kb
Host smart-d89eb42f-62ab-4741-9766-ee0d5e0677d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696192257 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3696192257
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2602156497
Short name T907
Test name
Test status
Simulation time 287287486 ps
CPU time 1.56 seconds
Started May 30 03:35:33 PM PDT 24
Finished May 30 03:35:36 PM PDT 24
Peak memory 206192 kb
Host smart-e761e37f-d222-4920-b2c4-38ea4143fc66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602156497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2602156497
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4031601629
Short name T875
Test name
Test status
Simulation time 22359957 ps
CPU time 1.5 seconds
Started May 30 03:35:30 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 214460 kb
Host smart-578f3d6d-ed9a-428c-9c1e-ad0545d7ec58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031601629 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4031601629
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.702423547
Short name T230
Test name
Test status
Simulation time 43903430 ps
CPU time 0.89 seconds
Started May 30 03:35:30 PM PDT 24
Finished May 30 03:35:32 PM PDT 24
Peak memory 206148 kb
Host smart-7084f167-1e8d-4943-8946-d975b225ec23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702423547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.702423547
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3704729871
Short name T949
Test name
Test status
Simulation time 31358814 ps
CPU time 0.8 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:33 PM PDT 24
Peak memory 205964 kb
Host smart-621c3a97-fb82-4e50-8e48-596fc6978001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704729871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3704729871
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2407099804
Short name T927
Test name
Test status
Simulation time 128467625 ps
CPU time 1.39 seconds
Started May 30 03:35:31 PM PDT 24
Finished May 30 03:35:34 PM PDT 24
Peak memory 206232 kb
Host smart-c56dd4f9-f2e6-418b-8e9e-3bd5a7716dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407099804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2407099804
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1595625461
Short name T962
Test name
Test status
Simulation time 27438183 ps
CPU time 1.75 seconds
Started May 30 03:35:34 PM PDT 24
Finished May 30 03:35:37 PM PDT 24
Peak memory 214360 kb
Host smart-2fa142ed-b272-402c-b14f-fc317a4c4e64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595625461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1595625461
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1115706251
Short name T884
Test name
Test status
Simulation time 179676978 ps
CPU time 1.69 seconds
Started May 30 03:35:32 PM PDT 24
Finished May 30 03:35:35 PM PDT 24
Peak memory 214428 kb
Host smart-c4a0d018-0370-47dc-9d62-e2c077c34661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115706251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1115706251
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.2612790084
Short name T323
Test name
Test status
Simulation time 31936517 ps
CPU time 0.98 seconds
Started May 30 02:01:18 PM PDT 24
Finished May 30 02:01:20 PM PDT 24
Peak memory 214360 kb
Host smart-0c055685-ac4e-454d-a5e2-fd5a99c4ae45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612790084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2612790084
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2324129837
Short name T816
Test name
Test status
Simulation time 80843019 ps
CPU time 1.13 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 216584 kb
Host smart-f7a45ffc-e36b-48c8-ae3b-f28bbed2bcfa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324129837 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2324129837
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2102573873
Short name T763
Test name
Test status
Simulation time 23865341 ps
CPU time 0.98 seconds
Started May 30 02:01:14 PM PDT 24
Finished May 30 02:01:17 PM PDT 24
Peak memory 218184 kb
Host smart-39cbd688-9afe-43d9-9f9a-c2c99f626943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102573873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2102573873
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1643828024
Short name T671
Test name
Test status
Simulation time 102058118 ps
CPU time 0.93 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 215032 kb
Host smart-9734530b-2326-45a5-aac1-6645f286f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643828024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1643828024
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.516810518
Short name T439
Test name
Test status
Simulation time 26458645 ps
CPU time 1.08 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 223624 kb
Host smart-c219fae5-f2c0-4297-be04-dac288693713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516810518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.516810518
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1320286411
Short name T19
Test name
Test status
Simulation time 1386797939 ps
CPU time 4.49 seconds
Started May 30 02:01:14 PM PDT 24
Finished May 30 02:01:20 PM PDT 24
Peak memory 235880 kb
Host smart-58c539b3-3ebb-4aef-ace5-ea55a7719b83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320286411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1320286411
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1743487437
Short name T308
Test name
Test status
Simulation time 16585024 ps
CPU time 1.06 seconds
Started May 30 02:01:18 PM PDT 24
Finished May 30 02:01:20 PM PDT 24
Peak memory 214800 kb
Host smart-f5c5e81a-844a-4515-8f6b-4842fb0984c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743487437 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1743487437
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.254157034
Short name T728
Test name
Test status
Simulation time 409956153 ps
CPU time 4.85 seconds
Started May 30 02:01:14 PM PDT 24
Finished May 30 02:01:20 PM PDT 24
Peak memory 216776 kb
Host smart-ce4d0cd7-528d-4a81-a42c-9a395c903461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254157034 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.254157034
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3662045041
Short name T461
Test name
Test status
Simulation time 23868299220 ps
CPU time 554.94 seconds
Started May 30 02:01:16 PM PDT 24
Finished May 30 02:10:32 PM PDT 24
Peak memory 218020 kb
Host smart-fc44a612-7281-4b3a-94bd-d9fa3cbdea30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662045041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3662045041
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2480535809
Short name T572
Test name
Test status
Simulation time 42392152 ps
CPU time 1.2 seconds
Started May 30 02:01:23 PM PDT 24
Finished May 30 02:01:25 PM PDT 24
Peak memory 215408 kb
Host smart-6714cb66-cbda-4535-bdc7-18e765f9d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480535809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2480535809
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1342316708
Short name T494
Test name
Test status
Simulation time 13817706 ps
CPU time 0.96 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 214528 kb
Host smart-9136453d-4b54-41a1-b785-f5c58881bd20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342316708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1342316708
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.671156294
Short name T70
Test name
Test status
Simulation time 12003009 ps
CPU time 0.92 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 216140 kb
Host smart-0c49ec6d-b21a-4e7c-a4a9-0ed0ee272165
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671156294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.671156294
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2268002000
Short name T619
Test name
Test status
Simulation time 41977687 ps
CPU time 1.32 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 217900 kb
Host smart-a133aff3-5c95-42a4-bc0b-518488b137e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268002000 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2268002000
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1374944853
Short name T67
Test name
Test status
Simulation time 18489879 ps
CPU time 1.08 seconds
Started May 30 02:01:24 PM PDT 24
Finished May 30 02:01:26 PM PDT 24
Peak memory 217988 kb
Host smart-e3e0f641-5f0a-48e7-9561-a9d1d701a99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374944853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1374944853
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_intr.339508567
Short name T667
Test name
Test status
Simulation time 116078401 ps
CPU time 0.85 seconds
Started May 30 02:01:15 PM PDT 24
Finished May 30 02:01:17 PM PDT 24
Peak memory 214916 kb
Host smart-824b69b7-9f4f-4a6e-921d-611f3da482bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339508567 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.339508567
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4168314630
Short name T138
Test name
Test status
Simulation time 330734896 ps
CPU time 5.83 seconds
Started May 30 02:01:27 PM PDT 24
Finished May 30 02:01:34 PM PDT 24
Peak memory 235000 kb
Host smart-03ef2985-8311-43db-9f9a-50765cb7b42b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168314630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4168314630
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1067002541
Short name T244
Test name
Test status
Simulation time 39111368 ps
CPU time 0.9 seconds
Started May 30 02:01:13 PM PDT 24
Finished May 30 02:01:15 PM PDT 24
Peak memory 215020 kb
Host smart-2735d665-b91d-49a4-b1a6-ab62ee3ed3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067002541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1067002541
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2129384309
Short name T325
Test name
Test status
Simulation time 176962336991 ps
CPU time 824.96 seconds
Started May 30 02:01:16 PM PDT 24
Finished May 30 02:15:02 PM PDT 24
Peak memory 220796 kb
Host smart-4390a236-19ac-44d2-b69a-3f5eae2c7494
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129384309 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2129384309
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.2263350544
Short name T269
Test name
Test status
Simulation time 29189086 ps
CPU time 1.27 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 215200 kb
Host smart-04e3daa4-4346-4b53-b783-adc0553041b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263350544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2263350544
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1325828955
Short name T657
Test name
Test status
Simulation time 36734699 ps
CPU time 1.01 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 214680 kb
Host smart-37574e93-e5b5-4f13-a4ae-df6c18fa6055
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325828955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1325828955
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3482960403
Short name T202
Test name
Test status
Simulation time 79673998 ps
CPU time 1.13 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:09 PM PDT 24
Peak memory 219116 kb
Host smart-8ff7f8bd-5055-4244-b64c-869dde938958
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482960403 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3482960403
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.877732803
Short name T47
Test name
Test status
Simulation time 28905086 ps
CPU time 1.36 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 229040 kb
Host smart-86ebc59c-4b8b-4f5f-b709-8d78d03640bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877732803 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.877732803
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3746102140
Short name T566
Test name
Test status
Simulation time 140876916 ps
CPU time 3.22 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:09 PM PDT 24
Peak memory 218824 kb
Host smart-7783e287-10ca-494e-910e-4ed94099fa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746102140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3746102140
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.1244064480
Short name T505
Test name
Test status
Simulation time 19615237 ps
CPU time 1.07 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 206752 kb
Host smart-618572da-ff33-4114-a8f3-9a50b1b79f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244064480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1244064480
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2336295214
Short name T574
Test name
Test status
Simulation time 78167588 ps
CPU time 1.63 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:09 PM PDT 24
Peak memory 214944 kb
Host smart-0f41f109-dbb2-4f1a-bd5a-abd40f71db9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336295214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2336295214
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.2111412975
Short name T302
Test name
Test status
Simulation time 67692632 ps
CPU time 1.76 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 219364 kb
Host smart-9f7166fe-7ea3-4125-a058-e424a50754ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111412975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2111412975
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2935857578
Short name T349
Test name
Test status
Simulation time 49792283 ps
CPU time 1.64 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 218072 kb
Host smart-3c46b6aa-8c19-4b49-bf54-558616075549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935857578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2935857578
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3886464588
Short name T759
Test name
Test status
Simulation time 30624901 ps
CPU time 1.3 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 216844 kb
Host smart-e4c3830b-5328-4380-b196-7f1ba58f3f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886464588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3886464588
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2087989248
Short name T590
Test name
Test status
Simulation time 33565130 ps
CPU time 1.42 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 216660 kb
Host smart-fae54de9-392c-4d3d-ab8c-396717c3c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087989248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2087989248
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1039936438
Short name T356
Test name
Test status
Simulation time 35946074 ps
CPU time 1.29 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 216648 kb
Host smart-271e5540-02ae-4626-82c9-209c7688728b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039936438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1039936438
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.71523639
Short name T321
Test name
Test status
Simulation time 70253457 ps
CPU time 1.17 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 216752 kb
Host smart-efdff4c9-2f8f-42b5-82fa-c5cdee6aabf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71523639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.71523639
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1148333609
Short name T278
Test name
Test status
Simulation time 79875683 ps
CPU time 1.5 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 219308 kb
Host smart-9b96711a-5944-4665-b2dc-728c1071a5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148333609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1148333609
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3587275455
Short name T280
Test name
Test status
Simulation time 30447058 ps
CPU time 1.26 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 217888 kb
Host smart-49e50bb5-6613-461e-8395-e75647810c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587275455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3587275455
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3731904430
Short name T793
Test name
Test status
Simulation time 39058877 ps
CPU time 1.39 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 217984 kb
Host smart-51d8866d-0532-494a-ba0a-b11a62224c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731904430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3731904430
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3259119716
Short name T156
Test name
Test status
Simulation time 66986814 ps
CPU time 2.6 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 219592 kb
Host smart-25db1335-a58b-41ba-9043-54a9579cb73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259119716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3259119716
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1949013722
Short name T576
Test name
Test status
Simulation time 38789047 ps
CPU time 0.88 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:19 PM PDT 24
Peak memory 214524 kb
Host smart-86d006e9-ef62-4bb2-80d1-4371e6f33feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949013722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1949013722
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3036473634
Short name T599
Test name
Test status
Simulation time 12053753 ps
CPU time 0.91 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 216280 kb
Host smart-f107151a-d279-43e8-b90c-7da55e181b39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036473634 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3036473634
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2567593418
Short name T630
Test name
Test status
Simulation time 68678683 ps
CPU time 1.03 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 229128 kb
Host smart-c81b2744-0864-428f-82d5-513f69ff13b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567593418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2567593418
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2895500317
Short name T151
Test name
Test status
Simulation time 49437847 ps
CPU time 1.7 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 217744 kb
Host smart-addbe274-21a2-4e7f-96b9-68917e685088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895500317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2895500317
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1017853145
Short name T159
Test name
Test status
Simulation time 40861587 ps
CPU time 0.86 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 215192 kb
Host smart-7b4e559f-fe6a-4875-baa7-a0f483148696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017853145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1017853145
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2853058422
Short name T327
Test name
Test status
Simulation time 42572821 ps
CPU time 0.93 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:05 PM PDT 24
Peak memory 215036 kb
Host smart-6c8e05a7-13de-4912-aa34-9779f252a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853058422 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2853058422
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.3731892778
Short name T582
Test name
Test status
Simulation time 485586317 ps
CPU time 5.3 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:11 PM PDT 24
Peak memory 217804 kb
Host smart-efa7ceaa-03ba-44ff-a1c0-1ef8469a84fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731892778 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3731892778
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2279054802
Short name T783
Test name
Test status
Simulation time 73767348713 ps
CPU time 931.31 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:17:38 PM PDT 24
Peak memory 221936 kb
Host smart-82a2a556-b193-4226-82cf-f91fd6a32f66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279054802 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2279054802
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.1803842655
Short name T134
Test name
Test status
Simulation time 45245071 ps
CPU time 1.41 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 218104 kb
Host smart-923e348e-dba0-404f-a66c-6ffb845ebe06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803842655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1803842655
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.3920805439
Short name T25
Test name
Test status
Simulation time 45272526 ps
CPU time 1.72 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 217716 kb
Host smart-3d9576ea-7918-4028-9b2f-724b5638244e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920805439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3920805439
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1279610925
Short name T747
Test name
Test status
Simulation time 85900275 ps
CPU time 1.16 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216868 kb
Host smart-f98e2b02-ab1b-4f49-8258-5b4e224be1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279610925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1279610925
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.484660265
Short name T703
Test name
Test status
Simulation time 53564629 ps
CPU time 1.35 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 217836 kb
Host smart-2c10c4ee-a61e-4f58-8e51-03ac419f0fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484660265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.484660265
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4078747093
Short name T826
Test name
Test status
Simulation time 118830807 ps
CPU time 2.53 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 219168 kb
Host smart-0a43a6a0-ea32-46d1-af74-95422f128b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078747093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4078747093
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.213590714
Short name T131
Test name
Test status
Simulation time 57299492 ps
CPU time 1.32 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 219292 kb
Host smart-51f9af99-27fd-47d8-8e7e-64f1e9628069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213590714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.213590714
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1666851971
Short name T109
Test name
Test status
Simulation time 99031906 ps
CPU time 1.26 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 216696 kb
Host smart-80b68031-a1c0-47f0-8a24-0be7e9ed774b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666851971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1666851971
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2963848992
Short name T675
Test name
Test status
Simulation time 72608231 ps
CPU time 1.19 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 216568 kb
Host smart-3edc5714-aeab-4b5a-a082-c360190399fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963848992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2963848992
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4178673759
Short name T588
Test name
Test status
Simulation time 59273802 ps
CPU time 1.29 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 218892 kb
Host smart-9ddc3c74-fc43-46f6-87f2-7e286b7eea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178673759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4178673759
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3627272479
Short name T729
Test name
Test status
Simulation time 53921101 ps
CPU time 1.63 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:29 PM PDT 24
Peak memory 217816 kb
Host smart-cd89ccfb-ba04-4f85-b0cb-d4b5aefdcb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627272479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3627272479
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4076016605
Short name T738
Test name
Test status
Simulation time 27083804 ps
CPU time 1.19 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 215420 kb
Host smart-e5a2c407-4615-40f4-a1a3-a86e4425271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076016605 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4076016605
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2237848681
Short name T547
Test name
Test status
Simulation time 39993294 ps
CPU time 0.85 seconds
Started May 30 02:02:11 PM PDT 24
Finished May 30 02:02:13 PM PDT 24
Peak memory 214408 kb
Host smart-65a89d6c-6011-477c-9cbf-fa980f17d777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237848681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2237848681
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1568230972
Short name T59
Test name
Test status
Simulation time 26401194 ps
CPU time 1.15 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 216820 kb
Host smart-0befcda8-ee4d-43c7-8ddf-0ff770799a1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568230972 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1568230972
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_genbits.2927196572
Short name T789
Test name
Test status
Simulation time 243129346 ps
CPU time 3.17 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:21 PM PDT 24
Peak memory 219752 kb
Host smart-9f0c4f2b-044f-4bf4-9dcb-564b2a893822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927196572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2927196572
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1420729006
Short name T170
Test name
Test status
Simulation time 20327248 ps
CPU time 1.09 seconds
Started May 30 02:02:18 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 215404 kb
Host smart-6ffcd1ee-0bda-4a23-b415-27b8bd43e240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420729006 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1420729006
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.777235101
Short name T700
Test name
Test status
Simulation time 18687386 ps
CPU time 1 seconds
Started May 30 02:02:12 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 214972 kb
Host smart-3b26760b-431a-4545-9b97-91354a549b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777235101 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.777235101
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2797438029
Short name T429
Test name
Test status
Simulation time 1568563093 ps
CPU time 2.59 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:17 PM PDT 24
Peak memory 216740 kb
Host smart-dec20f6f-4689-4bfa-bfbd-3e112f913393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797438029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2797438029
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1373778459
Short name T797
Test name
Test status
Simulation time 199645517348 ps
CPU time 1380.67 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:25:14 PM PDT 24
Peak memory 224892 kb
Host smart-fec08293-6cf0-4d1b-a93a-2c23fcd7b680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373778459 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1373778459
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1687393400
Short name T734
Test name
Test status
Simulation time 31222190 ps
CPU time 1.33 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 219424 kb
Host smart-6105760c-473b-41fa-8ed9-eea29c14e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687393400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1687393400
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2230644456
Short name T448
Test name
Test status
Simulation time 73698410 ps
CPU time 1.24 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 217948 kb
Host smart-e7a3ee45-477f-4224-bc73-c618d40220c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230644456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2230644456
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2354410942
Short name T653
Test name
Test status
Simulation time 131223445 ps
CPU time 1.08 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216872 kb
Host smart-184e6ede-6b23-45d4-b02a-3c2678fbab30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354410942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2354410942
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.520150552
Short name T623
Test name
Test status
Simulation time 79711973 ps
CPU time 1.08 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 216704 kb
Host smart-907ce45f-0b51-45fb-aa54-e740e1efc86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520150552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.520150552
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2348666217
Short name T780
Test name
Test status
Simulation time 84141843 ps
CPU time 1.86 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 218196 kb
Host smart-bc28fece-6400-4c5e-b5ef-393d8ca496d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348666217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2348666217
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2203349213
Short name T828
Test name
Test status
Simulation time 124417357 ps
CPU time 1.18 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 218392 kb
Host smart-efa309af-711d-467f-95bf-dc9887161714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203349213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2203349213
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.2537460330
Short name T839
Test name
Test status
Simulation time 110764270 ps
CPU time 1.19 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 216724 kb
Host smart-c4e324ad-26e2-4e94-ac2d-6b4ac47719c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537460330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2537460330
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1192710958
Short name T682
Test name
Test status
Simulation time 73394830 ps
CPU time 2.71 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 217240 kb
Host smart-2b4ed002-24a7-4f08-b1f6-ffa53dff11c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192710958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1192710958
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3685921650
Short name T499
Test name
Test status
Simulation time 118550417 ps
CPU time 1.27 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 216600 kb
Host smart-7ce5274e-8b53-4fa0-8297-9c28b8fbcb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685921650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3685921650
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2565029301
Short name T743
Test name
Test status
Simulation time 88322637 ps
CPU time 1.27 seconds
Started May 30 02:02:18 PM PDT 24
Finished May 30 02:02:21 PM PDT 24
Peak memory 215372 kb
Host smart-61b7b8aa-b8cc-4b11-93bd-4ff99cbb8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565029301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2565029301
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.11645261
Short name T688
Test name
Test status
Simulation time 24373072 ps
CPU time 0.86 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 206288 kb
Host smart-ad1b0236-0f1c-4ffd-a475-c6f74091501f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.11645261
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2203425437
Short name T443
Test name
Test status
Simulation time 22884024 ps
CPU time 0.86 seconds
Started May 30 02:02:18 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 215868 kb
Host smart-da3b3922-7bbc-41a6-bcc3-dd970cf05f98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203425437 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2203425437
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2928440863
Short name T491
Test name
Test status
Simulation time 42583174 ps
CPU time 1.03 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:21 PM PDT 24
Peak memory 216608 kb
Host smart-3093bcb5-0cad-4a14-a1c7-ccffbaeaf588
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928440863 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2928440863
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1537911916
Short name T88
Test name
Test status
Simulation time 18288190 ps
CPU time 1.15 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:18 PM PDT 24
Peak memory 223484 kb
Host smart-a482362f-fa71-4c2b-98ff-b9eacd059be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537911916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1537911916
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.316397881
Short name T315
Test name
Test status
Simulation time 44656245 ps
CPU time 1.26 seconds
Started May 30 02:02:11 PM PDT 24
Finished May 30 02:02:13 PM PDT 24
Peak memory 218128 kb
Host smart-5e64ea57-3097-4b0e-bffa-2b95d6d0e425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316397881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.316397881
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.448499441
Short name T698
Test name
Test status
Simulation time 40845757 ps
CPU time 0.93 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 215088 kb
Host smart-ddf1c8fe-2894-4add-82d0-85a24de6583d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448499441 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.448499441
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2452468317
Short name T666
Test name
Test status
Simulation time 27451489 ps
CPU time 0.96 seconds
Started May 30 02:02:12 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 215020 kb
Host smart-e75cbc52-326d-4064-b942-f9e1ea468dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452468317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2452468317
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4162498977
Short name T498
Test name
Test status
Simulation time 371249964 ps
CPU time 7 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:24 PM PDT 24
Peak memory 216684 kb
Host smart-d50befa1-b2b4-4ce3-befa-bbc99211338c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162498977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4162498977
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2273168339
Short name T720
Test name
Test status
Simulation time 80770286970 ps
CPU time 441.1 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:09:37 PM PDT 24
Peak memory 221536 kb
Host smart-61d6b414-4a09-435c-8fde-6bafd312ac26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273168339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2273168339
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1261893511
Short name T481
Test name
Test status
Simulation time 72748636 ps
CPU time 1.02 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 216788 kb
Host smart-0d6c6e1e-73c2-44ca-bf75-3d8924a2c8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261893511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1261893511
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.708572573
Short name T773
Test name
Test status
Simulation time 168674610 ps
CPU time 1.16 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216704 kb
Host smart-5c562b6d-5f1d-4299-b921-826bd6ff4070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708572573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.708572573
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2543592243
Short name T847
Test name
Test status
Simulation time 26281043 ps
CPU time 1.3 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 218968 kb
Host smart-4a1f1f4d-9868-4e09-9cdf-b2843891f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543592243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2543592243
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3496227046
Short name T488
Test name
Test status
Simulation time 55470374 ps
CPU time 1.43 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 217808 kb
Host smart-d6f7330c-da09-4a4a-8e56-2a19bd6f96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496227046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3496227046
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.614580515
Short name T492
Test name
Test status
Simulation time 88364340 ps
CPU time 1.54 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 217944 kb
Host smart-41f94e5f-e817-4c3b-81aa-38bcb8b3f904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614580515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.614580515
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3897981402
Short name T567
Test name
Test status
Simulation time 31180557 ps
CPU time 1.41 seconds
Started May 30 02:04:33 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 217828 kb
Host smart-b735fe27-e9d0-47fc-8864-c642b051536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897981402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3897981402
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.4128950818
Short name T482
Test name
Test status
Simulation time 74444741 ps
CPU time 1.34 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 218096 kb
Host smart-40b6017e-c21f-4a3e-bd05-1d26a1ea34ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128950818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4128950818
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.290982521
Short name T449
Test name
Test status
Simulation time 74038043 ps
CPU time 2.02 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:39 PM PDT 24
Peak memory 218012 kb
Host smart-ae37c63a-33f1-4475-abc0-02c68e83f595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290982521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.290982521
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3126712132
Short name T273
Test name
Test status
Simulation time 82780241 ps
CPU time 1.21 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 215424 kb
Host smart-88fc18e0-ea8d-48e9-92d7-8fb777c8b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126712132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3126712132
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.2737048967
Short name T533
Test name
Test status
Simulation time 31372774 ps
CPU time 0.91 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 206268 kb
Host smart-51390691-38e9-4c8e-905d-b6be73319baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737048967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2737048967
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1340561559
Short name T593
Test name
Test status
Simulation time 17840684 ps
CPU time 0.85 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 215244 kb
Host smart-e69b82a0-4b47-4f76-b8be-6a829bea9ae0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340561559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1340561559
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.2456183980
Short name T644
Test name
Test status
Simulation time 31051858 ps
CPU time 0.9 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 217904 kb
Host smart-12a0dc71-e13c-4fc5-97ca-2668d8337999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456183980 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2456183980
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3362499368
Short name T681
Test name
Test status
Simulation time 55402037 ps
CPU time 1.96 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 218016 kb
Host smart-86f34274-5c58-473b-9aa7-787a1cd0c6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362499368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3362499368
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4020997560
Short name T706
Test name
Test status
Simulation time 21041189 ps
CPU time 1.06 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 215396 kb
Host smart-427e0dfb-136d-4f5d-96f3-036ccaaaa476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020997560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4020997560
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2077107032
Short name T755
Test name
Test status
Simulation time 100607905 ps
CPU time 0.91 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:02:16 PM PDT 24
Peak memory 215096 kb
Host smart-6a257810-0a9e-431b-adb9-ee7706863b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077107032 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2077107032
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1456919876
Short name T5
Test name
Test status
Simulation time 164771383 ps
CPU time 2.13 seconds
Started May 30 02:02:12 PM PDT 24
Finished May 30 02:02:15 PM PDT 24
Peak memory 215036 kb
Host smart-75338d7c-76fd-4f77-bc52-44ce5e1009cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456919876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1456919876
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.820373687
Short name T825
Test name
Test status
Simulation time 132454503572 ps
CPU time 1312.08 seconds
Started May 30 02:02:14 PM PDT 24
Finished May 30 02:24:08 PM PDT 24
Peak memory 222824 kb
Host smart-793de1d6-c2b6-47bd-ba01-84b139ed140f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820373687 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.820373687
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.4102628940
Short name T345
Test name
Test status
Simulation time 64756708 ps
CPU time 1.43 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 218044 kb
Host smart-e7fcff6a-4440-4eea-9d5f-475bc3a9ee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102628940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4102628940
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.32129839
Short name T212
Test name
Test status
Simulation time 54089795 ps
CPU time 1.57 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 214900 kb
Host smart-7fb77149-e8a9-4617-b9ab-954893694dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32129839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.32129839
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1509816082
Short name T527
Test name
Test status
Simulation time 52205694 ps
CPU time 1.68 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 217880 kb
Host smart-b6512be0-04c0-4ae7-89a0-a4f490cb7059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509816082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1509816082
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2207873722
Short name T523
Test name
Test status
Simulation time 58806911 ps
CPU time 1.33 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 216588 kb
Host smart-2dcf617e-3391-4076-ac4e-aa84fbfefa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207873722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2207873722
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1549850670
Short name T841
Test name
Test status
Simulation time 45138609 ps
CPU time 1.24 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 216852 kb
Host smart-ef913e40-380b-4c68-aaf1-7e82bfa13f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549850670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1549850670
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3496323914
Short name T769
Test name
Test status
Simulation time 31171803 ps
CPU time 1.23 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:44 PM PDT 24
Peak memory 217952 kb
Host smart-4a5268d3-e7c1-4bf8-a1b0-05205ff69f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496323914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3496323914
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2078258082
Short name T680
Test name
Test status
Simulation time 40143012 ps
CPU time 1.44 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 218056 kb
Host smart-62d4665b-26b9-4997-a495-9360da5c05a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078258082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2078258082
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1603771698
Short name T754
Test name
Test status
Simulation time 52063677 ps
CPU time 1 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 215032 kb
Host smart-5fd73c3e-d304-4cdb-9b7f-599df484a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603771698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1603771698
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1093078739
Short name T110
Test name
Test status
Simulation time 73919238 ps
CPU time 1.29 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 218392 kb
Host smart-18fe7301-a9bd-433b-b3dc-70038e0e415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093078739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1093078739
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.597137222
Short name T829
Test name
Test status
Simulation time 59233684 ps
CPU time 1.3 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 219408 kb
Host smart-31a0b801-0330-4460-8378-14f18ad67c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597137222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.597137222
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.1882248394
Short name T833
Test name
Test status
Simulation time 61637544 ps
CPU time 1.35 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 215364 kb
Host smart-0b1d9326-001c-4bc2-9ee7-722e539caf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882248394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1882248394
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2325608904
Short name T542
Test name
Test status
Simulation time 68560342 ps
CPU time 1.02 seconds
Started May 30 02:02:17 PM PDT 24
Finished May 30 02:02:20 PM PDT 24
Peak memory 214880 kb
Host smart-7558a26c-21ca-40fa-86f2-521dfd869dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325608904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2325608904
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2423173099
Short name T99
Test name
Test status
Simulation time 92114900 ps
CPU time 0.85 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:17 PM PDT 24
Peak memory 216096 kb
Host smart-2b533cbd-8096-4079-9e7e-03d2b1e35138
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423173099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2423173099
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.737364829
Short name T44
Test name
Test status
Simulation time 32849167 ps
CPU time 1.23 seconds
Started May 30 02:02:12 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 216716 kb
Host smart-abe70ff3-c85c-43c1-ad59-04cd2b390add
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737364829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.737364829
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.440483229
Short name T794
Test name
Test status
Simulation time 19548519 ps
CPU time 1.09 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:15 PM PDT 24
Peak memory 218240 kb
Host smart-f8cb9015-d07f-4698-bf1f-69af450aa3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440483229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.440483229
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3158450249
Short name T301
Test name
Test status
Simulation time 35296832 ps
CPU time 1.51 seconds
Started May 30 02:02:20 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 218084 kb
Host smart-201b232d-7164-4494-839e-011d31cc7668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158450249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3158450249
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3480062292
Short name T366
Test name
Test status
Simulation time 18904024 ps
CPU time 0.9 seconds
Started May 30 02:02:16 PM PDT 24
Finished May 30 02:02:18 PM PDT 24
Peak memory 215072 kb
Host smart-fd2c935d-b780-457d-b12e-e27ee6df201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480062292 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3480062292
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.203253179
Short name T432
Test name
Test status
Simulation time 81809519 ps
CPU time 2.06 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:18 PM PDT 24
Peak memory 216700 kb
Host smart-ad262a41-3910-418a-ab99-02425ae4c2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203253179 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.203253179
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2593889536
Short name T204
Test name
Test status
Simulation time 49917325891 ps
CPU time 269.63 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:06:44 PM PDT 24
Peak memory 217252 kb
Host smart-b1959187-f4cc-4bac-b091-c10e510387a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593889536 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2593889536
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2563124074
Short name T643
Test name
Test status
Simulation time 39678333 ps
CPU time 1 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:39 PM PDT 24
Peak memory 216616 kb
Host smart-bb0f7576-dfbb-48ad-b972-9d3153a5d0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563124074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2563124074
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3146896019
Short name T804
Test name
Test status
Simulation time 48325471 ps
CPU time 1.15 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 218840 kb
Host smart-a0ddd080-9163-48a3-a1ac-c28b97fc42ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146896019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3146896019
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3157121276
Short name T132
Test name
Test status
Simulation time 74925380 ps
CPU time 1.52 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 218020 kb
Host smart-3a47cd74-15da-4caa-b097-28cd2ed42ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157121276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3157121276
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1491615009
Short name T502
Test name
Test status
Simulation time 35597067 ps
CPU time 1.31 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 216736 kb
Host smart-5a8641a4-7c36-4bb5-830f-25648fcbc7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491615009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1491615009
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.75549379
Short name T820
Test name
Test status
Simulation time 44854684 ps
CPU time 1.47 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 217876 kb
Host smart-d534e7a9-3f74-4c41-9c0f-c01d2a4e24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75549379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.75549379
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1635475361
Short name T155
Test name
Test status
Simulation time 444874975 ps
CPU time 1.47 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 219392 kb
Host smart-f2749c0e-3dc2-4d7c-afce-ee827393fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635475361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1635475361
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1450577297
Short name T458
Test name
Test status
Simulation time 31092242 ps
CPU time 1.27 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:37 PM PDT 24
Peak memory 216960 kb
Host smart-7ffdbbe7-fc86-489b-8ab1-262567ae6ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450577297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1450577297
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3861402245
Short name T74
Test name
Test status
Simulation time 58012042 ps
CPU time 1.34 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 215388 kb
Host smart-da0cb5ec-7e49-43e2-b052-a770e981b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861402245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3861402245
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3672237549
Short name T561
Test name
Test status
Simulation time 25946482 ps
CPU time 0.88 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 206308 kb
Host smart-499d852c-c9ec-4716-aea8-55648a866287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672237549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3672237549
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3552595972
Short name T65
Test name
Test status
Simulation time 21362435 ps
CPU time 0.9 seconds
Started May 30 02:02:20 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 215208 kb
Host smart-9155771b-c2c8-41b0-bc95-7162177b6d3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552595972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3552595972
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.2402972671
Short name T823
Test name
Test status
Simulation time 42982126 ps
CPU time 1.24 seconds
Started May 30 02:02:12 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 224916 kb
Host smart-eb2779e0-bfec-4bb5-86f5-679b33fee0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402972671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2402972671
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2624466943
Short name T399
Test name
Test status
Simulation time 38610300 ps
CPU time 1.45 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:21 PM PDT 24
Peak memory 219352 kb
Host smart-cddead7f-779c-40ec-ac82-b33a65969b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624466943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2624466943
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3737852539
Short name T118
Test name
Test status
Simulation time 31833418 ps
CPU time 0.9 seconds
Started May 30 02:02:13 PM PDT 24
Finished May 30 02:02:15 PM PDT 24
Peak memory 215268 kb
Host smart-43d2fb63-0f1f-4ad4-a88c-181be47e898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737852539 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3737852539
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1140732919
Short name T333
Test name
Test status
Simulation time 17883696 ps
CPU time 0.97 seconds
Started May 30 02:02:19 PM PDT 24
Finished May 30 02:02:21 PM PDT 24
Peak memory 214980 kb
Host smart-9d177011-c579-4535-9d6b-bad246498981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140732919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1140732919
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1878767547
Short name T348
Test name
Test status
Simulation time 241944472 ps
CPU time 5.08 seconds
Started May 30 02:02:15 PM PDT 24
Finished May 30 02:02:22 PM PDT 24
Peak memory 215028 kb
Host smart-9de3b0c3-86ac-4aa8-b732-62b1a48dbfa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878767547 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1878767547
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2104136696
Short name T650
Test name
Test status
Simulation time 47099496113 ps
CPU time 1188.56 seconds
Started May 30 02:02:11 PM PDT 24
Finished May 30 02:22:01 PM PDT 24
Peak memory 222256 kb
Host smart-c6ba6e4b-dfe2-4597-8012-4dda9d02feaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104136696 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2104136696
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.4277181992
Short name T827
Test name
Test status
Simulation time 57266822 ps
CPU time 1.02 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 216576 kb
Host smart-9454c918-15b9-4b2c-b356-7f810fe51a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277181992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.4277181992
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1931649279
Short name T391
Test name
Test status
Simulation time 83867475 ps
CPU time 1.26 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 216836 kb
Host smart-e418db53-6a70-4832-b523-f57fad1cc206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931649279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1931649279
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2305134216
Short name T735
Test name
Test status
Simulation time 37848325 ps
CPU time 1.48 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 216720 kb
Host smart-25826c60-398c-44e3-aa5a-5dd171395d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305134216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2305134216
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2571328529
Short name T459
Test name
Test status
Simulation time 39089903 ps
CPU time 1.53 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:44 PM PDT 24
Peak memory 216664 kb
Host smart-8a4f5b91-bc5f-464f-859d-a64b52b3b64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571328529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2571328529
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.641753414
Short name T128
Test name
Test status
Simulation time 26471962 ps
CPU time 1.18 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:40 PM PDT 24
Peak memory 216660 kb
Host smart-50f6f7fa-cdcd-4a67-9ee4-e1f89892eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641753414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.641753414
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2539544446
Short name T719
Test name
Test status
Simulation time 49804281 ps
CPU time 1.22 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 216736 kb
Host smart-b1087183-20d7-4768-9e93-3b9a95a4bb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539544446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2539544446
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.979065419
Short name T477
Test name
Test status
Simulation time 38729353 ps
CPU time 1.54 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 218000 kb
Host smart-0d812d41-5f41-407a-a1cf-01b7ddb15171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979065419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.979065419
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.638110631
Short name T263
Test name
Test status
Simulation time 25275865 ps
CPU time 1.22 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 218144 kb
Host smart-f353ae57-c48c-4705-9a68-0319fb612215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638110631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.638110631
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3368365085
Short name T392
Test name
Test status
Simulation time 331079661 ps
CPU time 4.12 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:44 PM PDT 24
Peak memory 218012 kb
Host smart-2d90a560-571c-456a-b206-fb135e17c12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368365085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3368365085
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.51303047
Short name T394
Test name
Test status
Simulation time 88273237 ps
CPU time 1.22 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:44 PM PDT 24
Peak memory 219344 kb
Host smart-ec08e47c-01fc-43d3-87b9-c71072b54c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51303047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.51303047
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4035507446
Short name T101
Test name
Test status
Simulation time 52517704 ps
CPU time 1.3 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 215420 kb
Host smart-1948d8e8-5ac8-4669-baa3-cde5f94bdd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035507446 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4035507446
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3160180496
Short name T489
Test name
Test status
Simulation time 37417172 ps
CPU time 0.8 seconds
Started May 30 02:02:28 PM PDT 24
Finished May 30 02:02:30 PM PDT 24
Peak memory 206460 kb
Host smart-edfb7e37-eec9-45ac-8856-e8f14d9d1863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160180496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3160180496
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.225075561
Short name T452
Test name
Test status
Simulation time 35113312 ps
CPU time 0.84 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 216152 kb
Host smart-5dc820cc-a91a-4788-897e-ca01c974f061
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225075561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.225075561
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.3140706636
Short name T46
Test name
Test status
Simulation time 34674527 ps
CPU time 0.92 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 219304 kb
Host smart-20098d2b-267b-4e24-afb5-a97817dbc8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140706636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3140706636
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3718081268
Short name T742
Test name
Test status
Simulation time 265586818 ps
CPU time 4.11 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 219448 kb
Host smart-574d1536-7fb0-4ab3-8d14-1b064d53fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718081268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3718081268
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1392530068
Short name T108
Test name
Test status
Simulation time 32428968 ps
CPU time 0.88 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:30 PM PDT 24
Peak memory 215164 kb
Host smart-307dcbc9-5b90-47ad-9bc2-c7b582a3c3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392530068 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1392530068
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.313940992
Short name T758
Test name
Test status
Simulation time 49687602 ps
CPU time 0.97 seconds
Started May 30 02:02:32 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 214988 kb
Host smart-1fa46cdc-c39d-46eb-a872-6ad077b8d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313940992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.313940992
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1209039789
Short name T447
Test name
Test status
Simulation time 296118085 ps
CPU time 6.12 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:38 PM PDT 24
Peak memory 217808 kb
Host smart-7a5f24b2-4753-4bf8-8d90-de5aa131cfea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209039789 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1209039789
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/170.edn_genbits.1338226248
Short name T362
Test name
Test status
Simulation time 171559015 ps
CPU time 3.64 seconds
Started May 30 02:04:41 PM PDT 24
Finished May 30 02:04:46 PM PDT 24
Peak memory 219728 kb
Host smart-972c557d-2eaf-44b9-9a7f-96639f316cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338226248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1338226248
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.236682929
Short name T822
Test name
Test status
Simulation time 37446306 ps
CPU time 1.44 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 216816 kb
Host smart-30520596-4743-4e54-91d6-7fb6db7c2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236682929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.236682929
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2328062002
Short name T377
Test name
Test status
Simulation time 79850318 ps
CPU time 1.27 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 218360 kb
Host smart-6395768f-2f64-4ef8-b5e2-1d6332aff5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328062002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2328062002
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4064557167
Short name T817
Test name
Test status
Simulation time 42560012 ps
CPU time 1.37 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 215028 kb
Host smart-87f50bcd-e048-49d1-9304-daa5f4afbd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064557167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4064557167
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.480060597
Short name T792
Test name
Test status
Simulation time 95193849 ps
CPU time 1.66 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 219560 kb
Host smart-937a0e11-ba80-48ac-874c-bf7d07d5cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480060597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.480060597
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1414013889
Short name T715
Test name
Test status
Simulation time 48484114 ps
CPU time 1.26 seconds
Started May 30 02:04:41 PM PDT 24
Finished May 30 02:04:44 PM PDT 24
Peak memory 219380 kb
Host smart-adf4b074-fbbd-4efc-aa0a-0454259d56db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414013889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1414013889
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3422112719
Short name T152
Test name
Test status
Simulation time 29462158 ps
CPU time 1.16 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 216812 kb
Host smart-5d9154b8-60ce-4304-94f2-c87142d0d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422112719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3422112719
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2036460595
Short name T602
Test name
Test status
Simulation time 39452870 ps
CPU time 1.48 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 217832 kb
Host smart-93a309ba-a146-4f0e-b5c2-2d236da52064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036460595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2036460595
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.533366249
Short name T710
Test name
Test status
Simulation time 136090989 ps
CPU time 1.53 seconds
Started May 30 02:04:39 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 217864 kb
Host smart-75f02f80-8630-4f31-9a36-cd61b2ac0903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533366249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.533366249
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.3982444374
Short name T518
Test name
Test status
Simulation time 68663201 ps
CPU time 0.98 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 206360 kb
Host smart-91582c0f-4649-47ae-99a0-8ec6e2763e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982444374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3982444374
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3867437985
Short name T711
Test name
Test status
Simulation time 12268934 ps
CPU time 0.93 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 216288 kb
Host smart-faae0cfa-5204-4b39-970d-f6146653dd2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867437985 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3867437985
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1786064298
Short name T485
Test name
Test status
Simulation time 315855815 ps
CPU time 1.12 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 216436 kb
Host smart-10259e49-f1f9-44e8-9c42-1cc4d8ea0504
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786064298 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1786064298
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.404196159
Short name T69
Test name
Test status
Simulation time 18339022 ps
CPU time 1.06 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 218100 kb
Host smart-da65bc3a-cd74-4684-b78a-c7fbf429e459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404196159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.404196159
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.2031044227
Short name T524
Test name
Test status
Simulation time 41521440 ps
CPU time 1.7 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 216692 kb
Host smart-8df4e302-01fa-4173-a4ad-8edfb2f26a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031044227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2031044227
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1601716363
Short name T105
Test name
Test status
Simulation time 21574249 ps
CPU time 1.19 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 223556 kb
Host smart-ba66fe06-72a6-46f6-8f41-1dde8d920be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601716363 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1601716363
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4033621856
Short name T304
Test name
Test status
Simulation time 25596752 ps
CPU time 0.95 seconds
Started May 30 02:02:27 PM PDT 24
Finished May 30 02:02:28 PM PDT 24
Peak memory 214952 kb
Host smart-c084691c-6f81-4add-b42d-6aeb8ddb30a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033621856 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4033621856
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.488206084
Short name T478
Test name
Test status
Simulation time 303001168 ps
CPU time 1.28 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 214940 kb
Host smart-2d1ec7ba-a7e0-4215-be4b-e9e81ce999f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488206084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.488206084
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1030627785
Short name T787
Test name
Test status
Simulation time 35509561590 ps
CPU time 920.78 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:17:53 PM PDT 24
Peak memory 219584 kb
Host smart-6088c5f8-021c-479b-9b87-bc96fb7d1821
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030627785 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1030627785
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1200956598
Short name T129
Test name
Test status
Simulation time 48997503 ps
CPU time 1.28 seconds
Started May 30 02:04:37 PM PDT 24
Finished May 30 02:04:39 PM PDT 24
Peak memory 216600 kb
Host smart-c627bbee-a3b5-4b36-819a-2c699613a10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200956598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1200956598
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3878181587
Short name T684
Test name
Test status
Simulation time 80384999 ps
CPU time 1.11 seconds
Started May 30 02:04:37 PM PDT 24
Finished May 30 02:04:40 PM PDT 24
Peak memory 217880 kb
Host smart-e4e5f042-dac3-4f56-8227-4391e1843108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878181587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3878181587
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.96545778
Short name T283
Test name
Test status
Simulation time 50470466 ps
CPU time 1.37 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:43 PM PDT 24
Peak memory 216840 kb
Host smart-0d2b70ba-07c0-43ac-a637-4caba91a66ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96545778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.96545778
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.239594018
Short name T613
Test name
Test status
Simulation time 402145109 ps
CPU time 3.9 seconds
Started May 30 02:04:40 PM PDT 24
Finished May 30 02:04:46 PM PDT 24
Peak memory 219032 kb
Host smart-ecf369ff-2458-4fbc-ad03-f54fb737d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239594018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.239594018
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4202206160
Short name T543
Test name
Test status
Simulation time 28474225 ps
CPU time 1.33 seconds
Started May 30 02:04:38 PM PDT 24
Finished May 30 02:04:41 PM PDT 24
Peak memory 216988 kb
Host smart-a129415e-25b1-414f-a396-4ec10c200617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202206160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4202206160
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3723808529
Short name T652
Test name
Test status
Simulation time 138857028 ps
CPU time 0.95 seconds
Started May 30 02:04:37 PM PDT 24
Finished May 30 02:04:39 PM PDT 24
Peak memory 216820 kb
Host smart-535332ea-ceae-4127-be7a-50660ffcaec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723808529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3723808529
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.960028378
Short name T573
Test name
Test status
Simulation time 59311095 ps
CPU time 1.08 seconds
Started May 30 02:04:46 PM PDT 24
Finished May 30 02:04:48 PM PDT 24
Peak memory 216852 kb
Host smart-455218ff-735c-419d-ab13-d1ba2250f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960028378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.960028378
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.938961038
Short name T300
Test name
Test status
Simulation time 104025382 ps
CPU time 1.24 seconds
Started May 30 02:04:46 PM PDT 24
Finished May 30 02:04:48 PM PDT 24
Peak memory 218056 kb
Host smart-c2bca4cd-22fc-4a49-b183-a81ad442c9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938961038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.938961038
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2688398170
Short name T276
Test name
Test status
Simulation time 30194795 ps
CPU time 1.24 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 215412 kb
Host smart-3f08ee76-fd25-4298-be6e-9965fb4f39b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688398170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2688398170
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3264481466
Short name T838
Test name
Test status
Simulation time 28630745 ps
CPU time 1 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 206324 kb
Host smart-00590ff2-8fbd-45f2-9704-481c34cca344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264481466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3264481466
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.1733406780
Short name T515
Test name
Test status
Simulation time 75039461 ps
CPU time 0.84 seconds
Started May 30 02:02:33 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 215648 kb
Host smart-5e8d8469-6523-4e4f-b74b-1669855439b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733406780 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1733406780
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.626015779
Short name T176
Test name
Test status
Simulation time 53073559 ps
CPU time 1.09 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 216732 kb
Host smart-5381d9d4-012e-4d11-a5ba-ef4bd16ff2bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626015779 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.626015779
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3921303430
Short name T744
Test name
Test status
Simulation time 33797900 ps
CPU time 0.97 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 219508 kb
Host smart-4880eeb5-3040-4bc7-ba04-a8f764a42b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921303430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3921303430
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.914013867
Short name T436
Test name
Test status
Simulation time 62839970 ps
CPU time 1.45 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 219632 kb
Host smart-84e13620-f997-4049-a243-28d478572ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914013867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.914013867
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.3029169194
Short name T771
Test name
Test status
Simulation time 18839057 ps
CPU time 1 seconds
Started May 30 02:02:32 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 215096 kb
Host smart-c4ecd610-7df7-4480-80a4-613002e6edd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029169194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3029169194
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4106578776
Short name T516
Test name
Test status
Simulation time 180369998 ps
CPU time 3.95 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:34 PM PDT 24
Peak memory 216672 kb
Host smart-1357d89b-c38e-4b3a-b304-516875451be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106578776 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4106578776
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.397522752
Short name T639
Test name
Test status
Simulation time 545541183181 ps
CPU time 1258.01 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:23:29 PM PDT 24
Peak memory 232232 kb
Host smart-bc7d8b29-54fa-492a-8476-79c690be6eba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397522752 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.397522752
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1829784587
Short name T736
Test name
Test status
Simulation time 60205483 ps
CPU time 1.35 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 216716 kb
Host smart-16c867dc-452c-4d46-bb28-7e35bd085157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829784587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1829784587
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2781833005
Short name T665
Test name
Test status
Simulation time 50492106 ps
CPU time 1.58 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 217792 kb
Host smart-3a2c363c-0624-4f7c-bf59-4f31007f2b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781833005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2781833005
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1057546299
Short name T615
Test name
Test status
Simulation time 42804194 ps
CPU time 1.55 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 216896 kb
Host smart-28ee6928-c429-406b-a16a-afd3e7558481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057546299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1057546299
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2132978074
Short name T631
Test name
Test status
Simulation time 32045551 ps
CPU time 1.21 seconds
Started May 30 02:04:54 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 219336 kb
Host smart-b5764219-531e-45e9-95b3-e54eb4a155c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132978074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2132978074
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3656385835
Short name T2
Test name
Test status
Simulation time 89199611 ps
CPU time 1.02 seconds
Started May 30 02:04:45 PM PDT 24
Finished May 30 02:04:47 PM PDT 24
Peak memory 216792 kb
Host smart-79697fae-1c28-4bdf-91eb-8ed388b744bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656385835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3656385835
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3382584117
Short name T544
Test name
Test status
Simulation time 29867383 ps
CPU time 1.21 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 216564 kb
Host smart-6df8819a-a550-4189-b5f4-2b21dec6f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382584117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3382584117
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3505441486
Short name T649
Test name
Test status
Simulation time 42798231 ps
CPU time 1.25 seconds
Started May 30 02:04:47 PM PDT 24
Finished May 30 02:04:49 PM PDT 24
Peak memory 219324 kb
Host smart-ca12b19c-44f4-4c95-b821-c9300bcc7345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505441486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3505441486
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3636555503
Short name T540
Test name
Test status
Simulation time 39685423 ps
CPU time 1.39 seconds
Started May 30 02:04:45 PM PDT 24
Finished May 30 02:04:48 PM PDT 24
Peak memory 216640 kb
Host smart-8c17d3a7-1d6f-44f1-83f2-f09e5ff3f0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636555503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3636555503
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3614991494
Short name T292
Test name
Test status
Simulation time 68324137 ps
CPU time 1.06 seconds
Started May 30 02:04:52 PM PDT 24
Finished May 30 02:04:54 PM PDT 24
Peak memory 216752 kb
Host smart-00cba028-a2c9-409b-a7b9-639fad789703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614991494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3614991494
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1669973131
Short name T670
Test name
Test status
Simulation time 131222884 ps
CPU time 1.54 seconds
Started May 30 02:04:47 PM PDT 24
Finished May 30 02:04:49 PM PDT 24
Peak memory 218940 kb
Host smart-b74f861d-961b-4366-a593-a035adededc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669973131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1669973131
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2416097020
Short name T272
Test name
Test status
Simulation time 24490556 ps
CPU time 1.21 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 215380 kb
Host smart-811381b3-7584-49c7-ad72-12f8de0b5232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416097020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2416097020
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.510448114
Short name T425
Test name
Test status
Simulation time 37417832 ps
CPU time 1.04 seconds
Started May 30 02:01:24 PM PDT 24
Finished May 30 02:01:26 PM PDT 24
Peak memory 214548 kb
Host smart-696ba39d-5e49-40d6-a22f-f69589cc013b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510448114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.510448114
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2547699771
Short name T733
Test name
Test status
Simulation time 29170126 ps
CPU time 0.82 seconds
Started May 30 02:01:26 PM PDT 24
Finished May 30 02:01:28 PM PDT 24
Peak memory 215688 kb
Host smart-692b30f4-ec1d-4b1b-bc79-55daef04a59d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547699771 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2547699771
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.3652100919
Short name T56
Test name
Test status
Simulation time 22985606 ps
CPU time 1.1 seconds
Started May 30 02:01:22 PM PDT 24
Finished May 30 02:01:24 PM PDT 24
Peak memory 219396 kb
Host smart-f11a32b9-13bc-4672-9b34-f6eb3777daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652100919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3652100919
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.3388564713
Short name T614
Test name
Test status
Simulation time 40579012 ps
CPU time 1.67 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:28 PM PDT 24
Peak memory 219512 kb
Host smart-2520421b-e7c8-4513-a506-79bb7d389f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388564713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3388564713
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1903838414
Short name T695
Test name
Test status
Simulation time 22935815 ps
CPU time 1.12 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 215084 kb
Host smart-dd75bc1e-163f-4e7b-b9ff-312b391b40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903838414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1903838414
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.835744635
Short name T689
Test name
Test status
Simulation time 68437581 ps
CPU time 0.89 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 214876 kb
Host smart-c180affa-de6f-4367-9074-fd5436f49e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835744635 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.835744635
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1693849869
Short name T468
Test name
Test status
Simulation time 146914757 ps
CPU time 2.3 seconds
Started May 30 02:01:24 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 215084 kb
Host smart-8cbf29a0-8c9c-4cbf-8317-c73438673828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693849869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1693849869
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1253852948
Short name T208
Test name
Test status
Simulation time 258365698561 ps
CPU time 1087.09 seconds
Started May 30 02:01:24 PM PDT 24
Finished May 30 02:19:32 PM PDT 24
Peak memory 221988 kb
Host smart-03e2272c-efd1-4a03-9980-601cc2d04110
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253852948 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1253852948
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4158336184
Short name T198
Test name
Test status
Simulation time 127470427 ps
CPU time 1.33 seconds
Started May 30 02:02:35 PM PDT 24
Finished May 30 02:02:37 PM PDT 24
Peak memory 215376 kb
Host smart-c1e8d58c-8a73-457f-a838-8775da01462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158336184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4158336184
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.155697859
Short name T800
Test name
Test status
Simulation time 24568748 ps
CPU time 1.1 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:32 PM PDT 24
Peak memory 206368 kb
Host smart-29b0c069-9c58-421d-8eb7-d904e392939a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155697859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.155697859
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1644689980
Short name T186
Test name
Test status
Simulation time 30290753 ps
CPU time 0.81 seconds
Started May 30 02:02:32 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 216084 kb
Host smart-4867bdbf-9653-4816-9d93-0044eba0040d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644689980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1644689980
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3670722827
Short name T621
Test name
Test status
Simulation time 83555647 ps
CPU time 1.09 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 219184 kb
Host smart-ef32645a-b011-429b-aed8-f3420f352585
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670722827 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3670722827
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3818997701
Short name T538
Test name
Test status
Simulation time 20508280 ps
CPU time 1.15 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 219380 kb
Host smart-c69ba303-3d21-467a-98ae-f933d72ebc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818997701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3818997701
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3106674329
Short name T554
Test name
Test status
Simulation time 29461355 ps
CPU time 1.24 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 216748 kb
Host smart-ec3a2a27-dedb-4f2a-a177-8f611032dd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106674329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3106674329
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.39072569
Short name T685
Test name
Test status
Simulation time 44034636 ps
CPU time 0.92 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 215108 kb
Host smart-7a224404-21e7-4618-802e-23c15d01c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39072569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.39072569
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1653080790
Short name T732
Test name
Test status
Simulation time 26809784 ps
CPU time 0.94 seconds
Started May 30 02:02:29 PM PDT 24
Finished May 30 02:02:31 PM PDT 24
Peak memory 214828 kb
Host smart-71fc8f12-1041-424f-92a3-eb1044ac5eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653080790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1653080790
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.392815979
Short name T702
Test name
Test status
Simulation time 55398639 ps
CPU time 0.94 seconds
Started May 30 02:02:35 PM PDT 24
Finished May 30 02:02:36 PM PDT 24
Peak memory 205980 kb
Host smart-44683ac9-4bfb-4c02-af02-3d3038932e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392815979 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.392815979
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2859712144
Short name T571
Test name
Test status
Simulation time 26599586609 ps
CPU time 368.19 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:08:39 PM PDT 24
Peak memory 218124 kb
Host smart-c745b69c-7d5d-477d-ad4b-f1c7e60e4d4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859712144 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2859712144
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3583031946
Short name T730
Test name
Test status
Simulation time 43473997 ps
CPU time 1.58 seconds
Started May 30 02:04:49 PM PDT 24
Finished May 30 02:04:52 PM PDT 24
Peak memory 218908 kb
Host smart-1568f123-8f81-4ff1-ad64-0df6ecc7f88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583031946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3583031946
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.166315367
Short name T589
Test name
Test status
Simulation time 40306697 ps
CPU time 1.43 seconds
Started May 30 02:04:52 PM PDT 24
Finished May 30 02:04:54 PM PDT 24
Peak memory 219132 kb
Host smart-08cc589c-a184-4de3-946c-a44c0639bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166315367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.166315367
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2764030615
Short name T496
Test name
Test status
Simulation time 102518033 ps
CPU time 1.27 seconds
Started May 30 02:04:51 PM PDT 24
Finished May 30 02:04:53 PM PDT 24
Peak memory 219532 kb
Host smart-9744019c-03f3-4cd4-b227-b4b157317c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764030615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2764030615
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3938137526
Short name T378
Test name
Test status
Simulation time 113075246 ps
CPU time 1.52 seconds
Started May 30 02:04:50 PM PDT 24
Finished May 30 02:04:53 PM PDT 24
Peak memory 218152 kb
Host smart-55b191f7-7067-4b58-9740-424e2070f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938137526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3938137526
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1098015042
Short name T618
Test name
Test status
Simulation time 37171000 ps
CPU time 1.4 seconds
Started May 30 02:04:50 PM PDT 24
Finished May 30 02:04:52 PM PDT 24
Peak memory 217900 kb
Host smart-ba97f611-80de-4ef9-93de-2af708f5918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098015042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1098015042
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.930951987
Short name T351
Test name
Test status
Simulation time 28096763 ps
CPU time 1.26 seconds
Started May 30 02:04:47 PM PDT 24
Finished May 30 02:04:49 PM PDT 24
Peak memory 218072 kb
Host smart-c13a54f5-d61f-4a88-96c2-92ca11b5baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930951987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.930951987
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3734949806
Short name T676
Test name
Test status
Simulation time 86025017 ps
CPU time 1.43 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:50 PM PDT 24
Peak memory 218292 kb
Host smart-536fa9b0-1355-4907-bc15-910ccc6902bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734949806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3734949806
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2041202895
Short name T289
Test name
Test status
Simulation time 106549614 ps
CPU time 1.3 seconds
Started May 30 02:04:49 PM PDT 24
Finished May 30 02:04:52 PM PDT 24
Peak memory 218680 kb
Host smart-fb44937a-5ac9-43a1-a2b9-ac0047b3173f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041202895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2041202895
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2040500528
Short name T558
Test name
Test status
Simulation time 45139648 ps
CPU time 1.9 seconds
Started May 30 02:04:47 PM PDT 24
Finished May 30 02:04:49 PM PDT 24
Peak memory 217868 kb
Host smart-ddb7ddce-cbd4-4ae2-b826-b1da923a58a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040500528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2040500528
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1155261417
Short name T29
Test name
Test status
Simulation time 80149772 ps
CPU time 1.18 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:07 PM PDT 24
Peak memory 215400 kb
Host smart-ada4bbea-ddf9-4462-9f8b-089a87a7872b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155261417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1155261417
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2620858612
Short name T386
Test name
Test status
Simulation time 34381876 ps
CPU time 0.99 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 214696 kb
Host smart-c0d4b621-da51-41e5-971c-02658024e86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620858612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2620858612
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1806632128
Short name T91
Test name
Test status
Simulation time 17301196 ps
CPU time 0.88 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 216224 kb
Host smart-73d519cb-5acb-4e9a-9dc0-67e5154f774e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806632128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1806632128
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1626161521
Short name T193
Test name
Test status
Simulation time 73995171 ps
CPU time 1.05 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:12 PM PDT 24
Peak memory 219384 kb
Host smart-52ab4d67-3636-47e6-9333-b4caca161876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626161521 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1626161521
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2452438885
Short name T13
Test name
Test status
Simulation time 132605739 ps
CPU time 1.19 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:02:33 PM PDT 24
Peak memory 219260 kb
Host smart-1d2e949c-4a6c-4206-8248-a0fb73a84653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452438885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2452438885
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2069265199
Short name T16
Test name
Test status
Simulation time 21450548 ps
CPU time 1.25 seconds
Started May 30 02:03:09 PM PDT 24
Finished May 30 02:03:13 PM PDT 24
Peak memory 223640 kb
Host smart-6d7a76d0-f632-4043-a726-c0ff64f0c56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069265199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2069265199
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.677198698
Short name T731
Test name
Test status
Simulation time 16544097 ps
CPU time 0.99 seconds
Started May 30 02:02:35 PM PDT 24
Finished May 30 02:02:36 PM PDT 24
Peak memory 215096 kb
Host smart-aa53cdd9-6655-4c02-b50c-3d9a51cb40b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677198698 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.677198698
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2878710457
Short name T442
Test name
Test status
Simulation time 280352817 ps
CPU time 3.26 seconds
Started May 30 02:02:30 PM PDT 24
Finished May 30 02:02:35 PM PDT 24
Peak memory 216824 kb
Host smart-9a6dc114-03c3-4ed9-89b9-1a27100ca052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878710457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2878710457
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2288542569
Short name T431
Test name
Test status
Simulation time 37475690077 ps
CPU time 418.75 seconds
Started May 30 02:02:31 PM PDT 24
Finished May 30 02:09:31 PM PDT 24
Peak memory 218572 kb
Host smart-d49b7f07-6d4d-4a80-a479-74a096463cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288542569 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2288542569
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1773805644
Short name T281
Test name
Test status
Simulation time 30641486 ps
CPU time 1.48 seconds
Started May 30 02:04:51 PM PDT 24
Finished May 30 02:04:54 PM PDT 24
Peak memory 217988 kb
Host smart-8c0cbc50-347b-43db-a71d-0decb733ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773805644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1773805644
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2877853754
Short name T141
Test name
Test status
Simulation time 94921128 ps
CPU time 2.34 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:57 PM PDT 24
Peak memory 219524 kb
Host smart-f44e86b1-fca6-418a-b6c1-4ddb7abbaa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877853754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2877853754
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.4017104588
Short name T480
Test name
Test status
Simulation time 55800811 ps
CPU time 1.26 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 216672 kb
Host smart-6414cd7a-f535-4823-bebd-40ba7cb22e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017104588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.4017104588
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2259874050
Short name T687
Test name
Test status
Simulation time 48633054 ps
CPU time 1.48 seconds
Started May 30 02:04:54 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 218204 kb
Host smart-be00b422-1075-4bcf-89ec-8adef78b108c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259874050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2259874050
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.439493659
Short name T683
Test name
Test status
Simulation time 119085747 ps
CPU time 1.14 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 219316 kb
Host smart-a1712eed-0162-45de-a514-778faa4f02f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439493659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.439493659
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1235568639
Short name T316
Test name
Test status
Simulation time 57026466 ps
CPU time 1.06 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:50 PM PDT 24
Peak memory 215020 kb
Host smart-a686a80b-5c49-49f1-bb95-0e3b67825f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235568639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1235568639
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4033295530
Short name T818
Test name
Test status
Simulation time 135413748 ps
CPU time 2.53 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:57 PM PDT 24
Peak memory 218944 kb
Host smart-66e5113b-0ca8-4276-9ed9-58b0c113a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033295530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4033295530
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.574317700
Short name T400
Test name
Test status
Simulation time 411183092 ps
CPU time 3.58 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:53 PM PDT 24
Peak memory 219396 kb
Host smart-31ba0a8c-dfe1-47b3-9864-eeb686038ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574317700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.574317700
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1540109957
Short name T252
Test name
Test status
Simulation time 67721353 ps
CPU time 1.18 seconds
Started May 30 02:04:48 PM PDT 24
Finished May 30 02:04:50 PM PDT 24
Peak memory 218172 kb
Host smart-9b829382-a099-4723-adb0-7e6d2853a5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540109957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1540109957
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3360206681
Short name T80
Test name
Test status
Simulation time 191727050 ps
CPU time 1.21 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:12 PM PDT 24
Peak memory 215364 kb
Host smart-19bdcdb9-11fa-45d8-bd9f-56435b66208b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360206681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3360206681
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.550478992
Short name T781
Test name
Test status
Simulation time 18389025 ps
CPU time 1.03 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 214580 kb
Host smart-73ca4042-90c1-4066-b2a6-1d8461094125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550478992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.550478992
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3228245027
Short name T467
Test name
Test status
Simulation time 92381896 ps
CPU time 1.15 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:07 PM PDT 24
Peak memory 216708 kb
Host smart-ecb1a4ae-d756-4ea4-8ef2-e6e9ab5c5a2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228245027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3228245027
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1215820884
Short name T464
Test name
Test status
Simulation time 45199506 ps
CPU time 1.14 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 218236 kb
Host smart-18c19acf-92af-46b8-9eba-9691808edf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215820884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1215820884
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.891810215
Short name T716
Test name
Test status
Simulation time 56084673 ps
CPU time 1.27 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 217964 kb
Host smart-eb02fd6a-78d9-4f11-a1dd-eab8979c39b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891810215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.891810215
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.650483813
Short name T124
Test name
Test status
Simulation time 22341923 ps
CPU time 1.1 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:12 PM PDT 24
Peak memory 215588 kb
Host smart-ca6d6f1f-99ec-4700-bd3d-82dae92c22dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650483813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.650483813
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1154102150
Short name T373
Test name
Test status
Simulation time 15298691 ps
CPU time 1.02 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 214932 kb
Host smart-6f6b38f8-3cc7-490b-a944-c40f471bbc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154102150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1154102150
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2570953343
Short name T412
Test name
Test status
Simulation time 157234513 ps
CPU time 3.44 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 218160 kb
Host smart-4e430f54-3a8e-4329-ba41-f53c705fdabf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570953343 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2570953343
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.4187424913
Short name T470
Test name
Test status
Simulation time 411460722768 ps
CPU time 2261.29 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:40:50 PM PDT 24
Peak memory 229052 kb
Host smart-82120218-c3d3-4db4-a976-6de9d59f63af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187424913 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.4187424913
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.1830908558
Short name T133
Test name
Test status
Simulation time 40598159 ps
CPU time 1.32 seconds
Started May 30 02:04:51 PM PDT 24
Finished May 30 02:04:54 PM PDT 24
Peak memory 218140 kb
Host smart-02bb7dd5-fbc4-4385-88ef-a49b6fe2f023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830908558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1830908558
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1205990044
Short name T506
Test name
Test status
Simulation time 46848652 ps
CPU time 1.69 seconds
Started May 30 02:04:52 PM PDT 24
Finished May 30 02:04:55 PM PDT 24
Peak memory 217904 kb
Host smart-01fa0c05-4bac-49c2-a868-5d32a05a85db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205990044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1205990044
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2573432612
Short name T749
Test name
Test status
Simulation time 85523134 ps
CPU time 2.81 seconds
Started May 30 02:04:53 PM PDT 24
Finished May 30 02:04:57 PM PDT 24
Peak memory 219544 kb
Host smart-711477e4-15a6-4c18-a462-afcd1bbd5675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573432612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2573432612
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.665355333
Short name T713
Test name
Test status
Simulation time 83788884 ps
CPU time 1.38 seconds
Started May 30 02:04:54 PM PDT 24
Finished May 30 02:04:56 PM PDT 24
Peak memory 217160 kb
Host smart-31be63fa-dad8-4f53-97af-8111d71a6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665355333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.665355333
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.4294846355
Short name T284
Test name
Test status
Simulation time 74416593 ps
CPU time 1.32 seconds
Started May 30 02:04:50 PM PDT 24
Finished May 30 02:04:52 PM PDT 24
Peak memory 218388 kb
Host smart-eb1e8175-9f7b-4d65-ac9e-6689501bf99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294846355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.4294846355
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3985650
Short name T690
Test name
Test status
Simulation time 26807404 ps
CPU time 1.28 seconds
Started May 30 02:04:49 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 216848 kb
Host smart-3a3f2414-def6-45ce-a323-035e8e426686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3985650
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.911863788
Short name T14
Test name
Test status
Simulation time 73958467 ps
CPU time 1.23 seconds
Started May 30 02:04:49 PM PDT 24
Finished May 30 02:04:51 PM PDT 24
Peak memory 217004 kb
Host smart-c2aeca93-4825-46cc-98f7-925821b6d824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911863788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.911863788
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1259285817
Short name T508
Test name
Test status
Simulation time 632909436 ps
CPU time 4.08 seconds
Started May 30 02:05:01 PM PDT 24
Finished May 30 02:05:06 PM PDT 24
Peak memory 219432 kb
Host smart-cedd17cb-600f-4dc5-9616-b6aa6fd36f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259285817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1259285817
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1134223578
Short name T831
Test name
Test status
Simulation time 97662343 ps
CPU time 1.19 seconds
Started May 30 02:04:57 PM PDT 24
Finished May 30 02:04:59 PM PDT 24
Peak memory 218140 kb
Host smart-5408fb46-847e-4ce3-9480-edb4d0f31e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134223578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1134223578
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1692329767
Short name T30
Test name
Test status
Simulation time 274021916 ps
CPU time 1.31 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 215376 kb
Host smart-3614df28-8c5b-4651-ad58-8053569661e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692329767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1692329767
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_disable.2740727016
Short name T199
Test name
Test status
Simulation time 18232986 ps
CPU time 0.88 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:12 PM PDT 24
Peak memory 215312 kb
Host smart-6d76880a-e1a0-4ee7-aa1f-6cd170e346a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740727016 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2740727016
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_genbits.2998830570
Short name T752
Test name
Test status
Simulation time 87664727 ps
CPU time 1.16 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 216596 kb
Host smart-5a14e6f8-862e-40a6-a204-c36ee3256f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998830570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2998830570
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2025679980
Short name T119
Test name
Test status
Simulation time 21426027 ps
CPU time 1.07 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 215392 kb
Host smart-e180ca79-1cac-4f06-acaf-846082898dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025679980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2025679980
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.975548118
Short name T111
Test name
Test status
Simulation time 14877181 ps
CPU time 0.94 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 215012 kb
Host smart-2573bcf2-f98d-44f4-8018-31989bade2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975548118 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.975548118
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.142370136
Short name T664
Test name
Test status
Simulation time 396353038 ps
CPU time 4.4 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 217984 kb
Host smart-050ad03f-02f5-456e-8c0f-85ddf71b1c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142370136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.142370136
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4280434069
Short name T384
Test name
Test status
Simulation time 88229743096 ps
CPU time 495.27 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:11:22 PM PDT 24
Peak memory 218840 kb
Host smart-b600f0cf-d9b6-46d2-9774-6460b8f69448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280434069 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4280434069
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3066650778
Short name T397
Test name
Test status
Simulation time 91486025 ps
CPU time 1.29 seconds
Started May 30 02:04:59 PM PDT 24
Finished May 30 02:05:01 PM PDT 24
Peak memory 216796 kb
Host smart-c363e802-51e3-4f72-82c4-cfbbbc5f4381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066650778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3066650778
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3415226564
Short name T421
Test name
Test status
Simulation time 56177991 ps
CPU time 2.29 seconds
Started May 30 02:04:57 PM PDT 24
Finished May 30 02:05:00 PM PDT 24
Peak memory 218876 kb
Host smart-c2b4b051-2669-45c5-82e5-13e79a56ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415226564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3415226564
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3999848782
Short name T528
Test name
Test status
Simulation time 34390304 ps
CPU time 1.15 seconds
Started May 30 02:04:59 PM PDT 24
Finished May 30 02:05:01 PM PDT 24
Peak memory 216604 kb
Host smart-f3118f28-35f4-4be7-a69d-2a63b626c550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999848782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3999848782
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3573372370
Short name T770
Test name
Test status
Simulation time 124548353 ps
CPU time 1.21 seconds
Started May 30 02:04:57 PM PDT 24
Finished May 30 02:04:59 PM PDT 24
Peak memory 219292 kb
Host smart-2ac59b09-b782-417e-a01d-19e3acd9f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573372370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3573372370
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.85558911
Short name T519
Test name
Test status
Simulation time 52745562 ps
CPU time 1.17 seconds
Started May 30 02:04:56 PM PDT 24
Finished May 30 02:04:58 PM PDT 24
Peak memory 217856 kb
Host smart-7df2c16e-a65a-482f-b8ab-1c9799c7f01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85558911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.85558911
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.4144326576
Short name T633
Test name
Test status
Simulation time 35955208 ps
CPU time 1.35 seconds
Started May 30 02:04:58 PM PDT 24
Finished May 30 02:05:00 PM PDT 24
Peak memory 216884 kb
Host smart-26a05ccd-64cd-42a6-876a-95ec61cec378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144326576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.4144326576
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3890621110
Short name T740
Test name
Test status
Simulation time 89064926 ps
CPU time 1.88 seconds
Started May 30 02:04:58 PM PDT 24
Finished May 30 02:05:00 PM PDT 24
Peak memory 219584 kb
Host smart-b1a11181-87b1-4244-8866-0d1f23211e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890621110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3890621110
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.368429766
Short name T560
Test name
Test status
Simulation time 95347740 ps
CPU time 2.64 seconds
Started May 30 02:05:09 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 218836 kb
Host smart-549985cb-b6c8-41c1-90e5-5e25b37c56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368429766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.368429766
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.4279502412
Short name T768
Test name
Test status
Simulation time 42830506 ps
CPU time 1.13 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 217064 kb
Host smart-53fd5107-1199-46d1-b631-842370c5699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279502412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.4279502412
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1059599996
Short name T587
Test name
Test status
Simulation time 37532267 ps
CPU time 1.18 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 215036 kb
Host smart-b44798a5-e117-4f23-8291-d9e9e82c3614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059599996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1059599996
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.222513739
Short name T201
Test name
Test status
Simulation time 94618652 ps
CPU time 1.29 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 215376 kb
Host smart-f771304a-e177-4ddb-9b11-d82e167db700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222513739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.222513739
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.675506958
Short name T843
Test name
Test status
Simulation time 16473749 ps
CPU time 0.97 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 206288 kb
Host smart-fd8f76d2-e65e-4634-9706-d506c503c0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675506958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.675506958
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.475218215
Short name T834
Test name
Test status
Simulation time 11374739 ps
CPU time 0.91 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 216076 kb
Host smart-bc4ce701-d951-4899-bb61-e80ab50e5e27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475218215 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.475218215
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1206527881
Short name T245
Test name
Test status
Simulation time 26889782 ps
CPU time 1.04 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 217888 kb
Host smart-4627d554-c9e6-47fe-81a7-fa9407329d8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206527881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1206527881
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3191564532
Short name T83
Test name
Test status
Simulation time 24731414 ps
CPU time 0.94 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 218056 kb
Host smart-8072a3a8-dfa4-45a9-bbf9-85f56b8a6015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191564532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3191564532
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.183703716
Short name T17
Test name
Test status
Simulation time 20685894 ps
CPU time 1.25 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 223640 kb
Host smart-0976a333-937b-4fe9-8b2b-875b1fd18b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183703716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.183703716
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3093627214
Short name T414
Test name
Test status
Simulation time 15644882 ps
CPU time 0.96 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 206828 kb
Host smart-a207a94f-37b7-4031-8bd3-1f518ee21fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093627214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3093627214
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2416013649
Short name T163
Test name
Test status
Simulation time 135288124 ps
CPU time 2.09 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:11 PM PDT 24
Peak memory 214888 kb
Host smart-5f444523-6447-4a20-b210-f885266ac3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416013649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2416013649
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1823299091
Short name T205
Test name
Test status
Simulation time 25195886054 ps
CPU time 642.28 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:13:50 PM PDT 24
Peak memory 218508 kb
Host smart-4e66dee9-b9fc-4093-9466-5c9f64056a52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823299091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1823299091
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2437045638
Short name T821
Test name
Test status
Simulation time 82931673 ps
CPU time 1.1 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 216680 kb
Host smart-60b3731f-8c78-42de-9fb1-a999493b2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437045638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2437045638
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1756869167
Short name T600
Test name
Test status
Simulation time 201843617 ps
CPU time 2.39 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 219396 kb
Host smart-86c2337e-e2bb-4e11-9c0e-12c42cf39d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756869167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1756869167
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.2720490685
Short name T808
Test name
Test status
Simulation time 45667629 ps
CPU time 1.08 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 216636 kb
Host smart-760eb5f0-c2a7-4aa9-b0d5-3b2712718904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720490685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2720490685
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1498935422
Short name T427
Test name
Test status
Simulation time 87346994 ps
CPU time 2.88 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:17 PM PDT 24
Peak memory 218340 kb
Host smart-d55e6fb9-1416-43ac-9ea3-a83088e3ea6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498935422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1498935422
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.975624221
Short name T565
Test name
Test status
Simulation time 31172535 ps
CPU time 1.31 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 218060 kb
Host smart-78c9e9b9-2f8e-4038-9c7a-92dd3421b067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975624221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.975624221
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.647693917
Short name T636
Test name
Test status
Simulation time 24781232 ps
CPU time 1.3 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 216972 kb
Host smart-e0f0c865-8e25-44c7-91a2-70c056f267ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647693917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.647693917
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3489707876
Short name T550
Test name
Test status
Simulation time 39534266 ps
CPU time 1.54 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 218120 kb
Host smart-f3bf8ce4-ad5b-435a-81dd-b9175a4684e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489707876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3489707876
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1364610053
Short name T617
Test name
Test status
Simulation time 66638173 ps
CPU time 1.03 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:12 PM PDT 24
Peak memory 216604 kb
Host smart-eeee3060-3f9c-4d8c-9294-7afec2445f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364610053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1364610053
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1475897400
Short name T691
Test name
Test status
Simulation time 59848112 ps
CPU time 1.81 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 218200 kb
Host smart-bf4854c5-e698-40e8-9a0d-fd7e6ec9e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475897400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1475897400
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1251506935
Short name T326
Test name
Test status
Simulation time 83671661 ps
CPU time 1.53 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 218172 kb
Host smart-66c6f7c4-4f3a-4895-88df-d7b2c975b3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251506935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1251506935
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3726178260
Short name T610
Test name
Test status
Simulation time 48830492 ps
CPU time 1.28 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 215412 kb
Host smart-d61f6bf1-b2d5-4678-82ea-746932e573c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726178260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3726178260
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3087518888
Short name T462
Test name
Test status
Simulation time 149925287 ps
CPU time 0.85 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 206152 kb
Host smart-902449a0-9033-460b-8ee4-f9af69b2657d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087518888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3087518888
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2492741268
Short name T85
Test name
Test status
Simulation time 10476659 ps
CPU time 0.89 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:07 PM PDT 24
Peak memory 216164 kb
Host smart-92722783-2c34-4131-bd08-d7af335758c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492741268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2492741268
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2097469973
Short name T307
Test name
Test status
Simulation time 152783647 ps
CPU time 1.08 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 216500 kb
Host smart-ac34bd46-c9d9-4323-9056-a59c6a335b3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097469973 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2097469973
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3291717318
Short name T6
Test name
Test status
Simulation time 33098749 ps
CPU time 1.05 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 219068 kb
Host smart-a376ec4f-9ed8-493e-a782-3cf26cb61dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291717318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3291717318
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.1471245019
Short name T409
Test name
Test status
Simulation time 46505850 ps
CPU time 1.51 seconds
Started May 30 02:03:09 PM PDT 24
Finished May 30 02:03:13 PM PDT 24
Peak memory 218048 kb
Host smart-e91bf421-70cd-4b03-a30b-732f7ad0b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471245019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1471245019
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.4173403665
Short name T122
Test name
Test status
Simulation time 24768453 ps
CPU time 0.93 seconds
Started May 30 02:03:06 PM PDT 24
Finished May 30 02:03:09 PM PDT 24
Peak memory 215420 kb
Host smart-09b5c24f-de36-44d5-9d65-de931c00a7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173403665 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4173403665
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3263972587
Short name T358
Test name
Test status
Simulation time 16440678 ps
CPU time 1 seconds
Started May 30 02:03:05 PM PDT 24
Finished May 30 02:03:08 PM PDT 24
Peak memory 214996 kb
Host smart-87cbc6be-9fc6-47c9-aae7-65d4c76fd38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263972587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3263972587
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1471861669
Short name T433
Test name
Test status
Simulation time 299924213 ps
CPU time 5.53 seconds
Started May 30 02:03:08 PM PDT 24
Finished May 30 02:03:16 PM PDT 24
Peak memory 216284 kb
Host smart-fb24cd06-6321-40b0-8927-51c55e3b74b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471861669 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1471861669
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3376478887
Short name T775
Test name
Test status
Simulation time 335970387102 ps
CPU time 1748.8 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:32:18 PM PDT 24
Peak memory 224728 kb
Host smart-049b1ce1-a2e4-4dc7-acab-ef5f4a103fab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376478887 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3376478887
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1531344331
Short name T440
Test name
Test status
Simulation time 43561092 ps
CPU time 1.17 seconds
Started May 30 02:05:08 PM PDT 24
Finished May 30 02:05:10 PM PDT 24
Peak memory 216672 kb
Host smart-442c08a2-23ed-4aa3-9287-26a26a9ac32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531344331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1531344331
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1601543843
Short name T28
Test name
Test status
Simulation time 69580177 ps
CPU time 1.36 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 218368 kb
Host smart-de2d652e-6ea6-4679-9df3-a52ab27c440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601543843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1601543843
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1733423316
Short name T819
Test name
Test status
Simulation time 50133640 ps
CPU time 1.3 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 217476 kb
Host smart-464db2ad-0c65-428a-8d18-a78b800960ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733423316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1733423316
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3171696809
Short name T673
Test name
Test status
Simulation time 83488186 ps
CPU time 2.18 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 219416 kb
Host smart-87ab77b2-f43c-4b49-96c5-7b19b15b3849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171696809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3171696809
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1839687987
Short name T612
Test name
Test status
Simulation time 104337245 ps
CPU time 1.55 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 218308 kb
Host smart-d3fde7a4-f63c-4aef-a8b2-deb1af7a5aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839687987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1839687987
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1987561282
Short name T697
Test name
Test status
Simulation time 373177596 ps
CPU time 2.89 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 219464 kb
Host smart-999d46d4-5260-4712-9133-ba5e3eba5d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987561282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1987561282
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1853758386
Short name T604
Test name
Test status
Simulation time 119507393 ps
CPU time 1.28 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:05:17 PM PDT 24
Peak memory 216964 kb
Host smart-eb0f1222-a670-4535-a396-9be594b3a8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853758386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1853758386
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1327811092
Short name T451
Test name
Test status
Simulation time 60376600 ps
CPU time 1.67 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 218164 kb
Host smart-2f36398d-280d-475c-92c5-c91b8ae0afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327811092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1327811092
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.559288277
Short name T635
Test name
Test status
Simulation time 79849361 ps
CPU time 2.86 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:21 PM PDT 24
Peak memory 216856 kb
Host smart-b1fbe6ac-9e06-455e-b5ee-b54d3ea9e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559288277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.559288277
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3214043578
Short name T364
Test name
Test status
Simulation time 54167261 ps
CPU time 1.45 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 219348 kb
Host smart-ddad58fd-45ca-463f-8568-1395c119157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214043578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3214043578
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3702515952
Short name T197
Test name
Test status
Simulation time 70720500 ps
CPU time 1.2 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 215396 kb
Host smart-bc06fb41-5f6f-4d24-8d8f-bc4bb6af958f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702515952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3702515952
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3388086614
Short name T367
Test name
Test status
Simulation time 57941324 ps
CPU time 0.96 seconds
Started May 30 02:03:14 PM PDT 24
Finished May 30 02:03:16 PM PDT 24
Peak memory 206284 kb
Host smart-faf402fc-d84f-4208-8db8-b467ab0f7a0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388086614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3388086614
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.326140536
Short name T526
Test name
Test status
Simulation time 126017816 ps
CPU time 0.85 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 215984 kb
Host smart-f06d1995-aa04-4c63-b422-1a5335eae910
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326140536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.326140536
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3477375778
Short name T408
Test name
Test status
Simulation time 76917941 ps
CPU time 1.02 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 216620 kb
Host smart-e862d3c5-c989-4763-8c9f-c52b3929f1fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477375778 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3477375778
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4042841890
Short name T583
Test name
Test status
Simulation time 21574297 ps
CPU time 1.06 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 219360 kb
Host smart-46782ba1-4446-4383-96eb-79a6ce9c6023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042841890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4042841890
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3982957714
Short name T359
Test name
Test status
Simulation time 68816714 ps
CPU time 1.07 seconds
Started May 30 02:03:12 PM PDT 24
Finished May 30 02:03:15 PM PDT 24
Peak memory 215028 kb
Host smart-c0c97acb-69e3-49ad-add7-712d30b0ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982957714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3982957714
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.695366470
Short name T549
Test name
Test status
Simulation time 120045760 ps
CPU time 0.95 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 223440 kb
Host smart-1e2ed211-f256-4706-bdc5-59aa738c4d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695366470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.695366470
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3427586969
Short name T112
Test name
Test status
Simulation time 45029984 ps
CPU time 0.96 seconds
Started May 30 02:03:07 PM PDT 24
Finished May 30 02:03:10 PM PDT 24
Peak memory 215012 kb
Host smart-c4cafea2-0ffb-4f12-97f4-e93f2631c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427586969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3427586969
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2024114889
Short name T472
Test name
Test status
Simulation time 271051230 ps
CPU time 5.13 seconds
Started May 30 02:03:14 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 216500 kb
Host smart-be10649d-d011-4c07-ac70-a9bef7b6f996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024114889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2024114889
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3712501476
Short name T209
Test name
Test status
Simulation time 15007668640 ps
CPU time 322.66 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:08:38 PM PDT 24
Peak memory 223224 kb
Host smart-4557748f-80da-4ca0-ae09-97055f63f410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712501476 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3712501476
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.3033121989
Short name T294
Test name
Test status
Simulation time 34399259 ps
CPU time 1.15 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 218288 kb
Host smart-52f42c73-4313-4e13-97e3-a147510e2617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033121989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3033121989
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.779401803
Short name T545
Test name
Test status
Simulation time 46042769 ps
CPU time 1.38 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 217992 kb
Host smart-e3eede15-ac67-4de4-8a17-581c8d40173b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779401803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.779401803
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.329330852
Short name T801
Test name
Test status
Simulation time 71015049 ps
CPU time 1.58 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 218132 kb
Host smart-cd9e846c-a227-43c2-878e-588592d3a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329330852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.329330852
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3202028605
Short name T709
Test name
Test status
Simulation time 34421847 ps
CPU time 1.24 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 217952 kb
Host smart-ac72078a-5c39-458d-bb8c-3870ff0c07b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202028605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3202028605
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2674613823
Short name T376
Test name
Test status
Simulation time 87704900 ps
CPU time 1.24 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 216664 kb
Host smart-b8d259ae-35bf-4138-98d1-7e89d0699210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674613823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2674613823
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2775218418
Short name T385
Test name
Test status
Simulation time 39165887 ps
CPU time 1.31 seconds
Started May 30 02:05:09 PM PDT 24
Finished May 30 02:05:11 PM PDT 24
Peak memory 217616 kb
Host smart-94f20e67-734e-4ff4-ac23-0d8fa817e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775218418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2775218418
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4095700797
Short name T756
Test name
Test status
Simulation time 69617048 ps
CPU time 1.45 seconds
Started May 30 02:05:09 PM PDT 24
Finished May 30 02:05:12 PM PDT 24
Peak memory 218168 kb
Host smart-3fbfac72-1252-4b6f-a7ea-ea9ab3e64284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095700797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4095700797
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3499274996
Short name T660
Test name
Test status
Simulation time 61557501 ps
CPU time 1.2 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 217936 kb
Host smart-5886025e-b72c-410e-af24-0c6ed54f3d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499274996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3499274996
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3226904009
Short name T445
Test name
Test status
Simulation time 49678708 ps
CPU time 1.23 seconds
Started May 30 02:05:09 PM PDT 24
Finished May 30 02:05:11 PM PDT 24
Peak memory 217904 kb
Host smart-6bcb016d-92e7-4209-96da-69c1e901a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226904009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3226904009
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2755767862
Short name T632
Test name
Test status
Simulation time 35737244 ps
CPU time 1.26 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 217148 kb
Host smart-b6d25756-89e6-467e-a90e-53f0ed583fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755767862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2755767862
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2940718978
Short name T167
Test name
Test status
Simulation time 44829133 ps
CPU time 1.17 seconds
Started May 30 02:03:14 PM PDT 24
Finished May 30 02:03:16 PM PDT 24
Peak memory 215396 kb
Host smart-26da0508-cdc0-4d55-ba5a-8a44a9d4f862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940718978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2940718978
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1757803442
Short name T320
Test name
Test status
Simulation time 26809586 ps
CPU time 0.93 seconds
Started May 30 02:03:14 PM PDT 24
Finished May 30 02:03:16 PM PDT 24
Peak memory 206316 kb
Host smart-9355ea22-d115-4740-bdae-06819a7aeffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757803442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1757803442
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3331427269
Short name T677
Test name
Test status
Simulation time 19615771 ps
CPU time 0.89 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:17 PM PDT 24
Peak memory 215736 kb
Host smart-56908021-456a-4a20-93b5-ec933f6462d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331427269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3331427269
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2590484845
Short name T175
Test name
Test status
Simulation time 34473954 ps
CPU time 1.25 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 218100 kb
Host smart-957eac2f-a222-4dff-aa94-60ccda206961
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590484845 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2590484845
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.4206141284
Short name T58
Test name
Test status
Simulation time 51757038 ps
CPU time 0.99 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:17 PM PDT 24
Peak memory 220108 kb
Host smart-d0bc89bb-c233-4c1b-9516-5db1fea8d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206141284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4206141284
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3079847791
Short name T553
Test name
Test status
Simulation time 127060222 ps
CPU time 1.2 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 219388 kb
Host smart-ebf17794-1446-4c9a-be66-f424183507e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079847791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3079847791
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2259585962
Short name T646
Test name
Test status
Simulation time 33070592 ps
CPU time 0.87 seconds
Started May 30 02:03:19 PM PDT 24
Finished May 30 02:03:22 PM PDT 24
Peak memory 215328 kb
Host smart-8296f555-1207-465a-b453-b6c3a7cedf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259585962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2259585962
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.4215850661
Short name T490
Test name
Test status
Simulation time 28953360 ps
CPU time 1 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 214920 kb
Host smart-b6550c9c-fc3a-4934-96cb-edaaf96e5b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215850661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.4215850661
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2454214425
Short name T453
Test name
Test status
Simulation time 787936340 ps
CPU time 4.19 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 215012 kb
Host smart-b899cc31-1f58-4c01-9352-7e12c8bd6298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454214425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2454214425
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2578052803
Short name T642
Test name
Test status
Simulation time 439675133104 ps
CPU time 1417.66 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:26:55 PM PDT 24
Peak memory 223604 kb
Host smart-9718954e-b200-4990-bf9f-520db4a4a857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578052803 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2578052803
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3638191633
Short name T282
Test name
Test status
Simulation time 79854116 ps
CPU time 1.08 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 216268 kb
Host smart-129af915-937f-49d6-bd1f-c23967eea3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638191633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3638191633
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2426166562
Short name T530
Test name
Test status
Simulation time 41091086 ps
CPU time 1.5 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 217904 kb
Host smart-680ecc4f-5044-4789-95e7-54128a2e39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426166562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2426166562
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.862583302
Short name T658
Test name
Test status
Simulation time 139831614 ps
CPU time 1.34 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 218012 kb
Host smart-e642a83f-a400-44de-b40f-9716a461465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862583302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.862583302
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1093607164
Short name T369
Test name
Test status
Simulation time 190187759 ps
CPU time 1.48 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:12 PM PDT 24
Peak memory 219240 kb
Host smart-401343ee-1e5a-4461-afc4-7121e6ca3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093607164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1093607164
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.4098981916
Short name T438
Test name
Test status
Simulation time 36416891 ps
CPU time 1.43 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:13 PM PDT 24
Peak memory 216588 kb
Host smart-8d3a8f25-eb2c-4586-8a23-fddb48d41e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098981916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4098981916
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.718775803
Short name T250
Test name
Test status
Simulation time 35206270 ps
CPU time 1.32 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 216068 kb
Host smart-45d942ae-bc87-48d1-93f1-362906a30435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718775803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.718775803
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.704248460
Short name T135
Test name
Test status
Simulation time 90105282 ps
CPU time 1.44 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 218448 kb
Host smart-0ff5f8c2-3557-4a79-a94d-36ebe265dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704248460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.704248460
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.35491950
Short name T626
Test name
Test status
Simulation time 48116896 ps
CPU time 1.11 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 216692 kb
Host smart-a02f2988-ea1b-4cc1-a415-15a845ab88d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35491950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.35491950
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.176752331
Short name T338
Test name
Test status
Simulation time 114412503 ps
CPU time 1.33 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 219168 kb
Host smart-58da7980-f6e5-4691-a098-b190589cd934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176752331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.176752331
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1374019208
Short name T434
Test name
Test status
Simulation time 41888204 ps
CPU time 1.57 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 217888 kb
Host smart-58825e1c-889e-432c-a551-7e386eb10556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374019208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1374019208
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.1784850790
Short name T330
Test name
Test status
Simulation time 152967619 ps
CPU time 0.91 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 206192 kb
Host smart-8b0b4119-4ac2-40d8-a414-735968e81e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784850790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1784850790
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1990600887
Short name T791
Test name
Test status
Simulation time 70661032 ps
CPU time 0.83 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 207100 kb
Host smart-8a9c5682-3688-4703-aa6b-a68a4ce614a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990600887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1990600887
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1705987871
Short name T638
Test name
Test status
Simulation time 52284127 ps
CPU time 1.12 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:21 PM PDT 24
Peak memory 219216 kb
Host smart-ba4482ce-821b-4e15-90b8-27a28f7ed0eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705987871 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1705987871
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.3454555214
Short name T751
Test name
Test status
Simulation time 16820605 ps
CPU time 0.99 seconds
Started May 30 02:03:19 PM PDT 24
Finished May 30 02:03:21 PM PDT 24
Peak memory 216636 kb
Host smart-c898453b-42ea-4386-9aba-e14aa99f3672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454555214 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3454555214
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.618469455
Short name T404
Test name
Test status
Simulation time 25890940 ps
CPU time 1 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 215124 kb
Host smart-4499a260-4dc1-4928-a8c4-908e04f3a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618469455 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.618469455
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3945745959
Short name T777
Test name
Test status
Simulation time 55098413 ps
CPU time 0.94 seconds
Started May 30 02:03:14 PM PDT 24
Finished May 30 02:03:16 PM PDT 24
Peak memory 215012 kb
Host smart-10f0ab25-d6d9-4df9-a9df-efe93782f326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945745959 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3945745959
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3768458516
Short name T811
Test name
Test status
Simulation time 205167097 ps
CPU time 4.03 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 216604 kb
Host smart-0c843525-4b32-4777-a699-08e1fdaab64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768458516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3768458516
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1125998287
Short name T487
Test name
Test status
Simulation time 86675818427 ps
CPU time 539.25 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:12:15 PM PDT 24
Peak memory 223416 kb
Host smart-afb7178e-0a1c-4a58-bff1-83808bb740d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125998287 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1125998287
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1602398752
Short name T849
Test name
Test status
Simulation time 43829751 ps
CPU time 1.14 seconds
Started May 30 02:05:10 PM PDT 24
Finished May 30 02:05:12 PM PDT 24
Peak memory 219156 kb
Host smart-8af64954-3354-4a9a-9e56-1352b2639011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602398752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1602398752
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4098930401
Short name T651
Test name
Test status
Simulation time 52277175 ps
CPU time 1.9 seconds
Started May 30 02:05:11 PM PDT 24
Finished May 30 02:05:14 PM PDT 24
Peak memory 217956 kb
Host smart-1f962c4e-a811-432d-b0e4-08d8a13c0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098930401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4098930401
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3412726608
Short name T437
Test name
Test status
Simulation time 309542600 ps
CPU time 4.17 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:21 PM PDT 24
Peak memory 217028 kb
Host smart-96392901-27e6-4910-8215-012d235b48cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412726608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3412726608
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2190622870
Short name T537
Test name
Test status
Simulation time 92471870 ps
CPU time 1.43 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 218044 kb
Host smart-e8e8b7a7-d08c-410b-aecc-91eb6c3e34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190622870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2190622870
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2628197585
Short name T563
Test name
Test status
Simulation time 36566525 ps
CPU time 1.33 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 216748 kb
Host smart-d87f84a2-f58f-499d-98d1-9969395154e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628197585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2628197585
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3828229409
Short name T153
Test name
Test status
Simulation time 175467886 ps
CPU time 1.37 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 216812 kb
Host smart-7f5be210-1f72-4692-9b13-78059b411017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828229409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3828229409
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.919901784
Short name T401
Test name
Test status
Simulation time 367583432 ps
CPU time 4.57 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:21 PM PDT 24
Peak memory 219632 kb
Host smart-5e15a903-c719-43d9-a02a-2ff713e5e5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919901784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.919901784
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2762106972
Short name T662
Test name
Test status
Simulation time 50086577 ps
CPU time 1.7 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 217920 kb
Host smart-8567ce9d-c724-4582-9377-a1c12693a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762106972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2762106972
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2733740638
Short name T471
Test name
Test status
Simulation time 54034398 ps
CPU time 1.9 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 217968 kb
Host smart-a2f3d87c-4274-4960-8d73-64dc6efdaa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733740638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2733740638
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3089018114
Short name T426
Test name
Test status
Simulation time 81091688 ps
CPU time 1.09 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 216680 kb
Host smart-e5ed4aa2-4b80-4f76-8707-6a1394434b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089018114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3089018114
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.3921236799
Short name T314
Test name
Test status
Simulation time 47532126 ps
CPU time 0.9 seconds
Started May 30 02:03:17 PM PDT 24
Finished May 30 02:03:19 PM PDT 24
Peak memory 206232 kb
Host smart-3aeded4a-d752-466f-9a40-1f5c19e994f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921236799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3921236799
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2231043736
Short name T192
Test name
Test status
Simulation time 23973732 ps
CPU time 0.86 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 216308 kb
Host smart-7189ee2d-7413-462f-afa7-3286b2203d55
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231043736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2231043736
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2367388874
Short name T837
Test name
Test status
Simulation time 25861366 ps
CPU time 1.22 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:19 PM PDT 24
Peak memory 218100 kb
Host smart-775c6886-69e2-4aa7-ab87-3c3782ab02b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367388874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2367388874
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2917861186
Short name T371
Test name
Test status
Simulation time 60532515 ps
CPU time 1.1 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 219444 kb
Host smart-41360ce2-829c-405d-85a2-0b4f986a0ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917861186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2917861186
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2538516378
Short name T727
Test name
Test status
Simulation time 22902454 ps
CPU time 1.22 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 223608 kb
Host smart-4f051fba-257f-4efd-9092-022a6895813b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538516378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2538516378
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4235428135
Short name T507
Test name
Test status
Simulation time 24034393 ps
CPU time 0.91 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 206840 kb
Host smart-138296aa-5e80-4a1f-9990-f493e2374069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235428135 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4235428135
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2088976113
Short name T692
Test name
Test status
Simulation time 199519472 ps
CPU time 4.52 seconds
Started May 30 02:03:17 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 215040 kb
Host smart-ac8941a2-8a52-42f0-8544-72ca8cb611ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088976113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2088976113
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/290.edn_genbits.2590243536
Short name T501
Test name
Test status
Simulation time 52487792 ps
CPU time 1.25 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:19 PM PDT 24
Peak memory 217704 kb
Host smart-e976eea6-57c5-4f3d-9609-4d687950760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590243536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2590243536
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1518460266
Short name T514
Test name
Test status
Simulation time 237669741 ps
CPU time 3.29 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:21 PM PDT 24
Peak memory 219496 kb
Host smart-5f2d9bde-7b86-4491-9e1c-12ccf41260d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518460266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1518460266
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1975443131
Short name T346
Test name
Test status
Simulation time 55400254 ps
CPU time 1.7 seconds
Started May 30 02:05:13 PM PDT 24
Finished May 30 02:05:16 PM PDT 24
Peak memory 219384 kb
Host smart-1a2676f5-50d9-4090-a646-57d6d5b2e9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975443131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1975443131
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2836333268
Short name T322
Test name
Test status
Simulation time 316363885 ps
CPU time 1.59 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 218324 kb
Host smart-0fb40036-8a13-4d22-96a6-c22999b33e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836333268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2836333268
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.409282668
Short name T417
Test name
Test status
Simulation time 212884272 ps
CPU time 3 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:22 PM PDT 24
Peak memory 219696 kb
Host smart-932a7e03-d9d4-4df7-b844-66b81d9bcb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409282668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.409282668
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2286808303
Short name T503
Test name
Test status
Simulation time 58297826 ps
CPU time 1.3 seconds
Started May 30 02:05:15 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 216652 kb
Host smart-14154174-77d7-4c38-8555-8f5e0b86b8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286808303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2286808303
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1295685814
Short name T355
Test name
Test status
Simulation time 26503959 ps
CPU time 1.1 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 216812 kb
Host smart-76a7fbda-b403-473a-a447-28f1c2ea9768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295685814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1295685814
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3874368548
Short name T465
Test name
Test status
Simulation time 49857980 ps
CPU time 1.87 seconds
Started May 30 02:05:14 PM PDT 24
Finished May 30 02:05:18 PM PDT 24
Peak memory 216968 kb
Host smart-ad08f0fb-b5c2-4379-87ad-764fbc89602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874368548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3874368548
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2847181767
Short name T420
Test name
Test status
Simulation time 35922707 ps
CPU time 1.39 seconds
Started May 30 02:05:16 PM PDT 24
Finished May 30 02:05:20 PM PDT 24
Peak memory 219296 kb
Host smart-33f993d0-8982-4a86-8830-0650333b6126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847181767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2847181767
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.594596696
Short name T379
Test name
Test status
Simulation time 94887242 ps
CPU time 1.09 seconds
Started May 30 02:05:12 PM PDT 24
Finished May 30 02:05:15 PM PDT 24
Peak memory 217872 kb
Host smart-b6462504-de73-4dfb-ab77-3c9fb70a5b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594596696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.594596696
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1762627713
Short name T35
Test name
Test status
Simulation time 22652732 ps
CPU time 1.19 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 215404 kb
Host smart-fb98544a-00f3-484b-b72e-b40dfd8be1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762627713 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1762627713
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3341577256
Short name T309
Test name
Test status
Simulation time 14393723 ps
CPU time 0.92 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 214532 kb
Host smart-cbfb5291-7bb5-4d60-9e0b-690ce8649cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341577256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3341577256
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1703193010
Short name T350
Test name
Test status
Simulation time 43309972 ps
CPU time 0.86 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:39 PM PDT 24
Peak memory 215152 kb
Host smart-af7fca3c-a195-4a32-8204-75933a588a13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703193010 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1703193010
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3133932228
Short name T381
Test name
Test status
Simulation time 111522082 ps
CPU time 1.1 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:39 PM PDT 24
Peak memory 218116 kb
Host smart-42970482-eec2-4d08-a364-527bad7c2a1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133932228 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3133932228
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1265891158
Short name T707
Test name
Test status
Simulation time 37164657 ps
CPU time 1.25 seconds
Started May 30 02:01:35 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 215288 kb
Host smart-e9d49c75-d55b-49a3-bd17-bf0d8d6744ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265891158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1265891158
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2662720762
Short name T331
Test name
Test status
Simulation time 224589237 ps
CPU time 3.58 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:30 PM PDT 24
Peak memory 218960 kb
Host smart-2a262806-1bc5-4930-980c-c3d14a03896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662720762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2662720762
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3467985269
Short name T142
Test name
Test status
Simulation time 22597233 ps
CPU time 1.06 seconds
Started May 30 02:01:35 PM PDT 24
Finished May 30 02:01:37 PM PDT 24
Peak memory 215160 kb
Host smart-448d14cb-7abe-41da-855f-10ef9289478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467985269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3467985269
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2147736943
Short name T267
Test name
Test status
Simulation time 15031614 ps
CPU time 0.97 seconds
Started May 30 02:01:25 PM PDT 24
Finished May 30 02:01:27 PM PDT 24
Peak memory 206764 kb
Host smart-cbe4e759-95ba-42ed-9e00-0e4a799502e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147736943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2147736943
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4012162653
Short name T139
Test name
Test status
Simulation time 1141504199 ps
CPU time 4.54 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:41 PM PDT 24
Peak memory 234800 kb
Host smart-6b360ef2-7ae5-4f24-b059-92e12a6ec36f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012162653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4012162653
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1573917634
Short name T521
Test name
Test status
Simulation time 51144652 ps
CPU time 0.99 seconds
Started May 30 02:01:26 PM PDT 24
Finished May 30 02:01:28 PM PDT 24
Peak memory 215020 kb
Host smart-2fde86de-685f-40e1-b4be-0752653728db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573917634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1573917634
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2948501135
Short name T287
Test name
Test status
Simulation time 130129728 ps
CPU time 2.85 seconds
Started May 30 02:01:27 PM PDT 24
Finished May 30 02:01:30 PM PDT 24
Peak memory 216680 kb
Host smart-5b6d5d97-00ce-4600-ad6b-2a1812be02eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948501135 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2948501135
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3759717112
Short name T207
Test name
Test status
Simulation time 70536267563 ps
CPU time 807.62 seconds
Started May 30 02:01:23 PM PDT 24
Finished May 30 02:14:52 PM PDT 24
Peak memory 223480 kb
Host smart-ab89dabf-b648-46af-abc8-c2710f258626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759717112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3759717112
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1226235375
Short name T270
Test name
Test status
Simulation time 313200449 ps
CPU time 1.12 seconds
Started May 30 02:03:17 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 215332 kb
Host smart-d7d1adee-37ac-4f51-b328-0ffce806082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226235375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1226235375
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3348866337
Short name T402
Test name
Test status
Simulation time 121264940 ps
CPU time 0.96 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:22 PM PDT 24
Peak memory 214548 kb
Host smart-2daf60d8-ca65-4ab7-b4a1-a8e8fdbe2a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348866337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3348866337
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2785184638
Short name T380
Test name
Test status
Simulation time 33504660 ps
CPU time 0.79 seconds
Started May 30 02:03:19 PM PDT 24
Finished May 30 02:03:22 PM PDT 24
Peak memory 215732 kb
Host smart-324ba8a2-ebf0-4146-8c5a-9ca914c1c13d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785184638 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2785184638
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3103549430
Short name T446
Test name
Test status
Simulation time 40996686 ps
CPU time 1.43 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 216448 kb
Host smart-7d3ba263-969b-48e2-9099-425d7575b223
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103549430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3103549430
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3753869794
Short name T96
Test name
Test status
Simulation time 18514651 ps
CPU time 1.19 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 223500 kb
Host smart-bdeb0ce3-64e3-4f6f-9ff8-371fc65c3887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753869794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3753869794
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1050633521
Short name T597
Test name
Test status
Simulation time 44928032 ps
CPU time 1.59 seconds
Started May 30 02:03:15 PM PDT 24
Finished May 30 02:03:18 PM PDT 24
Peak memory 217984 kb
Host smart-05570ad5-2a88-42a6-97c4-246cffc00a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050633521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1050633521
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3932827494
Short name T341
Test name
Test status
Simulation time 20628406 ps
CPU time 1.11 seconds
Started May 30 02:03:16 PM PDT 24
Finished May 30 02:03:19 PM PDT 24
Peak memory 215332 kb
Host smart-88bff48a-4e47-4dd9-b8fe-1e560ab2178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932827494 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3932827494
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.381934606
Short name T717
Test name
Test status
Simulation time 19273025 ps
CPU time 0.99 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:20 PM PDT 24
Peak memory 206844 kb
Host smart-d1480aa1-c2b4-4426-9d1f-2905550532a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381934606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.381934606
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3121725055
Short name T296
Test name
Test status
Simulation time 275130047 ps
CPU time 4.92 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 214956 kb
Host smart-5acd0a67-f328-4f48-8665-ae385303127e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121725055 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3121725055
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3982761506
Short name T648
Test name
Test status
Simulation time 637551692820 ps
CPU time 2234.5 seconds
Started May 30 02:03:19 PM PDT 24
Finished May 30 02:40:35 PM PDT 24
Peak memory 229952 kb
Host smart-d629e830-6e74-48f6-9780-ec6db9a7488f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982761506 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3982761506
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3689387514
Short name T721
Test name
Test status
Simulation time 149731780 ps
CPU time 1.34 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 215328 kb
Host smart-d30f4814-1f17-434d-8184-6a7b701f1c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689387514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3689387514
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.914958996
Short name T495
Test name
Test status
Simulation time 40415398 ps
CPU time 1.05 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 206292 kb
Host smart-4a153734-8140-4e1b-b151-30e5f20caa3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914958996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.914958996
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2336267529
Short name T90
Test name
Test status
Simulation time 20890307 ps
CPU time 0.81 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 216100 kb
Host smart-c495130a-52b6-4d26-8fad-94bad941d579
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336267529 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2336267529
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2467518579
Short name T61
Test name
Test status
Simulation time 53531600 ps
CPU time 1.63 seconds
Started May 30 02:03:19 PM PDT 24
Finished May 30 02:03:22 PM PDT 24
Peak memory 216816 kb
Host smart-91053623-c888-4996-81b2-2eba74f65a44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467518579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2467518579
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4024709020
Short name T724
Test name
Test status
Simulation time 28999057 ps
CPU time 1.33 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 224952 kb
Host smart-287e0ca7-3f96-46e7-a71c-1fef109de056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024709020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4024709020
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.855876536
Short name T812
Test name
Test status
Simulation time 106974031 ps
CPU time 1.2 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 218052 kb
Host smart-c32c7ddd-f17f-42ec-8fb7-3fe489163e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855876536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.855876536
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2469836751
Short name T725
Test name
Test status
Simulation time 24943436 ps
CPU time 1.14 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 223736 kb
Host smart-3dee2dd7-5f2d-4a1d-a071-f20a3cfdd46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469836751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2469836751
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3888282978
Short name T383
Test name
Test status
Simulation time 70076176 ps
CPU time 0.89 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 214852 kb
Host smart-069f0685-db91-4c3c-aaba-823cd0346dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888282978 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3888282978
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1222319215
Short name T382
Test name
Test status
Simulation time 808211026 ps
CPU time 4.49 seconds
Started May 30 02:03:18 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 215040 kb
Host smart-cd263cd0-5cf8-441a-953c-4256f975bd5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222319215 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1222319215
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3479133879
Short name T206
Test name
Test status
Simulation time 27981479244 ps
CPU time 745.78 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:15:49 PM PDT 24
Peak memory 223524 kb
Host smart-bc064e22-355c-4f8e-b6c1-1f946e1d98eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479133879 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3479133879
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3544791233
Short name T805
Test name
Test status
Simulation time 49291088 ps
CPU time 1.3 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 215392 kb
Host smart-8a385d30-f4b8-4705-8e32-6d51c988fc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544791233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3544791233
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.410335677
Short name T352
Test name
Test status
Simulation time 47072267 ps
CPU time 0.99 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 214516 kb
Host smart-f394e2cb-5b3a-428d-95bb-81ff2918d125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410335677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.410335677
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2722763975
Short name T66
Test name
Test status
Simulation time 36141305 ps
CPU time 0.82 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 215244 kb
Host smart-274b6587-7290-43af-84ed-c0bb6656806a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722763975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2722763975
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3915299830
Short name T512
Test name
Test status
Simulation time 98703562 ps
CPU time 1.11 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 217956 kb
Host smart-49b69527-c1b6-4779-aa2e-9ac31bb9abf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915299830 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3915299830
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.4071027063
Short name T663
Test name
Test status
Simulation time 31606493 ps
CPU time 1.16 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 219328 kb
Host smart-0af9a1f3-b86f-4a34-b846-9dc3985b7e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071027063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.4071027063
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1714410499
Short name T741
Test name
Test status
Simulation time 344929840 ps
CPU time 1.4 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 217020 kb
Host smart-8c3f24e3-c18f-4552-805d-9e4bf54537bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714410499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1714410499
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.138343402
Short name T424
Test name
Test status
Simulation time 85287488 ps
CPU time 0.88 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 215056 kb
Host smart-02efee19-27b3-4249-94e7-843edab0fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138343402 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.138343402
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3311385765
Short name T340
Test name
Test status
Simulation time 18671799 ps
CPU time 0.99 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 214992 kb
Host smart-5f6958f7-55db-419b-9afc-d4319e73888a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311385765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3311385765
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1897280622
Short name T693
Test name
Test status
Simulation time 516244730 ps
CPU time 4.42 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 219668 kb
Host smart-dd944701-6666-4eaf-b07a-3477c182ccb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897280622 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1897280622
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1331839893
Short name T686
Test name
Test status
Simulation time 48177169230 ps
CPU time 1062.5 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:21:06 PM PDT 24
Peak memory 219708 kb
Host smart-1854eb76-c987-4740-ae1d-7157126f7b94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331839893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1331839893
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.814508957
Short name T271
Test name
Test status
Simulation time 24189881 ps
CPU time 1.18 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 215404 kb
Host smart-e61bfe8c-e460-409b-8a5a-3cbad16e6867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814508957 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.814508957
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2757976488
Short name T407
Test name
Test status
Simulation time 22613491 ps
CPU time 0.89 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 206312 kb
Host smart-92ab2ed7-2e03-403d-9762-158353e55015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757976488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2757976488
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3010067438
Short name T486
Test name
Test status
Simulation time 12123510 ps
CPU time 0.92 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 215392 kb
Host smart-ec20b923-2a5b-440a-8aa6-f3e451e6a55c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010067438 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3010067438
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.1673093316
Short name T786
Test name
Test status
Simulation time 93346683 ps
CPU time 1.11 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 219968 kb
Host smart-f03e49cd-a84a-4cee-a3b4-f2e20b3a26fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673093316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1673093316
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1578513484
Short name T835
Test name
Test status
Simulation time 353570618 ps
CPU time 1.93 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 218268 kb
Host smart-1f2629a5-0cf4-485d-9422-52a8444d0a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578513484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1578513484
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3464547430
Short name T318
Test name
Test status
Simulation time 22742109 ps
CPU time 1.1 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 215100 kb
Host smart-89a74750-6529-41f2-a75e-5fe8adc51776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464547430 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3464547430
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.823164065
Short name T802
Test name
Test status
Simulation time 35167813 ps
CPU time 1.02 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 214964 kb
Host smart-708326e7-092b-4873-b8a9-c7dd711d4c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823164065 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.823164065
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.102876660
Short name T798
Test name
Test status
Simulation time 433465467 ps
CPU time 5.24 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 215192 kb
Host smart-75617d6d-7b11-4c37-92e1-1ec1f38efe6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102876660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.102876660
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3607956832
Short name T844
Test name
Test status
Simulation time 30076766949 ps
CPU time 704.93 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:15:09 PM PDT 24
Peak memory 218428 kb
Host smart-c976346c-1b43-4983-84eb-d76934273315
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607956832 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3607956832
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.1909818481
Short name T305
Test name
Test status
Simulation time 98163130 ps
CPU time 0.88 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 206276 kb
Host smart-0125687b-07da-4ff9-a689-00f112e4f059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909818481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1909818481
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3466770099
Short name T788
Test name
Test status
Simulation time 30737208 ps
CPU time 0.84 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 216188 kb
Host smart-190c09a5-d8c0-4634-8b34-a565e9b4c391
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466770099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3466770099
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3584448182
Short name T45
Test name
Test status
Simulation time 54374850 ps
CPU time 1.36 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 216496 kb
Host smart-98e7fd02-ef50-40a8-be04-7b3e19c3cb3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584448182 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3584448182
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4003930994
Short name T605
Test name
Test status
Simulation time 23584274 ps
CPU time 1.03 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 223548 kb
Host smart-cd6281a1-ad60-4e90-b052-b6263c7c51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003930994 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4003930994
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.385924601
Short name T765
Test name
Test status
Simulation time 62319032 ps
CPU time 1.74 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 218096 kb
Host smart-d4f3c692-235d-499b-a04e-7e9ed950071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385924601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.385924601
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1641966162
Short name T746
Test name
Test status
Simulation time 27002118 ps
CPU time 1.05 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 223616 kb
Host smart-c27764a1-545b-4c23-98a2-6e0663b43901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641966162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1641966162
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3335993207
Short name T799
Test name
Test status
Simulation time 17020777 ps
CPU time 0.99 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 214964 kb
Host smart-8cf25b07-5165-4b7c-89ff-4fb7e6409a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335993207 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3335993207
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2911088587
Short name T557
Test name
Test status
Simulation time 171080484 ps
CPU time 1.61 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 216824 kb
Host smart-af335eed-025c-4839-bba2-01919afaf778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911088587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2911088587
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1763486604
Short name T694
Test name
Test status
Simulation time 98920460348 ps
CPU time 1115.54 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:22:02 PM PDT 24
Peak memory 223496 kb
Host smart-6e74656a-a89d-4344-b629-2852706961a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763486604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1763486604
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1405752252
Short name T81
Test name
Test status
Simulation time 30485805 ps
CPU time 1.26 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 215312 kb
Host smart-f17491f2-bfcf-4b49-9f2b-ccd2e6e8ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405752252 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1405752252
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3381784440
Short name T306
Test name
Test status
Simulation time 79269427 ps
CPU time 0.94 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 206320 kb
Host smart-8ced452c-26d2-40c2-9283-b2ad0dee08c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381784440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3381784440
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.422301688
Short name T745
Test name
Test status
Simulation time 10699178 ps
CPU time 0.87 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 215808 kb
Host smart-dc4d8868-2f30-4ec5-acf0-f1bc6a3f1b09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422301688 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.422301688
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1811669444
Short name T179
Test name
Test status
Simulation time 53938185 ps
CPU time 1.1 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 216592 kb
Host smart-10639658-82fe-4bd4-8dfc-238e31108f53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811669444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1811669444
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3665225928
Short name T184
Test name
Test status
Simulation time 46353296 ps
CPU time 1.03 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 219396 kb
Host smart-097b2aff-ae0e-47db-9af2-504519fb3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665225928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3665225928
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2754929303
Short name T579
Test name
Test status
Simulation time 55299078 ps
CPU time 1.52 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 216748 kb
Host smart-159cf805-9c03-452c-ada6-1e776e40297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754929303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2754929303
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2841665878
Short name T413
Test name
Test status
Simulation time 22281886 ps
CPU time 1.1 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:26 PM PDT 24
Peak memory 215008 kb
Host smart-2058556a-0ba0-4560-b868-51f2161c8b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841665878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2841665878
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3233544583
Short name T556
Test name
Test status
Simulation time 17334913 ps
CPU time 1.02 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:23 PM PDT 24
Peak memory 215020 kb
Host smart-43e98286-18cf-45bd-aa5b-6e21ae307c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233544583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3233544583
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1181709353
Short name T672
Test name
Test status
Simulation time 404034720 ps
CPU time 7.27 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 217892 kb
Host smart-88bcf81a-9a30-4371-a798-fc5ee163a7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181709353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1181709353
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.1831347351
Short name T259
Test name
Test status
Simulation time 73720388 ps
CPU time 1.25 seconds
Started May 30 02:03:20 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 215396 kb
Host smart-36a92d5f-fc61-4dd6-908b-c2f127a80bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831347351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1831347351
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1748000738
Short name T168
Test name
Test status
Simulation time 39010520 ps
CPU time 0.86 seconds
Started May 30 02:03:36 PM PDT 24
Finished May 30 02:03:38 PM PDT 24
Peak memory 206196 kb
Host smart-97fe2714-6764-40be-b046-b286d0e65671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748000738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1748000738
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4076601711
Short name T357
Test name
Test status
Simulation time 54899544 ps
CPU time 0.85 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:25 PM PDT 24
Peak memory 215712 kb
Host smart-2ca53e50-a1e1-49a0-ac09-f408c69219ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076601711 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4076601711
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4056271134
Short name T62
Test name
Test status
Simulation time 65660795 ps
CPU time 1.34 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 216640 kb
Host smart-52ca0776-0c78-4e8d-8d99-ad1161704047
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056271134 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4056271134
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.634151153
Short name T7
Test name
Test status
Simulation time 56467519 ps
CPU time 0.97 seconds
Started May 30 02:03:21 PM PDT 24
Finished May 30 02:03:24 PM PDT 24
Peak memory 218056 kb
Host smart-7e8a10c3-0ca8-4d31-933c-a472f45e63b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634151153 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.634151153
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2122311519
Short name T11
Test name
Test status
Simulation time 54610026 ps
CPU time 2.16 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 219588 kb
Host smart-38c5e2b4-b860-446d-9451-f290aed0e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122311519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2122311519
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1963478893
Short name T169
Test name
Test status
Simulation time 24458871 ps
CPU time 0.95 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 215260 kb
Host smart-b775f36b-df05-4a90-9a17-44fe2c3616ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963478893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1963478893
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3528031130
Short name T388
Test name
Test status
Simulation time 19778684 ps
CPU time 1.01 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 214980 kb
Host smart-3f1645c2-596a-4878-b8ac-f8781e5bf1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528031130 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3528031130
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3393148041
Short name T803
Test name
Test status
Simulation time 327676482 ps
CPU time 6.58 seconds
Started May 30 02:03:22 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 216620 kb
Host smart-daf256ed-1942-4e8e-b5f2-57baee41645f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393148041 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3393148041
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.455072988
Short name T483
Test name
Test status
Simulation time 42414846579 ps
CPU time 971.37 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:19:39 PM PDT 24
Peak memory 217932 kb
Host smart-502429f7-7e7c-49b2-9070-89075a975e7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455072988 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.455072988
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2096026844
Short name T261
Test name
Test status
Simulation time 33692658 ps
CPU time 1.21 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 215404 kb
Host smart-95eb8671-5092-4277-8a47-abbee960df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096026844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2096026844
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2704480436
Short name T113
Test name
Test status
Simulation time 24117791 ps
CPU time 0.78 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 206620 kb
Host smart-d76932fd-f3ce-4b30-a38d-ee4e38fa1044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704480436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2704480436
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.157962623
Short name T647
Test name
Test status
Simulation time 39195982 ps
CPU time 0.88 seconds
Started May 30 02:03:27 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 215220 kb
Host smart-7bf5f763-c886-4658-9ea1-0fff444fc94c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157962623 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.157962623
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3528761099
Short name T52
Test name
Test status
Simulation time 48991210 ps
CPU time 1.09 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 218036 kb
Host smart-715b308f-f1bf-4f84-8707-5a44d2d5c81d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528761099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3528761099
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1742445818
Short name T48
Test name
Test status
Simulation time 60672484 ps
CPU time 1.13 seconds
Started May 30 02:03:25 PM PDT 24
Finished May 30 02:03:28 PM PDT 24
Peak memory 229184 kb
Host smart-030f26db-9fc4-4434-9ab5-360ad0741b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742445818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1742445818
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2831153632
Short name T147
Test name
Test status
Simulation time 32899500 ps
CPU time 1.44 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 216872 kb
Host smart-f9f05a16-9115-4f41-a650-c8965df991c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831153632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2831153632
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1535584714
Short name T654
Test name
Test status
Simulation time 34322013 ps
CPU time 0.92 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 215076 kb
Host smart-a58b44fe-9477-4df4-922b-acad87046507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535584714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1535584714
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2875482707
Short name T569
Test name
Test status
Simulation time 16696262 ps
CPU time 1.05 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 214716 kb
Host smart-1680434a-9063-420d-b4bf-7f3273de1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875482707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2875482707
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3926901687
Short name T552
Test name
Test status
Simulation time 366648943 ps
CPU time 6.86 seconds
Started May 30 02:03:29 PM PDT 24
Finished May 30 02:03:37 PM PDT 24
Peak memory 215044 kb
Host smart-5a50efd7-57d4-4f9a-8fbc-ed85474d5338
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926901687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3926901687
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1049165898
Short name T423
Test name
Test status
Simulation time 270314983919 ps
CPU time 1522.23 seconds
Started May 30 02:03:23 PM PDT 24
Finished May 30 02:28:49 PM PDT 24
Peak memory 224500 kb
Host smart-a547ddfb-41c9-47cc-99f7-69eb8cd544e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049165898 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1049165898
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1261845504
Short name T718
Test name
Test status
Simulation time 27218938 ps
CPU time 1.26 seconds
Started May 30 02:03:27 PM PDT 24
Finished May 30 02:03:30 PM PDT 24
Peak memory 215344 kb
Host smart-a4fc3b9d-dae3-4001-af52-f1b4f469a3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261845504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1261845504
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2503119209
Short name T628
Test name
Test status
Simulation time 67379787 ps
CPU time 0.92 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 205480 kb
Host smart-34875bbd-26c7-4d91-b31b-dd3f839bbc48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503119209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2503119209
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2914058540
Short name T182
Test name
Test status
Simulation time 11911793 ps
CPU time 0.94 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 216060 kb
Host smart-c6b122c5-058c-48bc-903a-5a8629b5446b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914058540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2914058540
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.494633911
Short name T510
Test name
Test status
Simulation time 53138097 ps
CPU time 1.11 seconds
Started May 30 02:03:32 PM PDT 24
Finished May 30 02:03:35 PM PDT 24
Peak memory 216652 kb
Host smart-dc4c0889-b6e5-4d70-bca6-cf7b459c9324
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494633911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.494633911
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1359355274
Short name T551
Test name
Test status
Simulation time 24522316 ps
CPU time 1.1 seconds
Started May 30 02:03:26 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 223464 kb
Host smart-2e668f8c-cce7-453f-973a-318e6f663cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359355274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1359355274
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3671363643
Short name T832
Test name
Test status
Simulation time 136345690 ps
CPU time 1.22 seconds
Started May 30 02:03:33 PM PDT 24
Finished May 30 02:03:35 PM PDT 24
Peak memory 219284 kb
Host smart-6eba6759-2f06-4e25-ba78-3fcf1976f2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671363643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3671363643
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3056853541
Short name T353
Test name
Test status
Simulation time 40375093 ps
CPU time 0.99 seconds
Started May 30 02:03:33 PM PDT 24
Finished May 30 02:03:35 PM PDT 24
Peak memory 223432 kb
Host smart-602db124-0cc6-461e-ba92-3108117ef014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056853541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3056853541
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3106584536
Short name T313
Test name
Test status
Simulation time 17485652 ps
CPU time 0.99 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 214956 kb
Host smart-039d77d0-9ebf-43fe-9924-be789acf232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106584536 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3106584536
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2833853805
Short name T476
Test name
Test status
Simulation time 142547542 ps
CPU time 3.16 seconds
Started May 30 02:03:33 PM PDT 24
Finished May 30 02:03:37 PM PDT 24
Peak memory 215004 kb
Host smart-30c4243c-995e-4a2d-9aeb-efcd7ba3239f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833853805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2833853805
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3226166665
Short name T790
Test name
Test status
Simulation time 261486776079 ps
CPU time 386.52 seconds
Started May 30 02:03:35 PM PDT 24
Finished May 30 02:10:03 PM PDT 24
Peak memory 218508 kb
Host smart-150c0add-7cd4-4324-9d02-2af5c34899f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226166665 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3226166665
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2805812875
Short name T739
Test name
Test status
Simulation time 27970166 ps
CPU time 1.3 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 215016 kb
Host smart-4a9ef151-5a0e-4cbb-bff0-2ad10c1d4e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805812875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2805812875
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2807772331
Short name T387
Test name
Test status
Simulation time 61348057 ps
CPU time 0.89 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 206260 kb
Host smart-3c0ffd3f-d306-4043-b2ad-d6e9bf9bdf96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807772331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2807772331
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2009284049
Short name T185
Test name
Test status
Simulation time 40098460 ps
CPU time 0.88 seconds
Started May 30 02:03:27 PM PDT 24
Finished May 30 02:03:30 PM PDT 24
Peak memory 216084 kb
Host smart-d3fd096f-3860-4667-b844-45c7a4a34c1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009284049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2009284049
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1259507906
Short name T53
Test name
Test status
Simulation time 57780072 ps
CPU time 1.04 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 216580 kb
Host smart-2c7c8e13-eb4a-4523-bcfc-3a82138b85f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259507906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1259507906
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2720220794
Short name T188
Test name
Test status
Simulation time 23509947 ps
CPU time 0.89 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 217456 kb
Host smart-d49afc3e-8781-45d5-8a65-a8b0e6e125f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720220794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2720220794
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2612171856
Short name T311
Test name
Test status
Simulation time 49715165 ps
CPU time 1.28 seconds
Started May 30 02:03:28 PM PDT 24
Finished May 30 02:03:30 PM PDT 24
Peak memory 218912 kb
Host smart-c6455e7f-ab7c-4fe6-898e-adf48495cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612171856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2612171856
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1352793348
Short name T760
Test name
Test status
Simulation time 25826352 ps
CPU time 0.96 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:03:27 PM PDT 24
Peak memory 215392 kb
Host smart-5eb4460c-3394-4950-b561-7fda8e257939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352793348 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1352793348
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1562261243
Short name T627
Test name
Test status
Simulation time 40661143 ps
CPU time 0.9 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 214932 kb
Host smart-665c4f3a-9d50-4751-9dea-d0e24d5292db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562261243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1562261243
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3997372531
Short name T559
Test name
Test status
Simulation time 183902576 ps
CPU time 3.9 seconds
Started May 30 02:03:27 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 216740 kb
Host smart-1fae39df-698d-40f1-8466-bbad7e4bc5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997372531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3997372531
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.888864218
Short name T674
Test name
Test status
Simulation time 13704425659 ps
CPU time 307.42 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:08:42 PM PDT 24
Peak memory 218624 kb
Host smart-0c36c59d-46a8-482c-ba27-9ecf82c7022f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888864218 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.888864218
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3922038997
Short name T668
Test name
Test status
Simulation time 70332977 ps
CPU time 1.13 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 215420 kb
Host smart-5bfed3d8-2c05-4c54-a25e-990808d6574b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922038997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3922038997
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2288392348
Short name T580
Test name
Test status
Simulation time 27005470 ps
CPU time 0.93 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 206348 kb
Host smart-da841d76-9ad7-4d63-a7d1-f8f97745e1f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288392348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2288392348
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.64063247
Short name T603
Test name
Test status
Simulation time 121774777 ps
CPU time 1.07 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 216560 kb
Host smart-976dff2e-8985-4755-8a50-0fa7f5b68f95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64063247 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disa
ble_auto_req_mode.64063247
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1616675194
Short name T708
Test name
Test status
Simulation time 29508193 ps
CPU time 1.41 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 225104 kb
Host smart-cfe0fdb3-1371-4f34-8cb9-7f34f30fd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616675194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1616675194
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.481911569
Short name T418
Test name
Test status
Simulation time 67987345 ps
CPU time 1.38 seconds
Started May 30 02:01:37 PM PDT 24
Finished May 30 02:01:39 PM PDT 24
Peak memory 216620 kb
Host smart-46c991de-0bdf-4f8a-9633-10f1be9d3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481911569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.481911569
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3656963820
Short name T548
Test name
Test status
Simulation time 25394586 ps
CPU time 1 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 215060 kb
Host smart-de4c52d3-ddf7-4014-be48-92b0f1458501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656963820 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3656963820
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.564985406
Short name T115
Test name
Test status
Simulation time 18839467 ps
CPU time 1.02 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:38 PM PDT 24
Peak memory 206832 kb
Host smart-e7e023bb-b2fe-4049-ad70-fdc7b2ffa1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564985406 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.564985406
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2489960255
Short name T20
Test name
Test status
Simulation time 1693384665 ps
CPU time 7.78 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:01:45 PM PDT 24
Peak memory 239600 kb
Host smart-de821888-f53f-43bd-a7d0-2b065e21101d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489960255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2489960255
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.521721949
Short name T598
Test name
Test status
Simulation time 40089568 ps
CPU time 0.91 seconds
Started May 30 02:01:37 PM PDT 24
Finished May 30 02:01:39 PM PDT 24
Peak memory 215112 kb
Host smart-4bdaccd7-cc4c-45c3-9612-04299151253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521721949 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.521721949
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2058573115
Short name T457
Test name
Test status
Simulation time 367129865 ps
CPU time 6.59 seconds
Started May 30 02:01:34 PM PDT 24
Finished May 30 02:01:41 PM PDT 24
Peak memory 216648 kb
Host smart-b8110313-660e-4e64-9b90-128e18460e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058573115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2058573115
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4273791276
Short name T416
Test name
Test status
Simulation time 588647423721 ps
CPU time 1771.52 seconds
Started May 30 02:01:36 PM PDT 24
Finished May 30 02:31:09 PM PDT 24
Peak memory 232984 kb
Host smart-244b4046-4cfe-4a2c-a9ce-a9203ebe0f7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273791276 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4273791276
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.2633355941
Short name T145
Test name
Test status
Simulation time 142858059 ps
CPU time 0.97 seconds
Started May 30 02:03:29 PM PDT 24
Finished May 30 02:03:31 PM PDT 24
Peak memory 214556 kb
Host smart-4a43f1b5-2786-4abb-91fb-df3244743468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633355941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2633355941
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.254410712
Short name T98
Test name
Test status
Simulation time 76817008 ps
CPU time 0.89 seconds
Started May 30 02:03:29 PM PDT 24
Finished May 30 02:03:31 PM PDT 24
Peak memory 216080 kb
Host smart-ed37541a-8cf3-42e4-935f-910ea247b5f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254410712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.254410712
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2404805141
Short name T39
Test name
Test status
Simulation time 241679856 ps
CPU time 1.16 seconds
Started May 30 02:03:26 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 216700 kb
Host smart-2653033d-aabe-4424-baa1-8b8611af18e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404805141 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2404805141
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3573364120
Short name T89
Test name
Test status
Simulation time 30502637 ps
CPU time 1.01 seconds
Started May 30 02:03:41 PM PDT 24
Finished May 30 02:03:42 PM PDT 24
Peak memory 223320 kb
Host smart-9ef39365-b77f-4ec5-8b95-8966c32fe6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573364120 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3573364120
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.427725999
Short name T504
Test name
Test status
Simulation time 53102968 ps
CPU time 1.86 seconds
Started May 30 02:03:28 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 218100 kb
Host smart-34de1978-7c4b-41b9-ad3d-7e6a695b08b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427725999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.427725999
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3321167121
Short name T121
Test name
Test status
Simulation time 31047394 ps
CPU time 1.23 seconds
Started May 30 02:03:40 PM PDT 24
Finished May 30 02:03:41 PM PDT 24
Peak memory 216364 kb
Host smart-e4fd0194-7bd4-4803-84e7-08e327868a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321167121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3321167121
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.501237514
Short name T171
Test name
Test status
Simulation time 16040225 ps
CPU time 1.02 seconds
Started May 30 02:03:35 PM PDT 24
Finished May 30 02:03:37 PM PDT 24
Peak memory 215076 kb
Host smart-737bb1fa-9b1e-4251-88ff-b88208e9664d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501237514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.501237514
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2249819696
Short name T535
Test name
Test status
Simulation time 526212368 ps
CPU time 5.15 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:38 PM PDT 24
Peak memory 219664 kb
Host smart-8fbdabd3-5984-4c3b-955f-2e2f9f41b85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249819696 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2249819696
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3556585204
Short name T164
Test name
Test status
Simulation time 8532645963 ps
CPU time 205.11 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:06:52 PM PDT 24
Peak memory 221728 kb
Host smart-9e1aeda2-cc08-4ff4-93b1-49d5927540ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556585204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3556585204
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2985450515
Short name T748
Test name
Test status
Simulation time 26191289 ps
CPU time 1.23 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 215464 kb
Host smart-c058ef60-33c2-44a0-8c83-9fa75272b027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985450515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2985450515
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1937130448
Short name T723
Test name
Test status
Simulation time 35618012 ps
CPU time 0.93 seconds
Started May 30 02:03:44 PM PDT 24
Finished May 30 02:03:46 PM PDT 24
Peak memory 206400 kb
Host smart-1e03c2a2-b713-4c33-b9e6-f3afa4340747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937130448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1937130448
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1059662649
Short name T71
Test name
Test status
Simulation time 28637726 ps
CPU time 0.8 seconds
Started May 30 02:03:41 PM PDT 24
Finished May 30 02:03:42 PM PDT 24
Peak memory 216076 kb
Host smart-83a9de02-a775-41d5-9f17-9263b556ba92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059662649 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1059662649
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.2308367206
Short name T332
Test name
Test status
Simulation time 99155249 ps
CPU time 1.12 seconds
Started May 30 02:03:42 PM PDT 24
Finished May 30 02:03:45 PM PDT 24
Peak memory 216648 kb
Host smart-4207f40a-84c2-4b06-8495-6563b786d1bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308367206 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.2308367206
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3502593622
Short name T38
Test name
Test status
Simulation time 25400573 ps
CPU time 1.18 seconds
Started May 30 02:03:29 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 220248 kb
Host smart-a6cf1930-284c-4646-9ae3-ebdb42468b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502593622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3502593622
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2552356013
Short name T622
Test name
Test status
Simulation time 61201126 ps
CPU time 1.3 seconds
Started May 30 02:03:28 PM PDT 24
Finished May 30 02:03:31 PM PDT 24
Peak memory 217792 kb
Host smart-fe1ab481-29d3-4e3b-b4e9-ac58359397ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552356013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2552356013
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.593224083
Short name T520
Test name
Test status
Simulation time 24064352 ps
CPU time 0.94 seconds
Started May 30 02:03:26 PM PDT 24
Finished May 30 02:03:29 PM PDT 24
Peak memory 215328 kb
Host smart-b82f5d0e-7cc4-40b1-bd95-1ffb9c9bbb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593224083 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.593224083
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3742859840
Short name T374
Test name
Test status
Simulation time 48202080 ps
CPU time 0.91 seconds
Started May 30 02:03:34 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 214772 kb
Host smart-f68402bf-bfd7-40dc-98ac-33605a39b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742859840 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3742859840
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1983586295
Short name T215
Test name
Test status
Simulation time 1410120609 ps
CPU time 6.04 seconds
Started May 30 02:03:29 PM PDT 24
Finished May 30 02:03:36 PM PDT 24
Peak memory 218988 kb
Host smart-33a59135-a1cf-48cf-8f7f-ed59aff5fb83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983586295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1983586295
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.445128848
Short name T640
Test name
Test status
Simulation time 158166548447 ps
CPU time 1084.68 seconds
Started May 30 02:03:24 PM PDT 24
Finished May 30 02:21:32 PM PDT 24
Peak memory 222832 kb
Host smart-704efec2-3f97-4c72-b337-b6f15d4ef901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445128848 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.445128848
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3620377955
Short name T737
Test name
Test status
Simulation time 44202458 ps
CPU time 1.07 seconds
Started May 30 02:03:28 PM PDT 24
Finished May 30 02:03:30 PM PDT 24
Peak memory 215400 kb
Host smart-a77b8fc8-05f9-4ff0-9e04-c34c1d761572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620377955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3620377955
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1279721697
Short name T136
Test name
Test status
Simulation time 25108160 ps
CPU time 0.88 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 214548 kb
Host smart-04e0a24b-f0a5-490c-b6e6-50842faa44d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279721697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1279721697
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1252161108
Short name T705
Test name
Test status
Simulation time 146557287 ps
CPU time 1.3 seconds
Started May 30 02:03:40 PM PDT 24
Finished May 30 02:03:41 PM PDT 24
Peak memory 216772 kb
Host smart-6dbbcfd9-e47d-4462-9bdc-eab0e5ecdd8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252161108 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1252161108
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3276259884
Short name T607
Test name
Test status
Simulation time 21256611 ps
CPU time 1.08 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:34 PM PDT 24
Peak memory 223332 kb
Host smart-a8bf49ed-db89-451f-9d3b-f37555264a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276259884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3276259884
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4121057859
Short name T539
Test name
Test status
Simulation time 33779105 ps
CPU time 1.35 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 218080 kb
Host smart-08840412-a257-4144-84d4-07a7a20a24a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121057859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4121057859
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2142796605
Short name T157
Test name
Test status
Simulation time 28888431 ps
CPU time 0.9 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:33 PM PDT 24
Peak memory 215564 kb
Host smart-04536b05-7eb0-4659-b3bf-a5b5dc1a8099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142796605 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2142796605
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1345528168
Short name T699
Test name
Test status
Simulation time 16546255 ps
CPU time 1.07 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:34 PM PDT 24
Peak memory 214980 kb
Host smart-08d98751-8fe2-4c3d-9f6c-8097a99329de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345528168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1345528168
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.392817891
Short name T4
Test name
Test status
Simulation time 1000505348 ps
CPU time 5.42 seconds
Started May 30 02:03:31 PM PDT 24
Finished May 30 02:03:38 PM PDT 24
Peak memory 216532 kb
Host smart-0408b81b-3aa2-4fc2-a3f2-85450eb01613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392817891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.392817891
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3784229598
Short name T375
Test name
Test status
Simulation time 48841401162 ps
CPU time 334.4 seconds
Started May 30 02:03:36 PM PDT 24
Finished May 30 02:09:11 PM PDT 24
Peak memory 218528 kb
Host smart-0d2c1598-23d2-45a0-a43e-8569894bf071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784229598 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3784229598
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2751782292
Short name T608
Test name
Test status
Simulation time 253806865 ps
CPU time 1.38 seconds
Started May 30 02:03:47 PM PDT 24
Finished May 30 02:03:49 PM PDT 24
Peak memory 215356 kb
Host smart-8868290b-7382-4d18-9f49-a6c1c89b4495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751782292 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2751782292
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3647368109
Short name T428
Test name
Test status
Simulation time 45993557 ps
CPU time 0.85 seconds
Started May 30 02:03:42 PM PDT 24
Finished May 30 02:03:44 PM PDT 24
Peak memory 214756 kb
Host smart-36acaffa-4f22-4ad4-889c-87b286f218dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647368109 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3647368109
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4127264148
Short name T564
Test name
Test status
Simulation time 10114164 ps
CPU time 0.88 seconds
Started May 30 02:03:42 PM PDT 24
Finished May 30 02:03:44 PM PDT 24
Peak memory 216064 kb
Host smart-21f8046f-4fcc-4f2a-bf77-caa741f26caf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127264148 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4127264148
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.2164536385
Short name T54
Test name
Test status
Simulation time 53451033 ps
CPU time 1.07 seconds
Started May 30 02:03:43 PM PDT 24
Finished May 30 02:03:45 PM PDT 24
Peak memory 223420 kb
Host smart-91a20ddb-67dd-494f-bb67-cd5ab51dcb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164536385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2164536385
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2871957060
Short name T24
Test name
Test status
Simulation time 28975883 ps
CPU time 1.14 seconds
Started May 30 02:03:43 PM PDT 24
Finished May 30 02:03:46 PM PDT 24
Peak memory 216624 kb
Host smart-3f9cabcc-dc85-4a6c-9d39-a05cfc9648eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871957060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2871957060
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.800126937
Short name T575
Test name
Test status
Simulation time 31149498 ps
CPU time 0.98 seconds
Started May 30 02:03:47 PM PDT 24
Finished May 30 02:03:49 PM PDT 24
Peak memory 223548 kb
Host smart-3d50b40d-5687-453d-9095-3c15ec524f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800126937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.800126937
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2168250110
Short name T824
Test name
Test status
Simulation time 19074251 ps
CPU time 0.98 seconds
Started May 30 02:03:30 PM PDT 24
Finished May 30 02:03:32 PM PDT 24
Peak memory 215044 kb
Host smart-f1258b96-651b-4f04-b0cf-3900405dd812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168250110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2168250110
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.687555785
Short name T343
Test name
Test status
Simulation time 156968490 ps
CPU time 2.3 seconds
Started May 30 02:03:43 PM PDT 24
Finished May 30 02:03:46 PM PDT 24
Peak memory 216616 kb
Host smart-9dc7369e-d7de-487c-b491-cef0646b9084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687555785 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.687555785
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3786925872
Short name T625
Test name
Test status
Simulation time 194703371821 ps
CPU time 890.82 seconds
Started May 30 02:03:47 PM PDT 24
Finished May 30 02:18:39 PM PDT 24
Peak memory 221616 kb
Host smart-cc60b47c-68cf-4f7e-a111-2151ad832120
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786925872 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3786925872
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3566461617
Short name T415
Test name
Test status
Simulation time 76968963 ps
CPU time 1.17 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 215468 kb
Host smart-82740334-854e-4eae-822e-e7dbf3ee2a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566461617 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3566461617
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3999450476
Short name T655
Test name
Test status
Simulation time 18124545 ps
CPU time 1.01 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 205920 kb
Host smart-5912b0d5-e831-4799-be44-4c623f8cf8ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999450476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3999450476
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2096090542
Short name T173
Test name
Test status
Simulation time 38053968 ps
CPU time 0.83 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 216212 kb
Host smart-fe549057-2702-4dd1-98b2-c65b49f48393
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096090542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2096090542
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4049160903
Short name T143
Test name
Test status
Simulation time 54464903 ps
CPU time 1.11 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 218012 kb
Host smart-fc17abc1-6f3e-43dc-a21b-b72a872f42d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049160903 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4049160903
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3700176386
Short name T493
Test name
Test status
Simulation time 34008597 ps
CPU time 0.84 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 217780 kb
Host smart-e75fbaf6-f20d-451b-a1e9-9571b83c66d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700176386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3700176386
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2526192044
Short name T149
Test name
Test status
Simulation time 47273524 ps
CPU time 1.64 seconds
Started May 30 02:03:43 PM PDT 24
Finished May 30 02:03:45 PM PDT 24
Peak memory 219232 kb
Host smart-f14d5ef7-b574-4810-a02d-5d37532cb75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526192044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2526192044
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2830066867
Short name T679
Test name
Test status
Simulation time 21053452 ps
CPU time 1.09 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 215060 kb
Host smart-ea80fe15-4978-4084-9e1a-5966a8ce031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830066867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2830066867
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3919946580
Short name T370
Test name
Test status
Simulation time 50057110 ps
CPU time 0.89 seconds
Started May 30 02:03:42 PM PDT 24
Finished May 30 02:03:44 PM PDT 24
Peak memory 215096 kb
Host smart-2cc1c2ca-9b69-4320-ba73-8563609d9ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919946580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3919946580
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1221762140
Short name T419
Test name
Test status
Simulation time 586283792 ps
CPU time 6.28 seconds
Started May 30 02:03:53 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 216620 kb
Host smart-836559b2-18a3-454b-a2f5-c21bb25bc742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221762140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1221762140
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.862650369
Short name T210
Test name
Test status
Simulation time 51427467365 ps
CPU time 1155.99 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:23:14 PM PDT 24
Peak memory 218816 kb
Host smart-ef955b70-5418-4bb1-bf34-a65f04666072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862650369 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.862650369
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1137787230
Short name T774
Test name
Test status
Simulation time 259257767 ps
CPU time 1.49 seconds
Started May 30 02:04:00 PM PDT 24
Finished May 30 02:04:02 PM PDT 24
Peak memory 215468 kb
Host smart-9534f804-1cf4-4d80-a9bc-f03c5713e3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137787230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1137787230
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1708680827
Short name T836
Test name
Test status
Simulation time 14406233 ps
CPU time 0.9 seconds
Started May 30 02:03:54 PM PDT 24
Finished May 30 02:03:56 PM PDT 24
Peak memory 206280 kb
Host smart-b09d5707-f81f-4dec-90c6-bbbf495bf7b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708680827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1708680827
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.588892607
Short name T23
Test name
Test status
Simulation time 32040806 ps
CPU time 1.17 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 219020 kb
Host smart-45ce9ba8-373e-4b13-9aad-ea8d030ab87f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588892607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.588892607
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.643037422
Short name T140
Test name
Test status
Simulation time 23867385 ps
CPU time 0.95 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 218384 kb
Host smart-91f67f3a-4c5d-49d8-9509-6c472d8e1ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643037422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.643037422
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.4291012949
Short name T778
Test name
Test status
Simulation time 115245427 ps
CPU time 1.24 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:01 PM PDT 24
Peak memory 219312 kb
Host smart-44ed6fce-a08a-4949-bd00-489d948c09d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291012949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.4291012949
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.2618321666
Short name T541
Test name
Test status
Simulation time 37024653 ps
CPU time 0.86 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:58 PM PDT 24
Peak memory 214968 kb
Host smart-e054c033-4fa2-48d8-9a61-495e150b9ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618321666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2618321666
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2125882778
Short name T509
Test name
Test status
Simulation time 23805452 ps
CPU time 1.11 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 215064 kb
Host smart-700dc8d9-f1c0-4e33-9ebd-bb7e6c251672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125882778 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2125882778
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.67742940
Short name T365
Test name
Test status
Simulation time 864816825 ps
CPU time 4.9 seconds
Started May 30 02:03:59 PM PDT 24
Finished May 30 02:04:05 PM PDT 24
Peak memory 216864 kb
Host smart-221b026b-8c6e-4a57-80fa-de27d5ceec58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67742940 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.67742940
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2656374557
Short name T637
Test name
Test status
Simulation time 56902055797 ps
CPU time 591.94 seconds
Started May 30 02:03:55 PM PDT 24
Finished May 30 02:13:47 PM PDT 24
Peak memory 218128 kb
Host smart-85659e0f-f602-44d5-8667-e2f6c5951aff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656374557 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2656374557
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1825410259
Short name T411
Test name
Test status
Simulation time 23876606 ps
CPU time 1.2 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 215416 kb
Host smart-9bab199b-80fc-4819-9649-8b536620dae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825410259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1825410259
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3431742641
Short name T473
Test name
Test status
Simulation time 18955067 ps
CPU time 0.97 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 206328 kb
Host smart-c228b7c3-3ac5-4c6d-8eb7-a6e0ffe2e020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431742641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3431742641
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1597167607
Short name T450
Test name
Test status
Simulation time 16206455 ps
CPU time 0.84 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 214868 kb
Host smart-37cc1716-9cfc-4a46-9347-b8c1a078204a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597167607 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1597167607
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2320056435
Short name T701
Test name
Test status
Simulation time 31105661 ps
CPU time 1.35 seconds
Started May 30 02:03:56 PM PDT 24
Finished May 30 02:03:59 PM PDT 24
Peak memory 219116 kb
Host smart-abc1f72b-9036-4545-835a-3a665038b524
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320056435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2320056435
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.1858181798
Short name T43
Test name
Test status
Simulation time 86493226 ps
CPU time 0.99 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 220136 kb
Host smart-f33739e1-3403-4bc5-91bb-0927bfcce343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858181798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1858181798
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1340931552
Short name T594
Test name
Test status
Simulation time 41124957 ps
CPU time 1.55 seconds
Started May 30 02:03:59 PM PDT 24
Finished May 30 02:04:01 PM PDT 24
Peak memory 217996 kb
Host smart-fc6f9cbd-fed0-408d-b0e6-d2256bb14372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340931552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1340931552
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.854586550
Short name T606
Test name
Test status
Simulation time 22205441 ps
CPU time 1.1 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 215124 kb
Host smart-2d506f9a-eee8-422c-b2fc-386bb425d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854586550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.854586550
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2090461661
Short name T634
Test name
Test status
Simulation time 40959511 ps
CPU time 0.93 seconds
Started May 30 02:03:55 PM PDT 24
Finished May 30 02:03:57 PM PDT 24
Peak memory 214996 kb
Host smart-2b7393cc-d4f1-4f1b-b8f6-22c460ddd797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090461661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2090461661
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2339070266
Short name T562
Test name
Test status
Simulation time 254074725 ps
CPU time 5.01 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:04 PM PDT 24
Peak memory 216636 kb
Host smart-ea204f21-64c2-4d2a-bc7b-a60f9817e881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339070266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2339070266
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1365672353
Short name T511
Test name
Test status
Simulation time 47940744800 ps
CPU time 1123.67 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:22:42 PM PDT 24
Peak memory 218356 kb
Host smart-d2d27d35-a3a0-47de-90e5-1fdc2781ea55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365672353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1365672353
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3579694824
Short name T165
Test name
Test status
Simulation time 26765654 ps
CPU time 1.21 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:01 PM PDT 24
Peak memory 215396 kb
Host smart-b0a4bebe-f55a-4ba6-b1f0-b695a8fefe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579694824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3579694824
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2165978860
Short name T809
Test name
Test status
Simulation time 31461078 ps
CPU time 0.98 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 206308 kb
Host smart-2429069e-da78-45a8-b438-fca270053adf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165978860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2165978860
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.691352869
Short name T586
Test name
Test status
Simulation time 13126933 ps
CPU time 0.9 seconds
Started May 30 02:03:56 PM PDT 24
Finished May 30 02:03:58 PM PDT 24
Peak memory 215252 kb
Host smart-a1f5489e-6c61-4432-8448-440701fa8721
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691352869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.691352869
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.4206908591
Short name T806
Test name
Test status
Simulation time 34017603 ps
CPU time 1.13 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 218068 kb
Host smart-b4211260-fb45-4c77-9a48-d54c599024d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206908591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.4206908591
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3700748942
Short name T189
Test name
Test status
Simulation time 22474428 ps
CPU time 0.97 seconds
Started May 30 02:03:55 PM PDT 24
Finished May 30 02:03:57 PM PDT 24
Peak memory 218228 kb
Host smart-5e06630e-fc57-4516-95e7-4b348a16396b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700748942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3700748942
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1902700976
Short name T291
Test name
Test status
Simulation time 30285669 ps
CPU time 1.24 seconds
Started May 30 02:03:54 PM PDT 24
Finished May 30 02:03:56 PM PDT 24
Peak memory 216704 kb
Host smart-f023889e-1be8-41c3-8b27-36301dd6c48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902700976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1902700976
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1976653381
Short name T534
Test name
Test status
Simulation time 28330816 ps
CPU time 0.89 seconds
Started May 30 02:03:54 PM PDT 24
Finished May 30 02:03:56 PM PDT 24
Peak memory 215256 kb
Host smart-3a54a322-1140-43f3-9bd8-092d15c37ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976653381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1976653381
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.713514674
Short name T620
Test name
Test status
Simulation time 27734211 ps
CPU time 0.95 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 215040 kb
Host smart-06161dc8-4771-42f5-a156-0015a86a17fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713514674 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.713514674
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3660344951
Short name T779
Test name
Test status
Simulation time 382457726 ps
CPU time 3.62 seconds
Started May 30 02:03:56 PM PDT 24
Finished May 30 02:04:00 PM PDT 24
Peak memory 216576 kb
Host smart-b660b310-de29-4e6d-9899-ac8935f729e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660344951 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3660344951
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3773326344
Short name T785
Test name
Test status
Simulation time 139251974569 ps
CPU time 1412.43 seconds
Started May 30 02:03:57 PM PDT 24
Finished May 30 02:27:30 PM PDT 24
Peak memory 222252 kb
Host smart-0b28fd06-3932-43ba-b3a6-e062af381ac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773326344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3773326344
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3521598951
Short name T807
Test name
Test status
Simulation time 48761963 ps
CPU time 1.23 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 215384 kb
Host smart-b79e68c1-33a5-49b8-a447-6df0d4d016ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521598951 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3521598951
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3539603541
Short name T310
Test name
Test status
Simulation time 44656245 ps
CPU time 0.84 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 214480 kb
Host smart-3b589833-ff9f-4468-be8b-b884056f550f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539603541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3539603541
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3357124844
Short name T72
Test name
Test status
Simulation time 21648348 ps
CPU time 0.86 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 216076 kb
Host smart-4933be77-166e-4918-876d-3b70abd562c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357124844 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3357124844
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3517611915
Short name T203
Test name
Test status
Simulation time 47485565 ps
CPU time 0.94 seconds
Started May 30 02:04:22 PM PDT 24
Finished May 30 02:04:24 PM PDT 24
Peak memory 219152 kb
Host smart-810aab71-f06d-4f8c-b393-3e0dc1136d7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517611915 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3517611915
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.2352210334
Short name T335
Test name
Test status
Simulation time 42201892 ps
CPU time 1.23 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 216744 kb
Host smart-2c64b2cb-d980-4358-8c7e-092a1a850cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352210334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2352210334
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2671072150
Short name T764
Test name
Test status
Simulation time 23789781 ps
CPU time 1.06 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 223364 kb
Host smart-e16e00e9-bf7d-42e0-b53c-eb5fb2b4b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671072150 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2671072150
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.864842267
Short name T454
Test name
Test status
Simulation time 28467552 ps
CPU time 1.01 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 215016 kb
Host smart-3896ef7a-8e74-4775-8996-1c3860da566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864842267 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.864842267
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4000900969
Short name T596
Test name
Test status
Simulation time 255521021 ps
CPU time 3.13 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 216704 kb
Host smart-1bac0082-e0e1-436f-850d-cf450aaad284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000900969 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4000900969
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3776364559
Short name T546
Test name
Test status
Simulation time 10171678710 ps
CPU time 115.92 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:06:24 PM PDT 24
Peak memory 221180 kb
Host smart-1ae7fe8b-b27f-4632-abc7-9cfc441bd856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776364559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3776364559
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.319192517
Short name T260
Test name
Test status
Simulation time 94005485 ps
CPU time 1.3 seconds
Started May 30 02:04:20 PM PDT 24
Finished May 30 02:04:22 PM PDT 24
Peak memory 215416 kb
Host smart-e8e31d59-e564-4a5e-92a1-5b0c499ae695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319192517 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.319192517
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1254041709
Short name T766
Test name
Test status
Simulation time 63802252 ps
CPU time 0.88 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 214480 kb
Host smart-e1dcf6a8-a48d-4fc5-ab7e-b8ff80da9b76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254041709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1254041709
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2980235184
Short name T712
Test name
Test status
Simulation time 11602916 ps
CPU time 0.87 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 215260 kb
Host smart-1af54bd0-605f-4a31-b78e-cbb074b8ac1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980235184 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2980235184
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.283392902
Short name T51
Test name
Test status
Simulation time 27877871 ps
CPU time 1.13 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 218228 kb
Host smart-22fa262f-fef0-4210-b2d8-e40a6161dd03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283392902 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.283392902
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1623715161
Short name T8
Test name
Test status
Simulation time 27370904 ps
CPU time 1.29 seconds
Started May 30 02:04:22 PM PDT 24
Finished May 30 02:04:24 PM PDT 24
Peak memory 220340 kb
Host smart-5b70ba7c-9c76-4e8c-a5ca-b6881f1be515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623715161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1623715161
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3451956305
Short name T531
Test name
Test status
Simulation time 51070710 ps
CPU time 1.69 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216768 kb
Host smart-f9af5c61-2ada-4894-9308-d087b204b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451956305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3451956305
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.233153018
Short name T319
Test name
Test status
Simulation time 37678948 ps
CPU time 0.98 seconds
Started May 30 02:04:20 PM PDT 24
Finished May 30 02:04:21 PM PDT 24
Peak memory 223392 kb
Host smart-911b29b7-a5b0-4f65-94da-bf6650e946ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233153018 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.233153018
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2916140983
Short name T584
Test name
Test status
Simulation time 16961697 ps
CPU time 1.01 seconds
Started May 30 02:04:19 PM PDT 24
Finished May 30 02:04:21 PM PDT 24
Peak memory 215020 kb
Host smart-165103dd-58c1-46f3-a8ce-c841e55f4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916140983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2916140983
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.922586266
Short name T213
Test name
Test status
Simulation time 104920790 ps
CPU time 1.6 seconds
Started May 30 02:04:22 PM PDT 24
Finished May 30 02:04:24 PM PDT 24
Peak memory 214956 kb
Host smart-2d62cc3f-a198-4d83-ae4d-06e72a3cae51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922586266 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.922586266
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2607370460
Short name T125
Test name
Test status
Simulation time 1604786632555 ps
CPU time 1973.9 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:37:20 PM PDT 24
Peak memory 225084 kb
Host smart-1607bf87-ac46-4849-9729-d6ca72cf1eb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607370460 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2607370460
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3077615417
Short name T455
Test name
Test status
Simulation time 44368876 ps
CPU time 1.14 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:47 PM PDT 24
Peak memory 215388 kb
Host smart-252a112a-9042-46d7-a33b-f227ed3a88a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077615417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3077615417
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1735217146
Short name T753
Test name
Test status
Simulation time 27274076 ps
CPU time 0.92 seconds
Started May 30 02:01:49 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 214292 kb
Host smart-658a7979-8cd0-441b-a083-a743cd84225c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735217146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1735217146
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3483679566
Short name T106
Test name
Test status
Simulation time 22559814 ps
CPU time 0.89 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:48 PM PDT 24
Peak memory 215708 kb
Host smart-67120e98-925b-4cd6-927c-0bdbf594a05c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483679566 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3483679566
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.68864726
Short name T183
Test name
Test status
Simulation time 56473825 ps
CPU time 1.54 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 216568 kb
Host smart-6354de5a-79dc-49e3-ac8e-0a7a939996f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68864726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disa
ble_auto_req_mode.68864726
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3569450088
Short name T624
Test name
Test status
Simulation time 67215913 ps
CPU time 0.9 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 217916 kb
Host smart-25d2865d-d223-43ae-8aff-2c89a5d473a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569450088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3569450088
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.381406190
Short name T295
Test name
Test status
Simulation time 29532480 ps
CPU time 1.41 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 219484 kb
Host smart-8ea30af7-fd5f-40d8-958c-91e214e0dc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381406190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.381406190
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3481318945
Short name T339
Test name
Test status
Simulation time 52958756 ps
CPU time 0.84 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 215188 kb
Host smart-27b10e1d-98fa-4937-9aa4-550eac183856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481318945 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3481318945
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.3822877148
Short name T347
Test name
Test status
Simulation time 30366808 ps
CPU time 0.97 seconds
Started May 30 02:01:38 PM PDT 24
Finished May 30 02:01:40 PM PDT 24
Peak memory 215028 kb
Host smart-6b3a9b12-be45-4c4a-9fb0-6bc0176903cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822877148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3822877148
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.407704526
Short name T214
Test name
Test status
Simulation time 251851235 ps
CPU time 2.59 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 216484 kb
Host smart-fe360cac-5d81-4aa6-a341-242d41420735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407704526 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.407704526
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.982529179
Short name T211
Test name
Test status
Simulation time 80411580393 ps
CPU time 1770.25 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:31:19 PM PDT 24
Peak memory 224144 kb
Host smart-f4ac97af-bb91-440a-8776-1e6ae8772d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982529179 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.982529179
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3948575034
Short name T611
Test name
Test status
Simulation time 111759154 ps
CPU time 1.01 seconds
Started May 30 02:04:22 PM PDT 24
Finished May 30 02:04:24 PM PDT 24
Peak memory 220612 kb
Host smart-6ae52e88-a2d0-434b-b154-8c100a72743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948575034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3948575034
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1536587619
Short name T396
Test name
Test status
Simulation time 309063282 ps
CPU time 1.04 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 216644 kb
Host smart-0536e8e2-5cd4-48ce-8e75-2522042f2441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536587619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1536587619
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1333361903
Short name T137
Test name
Test status
Simulation time 31060859 ps
CPU time 0.99 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 232104 kb
Host smart-25b8a657-af7d-4f61-a2d1-89de5e894cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333361903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1333361903
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4266369043
Short name T795
Test name
Test status
Simulation time 66889326 ps
CPU time 1.19 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 216712 kb
Host smart-565fc8f2-1342-4128-b5de-9e0a1a6a7338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266369043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4266369043
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1317958001
Short name T405
Test name
Test status
Simulation time 26388679 ps
CPU time 0.9 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 217700 kb
Host smart-000bca43-2b8c-4bad-92d1-076f5e0d7043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317958001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1317958001
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2366090145
Short name T422
Test name
Test status
Simulation time 140660601 ps
CPU time 1.55 seconds
Started May 30 02:03:58 PM PDT 24
Finished May 30 02:04:01 PM PDT 24
Peak memory 217868 kb
Host smart-03ef7b5e-2849-4a69-b75b-0dbe1dc310db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366090145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2366090145
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1798900904
Short name T525
Test name
Test status
Simulation time 18822189 ps
CPU time 1.03 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 217692 kb
Host smart-921fbae9-92d5-42a9-a559-a353000c67b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798900904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1798900904
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1662699528
Short name T536
Test name
Test status
Simulation time 111147681 ps
CPU time 1.06 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 216748 kb
Host smart-92d5321c-c920-4823-8e48-aceddbcfe239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662699528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1662699528
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3602288028
Short name T484
Test name
Test status
Simulation time 22970950 ps
CPU time 1.12 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 223388 kb
Host smart-fc66d24c-a9e2-4e4f-8755-9da628b2d961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602288028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3602288028
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.930617735
Short name T130
Test name
Test status
Simulation time 8722230403 ps
CPU time 118.15 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:06:22 PM PDT 24
Peak memory 216996 kb
Host smart-9b2a21cc-89b3-4bd7-b876-33de4c298dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930617735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.930617735
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2992801646
Short name T782
Test name
Test status
Simulation time 195761549 ps
CPU time 1.04 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 219280 kb
Host smart-160a5727-7ed5-4fa2-91a1-c1d4c882edc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992801646 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2992801646
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2632506133
Short name T324
Test name
Test status
Simulation time 62827101 ps
CPU time 1.05 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 219384 kb
Host smart-01caf222-07fe-462b-8433-0d2c57d70303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632506133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2632506133
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3501921585
Short name T722
Test name
Test status
Simulation time 91835896 ps
CPU time 1.19 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 219132 kb
Host smart-e13d254b-655f-4f85-9b5d-5c4ba88d08ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501921585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3501921585
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1864498483
Short name T368
Test name
Test status
Simulation time 55824261 ps
CPU time 1.06 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 216908 kb
Host smart-0769109d-c36d-43ec-a9e1-57357187d6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864498483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1864498483
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.857302093
Short name T696
Test name
Test status
Simulation time 48252048 ps
CPU time 1.06 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 223516 kb
Host smart-c816f261-b70a-4381-818f-f39d1c3d77d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857302093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.857302093
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3975197481
Short name T3
Test name
Test status
Simulation time 68411523 ps
CPU time 1.42 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 218172 kb
Host smart-00b2f956-a237-49cb-9a28-8b8bb4748e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975197481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3975197481
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2106676798
Short name T669
Test name
Test status
Simulation time 66748489 ps
CPU time 1.01 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 219316 kb
Host smart-83889dda-648e-4fe3-b771-50cf27bf3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106676798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2106676798
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3835308960
Short name T363
Test name
Test status
Simulation time 58618630 ps
CPU time 1.03 seconds
Started May 30 02:04:22 PM PDT 24
Finished May 30 02:04:24 PM PDT 24
Peak memory 216656 kb
Host smart-ef0d8e8e-074f-4426-b8fb-bf111ca536f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835308960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3835308960
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1477342406
Short name T846
Test name
Test status
Simulation time 19192766 ps
CPU time 1.05 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 218316 kb
Host smart-536b1d14-c142-4794-a46c-a36c2b4523fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477342406 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1477342406
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2724129949
Short name T286
Test name
Test status
Simulation time 55939332 ps
CPU time 1.29 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:23 PM PDT 24
Peak memory 216776 kb
Host smart-41a78116-ea3a-49fa-9988-f074dcd25693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724129949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2724129949
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3054729337
Short name T275
Test name
Test status
Simulation time 41620433 ps
CPU time 1.13 seconds
Started May 30 02:01:52 PM PDT 24
Finished May 30 02:01:53 PM PDT 24
Peak memory 215364 kb
Host smart-ea3ff940-88e5-4672-9b1d-d00d8f1bead3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054729337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3054729337
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2647539994
Short name T410
Test name
Test status
Simulation time 53150478 ps
CPU time 0.8 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 206580 kb
Host smart-aa0783c1-87ae-4142-a0ff-e027426668a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647539994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2647539994
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.897415595
Short name T529
Test name
Test status
Simulation time 12703745 ps
CPU time 0.91 seconds
Started May 30 02:01:49 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 216212 kb
Host smart-a71823db-a0e2-48df-8670-d9146134c710
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897415595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.897415595
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1302659699
Short name T40
Test name
Test status
Simulation time 40063128 ps
CPU time 1.36 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 216596 kb
Host smart-2a7be60e-2b0d-409f-9fb8-a1165de276c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302659699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1302659699
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1140793217
Short name T181
Test name
Test status
Simulation time 138819273 ps
CPU time 1.13 seconds
Started May 30 02:01:49 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 218884 kb
Host smart-ff33266a-884f-4ea5-a436-e428f56bd712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140793217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1140793217
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2104777529
Short name T144
Test name
Test status
Simulation time 37535453 ps
CPU time 1.41 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:51 PM PDT 24
Peak memory 216832 kb
Host smart-91e7bc9e-0eec-4748-802a-0a7e4f6ea754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104777529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2104777529
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3186381225
Short name T344
Test name
Test status
Simulation time 45197325 ps
CPU time 0.88 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:48 PM PDT 24
Peak memory 214888 kb
Host smart-fb52c38d-f272-45e3-8d50-8d77247e9b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186381225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3186381225
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3990156245
Short name T268
Test name
Test status
Simulation time 27768568 ps
CPU time 0.94 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 206756 kb
Host smart-ee9ccd64-7d04-4b75-b811-9be15996d2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990156245 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3990156245
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2170122367
Short name T444
Test name
Test status
Simulation time 27678518 ps
CPU time 0.97 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 215028 kb
Host smart-5aaa5dbf-b089-4fce-9bec-4d5854aeb893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170122367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2170122367
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.783885960
Short name T500
Test name
Test status
Simulation time 726106594 ps
CPU time 6.82 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:55 PM PDT 24
Peak memory 216828 kb
Host smart-79b424a8-e697-4f0b-a161-ea42eee22805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783885960 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.783885960
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1611929847
Short name T146
Test name
Test status
Simulation time 68163805371 ps
CPU time 772.47 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:14:39 PM PDT 24
Peak memory 218832 kb
Host smart-9cf85487-b948-4645-b3d8-c1b781150499
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611929847 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1611929847
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2770973932
Short name T532
Test name
Test status
Simulation time 18429465 ps
CPU time 1.16 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 223420 kb
Host smart-710077db-228e-4511-93f5-03b3f29ec4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770973932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2770973932
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.642076151
Short name T678
Test name
Test status
Simulation time 46774503 ps
CPU time 1.55 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 218116 kb
Host smart-7dd8b5a4-d160-4076-8b8a-977d5cf71cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642076151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.642076151
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3144335637
Short name T629
Test name
Test status
Simulation time 23770775 ps
CPU time 1.22 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 218016 kb
Host smart-f2bca3ee-6a04-4fcf-9138-f06d1599d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144335637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3144335637
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1459570344
Short name T336
Test name
Test status
Simulation time 57602138 ps
CPU time 0.95 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 216780 kb
Host smart-7237b4d7-b016-4351-9026-a67d22f7c9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459570344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1459570344
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1068968822
Short name T37
Test name
Test status
Simulation time 127770654 ps
CPU time 0.99 seconds
Started May 30 02:04:21 PM PDT 24
Finished May 30 02:04:22 PM PDT 24
Peak memory 219240 kb
Host smart-ca266216-c45b-4738-97c3-cc950d54fcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068968822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1068968822
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2765888765
Short name T592
Test name
Test status
Simulation time 48726544 ps
CPU time 1.3 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 219432 kb
Host smart-dd930b4e-b1f4-4ad0-a4f5-cc13a98a13cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765888765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2765888765
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.123504271
Short name T33
Test name
Test status
Simulation time 27855400 ps
CPU time 1.34 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 229328 kb
Host smart-fe67e19a-f989-4113-98b2-2d6148183fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123504271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.123504271
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.592336802
Short name T772
Test name
Test status
Simulation time 56685545 ps
CPU time 1.34 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 216676 kb
Host smart-62a17550-9cb5-46ca-946d-b0be79c65bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592336802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.592336802
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3674576102
Short name T27
Test name
Test status
Simulation time 68606415 ps
CPU time 0.9 seconds
Started May 30 02:04:20 PM PDT 24
Finished May 30 02:04:22 PM PDT 24
Peak memory 223336 kb
Host smart-55833326-099b-4487-b0d9-1280015272d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674576102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3674576102
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2507475931
Short name T49
Test name
Test status
Simulation time 52633419 ps
CPU time 1.36 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 219436 kb
Host smart-2ce9a3c3-39fa-4a14-be92-7332fcc246fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507475931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2507475931
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3911742207
Short name T79
Test name
Test status
Simulation time 20741727 ps
CPU time 1.01 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 218056 kb
Host smart-c51b0e12-2c67-4a97-9f96-7e02ca6853a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911742207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3911742207
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3737364787
Short name T329
Test name
Test status
Simulation time 38316936 ps
CPU time 1.34 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 217856 kb
Host smart-4899232d-ee93-4525-87b2-11599cab6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737364787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3737364787
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.627542727
Short name T77
Test name
Test status
Simulation time 78468125 ps
CPU time 1.15 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 225196 kb
Host smart-279aa52a-2c54-4768-9102-298b7d1eaab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627542727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.627542727
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3933102984
Short name T469
Test name
Test status
Simulation time 127303404 ps
CPU time 2.63 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:29 PM PDT 24
Peak memory 219596 kb
Host smart-3205c288-b7fa-452a-abf4-6265aac1e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933102984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3933102984
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.661607273
Short name T50
Test name
Test status
Simulation time 25534615 ps
CPU time 1.17 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:25 PM PDT 24
Peak memory 220004 kb
Host smart-8b54ae2c-4bfe-4d32-98e2-29bb09124fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661607273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.661607273
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1083983631
Short name T757
Test name
Test status
Simulation time 183894208 ps
CPU time 2.33 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216852 kb
Host smart-d4b0a01f-f2a3-4a70-9d55-411645dd5999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083983631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1083983631
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3216392154
Short name T616
Test name
Test status
Simulation time 21322159 ps
CPU time 0.98 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 223432 kb
Host smart-83945459-9151-400a-8bee-be66fe5d8d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216392154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3216392154
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1341581019
Short name T830
Test name
Test status
Simulation time 33297607 ps
CPU time 1.43 seconds
Started May 30 02:04:23 PM PDT 24
Finished May 30 02:04:26 PM PDT 24
Peak memory 218144 kb
Host smart-7044735c-b2b9-4734-a84f-a08c4642b65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341581019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1341581019
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.305236228
Short name T42
Test name
Test status
Simulation time 62348179 ps
CPU time 1.01 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 216992 kb
Host smart-408a49ea-ffc3-4d45-80a8-12c590da1ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305236228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.305236228
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.588471082
Short name T845
Test name
Test status
Simulation time 32832664 ps
CPU time 1.31 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 216728 kb
Host smart-e5f7982f-52e5-4d37-bd5f-9472e3d80853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588471082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.588471082
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1103926343
Short name T274
Test name
Test status
Simulation time 44899947 ps
CPU time 1.24 seconds
Started May 30 02:01:52 PM PDT 24
Finished May 30 02:01:54 PM PDT 24
Peak memory 215360 kb
Host smart-b01ee2fa-3195-49bb-863e-2bb5a8cedfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103926343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1103926343
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2824146097
Short name T398
Test name
Test status
Simulation time 22200080 ps
CPU time 1.02 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 206348 kb
Host smart-f452ff2b-6f37-444d-8801-3f01c0b6b4d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824146097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2824146097
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1119050021
Short name T585
Test name
Test status
Simulation time 17108027 ps
CPU time 0.95 seconds
Started May 30 02:01:52 PM PDT 24
Finished May 30 02:01:54 PM PDT 24
Peak memory 215288 kb
Host smart-7ea356f4-f579-43f2-a12c-e82dbc868c82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119050021 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1119050021
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.421915061
Short name T172
Test name
Test status
Simulation time 137688758 ps
CPU time 1.05 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:01:48 PM PDT 24
Peak memory 219224 kb
Host smart-b1b5d7ee-cb3f-4414-8f1b-5582d0a09d39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421915061 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.421915061
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_intr.2396035987
Short name T840
Test name
Test status
Simulation time 29542054 ps
CPU time 1.09 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 223612 kb
Host smart-cb13c8af-682b-4a3d-b86f-7114919364f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396035987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2396035987
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.488161188
Short name T114
Test name
Test status
Simulation time 112277679 ps
CPU time 0.94 seconds
Started May 30 02:01:47 PM PDT 24
Finished May 30 02:01:49 PM PDT 24
Peak memory 206816 kb
Host smart-cc251974-a90a-4c6d-a5ad-519e6aeb24a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488161188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.488161188
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.473804190
Short name T337
Test name
Test status
Simulation time 131847210 ps
CPU time 0.92 seconds
Started May 30 02:01:50 PM PDT 24
Finished May 30 02:01:52 PM PDT 24
Peak memory 215024 kb
Host smart-a4246b0e-13af-4acd-9b62-f0f9c7421643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473804190 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.473804190
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4002578509
Short name T848
Test name
Test status
Simulation time 56948983 ps
CPU time 1.07 seconds
Started May 30 02:01:48 PM PDT 24
Finished May 30 02:01:50 PM PDT 24
Peak memory 206168 kb
Host smart-9926bc07-2579-443f-bb33-86670337b199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002578509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4002578509
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3524819644
Short name T726
Test name
Test status
Simulation time 20831068055 ps
CPU time 348.24 seconds
Started May 30 02:01:46 PM PDT 24
Finished May 30 02:07:36 PM PDT 24
Peak memory 217960 kb
Host smart-508be926-c829-4046-a371-639ff56a13e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524819644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3524819644
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.23396057
Short name T57
Test name
Test status
Simulation time 60574767 ps
CPU time 1.07 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 220196 kb
Host smart-39751ed1-c5c9-42bf-9893-31c5e40fa004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23396057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.23396057
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2805848836
Short name T277
Test name
Test status
Simulation time 65944445 ps
CPU time 1.55 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 218124 kb
Host smart-2762e533-25b6-47e8-a0be-4a659791d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805848836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2805848836
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3641898801
Short name T659
Test name
Test status
Simulation time 24979491 ps
CPU time 0.94 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:29 PM PDT 24
Peak memory 218268 kb
Host smart-cf679141-4f3a-4d63-bb07-fa767d20494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641898801 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3641898801
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2065484930
Short name T342
Test name
Test status
Simulation time 33302916 ps
CPU time 1.41 seconds
Started May 30 02:04:25 PM PDT 24
Finished May 30 02:04:28 PM PDT 24
Peak memory 219316 kb
Host smart-f5b158e9-dbe4-4b76-ab5b-6f6495548d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065484930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2065484930
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1019062877
Short name T196
Test name
Test status
Simulation time 19388957 ps
CPU time 1.07 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 219048 kb
Host smart-6e49851a-7b8c-480c-8cbe-a7d4538527ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019062877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1019062877
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2030317594
Short name T251
Test name
Test status
Simulation time 28183341 ps
CPU time 1.2 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 217704 kb
Host smart-470f653a-624e-497a-a015-383b1c006993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030317594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2030317594
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.4269557921
Short name T82
Test name
Test status
Simulation time 18179925 ps
CPU time 1.13 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 223496 kb
Host smart-af86a1fc-d703-4e88-ae03-014090b218ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269557921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4269557921
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1020450691
Short name T389
Test name
Test status
Simulation time 30741206 ps
CPU time 1.14 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 216820 kb
Host smart-fa3888ff-1fbe-4b1c-9538-d2123b9fb75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020450691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1020450691
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3558798047
Short name T55
Test name
Test status
Simulation time 99674189 ps
CPU time 0.98 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 223240 kb
Host smart-f28abaa9-9e8d-47d4-8fdf-a3fbc18695f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558798047 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3558798047
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2841165445
Short name T361
Test name
Test status
Simulation time 237321160 ps
CPU time 0.95 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 216636 kb
Host smart-317fdcf9-1f73-4379-b787-e68ab0d062c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841165445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2841165445
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.382942556
Short name T762
Test name
Test status
Simulation time 61234096 ps
CPU time 1.25 seconds
Started May 30 02:04:33 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 229336 kb
Host smart-29a735f8-1c38-4c40-8ebe-e3af1a773333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382942556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.382942556
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2244189773
Short name T298
Test name
Test status
Simulation time 121133665 ps
CPU time 1.5 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 218448 kb
Host smart-229469bf-07d5-45b0-b110-32f11a3df170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244189773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2244189773
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3420460051
Short name T714
Test name
Test status
Simulation time 19039622 ps
CPU time 1.13 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 218168 kb
Host smart-fcbe185d-78be-450f-b69b-9f4e758c5e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420460051 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3420460051
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2799833025
Short name T241
Test name
Test status
Simulation time 88135834 ps
CPU time 1.17 seconds
Started May 30 02:04:33 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 216728 kb
Host smart-9ad319e2-170d-4caf-b2ee-231e489859d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799833025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2799833025
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2592740426
Short name T581
Test name
Test status
Simulation time 25078632 ps
CPU time 1.11 seconds
Started May 30 02:04:29 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 219372 kb
Host smart-d7523e0e-987e-4854-886d-d2dbe7f62a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592740426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2592740426
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3479834072
Short name T406
Test name
Test status
Simulation time 83757067 ps
CPU time 1.3 seconds
Started May 30 02:04:33 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 216728 kb
Host smart-a61fe30a-1a02-4b83-8ee0-35ef0cd8d4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479834072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3479834072
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.934489113
Short name T32
Test name
Test status
Simulation time 32248855 ps
CPU time 0.98 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 219292 kb
Host smart-39a8c3a4-f303-4038-b4da-22b63e96a09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934489113 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.934489113
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3812102816
Short name T279
Test name
Test status
Simulation time 84632744 ps
CPU time 1.37 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 219560 kb
Host smart-4dd505a4-f837-4d8f-82c6-fefca7fc709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812102816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3812102816
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1161171340
Short name T76
Test name
Test status
Simulation time 20207227 ps
CPU time 1.01 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 218132 kb
Host smart-ae693b3e-7d3b-4b7a-8ef8-476d0adf42b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161171340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1161171340
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2472005860
Short name T243
Test name
Test status
Simulation time 55497359 ps
CPU time 1.66 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:32 PM PDT 24
Peak memory 217772 kb
Host smart-c0d32829-ce84-427a-8a4d-ed27f8346848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472005860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2472005860
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.390856932
Short name T36
Test name
Test status
Simulation time 53532434 ps
CPU time 1.27 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 215380 kb
Host smart-da4d0ef9-f28d-4ad1-9181-e3ef9cafe2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390856932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.390856932
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2983972635
Short name T354
Test name
Test status
Simulation time 14919644 ps
CPU time 0.94 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 206332 kb
Host smart-1b325e49-d3d9-4b87-a786-4f614e7c4610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983972635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2983972635
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2613474316
Short name T842
Test name
Test status
Simulation time 113899299 ps
CPU time 0.91 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215644 kb
Host smart-7430c541-20fc-4acd-b0e5-ed2fc3df305f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613474316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2613474316
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3830998295
Short name T174
Test name
Test status
Simulation time 324130386 ps
CPU time 1.27 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 216572 kb
Host smart-eff12389-1741-4b7e-aeda-0ecbaadcbfdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830998295 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3830998295
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.42620616
Short name T522
Test name
Test status
Simulation time 38486895 ps
CPU time 1.02 seconds
Started May 30 02:02:07 PM PDT 24
Finished May 30 02:02:10 PM PDT 24
Peak memory 223440 kb
Host smart-e6046d57-064d-4f6d-a51e-292c41e8651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42620616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.42620616
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3911848475
Short name T601
Test name
Test status
Simulation time 55197020 ps
CPU time 1.68 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 218068 kb
Host smart-6f710e25-656a-42d8-844c-eed6ad96186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911848475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3911848475
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2911663450
Short name T815
Test name
Test status
Simulation time 27004472 ps
CPU time 0.95 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215328 kb
Host smart-2a38cd5f-dde3-44a6-8f1b-1f2a3de7adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911663450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2911663450
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.1611390998
Short name T661
Test name
Test status
Simulation time 20634561 ps
CPU time 1.06 seconds
Started May 30 02:02:00 PM PDT 24
Finished May 30 02:02:02 PM PDT 24
Peak memory 206760 kb
Host smart-cf8709c5-b3b0-421c-bcfb-89dcdfdd778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611390998 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1611390998
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2406925220
Short name T390
Test name
Test status
Simulation time 16796988 ps
CPU time 1.01 seconds
Started May 30 02:01:59 PM PDT 24
Finished May 30 02:02:01 PM PDT 24
Peak memory 215016 kb
Host smart-98845d38-0145-4728-b843-4a68607ed7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406925220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2406925220
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4230412209
Short name T513
Test name
Test status
Simulation time 350225908 ps
CPU time 6.65 seconds
Started May 30 02:02:07 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 216736 kb
Host smart-f0426f4e-599e-450d-80f8-e7593b592a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230412209 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4230412209
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1464461798
Short name T750
Test name
Test status
Simulation time 235178870774 ps
CPU time 1294.22 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:23:42 PM PDT 24
Peak memory 222808 kb
Host smart-4c7a0a24-2723-46f9-9923-1321572dcce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464461798 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1464461798
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3635850202
Short name T107
Test name
Test status
Simulation time 54860705 ps
CPU time 1.1 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 220632 kb
Host smart-224bd4d1-08f2-4e76-97ab-f55f472b5f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635850202 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3635850202
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.30018614
Short name T497
Test name
Test status
Simulation time 72840394 ps
CPU time 1.1 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 216960 kb
Host smart-cf243ce3-d7f1-491d-bd89-f6a4da6d8077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30018614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.30018614
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2769467538
Short name T93
Test name
Test status
Simulation time 52733722 ps
CPU time 0.85 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 217960 kb
Host smart-79465a0e-9bc8-40fc-b94c-c54c9d3da0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769467538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2769467538
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1434198218
Short name T395
Test name
Test status
Simulation time 25535139 ps
CPU time 1.24 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 217972 kb
Host smart-714a0765-81ac-4581-8934-60af286bdb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434198218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1434198218
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3539617812
Short name T86
Test name
Test status
Simulation time 18917393 ps
CPU time 1.21 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 223544 kb
Host smart-2f99bd6c-db82-4de4-8048-3e730b4132cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539617812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3539617812
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/83.edn_err.1771056354
Short name T568
Test name
Test status
Simulation time 224425684 ps
CPU time 1.27 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 225300 kb
Host smart-7ab53981-2d4e-492c-8244-d66acbfc44d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771056354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1771056354
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2742680920
Short name T609
Test name
Test status
Simulation time 87696077 ps
CPU time 1.13 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 216848 kb
Host smart-4c3a51a3-c049-41d4-9adb-f58b9763cd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742680920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2742680920
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2763729242
Short name T64
Test name
Test status
Simulation time 47018977 ps
CPU time 1.21 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 225056 kb
Host smart-56c9ebf1-b705-41ab-a8c9-d8ea75155e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763729242 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2763729242
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1324353549
Short name T656
Test name
Test status
Simulation time 67661410 ps
CPU time 1.4 seconds
Started May 30 02:04:35 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 218164 kb
Host smart-1f2cf704-c94f-4f02-878c-ddbd7f10d27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324353549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1324353549
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.221513548
Short name T641
Test name
Test status
Simulation time 22202764 ps
CPU time 0.93 seconds
Started May 30 02:04:34 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 218300 kb
Host smart-b9fc6359-315b-4c2b-ab09-256667bee77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221513548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.221513548
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1378802040
Short name T435
Test name
Test status
Simulation time 230620655 ps
CPU time 1.25 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 216880 kb
Host smart-910cce01-1243-4640-b29d-ed45e0a2aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378802040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1378802040
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2616704438
Short name T776
Test name
Test status
Simulation time 28335990 ps
CPU time 0.85 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 218036 kb
Host smart-51df6edc-c745-4e8a-8165-893b286cc508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616704438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2616704438
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4247188329
Short name T591
Test name
Test status
Simulation time 30606952 ps
CPU time 1.26 seconds
Started May 30 02:04:24 PM PDT 24
Finished May 30 02:04:27 PM PDT 24
Peak memory 217808 kb
Host smart-9bb98df5-04ca-423c-9d6d-2bc3c201fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247188329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4247188329
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1401165596
Short name T95
Test name
Test status
Simulation time 24431675 ps
CPU time 0.9 seconds
Started May 30 02:04:30 PM PDT 24
Finished May 30 02:04:33 PM PDT 24
Peak memory 217924 kb
Host smart-d8ee1221-3100-4207-89a4-d055bc5182cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401165596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1401165596
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.909026786
Short name T466
Test name
Test status
Simulation time 81531075 ps
CPU time 1.22 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 218184 kb
Host smart-aa7c463f-11a8-4301-9f18-4826188bc3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909026786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.909026786
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3456643480
Short name T194
Test name
Test status
Simulation time 31431070 ps
CPU time 0.91 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 219412 kb
Host smart-35779f82-62b2-4c9a-86fb-4a43d4e5a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456643480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3456643480
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3870411453
Short name T303
Test name
Test status
Simulation time 41179538 ps
CPU time 1.6 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 219648 kb
Host smart-89b4320a-aaaa-4612-8dd4-67b413b5d360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870411453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3870411453
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3195662387
Short name T68
Test name
Test status
Simulation time 32751713 ps
CPU time 0.9 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 217812 kb
Host smart-57d5c147-7e44-4a13-9181-5646c78abbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195662387 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3195662387
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.220293253
Short name T430
Test name
Test status
Simulation time 62164489 ps
CPU time 1.11 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 216876 kb
Host smart-892be18c-741c-4fdc-a46b-af2907550ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220293253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.220293253
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.386567346
Short name T200
Test name
Test status
Simulation time 29245012 ps
CPU time 1.38 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215424 kb
Host smart-46d5c225-c81a-4ace-b3e7-601ad84260c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386567346 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.386567346
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.365226702
Short name T475
Test name
Test status
Simulation time 35180122 ps
CPU time 0.99 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 206408 kb
Host smart-38650c47-462e-499c-abcd-e2b16d3142b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365226702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.365226702
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2501748031
Short name T784
Test name
Test status
Simulation time 16595279 ps
CPU time 0.91 seconds
Started May 30 02:02:06 PM PDT 24
Finished May 30 02:02:08 PM PDT 24
Peak memory 215604 kb
Host smart-8eff3100-5f7d-468b-baf1-0c705814b16e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501748031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2501748031
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.807057148
Short name T60
Test name
Test status
Simulation time 50325584 ps
CPU time 1.39 seconds
Started May 30 02:02:07 PM PDT 24
Finished May 30 02:02:10 PM PDT 24
Peak memory 216656 kb
Host smart-c3f717e2-289a-47bf-abcd-9fcc78699e3a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807057148 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.807057148
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.2208027507
Short name T474
Test name
Test status
Simulation time 35795733 ps
CPU time 0.94 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:07 PM PDT 24
Peak memory 223320 kb
Host smart-1901307a-b021-4f36-8d98-6ad37f28c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208027507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.2208027507
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1554579875
Short name T403
Test name
Test status
Simulation time 61671242 ps
CPU time 1.26 seconds
Started May 30 02:02:03 PM PDT 24
Finished May 30 02:02:05 PM PDT 24
Peak memory 215052 kb
Host smart-0a898869-6d6d-44b0-98aa-ed60e21152d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554579875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1554579875
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.4046821023
Short name T265
Test name
Test status
Simulation time 27977663 ps
CPU time 0.95 seconds
Started May 30 02:02:05 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 206852 kb
Host smart-f7651684-cf90-4465-af5b-c92078c177f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046821023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4046821023
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.3517614883
Short name T334
Test name
Test status
Simulation time 17151899 ps
CPU time 1.01 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:02:06 PM PDT 24
Peak memory 215016 kb
Host smart-f2cf6ab2-d74c-4c4f-8747-ddf25811ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517614883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3517614883
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.118789964
Short name T645
Test name
Test status
Simulation time 302075823 ps
CPU time 5.91 seconds
Started May 30 02:02:07 PM PDT 24
Finished May 30 02:02:14 PM PDT 24
Peak memory 214968 kb
Host smart-604c6933-5bcb-428b-bbe3-675f28d9a618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118789964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.118789964
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2816074305
Short name T162
Test name
Test status
Simulation time 660199292897 ps
CPU time 1183.54 seconds
Started May 30 02:02:04 PM PDT 24
Finished May 30 02:21:49 PM PDT 24
Peak memory 220812 kb
Host smart-7dac7a68-9e29-40e0-bde2-5c5bfc14ce94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816074305 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2816074305
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3523923514
Short name T704
Test name
Test status
Simulation time 20427729 ps
CPU time 1.04 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 219264 kb
Host smart-48149a94-cc6c-474d-8de4-8af4b4c68e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523923514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3523923514
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2406598931
Short name T312
Test name
Test status
Simulation time 78157109 ps
CPU time 1.24 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 218280 kb
Host smart-a81ef517-f81f-4edd-b685-b96760bb7f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406598931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2406598931
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.401748581
Short name T63
Test name
Test status
Simulation time 43207025 ps
CPU time 1.23 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 224972 kb
Host smart-d488a70e-2cb2-4dd4-9991-b7f5c3857028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401748581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.401748581
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.560295010
Short name T555
Test name
Test status
Simulation time 175314892 ps
CPU time 2.52 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:36 PM PDT 24
Peak memory 219492 kb
Host smart-20c66881-6cd6-4068-a70e-07127e213d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560295010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.560295010
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3624626799
Short name T178
Test name
Test status
Simulation time 129152389 ps
CPU time 1.09 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 219068 kb
Host smart-3b1a4b58-bb9e-4d76-b2d6-1654728e16fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624626799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3624626799
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2637272262
Short name T767
Test name
Test status
Simulation time 30259564 ps
CPU time 1.19 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 215016 kb
Host smart-8a459d93-2d58-4de0-8c31-f0e222670b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637272262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2637272262
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2121703961
Short name T103
Test name
Test status
Simulation time 25157359 ps
CPU time 1.05 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 229072 kb
Host smart-ee83248c-f7a1-4781-9023-4f0c5c13edcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121703961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2121703961
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.388728753
Short name T360
Test name
Test status
Simulation time 53165749 ps
CPU time 1.03 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 219156 kb
Host smart-3ce6961c-8e29-40d4-968f-8ed16e2d4b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388728753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.388728753
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2428346678
Short name T810
Test name
Test status
Simulation time 33963193 ps
CPU time 0.93 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 217844 kb
Host smart-4f366cae-c38a-4fc5-8753-1ad2bb80c943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428346678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2428346678
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4134303673
Short name T595
Test name
Test status
Simulation time 67346878 ps
CPU time 1.53 seconds
Started May 30 02:04:32 PM PDT 24
Finished May 30 02:04:35 PM PDT 24
Peak memory 219504 kb
Host smart-e0bd644e-c003-42a0-9701-3834bf710761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134303673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4134303673
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.859333107
Short name T78
Test name
Test status
Simulation time 38088659 ps
CPU time 1.01 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 223316 kb
Host smart-e136b982-4ec6-4dd8-9b73-14068609b524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859333107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.859333107
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1883000043
Short name T814
Test name
Test status
Simulation time 68856069 ps
CPU time 1.18 seconds
Started May 30 02:04:26 PM PDT 24
Finished May 30 02:04:29 PM PDT 24
Peak memory 218312 kb
Host smart-2dfc2f9f-939a-4297-bde8-315b7e1de650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883000043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1883000043
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3152058629
Short name T456
Test name
Test status
Simulation time 35017332 ps
CPU time 0.98 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 219160 kb
Host smart-103ede17-482f-46b4-a614-159f16b20cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152058629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3152058629
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1064640983
Short name T293
Test name
Test status
Simulation time 93422984 ps
CPU time 1.44 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:38 PM PDT 24
Peak memory 217696 kb
Host smart-e4f56825-0930-4dad-b0f1-220673dfc09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064640983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1064640983
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.369717259
Short name T104
Test name
Test status
Simulation time 20594825 ps
CPU time 1.06 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 218800 kb
Host smart-e02b42a7-8747-425f-9048-1d909dc3c297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369717259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.369717259
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.4042464867
Short name T150
Test name
Test status
Simulation time 479803660 ps
CPU time 4.86 seconds
Started May 30 02:04:36 PM PDT 24
Finished May 30 02:04:42 PM PDT 24
Peak memory 217996 kb
Host smart-28096aac-8a7a-4a0e-a63a-eb350a398da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042464867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.4042464867
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.815291240
Short name T84
Test name
Test status
Simulation time 21621260 ps
CPU time 1.04 seconds
Started May 30 02:04:27 PM PDT 24
Finished May 30 02:04:30 PM PDT 24
Peak memory 223500 kb
Host smart-561539bb-6ee8-45f4-9cb8-59dec92fede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815291240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.815291240
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1130269960
Short name T460
Test name
Test status
Simulation time 67422043 ps
CPU time 1.36 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 218256 kb
Host smart-31331b21-e618-4939-97f3-1e8f65d6141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130269960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1130269960
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.917380057
Short name T577
Test name
Test status
Simulation time 26078617 ps
CPU time 0.91 seconds
Started May 30 02:04:31 PM PDT 24
Finished May 30 02:04:34 PM PDT 24
Peak memory 217952 kb
Host smart-ee80ee9e-3927-4b78-a48f-137ca16de033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917380057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.917380057
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3322903925
Short name T328
Test name
Test status
Simulation time 39692541 ps
CPU time 1.24 seconds
Started May 30 02:04:28 PM PDT 24
Finished May 30 02:04:31 PM PDT 24
Peak memory 217880 kb
Host smart-4090201a-ae06-479f-8279-62724cfbe0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322903925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3322903925
Directory /workspace/99.edn_genbits/latest
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