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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.41 98.24 93.74 97.07 84.30 96.62 99.77 91.12


Total test records in report: 980
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T782 /workspace/coverage/default/96.edn_err.3393493329 Jun 02 02:45:07 PM PDT 24 Jun 02 02:45:09 PM PDT 24 73211763 ps
T783 /workspace/coverage/default/170.edn_genbits.3794037547 Jun 02 02:45:16 PM PDT 24 Jun 02 02:46:30 PM PDT 24 2289028061 ps
T784 /workspace/coverage/default/51.edn_err.249444986 Jun 02 02:44:34 PM PDT 24 Jun 02 02:44:36 PM PDT 24 24881314 ps
T785 /workspace/coverage/default/247.edn_genbits.913519544 Jun 02 02:45:12 PM PDT 24 Jun 02 02:45:16 PM PDT 24 382584663 ps
T786 /workspace/coverage/default/233.edn_genbits.1861119762 Jun 02 02:45:12 PM PDT 24 Jun 02 02:45:15 PM PDT 24 64812363 ps
T787 /workspace/coverage/default/39.edn_stress_all.364168554 Jun 02 02:44:20 PM PDT 24 Jun 02 02:44:26 PM PDT 24 199729094 ps
T788 /workspace/coverage/default/292.edn_genbits.4215943322 Jun 02 02:45:49 PM PDT 24 Jun 02 02:45:52 PM PDT 24 52093997 ps
T789 /workspace/coverage/default/264.edn_genbits.3847921997 Jun 02 02:45:26 PM PDT 24 Jun 02 02:45:28 PM PDT 24 90537938 ps
T790 /workspace/coverage/default/36.edn_genbits.3206418806 Jun 02 02:44:28 PM PDT 24 Jun 02 02:44:30 PM PDT 24 75597504 ps
T791 /workspace/coverage/default/17.edn_intr.1865512933 Jun 02 02:43:49 PM PDT 24 Jun 02 02:43:50 PM PDT 24 27510767 ps
T792 /workspace/coverage/default/46.edn_intr.74802121 Jun 02 02:44:24 PM PDT 24 Jun 02 02:44:27 PM PDT 24 38742796 ps
T173 /workspace/coverage/default/30.edn_err.3486763953 Jun 02 02:44:17 PM PDT 24 Jun 02 02:44:19 PM PDT 24 71994366 ps
T793 /workspace/coverage/default/165.edn_genbits.3699902481 Jun 02 02:45:09 PM PDT 24 Jun 02 02:45:12 PM PDT 24 106498267 ps
T794 /workspace/coverage/default/134.edn_genbits.2510072420 Jun 02 02:45:23 PM PDT 24 Jun 02 02:45:25 PM PDT 24 91538096 ps
T795 /workspace/coverage/default/75.edn_genbits.2760287691 Jun 02 02:44:54 PM PDT 24 Jun 02 02:44:57 PM PDT 24 53347518 ps
T796 /workspace/coverage/default/5.edn_alert_test.505746994 Jun 02 02:43:51 PM PDT 24 Jun 02 02:43:52 PM PDT 24 19882575 ps
T797 /workspace/coverage/default/161.edn_genbits.1554849970 Jun 02 02:45:09 PM PDT 24 Jun 02 02:45:11 PM PDT 24 67590494 ps
T798 /workspace/coverage/default/1.edn_alert_test.1768395578 Jun 02 02:43:50 PM PDT 24 Jun 02 02:43:52 PM PDT 24 137085987 ps
T799 /workspace/coverage/default/36.edn_intr.4102609199 Jun 02 02:44:30 PM PDT 24 Jun 02 02:44:32 PM PDT 24 21509841 ps
T176 /workspace/coverage/default/40.edn_err.459585133 Jun 02 02:44:53 PM PDT 24 Jun 02 02:44:55 PM PDT 24 19044274 ps
T800 /workspace/coverage/default/6.edn_regwen.3427545790 Jun 02 02:43:36 PM PDT 24 Jun 02 02:43:37 PM PDT 24 46157269 ps
T801 /workspace/coverage/default/39.edn_alert_test.1672098396 Jun 02 02:44:35 PM PDT 24 Jun 02 02:44:37 PM PDT 24 48285764 ps
T802 /workspace/coverage/default/25.edn_disable_auto_req_mode.3603601122 Jun 02 02:44:16 PM PDT 24 Jun 02 02:44:18 PM PDT 24 69067867 ps
T803 /workspace/coverage/default/86.edn_genbits.2875498344 Jun 02 02:44:58 PM PDT 24 Jun 02 02:45:00 PM PDT 24 41680606 ps
T804 /workspace/coverage/default/16.edn_smoke.4105209498 Jun 02 02:43:52 PM PDT 24 Jun 02 02:43:54 PM PDT 24 55365574 ps
T805 /workspace/coverage/default/198.edn_genbits.53617480 Jun 02 02:45:09 PM PDT 24 Jun 02 02:45:10 PM PDT 24 86198864 ps
T806 /workspace/coverage/default/47.edn_alert.2589317730 Jun 02 02:44:54 PM PDT 24 Jun 02 02:45:01 PM PDT 24 48589791 ps
T807 /workspace/coverage/default/63.edn_genbits.583858697 Jun 02 02:44:44 PM PDT 24 Jun 02 02:44:46 PM PDT 24 39877224 ps
T808 /workspace/coverage/default/187.edn_genbits.3010792284 Jun 02 02:45:16 PM PDT 24 Jun 02 02:45:20 PM PDT 24 44981051 ps
T809 /workspace/coverage/default/44.edn_smoke.2654537453 Jun 02 02:44:23 PM PDT 24 Jun 02 02:44:26 PM PDT 24 16393142 ps
T810 /workspace/coverage/default/277.edn_genbits.1468276997 Jun 02 02:45:16 PM PDT 24 Jun 02 02:45:21 PM PDT 24 174339413 ps
T130 /workspace/coverage/default/2.edn_sec_cm.2098794930 Jun 02 02:43:34 PM PDT 24 Jun 02 02:43:44 PM PDT 24 583105772 ps
T811 /workspace/coverage/default/44.edn_disable_auto_req_mode.2339977752 Jun 02 02:44:35 PM PDT 24 Jun 02 02:44:37 PM PDT 24 22266826 ps
T812 /workspace/coverage/default/41.edn_disable_auto_req_mode.3264473623 Jun 02 02:44:22 PM PDT 24 Jun 02 02:44:25 PM PDT 24 40064165 ps
T813 /workspace/coverage/default/15.edn_smoke.3113790388 Jun 02 02:43:50 PM PDT 24 Jun 02 02:43:52 PM PDT 24 16153457 ps
T814 /workspace/coverage/default/162.edn_genbits.3411059076 Jun 02 02:45:15 PM PDT 24 Jun 02 02:45:19 PM PDT 24 39601379 ps
T815 /workspace/coverage/default/30.edn_disable_auto_req_mode.679175971 Jun 02 02:44:13 PM PDT 24 Jun 02 02:44:15 PM PDT 24 52774021 ps
T816 /workspace/coverage/default/252.edn_genbits.2771481930 Jun 02 02:45:19 PM PDT 24 Jun 02 02:45:22 PM PDT 24 38901640 ps
T817 /workspace/coverage/default/32.edn_smoke.1382002729 Jun 02 02:44:17 PM PDT 24 Jun 02 02:44:19 PM PDT 24 38040645 ps
T818 /workspace/coverage/default/153.edn_genbits.3279803325 Jun 02 02:45:15 PM PDT 24 Jun 02 02:45:19 PM PDT 24 63787739 ps
T819 /workspace/coverage/default/48.edn_smoke.1139242189 Jun 02 02:44:35 PM PDT 24 Jun 02 02:44:37 PM PDT 24 19804626 ps
T820 /workspace/coverage/default/177.edn_genbits.1137268445 Jun 02 02:45:15 PM PDT 24 Jun 02 02:45:19 PM PDT 24 75901138 ps
T821 /workspace/coverage/default/4.edn_err.3416628093 Jun 02 02:43:44 PM PDT 24 Jun 02 02:43:46 PM PDT 24 35545488 ps
T822 /workspace/coverage/default/33.edn_disable_auto_req_mode.3598475694 Jun 02 02:44:31 PM PDT 24 Jun 02 02:44:33 PM PDT 24 34714163 ps
T823 /workspace/coverage/default/201.edn_genbits.2051460685 Jun 02 02:45:11 PM PDT 24 Jun 02 02:45:14 PM PDT 24 61430568 ps
T824 /workspace/coverage/default/20.edn_alert.2017300775 Jun 02 02:43:59 PM PDT 24 Jun 02 02:44:01 PM PDT 24 26705434 ps
T825 /workspace/coverage/default/2.edn_alert.2664005019 Jun 02 02:43:34 PM PDT 24 Jun 02 02:43:36 PM PDT 24 29313045 ps
T826 /workspace/coverage/default/227.edn_genbits.3842999451 Jun 02 02:45:08 PM PDT 24 Jun 02 02:45:10 PM PDT 24 56401755 ps
T827 /workspace/coverage/default/30.edn_stress_all.1386640139 Jun 02 02:44:13 PM PDT 24 Jun 02 02:44:18 PM PDT 24 517140973 ps
T828 /workspace/coverage/default/42.edn_intr.2342916253 Jun 02 02:44:35 PM PDT 24 Jun 02 02:44:37 PM PDT 24 33832991 ps
T829 /workspace/coverage/default/31.edn_alert.884872753 Jun 02 02:44:20 PM PDT 24 Jun 02 02:44:22 PM PDT 24 46084518 ps
T830 /workspace/coverage/default/14.edn_stress_all.1468912020 Jun 02 02:43:55 PM PDT 24 Jun 02 02:44:00 PM PDT 24 201849265 ps
T831 /workspace/coverage/default/19.edn_err.3165335738 Jun 02 02:43:53 PM PDT 24 Jun 02 02:43:55 PM PDT 24 55815363 ps
T832 /workspace/coverage/default/298.edn_genbits.2071681605 Jun 02 02:45:26 PM PDT 24 Jun 02 02:45:27 PM PDT 24 45855475 ps
T833 /workspace/coverage/default/39.edn_genbits.2015509529 Jun 02 02:44:29 PM PDT 24 Jun 02 02:44:33 PM PDT 24 201503303 ps
T834 /workspace/coverage/default/39.edn_disable_auto_req_mode.939114889 Jun 02 02:44:20 PM PDT 24 Jun 02 02:44:23 PM PDT 24 31599275 ps
T835 /workspace/coverage/default/30.edn_alert_test.3567263290 Jun 02 02:44:20 PM PDT 24 Jun 02 02:44:23 PM PDT 24 24127410 ps
T836 /workspace/coverage/default/142.edn_genbits.3364646088 Jun 02 02:45:12 PM PDT 24 Jun 02 02:45:16 PM PDT 24 60553027 ps
T837 /workspace/coverage/default/36.edn_alert_test.4186337518 Jun 02 02:44:23 PM PDT 24 Jun 02 02:44:26 PM PDT 24 44195231 ps
T45 /workspace/coverage/default/69.edn_err.4068124437 Jun 02 02:44:53 PM PDT 24 Jun 02 02:44:55 PM PDT 24 41893854 ps
T838 /workspace/coverage/default/83.edn_genbits.1321715747 Jun 02 02:44:59 PM PDT 24 Jun 02 02:45:05 PM PDT 24 822151494 ps
T839 /workspace/coverage/default/218.edn_genbits.122760302 Jun 02 02:45:15 PM PDT 24 Jun 02 02:45:18 PM PDT 24 78267012 ps
T840 /workspace/coverage/default/49.edn_disable.1779263393 Jun 02 02:44:57 PM PDT 24 Jun 02 02:44:59 PM PDT 24 39793660 ps
T841 /workspace/coverage/default/14.edn_smoke.3137249621 Jun 02 02:44:06 PM PDT 24 Jun 02 02:44:08 PM PDT 24 26918135 ps
T842 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3303367708 Jun 02 02:44:50 PM PDT 24 Jun 02 02:57:15 PM PDT 24 59474599820 ps
T843 /workspace/coverage/cover_reg_top/1.edn_intr_test.778261989 Jun 02 02:13:48 PM PDT 24 Jun 02 02:13:49 PM PDT 24 35900079 ps
T844 /workspace/coverage/cover_reg_top/24.edn_intr_test.2618910272 Jun 02 02:14:27 PM PDT 24 Jun 02 02:14:29 PM PDT 24 74657490 ps
T231 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.532820130 Jun 02 02:13:44 PM PDT 24 Jun 02 02:13:51 PM PDT 24 2757343258 ps
T206 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3455230969 Jun 02 02:13:37 PM PDT 24 Jun 02 02:13:39 PM PDT 24 17974381 ps
T232 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3902986656 Jun 02 02:14:07 PM PDT 24 Jun 02 02:14:09 PM PDT 24 53357528 ps
T845 /workspace/coverage/cover_reg_top/43.edn_intr_test.2029856875 Jun 02 02:14:29 PM PDT 24 Jun 02 02:14:30 PM PDT 24 21557805 ps
T846 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1198413550 Jun 02 02:14:01 PM PDT 24 Jun 02 02:14:05 PM PDT 24 183314692 ps
T847 /workspace/coverage/cover_reg_top/10.edn_intr_test.1703426834 Jun 02 02:14:10 PM PDT 24 Jun 02 02:14:11 PM PDT 24 16030345 ps
T848 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.914487174 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:11 PM PDT 24 43851897 ps
T207 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3444367614 Jun 02 02:14:15 PM PDT 24 Jun 02 02:14:16 PM PDT 24 16005959 ps
T218 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2523462772 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 107658673 ps
T849 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1141901013 Jun 02 02:14:22 PM PDT 24 Jun 02 02:14:24 PM PDT 24 14937442 ps
T208 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3166516050 Jun 02 02:14:11 PM PDT 24 Jun 02 02:14:12 PM PDT 24 14636187 ps
T219 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1220171563 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:34 PM PDT 24 37331279 ps
T209 /workspace/coverage/cover_reg_top/18.edn_csr_rw.303534648 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:33 PM PDT 24 15736377 ps
T220 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2113132275 Jun 02 02:14:22 PM PDT 24 Jun 02 02:14:24 PM PDT 24 155297733 ps
T850 /workspace/coverage/cover_reg_top/45.edn_intr_test.1511642474 Jun 02 02:14:29 PM PDT 24 Jun 02 02:14:31 PM PDT 24 19181806 ps
T851 /workspace/coverage/cover_reg_top/22.edn_intr_test.2291744160 Jun 02 02:14:28 PM PDT 24 Jun 02 02:14:29 PM PDT 24 18600073 ps
T852 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4081520013 Jun 02 02:13:45 PM PDT 24 Jun 02 02:13:46 PM PDT 24 19559855 ps
T853 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2323596168 Jun 02 02:13:49 PM PDT 24 Jun 02 02:13:51 PM PDT 24 29172324 ps
T854 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3915604654 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:02 PM PDT 24 61635962 ps
T221 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.561598491 Jun 02 02:14:22 PM PDT 24 Jun 02 02:14:24 PM PDT 24 59772642 ps
T233 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2987142474 Jun 02 02:13:55 PM PDT 24 Jun 02 02:13:57 PM PDT 24 39154253 ps
T210 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3094454965 Jun 02 02:14:15 PM PDT 24 Jun 02 02:14:17 PM PDT 24 47401406 ps
T211 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1214666220 Jun 02 02:13:54 PM PDT 24 Jun 02 02:13:55 PM PDT 24 64081828 ps
T855 /workspace/coverage/cover_reg_top/19.edn_intr_test.187645072 Jun 02 02:14:27 PM PDT 24 Jun 02 02:14:29 PM PDT 24 50054301 ps
T856 /workspace/coverage/cover_reg_top/26.edn_intr_test.1457666151 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 12363522 ps
T857 /workspace/coverage/cover_reg_top/14.edn_intr_test.3553091838 Jun 02 02:14:22 PM PDT 24 Jun 02 02:14:24 PM PDT 24 60492728 ps
T212 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3726963107 Jun 02 02:14:17 PM PDT 24 Jun 02 02:14:19 PM PDT 24 36546584 ps
T858 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3862581949 Jun 02 02:13:44 PM PDT 24 Jun 02 02:13:48 PM PDT 24 118239860 ps
T859 /workspace/coverage/cover_reg_top/30.edn_intr_test.1824274265 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 38843865 ps
T860 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.270397201 Jun 02 02:13:54 PM PDT 24 Jun 02 02:13:58 PM PDT 24 583738168 ps
T222 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2206637893 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:23 PM PDT 24 26748924 ps
T861 /workspace/coverage/cover_reg_top/36.edn_intr_test.2580182584 Jun 02 02:14:27 PM PDT 24 Jun 02 02:14:29 PM PDT 24 44760182 ps
T223 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2651266461 Jun 02 02:13:59 PM PDT 24 Jun 02 02:14:01 PM PDT 24 19612392 ps
T862 /workspace/coverage/cover_reg_top/12.edn_intr_test.2456746399 Jun 02 02:14:17 PM PDT 24 Jun 02 02:14:18 PM PDT 24 45703485 ps
T863 /workspace/coverage/cover_reg_top/6.edn_intr_test.212138456 Jun 02 02:13:59 PM PDT 24 Jun 02 02:14:00 PM PDT 24 11935569 ps
T234 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2021740734 Jun 02 02:14:04 PM PDT 24 Jun 02 02:14:07 PM PDT 24 174701950 ps
T213 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3423452393 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:02 PM PDT 24 78351524 ps
T864 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3472583870 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:22 PM PDT 24 96144673 ps
T865 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2309089474 Jun 02 02:13:58 PM PDT 24 Jun 02 02:14:03 PM PDT 24 478844620 ps
T235 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.704619699 Jun 02 02:13:56 PM PDT 24 Jun 02 02:13:58 PM PDT 24 155738363 ps
T866 /workspace/coverage/cover_reg_top/17.edn_intr_test.144872573 Jun 02 02:14:19 PM PDT 24 Jun 02 02:14:20 PM PDT 24 31106569 ps
T867 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4072439700 Jun 02 02:14:14 PM PDT 24 Jun 02 02:14:16 PM PDT 24 327385847 ps
T868 /workspace/coverage/cover_reg_top/42.edn_intr_test.1514635749 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:32 PM PDT 24 11450908 ps
T869 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1890099584 Jun 02 02:13:37 PM PDT 24 Jun 02 02:13:40 PM PDT 24 644369519 ps
T870 /workspace/coverage/cover_reg_top/3.edn_intr_test.3015353273 Jun 02 02:13:54 PM PDT 24 Jun 02 02:13:55 PM PDT 24 187926171 ps
T871 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1658851499 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:04 PM PDT 24 329410816 ps
T872 /workspace/coverage/cover_reg_top/8.edn_intr_test.4091426840 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:10 PM PDT 24 15982938 ps
T237 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3754729147 Jun 02 02:14:02 PM PDT 24 Jun 02 02:14:05 PM PDT 24 111142475 ps
T873 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3935734150 Jun 02 02:14:02 PM PDT 24 Jun 02 02:14:04 PM PDT 24 178096056 ps
T874 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4155058794 Jun 02 02:13:54 PM PDT 24 Jun 02 02:13:56 PM PDT 24 112545961 ps
T238 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.47968851 Jun 02 02:14:16 PM PDT 24 Jun 02 02:14:18 PM PDT 24 272496092 ps
T875 /workspace/coverage/cover_reg_top/7.edn_intr_test.1645890973 Jun 02 02:14:03 PM PDT 24 Jun 02 02:14:05 PM PDT 24 16321890 ps
T214 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3719844935 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:22 PM PDT 24 29384548 ps
T876 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1788930331 Jun 02 02:14:19 PM PDT 24 Jun 02 02:14:22 PM PDT 24 100364204 ps
T877 /workspace/coverage/cover_reg_top/16.edn_intr_test.1746314135 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:23 PM PDT 24 15554800 ps
T236 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1825435406 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:35 PM PDT 24 72525705 ps
T878 /workspace/coverage/cover_reg_top/49.edn_intr_test.1520052010 Jun 02 02:14:34 PM PDT 24 Jun 02 02:14:35 PM PDT 24 25196766 ps
T879 /workspace/coverage/cover_reg_top/32.edn_intr_test.936724293 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:28 PM PDT 24 15609279 ps
T880 /workspace/coverage/cover_reg_top/5.edn_intr_test.2216051356 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:02 PM PDT 24 14790093 ps
T881 /workspace/coverage/cover_reg_top/33.edn_intr_test.468608414 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:28 PM PDT 24 68832033 ps
T215 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3107511941 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:11 PM PDT 24 147714638 ps
T882 /workspace/coverage/cover_reg_top/9.edn_intr_test.1945379940 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:10 PM PDT 24 23369549 ps
T883 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.390625028 Jun 02 02:13:53 PM PDT 24 Jun 02 02:13:55 PM PDT 24 29395955 ps
T884 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2823311386 Jun 02 02:14:03 PM PDT 24 Jun 02 02:14:05 PM PDT 24 85451922 ps
T885 /workspace/coverage/cover_reg_top/14.edn_tl_errors.243559213 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:25 PM PDT 24 387854625 ps
T239 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3898114509 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:34 PM PDT 24 196577277 ps
T886 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4201171366 Jun 02 02:13:48 PM PDT 24 Jun 02 02:13:50 PM PDT 24 41472684 ps
T887 /workspace/coverage/cover_reg_top/4.edn_intr_test.250781065 Jun 02 02:13:54 PM PDT 24 Jun 02 02:13:55 PM PDT 24 19594807 ps
T888 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.638342572 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:10 PM PDT 24 54011279 ps
T889 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1452638727 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:11 PM PDT 24 21535706 ps
T890 /workspace/coverage/cover_reg_top/28.edn_intr_test.286800077 Jun 02 02:14:29 PM PDT 24 Jun 02 02:14:30 PM PDT 24 15509040 ps
T891 /workspace/coverage/cover_reg_top/40.edn_intr_test.1943864924 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:33 PM PDT 24 19965484 ps
T892 /workspace/coverage/cover_reg_top/11.edn_intr_test.2536534495 Jun 02 02:14:11 PM PDT 24 Jun 02 02:14:12 PM PDT 24 17830587 ps
T893 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1390468685 Jun 02 02:14:16 PM PDT 24 Jun 02 02:14:18 PM PDT 24 111866752 ps
T894 /workspace/coverage/cover_reg_top/13.edn_intr_test.2686365640 Jun 02 02:14:15 PM PDT 24 Jun 02 02:14:17 PM PDT 24 48790622 ps
T895 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4069598676 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:22 PM PDT 24 25012334 ps
T896 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3205746281 Jun 02 02:14:28 PM PDT 24 Jun 02 02:14:30 PM PDT 24 76265187 ps
T897 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2582422197 Jun 02 02:13:49 PM PDT 24 Jun 02 02:13:53 PM PDT 24 182406176 ps
T898 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.585238672 Jun 02 02:13:43 PM PDT 24 Jun 02 02:13:44 PM PDT 24 45057005 ps
T899 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1150246924 Jun 02 02:13:42 PM PDT 24 Jun 02 02:13:44 PM PDT 24 53385673 ps
T900 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3259855016 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:51 PM PDT 24 43404812 ps
T901 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1997364943 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:29 PM PDT 24 94409078 ps
T902 /workspace/coverage/cover_reg_top/17.edn_tl_errors.222585668 Jun 02 02:14:19 PM PDT 24 Jun 02 02:14:21 PM PDT 24 89767690 ps
T903 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3342623480 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:52 PM PDT 24 20847004 ps
T904 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1205648291 Jun 02 02:14:08 PM PDT 24 Jun 02 02:14:09 PM PDT 24 22286557 ps
T905 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2871447027 Jun 02 02:14:12 PM PDT 24 Jun 02 02:14:14 PM PDT 24 31540312 ps
T906 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2819874036 Jun 02 02:14:14 PM PDT 24 Jun 02 02:14:16 PM PDT 24 41336522 ps
T907 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2635587814 Jun 02 02:14:04 PM PDT 24 Jun 02 02:14:06 PM PDT 24 58230278 ps
T908 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1487953981 Jun 02 02:13:49 PM PDT 24 Jun 02 02:13:54 PM PDT 24 351391155 ps
T909 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2617514952 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:23 PM PDT 24 56174592 ps
T910 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1123052779 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:32 PM PDT 24 52096690 ps
T911 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3300086500 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:54 PM PDT 24 282822202 ps
T912 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2997045122 Jun 02 02:13:58 PM PDT 24 Jun 02 02:14:01 PM PDT 24 71971005 ps
T913 /workspace/coverage/cover_reg_top/35.edn_intr_test.2696915695 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:26 PM PDT 24 17948666 ps
T914 /workspace/coverage/cover_reg_top/15.edn_intr_test.3283485100 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:23 PM PDT 24 24348143 ps
T915 /workspace/coverage/cover_reg_top/27.edn_intr_test.1098083571 Jun 02 02:14:27 PM PDT 24 Jun 02 02:14:29 PM PDT 24 32754189 ps
T916 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1197724530 Jun 02 02:13:48 PM PDT 24 Jun 02 02:13:51 PM PDT 24 90242669 ps
T917 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3709191302 Jun 02 02:14:04 PM PDT 24 Jun 02 02:14:07 PM PDT 24 1285363396 ps
T918 /workspace/coverage/cover_reg_top/21.edn_intr_test.2359639235 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 49788552 ps
T919 /workspace/coverage/cover_reg_top/18.edn_intr_test.2384745548 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:22 PM PDT 24 24364502 ps
T920 /workspace/coverage/cover_reg_top/38.edn_intr_test.1449898701 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:31 PM PDT 24 13149700 ps
T921 /workspace/coverage/cover_reg_top/46.edn_intr_test.2754815287 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:33 PM PDT 24 107656805 ps
T922 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3729944670 Jun 02 02:14:15 PM PDT 24 Jun 02 02:14:16 PM PDT 24 44927052 ps
T923 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2006116073 Jun 02 02:14:03 PM PDT 24 Jun 02 02:14:05 PM PDT 24 38798248 ps
T924 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3513828497 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:28 PM PDT 24 44123687 ps
T925 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2798879655 Jun 02 02:13:40 PM PDT 24 Jun 02 02:13:41 PM PDT 24 122861510 ps
T926 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3199683784 Jun 02 02:13:46 PM PDT 24 Jun 02 02:13:47 PM PDT 24 58599993 ps
T927 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3478248597 Jun 02 02:14:10 PM PDT 24 Jun 02 02:14:11 PM PDT 24 14832135 ps
T928 /workspace/coverage/cover_reg_top/29.edn_intr_test.2869706820 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:27 PM PDT 24 16738938 ps
T929 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.718629740 Jun 02 02:14:17 PM PDT 24 Jun 02 02:14:19 PM PDT 24 26067350 ps
T930 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1566696997 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:33 PM PDT 24 47743133 ps
T931 /workspace/coverage/cover_reg_top/6.edn_csr_rw.18754497 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:02 PM PDT 24 17211257 ps
T217 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3716331929 Jun 02 02:13:58 PM PDT 24 Jun 02 02:14:00 PM PDT 24 22216419 ps
T932 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3085421763 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:29 PM PDT 24 22091452 ps
T933 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.639934528 Jun 02 02:13:55 PM PDT 24 Jun 02 02:13:57 PM PDT 24 38217838 ps
T934 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2882176208 Jun 02 02:14:11 PM PDT 24 Jun 02 02:14:13 PM PDT 24 20647537 ps
T935 /workspace/coverage/cover_reg_top/0.edn_intr_test.920505609 Jun 02 02:13:39 PM PDT 24 Jun 02 02:13:41 PM PDT 24 13414842 ps
T936 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.860446188 Jun 02 02:13:43 PM PDT 24 Jun 02 02:13:45 PM PDT 24 66021157 ps
T937 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1132937686 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:23 PM PDT 24 330187100 ps
T938 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2200826098 Jun 02 02:13:53 PM PDT 24 Jun 02 02:13:55 PM PDT 24 86998758 ps
T939 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.991983811 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:24 PM PDT 24 41960692 ps
T940 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1163657162 Jun 02 02:14:15 PM PDT 24 Jun 02 02:14:18 PM PDT 24 24659626 ps
T941 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2758021653 Jun 02 02:14:21 PM PDT 24 Jun 02 02:14:23 PM PDT 24 14607037 ps
T942 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1960730904 Jun 02 02:14:19 PM PDT 24 Jun 02 02:14:24 PM PDT 24 386042304 ps
T943 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3496087960 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:51 PM PDT 24 27823454 ps
T944 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3520928200 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:27 PM PDT 24 57116618 ps
T945 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2637808312 Jun 02 02:14:28 PM PDT 24 Jun 02 02:14:30 PM PDT 24 182703030 ps
T946 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2770171766 Jun 02 02:14:16 PM PDT 24 Jun 02 02:14:18 PM PDT 24 417489303 ps
T947 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.6361552 Jun 02 02:14:12 PM PDT 24 Jun 02 02:14:15 PM PDT 24 284471899 ps
T948 /workspace/coverage/cover_reg_top/2.edn_intr_test.2602444609 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:51 PM PDT 24 28082755 ps
T949 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2283053263 Jun 02 02:13:52 PM PDT 24 Jun 02 02:13:53 PM PDT 24 21135706 ps
T950 /workspace/coverage/cover_reg_top/37.edn_intr_test.618069290 Jun 02 02:14:28 PM PDT 24 Jun 02 02:14:30 PM PDT 24 37960257 ps
T951 /workspace/coverage/cover_reg_top/39.edn_intr_test.1147514238 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:32 PM PDT 24 51619018 ps
T952 /workspace/coverage/cover_reg_top/47.edn_intr_test.206237169 Jun 02 02:14:29 PM PDT 24 Jun 02 02:14:30 PM PDT 24 41601478 ps
T953 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1193843609 Jun 02 02:14:06 PM PDT 24 Jun 02 02:14:10 PM PDT 24 109158385 ps
T954 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.157533754 Jun 02 02:13:42 PM PDT 24 Jun 02 02:13:44 PM PDT 24 46069056 ps
T955 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3168728537 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:02 PM PDT 24 62685749 ps
T956 /workspace/coverage/cover_reg_top/41.edn_intr_test.459881925 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:32 PM PDT 24 49282052 ps
T957 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3910176865 Jun 02 02:13:37 PM PDT 24 Jun 02 02:13:39 PM PDT 24 117433310 ps
T958 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.135463137 Jun 02 02:14:00 PM PDT 24 Jun 02 02:14:06 PM PDT 24 223001024 ps
T959 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1239184126 Jun 02 02:14:32 PM PDT 24 Jun 02 02:14:35 PM PDT 24 264814174 ps
T960 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2430337255 Jun 02 02:14:31 PM PDT 24 Jun 02 02:14:33 PM PDT 24 48844760 ps
T961 /workspace/coverage/cover_reg_top/31.edn_intr_test.3751024329 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 23058872 ps
T962 /workspace/coverage/cover_reg_top/34.edn_intr_test.3555253773 Jun 02 02:14:28 PM PDT 24 Jun 02 02:14:29 PM PDT 24 24694179 ps
T963 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3774156538 Jun 02 02:14:20 PM PDT 24 Jun 02 02:14:22 PM PDT 24 25155205 ps
T964 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3745607986 Jun 02 02:14:10 PM PDT 24 Jun 02 02:14:13 PM PDT 24 87223454 ps
T965 /workspace/coverage/cover_reg_top/6.edn_tl_errors.322361803 Jun 02 02:14:03 PM PDT 24 Jun 02 02:14:05 PM PDT 24 207268843 ps
T966 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2402927484 Jun 02 02:13:58 PM PDT 24 Jun 02 02:13:59 PM PDT 24 14809404 ps
T967 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1123165038 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:11 PM PDT 24 72371652 ps
T968 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2815466100 Jun 02 02:14:05 PM PDT 24 Jun 02 02:14:06 PM PDT 24 66071011 ps
T969 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3446337614 Jun 02 02:14:09 PM PDT 24 Jun 02 02:14:11 PM PDT 24 30635860 ps
T216 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3691397713 Jun 02 02:13:50 PM PDT 24 Jun 02 02:13:51 PM PDT 24 34964770 ps
T970 /workspace/coverage/cover_reg_top/48.edn_intr_test.319882393 Jun 02 02:14:29 PM PDT 24 Jun 02 02:14:30 PM PDT 24 13735082 ps
T971 /workspace/coverage/cover_reg_top/23.edn_intr_test.1316252404 Jun 02 02:14:38 PM PDT 24 Jun 02 02:14:39 PM PDT 24 58974932 ps
T972 /workspace/coverage/cover_reg_top/25.edn_intr_test.1679919980 Jun 02 02:14:25 PM PDT 24 Jun 02 02:14:27 PM PDT 24 43034902 ps
T973 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.922420258 Jun 02 02:14:04 PM PDT 24 Jun 02 02:14:05 PM PDT 24 17971687 ps
T974 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1552567884 Jun 02 02:14:12 PM PDT 24 Jun 02 02:14:16 PM PDT 24 81641747 ps
T975 /workspace/coverage/cover_reg_top/44.edn_intr_test.3748388937 Jun 02 02:14:30 PM PDT 24 Jun 02 02:14:31 PM PDT 24 15928893 ps
T976 /workspace/coverage/cover_reg_top/20.edn_intr_test.414991477 Jun 02 02:14:26 PM PDT 24 Jun 02 02:14:27 PM PDT 24 41582533 ps
T977 /workspace/coverage/cover_reg_top/4.edn_csr_rw.535538509 Jun 02 02:13:58 PM PDT 24 Jun 02 02:13:59 PM PDT 24 24665458 ps
T978 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.861080131 Jun 02 02:14:17 PM PDT 24 Jun 02 02:14:19 PM PDT 24 22472368 ps
T979 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3048882168 Jun 02 02:13:45 PM PDT 24 Jun 02 02:13:47 PM PDT 24 667100006 ps
T980 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2190284444 Jun 02 02:14:03 PM PDT 24 Jun 02 02:14:05 PM PDT 24 62823978 ps

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.955163406
Short name T24
Test name
Test status
Simulation time 124408848732 ps
CPU time 811.91 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:57:50 PM PDT 24
Peak memory 223380 kb
Host smart-765d8c38-0838-44e9-8f7d-6468784345a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955163406 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.955163406
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.edn_genbits.2355495236
Short name T115
Test name
Test status
Simulation time 39891890 ps
CPU time 1.58 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 217976 kb
Host smart-2ad95377-78d2-4439-bcc7-8d03564380f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355495236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2355495236
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1085269112
Short name T8
Test name
Test status
Simulation time 27202219 ps
CPU time 1.22 seconds
Started Jun 02 02:44:10 PM PDT 24
Finished Jun 02 02:44:12 PM PDT 24
Peak memory 215304 kb
Host smart-b59ca41b-144d-4047-a2d3-6fdbdd5156e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085269112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1085269112
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1335161379
Short name T13
Test name
Test status
Simulation time 495670972 ps
CPU time 3.93 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 236068 kb
Host smart-b0a81b04-c514-4e72-8afa-132225ab8e62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335161379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1335161379
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/52.edn_genbits.2871195636
Short name T11
Test name
Test status
Simulation time 47813599 ps
CPU time 1.49 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 219320 kb
Host smart-ce394686-fef6-47e9-b4f6-cee0fd657cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871195636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2871195636
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3159924201
Short name T224
Test name
Test status
Simulation time 36469456 ps
CPU time 0.92 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 217900 kb
Host smart-2c7c6a3c-2bb5-4895-a8fe-f65a48089f1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159924201 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3159924201
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1398897621
Short name T129
Test name
Test status
Simulation time 999148225 ps
CPU time 14.04 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 234764 kb
Host smart-a9c7f2ee-9207-4980-9d01-7009e5d673f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398897621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1398897621
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/66.edn_err.336686446
Short name T2
Test name
Test status
Simulation time 43276934 ps
CPU time 1.09 seconds
Started Jun 02 02:44:56 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 215168 kb
Host smart-7f4f7dba-dca3-4815-a896-5c7fac766a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336686446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.336686446
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1706071632
Short name T53
Test name
Test status
Simulation time 221713139 ps
CPU time 1.15 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216696 kb
Host smart-233c9384-906b-46b4-9bf2-7c3facf3cb4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706071632 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1706071632
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_alert.365964658
Short name T67
Test name
Test status
Simulation time 46999657 ps
CPU time 1.16 seconds
Started Jun 02 02:44:42 PM PDT 24
Finished Jun 02 02:44:43 PM PDT 24
Peak memory 215328 kb
Host smart-b65a77d6-6d26-4905-aaa0-e42a7e4d7574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365964658 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.365964658
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/9.edn_regwen.4050430010
Short name T103
Test name
Test status
Simulation time 18406246 ps
CPU time 1 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 206752 kb
Host smart-6ba00216-4618-460a-b4f1-64d19e0752e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050430010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.4050430010
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/283.edn_genbits.3372017503
Short name T30
Test name
Test status
Simulation time 103636819 ps
CPU time 1.36 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:29 PM PDT 24
Peak memory 218352 kb
Host smart-a0584c2f-e0f9-459a-b131-b027735deaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372017503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3372017503
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.581425373
Short name T96
Test name
Test status
Simulation time 45857126 ps
CPU time 1.26 seconds
Started Jun 02 02:44:04 PM PDT 24
Finished Jun 02 02:44:06 PM PDT 24
Peak memory 215296 kb
Host smart-cdcd3859-6c5b-4834-b8de-8a00a4b505ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581425373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.581425373
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.6388482
Short name T195
Test name
Test status
Simulation time 183273957610 ps
CPU time 2074.92 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 03:18:38 PM PDT 24
Peak memory 226384 kb
Host smart-e9afe777-445d-4a16-b402-facce64a0a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6388482 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.6388482
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.846762365
Short name T28
Test name
Test status
Simulation time 48206935 ps
CPU time 1.5 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216672 kb
Host smart-624db01c-00ff-4852-9bf3-8f1b8f42b027
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846762365 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di
sable_auto_req_mode.846762365
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.47968851
Short name T238
Test name
Test status
Simulation time 272496092 ps
CPU time 2.3 seconds
Started Jun 02 02:14:16 PM PDT 24
Finished Jun 02 02:14:18 PM PDT 24
Peak memory 206132 kb
Host smart-d96c00ed-d3ac-4e56-87d9-94e627f16abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47968851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.47968851
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/default/18.edn_disable.1421180180
Short name T159
Test name
Test status
Simulation time 102997622 ps
CPU time 0.85 seconds
Started Jun 02 02:44:10 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 216008 kb
Host smart-910dd057-3d4a-4659-a976-558ae820a6e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421180180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1421180180
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable.3372836210
Short name T157
Test name
Test status
Simulation time 12141422 ps
CPU time 0.86 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216136 kb
Host smart-0800f142-da80-4d40-9f62-0848658f703f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372836210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3372836210
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable.2007129898
Short name T180
Test name
Test status
Simulation time 14249535 ps
CPU time 0.94 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 216164 kb
Host smart-2c3bdd2b-5782-4bd0-9af8-77a3383c1276
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007129898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2007129898
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.3331580924
Short name T97
Test name
Test status
Simulation time 34476116 ps
CPU time 0.85 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:43:39 PM PDT 24
Peak memory 218684 kb
Host smart-caba42b0-1f6e-4486-8983-a71187a9f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331580924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3331580924
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3444367614
Short name T207
Test name
Test status
Simulation time 16005959 ps
CPU time 0.95 seconds
Started Jun 02 02:14:15 PM PDT 24
Finished Jun 02 02:14:16 PM PDT 24
Peak memory 206068 kb
Host smart-88f111d6-32b6-4bd3-898d-3adeb3cc33d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444367614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3444367614
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/120.edn_genbits.4203597154
Short name T263
Test name
Test status
Simulation time 35046778 ps
CPU time 1.36 seconds
Started Jun 02 02:45:03 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 218812 kb
Host smart-49a93bd4-5f0d-4533-9c1b-871ef4feea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203597154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.4203597154
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_alert.1036308803
Short name T72
Test name
Test status
Simulation time 38984670 ps
CPU time 1.13 seconds
Started Jun 02 02:44:39 PM PDT 24
Finished Jun 02 02:44:41 PM PDT 24
Peak memory 215344 kb
Host smart-fb4660fc-4740-419b-b514-4d56e045b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036308803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1036308803
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.4165351326
Short name T34
Test name
Test status
Simulation time 95171806 ps
CPU time 1.17 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 216596 kb
Host smart-4f8ca75d-ce93-4178-aaa6-03401adb1fb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165351326 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.4165351326
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2087272135
Short name T15
Test name
Test status
Simulation time 19088093 ps
CPU time 1.17 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 223440 kb
Host smart-97fa5923-dc65-4105-b94b-d0d8b8f3927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087272135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2087272135
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.3809141343
Short name T17
Test name
Test status
Simulation time 37161870 ps
CPU time 0.88 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:02 PM PDT 24
Peak memory 215316 kb
Host smart-5a2601f3-925d-4fdf-985c-107d4c20aee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809141343 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3809141343
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.660484989
Short name T50
Test name
Test status
Simulation time 112172838 ps
CPU time 1.17 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 215344 kb
Host smart-3903925a-8490-4da4-9966-77a41739e70a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660484989 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.660484989
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_alert.2560051385
Short name T151
Test name
Test status
Simulation time 27426045 ps
CPU time 1.3 seconds
Started Jun 02 02:44:01 PM PDT 24
Finished Jun 02 02:44:03 PM PDT 24
Peak memory 215292 kb
Host smart-ad26e911-6dcd-48e9-bfc2-e11b728f9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560051385 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2560051385
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2748805318
Short name T33
Test name
Test status
Simulation time 118707936 ps
CPU time 1.11 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 216608 kb
Host smart-1722fee0-3847-4aca-8bf4-da955abf0418
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748805318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2748805318
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_disable.2732904348
Short name T187
Test name
Test status
Simulation time 81899761 ps
CPU time 0.87 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 215184 kb
Host smart-995cbf77-7785-4505-b1c1-776e9d6343db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732904348 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2732904348
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/84.edn_genbits.4142985001
Short name T21
Test name
Test status
Simulation time 61843084 ps
CPU time 1.12 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 219524 kb
Host smart-b8a515a5-cf81-4e5b-aedc-6a587bc0765c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142985001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4142985001
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_disable.1992209730
Short name T168
Test name
Test status
Simulation time 12437999 ps
CPU time 0.9 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216248 kb
Host smart-64cf2a8e-6567-4224-bc5f-ca1aecdcc5f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992209730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1992209730
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.2276108916
Short name T156
Test name
Test status
Simulation time 13303432 ps
CPU time 0.93 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 216272 kb
Host smart-55692151-9e41-44f4-af33-f5fa4b1533d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276108916 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2276108916
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/1.edn_intr.502408866
Short name T145
Test name
Test status
Simulation time 35815776 ps
CPU time 0.9 seconds
Started Jun 02 02:43:41 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 215168 kb
Host smart-a83114c1-1fbf-49e0-8f2f-21f72c3326f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502408866 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.502408866
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/12.edn_err.482989381
Short name T93
Test name
Test status
Simulation time 24235748 ps
CPU time 1 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:43:53 PM PDT 24
Peak memory 218028 kb
Host smart-723f0c2c-65db-4e01-9563-6a5fab8ac7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482989381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.482989381
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/16.edn_disable.519312970
Short name T82
Test name
Test status
Simulation time 14802557 ps
CPU time 0.94 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 216148 kb
Host smart-87f2ec8e-5ea3-4997-b44f-7d0884cad8a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519312970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.519312970
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.309156097
Short name T165
Test name
Test status
Simulation time 65813590 ps
CPU time 1.22 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 217792 kb
Host smart-e0e5b6f3-757c-4f5a-b4b8-3599334a7582
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309156097 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.309156097
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.1338766924
Short name T158
Test name
Test status
Simulation time 12525426 ps
CPU time 0.91 seconds
Started Jun 02 02:44:28 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 216492 kb
Host smart-623f2db5-0611-4ba0-be0e-baaadeb21cc4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338766924 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1338766924
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/72.edn_err.860955728
Short name T85
Test name
Test status
Simulation time 33997634 ps
CPU time 1.01 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 223284 kb
Host smart-bfff6fc5-87a5-4ce9-b9d8-06b6c9f3bdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860955728 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.860955728
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/11.edn_alert_test.3914629928
Short name T155
Test name
Test status
Simulation time 15890621 ps
CPU time 0.93 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 206264 kb
Host smart-95df7026-c04d-4e21-b23f-f2272ce933bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914629928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3914629928
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3691397713
Short name T216
Test name
Test status
Simulation time 34964770 ps
CPU time 0.91 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 206064 kb
Host smart-4597e8c6-05bf-4a78-b9ca-ace8cd1f3e87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691397713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3691397713
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/12.edn_stress_all.2656962191
Short name T204
Test name
Test status
Simulation time 2088246387 ps
CPU time 5.76 seconds
Started Jun 02 02:43:45 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 216800 kb
Host smart-26414a8a-31d3-49b3-b5ea-171622f6ac09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656962191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2656962191
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_regwen.3427545790
Short name T800
Test name
Test status
Simulation time 46157269 ps
CPU time 0.92 seconds
Started Jun 02 02:43:36 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 206772 kb
Host smart-2e801912-f18e-42cc-9d22-352f6f9dcbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427545790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3427545790
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/22.edn_intr.2748803356
Short name T107
Test name
Test status
Simulation time 24699385 ps
CPU time 0.9 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 215368 kb
Host smart-c6c61759-dc58-438e-ad5a-7aa2c264199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748803356 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2748803356
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/156.edn_genbits.1986835441
Short name T122
Test name
Test status
Simulation time 57239580 ps
CPU time 1.89 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 218024 kb
Host smart-73e5f99d-7207-4166-bab9-431146ea4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986835441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1986835441
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1825435406
Short name T236
Test name
Test status
Simulation time 72525705 ps
CPU time 2.22 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 206136 kb
Host smart-af6b9a72-963e-4bb5-9270-5fb354234858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825435406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1825435406
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.630308532
Short name T255
Test name
Test status
Simulation time 15975961 ps
CPU time 0.97 seconds
Started Jun 02 02:43:26 PM PDT 24
Finished Jun 02 02:43:29 PM PDT 24
Peak memory 206716 kb
Host smart-0555a35f-5dde-4d54-a032-24cff60d224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630308532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.630308532
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/111.edn_genbits.3832254389
Short name T280
Test name
Test status
Simulation time 366621110 ps
CPU time 4.03 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 216904 kb
Host smart-61f0f179-054a-4143-8198-30ff79aa5e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832254389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.3832254389
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.3915665687
Short name T306
Test name
Test status
Simulation time 312831330 ps
CPU time 2.08 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:08 PM PDT 24
Peak memory 218108 kb
Host smart-45560550-134f-4369-8f56-72e012decdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915665687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3915665687
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2954121199
Short name T282
Test name
Test status
Simulation time 44120763 ps
CPU time 1.69 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:01 PM PDT 24
Peak memory 217972 kb
Host smart-4cf12ac6-8571-4452-90e9-3b8995f19c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954121199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2954121199
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3322754702
Short name T697
Test name
Test status
Simulation time 162366018 ps
CPU time 1.33 seconds
Started Jun 02 02:44:08 PM PDT 24
Finished Jun 02 02:44:10 PM PDT 24
Peak memory 215348 kb
Host smart-c2df72da-8860-4467-9e7e-b7d346d422a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322754702 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3322754702
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/13.edn_genbits.2312859451
Short name T27
Test name
Test status
Simulation time 43278731 ps
CPU time 1.49 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 216648 kb
Host smart-06d20ae3-0c2f-4d10-97f2-a9f6427ca5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312859451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2312859451
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3806864023
Short name T136
Test name
Test status
Simulation time 40096959 ps
CPU time 1.46 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 217948 kb
Host smart-0d4a4c4d-e478-482a-932b-a91c210e580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806864023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3806864023
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3009136361
Short name T269
Test name
Test status
Simulation time 43763185 ps
CPU time 1.44 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 218044 kb
Host smart-cff3167d-e618-4292-9050-d660651afae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009136361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3009136361
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3776330011
Short name T66
Test name
Test status
Simulation time 95699526 ps
CPU time 1.21 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 215360 kb
Host smart-b700af0b-8f6e-480c-9629-a65172feada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776330011 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3776330011
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/173.edn_genbits.1656592103
Short name T266
Test name
Test status
Simulation time 136309639 ps
CPU time 1 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 216624 kb
Host smart-a7d0b301-f7f0-49ce-94a8-ced1bc488431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656592103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1656592103
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.489377961
Short name T272
Test name
Test status
Simulation time 135104229 ps
CPU time 1.12 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 216920 kb
Host smart-c820cc28-2087-4bef-a403-85265d7160ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489377961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.489377961
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3994779719
Short name T277
Test name
Test status
Simulation time 35661003626 ps
CPU time 397.55 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:50:28 PM PDT 24
Peak memory 216236 kb
Host smart-86a18311-adbe-4449-8437-5928a9bac002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994779719 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3994779719
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/234.edn_genbits.2413650406
Short name T23
Test name
Test status
Simulation time 54746827 ps
CPU time 1.06 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 218188 kb
Host smart-66168e0f-2b80-4c9e-9d02-b6ecacd1c94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413650406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2413650406
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.517025108
Short name T261
Test name
Test status
Simulation time 110756526 ps
CPU time 1.44 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 218120 kb
Host smart-01ae3871-56b8-4ae4-b244-7b6a0e09c231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517025108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.517025108
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.702489220
Short name T152
Test name
Test status
Simulation time 23037031 ps
CPU time 1.18 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215312 kb
Host smart-a03a27e3-0423-428e-b7e3-6831eaf9e9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702489220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.702489220
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/8.edn_regwen.3469790950
Short name T259
Test name
Test status
Simulation time 28868740 ps
CPU time 1.03 seconds
Started Jun 02 02:44:11 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 206704 kb
Host smart-7e97a029-7d32-40f6-a07e-17d3df91b92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469790950 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3469790950
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1258902649
Short name T131
Test name
Test status
Simulation time 30336121655 ps
CPU time 378.3 seconds
Started Jun 02 02:44:05 PM PDT 24
Finished Jun 02 02:50:23 PM PDT 24
Peak memory 216284 kb
Host smart-7b8fc80e-5d47-45b9-ae7f-2f02ffd880a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258902649 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1258902649
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_intr.1711197245
Short name T143
Test name
Test status
Simulation time 21528777 ps
CPU time 1.08 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 215376 kb
Host smart-fb22f6cd-191c-4c7e-a045-cebb103cca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711197245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1711197245
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/1.edn_err.1383701525
Short name T44
Test name
Test status
Simulation time 23545883 ps
CPU time 1.22 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 219284 kb
Host smart-448c1b21-588f-4c2c-9838-f65f4530721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383701525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1383701525
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/224.edn_genbits.1336799300
Short name T121
Test name
Test status
Simulation time 257421872 ps
CPU time 2.13 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 217960 kb
Host smart-5b8600b2-2b48-4575-ad86-b341c7f7e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336799300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1336799300
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.585238672
Short name T898
Test name
Test status
Simulation time 45057005 ps
CPU time 1.13 seconds
Started Jun 02 02:13:43 PM PDT 24
Finished Jun 02 02:13:44 PM PDT 24
Peak memory 206080 kb
Host smart-6c160fdf-c1a0-4fa9-a5bd-2960fd8884ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585238672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.585238672
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3862581949
Short name T858
Test name
Test status
Simulation time 118239860 ps
CPU time 3.28 seconds
Started Jun 02 02:13:44 PM PDT 24
Finished Jun 02 02:13:48 PM PDT 24
Peak memory 206140 kb
Host smart-826aa9a0-54dc-42b5-9ac8-22919758b617
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862581949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3862581949
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2798879655
Short name T925
Test name
Test status
Simulation time 122861510 ps
CPU time 0.91 seconds
Started Jun 02 02:13:40 PM PDT 24
Finished Jun 02 02:13:41 PM PDT 24
Peak memory 206080 kb
Host smart-5594712f-5950-45cf-84cf-8cd1d741c868
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798879655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2798879655
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.860446188
Short name T936
Test name
Test status
Simulation time 66021157 ps
CPU time 1.54 seconds
Started Jun 02 02:13:43 PM PDT 24
Finished Jun 02 02:13:45 PM PDT 24
Peak memory 206268 kb
Host smart-f885d02b-0402-4c98-8b4d-21c36bd5f3f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860446188 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.860446188
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3455230969
Short name T206
Test name
Test status
Simulation time 17974381 ps
CPU time 1 seconds
Started Jun 02 02:13:37 PM PDT 24
Finished Jun 02 02:13:39 PM PDT 24
Peak memory 206124 kb
Host smart-3ba4f978-6064-4a69-aa3a-706f227c4a2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455230969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3455230969
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.920505609
Short name T935
Test name
Test status
Simulation time 13414842 ps
CPU time 0.88 seconds
Started Jun 02 02:13:39 PM PDT 24
Finished Jun 02 02:13:41 PM PDT 24
Peak memory 205872 kb
Host smart-0dea775c-754d-4fa5-8bd2-2521f64ce494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920505609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.920505609
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3199683784
Short name T926
Test name
Test status
Simulation time 58599993 ps
CPU time 1.17 seconds
Started Jun 02 02:13:46 PM PDT 24
Finished Jun 02 02:13:47 PM PDT 24
Peak memory 206088 kb
Host smart-50e62293-2656-40f1-9790-75e138a816d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199683784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3199683784
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3910176865
Short name T957
Test name
Test status
Simulation time 117433310 ps
CPU time 2.19 seconds
Started Jun 02 02:13:37 PM PDT 24
Finished Jun 02 02:13:39 PM PDT 24
Peak memory 214336 kb
Host smart-66d58d38-a534-4722-9661-d1b2499e5e63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910176865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3910176865
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1890099584
Short name T869
Test name
Test status
Simulation time 644369519 ps
CPU time 2.41 seconds
Started Jun 02 02:13:37 PM PDT 24
Finished Jun 02 02:13:40 PM PDT 24
Peak memory 214336 kb
Host smart-b9938f0a-7464-4794-af85-8baafed99b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890099584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1890099584
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1150246924
Short name T899
Test name
Test status
Simulation time 53385673 ps
CPU time 1.27 seconds
Started Jun 02 02:13:42 PM PDT 24
Finished Jun 02 02:13:44 PM PDT 24
Peak memory 206132 kb
Host smart-026b3233-e16a-450d-9515-20bd44c060c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150246924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1150246924
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.532820130
Short name T231
Test name
Test status
Simulation time 2757343258 ps
CPU time 6.47 seconds
Started Jun 02 02:13:44 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 206256 kb
Host smart-05ce7737-67c6-4c06-9f9f-13a62be5f22f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532820130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.532820130
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.157533754
Short name T954
Test name
Test status
Simulation time 46069056 ps
CPU time 0.91 seconds
Started Jun 02 02:13:42 PM PDT 24
Finished Jun 02 02:13:44 PM PDT 24
Peak memory 206068 kb
Host smart-63f962f6-8079-4f5b-a383-d51cd6d98934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157533754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.157533754
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2323596168
Short name T853
Test name
Test status
Simulation time 29172324 ps
CPU time 1.42 seconds
Started Jun 02 02:13:49 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 214416 kb
Host smart-89d3a72e-3655-437e-bc27-384b2e55de06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323596168 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2323596168
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4081520013
Short name T852
Test name
Test status
Simulation time 19559855 ps
CPU time 0.83 seconds
Started Jun 02 02:13:45 PM PDT 24
Finished Jun 02 02:13:46 PM PDT 24
Peak memory 205984 kb
Host smart-00b03959-899a-4592-9689-36464b0bad1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081520013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4081520013
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.778261989
Short name T843
Test name
Test status
Simulation time 35900079 ps
CPU time 0.84 seconds
Started Jun 02 02:13:48 PM PDT 24
Finished Jun 02 02:13:49 PM PDT 24
Peak memory 206000 kb
Host smart-6398c101-8d74-4e13-b9b1-4ce87d5a3b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778261989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.778261989
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3496087960
Short name T943
Test name
Test status
Simulation time 27823454 ps
CPU time 1.14 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 206152 kb
Host smart-b297baae-4d2e-476b-81ad-9411754feaca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496087960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3496087960
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1197724530
Short name T916
Test name
Test status
Simulation time 90242669 ps
CPU time 2.26 seconds
Started Jun 02 02:13:48 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 214352 kb
Host smart-128c66c6-4e45-4223-a718-7e9963fd28ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197724530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1197724530
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3048882168
Short name T979
Test name
Test status
Simulation time 667100006 ps
CPU time 1.62 seconds
Started Jun 02 02:13:45 PM PDT 24
Finished Jun 02 02:13:47 PM PDT 24
Peak memory 206084 kb
Host smart-1067f984-1eeb-41da-948d-5ee4a24c9db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048882168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3048882168
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.914487174
Short name T848
Test name
Test status
Simulation time 43851897 ps
CPU time 1.25 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 214452 kb
Host smart-e029fef0-d508-4a2b-8613-9ac648ff8ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914487174 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.914487174
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2882176208
Short name T934
Test name
Test status
Simulation time 20647537 ps
CPU time 0.94 seconds
Started Jun 02 02:14:11 PM PDT 24
Finished Jun 02 02:14:13 PM PDT 24
Peak memory 206128 kb
Host smart-de28192e-1d31-41b4-9cf2-d3311da2db76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882176208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2882176208
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1703426834
Short name T847
Test name
Test status
Simulation time 16030345 ps
CPU time 0.96 seconds
Started Jun 02 02:14:10 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 206056 kb
Host smart-da3042f1-aae6-442e-9c47-93c2466da75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703426834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1703426834
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3446337614
Short name T969
Test name
Test status
Simulation time 30635860 ps
CPU time 1.39 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 206140 kb
Host smart-b949dbbf-5b92-4f31-a3f7-0d6f2d8ce480
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446337614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3446337614
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1452638727
Short name T889
Test name
Test status
Simulation time 21535706 ps
CPU time 1.54 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 222612 kb
Host smart-dd609b33-a38c-4218-8b5e-ed6a189b37ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452638727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1452638727
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3745607986
Short name T964
Test name
Test status
Simulation time 87223454 ps
CPU time 2.55 seconds
Started Jun 02 02:14:10 PM PDT 24
Finished Jun 02 02:14:13 PM PDT 24
Peak memory 214316 kb
Host smart-9588c61e-7dd9-4417-8942-43af0c690ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745607986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3745607986
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2819874036
Short name T906
Test name
Test status
Simulation time 41336522 ps
CPU time 1.82 seconds
Started Jun 02 02:14:14 PM PDT 24
Finished Jun 02 02:14:16 PM PDT 24
Peak memory 214424 kb
Host smart-83a442c4-2d0d-4806-9c38-b745e62a834d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819874036 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2819874036
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2536534495
Short name T892
Test name
Test status
Simulation time 17830587 ps
CPU time 0.78 seconds
Started Jun 02 02:14:11 PM PDT 24
Finished Jun 02 02:14:12 PM PDT 24
Peak memory 205920 kb
Host smart-a1fb794e-69de-4735-8b89-205190b28aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536534495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2536534495
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3726963107
Short name T212
Test name
Test status
Simulation time 36546584 ps
CPU time 0.9 seconds
Started Jun 02 02:14:17 PM PDT 24
Finished Jun 02 02:14:19 PM PDT 24
Peak memory 206088 kb
Host smart-e6bffd3b-83f6-4388-af31-2308006b02b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726963107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3726963107
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1552567884
Short name T974
Test name
Test status
Simulation time 81641747 ps
CPU time 3.22 seconds
Started Jun 02 02:14:12 PM PDT 24
Finished Jun 02 02:14:16 PM PDT 24
Peak memory 214304 kb
Host smart-ec975140-a8ba-4080-893c-4e3a675cd1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552567884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1552567884
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3902986656
Short name T232
Test name
Test status
Simulation time 53357528 ps
CPU time 1.76 seconds
Started Jun 02 02:14:07 PM PDT 24
Finished Jun 02 02:14:09 PM PDT 24
Peak memory 214332 kb
Host smart-fb911ff1-c30c-4821-b278-e0f5fb4bef06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902986656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3902986656
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.718629740
Short name T929
Test name
Test status
Simulation time 26067350 ps
CPU time 1.45 seconds
Started Jun 02 02:14:17 PM PDT 24
Finished Jun 02 02:14:19 PM PDT 24
Peak memory 214388 kb
Host smart-20f593c5-c3b7-416e-bc5a-78bf5b0043d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718629740 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.718629740
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3094454965
Short name T210
Test name
Test status
Simulation time 47401406 ps
CPU time 0.8 seconds
Started Jun 02 02:14:15 PM PDT 24
Finished Jun 02 02:14:17 PM PDT 24
Peak memory 205964 kb
Host smart-971e397e-fafb-4879-b350-50748029fef5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094454965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3094454965
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2456746399
Short name T862
Test name
Test status
Simulation time 45703485 ps
CPU time 0.85 seconds
Started Jun 02 02:14:17 PM PDT 24
Finished Jun 02 02:14:18 PM PDT 24
Peak memory 206012 kb
Host smart-18293b3c-42e9-40cb-b998-2177982686d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456746399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2456746399
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4072439700
Short name T867
Test name
Test status
Simulation time 327385847 ps
CPU time 1.39 seconds
Started Jun 02 02:14:14 PM PDT 24
Finished Jun 02 02:14:16 PM PDT 24
Peak memory 206416 kb
Host smart-8b0775e4-4e4c-4fbc-9ac3-74d6067b0209
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072439700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.4072439700
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1390468685
Short name T893
Test name
Test status
Simulation time 111866752 ps
CPU time 2 seconds
Started Jun 02 02:14:16 PM PDT 24
Finished Jun 02 02:14:18 PM PDT 24
Peak memory 214344 kb
Host smart-4760920a-e2ed-4627-9675-3dbabc28fb56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390468685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1390468685
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2770171766
Short name T946
Test name
Test status
Simulation time 417489303 ps
CPU time 1.73 seconds
Started Jun 02 02:14:16 PM PDT 24
Finished Jun 02 02:14:18 PM PDT 24
Peak memory 206140 kb
Host smart-298808d7-e0e2-44d3-b961-0cd0bd92607d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770171766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2770171766
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2617514952
Short name T909
Test name
Test status
Simulation time 56174592 ps
CPU time 1.07 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206212 kb
Host smart-b5920255-ee6b-45c3-8a97-a75ab3436eba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617514952 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2617514952
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3729944670
Short name T922
Test name
Test status
Simulation time 44927052 ps
CPU time 0.92 seconds
Started Jun 02 02:14:15 PM PDT 24
Finished Jun 02 02:14:16 PM PDT 24
Peak memory 206120 kb
Host smart-22aecc67-9946-498c-84ae-3a8d878bd122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729944670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3729944670
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2686365640
Short name T894
Test name
Test status
Simulation time 48790622 ps
CPU time 0.81 seconds
Started Jun 02 02:14:15 PM PDT 24
Finished Jun 02 02:14:17 PM PDT 24
Peak memory 205924 kb
Host smart-f328cb2e-129b-455d-9747-b7c0ed920c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686365640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2686365640
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.861080131
Short name T978
Test name
Test status
Simulation time 22472368 ps
CPU time 1.17 seconds
Started Jun 02 02:14:17 PM PDT 24
Finished Jun 02 02:14:19 PM PDT 24
Peak memory 206208 kb
Host smart-235e609e-9420-4fa7-8c70-2675b7477797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861080131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.861080131
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1163657162
Short name T940
Test name
Test status
Simulation time 24659626 ps
CPU time 1.8 seconds
Started Jun 02 02:14:15 PM PDT 24
Finished Jun 02 02:14:18 PM PDT 24
Peak memory 214316 kb
Host smart-8ba8c043-a714-4cba-acb3-b0902c1f9d1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163657162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1163657162
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.991983811
Short name T939
Test name
Test status
Simulation time 41960692 ps
CPU time 1.57 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 214344 kb
Host smart-5ec73390-e7ed-4df2-92a5-8b1f205dfcd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991983811 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.991983811
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2206637893
Short name T222
Test name
Test status
Simulation time 26748924 ps
CPU time 0.9 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206068 kb
Host smart-b4539d4a-d8c9-41f7-b207-6392bb7c70ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206637893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2206637893
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3553091838
Short name T857
Test name
Test status
Simulation time 60492728 ps
CPU time 0.99 seconds
Started Jun 02 02:14:22 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 206012 kb
Host smart-4a17613f-e4db-407a-a28b-0bd2e48107f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553091838 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3553091838
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2113132275
Short name T220
Test name
Test status
Simulation time 155297733 ps
CPU time 1.34 seconds
Started Jun 02 02:14:22 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 206204 kb
Host smart-b77d66a3-4c0b-4a16-bb4e-00e1dc4917c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113132275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2113132275
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.243559213
Short name T885
Test name
Test status
Simulation time 387854625 ps
CPU time 3.67 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:25 PM PDT 24
Peak memory 214328 kb
Host smart-2988eb16-80a0-4c62-b793-59d102c12668
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243559213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.243559213
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1132937686
Short name T937
Test name
Test status
Simulation time 330187100 ps
CPU time 2.53 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206164 kb
Host smart-744e1f47-1af3-455e-8262-97bb95b5ca75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132937686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1132937686
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2758021653
Short name T941
Test name
Test status
Simulation time 14607037 ps
CPU time 1.01 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206232 kb
Host smart-3b1348d0-993c-4335-836b-c61f01a47b41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758021653 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2758021653
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1220171563
Short name T219
Test name
Test status
Simulation time 37331279 ps
CPU time 0.93 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:34 PM PDT 24
Peak memory 206128 kb
Host smart-9e9b171f-44ed-48fa-a067-2f4be226cd8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220171563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1220171563
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3283485100
Short name T914
Test name
Test status
Simulation time 24348143 ps
CPU time 0.85 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206056 kb
Host smart-6b402bca-3b9e-4c5a-9130-29ce6b94ae60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283485100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3283485100
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.4069598676
Short name T895
Test name
Test status
Simulation time 25012334 ps
CPU time 1.13 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 206148 kb
Host smart-7da585e6-c461-43d2-b336-50d3d87c960b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069598676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.4069598676
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1960730904
Short name T942
Test name
Test status
Simulation time 386042304 ps
CPU time 3.97 seconds
Started Jun 02 02:14:19 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 214404 kb
Host smart-b9b5f3d3-2d2b-4891-83d0-fbaec7f5a700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960730904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1960730904
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1141901013
Short name T849
Test name
Test status
Simulation time 14937442 ps
CPU time 1.04 seconds
Started Jun 02 02:14:22 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 215728 kb
Host smart-db7486b0-b0e8-4db6-a846-8f2e0719f8b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141901013 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1141901013
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3774156538
Short name T963
Test name
Test status
Simulation time 25155205 ps
CPU time 0.9 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 206144 kb
Host smart-6ae02508-dd71-4335-976f-6e02c08de278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774156538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3774156538
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1746314135
Short name T877
Test name
Test status
Simulation time 15554800 ps
CPU time 0.89 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:23 PM PDT 24
Peak memory 206008 kb
Host smart-86fd25cc-d950-4ecd-abfe-f43a153ee322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746314135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1746314135
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1123052779
Short name T910
Test name
Test status
Simulation time 52096690 ps
CPU time 0.95 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:32 PM PDT 24
Peak memory 206196 kb
Host smart-e7168777-fa9b-4480-9203-a9e0f239db28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123052779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1123052779
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1788930331
Short name T876
Test name
Test status
Simulation time 100364204 ps
CPU time 2.16 seconds
Started Jun 02 02:14:19 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 214416 kb
Host smart-55e07ae6-b530-493d-a502-005d866b29e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788930331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1788930331
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1566696997
Short name T930
Test name
Test status
Simulation time 47743133 ps
CPU time 1.63 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 206136 kb
Host smart-1703269a-c3ab-4d1d-bf03-9a0727fe75ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566696997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1566696997
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3472583870
Short name T864
Test name
Test status
Simulation time 96144673 ps
CPU time 1.74 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 214444 kb
Host smart-dad90e3a-fbc4-4b67-8b52-855f46dd1b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472583870 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3472583870
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3719844935
Short name T214
Test name
Test status
Simulation time 29384548 ps
CPU time 0.9 seconds
Started Jun 02 02:14:21 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 206116 kb
Host smart-7f1a3916-2bd4-45d3-bfa3-10aab863bdde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719844935 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3719844935
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.144872573
Short name T866
Test name
Test status
Simulation time 31106569 ps
CPU time 0.83 seconds
Started Jun 02 02:14:19 PM PDT 24
Finished Jun 02 02:14:20 PM PDT 24
Peak memory 205864 kb
Host smart-dfe70a45-43bc-49e0-9bc2-0a169b895f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144872573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.144872573
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.561598491
Short name T221
Test name
Test status
Simulation time 59772642 ps
CPU time 1.36 seconds
Started Jun 02 02:14:22 PM PDT 24
Finished Jun 02 02:14:24 PM PDT 24
Peak memory 206176 kb
Host smart-dd55187a-24ef-4207-b69c-02b8e99ec6c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561598491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.561598491
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.222585668
Short name T902
Test name
Test status
Simulation time 89767690 ps
CPU time 1.95 seconds
Started Jun 02 02:14:19 PM PDT 24
Finished Jun 02 02:14:21 PM PDT 24
Peak memory 214284 kb
Host smart-f9059b92-48da-4305-b6d2-e072dbefaa88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222585668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.222585668
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2430337255
Short name T960
Test name
Test status
Simulation time 48844760 ps
CPU time 1.62 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 214676 kb
Host smart-b7ffc1e3-c17b-4b2f-8a10-4ad29bed02bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430337255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2430337255
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3205746281
Short name T896
Test name
Test status
Simulation time 76265187 ps
CPU time 1.24 seconds
Started Jun 02 02:14:28 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 214352 kb
Host smart-6b028330-6150-4bd6-b6a6-b45e8c830273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205746281 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3205746281
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.303534648
Short name T209
Test name
Test status
Simulation time 15736377 ps
CPU time 0.91 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 206128 kb
Host smart-b0bc1591-1213-445e-8936-89d6c055c181
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303534648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.303534648
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2384745548
Short name T919
Test name
Test status
Simulation time 24364502 ps
CPU time 0.9 seconds
Started Jun 02 02:14:20 PM PDT 24
Finished Jun 02 02:14:22 PM PDT 24
Peak memory 206008 kb
Host smart-c1ad339e-c935-4055-85bc-6b3597dd84be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384745548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2384745548
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2523462772
Short name T218
Test name
Test status
Simulation time 107658673 ps
CPU time 1.28 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206136 kb
Host smart-1507e2f1-e499-4fc2-806b-cfdd887a00d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523462772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2523462772
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1239184126
Short name T959
Test name
Test status
Simulation time 264814174 ps
CPU time 2.84 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 214340 kb
Host smart-3425bd14-1e42-4cdf-839a-9f7b8350c53f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239184126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1239184126
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3898114509
Short name T239
Test name
Test status
Simulation time 196577277 ps
CPU time 1.63 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:34 PM PDT 24
Peak memory 206448 kb
Host smart-8064a8f9-82ac-4687-8a94-67eb53ac4d86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898114509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3898114509
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3513828497
Short name T924
Test name
Test status
Simulation time 44123687 ps
CPU time 1.5 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:28 PM PDT 24
Peak memory 217936 kb
Host smart-096cd344-a8c5-4117-acb9-5d5e13a155d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513828497 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3513828497
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3520928200
Short name T944
Test name
Test status
Simulation time 57116618 ps
CPU time 0.86 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206028 kb
Host smart-103c0939-17ee-4f9a-aef4-5450dbdbb057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520928200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3520928200
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.187645072
Short name T855
Test name
Test status
Simulation time 50054301 ps
CPU time 0.96 seconds
Started Jun 02 02:14:27 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 205924 kb
Host smart-6738d509-63c0-405b-b6c9-38c3a4e8672f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187645072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.187645072
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2637808312
Short name T945
Test name
Test status
Simulation time 182703030 ps
CPU time 1.15 seconds
Started Jun 02 02:14:28 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 206116 kb
Host smart-2e9a3c25-f9ea-41ec-a018-684294f34e4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637808312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2637808312
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3085421763
Short name T932
Test name
Test status
Simulation time 22091452 ps
CPU time 1.57 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 214384 kb
Host smart-7ea57776-b331-405c-8009-e5d4e03067ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085421763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3085421763
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1997364943
Short name T901
Test name
Test status
Simulation time 94409078 ps
CPU time 2.64 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 214392 kb
Host smart-94198fae-88d1-4dac-a6ce-7fc952319fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997364943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1997364943
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4201171366
Short name T886
Test name
Test status
Simulation time 41472684 ps
CPU time 1.22 seconds
Started Jun 02 02:13:48 PM PDT 24
Finished Jun 02 02:13:50 PM PDT 24
Peak memory 206100 kb
Host smart-78d4cc04-7138-45b1-9ffa-8ca7fc8e064f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201171366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4201171366
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1487953981
Short name T908
Test name
Test status
Simulation time 351391155 ps
CPU time 5.18 seconds
Started Jun 02 02:13:49 PM PDT 24
Finished Jun 02 02:13:54 PM PDT 24
Peak memory 206212 kb
Host smart-4839b0ec-2277-46c1-8c2e-da5eba762b32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487953981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1487953981
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4155058794
Short name T874
Test name
Test status
Simulation time 112545961 ps
CPU time 1.92 seconds
Started Jun 02 02:13:54 PM PDT 24
Finished Jun 02 02:13:56 PM PDT 24
Peak memory 218936 kb
Host smart-3fc435db-9259-488f-b0ba-de5ca0290512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155058794 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4155058794
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3259855016
Short name T900
Test name
Test status
Simulation time 43404812 ps
CPU time 0.88 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 206064 kb
Host smart-4850f166-0dff-404c-9991-c3d9e23bd539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259855016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3259855016
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2602444609
Short name T948
Test name
Test status
Simulation time 28082755 ps
CPU time 0.96 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:51 PM PDT 24
Peak memory 206008 kb
Host smart-7f824ffe-4b22-4a77-9b4e-3a068c12eaa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602444609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2602444609
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3342623480
Short name T903
Test name
Test status
Simulation time 20847004 ps
CPU time 0.95 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:52 PM PDT 24
Peak memory 206140 kb
Host smart-3bf5c014-476d-47d8-96cd-1b408c9227a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342623480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3342623480
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2582422197
Short name T897
Test name
Test status
Simulation time 182406176 ps
CPU time 3.43 seconds
Started Jun 02 02:13:49 PM PDT 24
Finished Jun 02 02:13:53 PM PDT 24
Peak memory 218472 kb
Host smart-5806b831-e552-41b7-b0de-c5b707197850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582422197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2582422197
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3300086500
Short name T911
Test name
Test status
Simulation time 282822202 ps
CPU time 2.47 seconds
Started Jun 02 02:13:50 PM PDT 24
Finished Jun 02 02:13:54 PM PDT 24
Peak memory 206168 kb
Host smart-4cff4abb-41e5-42af-be79-c262804f03a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300086500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3300086500
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.414991477
Short name T976
Test name
Test status
Simulation time 41582533 ps
CPU time 0.86 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206000 kb
Host smart-0d0d3a93-07ac-441e-b4d0-35f9af0b3498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414991477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.414991477
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2359639235
Short name T918
Test name
Test status
Simulation time 49788552 ps
CPU time 0.88 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206044 kb
Host smart-0189807b-ec0a-4013-842e-06a40f6a1345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359639235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2359639235
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2291744160
Short name T851
Test name
Test status
Simulation time 18600073 ps
CPU time 0.84 seconds
Started Jun 02 02:14:28 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 205968 kb
Host smart-07295a91-21ee-4e4a-a261-0a7c5e38fcb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291744160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2291744160
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1316252404
Short name T971
Test name
Test status
Simulation time 58974932 ps
CPU time 0.9 seconds
Started Jun 02 02:14:38 PM PDT 24
Finished Jun 02 02:14:39 PM PDT 24
Peak memory 206012 kb
Host smart-c9f0ad49-ca22-416a-9c96-9b37653ed827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316252404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1316252404
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.2618910272
Short name T844
Test name
Test status
Simulation time 74657490 ps
CPU time 0.85 seconds
Started Jun 02 02:14:27 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 205920 kb
Host smart-e023b596-adc0-44aa-88c8-2e8ef22a03af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618910272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.2618910272
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1679919980
Short name T972
Test name
Test status
Simulation time 43034902 ps
CPU time 0.84 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 205960 kb
Host smart-e1f15c4a-387f-416a-8a4b-00085ba0cf64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679919980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1679919980
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1457666151
Short name T856
Test name
Test status
Simulation time 12363522 ps
CPU time 0.85 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206016 kb
Host smart-046149a7-d837-4502-895d-205c9f703544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457666151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1457666151
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1098083571
Short name T915
Test name
Test status
Simulation time 32754189 ps
CPU time 0.95 seconds
Started Jun 02 02:14:27 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 206008 kb
Host smart-cc2bec6e-c9ce-4b4f-9f0f-6d4187a6a899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098083571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1098083571
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.286800077
Short name T890
Test name
Test status
Simulation time 15509040 ps
CPU time 0.91 seconds
Started Jun 02 02:14:29 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 205952 kb
Host smart-40033954-5a8f-4521-a6de-cb12e24a462b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286800077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.286800077
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2869706820
Short name T928
Test name
Test status
Simulation time 16738938 ps
CPU time 0.9 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206076 kb
Host smart-e3bcbeec-045a-46c9-a018-bf8bca748390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869706820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2869706820
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1214666220
Short name T211
Test name
Test status
Simulation time 64081828 ps
CPU time 1.27 seconds
Started Jun 02 02:13:54 PM PDT 24
Finished Jun 02 02:13:55 PM PDT 24
Peak memory 206192 kb
Host smart-7c4904f8-224d-4e40-b3b0-7ec46dfcf215
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214666220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1214666220
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.270397201
Short name T860
Test name
Test status
Simulation time 583738168 ps
CPU time 3.31 seconds
Started Jun 02 02:13:54 PM PDT 24
Finished Jun 02 02:13:58 PM PDT 24
Peak memory 206104 kb
Host smart-7236e270-ac23-4eb4-8fab-9de2e0ed745d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270397201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.270397201
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2283053263
Short name T949
Test name
Test status
Simulation time 21135706 ps
CPU time 0.9 seconds
Started Jun 02 02:13:52 PM PDT 24
Finished Jun 02 02:13:53 PM PDT 24
Peak memory 206136 kb
Host smart-eb88515f-a7ae-4772-9947-3f19d687fd2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283053263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2283053263
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2200826098
Short name T938
Test name
Test status
Simulation time 86998758 ps
CPU time 1.8 seconds
Started Jun 02 02:13:53 PM PDT 24
Finished Jun 02 02:13:55 PM PDT 24
Peak memory 214468 kb
Host smart-e6c47f5a-42b3-4149-987f-64a1c2b68c8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200826098 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2200826098
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2402927484
Short name T966
Test name
Test status
Simulation time 14809404 ps
CPU time 0.88 seconds
Started Jun 02 02:13:58 PM PDT 24
Finished Jun 02 02:13:59 PM PDT 24
Peak memory 206092 kb
Host smart-813826bc-0d98-4d5f-87bb-0e00f96a5cdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402927484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2402927484
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3015353273
Short name T870
Test name
Test status
Simulation time 187926171 ps
CPU time 0.88 seconds
Started Jun 02 02:13:54 PM PDT 24
Finished Jun 02 02:13:55 PM PDT 24
Peak memory 206000 kb
Host smart-ab0b075b-604b-4f06-bf99-9bbb8f849c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015353273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3015353273
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.390625028
Short name T883
Test name
Test status
Simulation time 29395955 ps
CPU time 1.11 seconds
Started Jun 02 02:13:53 PM PDT 24
Finished Jun 02 02:13:55 PM PDT 24
Peak memory 206164 kb
Host smart-962b09aa-25b1-4b02-b405-5ac1e500d994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390625028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.390625028
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2997045122
Short name T912
Test name
Test status
Simulation time 71971005 ps
CPU time 2.51 seconds
Started Jun 02 02:13:58 PM PDT 24
Finished Jun 02 02:14:01 PM PDT 24
Peak memory 214392 kb
Host smart-70ef84ad-59e5-4636-b9ae-9cd493d04125
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997045122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2997045122
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2987142474
Short name T233
Test name
Test status
Simulation time 39154253 ps
CPU time 1.54 seconds
Started Jun 02 02:13:55 PM PDT 24
Finished Jun 02 02:13:57 PM PDT 24
Peak memory 206120 kb
Host smart-e0db53e8-4f66-488c-a9ce-9c30a960bc62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987142474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2987142474
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1824274265
Short name T859
Test name
Test status
Simulation time 38843865 ps
CPU time 0.82 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 205916 kb
Host smart-48551467-e714-4964-af85-e5835efde35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824274265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1824274265
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3751024329
Short name T961
Test name
Test status
Simulation time 23058872 ps
CPU time 0.89 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:27 PM PDT 24
Peak memory 206008 kb
Host smart-5abce584-7ce8-4362-93a4-2dc68177ce42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751024329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3751024329
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.936724293
Short name T879
Test name
Test status
Simulation time 15609279 ps
CPU time 0.96 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:28 PM PDT 24
Peak memory 206000 kb
Host smart-daf921f9-1f4e-47d5-8216-da6edb211ed4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936724293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.936724293
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.468608414
Short name T881
Test name
Test status
Simulation time 68832033 ps
CPU time 0.85 seconds
Started Jun 02 02:14:26 PM PDT 24
Finished Jun 02 02:14:28 PM PDT 24
Peak memory 206000 kb
Host smart-112d7673-03db-438a-ada1-93b7eab98c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468608414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.468608414
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3555253773
Short name T962
Test name
Test status
Simulation time 24694179 ps
CPU time 0.89 seconds
Started Jun 02 02:14:28 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 205944 kb
Host smart-faa8b24a-9105-4506-931a-b6a22c9fad36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555253773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3555253773
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2696915695
Short name T913
Test name
Test status
Simulation time 17948666 ps
CPU time 0.85 seconds
Started Jun 02 02:14:25 PM PDT 24
Finished Jun 02 02:14:26 PM PDT 24
Peak memory 205996 kb
Host smart-efdedc99-3af4-41aa-9ea8-28e3bd77f2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696915695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2696915695
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2580182584
Short name T861
Test name
Test status
Simulation time 44760182 ps
CPU time 0.89 seconds
Started Jun 02 02:14:27 PM PDT 24
Finished Jun 02 02:14:29 PM PDT 24
Peak memory 206012 kb
Host smart-5b895857-7963-493e-890c-184192fcb44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580182584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2580182584
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.618069290
Short name T950
Test name
Test status
Simulation time 37960257 ps
CPU time 0.79 seconds
Started Jun 02 02:14:28 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 205928 kb
Host smart-a0d45d37-c5ca-4fb6-a667-a2b0882154e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618069290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.618069290
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1449898701
Short name T920
Test name
Test status
Simulation time 13149700 ps
CPU time 0.92 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:31 PM PDT 24
Peak memory 205964 kb
Host smart-0766157c-85fc-4b48-84cb-c566f1246f16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449898701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1449898701
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1147514238
Short name T951
Test name
Test status
Simulation time 51619018 ps
CPU time 0.91 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:32 PM PDT 24
Peak memory 206012 kb
Host smart-0259daca-4383-48ef-91c0-f8e8a0827a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147514238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1147514238
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.3423452393
Short name T213
Test name
Test status
Simulation time 78351524 ps
CPU time 1.52 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:02 PM PDT 24
Peak memory 206136 kb
Host smart-4e1ee9bd-9cd4-41dc-b152-d3bad6e1c85c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423452393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.3423452393
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.135463137
Short name T958
Test name
Test status
Simulation time 223001024 ps
CPU time 6.4 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:06 PM PDT 24
Peak memory 206192 kb
Host smart-85a913cd-749d-4c5a-a447-4563749f18a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135463137 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.135463137
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.639934528
Short name T933
Test name
Test status
Simulation time 38217838 ps
CPU time 0.9 seconds
Started Jun 02 02:13:55 PM PDT 24
Finished Jun 02 02:13:57 PM PDT 24
Peak memory 206028 kb
Host smart-a39fcd38-3450-4959-9400-826bcf652126
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639934528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.639934528
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3935734150
Short name T873
Test name
Test status
Simulation time 178096056 ps
CPU time 1.01 seconds
Started Jun 02 02:14:02 PM PDT 24
Finished Jun 02 02:14:04 PM PDT 24
Peak memory 206212 kb
Host smart-bf257a29-ce7a-4389-8ce7-aee255027dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935734150 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3935734150
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.535538509
Short name T977
Test name
Test status
Simulation time 24665458 ps
CPU time 0.89 seconds
Started Jun 02 02:13:58 PM PDT 24
Finished Jun 02 02:13:59 PM PDT 24
Peak memory 206100 kb
Host smart-6e9f4dc2-5e67-4034-ac7d-77643d852416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535538509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.535538509
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.250781065
Short name T887
Test name
Test status
Simulation time 19594807 ps
CPU time 0.95 seconds
Started Jun 02 02:13:54 PM PDT 24
Finished Jun 02 02:13:55 PM PDT 24
Peak memory 206004 kb
Host smart-55db7b83-32bb-4a00-b8f6-d9ccfa4899bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250781065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.250781065
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2190284444
Short name T980
Test name
Test status
Simulation time 62823978 ps
CPU time 1.13 seconds
Started Jun 02 02:14:03 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206176 kb
Host smart-a572291e-a91f-426b-b80e-05219d898713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190284444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2190284444
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2309089474
Short name T865
Test name
Test status
Simulation time 478844620 ps
CPU time 4.43 seconds
Started Jun 02 02:13:58 PM PDT 24
Finished Jun 02 02:14:03 PM PDT 24
Peak memory 214412 kb
Host smart-597d4be5-b398-4d61-af83-7d2a085535ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309089474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2309089474
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.704619699
Short name T235
Test name
Test status
Simulation time 155738363 ps
CPU time 2.12 seconds
Started Jun 02 02:13:56 PM PDT 24
Finished Jun 02 02:13:58 PM PDT 24
Peak memory 214412 kb
Host smart-b887ac0f-c241-4013-bc65-098fa2b45519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704619699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.704619699
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1943864924
Short name T891
Test name
Test status
Simulation time 19965484 ps
CPU time 0.83 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 205868 kb
Host smart-2dc2561d-d1ab-406e-9e6b-54d4bcab52d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943864924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1943864924
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.459881925
Short name T956
Test name
Test status
Simulation time 49282052 ps
CPU time 0.92 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:32 PM PDT 24
Peak memory 206000 kb
Host smart-200ca29e-3016-4736-92b6-2ee60ce69232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459881925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.459881925
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1514635749
Short name T868
Test name
Test status
Simulation time 11450908 ps
CPU time 0.92 seconds
Started Jun 02 02:14:31 PM PDT 24
Finished Jun 02 02:14:32 PM PDT 24
Peak memory 206012 kb
Host smart-0586d55d-3c78-4acb-ab3b-2cf0216b94e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514635749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1514635749
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2029856875
Short name T845
Test name
Test status
Simulation time 21557805 ps
CPU time 0.82 seconds
Started Jun 02 02:14:29 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 205932 kb
Host smart-a77f31d8-84d3-4803-9213-95261b2da9fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029856875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2029856875
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3748388937
Short name T975
Test name
Test status
Simulation time 15928893 ps
CPU time 0.95 seconds
Started Jun 02 02:14:30 PM PDT 24
Finished Jun 02 02:14:31 PM PDT 24
Peak memory 205976 kb
Host smart-5d9bf214-5398-4388-87fc-0e125c3a3243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748388937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3748388937
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1511642474
Short name T850
Test name
Test status
Simulation time 19181806 ps
CPU time 0.84 seconds
Started Jun 02 02:14:29 PM PDT 24
Finished Jun 02 02:14:31 PM PDT 24
Peak memory 205924 kb
Host smart-7109d9fe-7c69-48b3-9edd-413e158aa032
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511642474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1511642474
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2754815287
Short name T921
Test name
Test status
Simulation time 107656805 ps
CPU time 0.81 seconds
Started Jun 02 02:14:32 PM PDT 24
Finished Jun 02 02:14:33 PM PDT 24
Peak memory 205880 kb
Host smart-eb517928-56b2-4aef-a391-b4d7cd1bef07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754815287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2754815287
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.206237169
Short name T952
Test name
Test status
Simulation time 41601478 ps
CPU time 0.87 seconds
Started Jun 02 02:14:29 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 206004 kb
Host smart-2c467180-ec68-4965-af23-9b8bc53f605d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206237169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.206237169
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.319882393
Short name T970
Test name
Test status
Simulation time 13735082 ps
CPU time 0.91 seconds
Started Jun 02 02:14:29 PM PDT 24
Finished Jun 02 02:14:30 PM PDT 24
Peak memory 206008 kb
Host smart-7e5c18df-b963-4ce1-b553-d412714f5706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319882393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.319882393
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1520052010
Short name T878
Test name
Test status
Simulation time 25196766 ps
CPU time 0.93 seconds
Started Jun 02 02:14:34 PM PDT 24
Finished Jun 02 02:14:35 PM PDT 24
Peak memory 205988 kb
Host smart-4e32ec61-6561-41cb-a27c-14a2db92f4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520052010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1520052010
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3168728537
Short name T955
Test name
Test status
Simulation time 62685749 ps
CPU time 1.53 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:02 PM PDT 24
Peak memory 214472 kb
Host smart-c7ad073d-f947-4505-9de2-001717d192eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168728537 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3168728537
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3716331929
Short name T217
Test name
Test status
Simulation time 22216419 ps
CPU time 0.85 seconds
Started Jun 02 02:13:58 PM PDT 24
Finished Jun 02 02:14:00 PM PDT 24
Peak memory 206144 kb
Host smart-628b2078-61ec-459c-84f0-b10dfaa6b3b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716331929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3716331929
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2216051356
Short name T880
Test name
Test status
Simulation time 14790093 ps
CPU time 0.88 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:02 PM PDT 24
Peak memory 205956 kb
Host smart-ba20dd6b-0eda-43e9-8a05-03a7ce2674a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216051356 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2216051356
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2651266461
Short name T223
Test name
Test status
Simulation time 19612392 ps
CPU time 1.25 seconds
Started Jun 02 02:13:59 PM PDT 24
Finished Jun 02 02:14:01 PM PDT 24
Peak memory 206144 kb
Host smart-d5f07a54-8890-45e4-a230-effa7eebc77b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651266461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2651266461
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1658851499
Short name T871
Test name
Test status
Simulation time 329410816 ps
CPU time 3.09 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:04 PM PDT 24
Peak memory 222468 kb
Host smart-a71ec5c2-33e3-4b1f-9003-e7e6de06a9b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658851499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1658851499
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3754729147
Short name T237
Test name
Test status
Simulation time 111142475 ps
CPU time 2.26 seconds
Started Jun 02 02:14:02 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206160 kb
Host smart-b9e2aa16-9751-4b59-9167-529d5f42d9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754729147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3754729147
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3915604654
Short name T854
Test name
Test status
Simulation time 61635962 ps
CPU time 2.09 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:02 PM PDT 24
Peak memory 214420 kb
Host smart-eb13e648-44fa-4ac4-af47-18460f8a10a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915604654 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3915604654
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.18754497
Short name T931
Test name
Test status
Simulation time 17211257 ps
CPU time 1.01 seconds
Started Jun 02 02:14:00 PM PDT 24
Finished Jun 02 02:14:02 PM PDT 24
Peak memory 206084 kb
Host smart-a0263d06-e45c-4d66-ab02-bc1111a5174a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18754497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.18754497
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.212138456
Short name T863
Test name
Test status
Simulation time 11935569 ps
CPU time 0.88 seconds
Started Jun 02 02:13:59 PM PDT 24
Finished Jun 02 02:14:00 PM PDT 24
Peak memory 205948 kb
Host smart-3969c709-e689-45dc-844f-6297e459ec3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212138456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.212138456
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.922420258
Short name T973
Test name
Test status
Simulation time 17971687 ps
CPU time 1.15 seconds
Started Jun 02 02:14:04 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206132 kb
Host smart-b8029ef7-7de2-4412-8a80-a60256ddb7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922420258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.922420258
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.322361803
Short name T965
Test name
Test status
Simulation time 207268843 ps
CPU time 1.85 seconds
Started Jun 02 02:14:03 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 222464 kb
Host smart-871a5290-1c1e-4cc7-89dd-b3303f681296
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322361803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.322361803
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2823311386
Short name T884
Test name
Test status
Simulation time 85451922 ps
CPU time 1.62 seconds
Started Jun 02 02:14:03 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206348 kb
Host smart-e9b1eb0c-bcbb-46d4-b23d-4768f8976184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823311386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2823311386
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2815466100
Short name T968
Test name
Test status
Simulation time 66071011 ps
CPU time 1.39 seconds
Started Jun 02 02:14:05 PM PDT 24
Finished Jun 02 02:14:06 PM PDT 24
Peak memory 214444 kb
Host smart-fc3a6447-c821-4c6f-8e18-2a157ff55872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815466100 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2815466100
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2006116073
Short name T923
Test name
Test status
Simulation time 38798248 ps
CPU time 0.89 seconds
Started Jun 02 02:14:03 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206128 kb
Host smart-f6280cf2-d1a0-4b02-aae6-26171e9f28ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006116073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2006116073
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1645890973
Short name T875
Test name
Test status
Simulation time 16321890 ps
CPU time 0.9 seconds
Started Jun 02 02:14:03 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 206016 kb
Host smart-cf036acc-dd99-4606-99fd-66ce29302b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645890973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1645890973
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2635587814
Short name T907
Test name
Test status
Simulation time 58230278 ps
CPU time 1.32 seconds
Started Jun 02 02:14:04 PM PDT 24
Finished Jun 02 02:14:06 PM PDT 24
Peak memory 206188 kb
Host smart-29e7f0d3-e3bd-4e3b-afc9-959b2533bca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635587814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2635587814
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1198413550
Short name T846
Test name
Test status
Simulation time 183314692 ps
CPU time 4.05 seconds
Started Jun 02 02:14:01 PM PDT 24
Finished Jun 02 02:14:05 PM PDT 24
Peak memory 214392 kb
Host smart-563c2fd2-2f59-4b94-aa06-6f8a8ec85786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198413550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1198413550
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2021740734
Short name T234
Test name
Test status
Simulation time 174701950 ps
CPU time 2.6 seconds
Started Jun 02 02:14:04 PM PDT 24
Finished Jun 02 02:14:07 PM PDT 24
Peak memory 214424 kb
Host smart-f670bb30-5fac-46cd-8494-13b25a349b91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021740734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2021740734
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.638342572
Short name T888
Test name
Test status
Simulation time 54011279 ps
CPU time 1.27 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:10 PM PDT 24
Peak memory 214460 kb
Host smart-88de7a72-f143-4d1f-bf0e-90938a03119b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638342572 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.638342572
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3478248597
Short name T927
Test name
Test status
Simulation time 14832135 ps
CPU time 0.94 seconds
Started Jun 02 02:14:10 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 206008 kb
Host smart-3e891577-308d-4840-86e6-b4af71503967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478248597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3478248597
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.4091426840
Short name T872
Test name
Test status
Simulation time 15982938 ps
CPU time 0.9 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:10 PM PDT 24
Peak memory 205996 kb
Host smart-ceaba1a1-ea40-45ec-b840-0f5e565f9674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091426840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.4091426840
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3107511941
Short name T215
Test name
Test status
Simulation time 147714638 ps
CPU time 1.75 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 206232 kb
Host smart-7a4e9815-69ff-4d02-94c9-7c8b87b70272
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107511941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3107511941
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3709191302
Short name T917
Test name
Test status
Simulation time 1285363396 ps
CPU time 3.58 seconds
Started Jun 02 02:14:04 PM PDT 24
Finished Jun 02 02:14:07 PM PDT 24
Peak memory 214328 kb
Host smart-5bfc605e-67ec-4ad6-8f7e-440a43e8e279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709191302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3709191302
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1193843609
Short name T953
Test name
Test status
Simulation time 109158385 ps
CPU time 2.26 seconds
Started Jun 02 02:14:06 PM PDT 24
Finished Jun 02 02:14:10 PM PDT 24
Peak memory 214264 kb
Host smart-21c578f2-aa26-4ec6-a577-439dc7a4a83a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193843609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1193843609
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1205648291
Short name T904
Test name
Test status
Simulation time 22286557 ps
CPU time 1.18 seconds
Started Jun 02 02:14:08 PM PDT 24
Finished Jun 02 02:14:09 PM PDT 24
Peak memory 214364 kb
Host smart-eba8347d-d07b-4922-8286-a5f76d50823e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205648291 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1205648291
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3166516050
Short name T208
Test name
Test status
Simulation time 14636187 ps
CPU time 0.92 seconds
Started Jun 02 02:14:11 PM PDT 24
Finished Jun 02 02:14:12 PM PDT 24
Peak memory 206128 kb
Host smart-b90d3a33-1cb3-45ef-b8a2-7939c1c8f699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166516050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3166516050
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1945379940
Short name T882
Test name
Test status
Simulation time 23369549 ps
CPU time 0.83 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:10 PM PDT 24
Peak memory 206000 kb
Host smart-125d9a39-544a-4481-9db0-d5558c2f97b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945379940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1945379940
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1123165038
Short name T967
Test name
Test status
Simulation time 72371652 ps
CPU time 0.95 seconds
Started Jun 02 02:14:09 PM PDT 24
Finished Jun 02 02:14:11 PM PDT 24
Peak memory 206132 kb
Host smart-334aaa6a-33b0-437e-ab19-e9f8565d6bef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123165038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1123165038
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2871447027
Short name T905
Test name
Test status
Simulation time 31540312 ps
CPU time 2.31 seconds
Started Jun 02 02:14:12 PM PDT 24
Finished Jun 02 02:14:14 PM PDT 24
Peak memory 214332 kb
Host smart-2cedf656-93b4-4a61-92b8-007926aacbd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871447027 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2871447027
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.6361552
Short name T947
Test name
Test status
Simulation time 284471899 ps
CPU time 2.25 seconds
Started Jun 02 02:14:12 PM PDT 24
Finished Jun 02 02:14:15 PM PDT 24
Peak memory 206108 kb
Host smart-9bf87953-033f-4a56-9991-6cb41e3aa520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6361552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.6361552
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1586079779
Short name T183
Test name
Test status
Simulation time 216261131 ps
CPU time 1.2 seconds
Started Jun 02 02:43:43 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 215360 kb
Host smart-3602b254-fbfc-46a4-ba0e-1ca0ba8fa20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586079779 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1586079779
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2441223326
Short name T574
Test name
Test status
Simulation time 11673243 ps
CPU time 0.83 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 206512 kb
Host smart-1c725d5c-3c53-48d0-a277-8a15b0c1d136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441223326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2441223326
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.528633851
Short name T409
Test name
Test status
Simulation time 17285334 ps
CPU time 0.88 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 215148 kb
Host smart-5b800a58-1a2a-4cb1-90a9-b602b2331ad1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528633851 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.528633851
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1040968731
Short name T38
Test name
Test status
Simulation time 50578493 ps
CPU time 1.1 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:41 PM PDT 24
Peak memory 216564 kb
Host smart-2a388a76-a750-4e36-b987-01ca0f75f07f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040968731 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1040968731
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1678450007
Short name T70
Test name
Test status
Simulation time 29958984 ps
CPU time 1.36 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 224976 kb
Host smart-f34b0f99-f8c6-42c7-a6b1-845301e0165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678450007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1678450007
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2837564522
Short name T336
Test name
Test status
Simulation time 48665078 ps
CPU time 1.46 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 217856 kb
Host smart-8f4d2bd1-6d6c-4ad0-8f22-7d5aa848c364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837564522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2837564522
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.3244351556
Short name T776
Test name
Test status
Simulation time 39490173 ps
CPU time 0.9 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 215284 kb
Host smart-94290784-2697-4256-b994-74218bb9a014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244351556 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3244351556
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_smoke.4196053255
Short name T389
Test name
Test status
Simulation time 21104984 ps
CPU time 1.04 seconds
Started Jun 02 02:43:28 PM PDT 24
Finished Jun 02 02:43:30 PM PDT 24
Peak memory 214948 kb
Host smart-b9152fde-3a5f-47a1-8775-fee858483bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196053255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4196053255
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3975152272
Short name T486
Test name
Test status
Simulation time 80323538 ps
CPU time 1.7 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 214936 kb
Host smart-6dc6b214-0f9d-44ad-9f62-0d6e3f277e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975152272 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3975152272
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2069944358
Short name T329
Test name
Test status
Simulation time 105515878256 ps
CPU time 1291.62 seconds
Started Jun 02 02:43:36 PM PDT 24
Finished Jun 02 03:05:09 PM PDT 24
Peak memory 225320 kb
Host smart-74075069-8f40-4d92-b4c9-195ac02bd76f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069944358 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2069944358
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.127646237
Short name T251
Test name
Test status
Simulation time 80727227 ps
CPU time 1.16 seconds
Started Jun 02 02:43:45 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 215328 kb
Host smart-01003bc2-ac3e-489b-9e11-e27461b418c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127646237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.127646237
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1768395578
Short name T798
Test name
Test status
Simulation time 137085987 ps
CPU time 0.81 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 206256 kb
Host smart-f634ad5d-6289-474d-8f26-7850d3d55bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768395578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1768395578
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2781812787
Short name T171
Test name
Test status
Simulation time 23387085 ps
CPU time 0.85 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 216168 kb
Host smart-9e826f46-8f64-4269-bf66-9788be3e3836
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781812787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2781812787
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2108833488
Short name T56
Test name
Test status
Simulation time 30128825 ps
CPU time 1.15 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 216472 kb
Host smart-d7ad471d-8a1d-4113-aa40-98409fd61eb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108833488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2108833488
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.2377554584
Short name T284
Test name
Test status
Simulation time 250607310 ps
CPU time 3.6 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 218340 kb
Host smart-ce8d02ac-311a-4a11-9678-78711b7d7c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377554584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2377554584
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.482350326
Short name T246
Test name
Test status
Simulation time 17324799 ps
CPU time 1.02 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:32 PM PDT 24
Peak memory 206720 kb
Host smart-c5db4e5b-ece5-47eb-955f-33f515bdf532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482350326 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.482350326
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2186914810
Short name T19
Test name
Test status
Simulation time 520951126 ps
CPU time 7.73 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:51 PM PDT 24
Peak memory 236400 kb
Host smart-cc2d908a-8e08-40fa-b88d-3038b1f7735c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186914810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2186914810
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3276748660
Short name T368
Test name
Test status
Simulation time 44791246 ps
CPU time 0.98 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:47 PM PDT 24
Peak memory 214952 kb
Host smart-dba5550c-f815-4b9c-9a2b-506b6e237b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276748660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3276748660
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3953730144
Short name T203
Test name
Test status
Simulation time 254388785 ps
CPU time 2.31 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 214920 kb
Host smart-29631551-b7dc-4d76-80de-f0528cade9fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953730144 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3953730144
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1554080875
Short name T112
Test name
Test status
Simulation time 134821616004 ps
CPU time 681.56 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:55:02 PM PDT 24
Peak memory 223352 kb
Host smart-dc9dd6dc-4268-4050-9227-e50648514269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554080875 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1554080875
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.344448642
Short name T29
Test name
Test status
Simulation time 23135288 ps
CPU time 1.17 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 215396 kb
Host smart-952cfc1f-c81b-49b6-ac49-53251beb1667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344448642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.344448642
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.1850196390
Short name T742
Test name
Test status
Simulation time 19868678 ps
CPU time 0.98 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 206252 kb
Host smart-c2b7ca42-1153-466d-b544-257122791718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850196390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1850196390
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.959044540
Short name T505
Test name
Test status
Simulation time 12473287 ps
CPU time 0.93 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 215788 kb
Host smart-cf43efca-f5ac-4ba2-b85d-6798411bf118
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959044540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.959044540
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.3505744383
Short name T47
Test name
Test status
Simulation time 45852028 ps
CPU time 0.88 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 219128 kb
Host smart-12a684e1-8bc4-4037-8641-e40c22c89cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505744383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3505744383
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3940203152
Short name T523
Test name
Test status
Simulation time 39699496 ps
CPU time 1.47 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 218200 kb
Host smart-dd7c698a-2140-49d5-84f7-16a9d564def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940203152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3940203152
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.33524962
Short name T493
Test name
Test status
Simulation time 22455890 ps
CPU time 1.21 seconds
Started Jun 02 02:43:46 PM PDT 24
Finished Jun 02 02:43:48 PM PDT 24
Peak memory 223552 kb
Host smart-995984d8-c613-480b-956d-ff68411338ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33524962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.33524962
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.136771341
Short name T436
Test name
Test status
Simulation time 16251506 ps
CPU time 0.98 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 206764 kb
Host smart-2ec845c7-226c-45f5-b20c-333a079cf05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136771341 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.136771341
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2933921299
Short name T426
Test name
Test status
Simulation time 132791211 ps
CPU time 1.38 seconds
Started Jun 02 02:43:52 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 215256 kb
Host smart-8f79f0b5-5582-49db-9827-6f9a11d22990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933921299 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2933921299
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3844190189
Short name T449
Test name
Test status
Simulation time 128896976536 ps
CPU time 722.9 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:57:08 PM PDT 24
Peak memory 223396 kb
Host smart-b153783f-dc21-436e-aa2c-a263b12a5c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844190189 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3844190189
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3896391215
Short name T543
Test name
Test status
Simulation time 43940346 ps
CPU time 1.32 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:08 PM PDT 24
Peak memory 217020 kb
Host smart-6858a1f0-569b-424e-8440-d5049c5b1e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896391215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3896391215
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3307746867
Short name T721
Test name
Test status
Simulation time 88568636 ps
CPU time 1.23 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 219080 kb
Host smart-4b53b7c3-d1f5-4419-9015-cbfc5d6bb43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307746867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3307746867
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.603324645
Short name T404
Test name
Test status
Simulation time 55410359 ps
CPU time 1.34 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:01 PM PDT 24
Peak memory 217756 kb
Host smart-bb686d6f-a7d9-406e-876c-83227a2a89a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603324645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.603324645
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4056653924
Short name T643
Test name
Test status
Simulation time 58592709 ps
CPU time 1.43 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 216724 kb
Host smart-4837e512-4fdc-4d46-bd41-0525dcc874c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056653924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4056653924
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.208311708
Short name T630
Test name
Test status
Simulation time 213237824 ps
CPU time 2.51 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 219408 kb
Host smart-6d9f56f7-cf17-499b-bdd9-455e7a98438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208311708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.208311708
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.268537783
Short name T137
Test name
Test status
Simulation time 30681023 ps
CPU time 1.24 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 216852 kb
Host smart-37c90b0e-247b-43d0-a04f-7bc298fcada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268537783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.268537783
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.924232316
Short name T685
Test name
Test status
Simulation time 22325848 ps
CPU time 1.24 seconds
Started Jun 02 02:45:04 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 218208 kb
Host smart-75332598-ce03-47d2-a952-615f7c67c2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924232316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.924232316
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2326864461
Short name T378
Test name
Test status
Simulation time 60350902 ps
CPU time 1.31 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 216876 kb
Host smart-8ac514fd-fcc5-48ed-b7ab-54d613eaf6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326864461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2326864461
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2226734388
Short name T536
Test name
Test status
Simulation time 45690800 ps
CPU time 1.14 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 216856 kb
Host smart-33783d1b-080a-4489-b7cb-559eb9f5814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226734388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2226734388
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3983382895
Short name T303
Test name
Test status
Simulation time 34675413 ps
CPU time 1.27 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 216628 kb
Host smart-58957a06-912f-46b4-8ac1-f6dfbab03329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983382895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3983382895
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2305952339
Short name T671
Test name
Test status
Simulation time 97786810 ps
CPU time 1.18 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 215348 kb
Host smart-d0a5bcaf-4cd4-443b-9656-b497fa104bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305952339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2305952339
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.1471249464
Short name T767
Test name
Test status
Simulation time 14041148 ps
CPU time 0.93 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 215760 kb
Host smart-1030e2d3-f609-4fcf-871d-429b0e0c9c22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471249464 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1471249464
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3181567591
Short name T524
Test name
Test status
Simulation time 110499901 ps
CPU time 1.12 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 217740 kb
Host smart-5852ca08-0fae-4d72-8862-074db3cd3955
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181567591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3181567591
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.862967854
Short name T465
Test name
Test status
Simulation time 38596101 ps
CPU time 0.87 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 218200 kb
Host smart-d66fafc2-4331-4184-b0d2-a2de4b9669de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862967854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.862967854
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.812820766
Short name T457
Test name
Test status
Simulation time 42442645 ps
CPU time 1.38 seconds
Started Jun 02 02:43:47 PM PDT 24
Finished Jun 02 02:43:49 PM PDT 24
Peak memory 217848 kb
Host smart-4af5a57b-2a01-4078-bb5e-636cbf5b97a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812820766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.812820766
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.1158187555
Short name T417
Test name
Test status
Simulation time 22512254 ps
CPU time 1.1 seconds
Started Jun 02 02:43:41 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 215292 kb
Host smart-2a84b0fa-bf75-4dc6-8d15-62d637ed35f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158187555 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1158187555
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4151563590
Short name T424
Test name
Test status
Simulation time 33175354 ps
CPU time 0.9 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 214968 kb
Host smart-6637d2b8-1637-4fcd-8c77-ad75925b6298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151563590 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4151563590
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4256028200
Short name T202
Test name
Test status
Simulation time 150032238 ps
CPU time 3.41 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 219388 kb
Host smart-16495ca7-30bd-452c-85d8-d4c4760c437b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256028200 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4256028200
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4125467625
Short name T616
Test name
Test status
Simulation time 35737254124 ps
CPU time 793.3 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:57:09 PM PDT 24
Peak memory 217332 kb
Host smart-33eec876-a747-4774-9108-d610d93ee1a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125467625 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4125467625
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.63531421
Short name T445
Test name
Test status
Simulation time 81607508 ps
CPU time 1.36 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 218076 kb
Host smart-fc1f3d03-5869-4f28-be23-6738d25e80d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63531421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.63531421
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1670226137
Short name T381
Test name
Test status
Simulation time 230427525 ps
CPU time 3.39 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 219408 kb
Host smart-fb03ce60-1947-4b44-b2b4-383f120d620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670226137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1670226137
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3268251281
Short name T117
Test name
Test status
Simulation time 43167017 ps
CPU time 1.59 seconds
Started Jun 02 02:45:04 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 218132 kb
Host smart-34636102-2f08-40ed-a625-ff4fbf217b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268251281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3268251281
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1411667315
Short name T662
Test name
Test status
Simulation time 66198953 ps
CPU time 1.05 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 216736 kb
Host smart-825cd2f7-ef49-4b84-b938-468ed9dcf9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411667315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1411667315
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2860386839
Short name T564
Test name
Test status
Simulation time 91774226 ps
CPU time 3.21 seconds
Started Jun 02 02:45:02 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 218004 kb
Host smart-4dec8d61-b9c8-41bb-bba9-9a4b4cafa718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860386839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2860386839
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3310743590
Short name T547
Test name
Test status
Simulation time 188951966 ps
CPU time 1.41 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 218252 kb
Host smart-1d01c558-46c5-4f43-8e75-e0bfa3101afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310743590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3310743590
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.373190362
Short name T309
Test name
Test status
Simulation time 42342563 ps
CPU time 1.19 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 218096 kb
Host smart-3fc02465-12a8-4d8e-858c-8af24696a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373190362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.373190362
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert_test.991129617
Short name T645
Test name
Test status
Simulation time 32958313 ps
CPU time 0.85 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:44 PM PDT 24
Peak memory 204492 kb
Host smart-94a61957-1be3-4aab-97f6-315c632a0571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991129617 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.991129617
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.3646911188
Short name T178
Test name
Test status
Simulation time 19251855 ps
CPU time 0.87 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 215972 kb
Host smart-dcd8c45e-a7b7-4ef6-8daf-53c9c2247365
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646911188 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3646911188
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.3630472168
Short name T670
Test name
Test status
Simulation time 125515804 ps
CPU time 0.92 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 216716 kb
Host smart-73722b83-ab15-4483-9e83-8f4d9e6ebf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630472168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.3630472168
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.547533661
Short name T111
Test name
Test status
Simulation time 22001919 ps
CPU time 1.11 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 215440 kb
Host smart-f521b6b5-b4c7-4ced-80f8-3cf1106cb06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547533661 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.547533661
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2056120889
Short name T549
Test name
Test status
Simulation time 34982013 ps
CPU time 0.9 seconds
Started Jun 02 02:43:47 PM PDT 24
Finished Jun 02 02:43:48 PM PDT 24
Peak memory 214972 kb
Host smart-39876176-14b1-4abc-86c2-5ae3be2b58b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056120889 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2056120889
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1873621772
Short name T349
Test name
Test status
Simulation time 76464633825 ps
CPU time 427.05 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:51:23 PM PDT 24
Peak memory 220544 kb
Host smart-bf47a8dc-94e3-4f7d-b6f4-51b452c61351
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873621772 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1873621772
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/121.edn_genbits.2782762242
Short name T695
Test name
Test status
Simulation time 198320690 ps
CPU time 1.38 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 219360 kb
Host smart-e3c745ac-ccf2-44c2-b483-a137f0507d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782762242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2782762242
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.142837017
Short name T508
Test name
Test status
Simulation time 29256044 ps
CPU time 1.12 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216896 kb
Host smart-d3402c04-94c7-45b5-85f2-50e46fc31851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142837017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.142837017
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2001956134
Short name T731
Test name
Test status
Simulation time 61977077 ps
CPU time 1.24 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 216644 kb
Host smart-ceaa3a89-ddc2-46ea-887f-70f6d79102f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001956134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2001956134
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3342634013
Short name T582
Test name
Test status
Simulation time 36017494 ps
CPU time 1.37 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 219288 kb
Host smart-b1069902-8a7b-436e-9d74-812bf622c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342634013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3342634013
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1105180983
Short name T690
Test name
Test status
Simulation time 48019041 ps
CPU time 1.72 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 217748 kb
Host smart-5bdfbcb6-2dd6-4460-87d7-6af833b46e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105180983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1105180983
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1261054202
Short name T483
Test name
Test status
Simulation time 73777100 ps
CPU time 1.19 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 216716 kb
Host smart-3a2004a9-a866-4e23-8bd6-abe29b48b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261054202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1261054202
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.605494547
Short name T114
Test name
Test status
Simulation time 34365346 ps
CPU time 1.31 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 216824 kb
Host smart-6f5afb1b-5229-4410-810b-5c5ae9642f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605494547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.605494547
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2524414668
Short name T133
Test name
Test status
Simulation time 54265862 ps
CPU time 1.61 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 217984 kb
Host smart-348fe1c0-fa82-46b1-81c6-09cc62d1299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524414668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2524414668
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3902298612
Short name T636
Test name
Test status
Simulation time 33595577 ps
CPU time 1.31 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 217952 kb
Host smart-c350b8d6-7f78-4ac1-859e-5d74b6fa97c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902298612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3902298612
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1328890500
Short name T36
Test name
Test status
Simulation time 109890857 ps
CPU time 1.28 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 215316 kb
Host smart-b5090a2b-86f4-4d1d-89d6-48084690c5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328890500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1328890500
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1116707771
Short name T376
Test name
Test status
Simulation time 27172473 ps
CPU time 1.07 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 214516 kb
Host smart-f84e1da1-1737-4725-b8bc-214b1956c8b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116707771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1116707771
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1026345201
Short name T88
Test name
Test status
Simulation time 19673777 ps
CPU time 0.89 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 216028 kb
Host smart-d9873e62-0559-4d84-9ab9-7b52a3c910c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026345201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1026345201
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2385407665
Short name T177
Test name
Test status
Simulation time 36678806 ps
CPU time 1.18 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 219200 kb
Host smart-bea846fa-8e74-49ed-9b48-878c68a3603e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385407665 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2385407665
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1447214346
Short name T52
Test name
Test status
Simulation time 23946055 ps
CPU time 1.26 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 223448 kb
Host smart-a8ab11e5-a832-43b4-8473-bb4b329be260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447214346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1447214346
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_intr.791774469
Short name T752
Test name
Test status
Simulation time 20565300 ps
CPU time 1.07 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 215132 kb
Host smart-2ab59159-59a8-4371-b2b5-c7557e77881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791774469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.791774469
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3090547813
Short name T438
Test name
Test status
Simulation time 15552877 ps
CPU time 0.99 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 215004 kb
Host smart-a65f0aff-6b30-4ade-8234-5300d73cfdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090547813 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3090547813
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2250101113
Short name T456
Test name
Test status
Simulation time 1183373758 ps
CPU time 4.75 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216792 kb
Host smart-98a20a48-cdcf-403b-a395-567cf07133a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250101113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2250101113
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2771710363
Short name T342
Test name
Test status
Simulation time 30820802508 ps
CPU time 694.53 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:55:26 PM PDT 24
Peak memory 218252 kb
Host smart-9e302f0c-234d-427e-b963-393b9fa7287f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771710363 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2771710363
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1990003529
Short name T572
Test name
Test status
Simulation time 104817542 ps
CPU time 1.26 seconds
Started Jun 02 02:44:59 PM PDT 24
Finished Jun 02 02:45:01 PM PDT 24
Peak memory 217664 kb
Host smart-071ba3ea-2705-44f9-9dbb-30e16916200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990003529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1990003529
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2979226960
Short name T364
Test name
Test status
Simulation time 72095387 ps
CPU time 1.34 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 217788 kb
Host smart-02590917-6695-43cd-8d36-15f5dcbf6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979226960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2979226960
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.555078093
Short name T10
Test name
Test status
Simulation time 78570203 ps
CPU time 1.16 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 219088 kb
Host smart-83274d10-7017-43ec-8e25-3f8f850afbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555078093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.555078093
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2510072420
Short name T794
Test name
Test status
Simulation time 91538096 ps
CPU time 1.09 seconds
Started Jun 02 02:45:23 PM PDT 24
Finished Jun 02 02:45:25 PM PDT 24
Peak memory 215052 kb
Host smart-2b76ec53-febd-4bcd-bb49-7e7eeecaadc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510072420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2510072420
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2932762443
Short name T597
Test name
Test status
Simulation time 39675330 ps
CPU time 1.2 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 218220 kb
Host smart-e9ccf3fe-263f-4a90-a11e-93697c74b55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932762443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2932762443
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3740696037
Short name T468
Test name
Test status
Simulation time 80978432 ps
CPU time 1.28 seconds
Started Jun 02 02:45:03 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 219576 kb
Host smart-a7bb08ca-b952-4c3f-89a7-c76b95c37cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740696037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3740696037
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1791088050
Short name T401
Test name
Test status
Simulation time 278450951 ps
CPU time 3.9 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 219748 kb
Host smart-a6fd2ce4-39a0-4a4a-9290-3f5b84bd482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791088050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1791088050
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2943717779
Short name T545
Test name
Test status
Simulation time 37833860 ps
CPU time 1.62 seconds
Started Jun 02 02:45:18 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 219476 kb
Host smart-fc4a69d0-3630-462f-9c1f-abc754e5aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943717779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2943717779
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2010238960
Short name T325
Test name
Test status
Simulation time 59157724 ps
CPU time 1.17 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 214968 kb
Host smart-58239aa0-6737-40a1-9d09-4cb2e6f670c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010238960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2010238960
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3194319648
Short name T498
Test name
Test status
Simulation time 82340760 ps
CPU time 1.11 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:56 PM PDT 24
Peak memory 215320 kb
Host smart-b9249c17-761f-4ae2-9cfc-1bbcf93e47d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194319648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3194319648
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1917298654
Short name T412
Test name
Test status
Simulation time 62186209 ps
CPU time 0.99 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 214568 kb
Host smart-2fa86a54-b78f-4592-aaab-97321b21a14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917298654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1917298654
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.316104173
Short name T698
Test name
Test status
Simulation time 52192338 ps
CPU time 1.04 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 216468 kb
Host smart-65cb309c-8a22-4831-abfc-647e74e5ee37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316104173 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.316104173
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.4127363852
Short name T694
Test name
Test status
Simulation time 24323842 ps
CPU time 0.92 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 218112 kb
Host smart-dc764650-2e89-4a34-bb71-ae32872a8d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127363852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4127363852
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.986082616
Short name T642
Test name
Test status
Simulation time 34773610 ps
CPU time 1.31 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 217832 kb
Host smart-8b3eaaa5-4d99-41e7-968f-730bd1a0c1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986082616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.986082616
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.914987117
Short name T618
Test name
Test status
Simulation time 24484008 ps
CPU time 0.96 seconds
Started Jun 02 02:44:11 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 215256 kb
Host smart-f314ee95-3918-46fb-90c6-91be07d4a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914987117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.914987117
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3137249621
Short name T841
Test name
Test status
Simulation time 26918135 ps
CPU time 0.94 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:08 PM PDT 24
Peak memory 214948 kb
Host smart-0ea48b47-9891-456e-821b-068b55e3665c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137249621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3137249621
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1468912020
Short name T830
Test name
Test status
Simulation time 201849265 ps
CPU time 4.07 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 215004 kb
Host smart-a61b7ce3-6aa3-4793-9b29-8bea1e37cd04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468912020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1468912020
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.546297264
Short name T201
Test name
Test status
Simulation time 55539704752 ps
CPU time 634.71 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:54:35 PM PDT 24
Peak memory 220196 kb
Host smart-9a9aa8f5-8a49-43a2-8241-fa3515e438c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546297264 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.546297264
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.4165847723
Short name T658
Test name
Test status
Simulation time 46955377 ps
CPU time 1.52 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 218640 kb
Host smart-1b446619-5637-4f0b-844e-c94ce87fd28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165847723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4165847723
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2155919313
Short name T323
Test name
Test status
Simulation time 36587959 ps
CPU time 1.47 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 215072 kb
Host smart-bdb8c380-df54-4669-9db2-2868ccaac5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155919313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2155919313
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3364646088
Short name T836
Test name
Test status
Simulation time 60553027 ps
CPU time 1.59 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 218140 kb
Host smart-2039db33-bb0b-4004-9d3c-676b0a36ad9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364646088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3364646088
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2782665143
Short name T423
Test name
Test status
Simulation time 105496251 ps
CPU time 1.09 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 216592 kb
Host smart-699e7242-4682-4325-9423-00bf963c92c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782665143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2782665143
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3517010172
Short name T289
Test name
Test status
Simulation time 32074099 ps
CPU time 1.31 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 217044 kb
Host smart-5f73f36c-3a8a-4b1d-8549-abbe02de669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517010172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3517010172
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1540438090
Short name T714
Test name
Test status
Simulation time 60179105 ps
CPU time 2.26 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 219460 kb
Host smart-1d8ab68e-deb5-40eb-bb6b-efe882851dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540438090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1540438090
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2911222300
Short name T559
Test name
Test status
Simulation time 45767607 ps
CPU time 1.13 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216776 kb
Host smart-1c73a3c2-efa3-4076-b086-ffab78daeb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911222300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2911222300
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2627387232
Short name T666
Test name
Test status
Simulation time 61806817 ps
CPU time 1.33 seconds
Started Jun 02 02:45:04 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 216712 kb
Host smart-3381485f-af98-4051-8a7f-c10a192ca073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627387232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2627387232
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1560758338
Short name T12
Test name
Test status
Simulation time 205669165 ps
CPU time 1.25 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 219340 kb
Host smart-70e7ae0a-d8a7-4d3e-9bcb-c4965c061e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560758338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1560758338
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.1205293106
Short name T312
Test name
Test status
Simulation time 51245159 ps
CPU time 0.88 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 206276 kb
Host smart-bf07a78e-5451-4d1a-8a08-57f0e33011e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205293106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1205293106
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.396501259
Short name T78
Test name
Test status
Simulation time 11060786 ps
CPU time 0.95 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 215936 kb
Host smart-c744a25c-82ca-49b3-b478-1e5a531dcef7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396501259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.396501259
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3903530282
Short name T54
Test name
Test status
Simulation time 52670543 ps
CPU time 1.15 seconds
Started Jun 02 02:44:16 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 216468 kb
Host smart-c17fe560-a7b1-4e0d-a514-ce11c00f6576
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903530282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3903530282
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.699632665
Short name T345
Test name
Test status
Simulation time 88898890 ps
CPU time 1.07 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 217012 kb
Host smart-06fed0ed-02a1-477a-a736-f707050d019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699632665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.699632665
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3433186609
Short name T288
Test name
Test status
Simulation time 122663796 ps
CPU time 2.48 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 219060 kb
Host smart-a0cbb0ae-4bd8-4352-9aaa-e0201188f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433186609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3433186609
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.653926599
Short name T98
Test name
Test status
Simulation time 21065084 ps
CPU time 1.11 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 215052 kb
Host smart-cc8df5e8-d282-4c95-bcda-baa45407144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653926599 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.653926599
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3113790388
Short name T813
Test name
Test status
Simulation time 16153457 ps
CPU time 1 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 214924 kb
Host smart-cbbd3747-fa71-4e0b-84bb-9fb6bf9f9638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113790388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3113790388
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3128892803
Short name T488
Test name
Test status
Simulation time 147602266 ps
CPU time 2.72 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 218024 kb
Host smart-d467c6dc-0952-4690-94f8-c5a68c10d04d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128892803 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3128892803
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1068106239
Short name T194
Test name
Test status
Simulation time 89844712715 ps
CPU time 538.3 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:52:53 PM PDT 24
Peak memory 218960 kb
Host smart-612b46ea-63eb-4f55-a7ec-ca667f38be31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068106239 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1068106239
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1902716193
Short name T542
Test name
Test status
Simulation time 50064127 ps
CPU time 1.82 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 219436 kb
Host smart-4c4da7ef-07da-42a9-a65d-eb3a6d517552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902716193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1902716193
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.242632642
Short name T499
Test name
Test status
Simulation time 72774958 ps
CPU time 1.76 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 218140 kb
Host smart-5f7abde2-d7be-45a8-bb54-13d4511a6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242632642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.242632642
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.1406599331
Short name T588
Test name
Test status
Simulation time 102796843 ps
CPU time 2.44 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 217876 kb
Host smart-29ff8a97-1b34-43b8-8cac-fb7062c70687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406599331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1406599331
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3279803325
Short name T818
Test name
Test status
Simulation time 63787739 ps
CPU time 1.29 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216668 kb
Host smart-c891fd52-dba9-4868-a6c0-b826aff4c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279803325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3279803325
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.128047315
Short name T474
Test name
Test status
Simulation time 79441653 ps
CPU time 1.1 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 216816 kb
Host smart-5bd97107-73a2-4c2f-8d80-1224a371b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128047315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.128047315
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2633982267
Short name T692
Test name
Test status
Simulation time 62987705 ps
CPU time 1.05 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216648 kb
Host smart-6805d190-b05b-4f61-b6ce-b1e969b754a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633982267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2633982267
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2353800300
Short name T777
Test name
Test status
Simulation time 40871506 ps
CPU time 1.59 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 219184 kb
Host smart-202a084d-cb13-438d-8ac7-dcda04c72130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353800300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2353800300
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2137080019
Short name T440
Test name
Test status
Simulation time 85789095 ps
CPU time 1.14 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216752 kb
Host smart-1bb24410-63a0-4be6-a4a5-0ee9f507e086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137080019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2137080019
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3086362677
Short name T343
Test name
Test status
Simulation time 48392155 ps
CPU time 1.22 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 219188 kb
Host smart-300e1b6a-a766-4c81-9218-a88f5df56725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086362677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3086362677
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.4234894530
Short name T743
Test name
Test status
Simulation time 43479324 ps
CPU time 1.23 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:56 PM PDT 24
Peak memory 215356 kb
Host smart-cf992af8-0390-45f8-b890-8d9fda3136ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234894530 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4234894530
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2565406235
Short name T663
Test name
Test status
Simulation time 49916003 ps
CPU time 0.86 seconds
Started Jun 02 02:44:10 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 214416 kb
Host smart-91c8d7d0-8b87-401a-a5cd-ae3d11dbcdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565406235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2565406235
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3861747896
Short name T174
Test name
Test status
Simulation time 56637937 ps
CPU time 1.13 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216440 kb
Host smart-086ce576-da7e-4687-9b62-a63a6d4d3f9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861747896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3861747896
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2728563641
Short name T162
Test name
Test status
Simulation time 77499154 ps
CPU time 0.88 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 217964 kb
Host smart-34f74cd0-173a-4bc0-8e76-8697dfbd026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728563641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2728563641
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.2326642569
Short name T294
Test name
Test status
Simulation time 123581402 ps
CPU time 1.09 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 216860 kb
Host smart-ce51815d-d596-4b90-910e-f4ab85bdad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326642569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2326642569
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2979050319
Short name T148
Test name
Test status
Simulation time 20905501 ps
CPU time 1.09 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 216264 kb
Host smart-6f889998-b616-40b7-9c07-2184e383de3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979050319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2979050319
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4105209498
Short name T804
Test name
Test status
Simulation time 55365574 ps
CPU time 0.85 seconds
Started Jun 02 02:43:52 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 214760 kb
Host smart-5fcf36e6-0a30-49ad-ae01-66b798c29f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105209498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4105209498
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4260387033
Short name T606
Test name
Test status
Simulation time 149003978 ps
CPU time 3.5 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:53 PM PDT 24
Peak memory 217984 kb
Host smart-d3f3d38f-aeb2-46b8-8d76-ebe3440357bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260387033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4260387033
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/160.edn_genbits.2920743791
Short name T370
Test name
Test status
Simulation time 190492234 ps
CPU time 1.57 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 218548 kb
Host smart-4a748ada-888d-4a0a-8ecd-dadca15d10e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920743791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2920743791
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1554849970
Short name T797
Test name
Test status
Simulation time 67590494 ps
CPU time 0.97 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 216548 kb
Host smart-71574e91-ef30-463e-8d51-ec3b7049b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554849970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1554849970
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3411059076
Short name T814
Test name
Test status
Simulation time 39601379 ps
CPU time 1.41 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 218084 kb
Host smart-1a9b1fa6-795e-411a-951f-f3745ba2e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411059076 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3411059076
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3346421111
Short name T585
Test name
Test status
Simulation time 75438439 ps
CPU time 2.77 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 219824 kb
Host smart-5c1f8b41-9c73-4499-8b32-8c79b95f5d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346421111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3346421111
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.1571256392
Short name T534
Test name
Test status
Simulation time 49357071 ps
CPU time 1.12 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 219120 kb
Host smart-f7bfa1cf-ead5-4a62-b1fb-41e9ff0368de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571256392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1571256392
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3699902481
Short name T793
Test name
Test status
Simulation time 106498267 ps
CPU time 1.51 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 218124 kb
Host smart-079f868e-b69a-4f6a-85f5-0067fc394e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699902481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3699902481
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.4286203260
Short name T579
Test name
Test status
Simulation time 42124542 ps
CPU time 0.92 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 216664 kb
Host smart-c119fb8d-1ffb-42bc-b136-ab094616258f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286203260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4286203260
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3816255639
Short name T539
Test name
Test status
Simulation time 47867418 ps
CPU time 1.18 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 216788 kb
Host smart-f55018ca-0415-4e2b-bc97-93a78d8f8a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816255639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3816255639
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1888935131
Short name T555
Test name
Test status
Simulation time 58972718 ps
CPU time 1.2 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 216964 kb
Host smart-6a566d83-6df0-488a-88f8-192243507a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888935131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1888935131
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2399351508
Short name T319
Test name
Test status
Simulation time 41947357 ps
CPU time 1.11 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:08 PM PDT 24
Peak memory 216696 kb
Host smart-62568b4b-18f5-45c1-a965-0182fd0fc157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399351508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2399351508
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2560300528
Short name T490
Test name
Test status
Simulation time 84284748 ps
CPU time 1.13 seconds
Started Jun 02 02:44:04 PM PDT 24
Finished Jun 02 02:44:06 PM PDT 24
Peak memory 215452 kb
Host smart-8eb769f4-93a5-4ea0-a779-ac33d8b4e49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560300528 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2560300528
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1011061151
Short name T324
Test name
Test status
Simulation time 16979623 ps
CPU time 0.93 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 206260 kb
Host smart-3b34381f-ffaa-4fde-a103-e020af5a488d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011061151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1011061151
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3041855838
Short name T701
Test name
Test status
Simulation time 10983956 ps
CPU time 0.85 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 215664 kb
Host smart-031be6bf-3b0c-4493-ae07-b67ab153c0b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041855838 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3041855838
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.4032171316
Short name T578
Test name
Test status
Simulation time 84082543 ps
CPU time 1.1 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:56 PM PDT 24
Peak memory 216428 kb
Host smart-e5d6f220-e834-47ab-bb29-32bea6703e66
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032171316 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.4032171316
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1735346399
Short name T507
Test name
Test status
Simulation time 19412684 ps
CPU time 1.03 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 218156 kb
Host smart-56606e45-7a95-4a04-a4c6-1bf486b12893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735346399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1735346399
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3702648210
Short name T497
Test name
Test status
Simulation time 37517444 ps
CPU time 1.37 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:56 PM PDT 24
Peak memory 216924 kb
Host smart-cddf661a-a3fe-4169-8ec2-73198b045bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702648210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3702648210
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1865512933
Short name T791
Test name
Test status
Simulation time 27510767 ps
CPU time 0.95 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 214980 kb
Host smart-914500c0-53cb-42f4-9adc-78850e558556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865512933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1865512933
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2334356156
Short name T615
Test name
Test status
Simulation time 46907876 ps
CPU time 0.94 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 214920 kb
Host smart-a7f62fd2-0e80-4637-9750-801a99ec1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334356156 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2334356156
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.585640239
Short name T746
Test name
Test status
Simulation time 569571936 ps
CPU time 6.14 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:14 PM PDT 24
Peak memory 217944 kb
Host smart-1954d2ca-fdf8-487e-8c7b-f8d53ee43c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585640239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.585640239
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1701798167
Short name T627
Test name
Test status
Simulation time 253191080070 ps
CPU time 1702 seconds
Started Jun 02 02:44:08 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 226308 kb
Host smart-6298afb1-e40a-4fac-82d6-0d25d3f6d036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701798167 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1701798167
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.3794037547
Short name T783
Test name
Test status
Simulation time 2289028061 ps
CPU time 71.65 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:46:30 PM PDT 24
Peak memory 219756 kb
Host smart-22d6ae9d-6948-405f-bcc6-83dad4d85d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794037547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.3794037547
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2630960235
Short name T502
Test name
Test status
Simulation time 73462006 ps
CPU time 1.38 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 217808 kb
Host smart-fea820f1-4607-4b13-9506-ecb304ded0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630960235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2630960235
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2409346694
Short name T613
Test name
Test status
Simulation time 38909851 ps
CPU time 1.49 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216932 kb
Host smart-d1636055-4bca-4986-a79f-8bed341c3c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409346694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2409346694
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.1916790106
Short name T9
Test name
Test status
Simulation time 525894585 ps
CPU time 4.16 seconds
Started Jun 02 02:45:29 PM PDT 24
Finished Jun 02 02:45:33 PM PDT 24
Peak memory 216812 kb
Host smart-595ffb3f-139a-45a4-8521-3f64da43d554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916790106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.1916790106
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2502576234
Short name T283
Test name
Test status
Simulation time 42576218 ps
CPU time 1.72 seconds
Started Jun 02 02:45:02 PM PDT 24
Finished Jun 02 02:45:04 PM PDT 24
Peak memory 218056 kb
Host smart-a98a78da-1e8e-4987-967a-b901d7a8110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502576234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2502576234
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1137268445
Short name T820
Test name
Test status
Simulation time 75901138 ps
CPU time 1.1 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216640 kb
Host smart-02d198a8-69a9-40b5-a565-61c44e4812a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137268445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1137268445
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1882321558
Short name T467
Test name
Test status
Simulation time 43496127 ps
CPU time 1.56 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 217892 kb
Host smart-1ba2d8a6-28bc-40fc-a35b-3ed676b1c2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882321558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1882321558
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1050268109
Short name T770
Test name
Test status
Simulation time 113604996 ps
CPU time 1.36 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 215548 kb
Host smart-2b57a8de-1445-4c76-9b2a-ec7b8017ebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050268109 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1050268109
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.547524140
Short name T335
Test name
Test status
Simulation time 55622669 ps
CPU time 0.92 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 206208 kb
Host smart-cf49139b-fa81-426a-a5e9-f0a967a49689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547524140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.547524140
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4049390805
Short name T571
Test name
Test status
Simulation time 26321916 ps
CPU time 1.09 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216600 kb
Host smart-279fbef6-3d46-4584-9c50-ac8603291523
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049390805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4049390805
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.1714411870
Short name T365
Test name
Test status
Simulation time 61403998 ps
CPU time 1.2 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 225028 kb
Host smart-c1b8e42a-c9d8-4975-9fef-b8d8afaa291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714411870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1714411870
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3341279595
Short name T763
Test name
Test status
Simulation time 61585309 ps
CPU time 1.47 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 218276 kb
Host smart-26b77d44-3d41-4cb3-aab2-fbf1495068b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341279595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3341279595
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.3409626412
Short name T313
Test name
Test status
Simulation time 26426307 ps
CPU time 0.97 seconds
Started Jun 02 02:43:59 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 215052 kb
Host smart-95435b70-46dd-4f14-a982-aab3c4dfcc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409626412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3409626412
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.3082188434
Short name T459
Test name
Test status
Simulation time 77817113 ps
CPU time 0.93 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 214944 kb
Host smart-6997ad51-95f4-4c2a-9d3c-d69bae8cf241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082188434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3082188434
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1067894493
Short name T268
Test name
Test status
Simulation time 556671407 ps
CPU time 3.36 seconds
Started Jun 02 02:43:54 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 214928 kb
Host smart-6b83ca4a-f990-454a-a26f-54a17270aa18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067894493 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1067894493
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/180.edn_genbits.4157090562
Short name T619
Test name
Test status
Simulation time 68374226 ps
CPU time 2.35 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 219688 kb
Host smart-b1ea9fa3-5258-4b28-a3b2-27bf1630034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157090562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.4157090562
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3380204746
Short name T778
Test name
Test status
Simulation time 65310537 ps
CPU time 1.42 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 218196 kb
Host smart-8a7f0dc6-ce94-4721-86ec-da287cab6399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380204746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3380204746
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.639785798
Short name T348
Test name
Test status
Simulation time 78713942 ps
CPU time 1.25 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 218184 kb
Host smart-c0b91c55-18d2-40b5-a9cc-9d36d8b9f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639785798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.639785798
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1092636615
Short name T267
Test name
Test status
Simulation time 40825678 ps
CPU time 1.11 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 216676 kb
Host smart-8bc4152b-d649-4e87-9fe6-97bfbda7fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092636615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1092636615
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2521102466
Short name T626
Test name
Test status
Simulation time 43978628 ps
CPU time 1.25 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 217644 kb
Host smart-b1882691-67d4-476d-91cc-dff683190f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521102466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2521102466
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.643451901
Short name T724
Test name
Test status
Simulation time 37953466 ps
CPU time 1.49 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 217832 kb
Host smart-adc4e789-ea4f-4beb-8796-5c677ec348cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643451901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.643451901
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2368400452
Short name T355
Test name
Test status
Simulation time 41292147 ps
CPU time 1.5 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 218008 kb
Host smart-73c53f3b-cef8-4f46-a908-f813bebde228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368400452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2368400452
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3010792284
Short name T808
Test name
Test status
Simulation time 44981051 ps
CPU time 1.42 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 217612 kb
Host smart-afbc648a-8b27-4dc2-9efd-ba017c1bd55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010792284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3010792284
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1390632058
Short name T229
Test name
Test status
Simulation time 28945481 ps
CPU time 1.31 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 216636 kb
Host smart-5961e0ea-8550-43f8-bea6-3a7897b717ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390632058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1390632058
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1269525029
Short name T433
Test name
Test status
Simulation time 116833577 ps
CPU time 1.25 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 216740 kb
Host smart-8a133adb-a0de-496d-89e1-bba5b8291ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269525029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1269525029
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.255011837
Short name T351
Test name
Test status
Simulation time 73625375 ps
CPU time 0.99 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 214656 kb
Host smart-d35a9af4-895c-4307-8d95-a0981b625f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255011837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.255011837
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.21796465
Short name T62
Test name
Test status
Simulation time 39937239 ps
CPU time 0.85 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 215164 kb
Host smart-877fb068-97f5-494b-9bd2-99b71165155f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21796465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.21796465
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.3165335738
Short name T831
Test name
Test status
Simulation time 55815363 ps
CPU time 1.38 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 219224 kb
Host smart-bd25a3ad-c12e-4ec5-96de-72dfac6798d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165335738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3165335738
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1366088563
Short name T623
Test name
Test status
Simulation time 192603486 ps
CPU time 2.41 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216880 kb
Host smart-d130d7cf-a8ff-4cf9-a1fb-d7a2ca9fda11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366088563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1366088563
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2287836286
Short name T110
Test name
Test status
Simulation time 20938003 ps
CPU time 1.07 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 215292 kb
Host smart-3b473c31-0e9d-4101-b9b6-99ce0b6dd6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287836286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2287836286
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2625840057
Short name T553
Test name
Test status
Simulation time 15742487 ps
CPU time 0.97 seconds
Started Jun 02 02:43:59 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 214888 kb
Host smart-f135a641-5701-4fbe-b552-608687adb147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625840057 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2625840057
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2047811884
Short name T496
Test name
Test status
Simulation time 153805190 ps
CPU time 3.5 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:14 PM PDT 24
Peak memory 216532 kb
Host smart-934a4e50-800b-4a4d-b6f5-f82e6ecefb7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047811884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2047811884
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3854712369
Short name T510
Test name
Test status
Simulation time 181641948644 ps
CPU time 653.37 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:55:06 PM PDT 24
Peak memory 219264 kb
Host smart-bc685295-6c41-4142-9237-21adb9361a06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854712369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3854712369
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1583769011
Short name T344
Test name
Test status
Simulation time 54283589 ps
CPU time 1.15 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 216688 kb
Host smart-a53101fb-a8cd-475d-ad5e-7e0226eb6901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583769011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1583769011
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3123087367
Short name T703
Test name
Test status
Simulation time 87997303 ps
CPU time 1.25 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 217900 kb
Host smart-2239cd5d-1ac4-4c7a-bfce-f8f02183634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123087367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3123087367
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3228348099
Short name T537
Test name
Test status
Simulation time 93246779 ps
CPU time 1.32 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 219136 kb
Host smart-2ef2d442-da74-41eb-839f-55085cc8abd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228348099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3228348099
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.196683631
Short name T492
Test name
Test status
Simulation time 90443458 ps
CPU time 1.31 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 218184 kb
Host smart-043146b2-cacd-4e48-a733-65d20ed6fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196683631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.196683631
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3280346608
Short name T617
Test name
Test status
Simulation time 62326380 ps
CPU time 1.24 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 218280 kb
Host smart-3fd452f2-2755-42c9-9d6c-9681edc7ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280346608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3280346608
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2560299296
Short name T22
Test name
Test status
Simulation time 94326586 ps
CPU time 1.19 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 217952 kb
Host smart-922722e2-22be-455c-af9a-c8c8c0f20a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560299296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2560299296
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3422901502
Short name T656
Test name
Test status
Simulation time 57008144 ps
CPU time 1.39 seconds
Started Jun 02 02:45:24 PM PDT 24
Finished Jun 02 02:45:26 PM PDT 24
Peak memory 216772 kb
Host smart-282956b4-82ff-4737-8c6e-966980a65efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422901502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3422901502
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.275947657
Short name T394
Test name
Test status
Simulation time 90663553 ps
CPU time 1.21 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 217020 kb
Host smart-59a1052c-e823-45fb-bbea-51a6e289482a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275947657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.275947657
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.53617480
Short name T805
Test name
Test status
Simulation time 86198864 ps
CPU time 0.99 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 216588 kb
Host smart-205e0fd9-2927-4eb7-a7d4-8694c1542a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53617480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.53617480
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.198604119
Short name T290
Test name
Test status
Simulation time 121902252 ps
CPU time 2.79 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 217044 kb
Host smart-04ae7a5f-7df9-4b76-acd1-39f673e03b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198604119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.198604119
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2664005019
Short name T825
Test name
Test status
Simulation time 29313045 ps
CPU time 1.13 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 215284 kb
Host smart-bbec0faf-2b33-46dd-ac2d-6b3db3c3ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664005019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2664005019
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3279167975
Short name T397
Test name
Test status
Simulation time 13549593 ps
CPU time 0.9 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 206296 kb
Host smart-884a5331-bef8-48df-9cf2-18db3136cbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279167975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3279167975
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.8999242
Short name T590
Test name
Test status
Simulation time 12929577 ps
CPU time 0.91 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:36 PM PDT 24
Peak memory 215796 kb
Host smart-76b77eef-b4d5-46c2-a7ac-1d27446e1412
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8999242 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.8999242
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1221218714
Short name T48
Test name
Test status
Simulation time 36046764 ps
CPU time 0.98 seconds
Started Jun 02 02:43:36 PM PDT 24
Finished Jun 02 02:43:38 PM PDT 24
Peak memory 218000 kb
Host smart-80f1329f-cb61-4d7c-8ef2-92e8b8786b40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221218714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1221218714
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3647417930
Short name T76
Test name
Test status
Simulation time 35134407 ps
CPU time 0.96 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 223548 kb
Host smart-ed2e38af-f5e7-4236-b0de-a96df64f9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647417930 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3647417930
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4169235211
Short name T120
Test name
Test status
Simulation time 112158770 ps
CPU time 1.27 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:47 PM PDT 24
Peak memory 216860 kb
Host smart-2dec998e-4a88-48f6-a204-ad2950cd4c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169235211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4169235211
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.380267066
Short name T315
Test name
Test status
Simulation time 25138047 ps
CPU time 0.93 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:43:38 PM PDT 24
Peak memory 215004 kb
Host smart-827c4ada-9ad0-464c-9093-a4dfc1d83c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380267066 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.380267066
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.143063974
Short name T105
Test name
Test status
Simulation time 27469514 ps
CPU time 0.91 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:43:39 PM PDT 24
Peak memory 206772 kb
Host smart-c9855163-c1db-4b98-8998-c79183c8c41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143063974 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.143063974
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2098794930
Short name T130
Test name
Test status
Simulation time 583105772 ps
CPU time 8.85 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 236108 kb
Host smart-5523bb17-c822-453a-a681-2b743bea836d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098794930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2098794930
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2886431740
Short name T302
Test name
Test status
Simulation time 15001491 ps
CPU time 0.93 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 214824 kb
Host smart-78396207-d656-4335-ac3b-40ff497e65d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886431740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2886431740
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.960364501
Short name T575
Test name
Test status
Simulation time 71964618 ps
CPU time 1.96 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 217856 kb
Host smart-f83aee7c-9380-41dd-9712-fea2ac532e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960364501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.960364501
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4173572286
Short name T764
Test name
Test status
Simulation time 27469390402 ps
CPU time 693.42 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:55:04 PM PDT 24
Peak memory 217180 kb
Host smart-6c4d39b1-41cf-4df3-aa1c-3797680eb313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173572286 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4173572286
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2017300775
Short name T824
Test name
Test status
Simulation time 26705434 ps
CPU time 1.27 seconds
Started Jun 02 02:43:59 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 215312 kb
Host smart-8858eb63-9d53-40d5-8594-f70c3825a299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017300775 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2017300775
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2361628285
Short name T500
Test name
Test status
Simulation time 59920636 ps
CPU time 0.93 seconds
Started Jun 02 02:44:04 PM PDT 24
Finished Jun 02 02:44:06 PM PDT 24
Peak memory 206248 kb
Host smart-d953b874-252f-4eeb-92ab-94f37a2b991e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361628285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2361628285
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3356352099
Short name T182
Test name
Test status
Simulation time 15707824 ps
CPU time 0.87 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 215168 kb
Host smart-b52bb4c7-55c1-4d05-831d-ae5e184f66b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356352099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3356352099
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1917580502
Short name T720
Test name
Test status
Simulation time 66772942 ps
CPU time 1.23 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 216516 kb
Host smart-cc6d9fe8-7396-4efc-9f9b-3d586e1f7ea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917580502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1917580502
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.460358106
Short name T660
Test name
Test status
Simulation time 72901113 ps
CPU time 1.22 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 224872 kb
Host smart-ef79ce12-9617-46d5-9af1-38e12666ba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460358106 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.460358106
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1349960737
Short name T470
Test name
Test status
Simulation time 98912733 ps
CPU time 1.19 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216752 kb
Host smart-2abd3cf1-a8c3-4b5d-a784-ad998d9aff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349960737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1349960737
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2664352592
Short name T387
Test name
Test status
Simulation time 40692924 ps
CPU time 0.89 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:03 PM PDT 24
Peak memory 215136 kb
Host smart-a71658ee-2dfb-4e5a-bdaf-4ed372972e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664352592 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2664352592
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1530072066
Short name T511
Test name
Test status
Simulation time 24037340 ps
CPU time 0.91 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 214952 kb
Host smart-4d9e9d77-3a57-44de-8888-75143aa1a7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530072066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1530072066
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3154044657
Short name T754
Test name
Test status
Simulation time 89962128 ps
CPU time 1.57 seconds
Started Jun 02 02:43:52 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 217880 kb
Host smart-5c6ae88c-f57f-4dcf-99d5-c96135a92217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154044657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3154044657
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/200.edn_genbits.3525116764
Short name T361
Test name
Test status
Simulation time 249929045 ps
CPU time 1.52 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 216768 kb
Host smart-f556799c-a9b2-4916-8f2b-6bace55e40ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525116764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3525116764
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2051460685
Short name T823
Test name
Test status
Simulation time 61430568 ps
CPU time 1.14 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 217024 kb
Host smart-5fcecdb2-b4d3-4538-bf1d-28dafb6828b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051460685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2051460685
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2211669694
Short name T653
Test name
Test status
Simulation time 51382809 ps
CPU time 1.95 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:30 PM PDT 24
Peak memory 217888 kb
Host smart-6892cdf4-ebd5-4c94-b5d1-6226088927f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211669694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2211669694
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2781382765
Short name T699
Test name
Test status
Simulation time 25182841 ps
CPU time 1.18 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 216572 kb
Host smart-ca194a80-2f68-4193-9ad0-29dc1b8ee48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781382765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2781382765
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.60753940
Short name T383
Test name
Test status
Simulation time 56662724 ps
CPU time 1.48 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:28 PM PDT 24
Peak memory 216744 kb
Host smart-667ff484-8027-4b51-9522-924600a19faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60753940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.60753940
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.981469659
Short name T399
Test name
Test status
Simulation time 42201590 ps
CPU time 1.41 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 217880 kb
Host smart-e0f1d82c-3f65-485e-b3ef-92f0f4aa8cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981469659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.981469659
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3250849757
Short name T432
Test name
Test status
Simulation time 52133032 ps
CPU time 1.36 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 219264 kb
Host smart-16cc9ca6-ed50-4a8e-9ccf-d81f1a2a3e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250849757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3250849757
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3871688035
Short name T442
Test name
Test status
Simulation time 36690583 ps
CPU time 1.32 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 217660 kb
Host smart-ba77e8ca-63cb-478b-9bc6-9f985a60ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871688035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3871688035
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2689287942
Short name T532
Test name
Test status
Simulation time 164038588 ps
CPU time 1.05 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 216576 kb
Host smart-0de67357-0090-4cc3-a4aa-474074bc8411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689287942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2689287942
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3466491526
Short name T326
Test name
Test status
Simulation time 87871714 ps
CPU time 2.98 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 219720 kb
Host smart-0ad32dff-5cb6-415e-8df3-7a00fe052dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466491526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3466491526
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2798049976
Short name T587
Test name
Test status
Simulation time 13235881 ps
CPU time 0.89 seconds
Started Jun 02 02:44:11 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 206628 kb
Host smart-9a7df8ee-284a-49cf-9287-275b72f7c7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798049976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2798049976
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_err.3135181364
Short name T772
Test name
Test status
Simulation time 44093102 ps
CPU time 1.08 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:57 PM PDT 24
Peak memory 219344 kb
Host smart-6f95301e-d1f8-4d83-a08a-ba08e3eb3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135181364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3135181364
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.546850279
Short name T481
Test name
Test status
Simulation time 55701504 ps
CPU time 1.48 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 218044 kb
Host smart-037febb1-4b6c-4ec1-92ad-ff3d19880417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546850279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.546850279
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3818882721
Short name T298
Test name
Test status
Simulation time 26302101 ps
CPU time 0.93 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 215136 kb
Host smart-f8cd5af5-bfe4-4274-8753-c852353c65f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818882721 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3818882721
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1949345802
Short name T750
Test name
Test status
Simulation time 44818366 ps
CPU time 0.93 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 214924 kb
Host smart-c16ff6de-d3a0-4c9a-8c37-95706cff21ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949345802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1949345802
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.363525931
Short name T722
Test name
Test status
Simulation time 260172817 ps
CPU time 5.21 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 216572 kb
Host smart-feaab6e7-b8a8-4a89-8bf0-682d2bbe80a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363525931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.363525931
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2731280948
Short name T769
Test name
Test status
Simulation time 351128151419 ps
CPU time 2063.16 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 03:18:39 PM PDT 24
Peak memory 226460 kb
Host smart-f70955bc-0b45-4a2e-9694-66907d1b0af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731280948 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2731280948
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3149904237
Short name T738
Test name
Test status
Simulation time 71865014 ps
CPU time 1.37 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 218092 kb
Host smart-d4983da1-1eb3-4ebc-ac0c-523dfe138967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149904237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3149904237
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2735890676
Short name T713
Test name
Test status
Simulation time 45989483 ps
CPU time 1.82 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 217964 kb
Host smart-cf623195-7ba7-4fc0-b81a-23c2ff4982df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735890676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2735890676
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3254339103
Short name T561
Test name
Test status
Simulation time 140543456 ps
CPU time 1 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216596 kb
Host smart-0dee449e-4fbd-46e8-881e-3ac49d5c8c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254339103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3254339103
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3178693318
Short name T485
Test name
Test status
Simulation time 64969128 ps
CPU time 1.54 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:29 PM PDT 24
Peak memory 217844 kb
Host smart-4abc07a4-b9c4-41bc-9d1e-fd6e45654283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178693318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3178693318
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.446094789
Short name T406
Test name
Test status
Simulation time 88182774 ps
CPU time 1.14 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216700 kb
Host smart-6b514c4a-adfb-4677-8871-809d31eabe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446094789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.446094789
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1835325341
Short name T287
Test name
Test status
Simulation time 75758649 ps
CPU time 1.04 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 216712 kb
Host smart-052fbe47-f42d-4b0c-b0f8-320cd89668b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835325341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1835325341
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.333879031
Short name T655
Test name
Test status
Simulation time 37204347 ps
CPU time 1.44 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 219368 kb
Host smart-3d43afc1-dc92-4839-9421-baa1e6921dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333879031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.333879031
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1586545891
Short name T744
Test name
Test status
Simulation time 98307223 ps
CPU time 1.14 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216724 kb
Host smart-da0f5405-4361-435e-a91c-7abcd714ba01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586545891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1586545891
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.122760302
Short name T839
Test name
Test status
Simulation time 78267012 ps
CPU time 1.14 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 218184 kb
Host smart-557c673b-cbf1-409d-a1ac-52adb0d38ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122760302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.122760302
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3743109787
Short name T260
Test name
Test status
Simulation time 20170630 ps
CPU time 1.04 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216628 kb
Host smart-c4966772-bd3a-4d72-bc50-efa66d4b720c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743109787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3743109787
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2891267558
Short name T35
Test name
Test status
Simulation time 48985032 ps
CPU time 1.2 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 215348 kb
Host smart-4ae68940-b128-4fc2-81a3-150dc4a69fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891267558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2891267558
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1443491013
Short name T359
Test name
Test status
Simulation time 31167245 ps
CPU time 0.94 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 206240 kb
Host smart-2fae0d61-86b8-4f32-938f-71797c8155d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443491013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1443491013
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3051589084
Short name T677
Test name
Test status
Simulation time 32433725 ps
CPU time 0.88 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 216020 kb
Host smart-d8096587-b883-49e7-b61a-23b3a616caeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051589084 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3051589084
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1167436193
Short name T434
Test name
Test status
Simulation time 43614551 ps
CPU time 0.98 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 216688 kb
Host smart-1afbe069-df55-429b-ab3b-81a33aa6ac19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167436193 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1167436193
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.764893449
Short name T600
Test name
Test status
Simulation time 20342469 ps
CPU time 1.15 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:20 PM PDT 24
Peak memory 219396 kb
Host smart-9b31099a-b335-4292-8ab2-89ecd41c7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764893449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.764893449
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.122849733
Short name T469
Test name
Test status
Simulation time 53783183 ps
CPU time 1.19 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 216656 kb
Host smart-b9ff66d1-0499-4af5-968a-755f0895a6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122849733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.122849733
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.3697531479
Short name T762
Test name
Test status
Simulation time 43295435 ps
CPU time 0.95 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 214900 kb
Host smart-f12a84e8-097b-4403-b897-013c02fb9f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697531479 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3697531479
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1401343187
Short name T373
Test name
Test status
Simulation time 83849643 ps
CPU time 1.56 seconds
Started Jun 02 02:43:55 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 214992 kb
Host smart-ade986c0-c347-4022-8042-01c6a7a157b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401343187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1401343187
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3117317240
Short name T668
Test name
Test status
Simulation time 76774592279 ps
CPU time 1110.11 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 03:02:34 PM PDT 24
Peak memory 220620 kb
Host smart-8634eaff-ff08-443c-906e-fdc49c52ca9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117317240 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3117317240
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.819839095
Short name T453
Test name
Test status
Simulation time 79738167 ps
CPU time 1.48 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 218108 kb
Host smart-f7b09e5c-4c43-456d-9a84-3398332860fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819839095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.819839095
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2083334383
Short name T566
Test name
Test status
Simulation time 71759950 ps
CPU time 1.15 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 216800 kb
Host smart-4867d66c-01bb-4b01-99fa-70e8ba1c39d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083334383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2083334383
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3788537209
Short name T669
Test name
Test status
Simulation time 49876571 ps
CPU time 0.99 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216556 kb
Host smart-1a42a03d-7718-4a94-8821-5fc7211aca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788537209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3788537209
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3172116354
Short name T529
Test name
Test status
Simulation time 45678022 ps
CPU time 1.55 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 219092 kb
Host smart-023c589f-9d24-41a0-8b55-380c6553ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172116354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3172116354
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.243874859
Short name T390
Test name
Test status
Simulation time 110921392 ps
CPU time 1.01 seconds
Started Jun 02 02:45:44 PM PDT 24
Finished Jun 02 02:45:46 PM PDT 24
Peak memory 216624 kb
Host smart-c08344c7-a4ed-4bf1-bd1e-af355158a6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243874859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.243874859
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1266914151
Short name T427
Test name
Test status
Simulation time 66853568 ps
CPU time 1.01 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 216788 kb
Host smart-2e95599f-dcb5-4c79-96ce-17f41602ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266914151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1266914151
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3842999451
Short name T826
Test name
Test status
Simulation time 56401755 ps
CPU time 1.66 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 218300 kb
Host smart-44dc059b-0fa4-4049-9911-8e73a059f88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842999451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3842999451
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.286368971
Short name T392
Test name
Test status
Simulation time 26580633 ps
CPU time 1.14 seconds
Started Jun 02 02:45:31 PM PDT 24
Finished Jun 02 02:45:33 PM PDT 24
Peak memory 219300 kb
Host smart-94db5951-3fa9-4169-8203-fa02dfae591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286368971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.286368971
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3592903905
Short name T609
Test name
Test status
Simulation time 148609784 ps
CPU time 2.81 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 219684 kb
Host smart-c47a7f76-4a40-4fc8-9346-5a9d04252185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592903905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3592903905
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.14033070
Short name T527
Test name
Test status
Simulation time 30518316 ps
CPU time 1.32 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:12 PM PDT 24
Peak memory 215300 kb
Host smart-c4f681dd-6452-49f7-9fee-4034e0b9dcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14033070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.14033070
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2210488715
Short name T476
Test name
Test status
Simulation time 32758064 ps
CPU time 0.87 seconds
Started Jun 02 02:44:04 PM PDT 24
Finished Jun 02 02:44:06 PM PDT 24
Peak memory 214524 kb
Host smart-bf097a64-f0c2-4590-8d27-402e2cfe4f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210488715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2210488715
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.398700767
Short name T65
Test name
Test status
Simulation time 27666730 ps
CPU time 0.8 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 215960 kb
Host smart-839bcb73-47ef-4631-ac1c-96889893812a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398700767 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.398700767
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.267431754
Short name T379
Test name
Test status
Simulation time 71292927 ps
CPU time 1.3 seconds
Started Jun 02 02:43:52 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 216756 kb
Host smart-3b6dd3a0-2da1-43f8-8c6e-65c7c155ed47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267431754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.267431754
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3234344693
Short name T594
Test name
Test status
Simulation time 75002846 ps
CPU time 1.26 seconds
Started Jun 02 02:44:05 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 225120 kb
Host smart-5f940d08-5e66-46e7-8eaa-e4229cadf3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234344693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3234344693
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3941842904
Short name T3
Test name
Test status
Simulation time 45751939 ps
CPU time 1.45 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 217756 kb
Host smart-c8188604-796d-4713-a245-c0c0d532ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941842904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3941842904
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.777642651
Short name T761
Test name
Test status
Simulation time 31360257 ps
CPU time 0.94 seconds
Started Jun 02 02:43:59 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 214964 kb
Host smart-2f44c429-39b5-40e0-8bcb-cbfe2989e130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777642651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.777642651
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1431911338
Short name T640
Test name
Test status
Simulation time 18224870 ps
CPU time 1.02 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 214952 kb
Host smart-321033a0-0cce-4b3e-9f87-06aac796fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431911338 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1431911338
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2484974382
Short name T760
Test name
Test status
Simulation time 405095770 ps
CPU time 2.61 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 219236 kb
Host smart-28e5a5c8-e8c9-4302-a541-563f0ab8453f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484974382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2484974382
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2966254450
Short name T197
Test name
Test status
Simulation time 88055437336 ps
CPU time 1876.29 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 03:15:29 PM PDT 24
Peak memory 225260 kb
Host smart-c2553e46-5c5c-45e3-9bd2-ca95dc085b5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966254450 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2966254450
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1615790132
Short name T734
Test name
Test status
Simulation time 53785042 ps
CPU time 1.2 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 219252 kb
Host smart-24ebfb06-0978-4223-958e-f0dfed49fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615790132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1615790132
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1636872554
Short name T441
Test name
Test status
Simulation time 43566097 ps
CPU time 1.2 seconds
Started Jun 02 02:45:03 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 217732 kb
Host smart-154e6eee-9477-40e3-a526-3fa355f30e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636872554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1636872554
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2713560860
Short name T380
Test name
Test status
Simulation time 42951668 ps
CPU time 1.4 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216620 kb
Host smart-6b6b5e52-59e5-4cca-a209-1ffcf4db5bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713560860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2713560860
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1861119762
Short name T786
Test name
Test status
Simulation time 64812363 ps
CPU time 1.29 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216764 kb
Host smart-0e16b8c3-43ca-42b4-abf5-2523a2e36aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861119762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1861119762
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.46723543
Short name T489
Test name
Test status
Simulation time 60486073 ps
CPU time 1.39 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 214968 kb
Host smart-f369a764-ebf5-402e-b5ec-546191fbc66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46723543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.46723543
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3838784096
Short name T718
Test name
Test status
Simulation time 258616014 ps
CPU time 1.19 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216948 kb
Host smart-cd317522-8ccd-4935-8f44-77878fd2098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838784096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3838784096
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1309059281
Short name T689
Test name
Test status
Simulation time 194216995 ps
CPU time 1.06 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 216640 kb
Host smart-cce7200f-78e7-451d-9301-e92729ccd902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309059281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1309059281
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1085718332
Short name T482
Test name
Test status
Simulation time 34073515 ps
CPU time 1.36 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 219324 kb
Host smart-76e0a0cd-0823-4c46-8093-f22ecfd319e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085718332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1085718332
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4106522082
Short name T463
Test name
Test status
Simulation time 61353684 ps
CPU time 1.11 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:20 PM PDT 24
Peak memory 215344 kb
Host smart-1bcbc4b8-410e-483b-81ea-06df83fb310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106522082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4106522082
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2112243709
Short name T596
Test name
Test status
Simulation time 18480963 ps
CPU time 0.94 seconds
Started Jun 02 02:44:16 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 206252 kb
Host smart-1c56b37f-cd67-491b-9685-cfe6aedb5d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112243709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2112243709
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1520672629
Short name T90
Test name
Test status
Simulation time 158392237 ps
CPU time 0.86 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:08 PM PDT 24
Peak memory 216132 kb
Host smart-574c2811-a5ac-4741-bfe9-bf35dc587e2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520672629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1520672629
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.997543693
Short name T773
Test name
Test status
Simulation time 50322365 ps
CPU time 1.66 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 216688 kb
Host smart-f7aef6ba-14d3-43c4-aff8-78e0f26b04e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997543693 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.997543693
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.762650499
Short name T63
Test name
Test status
Simulation time 39182133 ps
CPU time 0.99 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 223276 kb
Host smart-b85101d7-4345-4911-be25-5e30c548ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762650499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.762650499
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3833930579
Short name T681
Test name
Test status
Simulation time 49764158 ps
CPU time 1.24 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 217776 kb
Host smart-094433cd-b1d9-49d4-952d-7f9de932b4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833930579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3833930579
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.243828080
Short name T755
Test name
Test status
Simulation time 23401259 ps
CPU time 1.12 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 214996 kb
Host smart-8d766edd-acd1-4994-b51e-af38dd06e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243828080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.243828080
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.997923395
Short name T295
Test name
Test status
Simulation time 23424092 ps
CPU time 0.93 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 214872 kb
Host smart-623424da-23de-45a8-9eae-0ef8779357b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997923395 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.997923395
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2069687551
Short name T466
Test name
Test status
Simulation time 129823271 ps
CPU time 2.04 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:05 PM PDT 24
Peak memory 216660 kb
Host smart-856eb8ba-519f-418c-a5b5-fcf01f02703a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069687551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2069687551
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/240.edn_genbits.1521092458
Short name T601
Test name
Test status
Simulation time 51475978 ps
CPU time 1.83 seconds
Started Jun 02 02:45:24 PM PDT 24
Finished Jun 02 02:45:27 PM PDT 24
Peak memory 218764 kb
Host smart-bb6419ae-7f74-46ae-9133-2d9fd4be294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521092458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1521092458
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1924029932
Short name T732
Test name
Test status
Simulation time 69708104 ps
CPU time 1.22 seconds
Started Jun 02 02:45:29 PM PDT 24
Finished Jun 02 02:45:31 PM PDT 24
Peak memory 218260 kb
Host smart-6025fcaa-3fa3-4e6b-abe8-6268076007c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924029932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1924029932
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.546220208
Short name T367
Test name
Test status
Simulation time 35121790 ps
CPU time 1.35 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 216616 kb
Host smart-f8e3156b-44ce-4b6f-b7ec-2ff2c9cc8761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546220208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.546220208
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3322153004
Short name T448
Test name
Test status
Simulation time 71669262 ps
CPU time 1.11 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 219444 kb
Host smart-fe4361ff-6fbd-49a6-8256-1c77342d839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322153004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3322153004
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2853323560
Short name T569
Test name
Test status
Simulation time 85276922 ps
CPU time 1.45 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:28 PM PDT 24
Peak memory 218188 kb
Host smart-3af40e1a-6603-44f9-a6c1-8b9ca481751f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853323560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2853323560
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.574187425
Short name T691
Test name
Test status
Simulation time 47678708 ps
CPU time 1.85 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 217704 kb
Host smart-c6389332-4efd-490e-93eb-bd2054a671b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574187425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.574187425
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2329867380
Short name T607
Test name
Test status
Simulation time 340315251 ps
CPU time 2.04 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 218204 kb
Host smart-7ef61a37-f910-4820-adc1-bd468ab5b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329867380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2329867380
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.913519544
Short name T785
Test name
Test status
Simulation time 382584663 ps
CPU time 2.02 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 218220 kb
Host smart-1dd3cf0a-d745-4b92-9314-2ccb41eb1f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913519544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.913519544
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1191148775
Short name T241
Test name
Test status
Simulation time 42172802 ps
CPU time 1.63 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 217972 kb
Host smart-ba47e5da-8176-4114-b5c9-5e56a4ad3e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191148775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1191148775
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.636150600
Short name T357
Test name
Test status
Simulation time 184053360 ps
CPU time 1.18 seconds
Started Jun 02 02:45:24 PM PDT 24
Finished Jun 02 02:45:26 PM PDT 24
Peak memory 216656 kb
Host smart-ee8f472d-11e4-4b03-b3c3-bd8159a9bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636150600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.636150600
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.1080824791
Short name T347
Test name
Test status
Simulation time 29316805 ps
CPU time 0.97 seconds
Started Jun 02 02:44:11 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 214424 kb
Host smart-4321ade2-53ae-4b43-a434-ef5953aa945a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080824791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1080824791
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2210921588
Short name T386
Test name
Test status
Simulation time 38196089 ps
CPU time 0.9 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 215780 kb
Host smart-6136e85f-8222-4d5e-89fa-b8b7f1e6e75a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210921588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2210921588
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3603601122
Short name T802
Test name
Test status
Simulation time 69067867 ps
CPU time 0.97 seconds
Started Jun 02 02:44:16 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 218060 kb
Host smart-565c41c9-d9cf-409d-8f78-bc393a1cced9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603601122 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3603601122
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2236409749
Short name T91
Test name
Test status
Simulation time 21977806 ps
CPU time 1.04 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 223452 kb
Host smart-ee2e37c2-c874-46ab-9b22-02e653cd8285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236409749 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2236409749
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.701606771
Short name T712
Test name
Test status
Simulation time 42809293 ps
CPU time 1.14 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216884 kb
Host smart-d99e53b5-3d6e-4e58-99b2-74382eb19bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701606771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.701606771
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1907979861
Short name T632
Test name
Test status
Simulation time 28515668 ps
CPU time 0.95 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 215684 kb
Host smart-04ec1bf6-3b70-4ad6-8603-ff8bb4837038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907979861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1907979861
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3578864876
Short name T317
Test name
Test status
Simulation time 16743508 ps
CPU time 0.99 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 214964 kb
Host smart-67ae84cb-0324-4b7e-8470-be77d21197e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578864876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3578864876
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.375576839
Short name T733
Test name
Test status
Simulation time 309089941 ps
CPU time 3.68 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216520 kb
Host smart-c6b9fb2e-eee4-47f6-a6c3-d4246f6ecfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375576839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.375576839
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2997424823
Short name T339
Test name
Test status
Simulation time 74762185526 ps
CPU time 937.58 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:59:45 PM PDT 24
Peak memory 223304 kb
Host smart-dad6667d-8b91-4e26-befd-a7d4f0182a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997424823 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2997424823
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3520681697
Short name T320
Test name
Test status
Simulation time 41883313 ps
CPU time 1.03 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 216732 kb
Host smart-6bd66d31-0fbe-4b7f-8202-1440c1a53b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520681697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3520681697
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.634306218
Short name T723
Test name
Test status
Simulation time 95599464 ps
CPU time 1.21 seconds
Started Jun 02 02:45:46 PM PDT 24
Finished Jun 02 02:45:48 PM PDT 24
Peak memory 218740 kb
Host smart-eb7756ca-1d3a-4ba5-a8c2-81c6785dc0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634306218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.634306218
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2771481930
Short name T816
Test name
Test status
Simulation time 38901640 ps
CPU time 1.1 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 217872 kb
Host smart-67f58c25-28e2-4048-ac80-914009bd9aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771481930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2771481930
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1046953473
Short name T291
Test name
Test status
Simulation time 41570072 ps
CPU time 1.31 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 217128 kb
Host smart-1805a984-a37e-4dca-9336-da142d175423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046953473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1046953473
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1146172215
Short name T332
Test name
Test status
Simulation time 48386500 ps
CPU time 1.63 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 217932 kb
Host smart-19a6c806-42dd-4545-a1b8-566347e29c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146172215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1146172215
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3814543691
Short name T116
Test name
Test status
Simulation time 49486168 ps
CPU time 1.32 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 216656 kb
Host smart-6e2d9dcb-98ba-44b7-ba0a-b17c69bdea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814543691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3814543691
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2128102304
Short name T226
Test name
Test status
Simulation time 97890440 ps
CPU time 1.25 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 216488 kb
Host smart-0b21f5b1-98f4-486a-b1bd-61c42e0a31ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128102304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2128102304
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1342342939
Short name T535
Test name
Test status
Simulation time 37385080 ps
CPU time 1.33 seconds
Started Jun 02 02:45:23 PM PDT 24
Finished Jun 02 02:45:25 PM PDT 24
Peak memory 216548 kb
Host smart-27ad9d9a-4d65-46ff-8305-72d85500dc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342342939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1342342939
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1633865740
Short name T338
Test name
Test status
Simulation time 45064927 ps
CPU time 1.66 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 217708 kb
Host smart-8b7fa985-d322-4f18-a78d-306732ce03da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633865740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1633865740
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4230559552
Short name T517
Test name
Test status
Simulation time 62529288 ps
CPU time 0.98 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 216552 kb
Host smart-6771273b-f7e4-452c-bcbb-3e67f4f3b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230559552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4230559552
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3524689613
Short name T652
Test name
Test status
Simulation time 30481794 ps
CPU time 1.28 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 215348 kb
Host smart-d8774194-8e4c-43b2-a18f-04d33340951e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524689613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3524689613
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1379491906
Short name T530
Test name
Test status
Simulation time 20168264 ps
CPU time 1.01 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 206256 kb
Host smart-b312ce50-f642-4855-8413-f8b0ff6e5b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379491906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1379491906
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3017162369
Short name T184
Test name
Test status
Simulation time 13013438 ps
CPU time 0.84 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216088 kb
Host smart-569c099e-ebd6-4c34-bf5f-fb3dccc2fd9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017162369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3017162369
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3800235745
Short name T631
Test name
Test status
Simulation time 35356521 ps
CPU time 1.33 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 216636 kb
Host smart-1d682851-8f51-4360-ae31-d2a8532a2c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800235745 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3800235745
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2513507305
Short name T167
Test name
Test status
Simulation time 35587056 ps
CPU time 0.88 seconds
Started Jun 02 02:44:08 PM PDT 24
Finished Jun 02 02:44:10 PM PDT 24
Peak memory 217988 kb
Host smart-e97964f9-a221-4a9a-92bd-c48ae4c99592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513507305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2513507305
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.740392312
Short name T683
Test name
Test status
Simulation time 254868936 ps
CPU time 1.11 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 216624 kb
Host smart-1520856c-b161-418b-8e82-a10aefe6c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740392312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.740392312
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2479341996
Short name T751
Test name
Test status
Simulation time 50708689 ps
CPU time 0.89 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 215108 kb
Host smart-e1a5d09d-fa7a-4499-bf67-ace0aa405e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479341996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2479341996
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2913452553
Short name T446
Test name
Test status
Simulation time 20543808 ps
CPU time 1.03 seconds
Started Jun 02 02:44:11 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 214972 kb
Host smart-4113a4d3-fc1e-40b2-93ed-1305637cc736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913452553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2913452553
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2731621876
Short name T657
Test name
Test status
Simulation time 388579153 ps
CPU time 4.24 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 216612 kb
Host smart-8789e01e-9a6c-41db-8686-6d584ed01361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731621876 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2731621876
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3885351897
Short name T278
Test name
Test status
Simulation time 42087699332 ps
CPU time 1058.45 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 03:01:48 PM PDT 24
Peak memory 220964 kb
Host smart-b70de6c8-c4e8-4235-9c3d-b1bacb173bd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885351897 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3885351897
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.904765505
Short name T648
Test name
Test status
Simulation time 45987665 ps
CPU time 1.77 seconds
Started Jun 02 02:45:20 PM PDT 24
Finished Jun 02 02:45:28 PM PDT 24
Peak memory 217848 kb
Host smart-681cba2e-9c16-4976-838d-8d67467944ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904765505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.904765505
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2926882685
Short name T274
Test name
Test status
Simulation time 35389842 ps
CPU time 1.36 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 218064 kb
Host smart-0681c0c1-a4a4-4b0d-a6b7-45082115b1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926882685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2926882685
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3019714295
Short name T749
Test name
Test status
Simulation time 40485464 ps
CPU time 1.42 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 219288 kb
Host smart-0a2ffab4-dc65-4971-8501-56ff981aef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019714295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3019714295
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.458852360
Short name T473
Test name
Test status
Simulation time 84868468 ps
CPU time 1.19 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:13 PM PDT 24
Peak memory 216884 kb
Host smart-1795f8f9-e5eb-4f5c-841d-028a11ba7640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458852360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.458852360
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.3847921997
Short name T789
Test name
Test status
Simulation time 90537938 ps
CPU time 1.17 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:28 PM PDT 24
Peak memory 218220 kb
Host smart-768223d9-7ff2-48b5-a58b-f498ef0832d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847921997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.3847921997
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2015635045
Short name T771
Test name
Test status
Simulation time 83727169 ps
CPU time 1.08 seconds
Started Jun 02 02:45:34 PM PDT 24
Finished Jun 02 02:45:36 PM PDT 24
Peak memory 216664 kb
Host smart-a0dd79ac-47f9-43f6-8f53-8d7712706e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015635045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2015635045
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2961319360
Short name T608
Test name
Test status
Simulation time 31338105 ps
CPU time 1.3 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216684 kb
Host smart-a4d02220-d03e-43e4-8d4e-3f206aa74149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961319360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2961319360
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3914005934
Short name T605
Test name
Test status
Simulation time 35901085 ps
CPU time 1.35 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216540 kb
Host smart-b57caf66-80b9-4844-9110-7736668a5016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914005934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3914005934
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1044053241
Short name T118
Test name
Test status
Simulation time 61553027 ps
CPU time 1.35 seconds
Started Jun 02 02:45:51 PM PDT 24
Finished Jun 02 02:45:53 PM PDT 24
Peak memory 216776 kb
Host smart-ad4106be-5546-4f81-bf3a-8b963b048457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044053241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1044053241
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.631484219
Short name T119
Test name
Test status
Simulation time 39435232 ps
CPU time 1.67 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 218012 kb
Host smart-2f48a74e-d667-4005-b6c0-d892d2a8d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631484219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.631484219
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.1341076889
Short name T552
Test name
Test status
Simulation time 42996194 ps
CPU time 0.88 seconds
Started Jun 02 02:44:02 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 214780 kb
Host smart-383180cc-86bf-43a1-bc59-164ce19ed193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341076889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1341076889
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3956682042
Short name T89
Test name
Test status
Simulation time 34435003 ps
CPU time 0.85 seconds
Started Jun 02 02:44:06 PM PDT 24
Finished Jun 02 02:44:08 PM PDT 24
Peak memory 216156 kb
Host smart-f71d3875-810d-4fc9-a415-deeb32fd2f8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956682042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3956682042
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.3707281954
Short name T509
Test name
Test status
Simulation time 25676497 ps
CPU time 1 seconds
Started Jun 02 02:44:07 PM PDT 24
Finished Jun 02 02:44:09 PM PDT 24
Peak memory 219472 kb
Host smart-1fda5724-b7cc-4f3e-930d-87b23eb93d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707281954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3707281954
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.503426037
Short name T285
Test name
Test status
Simulation time 33392748 ps
CPU time 1.29 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 216892 kb
Host smart-7b367b55-de4f-4fbf-b2b4-637ba92518ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503426037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.503426037
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.169453119
Short name T687
Test name
Test status
Simulation time 21315804 ps
CPU time 1.03 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:20 PM PDT 24
Peak memory 215064 kb
Host smart-afb898bb-0920-46e5-bb7f-35d22b7d9ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169453119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.169453119
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1181030305
Short name T450
Test name
Test status
Simulation time 75520833 ps
CPU time 0.94 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 214916 kb
Host smart-f9a92b86-c733-414c-88cb-c1dc3561d0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181030305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1181030305
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.2740624032
Short name T301
Test name
Test status
Simulation time 920620041 ps
CPU time 5.1 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 216840 kb
Host smart-6fc944b2-c083-4ebd-8b36-abee9b397a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740624032 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2740624032
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1210382806
Short name T193
Test name
Test status
Simulation time 12927881767 ps
CPU time 277.95 seconds
Started Jun 02 02:44:36 PM PDT 24
Finished Jun 02 02:49:14 PM PDT 24
Peak memory 219436 kb
Host smart-1e4915e8-8825-43d5-8b90-1cf3ad35bcf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210382806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1210382806
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4008569544
Short name T142
Test name
Test status
Simulation time 132971037 ps
CPU time 2.8 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 219648 kb
Host smart-297c69e7-a8bc-4fa6-9199-06d320255868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008569544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4008569544
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1289569577
Short name T766
Test name
Test status
Simulation time 77032766 ps
CPU time 1.41 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 218144 kb
Host smart-f7def91a-fe91-4f6e-a5d9-04314efeca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289569577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1289569577
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.642370027
Short name T330
Test name
Test status
Simulation time 72824620 ps
CPU time 1.03 seconds
Started Jun 02 02:45:33 PM PDT 24
Finished Jun 02 02:45:34 PM PDT 24
Peak memory 216668 kb
Host smart-54f107c0-d683-4780-8aaf-1801b302cd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642370027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.642370027
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.4119436957
Short name T400
Test name
Test status
Simulation time 60605365 ps
CPU time 0.96 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216576 kb
Host smart-5d12f9ed-8303-485b-af3d-68c3f1c1860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119436957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.4119436957
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.322748569
Short name T711
Test name
Test status
Simulation time 74740297 ps
CPU time 1.2 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 219296 kb
Host smart-9f9bd4c0-701a-4e75-93e5-20e1fc206d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322748569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.322748569
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2788359789
Short name T654
Test name
Test status
Simulation time 28479783 ps
CPU time 1.28 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 219304 kb
Host smart-bb92f89b-a9db-4417-83b6-9111c21e225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788359789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2788359789
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.2570825482
Short name T418
Test name
Test status
Simulation time 65411062 ps
CPU time 0.98 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 216624 kb
Host smart-bfda4191-437c-452e-96e8-caa95eceb8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570825482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.2570825482
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1468276997
Short name T810
Test name
Test status
Simulation time 174339413 ps
CPU time 2.6 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 219788 kb
Host smart-f8b629ab-3fa6-4af2-907a-e2f7b8e1aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468276997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1468276997
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2073862669
Short name T25
Test name
Test status
Simulation time 85521150 ps
CPU time 1.29 seconds
Started Jun 02 02:45:25 PM PDT 24
Finished Jun 02 02:45:26 PM PDT 24
Peak memory 216804 kb
Host smart-e74217dc-9cca-4db9-a55d-dec5536df012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073862669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2073862669
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1821078564
Short name T538
Test name
Test status
Simulation time 57023768 ps
CPU time 1.32 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 218680 kb
Host smart-1852ce2e-db73-4374-96f1-7aaf779f671a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821078564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1821078564
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.686761560
Short name T188
Test name
Test status
Simulation time 98397512 ps
CPU time 1.22 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 215292 kb
Host smart-3b80d58b-c002-486d-9799-03ef6eeb97c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686761560 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.686761560
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.4059881845
Short name T437
Test name
Test status
Simulation time 45976849 ps
CPU time 0.86 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 206192 kb
Host smart-22b652b8-9952-42f6-983a-cae75e0d9cf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059881845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.4059881845
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1050060275
Short name T185
Test name
Test status
Simulation time 26268321 ps
CPU time 0.85 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:20 PM PDT 24
Peak memory 215164 kb
Host smart-53080848-3f96-4af4-8477-79c344c4d65e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050060275 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1050060275
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1407407496
Short name T416
Test name
Test status
Simulation time 25159238 ps
CPU time 1.04 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 217848 kb
Host smart-7c6a68dd-ceb3-4615-aaf9-070b43b312b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407407496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1407407496
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.2463650941
Short name T551
Test name
Test status
Simulation time 67258771 ps
CPU time 1.19 seconds
Started Jun 02 02:44:05 PM PDT 24
Finished Jun 02 02:44:07 PM PDT 24
Peak memory 216752 kb
Host smart-0784c539-e07c-4b4e-a1f4-eeddf2c831cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463650941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2463650941
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2927881378
Short name T305
Test name
Test status
Simulation time 42672863 ps
CPU time 0.85 seconds
Started Jun 02 02:44:10 PM PDT 24
Finished Jun 02 02:44:12 PM PDT 24
Peak memory 214900 kb
Host smart-8fdfdc23-e55d-4f37-bdd6-98e208471fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927881378 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2927881378
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3980977272
Short name T407
Test name
Test status
Simulation time 183192294 ps
CPU time 0.89 seconds
Started Jun 02 02:44:25 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 214940 kb
Host smart-1677034e-da8b-4c24-81e0-cda7f83e57ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980977272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3980977272
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.4141337051
Short name T125
Test name
Test status
Simulation time 542423187 ps
CPU time 5.66 seconds
Started Jun 02 02:44:25 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 216488 kb
Host smart-4e9fb62e-fae9-4bde-b90d-9a70c5150071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141337051 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.4141337051
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.885489382
Short name T702
Test name
Test status
Simulation time 68302270314 ps
CPU time 1550.45 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 03:10:13 PM PDT 24
Peak memory 223548 kb
Host smart-7f89a80e-aebd-462e-bd11-926ea895e08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885489382 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.885489382
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2879415641
Short name T374
Test name
Test status
Simulation time 51084148 ps
CPU time 1.36 seconds
Started Jun 02 02:45:20 PM PDT 24
Finished Jun 02 02:45:22 PM PDT 24
Peak memory 219316 kb
Host smart-c258ad32-8436-48cf-8224-cad92a6eb269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879415641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2879415641
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4286545092
Short name T478
Test name
Test status
Simulation time 664499065 ps
CPU time 5.89 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 219376 kb
Host smart-3942bbd0-c3e2-4565-a187-cc080cf43c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286545092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4286545092
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2487982180
Short name T472
Test name
Test status
Simulation time 54585673 ps
CPU time 1.6 seconds
Started Jun 02 02:45:25 PM PDT 24
Finished Jun 02 02:45:27 PM PDT 24
Peak memory 217728 kb
Host smart-2417c70b-bd75-4430-adee-3b1cffd138d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487982180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2487982180
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2898860831
Short name T422
Test name
Test status
Simulation time 42958824 ps
CPU time 1.44 seconds
Started Jun 02 02:45:27 PM PDT 24
Finished Jun 02 02:45:30 PM PDT 24
Peak memory 218060 kb
Host smart-88f8989c-3176-4a18-9bb8-c6028b09e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898860831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2898860831
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3980346650
Short name T560
Test name
Test status
Simulation time 221671792 ps
CPU time 1.16 seconds
Started Jun 02 02:45:23 PM PDT 24
Finished Jun 02 02:45:25 PM PDT 24
Peak memory 216544 kb
Host smart-075c25dc-bdee-4870-b2f4-dff5197491e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980346650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3980346650
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2588661729
Short name T391
Test name
Test status
Simulation time 55760096 ps
CPU time 1.28 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 216540 kb
Host smart-11a4dc9f-3cf0-4cd2-8023-77779aca123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588661729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2588661729
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2659630231
Short name T94
Test name
Test status
Simulation time 52829346 ps
CPU time 1.37 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:21 PM PDT 24
Peak memory 218204 kb
Host smart-2b8e66f7-a243-4ecf-92b4-664283226be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659630231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2659630231
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3642855083
Short name T141
Test name
Test status
Simulation time 87595010 ps
CPU time 1.16 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:16 PM PDT 24
Peak memory 216632 kb
Host smart-5c996ce3-9606-49b8-b1f3-cf1d167cbf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642855083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3642855083
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3853850110
Short name T314
Test name
Test status
Simulation time 56423148 ps
CPU time 1.52 seconds
Started Jun 02 02:45:28 PM PDT 24
Finished Jun 02 02:45:30 PM PDT 24
Peak memory 217916 kb
Host smart-253211bf-21c3-4986-bfdf-026f7f162153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853850110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3853850110
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1516089587
Short name T68
Test name
Test status
Simulation time 27369495 ps
CPU time 1.21 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 215368 kb
Host smart-9d8cd637-a606-40f3-b70e-1ecd9944d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516089587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1516089587
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3306902674
Short name T725
Test name
Test status
Simulation time 44000425 ps
CPU time 0.84 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 214856 kb
Host smart-dfba74ce-471b-47b1-bd8f-8ce3068e5c95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306902674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3306902674
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1786792189
Short name T739
Test name
Test status
Simulation time 13846816 ps
CPU time 0.88 seconds
Started Jun 02 02:44:09 PM PDT 24
Finished Jun 02 02:44:11 PM PDT 24
Peak memory 215112 kb
Host smart-e890655e-ce5e-4b0a-b4ce-5dbadf60a608
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786792189 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1786792189
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2561089207
Short name T230
Test name
Test status
Simulation time 71472629 ps
CPU time 1.06 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 217820 kb
Host smart-2dcb60ba-fd9e-4ae2-8aa9-ee041039229e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561089207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2561089207
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.963984471
Short name T558
Test name
Test status
Simulation time 20427339 ps
CPU time 1.11 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 217872 kb
Host smart-ab7e3538-540f-4c6f-94ea-9eb515bfedd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963984471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.963984471
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3523216662
Short name T614
Test name
Test status
Simulation time 31065762 ps
CPU time 1.4 seconds
Started Jun 02 02:44:16 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 219360 kb
Host smart-4fea442f-a11e-41ca-bd76-94f614b99e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523216662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3523216662
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.559003173
Short name T479
Test name
Test status
Simulation time 22376846 ps
CPU time 1.07 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 215344 kb
Host smart-e4d1e2a2-becc-4aff-80a5-539bed7bd4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559003173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.559003173
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.462126664
Short name T435
Test name
Test status
Simulation time 34264541 ps
CPU time 0.87 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 214920 kb
Host smart-c0fe4d96-a7b2-43ce-bdfc-9c16ebc49888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462126664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.462126664
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2717074995
Short name T205
Test name
Test status
Simulation time 389411568 ps
CPU time 1.96 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 216588 kb
Host smart-3f3f2796-f71a-4740-a4d9-9e67542fd082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717074995 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2717074995
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2480211394
Short name T568
Test name
Test status
Simulation time 77412710815 ps
CPU time 1984.97 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 03:17:28 PM PDT 24
Peak memory 228308 kb
Host smart-7698a26b-5a70-4544-a55c-ad2de49ebdde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480211394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2480211394
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.757041134
Short name T296
Test name
Test status
Simulation time 79814366 ps
CPU time 1.03 seconds
Started Jun 02 02:45:16 PM PDT 24
Finished Jun 02 02:45:19 PM PDT 24
Peak memory 216792 kb
Host smart-a35fcd6a-ba03-441b-81db-53b99b04021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757041134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.757041134
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2187281894
Short name T139
Test name
Test status
Simulation time 186909704 ps
CPU time 1.23 seconds
Started Jun 02 02:45:17 PM PDT 24
Finished Jun 02 02:45:20 PM PDT 24
Peak memory 216752 kb
Host smart-29d9ed60-c5af-4346-b1db-61edf9b9f236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187281894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2187281894
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4215943322
Short name T788
Test name
Test status
Simulation time 52093997 ps
CPU time 1.97 seconds
Started Jun 02 02:45:49 PM PDT 24
Finished Jun 02 02:45:52 PM PDT 24
Peak memory 217892 kb
Host smart-251d5dd8-9cf6-4c6c-afe5-af25a8e6a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215943322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4215943322
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1894369087
Short name T682
Test name
Test status
Simulation time 29562997 ps
CPU time 1.21 seconds
Started Jun 02 02:45:40 PM PDT 24
Finished Jun 02 02:45:42 PM PDT 24
Peak memory 216596 kb
Host smart-4477572e-62b0-4885-87e4-4f4debb39e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894369087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1894369087
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3622734854
Short name T651
Test name
Test status
Simulation time 54444686 ps
CPU time 1.36 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 216592 kb
Host smart-8f96ca41-2991-4b50-b11d-33c98c4b7faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622734854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3622734854
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2782380249
Short name T591
Test name
Test status
Simulation time 40028149 ps
CPU time 1.36 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 217708 kb
Host smart-ea67dd37-2cf7-494c-a04e-aae051df978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782380249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2782380249
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1742004445
Short name T354
Test name
Test status
Simulation time 123274507 ps
CPU time 2.62 seconds
Started Jun 02 02:45:19 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 218516 kb
Host smart-d0edd08f-2446-4811-90d7-7f87d67770ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742004445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1742004445
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1666524383
Short name T700
Test name
Test status
Simulation time 40266831 ps
CPU time 1.59 seconds
Started Jun 02 02:45:21 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 217808 kb
Host smart-3a763b99-6ba5-4007-9f3c-d296be21a4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666524383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1666524383
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2071681605
Short name T832
Test name
Test status
Simulation time 45855475 ps
CPU time 1.14 seconds
Started Jun 02 02:45:26 PM PDT 24
Finished Jun 02 02:45:27 PM PDT 24
Peak memory 218952 kb
Host smart-89fbe536-52c7-41a0-81e5-c374373b93e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071681605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2071681605
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3158968127
Short name T672
Test name
Test status
Simulation time 40331449 ps
CPU time 1.54 seconds
Started Jun 02 02:45:20 PM PDT 24
Finished Jun 02 02:45:23 PM PDT 24
Peak memory 218032 kb
Host smart-acbf1a47-deb9-4f56-ad35-5f9ce01f8c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158968127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3158968127
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2298072016
Short name T16
Test name
Test status
Simulation time 26119508 ps
CPU time 1.27 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 215320 kb
Host smart-f395e4bd-b7cf-4492-9925-ba3c31382bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298072016 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2298072016
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1868570411
Short name T102
Test name
Test status
Simulation time 17634007 ps
CPU time 0.93 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 206252 kb
Host smart-5d26d43a-8125-4f98-85f0-e5bfc92dea0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868570411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1868570411
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1627613258
Short name T706
Test name
Test status
Simulation time 13199352 ps
CPU time 0.87 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 215284 kb
Host smart-ae502cf0-8b34-4e91-a9dc-38e5854fcd8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627613258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1627613258
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.508029395
Short name T57
Test name
Test status
Simulation time 87057450 ps
CPU time 1.17 seconds
Started Jun 02 02:43:49 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 216808 kb
Host smart-a4024796-8e70-4745-a01b-7805b781ebf6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508029395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.508029395
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2317973948
Short name T425
Test name
Test status
Simulation time 22497732 ps
CPU time 0.92 seconds
Started Jun 02 02:43:45 PM PDT 24
Finished Jun 02 02:43:49 PM PDT 24
Peak memory 218208 kb
Host smart-dadb49ce-577f-4f6a-8a9f-dbffe53e8af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317973948 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2317973948
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.4117609183
Short name T491
Test name
Test status
Simulation time 79822752 ps
CPU time 0.95 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 216792 kb
Host smart-4fa47360-69a6-4b72-842d-79ee53eba52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117609183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.4117609183
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3442051437
Short name T124
Test name
Test status
Simulation time 27996267 ps
CPU time 1.06 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 223448 kb
Host smart-c82e57ad-192e-4a43-870f-a9878bd3db50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442051437 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3442051437
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.102261455
Short name T104
Test name
Test status
Simulation time 36364242 ps
CPU time 0.86 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 207048 kb
Host smart-9c064dc3-5e66-4e09-963f-edd9be8e5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102261455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.102261455
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.2675705729
Short name T756
Test name
Test status
Simulation time 84243983 ps
CPU time 0.92 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:31 PM PDT 24
Peak memory 214956 kb
Host smart-dda526dc-ba0c-40ad-ba41-8fb9d07062b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675705729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2675705729
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1368999233
Short name T161
Test name
Test status
Simulation time 308462786 ps
CPU time 2.78 seconds
Started Jun 02 02:43:52 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 217964 kb
Host smart-f37227e2-3410-4ef4-a6c7-79fb39aa140d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368999233 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1368999233
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.84429382
Short name T431
Test name
Test status
Simulation time 88776063849 ps
CPU time 1004.98 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 03:00:28 PM PDT 24
Peak memory 221104 kb
Host smart-b2365f58-dc11-460f-b777-dc7b4eefff89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84429382 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.84429382
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2962523689
Short name T715
Test name
Test status
Simulation time 134725612 ps
CPU time 1.3 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 215348 kb
Host smart-aa6d20ef-4b71-47a6-853c-a5e1f67b9d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962523689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2962523689
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3567263290
Short name T835
Test name
Test status
Simulation time 24127410 ps
CPU time 0.88 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 206236 kb
Host smart-4b9b8241-1475-4a32-b78a-eb4b35896a98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567263290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3567263290
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.679175971
Short name T815
Test name
Test status
Simulation time 52774021 ps
CPU time 1.02 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:15 PM PDT 24
Peak memory 219092 kb
Host smart-c1e98b38-9baa-4ce5-97d0-cab5f84de025
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679175971 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.679175971
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3486763953
Short name T173
Test name
Test status
Simulation time 71994366 ps
CPU time 1.08 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 219208 kb
Host smart-bb5e9595-d15c-4212-a0aa-34e739288e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486763953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3486763953
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2227455210
Short name T281
Test name
Test status
Simulation time 41779212 ps
CPU time 1.51 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 218840 kb
Host smart-62c499d4-605d-4dfc-b571-2495b361c18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227455210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2227455210
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_smoke.1928875660
Short name T292
Test name
Test status
Simulation time 25277562 ps
CPU time 0.97 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 214916 kb
Host smart-36f9f081-db94-4bf7-870e-372dbeecb099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928875660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1928875660
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1386640139
Short name T827
Test name
Test status
Simulation time 517140973 ps
CPU time 4.7 seconds
Started Jun 02 02:44:13 PM PDT 24
Finished Jun 02 02:44:18 PM PDT 24
Peak memory 216632 kb
Host smart-8f380a17-be50-4b5a-b889-10569bf10f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386640139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1386640139
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2542995384
Short name T189
Test name
Test status
Simulation time 280232337525 ps
CPU time 1673.84 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 03:12:16 PM PDT 24
Peak memory 223928 kb
Host smart-587139e3-6da8-425c-bab9-65c64d3c53e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542995384 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2542995384
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.884872753
Short name T829
Test name
Test status
Simulation time 46084518 ps
CPU time 1.06 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 215352 kb
Host smart-414f068d-6588-41fb-bfc1-fd7d1b7668ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884872753 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.884872753
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3744466812
Short name T375
Test name
Test status
Simulation time 39585092 ps
CPU time 0.85 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 206064 kb
Host smart-27e28a4d-c8d7-41c6-871b-cd9e3d34f8aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744466812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3744466812
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2726076874
Short name T160
Test name
Test status
Simulation time 11972006 ps
CPU time 0.88 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 215128 kb
Host smart-21c5e189-7df3-4fe8-817b-5ad489a97775
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726076874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2726076874
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2810871766
Short name T43
Test name
Test status
Simulation time 37776597 ps
CPU time 1.25 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216808 kb
Host smart-9c02f082-ba32-4410-ba5a-f081fe5724f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810871766 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2810871766
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1249199329
Short name T484
Test name
Test status
Simulation time 19599203 ps
CPU time 1.11 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 223556 kb
Host smart-a9a561e4-0f2e-43de-a5e3-a6ab1b0c5e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249199329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1249199329
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.2497571402
Short name T693
Test name
Test status
Simulation time 72032162 ps
CPU time 1.11 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 216648 kb
Host smart-e569d5e3-151a-4baf-868b-c8e79e3057d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497571402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.2497571402
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1893914997
Short name T147
Test name
Test status
Simulation time 75806895 ps
CPU time 0.8 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215040 kb
Host smart-a48f6083-6702-4f56-908c-70f07e2ed251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893914997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1893914997
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3660884849
Short name T688
Test name
Test status
Simulation time 24707365 ps
CPU time 0.93 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 214988 kb
Host smart-3d03fe54-0991-41f2-8c01-11b89ed12dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660884849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3660884849
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.363299487
Short name T428
Test name
Test status
Simulation time 408318876 ps
CPU time 4.31 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 214920 kb
Host smart-010bbe60-9859-4190-a16a-84b2a16f363d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363299487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.363299487
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3192327307
Short name T190
Test name
Test status
Simulation time 116975858786 ps
CPU time 1277.25 seconds
Started Jun 02 02:44:14 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 224588 kb
Host smart-17dab89d-6002-4024-bf50-66b97d62a81e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192327307 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3192327307
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2477530079
Short name T676
Test name
Test status
Simulation time 54179948 ps
CPU time 1.2 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 215272 kb
Host smart-39b7de53-a5d4-464c-9699-1f1317320ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477530079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2477530079
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1668091836
Short name T352
Test name
Test status
Simulation time 42305704 ps
CPU time 0.84 seconds
Started Jun 02 02:44:37 PM PDT 24
Finished Jun 02 02:44:38 PM PDT 24
Peak memory 206484 kb
Host smart-aacbe07d-344c-4cc5-8f41-2309a54d2fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668091836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1668091836
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2500406506
Short name T611
Test name
Test status
Simulation time 84768609 ps
CPU time 0.89 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 215812 kb
Host smart-a0954105-f2a9-482e-8a1c-97954f2a453b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500406506 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2500406506
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3272250740
Short name T759
Test name
Test status
Simulation time 44775994 ps
CPU time 1.27 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 216564 kb
Host smart-c2d7a824-7491-4ed2-9fcc-2032e02cfbe8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272250740 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3272250740
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3424800714
Short name T4
Test name
Test status
Simulation time 29230215 ps
CPU time 0.9 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 218132 kb
Host smart-c58342a2-10ba-4bd3-bce2-0d3e1873da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424800714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3424800714
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.405202808
Short name T307
Test name
Test status
Simulation time 50630609 ps
CPU time 0.9 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:16 PM PDT 24
Peak memory 216568 kb
Host smart-eadbc543-ab88-413d-bcbf-47790f9bbfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405202808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.405202808
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.2733776720
Short name T146
Test name
Test status
Simulation time 20518957 ps
CPU time 1.01 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215332 kb
Host smart-2e657f81-74cd-4a5f-bf8e-d0b3050a98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733776720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.2733776720
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1382002729
Short name T817
Test name
Test status
Simulation time 38040645 ps
CPU time 0.95 seconds
Started Jun 02 02:44:17 PM PDT 24
Finished Jun 02 02:44:19 PM PDT 24
Peak memory 214952 kb
Host smart-b6401553-be37-4901-99b4-d17626b4fe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382002729 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1382002729
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2535887487
Short name T460
Test name
Test status
Simulation time 1074052286 ps
CPU time 3.3 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 216360 kb
Host smart-cabc8db7-5005-4a77-b8bf-ad5559bfec47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535887487 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2535887487
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2889590619
Short name T382
Test name
Test status
Simulation time 77132702814 ps
CPU time 924.12 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 03:00:02 PM PDT 24
Peak memory 219764 kb
Host smart-08e2abbc-13ee-407b-83e6-129b6d1f9405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889590619 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2889590619
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.402961127
Short name T249
Test name
Test status
Simulation time 29566331 ps
CPU time 1.24 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 215344 kb
Host smart-ec2f494c-2f31-480c-a339-a4ff376dae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402961127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.402961127
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.422966143
Short name T696
Test name
Test status
Simulation time 75057268 ps
CPU time 0.87 seconds
Started Jun 02 02:44:26 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 206196 kb
Host smart-7f672917-5e04-4a15-8b8f-ee0888d1ece3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422966143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.422966143
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.414751051
Short name T60
Test name
Test status
Simulation time 11820543 ps
CPU time 0.88 seconds
Started Jun 02 02:44:32 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 215160 kb
Host smart-a0daa8b0-0fad-4fe5-a14c-405a0b3d3cf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414751051 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.414751051
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3598475694
Short name T822
Test name
Test status
Simulation time 34714163 ps
CPU time 1.02 seconds
Started Jun 02 02:44:31 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 217916 kb
Host smart-c482a6dd-f114-416d-a487-6e488baf4a3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598475694 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3598475694
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.341017167
Short name T87
Test name
Test status
Simulation time 31888932 ps
CPU time 0.88 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 217836 kb
Host smart-8ee763ba-62c9-4b43-be64-286b95018241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341017167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.341017167
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2858241153
Short name T275
Test name
Test status
Simulation time 342477569 ps
CPU time 1.28 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 219240 kb
Host smart-a4f4e5bf-779f-475f-9a21-07168b4f6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858241153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2858241153
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2448345767
Short name T384
Test name
Test status
Simulation time 58199969 ps
CPU time 0.86 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 214896 kb
Host smart-f7746edd-646f-4e39-9ca5-00e41b8d6868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448345767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2448345767
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1792422444
Short name T311
Test name
Test status
Simulation time 18011800 ps
CPU time 1.01 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 214992 kb
Host smart-f1d4c633-28b4-44f8-bce2-002e0e94bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792422444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1792422444
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3916006650
Short name T580
Test name
Test status
Simulation time 159392570 ps
CPU time 3.03 seconds
Started Jun 02 02:44:45 PM PDT 24
Finished Jun 02 02:44:49 PM PDT 24
Peak memory 214892 kb
Host smart-ac53e720-a09c-4b70-8605-439521cf0ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916006650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3916006650
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2558330422
Short name T544
Test name
Test status
Simulation time 92011082550 ps
CPU time 492.98 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 02:52:47 PM PDT 24
Peak memory 219224 kb
Host smart-fc93ee9a-b6e7-4625-9090-5080815f20a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558330422 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2558330422
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2859386187
Short name T243
Test name
Test status
Simulation time 25956520 ps
CPU time 1.26 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 215264 kb
Host smart-cf4822a1-b4c2-49fe-b1c1-5a14f112ecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859386187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2859386187
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3521238225
Short name T684
Test name
Test status
Simulation time 78227300 ps
CPU time 0.86 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 206292 kb
Host smart-5cb1d317-f77c-4be4-85c3-559cf362091b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521238225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3521238225
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.3257833146
Short name T664
Test name
Test status
Simulation time 26567361 ps
CPU time 0.8 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:20 PM PDT 24
Peak memory 215136 kb
Host smart-76a979d7-1467-489e-8bd2-445f4ac31e85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257833146 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3257833146
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3157300398
Short name T18
Test name
Test status
Simulation time 21569492 ps
CPU time 0.93 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 217924 kb
Host smart-281271b4-9d5f-459f-962c-ac65c52b923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157300398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3157300398
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4238545322
Short name T637
Test name
Test status
Simulation time 61336419 ps
CPU time 1.01 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 216732 kb
Host smart-47ce5bf3-231d-48d2-ac42-894def706060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238545322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4238545322
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1375788230
Short name T410
Test name
Test status
Simulation time 31931622 ps
CPU time 0.89 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 215128 kb
Host smart-2fea4b22-7692-4d3c-a1e9-16e2568e233d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375788230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1375788230
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1206554211
Short name T647
Test name
Test status
Simulation time 116253089 ps
CPU time 0.97 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 214976 kb
Host smart-41f7f6d6-733b-40f4-ab2f-70b627915fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206554211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1206554211
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4185376637
Short name T464
Test name
Test status
Simulation time 300845830 ps
CPU time 1.87 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 216488 kb
Host smart-d336a760-050f-4b58-b930-175fd5dc29eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185376637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4185376637
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1182862005
Short name T495
Test name
Test status
Simulation time 108815393617 ps
CPU time 1281.36 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 223472 kb
Host smart-fc1c3bf2-cf3d-4072-95b3-72f2b98aca2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182862005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1182862005
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3443304092
Short name T244
Test name
Test status
Simulation time 187552968 ps
CPU time 1.24 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 215304 kb
Host smart-242cae66-82f2-409c-a61c-cd07807d291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443304092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3443304092
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.708404586
Short name T540
Test name
Test status
Simulation time 15048712 ps
CPU time 0.91 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 214592 kb
Host smart-81886a32-a937-4c08-97b3-e0067b9e046b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708404586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.708404586
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2643143823
Short name T533
Test name
Test status
Simulation time 27257757 ps
CPU time 0.9 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 216316 kb
Host smart-5e356b67-10e8-4dd9-bcc6-3637299efc11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643143823 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2643143823
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.218858941
Short name T166
Test name
Test status
Simulation time 39524920 ps
CPU time 1.26 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 216512 kb
Host smart-1e6020e9-85c3-483b-9df5-28af803814f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218858941 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.218858941
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.1808207326
Short name T92
Test name
Test status
Simulation time 19483500 ps
CPU time 1.15 seconds
Started Jun 02 02:44:31 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 223376 kb
Host smart-8604fdd2-0ba7-47d2-897d-0d45bc67b61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808207326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1808207326
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.2484627663
Short name T413
Test name
Test status
Simulation time 50344782 ps
CPU time 1.82 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 216736 kb
Host smart-60b4676d-5d22-4223-8286-45f623b22952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484627663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2484627663
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4286120373
Short name T106
Test name
Test status
Simulation time 20576544 ps
CPU time 1.06 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 215304 kb
Host smart-aefe679b-00bd-4e3e-bac6-3da759b7d96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286120373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4286120373
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2907160560
Short name T304
Test name
Test status
Simulation time 16961413 ps
CPU time 1 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 214980 kb
Host smart-43cec17d-f7dd-4358-a22f-1341de6005c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907160560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2907160560
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2244205138
Short name T675
Test name
Test status
Simulation time 173022801 ps
CPU time 1.38 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 214976 kb
Host smart-8892512c-1d42-45ec-9734-f4dd6b4f1f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244205138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2244205138
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3706225057
Short name T1
Test name
Test status
Simulation time 55910712458 ps
CPU time 322.84 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:49:48 PM PDT 24
Peak memory 218276 kb
Host smart-8956b3f6-a8e2-48e4-9164-62e2c4ef7e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706225057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3706225057
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.865341256
Short name T150
Test name
Test status
Simulation time 89341027 ps
CPU time 1.2 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 215272 kb
Host smart-367036a5-c5c2-41bd-b1db-8c3beb7a7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865341256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.865341256
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.4186337518
Short name T837
Test name
Test status
Simulation time 44195231 ps
CPU time 0.91 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 214464 kb
Host smart-54e1f361-31e8-4050-89ce-ef95b06aa94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186337518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.4186337518
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1641400514
Short name T644
Test name
Test status
Simulation time 58446147 ps
CPU time 1.15 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216640 kb
Host smart-665deaba-2815-4c30-9a96-29bcb6f0f0ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641400514 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1641400514
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2972466770
Short name T172
Test name
Test status
Simulation time 19629945 ps
CPU time 1.07 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 218196 kb
Host smart-50d8f196-2094-4191-b9b4-32297ced819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972466770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2972466770
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3206418806
Short name T790
Test name
Test status
Simulation time 75597504 ps
CPU time 1.39 seconds
Started Jun 02 02:44:28 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 218332 kb
Host smart-71641f08-a336-436e-b6ea-25e824ed9fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206418806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3206418806
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4102609199
Short name T799
Test name
Test status
Simulation time 21509841 ps
CPU time 1.07 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 215344 kb
Host smart-b8e542bb-69df-48c7-adbf-e3e063e01d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102609199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4102609199
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.810656656
Short name T293
Test name
Test status
Simulation time 16951037 ps
CPU time 0.97 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 214880 kb
Host smart-b949d55d-8d5f-45fb-9439-4d0366b52b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810656656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.810656656
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1632971433
Short name T506
Test name
Test status
Simulation time 1091625857 ps
CPU time 5.79 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 216812 kb
Host smart-c2f82679-28b8-494a-a9c1-aca2f043922c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632971433 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1632971433
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3443861016
Short name T191
Test name
Test status
Simulation time 38403820455 ps
CPU time 503.26 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:52:48 PM PDT 24
Peak memory 217412 kb
Host smart-a9853b46-a50b-4e03-98f0-e41ab83502a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443861016 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3443861016
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2939070831
Short name T240
Test name
Test status
Simulation time 71817918 ps
CPU time 1.17 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 215348 kb
Host smart-5655979d-6a56-4133-9b28-c49a8b81aede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939070831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2939070831
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.758212722
Short name T592
Test name
Test status
Simulation time 30823972 ps
CPU time 0.87 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 214324 kb
Host smart-76566b2d-2895-4c2e-bf98-1b88353d40cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758212722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.758212722
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2621286393
Short name T83
Test name
Test status
Simulation time 11756830 ps
CPU time 0.86 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:35 PM PDT 24
Peak memory 216152 kb
Host smart-2e8a2cd8-657f-4c98-ae36-9dd9ff1861d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621286393 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2621286393
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2638876414
Short name T341
Test name
Test status
Simulation time 26582428 ps
CPU time 0.95 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 223280 kb
Host smart-1fd36f30-ad41-44d0-a606-73739fffe749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638876414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2638876414
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3864359195
Short name T680
Test name
Test status
Simulation time 104686588 ps
CPU time 1.34 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216840 kb
Host smart-34b4fd03-90f5-40b2-b355-533416b51d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864359195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3864359195
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2463038418
Short name T774
Test name
Test status
Simulation time 37656257 ps
CPU time 1.03 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 223392 kb
Host smart-06c0e505-22c4-4b19-8f78-73642fc28b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463038418 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2463038418
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1604278074
Short name T515
Test name
Test status
Simulation time 59531114 ps
CPU time 0.84 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 214752 kb
Host smart-d5164e48-bc0b-44f0-9aa6-4f713ac9cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604278074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1604278074
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3449194663
Short name T475
Test name
Test status
Simulation time 919804964 ps
CPU time 4.28 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 216600 kb
Host smart-782b2792-8498-4e4a-9cf6-bd1333721309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449194663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3449194663
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.725179985
Short name T747
Test name
Test status
Simulation time 313751721964 ps
CPU time 1400.22 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 225116 kb
Host smart-064b31a1-e617-4c21-a0eb-5c9058b655ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725179985 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.725179985
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.461485563
Short name T638
Test name
Test status
Simulation time 29763169 ps
CPU time 1.3 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 215352 kb
Host smart-4380be8f-2e1a-48d9-9f65-26aeb1373116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461485563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.461485563
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1743507827
Short name T708
Test name
Test status
Simulation time 58087192 ps
CPU time 0.92 seconds
Started Jun 02 02:44:36 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 206316 kb
Host smart-379839f9-614d-4555-8785-ff2e19f7b818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743507827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1743507827
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2305262746
Short name T84
Test name
Test status
Simulation time 36491692 ps
CPU time 0.82 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 216016 kb
Host smart-be397c55-eccd-4962-be57-c9841b2ffced
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305262746 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2305262746
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1781880782
Short name T395
Test name
Test status
Simulation time 217538343 ps
CPU time 1.28 seconds
Started Jun 02 02:44:18 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 216688 kb
Host smart-82496e48-1bcd-4eff-b520-7c309b373cca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781880782 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1781880782
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1198342141
Short name T181
Test name
Test status
Simulation time 65329089 ps
CPU time 1.04 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 220272 kb
Host smart-ef7aecd9-2469-42a8-babb-c1fa59620411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198342141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1198342141
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2612469995
Short name T265
Test name
Test status
Simulation time 81646039 ps
CPU time 1.45 seconds
Started Jun 02 02:44:15 PM PDT 24
Finished Jun 02 02:44:17 PM PDT 24
Peak memory 218332 kb
Host smart-e6d5ed36-4fcb-49a4-a891-b46b57847f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612469995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2612469995
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3705430221
Short name T123
Test name
Test status
Simulation time 35339573 ps
CPU time 1.01 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 223556 kb
Host smart-76fe3212-fa59-4ce3-8ede-3fad73aea298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705430221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3705430221
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1827805995
Short name T546
Test name
Test status
Simulation time 18727821 ps
CPU time 1.07 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:22 PM PDT 24
Peak memory 214896 kb
Host smart-35ffbefc-0bef-47ea-9a1f-cf9f7a4fdf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827805995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1827805995
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4071705022
Short name T719
Test name
Test status
Simulation time 364256791 ps
CPU time 3.12 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:28 PM PDT 24
Peak memory 214896 kb
Host smart-01d4cce4-93b9-4d86-8f5f-2f73a22dd7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071705022 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4071705022
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.911234310
Short name T610
Test name
Test status
Simulation time 69646266009 ps
CPU time 1801.85 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 226632 kb
Host smart-d86b9066-53d1-46cc-b6eb-b4bab6c8a69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911234310 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.911234310
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2798921790
Short name T153
Test name
Test status
Simulation time 242653410 ps
CPU time 1.25 seconds
Started Jun 02 02:44:25 PM PDT 24
Finished Jun 02 02:44:28 PM PDT 24
Peak memory 215296 kb
Host smart-4fad6930-81d4-42c8-8666-71722e8ea8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798921790 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2798921790
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1672098396
Short name T801
Test name
Test status
Simulation time 48285764 ps
CPU time 0.84 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 206720 kb
Host smart-c3a53178-a755-43a0-8554-303237d49b38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672098396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1672098396
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.939114889
Short name T834
Test name
Test status
Simulation time 31599275 ps
CPU time 1.13 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216444 kb
Host smart-6627f97b-02cd-4091-bc73-24b59e25b2e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939114889 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.939114889
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3140650898
Short name T471
Test name
Test status
Simulation time 19235045 ps
CPU time 1.11 seconds
Started Jun 02 02:44:28 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 218112 kb
Host smart-7e99dd00-b3b8-4bd1-b531-e884708b91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140650898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3140650898
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2015509529
Short name T833
Test name
Test status
Simulation time 201503303 ps
CPU time 3.23 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 219768 kb
Host smart-db6ea02d-e6d4-4cb6-9f08-657c1a39bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015509529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2015509529
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4066718932
Short name T604
Test name
Test status
Simulation time 22159192 ps
CPU time 1.07 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215036 kb
Host smart-c880f04f-eefb-4331-9593-9850ae93ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066718932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4066718932
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2717123764
Short name T366
Test name
Test status
Simulation time 52076031 ps
CPU time 0.94 seconds
Started Jun 02 02:44:25 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 214924 kb
Host smart-cb05d917-a365-4a1e-9b3e-8d5b69f7ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717123764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2717123764
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.364168554
Short name T787
Test name
Test status
Simulation time 199729094 ps
CPU time 4.06 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 217892 kb
Host smart-0db6b1c3-8221-4fa1-9574-21a63932cda2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364168554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.364168554
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3252132311
Short name T132
Test name
Test status
Simulation time 221800759423 ps
CPU time 757.68 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 02:57:12 PM PDT 24
Peak memory 221388 kb
Host smart-5c67e040-9ba8-4175-bba0-14923045dcb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252132311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3252132311
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3809819164
Short name T245
Test name
Test status
Simulation time 191804127 ps
CPU time 1.36 seconds
Started Jun 02 02:43:33 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 215308 kb
Host smart-0ee772f1-1145-440b-bb00-f044ed14c74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809819164 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3809819164
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2484087923
Short name T414
Test name
Test status
Simulation time 14279302 ps
CPU time 0.92 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 206220 kb
Host smart-d5f8b558-16d4-472d-8273-4c8ea5ef1c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484087923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2484087923
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3193578522
Short name T503
Test name
Test status
Simulation time 34310155 ps
CPU time 0.87 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:44 PM PDT 24
Peak memory 213768 kb
Host smart-5fb995a8-e185-453d-bac1-103bcc262cb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193578522 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3193578522
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4270938980
Short name T661
Test name
Test status
Simulation time 43203201 ps
CPU time 1.15 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 217856 kb
Host smart-db1ac2a1-7ad2-4bd3-8059-16c65682fbf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270938980 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4270938980
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3416628093
Short name T821
Test name
Test status
Simulation time 35545488 ps
CPU time 0.92 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:46 PM PDT 24
Peak memory 218120 kb
Host smart-56bab097-c51b-44b5-9ab9-670d7b3a309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416628093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3416628093
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.434289065
Short name T411
Test name
Test status
Simulation time 52736485 ps
CPU time 1.38 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 216756 kb
Host smart-903f2544-a9d4-48d3-891c-cb41e4fcc482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434289065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.434289065
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.993118230
Short name T556
Test name
Test status
Simulation time 23629809 ps
CPU time 1.27 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 223564 kb
Host smart-d6953f0f-7f19-4e2c-9bfd-df4265b89a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993118230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.993118230
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3141548121
Short name T253
Test name
Test status
Simulation time 40676383 ps
CPU time 0.94 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:49 PM PDT 24
Peak memory 206772 kb
Host smart-4a8d3eca-d23c-4916-b011-198f5c097139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141548121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3141548121
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.163387727
Short name T20
Test name
Test status
Simulation time 645354282 ps
CPU time 7.03 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 235800 kb
Host smart-940573ae-7985-48c1-8e56-cacf8b125085
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163387727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.163387727
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2782290058
Short name T402
Test name
Test status
Simulation time 19742545 ps
CPU time 1.04 seconds
Started Jun 02 02:43:41 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 206728 kb
Host smart-2ee26c89-fbd1-40bc-b0f7-62be96f7b5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782290058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2782290058
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1096084159
Short name T736
Test name
Test status
Simulation time 130128350 ps
CPU time 2.98 seconds
Started Jun 02 02:43:30 PM PDT 24
Finished Jun 02 02:43:34 PM PDT 24
Peak memory 216600 kb
Host smart-cec1643e-81da-46b5-83d7-9a24ab6235be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096084159 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1096084159
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4288977172
Short name T200
Test name
Test status
Simulation time 8093147571 ps
CPU time 180.64 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:46:39 PM PDT 24
Peak memory 218556 kb
Host smart-aecf587e-302d-465b-8f82-9851ea507d06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288977172 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4288977172
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1702124326
Short name T252
Test name
Test status
Simulation time 81546279 ps
CPU time 1.19 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215316 kb
Host smart-c2cbb60b-e08d-4ec5-8dab-ff65f9ebd422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702124326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1702124326
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.941574519
Short name T598
Test name
Test status
Simulation time 21463208 ps
CPU time 0.86 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:29 PM PDT 24
Peak memory 206040 kb
Host smart-a7db90a7-3dc0-4329-bf7d-9348a1d68db4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941574519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.941574519
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3159112026
Short name T775
Test name
Test status
Simulation time 115507957 ps
CPU time 0.83 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215176 kb
Host smart-39f07ece-eb5b-4a5d-aeac-ecd71abcc0fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159112026 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3159112026
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2938393435
Short name T179
Test name
Test status
Simulation time 45972556 ps
CPU time 1.47 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 02:44:35 PM PDT 24
Peak memory 216648 kb
Host smart-dfa60346-a532-453c-a142-ba592e114118
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938393435 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2938393435
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.459585133
Short name T176
Test name
Test status
Simulation time 19044274 ps
CPU time 1.06 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 217864 kb
Host smart-a749f729-f138-4121-bcc7-f0ab0050f1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459585133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.459585133
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1697671400
Short name T322
Test name
Test status
Simulation time 42728292 ps
CPU time 1.49 seconds
Started Jun 02 02:44:49 PM PDT 24
Finished Jun 02 02:44:50 PM PDT 24
Peak memory 218116 kb
Host smart-90ae34cb-d445-4093-9164-ad48e7eb503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697671400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1697671400
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3356165958
Short name T109
Test name
Test status
Simulation time 29720726 ps
CPU time 0.89 seconds
Started Jun 02 02:44:39 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 215400 kb
Host smart-b8c346d7-0312-4e57-b625-bf9477cb9f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356165958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3356165958
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1527903200
Short name T514
Test name
Test status
Simulation time 31428689 ps
CPU time 0.91 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 214964 kb
Host smart-b6066b4b-0b6f-403a-b2a8-98e7bbe7148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527903200 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1527903200
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2054627523
Short name T26
Test name
Test status
Simulation time 308628083 ps
CPU time 5.94 seconds
Started Jun 02 02:44:40 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 216600 kb
Host smart-23129784-7ea5-45c4-9133-02cc1c438148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054627523 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2054627523
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.427534338
Short name T447
Test name
Test status
Simulation time 50597501942 ps
CPU time 1167.45 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 03:03:59 PM PDT 24
Peak memory 220636 kb
Host smart-f67804cc-206f-47c4-b36c-ce25a76fbef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427534338 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.427534338
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2573605947
Short name T258
Test name
Test status
Simulation time 31034192 ps
CPU time 1.31 seconds
Started Jun 02 02:44:49 PM PDT 24
Finished Jun 02 02:44:51 PM PDT 24
Peak memory 215324 kb
Host smart-98177f7a-c3bf-4e2d-ae55-dc7f3d9f85f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573605947 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2573605947
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.911083530
Short name T550
Test name
Test status
Simulation time 33113718 ps
CPU time 0.94 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 206248 kb
Host smart-dcd72331-08f7-4f3f-b217-1df42779c097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911083530 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.911083530
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.20325112
Short name T745
Test name
Test status
Simulation time 24298041 ps
CPU time 0.86 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 215988 kb
Host smart-1874f0c7-db4c-4aad-8acc-2f8e2ccb572a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.20325112
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3264473623
Short name T812
Test name
Test status
Simulation time 40064165 ps
CPU time 1.35 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 218876 kb
Host smart-9aa5e5f5-b4bb-4b01-8d7c-103dfb94a45e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264473623 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3264473623
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3478553323
Short name T646
Test name
Test status
Simulation time 32891478 ps
CPU time 0.95 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 219408 kb
Host smart-4253e4da-f655-46e0-a178-5a1cc83f9918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478553323 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3478553323
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2581740526
Short name T707
Test name
Test status
Simulation time 241119605 ps
CPU time 1.1 seconds
Started Jun 02 02:44:31 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 216644 kb
Host smart-a8ac9643-6502-44c4-95b7-54ef926fcf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581740526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2581740526
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3697580909
Short name T108
Test name
Test status
Simulation time 21353547 ps
CPU time 1.12 seconds
Started Jun 02 02:44:21 PM PDT 24
Finished Jun 02 02:44:24 PM PDT 24
Peak memory 215440 kb
Host smart-9dd65e47-f79a-4612-9dc4-947b8ef981e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697580909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3697580909
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3621301202
Short name T300
Test name
Test status
Simulation time 16894612 ps
CPU time 0.98 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 215000 kb
Host smart-ebf4a93a-14a2-4719-88ce-fda5f04e2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621301202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3621301202
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.865195090
Short name T737
Test name
Test status
Simulation time 530024822 ps
CPU time 6.33 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 216504 kb
Host smart-19467c05-189b-490f-9dfa-41375ac9ff87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865195090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.865195090
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2370447109
Short name T477
Test name
Test status
Simulation time 59919310594 ps
CPU time 688.43 seconds
Started Jun 02 02:44:41 PM PDT 24
Finished Jun 02 02:56:10 PM PDT 24
Peak memory 218904 kb
Host smart-7d12efae-b0b5-41cf-89ba-6f304d54e4de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370447109 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2370447109
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1381218992
Short name T256
Test name
Test status
Simulation time 96866460 ps
CPU time 1.23 seconds
Started Jun 02 02:44:45 PM PDT 24
Finished Jun 02 02:44:47 PM PDT 24
Peak memory 215108 kb
Host smart-b120b5b0-95de-4f32-a754-27f1435dd543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381218992 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1381218992
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.119335553
Short name T371
Test name
Test status
Simulation time 240677635 ps
CPU time 1.02 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 206344 kb
Host smart-b0a03df9-a342-4716-a210-ba44447fb233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119335553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.119335553
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.2739272045
Short name T735
Test name
Test status
Simulation time 24035407 ps
CPU time 0.88 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 216024 kb
Host smart-6db90482-9e1a-4b67-9be9-464bc6e2b77e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739272045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2739272045
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3380129762
Short name T55
Test name
Test status
Simulation time 45779482 ps
CPU time 1.5 seconds
Started Jun 02 02:44:20 PM PDT 24
Finished Jun 02 02:44:23 PM PDT 24
Peak memory 216488 kb
Host smart-d10605b7-32a8-4777-80e5-fbd26787d051
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380129762 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3380129762
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.669825356
Short name T170
Test name
Test status
Simulation time 75147494 ps
CPU time 1.32 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 225128 kb
Host smart-fe2f9242-cd00-43d3-9d8b-15c4bd001692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669825356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.669825356
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3694143618
Short name T628
Test name
Test status
Simulation time 33665484 ps
CPU time 1.35 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 218096 kb
Host smart-3852cada-82d0-4f90-aea7-a7b30ef88c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694143618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3694143618
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2342916253
Short name T828
Test name
Test status
Simulation time 33832991 ps
CPU time 0.99 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 223560 kb
Host smart-d6297f19-aebc-4f66-85ad-c139fb4444c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342916253 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2342916253
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3152458290
Short name T602
Test name
Test status
Simulation time 25929668 ps
CPU time 0.94 seconds
Started Jun 02 02:44:32 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 214952 kb
Host smart-3e6d3a8a-7d82-4c34-8eac-7b2e664b378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152458290 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3152458290
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1389407224
Short name T461
Test name
Test status
Simulation time 57454612 ps
CPU time 1.28 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 217868 kb
Host smart-48740b86-2a5d-47e0-95bc-af13c502c027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389407224 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1389407224
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.266072064
Short name T276
Test name
Test status
Simulation time 280272765056 ps
CPU time 1192.58 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 03:04:18 PM PDT 24
Peak memory 223848 kb
Host smart-671b5c63-b845-4e49-8397-5a920bf2f308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266072064 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.266072064
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert_test.560791453
Short name T586
Test name
Test status
Simulation time 19617164 ps
CPU time 0.8 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 206096 kb
Host smart-02de5f4f-8862-48a3-bc28-65f47563fc21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560791453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.560791453
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2575612908
Short name T77
Test name
Test status
Simulation time 14076973 ps
CPU time 0.95 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 216136 kb
Host smart-df80bc40-be7b-402d-ac19-9fbf917bd127
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575612908 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2575612908
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.485098336
Short name T39
Test name
Test status
Simulation time 49400486 ps
CPU time 1.16 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 216696 kb
Host smart-3a70c614-70eb-45a5-af4e-8c78524515c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485098336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.485098336
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3898193734
Short name T51
Test name
Test status
Simulation time 59231465 ps
CPU time 1.24 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 225100 kb
Host smart-f84ce1d0-2717-4a19-8124-71965def2f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898193734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3898193734
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.356927276
Short name T667
Test name
Test status
Simulation time 235069724 ps
CPU time 1.37 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:38 PM PDT 24
Peak memory 216792 kb
Host smart-9e62a751-b0f8-4705-a7ee-c882e2b4310e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356927276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.356927276
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.427301765
Short name T225
Test name
Test status
Simulation time 23527306 ps
CPU time 1.06 seconds
Started Jun 02 02:44:26 PM PDT 24
Finished Jun 02 02:44:28 PM PDT 24
Peak memory 215052 kb
Host smart-39fa31a3-b44f-43e3-9c3b-ccde86ed405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427301765 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.427301765
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1427110169
Short name T727
Test name
Test status
Simulation time 51322025 ps
CPU time 0.9 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 206792 kb
Host smart-44c550f4-ea79-4305-8169-e120ccd16b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427110169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1427110169
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.612342239
Short name T149
Test name
Test status
Simulation time 132196579 ps
CPU time 3.08 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 216468 kb
Host smart-95de635d-21de-4c45-a78a-6ccf32515ea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612342239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.612342239
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3112679020
Short name T649
Test name
Test status
Simulation time 44943967340 ps
CPU time 1039.83 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 03:01:54 PM PDT 24
Peak memory 219104 kb
Host smart-0c56f4ec-4d26-46de-98ea-7326f6869a7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112679020 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3112679020
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2701029373
Short name T444
Test name
Test status
Simulation time 25790715 ps
CPU time 1.29 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 215360 kb
Host smart-a2e297a0-565d-40d0-b618-8db83f3806e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701029373 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2701029373
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.4174901373
Short name T454
Test name
Test status
Simulation time 37112689 ps
CPU time 0.81 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:56 PM PDT 24
Peak memory 206572 kb
Host smart-fa7ed5cd-7018-4c98-a92a-2fb6f4b748ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174901373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.4174901373
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3527469099
Short name T140
Test name
Test status
Simulation time 29782696 ps
CPU time 0.81 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:25 PM PDT 24
Peak memory 215676 kb
Host smart-943b9abf-8191-4736-8e90-b7a1c400a14e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527469099 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3527469099
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2339977752
Short name T811
Test name
Test status
Simulation time 22266826 ps
CPU time 0.98 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 216472 kb
Host smart-387bbd16-6e64-4806-8633-64f35facf449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339977752 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2339977752
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3520376396
Short name T58
Test name
Test status
Simulation time 39607919 ps
CPU time 1.29 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 225136 kb
Host smart-886ebd72-beb5-4442-a3da-81cd4ee1b67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520376396 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3520376396
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1198443635
Short name T321
Test name
Test status
Simulation time 83816373 ps
CPU time 1.28 seconds
Started Jun 02 02:44:29 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 219288 kb
Host smart-ec1388f6-3d16-4205-9244-e22d365f2de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198443635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1198443635
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4001202297
Short name T308
Test name
Test status
Simulation time 37242648 ps
CPU time 0.88 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 215036 kb
Host smart-8c152779-426a-4443-9490-ec7bf9bf4f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001202297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4001202297
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2654537453
Short name T809
Test name
Test status
Simulation time 16393142 ps
CPU time 0.96 seconds
Started Jun 02 02:44:23 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 214980 kb
Host smart-601238d2-918c-413d-bafd-dfbb53b76397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654537453 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2654537453
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.751110794
Short name T408
Test name
Test status
Simulation time 39484122 ps
CPU time 1.37 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 214788 kb
Host smart-e2a7b8c9-4631-4210-b138-fe48d9245866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751110794 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.751110794
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1274137129
Short name T650
Test name
Test status
Simulation time 31747731446 ps
CPU time 666.08 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:55:41 PM PDT 24
Peak memory 216988 kb
Host smart-11844ed8-7961-4283-9670-874924ade02e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274137129 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1274137129
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.3721687462
Short name T154
Test name
Test status
Simulation time 15224968 ps
CPU time 0.89 seconds
Started Jun 02 02:44:26 PM PDT 24
Finished Jun 02 02:44:28 PM PDT 24
Peak memory 206212 kb
Host smart-fe4eecda-e535-427a-aa1d-8c448ac9d700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721687462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3721687462
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2679127504
Short name T439
Test name
Test status
Simulation time 21726519 ps
CPU time 0.87 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 216072 kb
Host smart-4362b414-a0b8-4753-a7fb-b2edabaa61a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679127504 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2679127504
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3356063782
Short name T480
Test name
Test status
Simulation time 27851545 ps
CPU time 1.12 seconds
Started Jun 02 02:44:31 PM PDT 24
Finished Jun 02 02:44:33 PM PDT 24
Peak memory 217868 kb
Host smart-ae3d857a-0f3d-4e57-9d4a-20093119aab8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356063782 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3356063782
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3509346988
Short name T612
Test name
Test status
Simulation time 69184810 ps
CPU time 1.12 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 225100 kb
Host smart-12b6ad5c-05ed-4837-af87-59b3e68868d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509346988 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3509346988
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1191653061
Short name T567
Test name
Test status
Simulation time 146742943 ps
CPU time 1.35 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:44:52 PM PDT 24
Peak memory 218332 kb
Host smart-0bb9d1a5-f71f-46b9-a8fd-6ebfa1a0b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191653061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1191653061
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3202408451
Short name T757
Test name
Test status
Simulation time 22767135 ps
CPU time 0.93 seconds
Started Jun 02 02:44:33 PM PDT 24
Finished Jun 02 02:44:35 PM PDT 24
Peak memory 215308 kb
Host smart-9687db87-e025-410c-bd54-2c56d0fceda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202408451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3202408451
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2663752351
Short name T633
Test name
Test status
Simulation time 16268383 ps
CPU time 0.96 seconds
Started Jun 02 02:44:28 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 214972 kb
Host smart-e41f948b-4ab3-4927-a97b-6cf6f8f5c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663752351 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2663752351
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1387250139
Short name T781
Test name
Test status
Simulation time 265138476 ps
CPU time 3.2 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:31 PM PDT 24
Peak memory 216756 kb
Host smart-4619230b-cf07-44cc-8fc7-0a2c887099fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387250139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1387250139
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4078523005
Short name T584
Test name
Test status
Simulation time 92736824029 ps
CPU time 722.41 seconds
Started Jun 02 02:44:40 PM PDT 24
Finished Jun 02 02:56:43 PM PDT 24
Peak memory 223328 kb
Host smart-45dbec59-4d77-41c1-8d7f-bb07240fb399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078523005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4078523005
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.125547240
Short name T144
Test name
Test status
Simulation time 82592493 ps
CPU time 1.23 seconds
Started Jun 02 02:44:32 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 215320 kb
Host smart-19ab12c6-7fa2-44fd-912c-389b01171f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125547240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.125547240
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2596059904
Short name T593
Test name
Test status
Simulation time 18563981 ps
CPU time 0.99 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 02:44:26 PM PDT 24
Peak memory 214344 kb
Host smart-87952fb1-480f-4cc4-baaf-0fc7321c2c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596059904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2596059904
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1464267396
Short name T42
Test name
Test status
Simulation time 258801295 ps
CPU time 1.12 seconds
Started Jun 02 02:44:28 PM PDT 24
Finished Jun 02 02:44:30 PM PDT 24
Peak memory 216720 kb
Host smart-081664f7-d5e7-4a79-b11d-fec476b16394
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464267396 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1464267396
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2943972580
Short name T583
Test name
Test status
Simulation time 25186933 ps
CPU time 0.89 seconds
Started Jun 02 02:44:27 PM PDT 24
Finished Jun 02 02:44:35 PM PDT 24
Peak memory 217900 kb
Host smart-14604eec-3c4a-4fc7-aecb-7e7394fbb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943972580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2943972580
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.466088183
Short name T369
Test name
Test status
Simulation time 168765677 ps
CPU time 3.78 seconds
Started Jun 02 02:44:32 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 219536 kb
Host smart-21384331-4d78-4d17-b7aa-42358ca4c60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466088183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.466088183
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.74802121
Short name T792
Test name
Test status
Simulation time 38742796 ps
CPU time 0.88 seconds
Started Jun 02 02:44:24 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 214996 kb
Host smart-069919c8-d2f6-4968-a381-c1c6d94e2720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74802121 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.74802121
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3031676657
Short name T337
Test name
Test status
Simulation time 41681370 ps
CPU time 0.89 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 215228 kb
Host smart-54e19216-dd44-4bb2-b914-f3e9c809866e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031676657 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3031676657
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1855705369
Short name T768
Test name
Test status
Simulation time 32862389 ps
CPU time 1.29 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 214932 kb
Host smart-31998e29-7c0a-460d-99c1-b1b3c94d6b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855705369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1855705369
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.575786313
Short name T192
Test name
Test status
Simulation time 40501060632 ps
CPU time 507.2 seconds
Started Jun 02 02:44:36 PM PDT 24
Finished Jun 02 02:53:04 PM PDT 24
Peak memory 223464 kb
Host smart-95f68681-a059-4f73-becb-d568dbbdb4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575786313 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.575786313
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2589317730
Short name T806
Test name
Test status
Simulation time 48589791 ps
CPU time 1.26 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:45:01 PM PDT 24
Peak memory 215340 kb
Host smart-066f57ee-b3d4-4a85-b7f0-5eb966ff0abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589317730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2589317730
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.926158441
Short name T318
Test name
Test status
Simulation time 43730186 ps
CPU time 0.92 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 206292 kb
Host smart-5e94a985-f37b-481c-8675-d595ffd1983a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926158441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.926158441
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.921503481
Short name T134
Test name
Test status
Simulation time 37422812 ps
CPU time 0.84 seconds
Started Jun 02 02:44:40 PM PDT 24
Finished Jun 02 02:44:41 PM PDT 24
Peak memory 216004 kb
Host smart-d439d4cd-acbb-4d8f-9df9-7193b8c7ff8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921503481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.921503481
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.454666431
Short name T659
Test name
Test status
Simulation time 252117380 ps
CPU time 1.19 seconds
Started Jun 02 02:45:03 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 216460 kb
Host smart-7a84d604-506c-41da-821d-aafa961e7755
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454666431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.454666431
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.880121852
Short name T79
Test name
Test status
Simulation time 31531586 ps
CPU time 0.85 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 217816 kb
Host smart-5548ad5c-5691-4951-ae78-52a5af7ed85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880121852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.880121852
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3665928702
Short name T541
Test name
Test status
Simulation time 30994417 ps
CPU time 1.16 seconds
Started Jun 02 02:44:25 PM PDT 24
Finished Jun 02 02:44:27 PM PDT 24
Peak memory 216648 kb
Host smart-625196db-825f-4f41-b8ac-3181f1d571c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665928702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3665928702
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1259959836
Short name T521
Test name
Test status
Simulation time 26445054 ps
CPU time 1 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 215268 kb
Host smart-7f678ff4-2096-4d1b-a934-ad75023cde4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259959836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1259959836
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.827873100
Short name T704
Test name
Test status
Simulation time 70028652 ps
CPU time 0.87 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 214952 kb
Host smart-e932754e-0d48-414b-9fae-8d3018ac79a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827873100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.827873100
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3749512284
Short name T641
Test name
Test status
Simulation time 236001491 ps
CPU time 4.99 seconds
Started Jun 02 02:44:41 PM PDT 24
Finished Jun 02 02:44:47 PM PDT 24
Peak memory 215032 kb
Host smart-f1f83e08-9ebd-4ba1-92b4-d1930dc2fa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749512284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3749512284
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.544690681
Short name T635
Test name
Test status
Simulation time 271596369783 ps
CPU time 719.89 seconds
Started Jun 02 02:44:22 PM PDT 24
Finished Jun 02 02:56:23 PM PDT 24
Peak memory 220628 kb
Host smart-5439bb58-b3e2-45d4-bb81-c15dc333bfe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544690681 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.544690681
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.3657995954
Short name T634
Test name
Test status
Simulation time 27365833 ps
CPU time 1.27 seconds
Started Jun 02 02:44:48 PM PDT 24
Finished Jun 02 02:44:50 PM PDT 24
Peak memory 215336 kb
Host smart-a255a060-e8ed-4bb5-a19c-3add625bacba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657995954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3657995954
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2476919323
Short name T362
Test name
Test status
Simulation time 14729808 ps
CPU time 0.94 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:56 PM PDT 24
Peak memory 206184 kb
Host smart-9e14b19d-dadd-471f-ae3c-0e0e97c44331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476919323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2476919323
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2256996988
Short name T61
Test name
Test status
Simulation time 34678146 ps
CPU time 0.83 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:56 PM PDT 24
Peak memory 215140 kb
Host smart-21f79890-885a-4dcc-9aab-c1d4a6718174
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256996988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2256996988
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3482048044
Short name T526
Test name
Test status
Simulation time 118479831 ps
CPU time 1.06 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 216516 kb
Host smart-3f60826c-6b44-4dde-81f8-1dd0645b1768
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482048044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3482048044
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.946803520
Short name T164
Test name
Test status
Simulation time 28785743 ps
CPU time 0.97 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 218160 kb
Host smart-1a418576-a099-49b7-9c31-efb5b3bd22c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946803520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.946803520
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3449993080
Short name T455
Test name
Test status
Simulation time 36371853 ps
CPU time 1.53 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 219408 kb
Host smart-3e698f22-cbf1-4d0c-8d1f-8c94ccea76d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449993080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3449993080
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.774218319
Short name T748
Test name
Test status
Simulation time 84891585 ps
CPU time 0.83 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 215248 kb
Host smart-d8e0e8fe-2532-418d-b734-97d460078040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774218319 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.774218319
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1139242189
Short name T819
Test name
Test status
Simulation time 19804626 ps
CPU time 1.06 seconds
Started Jun 02 02:44:35 PM PDT 24
Finished Jun 02 02:44:37 PM PDT 24
Peak memory 214960 kb
Host smart-e9ccece3-31bc-4ebb-9b17-eaa473c5c149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139242189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1139242189
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1421850821
Short name T353
Test name
Test status
Simulation time 1250339055 ps
CPU time 3.88 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 214948 kb
Host smart-e6404697-dec7-46d1-8ae4-323ac8358c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421850821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1421850821
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2201772971
Short name T398
Test name
Test status
Simulation time 111562250285 ps
CPU time 609.29 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:55:08 PM PDT 24
Peak memory 220048 kb
Host smart-3edbab49-3a24-4918-9883-11a0e6ba2d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201772971 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2201772971
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1350070997
Short name T250
Test name
Test status
Simulation time 23387592 ps
CPU time 1.18 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 215344 kb
Host smart-6ba58c88-2459-4939-a415-aa2dc090da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350070997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1350070997
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2093864329
Short name T327
Test name
Test status
Simulation time 18572714 ps
CPU time 1.01 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 206204 kb
Host smart-e74383e9-7429-4491-8692-bcdac7f88406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093864329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2093864329
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1779263393
Short name T840
Test name
Test status
Simulation time 39793660 ps
CPU time 0.84 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 215164 kb
Host smart-c342d2c1-3ff5-4584-b5b9-0512317c2b84
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779263393 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1779263393
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3765298618
Short name T595
Test name
Test status
Simulation time 73449364 ps
CPU time 1.13 seconds
Started Jun 02 02:44:45 PM PDT 24
Finished Jun 02 02:44:47 PM PDT 24
Peak memory 216380 kb
Host smart-d2fcc0be-1fa3-4ec7-8ac4-6ac65c2eb2f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765298618 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3765298618
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1912491358
Short name T504
Test name
Test status
Simulation time 34047211 ps
CPU time 1.03 seconds
Started Jun 02 02:44:32 PM PDT 24
Finished Jun 02 02:44:34 PM PDT 24
Peak memory 223216 kb
Host smart-24a9cadd-54a4-48c0-9a2d-79752bbd24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912491358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1912491358
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2030124082
Short name T753
Test name
Test status
Simulation time 242543420 ps
CPU time 1.17 seconds
Started Jun 02 02:44:40 PM PDT 24
Finished Jun 02 02:44:41 PM PDT 24
Peak memory 216804 kb
Host smart-86e02305-a945-45d2-b46d-d033cd50b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030124082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2030124082
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.267258867
Short name T396
Test name
Test status
Simulation time 17612252 ps
CPU time 0.99 seconds
Started Jun 02 02:45:02 PM PDT 24
Finished Jun 02 02:45:04 PM PDT 24
Peak memory 214964 kb
Host smart-006b9daf-7a8b-4b1d-8d01-ffbd41d043f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267258867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.267258867
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3192004325
Short name T297
Test name
Test status
Simulation time 813309789 ps
CPU time 4.74 seconds
Started Jun 02 02:44:37 PM PDT 24
Finished Jun 02 02:44:42 PM PDT 24
Peak memory 216456 kb
Host smart-d8491e2a-0629-4ab4-bc13-487c75be6186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192004325 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3192004325
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3303367708
Short name T842
Test name
Test status
Simulation time 59474599820 ps
CPU time 744.2 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:57:15 PM PDT 24
Peak memory 219796 kb
Host smart-dee043fe-9962-42d8-9b48-5f30ffe01022
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303367708 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3303367708
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1925199278
Short name T95
Test name
Test status
Simulation time 50817690 ps
CPU time 1.23 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:45 PM PDT 24
Peak memory 213360 kb
Host smart-c8a1be10-cd5e-46d2-8e4d-fc52f5985454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925199278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1925199278
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.505746994
Short name T796
Test name
Test status
Simulation time 19882575 ps
CPU time 1.05 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 214564 kb
Host smart-74e9b164-b994-4926-81a5-de50bd1340aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505746994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.505746994
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.4246892137
Short name T227
Test name
Test status
Simulation time 17003267 ps
CPU time 0.89 seconds
Started Jun 02 02:43:31 PM PDT 24
Finished Jun 02 02:43:33 PM PDT 24
Peak memory 215588 kb
Host smart-ce98f9a5-3664-4f68-adc8-f0da1aff5006
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246892137 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.4246892137
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1967456864
Short name T779
Test name
Test status
Simulation time 78081065 ps
CPU time 1.11 seconds
Started Jun 02 02:43:39 PM PDT 24
Finished Jun 02 02:43:41 PM PDT 24
Peak memory 217936 kb
Host smart-1c999bc9-3609-48eb-9be1-7467cbdb60f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967456864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1967456864
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.677734520
Short name T728
Test name
Test status
Simulation time 87007409 ps
CPU time 1.03 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 218156 kb
Host smart-813cf66a-b831-40ae-b602-be641f45735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677734520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.677734520
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2099327691
Short name T589
Test name
Test status
Simulation time 41018378 ps
CPU time 1.41 seconds
Started Jun 02 02:43:53 PM PDT 24
Finished Jun 02 02:43:54 PM PDT 24
Peak memory 217944 kb
Host smart-84e6eebd-f481-4b9f-9e86-94b0801e06d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099327691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2099327691
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.4129562513
Short name T430
Test name
Test status
Simulation time 24734866 ps
CPU time 1.09 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 223544 kb
Host smart-7a8a1568-9395-489f-bf04-13d021381a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129562513 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.4129562513
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3748054868
Short name T247
Test name
Test status
Simulation time 26448051 ps
CPU time 0.92 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 206736 kb
Host smart-44dc1fae-ce00-4b2a-b88e-98ce05d01546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748054868 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3748054868
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1801453859
Short name T420
Test name
Test status
Simulation time 23853090 ps
CPU time 0.93 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:43:53 PM PDT 24
Peak memory 215092 kb
Host smart-0a223229-6712-4111-9232-b264e7a424b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801453859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1801453859
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2035347180
Short name T128
Test name
Test status
Simulation time 718747014 ps
CPU time 3.46 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:47 PM PDT 24
Peak memory 214068 kb
Host smart-e6f4fcf4-9565-43a3-9f1c-64b7a381b734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035347180 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2035347180
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1282087407
Short name T199
Test name
Test status
Simulation time 80751416910 ps
CPU time 1476.66 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 03:09:21 PM PDT 24
Peak memory 223388 kb
Host smart-1024367c-a5a6-4a91-92d7-022d471fdda6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282087407 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1282087407
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2756390609
Short name T458
Test name
Test status
Simulation time 28909898 ps
CPU time 0.83 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 217740 kb
Host smart-ff10e200-01a7-4404-bb71-99a84ea33fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756390609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2756390609
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1944037359
Short name T501
Test name
Test status
Simulation time 67400429 ps
CPU time 1.38 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 216744 kb
Host smart-dea22de1-48c9-4f30-ae17-1e0a01932f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944037359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1944037359
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.249444986
Short name T784
Test name
Test status
Simulation time 24881314 ps
CPU time 0.95 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 219352 kb
Host smart-6f7e0689-0fe5-4694-aeb6-9b3c7cfa0f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249444986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.249444986
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.2104192091
Short name T562
Test name
Test status
Simulation time 231101058 ps
CPU time 1.51 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 216944 kb
Host smart-a2a06659-8ee3-445e-88c7-e5b23d24795a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104192091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.2104192091
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.646935525
Short name T59
Test name
Test status
Simulation time 19011309 ps
CPU time 1.03 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 217912 kb
Host smart-d4a48117-2353-4594-a538-d23850b94d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646935525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.646935525
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/53.edn_err.3103049435
Short name T525
Test name
Test status
Simulation time 33006758 ps
CPU time 0.97 seconds
Started Jun 02 02:44:30 PM PDT 24
Finished Jun 02 02:44:32 PM PDT 24
Peak memory 218320 kb
Host smart-3b86b611-d769-4a0a-b355-11268bb0a942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103049435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3103049435
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4059460864
Short name T264
Test name
Test status
Simulation time 32535649 ps
CPU time 1.38 seconds
Started Jun 02 02:44:41 PM PDT 24
Finished Jun 02 02:44:43 PM PDT 24
Peak memory 217900 kb
Host smart-e7dcbc0d-a825-4a5b-80bf-f2333d32ab0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059460864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4059460864
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2271219965
Short name T101
Test name
Test status
Simulation time 32755699 ps
CPU time 0.9 seconds
Started Jun 02 02:44:41 PM PDT 24
Finished Jun 02 02:44:43 PM PDT 24
Peak memory 218116 kb
Host smart-60c18b82-4555-4855-bf56-9beb2f116c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271219965 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2271219965
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.4200744351
Short name T512
Test name
Test status
Simulation time 82611809 ps
CPU time 1.24 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 216640 kb
Host smart-ae410045-02af-4e2f-9491-f7d882428759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200744351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4200744351
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.4271369642
Short name T75
Test name
Test status
Simulation time 22122180 ps
CPU time 1.02 seconds
Started Jun 02 02:44:34 PM PDT 24
Finished Jun 02 02:44:36 PM PDT 24
Peak memory 223440 kb
Host smart-a49b258e-0423-4d99-8cf3-cfb50b38eacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271369642 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.4271369642
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1803100478
Short name T405
Test name
Test status
Simulation time 58147247 ps
CPU time 1.22 seconds
Started Jun 02 02:44:41 PM PDT 24
Finished Jun 02 02:44:43 PM PDT 24
Peak memory 218884 kb
Host smart-ac089447-bf78-4665-99e1-0b8265e5a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803100478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1803100478
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1002507919
Short name T462
Test name
Test status
Simulation time 53633968 ps
CPU time 0.91 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 219400 kb
Host smart-703600f9-464e-41f9-8296-db9a9004c8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002507919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1002507919
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1839368771
Short name T726
Test name
Test status
Simulation time 74186262 ps
CPU time 1.14 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:44 PM PDT 24
Peak memory 216748 kb
Host smart-7802b6a4-4aa2-455a-84fb-54f4dc508485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839368771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1839368771
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2677592437
Short name T333
Test name
Test status
Simulation time 29121928 ps
CPU time 0.93 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:56 PM PDT 24
Peak memory 223224 kb
Host smart-633b8c3e-b4b8-481d-a89f-44ae9e1b9be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677592437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2677592437
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2226512706
Short name T622
Test name
Test status
Simulation time 73237139 ps
CPU time 1.09 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 219276 kb
Host smart-609216a7-5459-4eaa-9480-e2e4522b6cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226512706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2226512706
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2617279414
Short name T242
Test name
Test status
Simulation time 30631658 ps
CPU time 0.89 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 217892 kb
Host smart-328c20ce-0555-4517-a6c5-a138cf0f2f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617279414 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2617279414
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2946819834
Short name T388
Test name
Test status
Simulation time 41967956 ps
CPU time 1.5 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:56 PM PDT 24
Peak memory 217052 kb
Host smart-daa4a9f9-e409-448f-bcaf-bf94712c587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946819834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2946819834
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.526185545
Short name T7
Test name
Test status
Simulation time 25785137 ps
CPU time 1.14 seconds
Started Jun 02 02:44:40 PM PDT 24
Finished Jun 02 02:44:42 PM PDT 24
Peak memory 229072 kb
Host smart-1e0308d8-d962-4713-846a-527e46eadd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526185545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.526185545
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3395675042
Short name T356
Test name
Test status
Simulation time 54214189 ps
CPU time 1.04 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:45 PM PDT 24
Peak memory 216704 kb
Host smart-f164720c-c83a-44be-86c0-4635c50a34d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395675042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3395675042
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3449799266
Short name T565
Test name
Test status
Simulation time 41364456 ps
CPU time 1.19 seconds
Started Jun 02 02:44:19 PM PDT 24
Finished Jun 02 02:44:21 PM PDT 24
Peak memory 215360 kb
Host smart-e9806b60-a59f-4c2b-8207-85f663b8ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449799266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3449799266
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2801998376
Short name T780
Test name
Test status
Simulation time 86953498 ps
CPU time 0.88 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 206244 kb
Host smart-4d567c13-592b-41d3-bb7b-6dd9c0be728a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801998376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2801998376
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.114796928
Short name T135
Test name
Test status
Simulation time 32536536 ps
CPU time 0.83 seconds
Started Jun 02 02:43:37 PM PDT 24
Finished Jun 02 02:43:39 PM PDT 24
Peak memory 216088 kb
Host smart-658d537f-fc8b-42e6-8946-ca110197def3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114796928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.114796928
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3912108452
Short name T729
Test name
Test status
Simulation time 67908396 ps
CPU time 1.01 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 216424 kb
Host smart-4273f93b-038d-4c73-a3ab-b0edeb0210c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912108452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3912108452
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.972514010
Short name T5
Test name
Test status
Simulation time 86629337 ps
CPU time 1.14 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 219112 kb
Host smart-76afe673-5d9b-4afb-9ab6-fae7ead076c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972514010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.972514010
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2735071360
Short name T557
Test name
Test status
Simulation time 43631987 ps
CPU time 1.3 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:45 PM PDT 24
Peak memory 217556 kb
Host smart-8ad01c38-ac8d-467f-adf2-387991f24a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735071360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2735071360
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2802717079
Short name T522
Test name
Test status
Simulation time 95760510 ps
CPU time 0.87 seconds
Started Jun 02 02:43:57 PM PDT 24
Finished Jun 02 02:43:59 PM PDT 24
Peak memory 215136 kb
Host smart-da500c7e-6b4f-4e06-9768-d7b254f72f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802717079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2802717079
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.145467301
Short name T443
Test name
Test status
Simulation time 50799062 ps
CPU time 0.9 seconds
Started Jun 02 02:43:34 PM PDT 24
Finished Jun 02 02:43:35 PM PDT 24
Peak memory 214988 kb
Host smart-81632940-9138-4d7a-962f-979d64bae8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145467301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.145467301
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.190275664
Short name T299
Test name
Test status
Simulation time 362290026 ps
CPU time 4.35 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:43:56 PM PDT 24
Peak memory 214968 kb
Host smart-9a423947-fe2e-4ff8-8a14-f38a9e5be5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190275664 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.190275664
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3580187279
Short name T126
Test name
Test status
Simulation time 25097650462 ps
CPU time 619.74 seconds
Started Jun 02 02:43:47 PM PDT 24
Finished Jun 02 02:54:08 PM PDT 24
Peak memory 216692 kb
Host smart-5f8cfe44-1602-42cf-b3f8-77ebf1e4ce4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580187279 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3580187279
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1688630917
Short name T730
Test name
Test status
Simulation time 24946193 ps
CPU time 1.29 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 218108 kb
Host smart-059b714c-b789-4d52-a03d-afc9b7df25aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688630917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1688630917
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1022786746
Short name T531
Test name
Test status
Simulation time 46151560 ps
CPU time 1.64 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 218008 kb
Host smart-2e2798c8-f7b6-490a-8730-f35e473599bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022786746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1022786746
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2799413513
Short name T581
Test name
Test status
Simulation time 115066517 ps
CPU time 0.99 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 220252 kb
Host smart-7d666817-de48-4fac-85e0-622c307cf78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799413513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2799413513
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1536905901
Short name T554
Test name
Test status
Simulation time 45160598 ps
CPU time 1.48 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:40 PM PDT 24
Peak memory 216616 kb
Host smart-d2723f45-d0e1-4b6a-8902-6721f06e2be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536905901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1536905901
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2377199949
Short name T163
Test name
Test status
Simulation time 29379389 ps
CPU time 1.26 seconds
Started Jun 02 02:44:47 PM PDT 24
Finished Jun 02 02:44:48 PM PDT 24
Peak memory 219240 kb
Host smart-b03c40c1-3547-4911-90ff-407055637840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377199949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2377199949
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2112406741
Short name T372
Test name
Test status
Simulation time 87595038 ps
CPU time 2.67 seconds
Started Jun 02 02:44:49 PM PDT 24
Finished Jun 02 02:44:52 PM PDT 24
Peak memory 219456 kb
Host smart-5e3cea7d-0aeb-468b-9ddc-2f4aaa1d46ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112406741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2112406741
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.810243754
Short name T71
Test name
Test status
Simulation time 48208864 ps
CPU time 0.97 seconds
Started Jun 02 02:44:46 PM PDT 24
Finished Jun 02 02:44:48 PM PDT 24
Peak memory 223264 kb
Host smart-fe2c1f8b-9f71-4fe9-8e7f-95d90b4a487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810243754 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.810243754
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.583858697
Short name T807
Test name
Test status
Simulation time 39877224 ps
CPU time 1.12 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 217936 kb
Host smart-a250735d-d68a-4e31-8757-473eaff2b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583858697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.583858697
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4287836648
Short name T519
Test name
Test status
Simulation time 23152609 ps
CPU time 0.96 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 218128 kb
Host smart-870dd5f0-8e20-4f66-8171-005ca0266dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287836648 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4287836648
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3771938556
Short name T363
Test name
Test status
Simulation time 53276323 ps
CPU time 1.3 seconds
Started Jun 02 02:44:36 PM PDT 24
Finished Jun 02 02:44:43 PM PDT 24
Peak memory 216732 kb
Host smart-e8fc138d-086e-420e-9f7f-5f89238910cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771938556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3771938556
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2855064900
Short name T46
Test name
Test status
Simulation time 20084577 ps
CPU time 1.23 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 228972 kb
Host smart-d2029b11-e632-4f2b-829a-a9016d147a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855064900 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2855064900
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3753660131
Short name T603
Test name
Test status
Simulation time 77957878 ps
CPU time 1.93 seconds
Started Jun 02 02:44:51 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 218196 kb
Host smart-d7a9910c-69e2-4fff-a310-6f9ee00ff9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753660131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3753660131
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.717389648
Short name T273
Test name
Test status
Simulation time 47506899 ps
CPU time 1.13 seconds
Started Jun 02 02:44:46 PM PDT 24
Finished Jun 02 02:44:48 PM PDT 24
Peak memory 218252 kb
Host smart-86bff014-5b15-44cc-af29-6b31d799e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717389648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.717389648
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3778705798
Short name T69
Test name
Test status
Simulation time 31687852 ps
CPU time 1.3 seconds
Started Jun 02 02:44:48 PM PDT 24
Finished Jun 02 02:44:50 PM PDT 24
Peak memory 225056 kb
Host smart-5ca3090c-eea0-4b86-ba24-06b9e5bfeb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778705798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3778705798
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2627891555
Short name T705
Test name
Test status
Simulation time 33706721 ps
CPU time 1.48 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 216616 kb
Host smart-bfdd4395-141b-4cf0-bdd4-f23d534aad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627891555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2627891555
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.850848075
Short name T316
Test name
Test status
Simulation time 27938097 ps
CPU time 1.01 seconds
Started Jun 02 02:45:04 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 223276 kb
Host smart-07b124f0-2b9d-444a-93e0-a2757add6a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850848075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.850848075
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2762047767
Short name T350
Test name
Test status
Simulation time 428847553 ps
CPU time 1.34 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 216748 kb
Host smart-88702c9c-fa8e-4db2-836f-e3a9d07b2412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762047767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2762047767
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.4068124437
Short name T45
Test name
Test status
Simulation time 41893854 ps
CPU time 0.91 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 219156 kb
Host smart-8b7d832f-db64-42c0-ac6c-e2c0058a012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068124437 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.4068124437
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2007476595
Short name T262
Test name
Test status
Simulation time 37462464 ps
CPU time 1.34 seconds
Started Jun 02 02:45:00 PM PDT 24
Finished Jun 02 02:45:02 PM PDT 24
Peak memory 216840 kb
Host smart-021609bb-e0a3-4216-ac0a-3c60e014d36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007476595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2007476595
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.3141820529
Short name T254
Test name
Test status
Simulation time 27278973 ps
CPU time 1.22 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 215128 kb
Host smart-a3dac937-275f-45ed-9def-9b65218e375d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141820529 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3141820529
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1302525289
Short name T717
Test name
Test status
Simulation time 20417691 ps
CPU time 1.06 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:43 PM PDT 24
Peak memory 206208 kb
Host smart-88df6133-47ac-4970-a181-8942d273100f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302525289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1302525289
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.767739981
Short name T528
Test name
Test status
Simulation time 28894218 ps
CPU time 0.83 seconds
Started Jun 02 02:44:03 PM PDT 24
Finished Jun 02 02:44:04 PM PDT 24
Peak memory 216000 kb
Host smart-0d873fd7-8db7-4db0-aa52-55f34fffcc17
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767739981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.767739981
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2432954551
Short name T665
Test name
Test status
Simulation time 24581463 ps
CPU time 1.07 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 217896 kb
Host smart-dc06b52e-d882-41b5-b826-d7962f1aee81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432954551 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2432954551
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.660021599
Short name T40
Test name
Test status
Simulation time 25648561 ps
CPU time 1.27 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:02 PM PDT 24
Peak memory 219948 kb
Host smart-837f8965-1b53-4a41-8a79-64c01659527c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660021599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.660021599
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.846326913
Short name T599
Test name
Test status
Simulation time 29280009 ps
CPU time 1.04 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 216896 kb
Host smart-1ae92f0d-41c6-4eab-a9d5-c53d380ea77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846326913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.846326913
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1883407512
Short name T228
Test name
Test status
Simulation time 36662028 ps
CPU time 0.86 seconds
Started Jun 02 02:43:35 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 215116 kb
Host smart-450690b7-4f28-4232-926b-4836ed6cd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883407512 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1883407512
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.930349213
Short name T257
Test name
Test status
Simulation time 113409408 ps
CPU time 0.89 seconds
Started Jun 02 02:43:41 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 206568 kb
Host smart-c842cf93-1a28-4b92-95c5-748987daa9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930349213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.930349213
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1191033669
Short name T328
Test name
Test status
Simulation time 37438346 ps
CPU time 0.92 seconds
Started Jun 02 02:43:46 PM PDT 24
Finished Jun 02 02:43:47 PM PDT 24
Peak memory 215048 kb
Host smart-b7ac6680-f62a-4ff5-a5b3-4892ebac628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191033669 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1191033669
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.47754674
Short name T346
Test name
Test status
Simulation time 256138799 ps
CPU time 1.95 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:51 PM PDT 24
Peak memory 216536 kb
Host smart-68e421c7-ce3c-4a9e-b463-a57e6dcbdc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47754674 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.47754674
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.3658327957
Short name T198
Test name
Test status
Simulation time 49153946028 ps
CPU time 1127.09 seconds
Started Jun 02 02:43:39 PM PDT 24
Finished Jun 02 03:02:27 PM PDT 24
Peak memory 219812 kb
Host smart-b374a766-0130-4550-98be-61bf87f4091e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658327957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.3658327957
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.580682119
Short name T86
Test name
Test status
Simulation time 18739224 ps
CPU time 1.18 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 223704 kb
Host smart-aa3779a7-f31b-4fdd-83c1-8ff3be0e88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580682119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.580682119
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1536761602
Short name T385
Test name
Test status
Simulation time 43452373 ps
CPU time 1.58 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 217676 kb
Host smart-bc85ba4b-bcbb-403a-8343-e0ac2b78f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536761602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1536761602
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1474994388
Short name T709
Test name
Test status
Simulation time 94058162 ps
CPU time 1.02 seconds
Started Jun 02 02:44:59 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 218708 kb
Host smart-a5c3c712-ecb8-4437-a34b-28643f994ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474994388 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1474994388
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.680322296
Short name T113
Test name
Test status
Simulation time 80812571 ps
CPU time 1.15 seconds
Started Jun 02 02:44:43 PM PDT 24
Finished Jun 02 02:44:45 PM PDT 24
Peak memory 216872 kb
Host smart-6c66dd30-9a08-4561-a40b-d02805e0bf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680322296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.680322296
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_genbits.1264364188
Short name T452
Test name
Test status
Simulation time 76657303 ps
CPU time 1.18 seconds
Started Jun 02 02:44:44 PM PDT 24
Finished Jun 02 02:44:46 PM PDT 24
Peak memory 216952 kb
Host smart-3b4e1f66-5e22-414c-a584-d4949809c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264364188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1264364188
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.600955964
Short name T570
Test name
Test status
Simulation time 96004708 ps
CPU time 0.94 seconds
Started Jun 02 02:44:38 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 218260 kb
Host smart-0b598f64-8998-458c-9b0a-d5e8e9d42e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600955964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.600955964
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3734333623
Short name T765
Test name
Test status
Simulation time 72682961 ps
CPU time 1.14 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:44:52 PM PDT 24
Peak memory 216708 kb
Host smart-6fefc344-e7e0-4575-975f-24324babc321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734333623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3734333623
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3169768674
Short name T74
Test name
Test status
Simulation time 20012100 ps
CPU time 1.13 seconds
Started Jun 02 02:44:47 PM PDT 24
Finished Jun 02 02:44:48 PM PDT 24
Peak memory 223436 kb
Host smart-a0894bc5-d0ce-4cbc-a463-da9b9a31205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169768674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3169768674
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.712261733
Short name T340
Test name
Test status
Simulation time 96898596 ps
CPU time 1.6 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:44:52 PM PDT 24
Peak memory 218372 kb
Host smart-8bbef5c3-ecae-46ae-8101-2388f50e3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712261733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.712261733
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.734764141
Short name T678
Test name
Test status
Simulation time 27052212 ps
CPU time 1.17 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:44:52 PM PDT 24
Peak memory 218072 kb
Host smart-6533fb95-d5a9-4c96-a263-1b811db81445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734764141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.734764141
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2760287691
Short name T795
Test name
Test status
Simulation time 53347518 ps
CPU time 1.58 seconds
Started Jun 02 02:44:54 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 217680 kb
Host smart-45b10612-5aab-4524-8871-a13c9c69b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760287691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2760287691
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.4012659361
Short name T360
Test name
Test status
Simulation time 20492168 ps
CPU time 1.1 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 218564 kb
Host smart-6886f02a-9f64-4c00-b042-dfab1f3c5a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012659361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.4012659361
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3338814885
Short name T629
Test name
Test status
Simulation time 226476726 ps
CPU time 1.89 seconds
Started Jun 02 02:44:37 PM PDT 24
Finished Jun 02 02:44:39 PM PDT 24
Peak memory 218600 kb
Host smart-a6fc3b1f-9ce1-4d5e-acaa-b3fc65fbde94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338814885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3338814885
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2404139652
Short name T625
Test name
Test status
Simulation time 29227960 ps
CPU time 0.88 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 217956 kb
Host smart-3eaf7bc3-edaf-4ee8-8ba7-84d7713095de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404139652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2404139652
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2855099958
Short name T279
Test name
Test status
Simulation time 53805783 ps
CPU time 1.47 seconds
Started Jun 02 02:44:56 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 219480 kb
Host smart-0ba41f9f-9a89-457b-ae42-94f27f2607ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855099958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2855099958
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.260255890
Short name T518
Test name
Test status
Simulation time 23136785 ps
CPU time 1.08 seconds
Started Jun 02 02:45:10 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 218016 kb
Host smart-9548e289-4288-45ee-a384-3c7f817d07f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260255890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.260255890
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.301834798
Short name T673
Test name
Test status
Simulation time 62164821 ps
CPU time 2.42 seconds
Started Jun 02 02:44:48 PM PDT 24
Finished Jun 02 02:44:51 PM PDT 24
Peak memory 218156 kb
Host smart-650c9986-8651-4b8f-8600-03e30e577f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301834798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.301834798
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.201627292
Short name T81
Test name
Test status
Simulation time 29393981 ps
CPU time 0.8 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 217864 kb
Host smart-c53b458b-9338-4795-8c41-21b199d2ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201627292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.201627292
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.502614710
Short name T516
Test name
Test status
Simulation time 73051722 ps
CPU time 1.1 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 218940 kb
Host smart-d540dc91-c665-4152-88fb-3f38baef6175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502614710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.502614710
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3558969900
Short name T73
Test name
Test status
Simulation time 55762381 ps
CPU time 1.22 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 215352 kb
Host smart-b0d82235-54d0-429f-8260-0da60ff23720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558969900 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3558969900
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.1930773770
Short name T429
Test name
Test status
Simulation time 31314817 ps
CPU time 0.85 seconds
Started Jun 02 02:44:00 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 214328 kb
Host smart-10123c94-95da-4dc1-a70e-11e52cac4bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930773770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1930773770
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3581188396
Short name T679
Test name
Test status
Simulation time 51175961 ps
CPU time 0.86 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:44:14 PM PDT 24
Peak memory 215656 kb
Host smart-12b7de9d-86ed-4e63-bbdf-602220d78753
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581188396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3581188396
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1762905692
Short name T49
Test name
Test status
Simulation time 66018306 ps
CPU time 1.03 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 02:43:58 PM PDT 24
Peak memory 217944 kb
Host smart-6148c918-5d3a-4500-a10a-ed698aa18aeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762905692 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1762905692
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_genbits.444326976
Short name T127
Test name
Test status
Simulation time 78770730 ps
CPU time 1.16 seconds
Started Jun 02 02:43:58 PM PDT 24
Finished Jun 02 02:44:00 PM PDT 24
Peak memory 216512 kb
Host smart-f3dcd268-49d8-4dc3-acc9-d1f7e570e9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444326976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.444326976
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.255505796
Short name T393
Test name
Test status
Simulation time 21755815 ps
CPU time 1.05 seconds
Started Jun 02 02:44:12 PM PDT 24
Finished Jun 02 02:44:13 PM PDT 24
Peak memory 215328 kb
Host smart-8dbd2ca3-55a4-4ede-850c-c7ce619b70f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255505796 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.255505796
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.570894832
Short name T419
Test name
Test status
Simulation time 14438621 ps
CPU time 1.01 seconds
Started Jun 02 02:43:44 PM PDT 24
Finished Jun 02 02:43:47 PM PDT 24
Peak memory 214984 kb
Host smart-fc31c423-0571-4d6d-ab15-48586300e66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570894832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.570894832
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2530473945
Short name T334
Test name
Test status
Simulation time 48993722 ps
CPU time 1.55 seconds
Started Jun 02 02:43:48 PM PDT 24
Finished Jun 02 02:43:50 PM PDT 24
Peak memory 217688 kb
Host smart-f0501497-52f7-43ed-93f4-5a176a6e7dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530473945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2530473945
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2032414369
Short name T196
Test name
Test status
Simulation time 424891718822 ps
CPU time 1604.26 seconds
Started Jun 02 02:43:56 PM PDT 24
Finished Jun 02 03:10:41 PM PDT 24
Peak memory 224408 kb
Host smart-d63d5ffa-3f45-4927-9649-9b2cd1c5148f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032414369 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2032414369
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.543906419
Short name T14
Test name
Test status
Simulation time 36011420 ps
CPU time 1.01 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 223276 kb
Host smart-c2a25482-35f9-446b-8914-eff946881e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543906419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.543906419
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1540953649
Short name T621
Test name
Test status
Simulation time 74430170 ps
CPU time 1.43 seconds
Started Jun 02 02:44:57 PM PDT 24
Finished Jun 02 02:44:59 PM PDT 24
Peak memory 218200 kb
Host smart-293d5604-e1fe-488a-9407-655c0f978d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540953649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1540953649
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1537042421
Short name T548
Test name
Test status
Simulation time 26619279 ps
CPU time 1.22 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 220432 kb
Host smart-c9b8dcef-6571-4ae9-980b-2d8e142fc224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537042421 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1537042421
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.4189393673
Short name T710
Test name
Test status
Simulation time 68869382 ps
CPU time 1.18 seconds
Started Jun 02 02:44:56 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 218084 kb
Host smart-7ca03c01-cfea-48e9-b67c-1abe6880952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189393673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.4189393673
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1810257111
Short name T37
Test name
Test status
Simulation time 32618530 ps
CPU time 1.13 seconds
Started Jun 02 02:44:50 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 220052 kb
Host smart-a07cd43b-10e4-4254-ae80-050df0e0f8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810257111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1810257111
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.2257796679
Short name T415
Test name
Test status
Simulation time 191216025 ps
CPU time 1.18 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 216744 kb
Host smart-f2894a30-3fc9-43f5-b910-dc1372c81ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257796679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.2257796679
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2722322788
Short name T513
Test name
Test status
Simulation time 28624056 ps
CPU time 0.96 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 217976 kb
Host smart-43187693-51d5-4037-a7a8-e4aa09123ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722322788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2722322788
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1321715747
Short name T838
Test name
Test status
Simulation time 822151494 ps
CPU time 5.98 seconds
Started Jun 02 02:44:59 PM PDT 24
Finished Jun 02 02:45:05 PM PDT 24
Peak memory 216904 kb
Host smart-43b4319d-2198-4d9a-b1f5-fa8dd0ea2800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321715747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1321715747
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1527990525
Short name T175
Test name
Test status
Simulation time 29353409 ps
CPU time 0.85 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 218096 kb
Host smart-c43c54d3-bb70-4db3-8f9d-4f3505276fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527990525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1527990525
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/85.edn_err.3487996636
Short name T6
Test name
Test status
Simulation time 56627774 ps
CPU time 1.1 seconds
Started Jun 02 02:45:15 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 223412 kb
Host smart-280da67a-ade2-45a3-9221-0ac2fd8c34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487996636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3487996636
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3786246476
Short name T270
Test name
Test status
Simulation time 47712175 ps
CPU time 1.52 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:12 PM PDT 24
Peak memory 217824 kb
Host smart-176225ec-09db-4bed-a8d1-9b7d28c5cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786246476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3786246476
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2500146497
Short name T41
Test name
Test status
Simulation time 37153996 ps
CPU time 1.17 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 229196 kb
Host smart-86c9711d-b5c5-482a-a51d-ef1694edea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500146497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2500146497
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2875498344
Short name T803
Test name
Test status
Simulation time 41680606 ps
CPU time 1.11 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 214964 kb
Host smart-ad6c2208-7137-4ee1-b916-f41cd81338f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875498344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2875498344
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2161883759
Short name T64
Test name
Test status
Simulation time 23408645 ps
CPU time 0.92 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 218416 kb
Host smart-b1197183-b592-4168-8504-cd860d0776f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161883759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2161883759
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1863108794
Short name T563
Test name
Test status
Simulation time 110865851 ps
CPU time 1.54 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 218036 kb
Host smart-9be35e65-dd59-49bf-8a63-e77c07f0db8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863108794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1863108794
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2428820470
Short name T573
Test name
Test status
Simulation time 19650462 ps
CPU time 1.01 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 217832 kb
Host smart-a618d9d3-4eea-4613-ac94-1303c6c5e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428820470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2428820470
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.82901847
Short name T494
Test name
Test status
Simulation time 168419362 ps
CPU time 2.96 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 219472 kb
Host smart-124a3319-d4bf-4a07-b3c3-342e2376e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82901847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.82901847
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2108307669
Short name T80
Test name
Test status
Simulation time 18795825 ps
CPU time 1.01 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:53 PM PDT 24
Peak memory 217772 kb
Host smart-d537f6c4-783f-46d3-9110-22f14552f6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108307669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2108307669
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.353278340
Short name T758
Test name
Test status
Simulation time 30205341 ps
CPU time 1.12 seconds
Started Jun 02 02:45:02 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 216852 kb
Host smart-58215638-48a3-483f-8c88-5a31d8cfa235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353278340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.353278340
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4025243240
Short name T248
Test name
Test status
Simulation time 27892323 ps
CPU time 1.3 seconds
Started Jun 02 02:43:59 PM PDT 24
Finished Jun 02 02:44:01 PM PDT 24
Peak memory 215308 kb
Host smart-9b1efaba-e99e-4c86-9d9b-b6741b12b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025243240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4025243240
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3498904681
Short name T487
Test name
Test status
Simulation time 17820523 ps
CPU time 0.93 seconds
Started Jun 02 02:43:47 PM PDT 24
Finished Jun 02 02:43:49 PM PDT 24
Peak memory 206236 kb
Host smart-4da3f860-c39f-47a3-b748-50e2e366fc8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498904681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3498904681
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2414153005
Short name T186
Test name
Test status
Simulation time 16937902 ps
CPU time 0.83 seconds
Started Jun 02 02:43:41 PM PDT 24
Finished Jun 02 02:43:42 PM PDT 24
Peak memory 216000 kb
Host smart-0eabcfd0-3fc1-44db-95e1-03c111c11e29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414153005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2414153005
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.852198329
Short name T169
Test name
Test status
Simulation time 56668293 ps
CPU time 1.03 seconds
Started Jun 02 02:43:36 PM PDT 24
Finished Jun 02 02:43:37 PM PDT 24
Peak memory 216460 kb
Host smart-6ced32c9-b1b8-47ca-b86d-16ca41158d95
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852198329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis
able_auto_req_mode.852198329
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1275145443
Short name T716
Test name
Test status
Simulation time 25002829 ps
CPU time 1.08 seconds
Started Jun 02 02:43:42 PM PDT 24
Finished Jun 02 02:43:44 PM PDT 24
Peak memory 218460 kb
Host smart-e550ca42-3bcc-4bfd-af8e-3006db418a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275145443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1275145443
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3241671418
Short name T520
Test name
Test status
Simulation time 30521688 ps
CPU time 1.32 seconds
Started Jun 02 02:43:43 PM PDT 24
Finished Jun 02 02:43:45 PM PDT 24
Peak memory 216564 kb
Host smart-e77da8de-48d7-4b88-ad5a-3aec17f38d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241671418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3241671418
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3258013009
Short name T403
Test name
Test status
Simulation time 32907296 ps
CPU time 0.89 seconds
Started Jun 02 02:43:51 PM PDT 24
Finished Jun 02 02:43:52 PM PDT 24
Peak memory 215048 kb
Host smart-4103aedc-a9d3-4f38-8d78-c930fad4f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258013009 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3258013009
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.1667270006
Short name T310
Test name
Test status
Simulation time 21270091 ps
CPU time 0.97 seconds
Started Jun 02 02:43:38 PM PDT 24
Finished Jun 02 02:43:40 PM PDT 24
Peak memory 214972 kb
Host smart-4e985f64-12ff-4a15-b32f-dc756c6d2fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667270006 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1667270006
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1874914648
Short name T451
Test name
Test status
Simulation time 880867943 ps
CPU time 3.94 seconds
Started Jun 02 02:43:50 PM PDT 24
Finished Jun 02 02:43:55 PM PDT 24
Peak memory 216692 kb
Host smart-00a9e25b-8261-473d-a791-71866c221a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874914648 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1874914648
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.943111894
Short name T740
Test name
Test status
Simulation time 131234497239 ps
CPU time 935.09 seconds
Started Jun 02 02:43:40 PM PDT 24
Finished Jun 02 02:59:16 PM PDT 24
Peak memory 223300 kb
Host smart-2bfb81de-799f-45ae-827c-99b7502b76e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943111894 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.943111894
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.182349986
Short name T741
Test name
Test status
Simulation time 55107188 ps
CPU time 0.91 seconds
Started Jun 02 02:44:53 PM PDT 24
Finished Jun 02 02:44:55 PM PDT 24
Peak memory 223296 kb
Host smart-f74f410f-63bb-4ae4-b324-433867540425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182349986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.182349986
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.2382980685
Short name T271
Test name
Test status
Simulation time 76010023 ps
CPU time 1.21 seconds
Started Jun 02 02:44:58 PM PDT 24
Finished Jun 02 02:45:00 PM PDT 24
Peak memory 219568 kb
Host smart-5d001cc3-ee27-46b8-adc3-164a09e999fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382980685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.2382980685
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.974927809
Short name T421
Test name
Test status
Simulation time 20842415 ps
CPU time 0.93 seconds
Started Jun 02 02:45:13 PM PDT 24
Finished Jun 02 02:45:17 PM PDT 24
Peak memory 217960 kb
Host smart-8d06e1d7-83f7-4dae-96d6-8ed23c5a3c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974927809 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.974927809
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2532306711
Short name T576
Test name
Test status
Simulation time 46527465 ps
CPU time 1.48 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 216616 kb
Host smart-442e245c-a23a-4f91-ba02-bf9d751ab33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532306711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2532306711
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2351379874
Short name T620
Test name
Test status
Simulation time 27022182 ps
CPU time 0.84 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 217720 kb
Host smart-bd26492f-f26e-4e2d-a9e4-8d477c79de53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351379874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2351379874
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.487039973
Short name T674
Test name
Test status
Simulation time 36993054 ps
CPU time 1.33 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 216728 kb
Host smart-1fb8e4d5-7158-4e5a-a85d-502c986c172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487039973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.487039973
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1432466217
Short name T99
Test name
Test status
Simulation time 21341080 ps
CPU time 1.07 seconds
Started Jun 02 02:45:12 PM PDT 24
Finished Jun 02 02:45:14 PM PDT 24
Peak memory 219308 kb
Host smart-2920b5c9-2a12-4f7f-9466-a56655879811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432466217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1432466217
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2291432168
Short name T331
Test name
Test status
Simulation time 218369482 ps
CPU time 3.06 seconds
Started Jun 02 02:45:11 PM PDT 24
Finished Jun 02 02:45:15 PM PDT 24
Peak memory 219548 kb
Host smart-257501cf-6898-461b-a5a0-e75b6719e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291432168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2291432168
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3147352711
Short name T32
Test name
Test status
Simulation time 50028347 ps
CPU time 1.01 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 220024 kb
Host smart-84ed17d6-e1bc-4296-a690-7e84509268f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147352711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3147352711
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.75879230
Short name T639
Test name
Test status
Simulation time 129307286 ps
CPU time 1.27 seconds
Started Jun 02 02:45:01 PM PDT 24
Finished Jun 02 02:45:03 PM PDT 24
Peak memory 219244 kb
Host smart-c07112a1-3aba-4501-8ac1-77637856c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75879230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.75879230
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2840284094
Short name T100
Test name
Test status
Simulation time 19660503 ps
CPU time 1.12 seconds
Started Jun 02 02:44:59 PM PDT 24
Finished Jun 02 02:45:01 PM PDT 24
Peak memory 219248 kb
Host smart-c9a8f478-ce63-441d-8b0a-b68cb0ae7ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840284094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2840284094
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.171813006
Short name T377
Test name
Test status
Simulation time 172105831 ps
CPU time 1.36 seconds
Started Jun 02 02:44:52 PM PDT 24
Finished Jun 02 02:44:54 PM PDT 24
Peak memory 219036 kb
Host smart-76a1631d-1660-48ad-b1ee-5e7adcfd39ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171813006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.171813006
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3393493329
Short name T782
Test name
Test status
Simulation time 73211763 ps
CPU time 1.1 seconds
Started Jun 02 02:45:07 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 218948 kb
Host smart-90d80969-940a-4cc5-9662-e27bb1d79be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393493329 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3393493329
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2613413687
Short name T286
Test name
Test status
Simulation time 41136120 ps
CPU time 1.57 seconds
Started Jun 02 02:45:06 PM PDT 24
Finished Jun 02 02:45:09 PM PDT 24
Peak memory 217768 kb
Host smart-dff46be7-2267-40ae-8325-2ea2d8b33281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613413687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2613413687
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1156538426
Short name T624
Test name
Test status
Simulation time 25058654 ps
CPU time 1.01 seconds
Started Jun 02 02:45:09 PM PDT 24
Finished Jun 02 02:45:11 PM PDT 24
Peak memory 219484 kb
Host smart-9c821cd5-ab19-4753-969a-7c260367b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156538426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1156538426
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1602179603
Short name T138
Test name
Test status
Simulation time 59386855 ps
CPU time 1.12 seconds
Started Jun 02 02:45:14 PM PDT 24
Finished Jun 02 02:45:18 PM PDT 24
Peak memory 217948 kb
Host smart-219c77a9-35b5-4154-a44b-ad9050112750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602179603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1602179603
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2029285046
Short name T31
Test name
Test status
Simulation time 25747990 ps
CPU time 1.23 seconds
Started Jun 02 02:45:08 PM PDT 24
Finished Jun 02 02:45:10 PM PDT 24
Peak memory 228896 kb
Host smart-adbc99f5-85b0-44a3-b7db-f79ce17467cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029285046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2029285046
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.88049591
Short name T358
Test name
Test status
Simulation time 45595658 ps
CPU time 1.79 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:58 PM PDT 24
Peak memory 217984 kb
Host smart-1c92bc44-1ccf-46ba-82aa-0af0a937a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88049591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.88049591
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3150915057
Short name T686
Test name
Test status
Simulation time 29618384 ps
CPU time 1.38 seconds
Started Jun 02 02:44:55 PM PDT 24
Finished Jun 02 02:44:57 PM PDT 24
Peak memory 224132 kb
Host smart-d6481c47-bad8-44f5-97eb-84e6f43dbe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150915057 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3150915057
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.981205136
Short name T577
Test name
Test status
Simulation time 114350130 ps
CPU time 1.32 seconds
Started Jun 02 02:45:05 PM PDT 24
Finished Jun 02 02:45:07 PM PDT 24
Peak memory 218248 kb
Host smart-fa9557aa-7702-4658-9cb1-91660d149852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981205136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.981205136
Directory /workspace/99.edn_genbits/latest
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