Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7673

1

T4

36

T103

25

T104

132

all_values[1]

7673

1

T4

36

T103

25

T104

132

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7844

1

T4

30

T103

29

T104

145

auto[1]

7502

1

T4

42

T103

21

T104

119

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5935

1

T4

22

T103

18

T104

102

auto[1]

9411

1

T4

50

T103

32

T104

162

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9043

1

T4

42

T103

29

T104

154

auto[1]

6303

1

T4

30

T103

21

T104

110

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1585

1

T4

4

T103

4

T104

37

all_values[0]

auto[0]

auto[0]

auto[1]

739

1

T4

5

T103

5

T104

10

all_values[0]

auto[0]

auto[1]

auto[0]

1417

1

T4

7

T103

4

T104

22

all_values[0]

auto[0]

auto[1]

auto[1]

783

1

T4

6

T103

2

T104

12

all_values[0]

auto[1]

auto[0]

auto[1]

1644

1

T4

9

T103

8

T104

32

all_values[0]

auto[1]

auto[1]

auto[1]

1505

1

T4

5

T103

2

T104

19

all_values[1]

auto[0]

auto[0]

auto[0]

1488

1

T4

5

T103

6

T104

19

all_values[1]

auto[0]

auto[0]

auto[1]

765

1

T4

3

T103

3

T104

16

all_values[1]

auto[0]

auto[1]

auto[0]

1445

1

T4

6

T103

4

T104

24

all_values[1]

auto[0]

auto[1]

auto[1]

821

1

T4

6

T103

1

T104

14

all_values[1]

auto[1]

auto[0]

auto[1]

1623

1

T4

4

T103

3

T104

31

all_values[1]

auto[1]

auto[1]

auto[1]

1531

1

T4

12

T103

8

T104

28

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal