Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.53 98.24 93.80 97.07 84.88 96.62 99.77 91.31


Total test records in report: 980
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T788 /workspace/coverage/default/250.edn_genbits.2197051604 Jun 04 01:45:38 PM PDT 24 Jun 04 01:45:41 PM PDT 24 33426483 ps
T789 /workspace/coverage/default/113.edn_genbits.874355299 Jun 04 01:45:20 PM PDT 24 Jun 04 01:45:23 PM PDT 24 196786915 ps
T790 /workspace/coverage/default/22.edn_smoke.2179160145 Jun 04 01:44:26 PM PDT 24 Jun 04 01:44:28 PM PDT 24 43084881 ps
T164 /workspace/coverage/default/2.edn_intr.1872323257 Jun 04 01:43:43 PM PDT 24 Jun 04 01:43:45 PM PDT 24 21064081 ps
T791 /workspace/coverage/default/65.edn_genbits.3063553907 Jun 04 01:45:10 PM PDT 24 Jun 04 01:45:13 PM PDT 24 93059013 ps
T284 /workspace/coverage/default/60.edn_genbits.356531663 Jun 04 01:45:05 PM PDT 24 Jun 04 01:45:10 PM PDT 24 69446067 ps
T792 /workspace/coverage/default/198.edn_genbits.2788017578 Jun 04 01:45:34 PM PDT 24 Jun 04 01:45:38 PM PDT 24 47794228 ps
T793 /workspace/coverage/default/26.edn_disable_auto_req_mode.4123134472 Jun 04 01:44:28 PM PDT 24 Jun 04 01:44:31 PM PDT 24 38323405 ps
T794 /workspace/coverage/default/25.edn_alert.3316242948 Jun 04 01:44:28 PM PDT 24 Jun 04 01:44:31 PM PDT 24 75945411 ps
T795 /workspace/coverage/default/44.edn_smoke.3237843917 Jun 04 01:45:00 PM PDT 24 Jun 04 01:45:04 PM PDT 24 48581765 ps
T796 /workspace/coverage/default/243.edn_genbits.2204661115 Jun 04 01:45:37 PM PDT 24 Jun 04 01:45:40 PM PDT 24 92728824 ps
T797 /workspace/coverage/default/30.edn_smoke.1222788383 Jun 04 01:44:37 PM PDT 24 Jun 04 01:44:40 PM PDT 24 64363498 ps
T798 /workspace/coverage/default/219.edn_genbits.3689710665 Jun 04 01:45:35 PM PDT 24 Jun 04 01:45:38 PM PDT 24 55551138 ps
T799 /workspace/coverage/default/48.edn_disable_auto_req_mode.1353367016 Jun 04 01:45:12 PM PDT 24 Jun 04 01:45:16 PM PDT 24 78919991 ps
T800 /workspace/coverage/default/16.edn_err.202269820 Jun 04 01:44:20 PM PDT 24 Jun 04 01:44:24 PM PDT 24 19787859 ps
T801 /workspace/coverage/default/48.edn_alert.3449555343 Jun 04 01:45:02 PM PDT 24 Jun 04 01:45:07 PM PDT 24 229650722 ps
T802 /workspace/coverage/default/95.edn_genbits.3211240520 Jun 04 01:45:26 PM PDT 24 Jun 04 01:45:30 PM PDT 24 67928900 ps
T803 /workspace/coverage/default/187.edn_genbits.3612455005 Jun 04 01:45:29 PM PDT 24 Jun 04 01:45:32 PM PDT 24 54577536 ps
T804 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.390146586 Jun 04 01:44:41 PM PDT 24 Jun 04 01:57:12 PM PDT 24 40769240690 ps
T805 /workspace/coverage/default/294.edn_genbits.2139639786 Jun 04 01:45:53 PM PDT 24 Jun 04 01:46:00 PM PDT 24 751550860 ps
T806 /workspace/coverage/default/28.edn_disable.4156909208 Jun 04 01:44:37 PM PDT 24 Jun 04 01:44:40 PM PDT 24 11433429 ps
T807 /workspace/coverage/default/3.edn_err.2730722237 Jun 04 01:43:45 PM PDT 24 Jun 04 01:43:48 PM PDT 24 46410167 ps
T808 /workspace/coverage/default/50.edn_err.3897346952 Jun 04 01:45:12 PM PDT 24 Jun 04 01:45:16 PM PDT 24 25885770 ps
T809 /workspace/coverage/default/194.edn_genbits.2259522253 Jun 04 01:45:29 PM PDT 24 Jun 04 01:45:33 PM PDT 24 33655114 ps
T810 /workspace/coverage/default/12.edn_err.1962324432 Jun 04 01:44:08 PM PDT 24 Jun 04 01:44:10 PM PDT 24 24184332 ps
T811 /workspace/coverage/default/8.edn_stress_all.3861583964 Jun 04 01:44:04 PM PDT 24 Jun 04 01:44:09 PM PDT 24 171793243 ps
T812 /workspace/coverage/default/7.edn_smoke.139238687 Jun 04 01:43:51 PM PDT 24 Jun 04 01:43:53 PM PDT 24 25727288 ps
T813 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3429577030 Jun 04 01:44:47 PM PDT 24 Jun 04 01:48:02 PM PDT 24 16729725110 ps
T814 /workspace/coverage/default/289.edn_genbits.1296048337 Jun 04 01:45:44 PM PDT 24 Jun 04 01:45:46 PM PDT 24 56270781 ps
T815 /workspace/coverage/default/145.edn_genbits.2213642913 Jun 04 01:45:34 PM PDT 24 Jun 04 01:45:37 PM PDT 24 70018955 ps
T816 /workspace/coverage/default/2.edn_disable_auto_req_mode.581231672 Jun 04 01:43:43 PM PDT 24 Jun 04 01:43:45 PM PDT 24 124208390 ps
T817 /workspace/coverage/default/17.edn_disable.902931953 Jun 04 01:44:22 PM PDT 24 Jun 04 01:44:25 PM PDT 24 18736817 ps
T818 /workspace/coverage/default/8.edn_alert_test.3387923401 Jun 04 01:44:01 PM PDT 24 Jun 04 01:44:03 PM PDT 24 47364447 ps
T819 /workspace/coverage/default/213.edn_genbits.571771931 Jun 04 01:45:36 PM PDT 24 Jun 04 01:45:40 PM PDT 24 35741191 ps
T820 /workspace/coverage/default/1.edn_genbits.688511789 Jun 04 01:43:36 PM PDT 24 Jun 04 01:43:39 PM PDT 24 79177348 ps
T61 /workspace/coverage/default/79.edn_err.2023981071 Jun 04 01:45:13 PM PDT 24 Jun 04 01:45:17 PM PDT 24 32619329 ps
T263 /workspace/coverage/default/46.edn_alert.534761906 Jun 04 01:44:54 PM PDT 24 Jun 04 01:44:56 PM PDT 24 45307465 ps
T821 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3755846314 Jun 04 01:44:27 PM PDT 24 Jun 04 01:50:50 PM PDT 24 85689015679 ps
T822 /workspace/coverage/default/47.edn_alert_test.728296310 Jun 04 01:45:02 PM PDT 24 Jun 04 01:45:07 PM PDT 24 19992278 ps
T282 /workspace/coverage/default/163.edn_genbits.95944345 Jun 04 01:45:31 PM PDT 24 Jun 04 01:45:35 PM PDT 24 46088238 ps
T823 /workspace/coverage/default/27.edn_smoke.2363112749 Jun 04 01:44:31 PM PDT 24 Jun 04 01:44:34 PM PDT 24 20363502 ps
T824 /workspace/coverage/default/215.edn_genbits.3473220734 Jun 04 01:45:35 PM PDT 24 Jun 04 01:45:38 PM PDT 24 39050483 ps
T825 /workspace/coverage/default/128.edn_genbits.1516589696 Jun 04 01:45:26 PM PDT 24 Jun 04 01:45:30 PM PDT 24 46468670 ps
T826 /workspace/coverage/default/22.edn_intr.3655081701 Jun 04 01:44:31 PM PDT 24 Jun 04 01:44:34 PM PDT 24 46790143 ps
T827 /workspace/coverage/default/58.edn_err.2641008482 Jun 04 01:45:03 PM PDT 24 Jun 04 01:45:08 PM PDT 24 18572731 ps
T828 /workspace/coverage/default/45.edn_disable_auto_req_mode.2060524098 Jun 04 01:44:59 PM PDT 24 Jun 04 01:45:04 PM PDT 24 164490457 ps
T829 /workspace/coverage/default/42.edn_disable_auto_req_mode.206446893 Jun 04 01:44:49 PM PDT 24 Jun 04 01:44:52 PM PDT 24 156869004 ps
T830 /workspace/coverage/default/43.edn_alert.2540925202 Jun 04 01:44:49 PM PDT 24 Jun 04 01:44:52 PM PDT 24 51960386 ps
T831 /workspace/coverage/default/10.edn_alert_test.2296598609 Jun 04 01:44:09 PM PDT 24 Jun 04 01:44:11 PM PDT 24 18367607 ps
T832 /workspace/coverage/default/56.edn_genbits.3751156674 Jun 04 01:45:04 PM PDT 24 Jun 04 01:45:10 PM PDT 24 92026844 ps
T833 /workspace/coverage/default/43.edn_alert_test.2211556911 Jun 04 01:44:57 PM PDT 24 Jun 04 01:45:00 PM PDT 24 17637450 ps
T269 /workspace/coverage/default/18.edn_alert.1550764675 Jun 04 01:44:21 PM PDT 24 Jun 04 01:44:25 PM PDT 24 35176230 ps
T834 /workspace/coverage/default/31.edn_alert.1532493674 Jun 04 01:44:35 PM PDT 24 Jun 04 01:44:39 PM PDT 24 32199892 ps
T835 /workspace/coverage/default/22.edn_alert.910489493 Jun 04 01:44:28 PM PDT 24 Jun 04 01:44:31 PM PDT 24 46504389 ps
T836 /workspace/coverage/default/41.edn_err.1466786177 Jun 04 01:44:55 PM PDT 24 Jun 04 01:44:57 PM PDT 24 24948862 ps
T837 /workspace/coverage/default/12.edn_intr.1589417002 Jun 04 01:44:09 PM PDT 24 Jun 04 01:44:11 PM PDT 24 22203364 ps
T838 /workspace/coverage/default/8.edn_disable.2597861794 Jun 04 01:43:59 PM PDT 24 Jun 04 01:44:02 PM PDT 24 28072901 ps
T839 /workspace/coverage/default/44.edn_alert.3464809147 Jun 04 01:44:58 PM PDT 24 Jun 04 01:45:01 PM PDT 24 37825417 ps
T840 /workspace/coverage/default/281.edn_genbits.1443062658 Jun 04 01:45:50 PM PDT 24 Jun 04 01:45:52 PM PDT 24 42387833 ps
T285 /workspace/coverage/default/103.edn_genbits.2928298259 Jun 04 01:45:29 PM PDT 24 Jun 04 01:45:34 PM PDT 24 93613212 ps
T841 /workspace/coverage/default/25.edn_intr.907120565 Jun 04 01:44:31 PM PDT 24 Jun 04 01:44:34 PM PDT 24 21270905 ps
T842 /workspace/coverage/default/43.edn_stress_all.1837642993 Jun 04 01:44:50 PM PDT 24 Jun 04 01:44:55 PM PDT 24 603368584 ps
T843 /workspace/coverage/default/81.edn_genbits.3186331437 Jun 04 01:45:22 PM PDT 24 Jun 04 01:45:26 PM PDT 24 221657356 ps
T844 /workspace/coverage/default/211.edn_genbits.2949168306 Jun 04 01:45:25 PM PDT 24 Jun 04 01:45:28 PM PDT 24 20876818 ps
T845 /workspace/coverage/default/24.edn_alert.717119165 Jun 04 01:44:30 PM PDT 24 Jun 04 01:44:33 PM PDT 24 63221096 ps
T846 /workspace/coverage/cover_reg_top/4.edn_intr_test.2676965076 Jun 04 12:55:47 PM PDT 24 Jun 04 12:55:49 PM PDT 24 31072987 ps
T847 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3722997970 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:10 PM PDT 24 345851748 ps
T216 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1869603070 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:05 PM PDT 24 25629606 ps
T237 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1525948414 Jun 04 12:55:59 PM PDT 24 Jun 04 12:56:01 PM PDT 24 33037191 ps
T848 /workspace/coverage/cover_reg_top/13.edn_tl_errors.779961017 Jun 04 12:55:43 PM PDT 24 Jun 04 12:55:46 PM PDT 24 77098046 ps
T849 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1771010037 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:06 PM PDT 24 235498241 ps
T850 /workspace/coverage/cover_reg_top/3.edn_intr_test.1664960211 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 25092259 ps
T851 /workspace/coverage/cover_reg_top/14.edn_intr_test.1886171239 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:58 PM PDT 24 130565612 ps
T852 /workspace/coverage/cover_reg_top/37.edn_intr_test.1742517503 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:07 PM PDT 24 11971573 ps
T853 /workspace/coverage/cover_reg_top/7.edn_intr_test.2578029873 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 16373163 ps
T854 /workspace/coverage/cover_reg_top/27.edn_intr_test.1620200579 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 27312165 ps
T855 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1051336214 Jun 04 12:55:55 PM PDT 24 Jun 04 12:55:57 PM PDT 24 24398613 ps
T856 /workspace/coverage/cover_reg_top/22.edn_intr_test.2105593740 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 14084342 ps
T857 /workspace/coverage/cover_reg_top/30.edn_intr_test.2957797642 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:08 PM PDT 24 43299738 ps
T858 /workspace/coverage/cover_reg_top/44.edn_intr_test.3979590558 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 16332547 ps
T217 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1736089050 Jun 04 12:55:59 PM PDT 24 Jun 04 12:56:01 PM PDT 24 14419627 ps
T859 /workspace/coverage/cover_reg_top/20.edn_intr_test.3229739499 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 11737804 ps
T860 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2876324217 Jun 04 12:55:52 PM PDT 24 Jun 04 12:55:55 PM PDT 24 191024801 ps
T218 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2554161658 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:39 PM PDT 24 66271510 ps
T861 /workspace/coverage/cover_reg_top/46.edn_intr_test.3121313916 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 45490625 ps
T239 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1743735418 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:07 PM PDT 24 206002773 ps
T219 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2804734368 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:08 PM PDT 24 11960121 ps
T862 /workspace/coverage/cover_reg_top/34.edn_intr_test.213060683 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 93526091 ps
T863 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2664696599 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:05 PM PDT 24 31711381 ps
T864 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1690577332 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:40 PM PDT 24 73504524 ps
T865 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2131108141 Jun 04 12:55:32 PM PDT 24 Jun 04 12:55:34 PM PDT 24 134074767 ps
T866 /workspace/coverage/cover_reg_top/11.edn_intr_test.4170144827 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 13789583 ps
T867 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3840120393 Jun 04 12:55:33 PM PDT 24 Jun 04 12:55:35 PM PDT 24 32209590 ps
T868 /workspace/coverage/cover_reg_top/8.edn_intr_test.2268333405 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 21630143 ps
T240 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.344297585 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:09 PM PDT 24 93755406 ps
T869 /workspace/coverage/cover_reg_top/2.edn_intr_test.3561787650 Jun 04 12:55:32 PM PDT 24 Jun 04 12:55:43 PM PDT 24 21559327 ps
T870 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.909109475 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:40 PM PDT 24 77119220 ps
T871 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3961986713 Jun 04 12:56:13 PM PDT 24 Jun 04 12:56:16 PM PDT 24 53695299 ps
T231 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3971767763 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:55 PM PDT 24 64450124 ps
T220 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2956793045 Jun 04 12:55:51 PM PDT 24 Jun 04 12:55:58 PM PDT 24 254273865 ps
T238 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.402431602 Jun 04 12:55:41 PM PDT 24 Jun 04 12:55:43 PM PDT 24 26004108 ps
T241 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1983526250 Jun 04 12:55:47 PM PDT 24 Jun 04 12:55:50 PM PDT 24 644128718 ps
T232 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2786192256 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:39 PM PDT 24 38169827 ps
T872 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3128373859 Jun 04 12:56:12 PM PDT 24 Jun 04 12:56:15 PM PDT 24 35722066 ps
T221 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3021620951 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:38 PM PDT 24 206002421 ps
T873 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2369219554 Jun 04 12:55:58 PM PDT 24 Jun 04 12:56:03 PM PDT 24 102972270 ps
T874 /workspace/coverage/cover_reg_top/17.edn_intr_test.854546094 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:04 PM PDT 24 131425444 ps
T875 /workspace/coverage/cover_reg_top/43.edn_intr_test.2603149191 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:58 PM PDT 24 20118133 ps
T222 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2765571493 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:52 PM PDT 24 63662250 ps
T876 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3347261830 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:36 PM PDT 24 76878808 ps
T877 /workspace/coverage/cover_reg_top/33.edn_intr_test.1719907490 Jun 04 12:56:00 PM PDT 24 Jun 04 12:56:01 PM PDT 24 24367916 ps
T246 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.547213678 Jun 04 12:55:52 PM PDT 24 Jun 04 12:55:56 PM PDT 24 156743258 ps
T878 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3763706553 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 18937524 ps
T879 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.924531734 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:57 PM PDT 24 356351069 ps
T880 /workspace/coverage/cover_reg_top/16.edn_intr_test.813631024 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 37350204 ps
T223 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4201348425 Jun 04 12:56:06 PM PDT 24 Jun 04 12:56:08 PM PDT 24 23243597 ps
T881 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.948829094 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:08 PM PDT 24 27649914 ps
T233 /workspace/coverage/cover_reg_top/2.edn_csr_rw.786034801 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:55 PM PDT 24 28225182 ps
T882 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1687283143 Jun 04 12:55:55 PM PDT 24 Jun 04 12:55:57 PM PDT 24 29213483 ps
T247 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4277557875 Jun 04 12:56:00 PM PDT 24 Jun 04 12:56:02 PM PDT 24 129098269 ps
T883 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1857692302 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:59 PM PDT 24 78393528 ps
T245 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2568434695 Jun 04 12:55:54 PM PDT 24 Jun 04 12:55:57 PM PDT 24 399424468 ps
T884 /workspace/coverage/cover_reg_top/39.edn_intr_test.538849671 Jun 04 12:55:55 PM PDT 24 Jun 04 12:55:56 PM PDT 24 10620152 ps
T224 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2343319958 Jun 04 12:55:58 PM PDT 24 Jun 04 12:56:00 PM PDT 24 109392163 ps
T885 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3992851389 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:58 PM PDT 24 113663023 ps
T886 /workspace/coverage/cover_reg_top/15.edn_intr_test.943317468 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:05 PM PDT 24 25505394 ps
T887 /workspace/coverage/cover_reg_top/48.edn_intr_test.2580991132 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 11028169 ps
T888 /workspace/coverage/cover_reg_top/25.edn_intr_test.3951443410 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 22742342 ps
T889 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.957372228 Jun 04 12:55:33 PM PDT 24 Jun 04 12:55:34 PM PDT 24 18355930 ps
T890 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1315661636 Jun 04 12:55:52 PM PDT 24 Jun 04 12:55:55 PM PDT 24 171492659 ps
T234 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3532187342 Jun 04 12:55:58 PM PDT 24 Jun 04 12:56:00 PM PDT 24 25335199 ps
T891 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3561276809 Jun 04 12:55:58 PM PDT 24 Jun 04 12:56:01 PM PDT 24 72560600 ps
T892 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4263821858 Jun 04 12:55:46 PM PDT 24 Jun 04 12:55:48 PM PDT 24 19208139 ps
T225 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4241613471 Jun 04 12:55:50 PM PDT 24 Jun 04 12:55:53 PM PDT 24 112029487 ps
T893 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1235379513 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:04 PM PDT 24 273081214 ps
T226 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3814683564 Jun 04 12:55:58 PM PDT 24 Jun 04 12:55:59 PM PDT 24 15432255 ps
T894 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.804051740 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:51 PM PDT 24 99622788 ps
T895 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3226699041 Jun 04 12:55:45 PM PDT 24 Jun 04 12:55:47 PM PDT 24 106660379 ps
T896 /workspace/coverage/cover_reg_top/18.edn_intr_test.1540420402 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 21089681 ps
T897 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.46226790 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:52 PM PDT 24 30708049 ps
T227 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3144722188 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 14088314 ps
T228 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2631810094 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:36 PM PDT 24 30277903 ps
T898 /workspace/coverage/cover_reg_top/38.edn_intr_test.25770785 Jun 04 12:56:00 PM PDT 24 Jun 04 12:56:02 PM PDT 24 13441250 ps
T899 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1402670981 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:36 PM PDT 24 25091204 ps
T900 /workspace/coverage/cover_reg_top/40.edn_intr_test.342522489 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 20114682 ps
T901 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3673686724 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:05 PM PDT 24 101683611 ps
T902 /workspace/coverage/cover_reg_top/31.edn_intr_test.2398543082 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:04 PM PDT 24 37888059 ps
T903 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4129121986 Jun 04 12:55:51 PM PDT 24 Jun 04 12:55:54 PM PDT 24 190190926 ps
T904 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2467203864 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 43484835 ps
T905 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3354372688 Jun 04 12:55:31 PM PDT 24 Jun 04 12:55:34 PM PDT 24 163257768 ps
T906 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2365816314 Jun 04 12:55:54 PM PDT 24 Jun 04 12:55:56 PM PDT 24 96352491 ps
T235 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.841859524 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 12902186 ps
T248 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1993683680 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:06 PM PDT 24 302008857 ps
T907 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2141048244 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:05 PM PDT 24 20551503 ps
T908 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1985490790 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 20065576 ps
T909 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.31826182 Jun 04 12:55:35 PM PDT 24 Jun 04 12:55:37 PM PDT 24 43247711 ps
T910 /workspace/coverage/cover_reg_top/36.edn_intr_test.10604905 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 13234622 ps
T911 /workspace/coverage/cover_reg_top/10.edn_csr_rw.67419575 Jun 04 12:55:50 PM PDT 24 Jun 04 12:55:52 PM PDT 24 15099174 ps
T912 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2597346481 Jun 04 12:56:06 PM PDT 24 Jun 04 12:56:09 PM PDT 24 95701213 ps
T913 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3026852627 Jun 04 12:55:45 PM PDT 24 Jun 04 12:55:47 PM PDT 24 23503614 ps
T914 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2036183863 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:56 PM PDT 24 131154908 ps
T915 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1515886422 Jun 04 12:55:48 PM PDT 24 Jun 04 12:55:51 PM PDT 24 65996969 ps
T916 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2182331411 Jun 04 12:55:48 PM PDT 24 Jun 04 12:55:49 PM PDT 24 29055677 ps
T917 /workspace/coverage/cover_reg_top/8.edn_csr_rw.799351417 Jun 04 12:55:51 PM PDT 24 Jun 04 12:55:53 PM PDT 24 23625847 ps
T918 /workspace/coverage/cover_reg_top/12.edn_intr_test.3948809333 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 37344611 ps
T919 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4221556621 Jun 04 12:55:48 PM PDT 24 Jun 04 12:55:49 PM PDT 24 46170551 ps
T920 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1184146883 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:38 PM PDT 24 37490076 ps
T921 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3487081671 Jun 04 12:55:46 PM PDT 24 Jun 04 12:55:48 PM PDT 24 12659303 ps
T922 /workspace/coverage/cover_reg_top/19.edn_intr_test.2074761574 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:55 PM PDT 24 21823889 ps
T923 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1478732120 Jun 04 12:55:44 PM PDT 24 Jun 04 12:55:47 PM PDT 24 48064771 ps
T924 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1222924205 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:38 PM PDT 24 84323346 ps
T925 /workspace/coverage/cover_reg_top/29.edn_intr_test.2491786852 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 14792833 ps
T926 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2667098501 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 23834010 ps
T927 /workspace/coverage/cover_reg_top/23.edn_intr_test.88475677 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 28546424 ps
T928 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3446654280 Jun 04 12:55:38 PM PDT 24 Jun 04 12:55:39 PM PDT 24 41631130 ps
T929 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3856567947 Jun 04 12:55:44 PM PDT 24 Jun 04 12:55:46 PM PDT 24 19792829 ps
T930 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2217743002 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:56 PM PDT 24 44163115 ps
T931 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2313420184 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 196875872 ps
T932 /workspace/coverage/cover_reg_top/10.edn_intr_test.1439868989 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 23775727 ps
T933 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3111925201 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:40 PM PDT 24 38281230 ps
T249 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3259166067 Jun 04 12:55:50 PM PDT 24 Jun 04 12:55:54 PM PDT 24 256908401 ps
T934 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2378712781 Jun 04 12:55:35 PM PDT 24 Jun 04 12:55:37 PM PDT 24 35202404 ps
T935 /workspace/coverage/cover_reg_top/1.edn_intr_test.479438133 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:51 PM PDT 24 17101170 ps
T936 /workspace/coverage/cover_reg_top/19.edn_tl_errors.2644412125 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:08 PM PDT 24 213572830 ps
T937 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3252873270 Jun 04 12:55:29 PM PDT 24 Jun 04 12:55:32 PM PDT 24 61755813 ps
T938 /workspace/coverage/cover_reg_top/49.edn_intr_test.591568377 Jun 04 12:56:36 PM PDT 24 Jun 04 12:56:37 PM PDT 24 23464045 ps
T939 /workspace/coverage/cover_reg_top/15.edn_csr_rw.326269156 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:08 PM PDT 24 14236706 ps
T230 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1836577741 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:42 PM PDT 24 719093179 ps
T940 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1182798195 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:57 PM PDT 24 28926181 ps
T941 /workspace/coverage/cover_reg_top/8.edn_tl_errors.873222481 Jun 04 12:55:39 PM PDT 24 Jun 04 12:55:42 PM PDT 24 46415562 ps
T942 /workspace/coverage/cover_reg_top/41.edn_intr_test.2427422728 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 13526675 ps
T943 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3787537332 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:36 PM PDT 24 19544327 ps
T944 /workspace/coverage/cover_reg_top/5.edn_tl_errors.169257723 Jun 04 12:55:39 PM PDT 24 Jun 04 12:55:41 PM PDT 24 91657813 ps
T945 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.590149702 Jun 04 12:55:41 PM PDT 24 Jun 04 12:55:43 PM PDT 24 14415640 ps
T946 /workspace/coverage/cover_reg_top/0.edn_intr_test.4073162487 Jun 04 12:55:52 PM PDT 24 Jun 04 12:55:54 PM PDT 24 41996249 ps
T947 /workspace/coverage/cover_reg_top/4.edn_tl_errors.4147311102 Jun 04 12:55:36 PM PDT 24 Jun 04 12:55:41 PM PDT 24 55612206 ps
T948 /workspace/coverage/cover_reg_top/47.edn_intr_test.3471778316 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:04 PM PDT 24 42464103 ps
T949 /workspace/coverage/cover_reg_top/9.edn_intr_test.4027485153 Jun 04 12:55:42 PM PDT 24 Jun 04 12:55:43 PM PDT 24 15819462 ps
T950 /workspace/coverage/cover_reg_top/35.edn_intr_test.920996862 Jun 04 12:56:06 PM PDT 24 Jun 04 12:56:08 PM PDT 24 54060721 ps
T229 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1572198961 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:39 PM PDT 24 38880989 ps
T951 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3586222059 Jun 04 12:55:33 PM PDT 24 Jun 04 12:55:36 PM PDT 24 32566727 ps
T952 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2324364660 Jun 04 12:56:09 PM PDT 24 Jun 04 12:56:10 PM PDT 24 16399248 ps
T953 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2481663445 Jun 04 12:55:50 PM PDT 24 Jun 04 12:55:53 PM PDT 24 48312615 ps
T954 /workspace/coverage/cover_reg_top/24.edn_intr_test.830248642 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:03 PM PDT 24 22493065 ps
T955 /workspace/coverage/cover_reg_top/42.edn_intr_test.3207185378 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:06 PM PDT 24 14540759 ps
T956 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1732757484 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:52 PM PDT 24 42174159 ps
T957 /workspace/coverage/cover_reg_top/28.edn_intr_test.1376985651 Jun 04 12:56:06 PM PDT 24 Jun 04 12:56:08 PM PDT 24 46694751 ps
T958 /workspace/coverage/cover_reg_top/13.edn_intr_test.2787314503 Jun 04 12:55:50 PM PDT 24 Jun 04 12:55:52 PM PDT 24 26618942 ps
T959 /workspace/coverage/cover_reg_top/21.edn_intr_test.4029008313 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:58 PM PDT 24 22168458 ps
T960 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1039967370 Jun 04 12:56:01 PM PDT 24 Jun 04 12:56:04 PM PDT 24 240862950 ps
T961 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4052046749 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 14418939 ps
T962 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3058424928 Jun 04 12:55:51 PM PDT 24 Jun 04 12:55:55 PM PDT 24 151930354 ps
T963 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2071996136 Jun 04 12:56:05 PM PDT 24 Jun 04 12:56:08 PM PDT 24 228114366 ps
T964 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.280064757 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:09 PM PDT 24 106435815 ps
T965 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3024171019 Jun 04 12:55:49 PM PDT 24 Jun 04 12:55:53 PM PDT 24 165366121 ps
T966 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1113506979 Jun 04 12:55:29 PM PDT 24 Jun 04 12:55:32 PM PDT 24 869237534 ps
T967 /workspace/coverage/cover_reg_top/13.edn_csr_rw.1888812505 Jun 04 12:55:57 PM PDT 24 Jun 04 12:55:59 PM PDT 24 11447960 ps
T968 /workspace/coverage/cover_reg_top/32.edn_intr_test.3007511889 Jun 04 12:56:02 PM PDT 24 Jun 04 12:56:04 PM PDT 24 10800743 ps
T969 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1720683485 Jun 04 12:55:34 PM PDT 24 Jun 04 12:55:36 PM PDT 24 13865547 ps
T970 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1132197263 Jun 04 12:55:48 PM PDT 24 Jun 04 12:55:50 PM PDT 24 62358434 ps
T971 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1431248162 Jun 04 12:55:55 PM PDT 24 Jun 04 12:55:57 PM PDT 24 52657656 ps
T972 /workspace/coverage/cover_reg_top/45.edn_intr_test.757257038 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:05 PM PDT 24 37554821 ps
T973 /workspace/coverage/cover_reg_top/6.edn_intr_test.3659196751 Jun 04 12:55:53 PM PDT 24 Jun 04 12:55:55 PM PDT 24 34223516 ps
T974 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.955141148 Jun 04 12:55:56 PM PDT 24 Jun 04 12:55:58 PM PDT 24 26459311 ps
T975 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.656302899 Jun 04 12:55:38 PM PDT 24 Jun 04 12:55:40 PM PDT 24 101303510 ps
T976 /workspace/coverage/cover_reg_top/26.edn_intr_test.3922352454 Jun 04 12:56:04 PM PDT 24 Jun 04 12:56:07 PM PDT 24 14878598 ps
T977 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1058482384 Jun 04 12:55:37 PM PDT 24 Jun 04 12:55:39 PM PDT 24 48233640 ps
T978 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1619407080 Jun 04 12:56:03 PM PDT 24 Jun 04 12:56:06 PM PDT 24 28422589 ps
T979 /workspace/coverage/cover_reg_top/5.edn_intr_test.2175630375 Jun 04 12:55:35 PM PDT 24 Jun 04 12:55:39 PM PDT 24 15590778 ps
T980 /workspace/coverage/cover_reg_top/17.edn_csr_rw.380062508 Jun 04 12:56:00 PM PDT 24 Jun 04 12:56:02 PM PDT 24 17146600 ps

Test location /workspace/coverage/default/259.edn_genbits.391008858
Short name T20
Test name
Test status
Simulation time 57212721 ps
CPU time 1.92 seconds
Started Jun 04 01:45:46 PM PDT 24
Finished Jun 04 01:45:49 PM PDT 24
Peak memory 216888 kb
Host smart-6f745c3d-22b6-4e31-ae84-d41359a79cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391008858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.391008858
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_err.1756127343
Short name T6
Test name
Test status
Simulation time 37100215 ps
CPU time 1.04 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 229152 kb
Host smart-ca76ce34-ba51-41e3-acf3-44674e581e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756127343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1756127343
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2910648505
Short name T104
Test name
Test status
Simulation time 38111645177 ps
CPU time 841.7 seconds
Started Jun 04 01:43:39 PM PDT 24
Finished Jun 04 01:57:41 PM PDT 24
Peak memory 218576 kb
Host smart-c3d77d97-5189-414a-ace6-f3c59f791339
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910648505 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2910648505
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2564928247
Short name T16
Test name
Test status
Simulation time 1974852534 ps
CPU time 7.97 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:44:00 PM PDT 24
Peak memory 235796 kb
Host smart-87deb477-bd55-4fda-84cc-929a1b456354
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564928247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2564928247
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/167.edn_genbits.3374028690
Short name T8
Test name
Test status
Simulation time 43485604 ps
CPU time 1.23 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:23 PM PDT 24
Peak memory 219356 kb
Host smart-1846e478-d813-4f10-a108-28408a52079f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374028690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3374028690
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2866340145
Short name T26
Test name
Test status
Simulation time 77991913 ps
CPU time 1.15 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:29 PM PDT 24
Peak memory 215388 kb
Host smart-bcf46228-65d9-46cf-807c-ad5c44b67ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866340145 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2866340145
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/34.edn_stress_all.2570625479
Short name T4
Test name
Test status
Simulation time 244296445 ps
CPU time 4.92 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 215020 kb
Host smart-aa8811c5-9c7f-426b-b281-f1f2f812f4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570625479 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2570625479
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_alert.3267696894
Short name T270
Test name
Test status
Simulation time 124742658 ps
CPU time 1.23 seconds
Started Jun 04 01:44:04 PM PDT 24
Finished Jun 04 01:44:06 PM PDT 24
Peak memory 215400 kb
Host smart-be939dfa-3dc9-4be8-bea4-bd8fd18b0529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267696894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3267696894
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert.453552643
Short name T252
Test name
Test status
Simulation time 51403115 ps
CPU time 1.26 seconds
Started Jun 04 01:44:44 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 215420 kb
Host smart-37b85aec-bf09-483f-88bf-fe107ba0ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453552643 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.453552643
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.253075967
Short name T37
Test name
Test status
Simulation time 25782009 ps
CPU time 1.1 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 216716 kb
Host smart-dfe39a88-a8c4-4782-8835-d8312b29d9a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253075967 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.253075967
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_regwen.1287114967
Short name T262
Test name
Test status
Simulation time 54039683 ps
CPU time 0.95 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 206728 kb
Host smart-59d0f319-456c-4145-afeb-9a1627da5a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287114967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1287114967
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2804734368
Short name T219
Test name
Test status
Simulation time 11960121 ps
CPU time 0.88 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 206140 kb
Host smart-a26f2b80-0367-4657-976a-d000fb9daa37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804734368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2804734368
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/default/42.edn_err.2873821021
Short name T14
Test name
Test status
Simulation time 30744470 ps
CPU time 0.89 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 217960 kb
Host smart-5985f59d-ee74-45ca-bc5e-c7a49dae6f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873821021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2873821021
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.1509825214
Short name T136
Test name
Test status
Simulation time 383167032046 ps
CPU time 2114.83 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 02:20:20 PM PDT 24
Peak memory 225988 kb
Host smart-5f979cdf-651a-4a32-8df6-504765160a85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509825214 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.1509825214
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_disable.4076464354
Short name T24
Test name
Test status
Simulation time 28401458 ps
CPU time 0.81 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 216060 kb
Host smart-2465650a-e0ea-4776-8980-362d7be5d479
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076464354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.4076464354
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4277557875
Short name T247
Test name
Test status
Simulation time 129098269 ps
CPU time 1.54 seconds
Started Jun 04 12:56:00 PM PDT 24
Finished Jun 04 12:56:02 PM PDT 24
Peak memory 206156 kb
Host smart-79011027-8e45-4ae2-a3bd-ec2d88050f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277557875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4277557875
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/43.edn_disable.2265873373
Short name T67
Test name
Test status
Simulation time 28606710 ps
CPU time 0.83 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 216220 kb
Host smart-80c828ae-d389-43a5-b7d8-6363bb3d1220
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265873373 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2265873373
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable.2396637069
Short name T93
Test name
Test status
Simulation time 16928828 ps
CPU time 0.85 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 215976 kb
Host smart-504bd386-1f9e-4507-b510-3ed07b852c77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396637069 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.2396637069
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/1.edn_err.2694284368
Short name T101
Test name
Test status
Simulation time 101778463 ps
CPU time 0.94 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 228836 kb
Host smart-e9fd77b0-d20a-4b57-900d-1c0297cf35ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694284368 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2694284368
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1863089342
Short name T178
Test name
Test status
Simulation time 42059799 ps
CPU time 1.44 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 216780 kb
Host smart-79215451-dae6-45ea-9a8d-dec82b787aff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863089342 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1863089342
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1269072445
Short name T31
Test name
Test status
Simulation time 53560903 ps
CPU time 1.08 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 219244 kb
Host smart-4fd52cbd-bcea-4d31-8445-f12b79081ea5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269072445 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1269072445
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_alert.4213391144
Short name T76
Test name
Test status
Simulation time 47106175 ps
CPU time 1.18 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 215392 kb
Host smart-2903f1f8-797f-4abd-9e17-12e35fa2d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213391144 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4213391144
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/230.edn_genbits.3500856686
Short name T148
Test name
Test status
Simulation time 96779915 ps
CPU time 1.58 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218520 kb
Host smart-bea24b16-2f6e-46c2-8e30-4e5e473f2df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500856686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3500856686
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2582060462
Short name T109
Test name
Test status
Simulation time 27523665 ps
CPU time 0.88 seconds
Started Jun 04 01:44:54 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 215352 kb
Host smart-f8e0c201-7715-460b-aad4-52771e279b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582060462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2582060462
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/10.edn_intr.526653937
Short name T166
Test name
Test status
Simulation time 35999240 ps
CPU time 0.97 seconds
Started Jun 04 01:44:01 PM PDT 24
Finished Jun 04 01:44:04 PM PDT 24
Peak memory 215260 kb
Host smart-fe3c506a-1632-47cc-b20f-ea21f05cf809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526653937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.526653937
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/139.edn_genbits.310511968
Short name T390
Test name
Test status
Simulation time 44929132 ps
CPU time 1.63 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 218084 kb
Host smart-58ec53f2-9b37-4466-b5a3-e778bc672925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310511968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.310511968
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.470883166
Short name T259
Test name
Test status
Simulation time 45228642 ps
CPU time 0.94 seconds
Started Jun 04 01:44:00 PM PDT 24
Finished Jun 04 01:44:03 PM PDT 24
Peak memory 206756 kb
Host smart-e8cdb902-670b-4645-a0d8-20bf4bdf8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470883166 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.470883166
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/14.edn_disable.469547415
Short name T585
Test name
Test status
Simulation time 97908257 ps
CPU time 0.88 seconds
Started Jun 04 01:44:13 PM PDT 24
Finished Jun 04 01:44:15 PM PDT 24
Peak memory 215264 kb
Host smart-a31dce01-7824-410c-b2fe-66ec963b5e2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469547415 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.469547415
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.1873592111
Short name T84
Test name
Test status
Simulation time 10964790 ps
CPU time 0.86 seconds
Started Jun 04 01:44:06 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 216040 kb
Host smart-deb3c723-7a37-4be6-b30b-406896af3496
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873592111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1873592111
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4249830314
Short name T747
Test name
Test status
Simulation time 54423015 ps
CPU time 1.54 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 01:44:18 PM PDT 24
Peak memory 216660 kb
Host smart-39916389-34c3-4e04-8d5d-c7925d4785f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249830314 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4249830314
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4251383437
Short name T55
Test name
Test status
Simulation time 31271518 ps
CPU time 1.06 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 216576 kb
Host smart-9a554252-4de6-4388-b5b6-8c14a635bda2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251383437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4251383437
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.581231672
Short name T816
Test name
Test status
Simulation time 124208390 ps
CPU time 1.09 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 216616 kb
Host smart-603d5257-786e-4bc4-bda3-03f102bae687
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581231672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.581231672
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable.724380895
Short name T190
Test name
Test status
Simulation time 14866508 ps
CPU time 0.82 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 216032 kb
Host smart-d6a8a9e0-3d64-4c82-9804-746f8bbbc8e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724380895 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.724380895
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.429257496
Short name T94
Test name
Test status
Simulation time 87290667 ps
CPU time 0.9 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 215236 kb
Host smart-462e6a81-4c41-48a7-8955-d1d5ec8fc2be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429257496 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.429257496
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.345716085
Short name T54
Test name
Test status
Simulation time 66464612 ps
CPU time 1.1 seconds
Started Jun 04 01:44:33 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 216544 kb
Host smart-b11a02cc-f337-40e4-887f-18fdda02c1b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345716085 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.345716085
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_disable.3194083588
Short name T92
Test name
Test status
Simulation time 37314859 ps
CPU time 0.89 seconds
Started Jun 04 01:43:53 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215992 kb
Host smart-71c6b96e-38e2-4464-aac8-5241fc1ca7c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194083588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3194083588
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/66.edn_err.2055396775
Short name T95
Test name
Test status
Simulation time 19210677 ps
CPU time 1.05 seconds
Started Jun 04 01:45:19 PM PDT 24
Finished Jun 04 01:45:21 PM PDT 24
Peak memory 218056 kb
Host smart-eaebf48a-73eb-4d6c-bcc6-7b0297521576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055396775 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2055396775
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/165.edn_genbits.3640500617
Short name T10
Test name
Test status
Simulation time 123306677 ps
CPU time 1.38 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 219316 kb
Host smart-f4cc3e35-34a9-44be-8fda-4241bf500914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640500617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3640500617
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.3073644068
Short name T139
Test name
Test status
Simulation time 22520118 ps
CPU time 0.87 seconds
Started Jun 04 01:43:35 PM PDT 24
Finished Jun 04 01:43:38 PM PDT 24
Peak memory 214896 kb
Host smart-42492c68-dd40-4b4e-9f13-79357b615881
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073644068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3073644068
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_alert.365059009
Short name T266
Test name
Test status
Simulation time 74224398 ps
CPU time 1.27 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 01:44:18 PM PDT 24
Peak memory 215464 kb
Host smart-dc8c950b-f193-4a27-b967-2e3019de44e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365059009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.365059009
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/24.edn_err.1168557708
Short name T5
Test name
Test status
Simulation time 20651830 ps
CPU time 1.2 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:29 PM PDT 24
Peak memory 219420 kb
Host smart-1fe9a6ff-d634-4338-836b-27017d85495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168557708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1168557708
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3259166067
Short name T249
Test name
Test status
Simulation time 256908401 ps
CPU time 2.13 seconds
Started Jun 04 12:55:50 PM PDT 24
Finished Jun 04 12:55:54 PM PDT 24
Peak memory 206368 kb
Host smart-69a725c4-a06c-4c0a-a14b-96a89567a711
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259166067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3259166067
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/115.edn_genbits.2404320423
Short name T156
Test name
Test status
Simulation time 338006835 ps
CPU time 1.49 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:22 PM PDT 24
Peak memory 219256 kb
Host smart-6fa6f5d4-15be-49ee-9e3a-50cfca726186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404320423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2404320423
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.29729982
Short name T277
Test name
Test status
Simulation time 56697054 ps
CPU time 1.09 seconds
Started Jun 04 01:45:42 PM PDT 24
Finished Jun 04 01:45:45 PM PDT 24
Peak memory 218976 kb
Host smart-b9269da3-be1d-499a-ac66-0732de499d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29729982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.29729982
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1889512171
Short name T96
Test name
Test status
Simulation time 88645176 ps
CPU time 1.24 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 215380 kb
Host smart-0928c8cb-1278-486b-80a7-654cd2fc16a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889512171 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1889512171
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/2.edn_intr.1872323257
Short name T164
Test name
Test status
Simulation time 21064081 ps
CPU time 1.11 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 215596 kb
Host smart-6ea3de46-48bb-4753-be57-a7a0f0e6cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872323257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1872323257
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/26.edn_genbits.1790835744
Short name T123
Test name
Test status
Simulation time 50901204 ps
CPU time 1.59 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 217484 kb
Host smart-87ed7e04-5410-427b-ac81-4a20512d1b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790835744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1790835744
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.80508803
Short name T556
Test name
Test status
Simulation time 697836597246 ps
CPU time 821.56 seconds
Started Jun 04 01:43:35 PM PDT 24
Finished Jun 04 01:57:18 PM PDT 24
Peak memory 220292 kb
Host smart-21f9f501-f32f-4a8b-98c1-c8ca0dbeb40d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80508803 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.80508803
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.96181452
Short name T427
Test name
Test status
Simulation time 232272603 ps
CPU time 1.13 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:22 PM PDT 24
Peak memory 216744 kb
Host smart-2abae2ec-52ba-4ea8-9e90-2f9ad51375c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96181452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.96181452
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2928298259
Short name T285
Test name
Test status
Simulation time 93613212 ps
CPU time 1.73 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 218456 kb
Host smart-2d615ca3-d4ce-4e90-8dec-16dc9bd21e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928298259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2928298259
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1479787493
Short name T651
Test name
Test status
Simulation time 82116801 ps
CPU time 1.02 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 216720 kb
Host smart-414b25c5-1c25-42e6-9377-625eec3aaffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479787493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1479787493
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.4292194568
Short name T484
Test name
Test status
Simulation time 66411225 ps
CPU time 1.73 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 216900 kb
Host smart-2563c7d8-5634-4c3a-8580-1209c7e78288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292194568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.4292194568
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/150.edn_genbits.350198655
Short name T153
Test name
Test status
Simulation time 107374635 ps
CPU time 0.94 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216640 kb
Host smart-0f62bcdd-16c0-4350-8143-beed069a7a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350198655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.350198655
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.58617699
Short name T630
Test name
Test status
Simulation time 84775835 ps
CPU time 2.31 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 219460 kb
Host smart-723ab9b0-9e90-4495-bbb7-dcd3c0e4644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58617699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.58617699
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.95944345
Short name T282
Test name
Test status
Simulation time 46088238 ps
CPU time 1.6 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 219232 kb
Host smart-37ec940c-698c-404a-99e0-ac9a8371b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95944345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.95944345
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.3300539550
Short name T274
Test name
Test status
Simulation time 55527234 ps
CPU time 1.34 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 216876 kb
Host smart-bdc2834f-e0c5-479d-8064-5fcfb1c00b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300539550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3300539550
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1991967031
Short name T295
Test name
Test status
Simulation time 190127295 ps
CPU time 1.46 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218512 kb
Host smart-e0357221-1cf0-4978-89e2-3553d47705f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991967031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1991967031
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1550764675
Short name T269
Test name
Test status
Simulation time 35176230 ps
CPU time 1.35 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 215404 kb
Host smart-5360a997-c5d4-4e3e-ad74-7a177181ad4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550764675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1550764675
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.883117808
Short name T236
Test name
Test status
Simulation time 77441102 ps
CPU time 1.05 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 218192 kb
Host smart-25d7d4da-d40f-4f20-b0f3-ac3a8d5ae07d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883117808 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.883117808
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_regwen.3462614155
Short name T106
Test name
Test status
Simulation time 30431442 ps
CPU time 0.98 seconds
Started Jun 04 01:43:57 PM PDT 24
Finished Jun 04 01:43:59 PM PDT 24
Peak memory 206740 kb
Host smart-67e25667-e849-4f9e-9691-6fb0fdc7ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462614155 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3462614155
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_regwen.1776590757
Short name T260
Test name
Test status
Simulation time 47978059 ps
CPU time 0.94 seconds
Started Jun 04 01:44:00 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 206848 kb
Host smart-b3ee0512-7b9b-4edf-a748-2bb09be37406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776590757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1776590757
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_intr.4012670565
Short name T165
Test name
Test status
Simulation time 28545371 ps
CPU time 0.9 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 215328 kb
Host smart-66698531-362d-46ba-b32f-e7868df3071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012670565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.4012670565
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/15.edn_alert.3748495242
Short name T194
Test name
Test status
Simulation time 23966860 ps
CPU time 1.28 seconds
Started Jun 04 01:44:25 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 215388 kb
Host smart-bf3b7052-a1b0-4739-916e-04ca8d54530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748495242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3748495242
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/7.edn_disable.1194861117
Short name T195
Test name
Test status
Simulation time 114329149 ps
CPU time 0.89 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 216012 kb
Host smart-67999e5e-7fb7-4b09-9ade-fe73499ec512
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194861117 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1194861117
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/137.edn_genbits.1175859250
Short name T768
Test name
Test status
Simulation time 47310131 ps
CPU time 1.64 seconds
Started Jun 04 01:45:39 PM PDT 24
Finished Jun 04 01:45:42 PM PDT 24
Peak memory 219032 kb
Host smart-3d15f417-d143-44be-9a22-cd5088220905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175859250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1175859250
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.794684818
Short name T731
Test name
Test status
Simulation time 48135505 ps
CPU time 1.76 seconds
Started Jun 04 01:45:27 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 219316 kb
Host smart-96e57195-acb8-4e6c-a16c-06a89815f0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794684818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.794684818
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2554161658
Short name T218
Test name
Test status
Simulation time 66271510 ps
CPU time 1.3 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206060 kb
Host smart-7427aba3-5845-4b8c-a03c-cd5bf4fac0ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554161658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2554161658
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3021620951
Short name T221
Test name
Test status
Simulation time 206002421 ps
CPU time 3.68 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:38 PM PDT 24
Peak memory 206128 kb
Host smart-6af248a7-070f-4af8-aa9c-cb6558a5bbf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021620951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3021620951
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2631810094
Short name T228
Test name
Test status
Simulation time 30277903 ps
CPU time 0.95 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 206112 kb
Host smart-fd254e73-839d-4fda-bafd-9aa4fa94cbe2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631810094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2631810094
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2131108141
Short name T865
Test name
Test status
Simulation time 134074767 ps
CPU time 1.56 seconds
Started Jun 04 12:55:32 PM PDT 24
Finished Jun 04 12:55:34 PM PDT 24
Peak memory 214424 kb
Host smart-896250f8-7bbb-4922-831c-c176da290be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131108141 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2131108141
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1402670981
Short name T899
Test name
Test status
Simulation time 25091204 ps
CPU time 0.84 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 206128 kb
Host smart-2f3a7ca6-ce7a-476e-98f6-a6627c4e12fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402670981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1402670981
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.4073162487
Short name T946
Test name
Test status
Simulation time 41996249 ps
CPU time 0.81 seconds
Started Jun 04 12:55:52 PM PDT 24
Finished Jun 04 12:55:54 PM PDT 24
Peak memory 205964 kb
Host smart-fabe3abb-196d-46eb-bb8a-61038eadff0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073162487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.4073162487
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1058482384
Short name T977
Test name
Test status
Simulation time 48233640 ps
CPU time 0.97 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206112 kb
Host smart-76c73ab4-a48d-413c-a69e-f3fb47814ae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058482384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1058482384
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3252873270
Short name T937
Test name
Test status
Simulation time 61755813 ps
CPU time 2.17 seconds
Started Jun 04 12:55:29 PM PDT 24
Finished Jun 04 12:55:32 PM PDT 24
Peak memory 214348 kb
Host smart-132feeb5-a9a4-4099-b355-4488d34894f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252873270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3252873270
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3787537332
Short name T943
Test name
Test status
Simulation time 19544327 ps
CPU time 1.3 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 206104 kb
Host smart-e7a087d9-fc30-4eb9-a7e9-afd9926eed9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787537332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3787537332
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1836577741
Short name T230
Test name
Test status
Simulation time 719093179 ps
CPU time 3.89 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:42 PM PDT 24
Peak memory 206172 kb
Host smart-f0648ba3-5cfb-4589-8c7a-c93094c949c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836577741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1836577741
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.804051740
Short name T894
Test name
Test status
Simulation time 99622788 ps
CPU time 0.93 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:51 PM PDT 24
Peak memory 206084 kb
Host smart-6a48f2c8-d28a-406d-a020-c9086d098618
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804051740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.804051740
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2365816314
Short name T906
Test name
Test status
Simulation time 96352491 ps
CPU time 1.28 seconds
Started Jun 04 12:55:54 PM PDT 24
Finished Jun 04 12:55:56 PM PDT 24
Peak memory 214380 kb
Host smart-07c719b8-712b-4447-94ce-2ac4b792c966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365816314 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2365816314
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1572198961
Short name T229
Test name
Test status
Simulation time 38880989 ps
CPU time 0.89 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206148 kb
Host smart-ebee7273-816a-45f5-be1c-34a9e60f4474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572198961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1572198961
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.479438133
Short name T935
Test name
Test status
Simulation time 17101170 ps
CPU time 0.79 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:51 PM PDT 24
Peak memory 205868 kb
Host smart-e30e7714-ec4d-47f3-af36-393786cdbb3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479438133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.479438133
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.31826182
Short name T909
Test name
Test status
Simulation time 43247711 ps
CPU time 0.87 seconds
Started Jun 04 12:55:35 PM PDT 24
Finished Jun 04 12:55:37 PM PDT 24
Peak memory 206152 kb
Host smart-c9ea28d2-b128-485b-ab8c-c8d0e05b28a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_outs
tanding.31826182
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3586222059
Short name T951
Test name
Test status
Simulation time 32566727 ps
CPU time 2.2 seconds
Started Jun 04 12:55:33 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 214332 kb
Host smart-af4182e9-f8d8-407b-b287-efe5f218b6b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586222059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3586222059
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1113506979
Short name T966
Test name
Test status
Simulation time 869237534 ps
CPU time 2.3 seconds
Started Jun 04 12:55:29 PM PDT 24
Finished Jun 04 12:55:32 PM PDT 24
Peak memory 206120 kb
Host smart-99154972-4642-49c9-933d-1051c78f7cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113506979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1113506979
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4221556621
Short name T919
Test name
Test status
Simulation time 46170551 ps
CPU time 0.9 seconds
Started Jun 04 12:55:48 PM PDT 24
Finished Jun 04 12:55:49 PM PDT 24
Peak memory 206268 kb
Host smart-e83afa0b-91b6-45e2-8cd7-c519899b69be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221556621 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4221556621
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.67419575
Short name T911
Test name
Test status
Simulation time 15099174 ps
CPU time 0.97 seconds
Started Jun 04 12:55:50 PM PDT 24
Finished Jun 04 12:55:52 PM PDT 24
Peak memory 206124 kb
Host smart-896ff355-8c32-4526-a1c7-733577628e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67419575 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.67419575
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1439868989
Short name T932
Test name
Test status
Simulation time 23775727 ps
CPU time 0.87 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 205992 kb
Host smart-4521f3c7-9801-4921-80f0-158c550b27db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439868989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1439868989
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3026852627
Short name T913
Test name
Test status
Simulation time 23503614 ps
CPU time 1.14 seconds
Started Jun 04 12:55:45 PM PDT 24
Finished Jun 04 12:55:47 PM PDT 24
Peak memory 206156 kb
Host smart-0996cc99-d3c0-44e6-bae6-65c49c112a75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026852627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3026852627
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1051336214
Short name T855
Test name
Test status
Simulation time 24398613 ps
CPU time 1.65 seconds
Started Jun 04 12:55:55 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 214292 kb
Host smart-8ae45456-fcda-4535-a2d9-5b0b78e854e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051336214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1051336214
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1687283143
Short name T882
Test name
Test status
Simulation time 29213483 ps
CPU time 1.71 seconds
Started Jun 04 12:55:55 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 219088 kb
Host smart-ca1d76ae-5baf-417c-9b83-1d92c2ce0a92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687283143 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1687283143
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4052046749
Short name T961
Test name
Test status
Simulation time 14418939 ps
CPU time 0.93 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206152 kb
Host smart-cbcde633-4582-45dc-846a-cd46b3c7dcb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052046749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4052046749
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.4170144827
Short name T866
Test name
Test status
Simulation time 13789583 ps
CPU time 0.89 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 205984 kb
Host smart-f0b2b73e-9ee3-4193-9b7a-a3ec06f25af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170144827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4170144827
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.280064757
Short name T964
Test name
Test status
Simulation time 106435815 ps
CPU time 1.26 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:09 PM PDT 24
Peak memory 206112 kb
Host smart-6cbc5907-a55b-4988-9b96-4be1c61712fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280064757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.280064757
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3722997970
Short name T847
Test name
Test status
Simulation time 345851748 ps
CPU time 4.21 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:10 PM PDT 24
Peak memory 214240 kb
Host smart-0a55a884-c543-47de-8efa-80e358e12747
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722997970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3722997970
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1315661636
Short name T890
Test name
Test status
Simulation time 171492659 ps
CPU time 1.51 seconds
Started Jun 04 12:55:52 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 206128 kb
Host smart-3f217b70-3f6e-4bcb-a996-0d0b576a3f00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315661636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1315661636
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1132197263
Short name T970
Test name
Test status
Simulation time 62358434 ps
CPU time 1.01 seconds
Started Jun 04 12:55:48 PM PDT 24
Finished Jun 04 12:55:50 PM PDT 24
Peak memory 206144 kb
Host smart-74382c19-fbfd-42d3-8fbe-8e972f979778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132197263 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1132197263
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1736089050
Short name T217
Test name
Test status
Simulation time 14419627 ps
CPU time 0.94 seconds
Started Jun 04 12:55:59 PM PDT 24
Finished Jun 04 12:56:01 PM PDT 24
Peak memory 206100 kb
Host smart-7c7dedd1-d8ca-4188-955d-c58c2a2ba97a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736089050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1736089050
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3948809333
Short name T918
Test name
Test status
Simulation time 37344611 ps
CPU time 0.82 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 205996 kb
Host smart-b4ac5b5b-5660-42b8-a816-a2fd0cb016f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948809333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3948809333
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1732757484
Short name T956
Test name
Test status
Simulation time 42174159 ps
CPU time 1.34 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:52 PM PDT 24
Peak memory 206188 kb
Host smart-f7d18863-1940-4d6f-9c5d-2cecfb55c5da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732757484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1732757484
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1771010037
Short name T849
Test name
Test status
Simulation time 235498241 ps
CPU time 2.42 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 214420 kb
Host smart-912a94b4-5449-4b91-bdf8-b402c8e0a749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771010037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1771010037
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1743735418
Short name T239
Test name
Test status
Simulation time 206002773 ps
CPU time 1.41 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:07 PM PDT 24
Peak memory 206064 kb
Host smart-f2212765-58f6-4675-807e-d355d1590120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743735418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1743735418
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3763706553
Short name T878
Test name
Test status
Simulation time 18937524 ps
CPU time 0.99 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206224 kb
Host smart-2d53b6ef-c209-49f1-8aa9-31c6326ecce5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763706553 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3763706553
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1888812505
Short name T967
Test name
Test status
Simulation time 11447960 ps
CPU time 0.86 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206148 kb
Host smart-44bbeb9f-2cd1-498c-9aff-c0cee655f17f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888812505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1888812505
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2787314503
Short name T958
Test name
Test status
Simulation time 26618942 ps
CPU time 0.76 seconds
Started Jun 04 12:55:50 PM PDT 24
Finished Jun 04 12:55:52 PM PDT 24
Peak memory 205932 kb
Host smart-d747c2ac-9c9b-4f6d-9f08-dbf488401f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787314503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2787314503
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.955141148
Short name T974
Test name
Test status
Simulation time 26459311 ps
CPU time 1.21 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 205880 kb
Host smart-0b5be5b7-ead1-49b4-af2e-78e4d023cea3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955141148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.955141148
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.779961017
Short name T848
Test name
Test status
Simulation time 77098046 ps
CPU time 2.81 seconds
Started Jun 04 12:55:43 PM PDT 24
Finished Jun 04 12:55:46 PM PDT 24
Peak memory 214444 kb
Host smart-8d52dcfd-3293-4dd5-ac65-226e8661f0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779961017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.779961017
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.547213678
Short name T246
Test name
Test status
Simulation time 156743258 ps
CPU time 2.36 seconds
Started Jun 04 12:55:52 PM PDT 24
Finished Jun 04 12:55:56 PM PDT 24
Peak memory 206136 kb
Host smart-6343af85-3e22-458b-9d7d-ebb15fe2af4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547213678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.547213678
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2141048244
Short name T907
Test name
Test status
Simulation time 20551503 ps
CPU time 1.3 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 214536 kb
Host smart-dc99b8f7-25f9-44bd-a7ee-057545776575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141048244 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2141048244
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3487081671
Short name T921
Test name
Test status
Simulation time 12659303 ps
CPU time 0.91 seconds
Started Jun 04 12:55:46 PM PDT 24
Finished Jun 04 12:55:48 PM PDT 24
Peak memory 206148 kb
Host smart-18928eb9-f062-430b-bdd2-8df6cba0e024
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487081671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3487081671
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1886171239
Short name T851
Test name
Test status
Simulation time 130565612 ps
CPU time 0.79 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 205916 kb
Host smart-2ad3df89-c87d-4e28-83d6-c30f2acba669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886171239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1886171239
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3532187342
Short name T234
Test name
Test status
Simulation time 25335199 ps
CPU time 1.13 seconds
Started Jun 04 12:55:58 PM PDT 24
Finished Jun 04 12:56:00 PM PDT 24
Peak memory 206244 kb
Host smart-07acee56-bb57-4161-a09c-ccf04198737d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532187342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3532187342
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3961986713
Short name T871
Test name
Test status
Simulation time 53695299 ps
CPU time 2.09 seconds
Started Jun 04 12:56:13 PM PDT 24
Finished Jun 04 12:56:16 PM PDT 24
Peak memory 214352 kb
Host smart-1fe17436-6f8b-4682-89bf-9d7c343bb0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961986713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3961986713
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1431248162
Short name T971
Test name
Test status
Simulation time 52657656 ps
CPU time 1.74 seconds
Started Jun 04 12:55:55 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 206152 kb
Host smart-a2252316-c689-489f-bc7b-2b5f38d62043
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431248162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1431248162
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1039967370
Short name T960
Test name
Test status
Simulation time 240862950 ps
CPU time 1.44 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 214428 kb
Host smart-0962ef70-1123-44cb-bb1b-c86d14ef1415
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039967370 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1039967370
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.326269156
Short name T939
Test name
Test status
Simulation time 14236706 ps
CPU time 0.98 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 206136 kb
Host smart-28ebd46a-f5af-493d-8d3d-558946411127
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326269156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.326269156
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.943317468
Short name T886
Test name
Test status
Simulation time 25505394 ps
CPU time 0.85 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 205972 kb
Host smart-b1f6ed38-8783-4af9-b4c9-2adc2432ce15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943317468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.943317468
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1869603070
Short name T216
Test name
Test status
Simulation time 25629606 ps
CPU time 0.94 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 206216 kb
Host smart-b7f87b03-73bf-4480-a6f2-4f3558a45baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869603070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1869603070
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2481663445
Short name T953
Test name
Test status
Simulation time 48312615 ps
CPU time 1.89 seconds
Started Jun 04 12:55:50 PM PDT 24
Finished Jun 04 12:55:53 PM PDT 24
Peak memory 214324 kb
Host smart-58c58f38-01a5-4bbf-9c09-ddf2d3a68b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481663445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2481663445
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2036183863
Short name T914
Test name
Test status
Simulation time 131154908 ps
CPU time 1.57 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:56 PM PDT 24
Peak memory 214336 kb
Host smart-bba10176-0812-4f16-9504-a904af9cee1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036183863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2036183863
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1235379513
Short name T893
Test name
Test status
Simulation time 273081214 ps
CPU time 1.53 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 214320 kb
Host smart-8e9fa257-5854-4731-9a26-c3c954152970
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235379513 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1235379513
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2324364660
Short name T952
Test name
Test status
Simulation time 16399248 ps
CPU time 0.79 seconds
Started Jun 04 12:56:09 PM PDT 24
Finished Jun 04 12:56:10 PM PDT 24
Peak memory 206060 kb
Host smart-4e4280f6-f04a-4208-80cc-413efbd982c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324364660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2324364660
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.813631024
Short name T880
Test name
Test status
Simulation time 37350204 ps
CPU time 0.87 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 205940 kb
Host smart-3caff9a7-7407-4d20-b5cd-163b6de85ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813631024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.813631024
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1985490790
Short name T908
Test name
Test status
Simulation time 20065576 ps
CPU time 1.18 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206124 kb
Host smart-3e93fee7-36ff-4b24-8272-03da070fbd99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985490790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1985490790
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3673686724
Short name T901
Test name
Test status
Simulation time 101683611 ps
CPU time 2 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 214312 kb
Host smart-53de005a-9262-4b61-8203-c51fb9e9d5d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673686724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3673686724
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2597346481
Short name T912
Test name
Test status
Simulation time 95701213 ps
CPU time 2.28 seconds
Started Jun 04 12:56:06 PM PDT 24
Finished Jun 04 12:56:09 PM PDT 24
Peak memory 206392 kb
Host smart-a9de235a-c370-4c65-a9e3-502a80b3570c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597346481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2597346481
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2467203864
Short name T904
Test name
Test status
Simulation time 43484835 ps
CPU time 1.09 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 215548 kb
Host smart-f5343bf3-4173-4e6b-b6b0-a5a0572fa7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467203864 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2467203864
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.380062508
Short name T980
Test name
Test status
Simulation time 17146600 ps
CPU time 0.95 seconds
Started Jun 04 12:56:00 PM PDT 24
Finished Jun 04 12:56:02 PM PDT 24
Peak memory 206120 kb
Host smart-5f279c09-3d9b-4da6-b7c1-73c24eea14f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380062508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.380062508
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.854546094
Short name T874
Test name
Test status
Simulation time 131425444 ps
CPU time 0.85 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 205984 kb
Host smart-3597f50e-413f-497a-9cd3-90f788b9f1c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854546094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.854546094
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2667098501
Short name T926
Test name
Test status
Simulation time 23834010 ps
CPU time 1.1 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206176 kb
Host smart-2dcdbd00-7ddf-4e39-862f-13b91cf3de8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667098501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2667098501
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3561276809
Short name T891
Test name
Test status
Simulation time 72560600 ps
CPU time 2.46 seconds
Started Jun 04 12:55:58 PM PDT 24
Finished Jun 04 12:56:01 PM PDT 24
Peak memory 222528 kb
Host smart-8722acca-a201-4be0-bd8e-728505d342ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561276809 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3561276809
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1993683680
Short name T248
Test name
Test status
Simulation time 302008857 ps
CPU time 2.27 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206148 kb
Host smart-20d34592-a827-4cac-8bee-46ae596e607a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993683680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1993683680
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3128373859
Short name T872
Test name
Test status
Simulation time 35722066 ps
CPU time 1.94 seconds
Started Jun 04 12:56:12 PM PDT 24
Finished Jun 04 12:56:15 PM PDT 24
Peak memory 214552 kb
Host smart-81298107-f940-43fa-9661-972cbcd1aab7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128373859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3128373859
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1619407080
Short name T978
Test name
Test status
Simulation time 28422589 ps
CPU time 0.83 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206096 kb
Host smart-515c8c10-8127-4393-b026-1ee084e54c2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619407080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1619407080
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1540420402
Short name T896
Test name
Test status
Simulation time 21089681 ps
CPU time 0.8 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 205884 kb
Host smart-50bc0bba-5687-4d5c-9795-726b72cd649a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540420402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1540420402
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4201348425
Short name T223
Test name
Test status
Simulation time 23243597 ps
CPU time 0.99 seconds
Started Jun 04 12:56:06 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 206196 kb
Host smart-6bd2eecb-99c0-46f9-89ac-d34f1f8b3fa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201348425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4201348425
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2876324217
Short name T860
Test name
Test status
Simulation time 191024801 ps
CPU time 2.52 seconds
Started Jun 04 12:55:52 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 218228 kb
Host smart-e1e0a311-9545-4d3d-973a-ba54088f6248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876324217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2876324217
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1857692302
Short name T883
Test name
Test status
Simulation time 78393528 ps
CPU time 2.27 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206152 kb
Host smart-9db6f4e8-a971-43a2-9a6e-15c2beeb8c98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857692302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1857692302
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2664696599
Short name T863
Test name
Test status
Simulation time 31711381 ps
CPU time 1.06 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 206216 kb
Host smart-8cf9c81a-b491-47d1-b8ad-acbde6ad8488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664696599 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2664696599
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2074761574
Short name T922
Test name
Test status
Simulation time 21823889 ps
CPU time 0.86 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 206020 kb
Host smart-c7075b96-0b06-4ed5-99ba-d9ba7afaff16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074761574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2074761574
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.2343319958
Short name T224
Test name
Test status
Simulation time 109392163 ps
CPU time 1.01 seconds
Started Jun 04 12:55:58 PM PDT 24
Finished Jun 04 12:56:00 PM PDT 24
Peak memory 206144 kb
Host smart-f0864e39-726b-4670-9cae-11ae0f0ade5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343319958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.2343319958
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2644412125
Short name T936
Test name
Test status
Simulation time 213572830 ps
CPU time 2.18 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 214452 kb
Host smart-6e93bcc1-ce91-4568-97eb-6b75040cbd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644412125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2644412125
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2313420184
Short name T931
Test name
Test status
Simulation time 196875872 ps
CPU time 1.51 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206236 kb
Host smart-19c6b295-855e-4030-a88a-65c64a0024c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313420184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2313420184
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3856567947
Short name T929
Test name
Test status
Simulation time 19792829 ps
CPU time 1.32 seconds
Started Jun 04 12:55:44 PM PDT 24
Finished Jun 04 12:55:46 PM PDT 24
Peak memory 206120 kb
Host smart-52ff52d9-4be0-4183-90ac-34e8c52176b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856567947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3856567947
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.924531734
Short name T879
Test name
Test status
Simulation time 356351069 ps
CPU time 3.02 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 206124 kb
Host smart-2d4c071f-388b-4d6d-aca1-4c76a1a0598f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924531734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.924531734
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4241613471
Short name T225
Test name
Test status
Simulation time 112029487 ps
CPU time 0.87 seconds
Started Jun 04 12:55:50 PM PDT 24
Finished Jun 04 12:55:53 PM PDT 24
Peak memory 206124 kb
Host smart-5e44adb7-1e5d-41eb-b967-004a0ac87240
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241613471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4241613471
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4129121986
Short name T903
Test name
Test status
Simulation time 190190926 ps
CPU time 1.55 seconds
Started Jun 04 12:55:51 PM PDT 24
Finished Jun 04 12:55:54 PM PDT 24
Peak memory 222444 kb
Host smart-c7e8bbe1-b8a1-4f46-8b1d-374541039b48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129121986 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4129121986
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.786034801
Short name T233
Test name
Test status
Simulation time 28225182 ps
CPU time 0.85 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 206108 kb
Host smart-8916f793-9cd6-4aff-b5b7-84ebf072f114
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786034801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.786034801
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3561787650
Short name T869
Test name
Test status
Simulation time 21559327 ps
CPU time 0.88 seconds
Started Jun 04 12:55:32 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 205924 kb
Host smart-a0b6e7ec-6102-45e8-87e1-35451039234a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561787650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3561787650
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3971767763
Short name T231
Test name
Test status
Simulation time 64450124 ps
CPU time 1.09 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 206184 kb
Host smart-ceb14021-5617-4ccd-bdbe-4593044dfd4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971767763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3971767763
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1222924205
Short name T924
Test name
Test status
Simulation time 84323346 ps
CPU time 3.08 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:38 PM PDT 24
Peak memory 214480 kb
Host smart-31a4d678-ea5f-43a6-8d38-8b8b7af7f842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222924205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1222924205
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3354372688
Short name T905
Test name
Test status
Simulation time 163257768 ps
CPU time 2.52 seconds
Started Jun 04 12:55:31 PM PDT 24
Finished Jun 04 12:55:34 PM PDT 24
Peak memory 206256 kb
Host smart-65c72a65-2dee-4807-b586-6f0958cac986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354372688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3354372688
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3229739499
Short name T859
Test name
Test status
Simulation time 11737804 ps
CPU time 0.84 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206016 kb
Host smart-35583362-18cb-4d50-912f-ab2dfd3b23f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229739499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3229739499
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.4029008313
Short name T959
Test name
Test status
Simulation time 22168458 ps
CPU time 0.83 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 206016 kb
Host smart-2e37fe80-d4a3-441a-ab37-9f81729975e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029008313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.4029008313
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2105593740
Short name T856
Test name
Test status
Simulation time 14084342 ps
CPU time 0.87 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206056 kb
Host smart-8d6a9808-dae0-42aa-910e-b367920f3a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105593740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2105593740
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.88475677
Short name T927
Test name
Test status
Simulation time 28546424 ps
CPU time 0.76 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 205904 kb
Host smart-45c12cff-0427-4fc6-8c2f-6208b77d7a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88475677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.88475677
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.830248642
Short name T954
Test name
Test status
Simulation time 22493065 ps
CPU time 0.83 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 205936 kb
Host smart-d99fe9ea-ed5a-4fcc-ae96-c550e0ab01ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830248642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.830248642
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3951443410
Short name T888
Test name
Test status
Simulation time 22742342 ps
CPU time 0.85 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 206024 kb
Host smart-b44e8037-7d2e-4e78-8ddd-2edc98f529c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951443410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3951443410
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3922352454
Short name T976
Test name
Test status
Simulation time 14878598 ps
CPU time 0.96 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:07 PM PDT 24
Peak memory 206032 kb
Host smart-273ee820-93dd-48c8-830c-3a29dfe24ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922352454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3922352454
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1620200579
Short name T854
Test name
Test status
Simulation time 27312165 ps
CPU time 0.85 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206016 kb
Host smart-46c40bea-81c1-4dd8-bb91-fc7c45201e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620200579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1620200579
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1376985651
Short name T957
Test name
Test status
Simulation time 46694751 ps
CPU time 0.82 seconds
Started Jun 04 12:56:06 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 205836 kb
Host smart-df5b58d5-d0b3-4416-b321-3a5460ef91be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376985651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1376985651
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2491786852
Short name T925
Test name
Test status
Simulation time 14792833 ps
CPU time 1 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 205948 kb
Host smart-5f42a63f-ee31-441f-911f-2d01c9460961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491786852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2491786852
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2378712781
Short name T934
Test name
Test status
Simulation time 35202404 ps
CPU time 1.5 seconds
Started Jun 04 12:55:35 PM PDT 24
Finished Jun 04 12:55:37 PM PDT 24
Peak memory 206168 kb
Host smart-a48f922a-15bd-4317-8bd2-8b6b887e3b34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378712781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2378712781
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2956793045
Short name T220
Test name
Test status
Simulation time 254273865 ps
CPU time 6.43 seconds
Started Jun 04 12:55:51 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 206124 kb
Host smart-e5867b8f-560a-4680-93d0-1b33a6bc8f73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956793045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2956793045
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.402431602
Short name T238
Test name
Test status
Simulation time 26004108 ps
CPU time 0.92 seconds
Started Jun 04 12:55:41 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 206080 kb
Host smart-727c1694-9f09-471b-a742-83bd9a2f31a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402431602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.402431602
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1690577332
Short name T864
Test name
Test status
Simulation time 73504524 ps
CPU time 1.34 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:40 PM PDT 24
Peak memory 214524 kb
Host smart-3056aa92-b6bf-4aae-9590-75376318496d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690577332 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1690577332
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1182798195
Short name T940
Test name
Test status
Simulation time 28926181 ps
CPU time 0.9 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 206112 kb
Host smart-bc82005b-0f13-41a9-8a5d-c69a4ece6b38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182798195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1182798195
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1664960211
Short name T850
Test name
Test status
Simulation time 25092259 ps
CPU time 0.87 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 205980 kb
Host smart-409024ee-e4f1-4ac5-aee0-41c02efb184a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664960211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1664960211
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3111925201
Short name T933
Test name
Test status
Simulation time 38281230 ps
CPU time 1.51 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:40 PM PDT 24
Peak memory 206136 kb
Host smart-67a1f9bb-3e29-4300-8b09-c17ec2e559e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111925201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3111925201
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2369219554
Short name T873
Test name
Test status
Simulation time 102972270 ps
CPU time 3.67 seconds
Started Jun 04 12:55:58 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 214404 kb
Host smart-f1aa6d68-7282-4c5d-8a0b-174344773484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369219554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2369219554
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3024171019
Short name T965
Test name
Test status
Simulation time 165366121 ps
CPU time 2.23 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:53 PM PDT 24
Peak memory 214344 kb
Host smart-71fbca65-c7c4-4637-ac78-5ea64d70ab61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024171019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3024171019
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2957797642
Short name T857
Test name
Test status
Simulation time 43299738 ps
CPU time 0.89 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 205936 kb
Host smart-12ac1a12-8246-4f26-8ed8-24ef96777eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957797642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2957797642
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2398543082
Short name T902
Test name
Test status
Simulation time 37888059 ps
CPU time 0.79 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 205892 kb
Host smart-3d1d97ec-1cfd-4f7f-afb8-9c27677b0b92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398543082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2398543082
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3007511889
Short name T968
Test name
Test status
Simulation time 10800743 ps
CPU time 0.84 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 205992 kb
Host smart-eed86258-c876-485a-a99d-fd01bbd9f542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007511889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3007511889
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1719907490
Short name T877
Test name
Test status
Simulation time 24367916 ps
CPU time 0.83 seconds
Started Jun 04 12:56:00 PM PDT 24
Finished Jun 04 12:56:01 PM PDT 24
Peak memory 206024 kb
Host smart-d683288b-eaae-4182-8cc4-0275d33fcdbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719907490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1719907490
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.213060683
Short name T862
Test name
Test status
Simulation time 93526091 ps
CPU time 0.83 seconds
Started Jun 04 12:55:57 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206000 kb
Host smart-b834249d-b7d5-4e9a-b325-a44bed95ee7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213060683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.213060683
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.920996862
Short name T950
Test name
Test status
Simulation time 54060721 ps
CPU time 0.77 seconds
Started Jun 04 12:56:06 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 205840 kb
Host smart-aa0bad2f-9235-47d8-ae7c-a49c3b9945fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920996862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.920996862
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.10604905
Short name T910
Test name
Test status
Simulation time 13234622 ps
CPU time 0.9 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 206004 kb
Host smart-f28ca13d-6bd4-455a-a04b-991babf362b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10604905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.10604905
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1742517503
Short name T852
Test name
Test status
Simulation time 11971573 ps
CPU time 0.86 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:07 PM PDT 24
Peak memory 206024 kb
Host smart-48a39a26-87a2-4f12-ae55-e8e44cfcae57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742517503 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1742517503
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.25770785
Short name T898
Test name
Test status
Simulation time 13441250 ps
CPU time 0.88 seconds
Started Jun 04 12:56:00 PM PDT 24
Finished Jun 04 12:56:02 PM PDT 24
Peak memory 205932 kb
Host smart-253a85aa-5a4e-4ec6-8a42-9c7d461e64b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25770785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.25770785
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.538849671
Short name T884
Test name
Test status
Simulation time 10620152 ps
CPU time 0.83 seconds
Started Jun 04 12:55:55 PM PDT 24
Finished Jun 04 12:55:56 PM PDT 24
Peak memory 205896 kb
Host smart-fb4928f2-7c50-4ffe-9726-7f290c3b801f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538849671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.538849671
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.957372228
Short name T889
Test name
Test status
Simulation time 18355930 ps
CPU time 1.08 seconds
Started Jun 04 12:55:33 PM PDT 24
Finished Jun 04 12:55:34 PM PDT 24
Peak memory 206184 kb
Host smart-5fff0732-f06c-45b0-83fb-1cc3404f1d0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957372228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.957372228
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2765571493
Short name T222
Test name
Test status
Simulation time 63662250 ps
CPU time 2.01 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:52 PM PDT 24
Peak memory 206164 kb
Host smart-94095c27-88ce-48c8-9fb6-e9cdf2f761ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765571493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2765571493
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3814683564
Short name T226
Test name
Test status
Simulation time 15432255 ps
CPU time 0.88 seconds
Started Jun 04 12:55:58 PM PDT 24
Finished Jun 04 12:55:59 PM PDT 24
Peak memory 206076 kb
Host smart-6e6b8701-4877-464d-b50c-1cb362e2e5e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814683564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3814683564
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3840120393
Short name T867
Test name
Test status
Simulation time 32209590 ps
CPU time 1.06 seconds
Started Jun 04 12:55:33 PM PDT 24
Finished Jun 04 12:55:35 PM PDT 24
Peak memory 216184 kb
Host smart-c2fe14d8-cd8d-4b5c-ac83-a8a2f911cb7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840120393 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3840120393
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1184146883
Short name T920
Test name
Test status
Simulation time 37490076 ps
CPU time 0.9 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:38 PM PDT 24
Peak memory 206136 kb
Host smart-cd9aa46e-516b-45cf-81e7-1f6f42356e72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184146883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1184146883
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2676965076
Short name T846
Test name
Test status
Simulation time 31072987 ps
CPU time 0.82 seconds
Started Jun 04 12:55:47 PM PDT 24
Finished Jun 04 12:55:49 PM PDT 24
Peak memory 205960 kb
Host smart-faccb0f6-1e58-493d-90c5-69c5819194d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676965076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2676965076
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1720683485
Short name T969
Test name
Test status
Simulation time 13865547 ps
CPU time 0.99 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 206136 kb
Host smart-9defe6f8-18fd-4c49-8bfc-ee99519ac04b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720683485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1720683485
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.4147311102
Short name T947
Test name
Test status
Simulation time 55612206 ps
CPU time 2.93 seconds
Started Jun 04 12:55:36 PM PDT 24
Finished Jun 04 12:55:41 PM PDT 24
Peak memory 214340 kb
Host smart-53e7ec9d-b4ec-4dd4-9d55-8e3225461e06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147311102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.4147311102
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1983526250
Short name T241
Test name
Test status
Simulation time 644128718 ps
CPU time 2.63 seconds
Started Jun 04 12:55:47 PM PDT 24
Finished Jun 04 12:55:50 PM PDT 24
Peak memory 206160 kb
Host smart-bdeb9b1e-3011-4f9c-a06b-df548b5c3edf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983526250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1983526250
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.342522489
Short name T900
Test name
Test status
Simulation time 20114682 ps
CPU time 0.84 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206020 kb
Host smart-c142aec2-156d-4985-b1d8-b75c7b6ccf98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342522489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.342522489
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2427422728
Short name T942
Test name
Test status
Simulation time 13526675 ps
CPU time 0.84 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 205972 kb
Host smart-4cf6b9b3-23fa-4388-8e38-55a7f601b3f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427422728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2427422728
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3207185378
Short name T955
Test name
Test status
Simulation time 14540759 ps
CPU time 0.89 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206032 kb
Host smart-2303e8ca-4819-4865-a38e-8e21d3c0ca51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207185378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3207185378
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2603149191
Short name T875
Test name
Test status
Simulation time 20118133 ps
CPU time 0.81 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 205940 kb
Host smart-0ef90f3b-6dc8-46a0-87cb-e0d79465f675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603149191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2603149191
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3979590558
Short name T858
Test name
Test status
Simulation time 16332547 ps
CPU time 0.88 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 205992 kb
Host smart-0d0b1b7f-780a-489a-a36d-89d32d3509fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979590558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3979590558
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.757257038
Short name T972
Test name
Test status
Simulation time 37554821 ps
CPU time 0.83 seconds
Started Jun 04 12:56:03 PM PDT 24
Finished Jun 04 12:56:05 PM PDT 24
Peak memory 206020 kb
Host smart-daf29b5a-783e-4834-b864-51cb8eb9d50a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757257038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.757257038
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3121313916
Short name T861
Test name
Test status
Simulation time 45490625 ps
CPU time 0.89 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 205960 kb
Host smart-bd084217-1eeb-4585-beea-e20411e2bece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121313916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3121313916
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3471778316
Short name T948
Test name
Test status
Simulation time 42464103 ps
CPU time 0.82 seconds
Started Jun 04 12:56:02 PM PDT 24
Finished Jun 04 12:56:04 PM PDT 24
Peak memory 205908 kb
Host smart-b32409a4-9d71-4d07-af19-713ed4e367f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471778316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3471778316
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2580991132
Short name T887
Test name
Test status
Simulation time 11028169 ps
CPU time 0.86 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206024 kb
Host smart-1d2163fe-1961-4fc4-aa4e-47e1048bd67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580991132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2580991132
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.591568377
Short name T938
Test name
Test status
Simulation time 23464045 ps
CPU time 0.87 seconds
Started Jun 04 12:56:36 PM PDT 24
Finished Jun 04 12:56:37 PM PDT 24
Peak memory 206028 kb
Host smart-7d2d01ed-fba0-4b10-b7da-10a814bd75a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591568377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.591568377
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.909109475
Short name T870
Test name
Test status
Simulation time 77119220 ps
CPU time 1.47 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:40 PM PDT 24
Peak memory 214380 kb
Host smart-56717447-5172-4ac4-991e-990595e7e82a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909109475 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.909109475
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3347261830
Short name T876
Test name
Test status
Simulation time 76878808 ps
CPU time 0.83 seconds
Started Jun 04 12:55:34 PM PDT 24
Finished Jun 04 12:55:36 PM PDT 24
Peak memory 206060 kb
Host smart-5c4f7948-61b0-4ca1-bb97-a7c2cf3c5d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347261830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3347261830
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2175630375
Short name T979
Test name
Test status
Simulation time 15590778 ps
CPU time 0.88 seconds
Started Jun 04 12:55:35 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206016 kb
Host smart-7eb6aa55-e6bd-4e04-a09b-3ead255ac84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175630375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2175630375
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2786192256
Short name T232
Test name
Test status
Simulation time 38169827 ps
CPU time 1.16 seconds
Started Jun 04 12:55:37 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206104 kb
Host smart-ecac3aad-4795-4ac9-8135-f40adb196872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786192256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2786192256
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.169257723
Short name T944
Test name
Test status
Simulation time 91657813 ps
CPU time 1.95 seconds
Started Jun 04 12:55:39 PM PDT 24
Finished Jun 04 12:55:41 PM PDT 24
Peak memory 214348 kb
Host smart-136ec137-d1e4-4010-b4a5-ad4583c62d40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169257723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.169257723
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.656302899
Short name T975
Test name
Test status
Simulation time 101303510 ps
CPU time 1.77 seconds
Started Jun 04 12:55:38 PM PDT 24
Finished Jun 04 12:55:40 PM PDT 24
Peak memory 206104 kb
Host smart-a256feee-5b69-4752-b6ac-9cd49021e273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656302899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.656302899
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.46226790
Short name T897
Test name
Test status
Simulation time 30708049 ps
CPU time 2.02 seconds
Started Jun 04 12:55:49 PM PDT 24
Finished Jun 04 12:55:52 PM PDT 24
Peak memory 214480 kb
Host smart-45663521-f7ae-4bfb-902d-6a1f0e6412ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46226790 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.46226790
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3446654280
Short name T928
Test name
Test status
Simulation time 41631130 ps
CPU time 0.9 seconds
Started Jun 04 12:55:38 PM PDT 24
Finished Jun 04 12:55:39 PM PDT 24
Peak memory 206144 kb
Host smart-79862af9-ca8f-4e6a-99cf-e96e680b3c45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446654280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3446654280
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3659196751
Short name T973
Test name
Test status
Simulation time 34223516 ps
CPU time 0.8 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 205920 kb
Host smart-f9dc48c4-a083-4fa7-94fe-286a0272fab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659196751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3659196751
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2182331411
Short name T916
Test name
Test status
Simulation time 29055677 ps
CPU time 1.05 seconds
Started Jun 04 12:55:48 PM PDT 24
Finished Jun 04 12:55:49 PM PDT 24
Peak memory 206092 kb
Host smart-37433e7e-9b9f-4458-b9e2-2f8ac6629cf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182331411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2182331411
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1478732120
Short name T923
Test name
Test status
Simulation time 48064771 ps
CPU time 2.07 seconds
Started Jun 04 12:55:44 PM PDT 24
Finished Jun 04 12:55:47 PM PDT 24
Peak memory 214444 kb
Host smart-32548855-d54c-4ae9-97fb-fc82f7e4177d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478732120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1478732120
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.344297585
Short name T240
Test name
Test status
Simulation time 93755406 ps
CPU time 2.12 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:09 PM PDT 24
Peak memory 214212 kb
Host smart-d276e9b2-6fdc-4637-999b-097464d7ccf6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344297585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.344297585
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3226699041
Short name T895
Test name
Test status
Simulation time 106660379 ps
CPU time 1.94 seconds
Started Jun 04 12:55:45 PM PDT 24
Finished Jun 04 12:55:47 PM PDT 24
Peak memory 214432 kb
Host smart-65adb74e-7287-4d89-a222-2176ebb9d48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226699041 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3226699041
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3144722188
Short name T227
Test name
Test status
Simulation time 14088314 ps
CPU time 0.89 seconds
Started Jun 04 12:56:04 PM PDT 24
Finished Jun 04 12:56:06 PM PDT 24
Peak memory 206064 kb
Host smart-a939f59c-3421-4d6e-9c1e-32908f403aac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144722188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3144722188
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2578029873
Short name T853
Test name
Test status
Simulation time 16373163 ps
CPU time 0.79 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 205832 kb
Host smart-9def0b35-04f9-4014-af37-6ea3c7bb9382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578029873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2578029873
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.841859524
Short name T235
Test name
Test status
Simulation time 12902186 ps
CPU time 0.98 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 206076 kb
Host smart-76714645-eb70-4bab-8de2-2c9044d9c1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841859524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.841859524
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1515886422
Short name T915
Test name
Test status
Simulation time 65996969 ps
CPU time 2.59 seconds
Started Jun 04 12:55:48 PM PDT 24
Finished Jun 04 12:55:51 PM PDT 24
Peak memory 214284 kb
Host smart-21c7c0ba-0681-4465-a4d2-130bf1935f51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515886422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1515886422
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2217743002
Short name T930
Test name
Test status
Simulation time 44163115 ps
CPU time 1.56 seconds
Started Jun 04 12:55:53 PM PDT 24
Finished Jun 04 12:55:56 PM PDT 24
Peak memory 206176 kb
Host smart-d20b3f80-4dd8-452d-9549-c83ef7d8adbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217743002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2217743002
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4263821858
Short name T892
Test name
Test status
Simulation time 19208139 ps
CPU time 1.12 seconds
Started Jun 04 12:55:46 PM PDT 24
Finished Jun 04 12:55:48 PM PDT 24
Peak memory 214340 kb
Host smart-4d52500c-2125-4df9-97d0-618bd9a892ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263821858 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4263821858
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.799351417
Short name T917
Test name
Test status
Simulation time 23625847 ps
CPU time 0.86 seconds
Started Jun 04 12:55:51 PM PDT 24
Finished Jun 04 12:55:53 PM PDT 24
Peak memory 206028 kb
Host smart-965730fb-ca4d-4985-89f2-e42d765bcf13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799351417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.799351417
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2268333405
Short name T868
Test name
Test status
Simulation time 21630143 ps
CPU time 0.85 seconds
Started Jun 04 12:56:01 PM PDT 24
Finished Jun 04 12:56:03 PM PDT 24
Peak memory 206024 kb
Host smart-21b7d614-dd26-43bb-b2dd-dd44c6736275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268333405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2268333405
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2071996136
Short name T963
Test name
Test status
Simulation time 228114366 ps
CPU time 1.09 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 206088 kb
Host smart-0c37f478-123d-44f5-85e4-80796864e7c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071996136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2071996136
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.873222481
Short name T941
Test name
Test status
Simulation time 46415562 ps
CPU time 1.72 seconds
Started Jun 04 12:55:39 PM PDT 24
Finished Jun 04 12:55:42 PM PDT 24
Peak memory 214336 kb
Host smart-95335290-2ded-46c2-ab0c-3a7b7f685613
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873222481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.873222481
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3992851389
Short name T885
Test name
Test status
Simulation time 113663023 ps
CPU time 1.93 seconds
Started Jun 04 12:55:56 PM PDT 24
Finished Jun 04 12:55:58 PM PDT 24
Peak memory 206104 kb
Host smart-59d11aea-b463-42d4-bddc-9afe3cd0840a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992851389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3992851389
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.948829094
Short name T881
Test name
Test status
Simulation time 27649914 ps
CPU time 1.27 seconds
Started Jun 04 12:56:05 PM PDT 24
Finished Jun 04 12:56:08 PM PDT 24
Peak memory 216956 kb
Host smart-a8a5757a-20df-47ef-8c97-7881ebf70ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948829094 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.948829094
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1525948414
Short name T237
Test name
Test status
Simulation time 33037191 ps
CPU time 0.81 seconds
Started Jun 04 12:55:59 PM PDT 24
Finished Jun 04 12:56:01 PM PDT 24
Peak memory 206020 kb
Host smart-e0e5baff-6d6e-4f26-b643-84f8f03849d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525948414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1525948414
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.4027485153
Short name T949
Test name
Test status
Simulation time 15819462 ps
CPU time 0.96 seconds
Started Jun 04 12:55:42 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 206172 kb
Host smart-255cb3dd-df49-46aa-bd9f-ff82211651c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027485153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.4027485153
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.590149702
Short name T945
Test name
Test status
Simulation time 14415640 ps
CPU time 1 seconds
Started Jun 04 12:55:41 PM PDT 24
Finished Jun 04 12:55:43 PM PDT 24
Peak memory 206172 kb
Host smart-3ffdfb0f-5142-40fe-871e-1599242c05e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590149702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.590149702
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3058424928
Short name T962
Test name
Test status
Simulation time 151930354 ps
CPU time 2.91 seconds
Started Jun 04 12:55:51 PM PDT 24
Finished Jun 04 12:55:55 PM PDT 24
Peak memory 222572 kb
Host smart-1c6e0b19-9877-496b-a27f-a69afcff9fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058424928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3058424928
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2568434695
Short name T245
Test name
Test status
Simulation time 399424468 ps
CPU time 1.8 seconds
Started Jun 04 12:55:54 PM PDT 24
Finished Jun 04 12:55:57 PM PDT 24
Peak memory 206168 kb
Host smart-eb9dfbc8-f4a1-4be6-88be-ffb89729241f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568434695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2568434695
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.1486803691
Short name T267
Test name
Test status
Simulation time 45021986 ps
CPU time 1.2 seconds
Started Jun 04 01:43:39 PM PDT 24
Finished Jun 04 01:43:41 PM PDT 24
Peak memory 215388 kb
Host smart-be4a8dfe-5aee-49e8-9f87-148d7b65c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486803691 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1486803691
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable.2294091210
Short name T188
Test name
Test status
Simulation time 11124760 ps
CPU time 0.93 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:38 PM PDT 24
Peak memory 216092 kb
Host smart-6d50f19d-60f5-417d-8534-5f31102e2b29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294091210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2294091210
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.316676558
Short name T408
Test name
Test status
Simulation time 38275095 ps
CPU time 1.34 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:39 PM PDT 24
Peak memory 216556 kb
Host smart-b9f51290-facb-4101-b63d-68abf0119f79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316676558 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.316676558
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.654400953
Short name T709
Test name
Test status
Simulation time 34608187 ps
CPU time 0.97 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:38 PM PDT 24
Peak memory 223292 kb
Host smart-77202586-ae54-4668-868f-439e4828304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654400953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.654400953
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.538006396
Short name T784
Test name
Test status
Simulation time 35095501 ps
CPU time 1.6 seconds
Started Jun 04 01:43:39 PM PDT 24
Finished Jun 04 01:43:41 PM PDT 24
Peak memory 216668 kb
Host smart-b41d3738-bf88-47b3-b90c-f3f89d05d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538006396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.538006396
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.277989460
Short name T615
Test name
Test status
Simulation time 28212815 ps
CPU time 0.87 seconds
Started Jun 04 01:43:38 PM PDT 24
Finished Jun 04 01:43:40 PM PDT 24
Peak memory 215268 kb
Host smart-bbc9c442-5be3-490f-94f1-be312b864066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277989460 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.277989460
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3396797981
Short name T21
Test name
Test status
Simulation time 201713025 ps
CPU time 0.96 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:38 PM PDT 24
Peak memory 206796 kb
Host smart-1c83f8f2-b3a5-49a9-869d-e4b5e97c1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396797981 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3396797981
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1910076488
Short name T17
Test name
Test status
Simulation time 235723941 ps
CPU time 4.17 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:42 PM PDT 24
Peak memory 236128 kb
Host smart-d75a5df3-ea02-494a-a06d-bc0b37dad3fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910076488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1910076488
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2653295965
Short name T738
Test name
Test status
Simulation time 53571091 ps
CPU time 0.92 seconds
Started Jun 04 01:43:34 PM PDT 24
Finished Jun 04 01:43:36 PM PDT 24
Peak memory 215012 kb
Host smart-edc94b42-7cd1-45d3-96e8-a9bab5c05a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653295965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2653295965
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3568903907
Short name T659
Test name
Test status
Simulation time 359152076 ps
CPU time 6.91 seconds
Started Jun 04 01:43:38 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 214972 kb
Host smart-88cdc8cd-80da-4a9e-91d4-ee3ba26c2a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568903907 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3568903907
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.2832936503
Short name T663
Test name
Test status
Simulation time 36488475 ps
CPU time 1.11 seconds
Started Jun 04 01:43:42 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 215380 kb
Host smart-44796ab3-2baf-4e04-8f69-644d898c58bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832936503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2832936503
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1763573361
Short name T435
Test name
Test status
Simulation time 182767262 ps
CPU time 0.92 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 206356 kb
Host smart-8da4e117-8ac2-42bd-b32d-e528a3a66334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763573361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1763573361
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1814433064
Short name T627
Test name
Test status
Simulation time 116422245 ps
CPU time 0.85 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:43:47 PM PDT 24
Peak memory 215248 kb
Host smart-7be86e6c-3bac-4205-b25c-19ef2aa3617e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814433064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1814433064
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.550736557
Short name T184
Test name
Test status
Simulation time 76280566 ps
CPU time 1.12 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 216824 kb
Host smart-ceaa34e3-6aa2-4352-86d9-599e15d175eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550736557 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.550736557
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.688511789
Short name T820
Test name
Test status
Simulation time 79177348 ps
CPU time 1.17 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:39 PM PDT 24
Peak memory 216848 kb
Host smart-986cdff9-f6fe-4937-b83c-43f5ae3b6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688511789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.688511789
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.4115356167
Short name T654
Test name
Test status
Simulation time 26574330 ps
CPU time 1.23 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:39 PM PDT 24
Peak memory 223636 kb
Host smart-49f507de-b539-46d4-b8e1-0c33cffcb0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115356167 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4115356167
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2408624770
Short name T257
Test name
Test status
Simulation time 23828149 ps
CPU time 0.95 seconds
Started Jun 04 01:43:38 PM PDT 24
Finished Jun 04 01:43:40 PM PDT 24
Peak memory 206788 kb
Host smart-62c76d64-8658-47d8-a9b0-07d13b5f315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408624770 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2408624770
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.776502632
Short name T133
Test name
Test status
Simulation time 537212065 ps
CPU time 4.77 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:50 PM PDT 24
Peak memory 234360 kb
Host smart-18f36d17-eef6-4ff4-b759-adf7242b2501
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776502632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.776502632
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2220270788
Short name T114
Test name
Test status
Simulation time 19245618 ps
CPU time 1.03 seconds
Started Jun 04 01:43:36 PM PDT 24
Finished Jun 04 01:43:38 PM PDT 24
Peak memory 214960 kb
Host smart-94addba1-50de-435f-aafa-05233281cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220270788 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2220270788
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.4216323249
Short name T587
Test name
Test status
Simulation time 714052177 ps
CPU time 4.22 seconds
Started Jun 04 01:43:35 PM PDT 24
Finished Jun 04 01:43:41 PM PDT 24
Peak memory 215076 kb
Host smart-431f8028-78c8-42f9-9c97-df189b72fbf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216323249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4216323249
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.1645408279
Short name T251
Test name
Test status
Simulation time 44781811 ps
CPU time 1.18 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 215400 kb
Host smart-0d87aeac-e561-4af9-8bbe-8aa814a910a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645408279 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1645408279
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2296598609
Short name T831
Test name
Test status
Simulation time 18367607 ps
CPU time 1 seconds
Started Jun 04 01:44:09 PM PDT 24
Finished Jun 04 01:44:11 PM PDT 24
Peak memory 206316 kb
Host smart-4b92afed-027e-4c24-a429-682660ad21cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296598609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2296598609
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.941158349
Short name T617
Test name
Test status
Simulation time 73385809 ps
CPU time 0.85 seconds
Started Jun 04 01:44:06 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 215292 kb
Host smart-26aeaa6c-d35f-4fa7-883c-9dc73aedcba8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941158349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.941158349
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.291973409
Short name T604
Test name
Test status
Simulation time 20429054 ps
CPU time 1.06 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 216580 kb
Host smart-0834c15a-6f2b-4a15-b7c4-898aba5aed8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291973409 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.291973409
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1418361014
Short name T530
Test name
Test status
Simulation time 25016036 ps
CPU time 0.87 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:01 PM PDT 24
Peak memory 217692 kb
Host smart-d6b950d8-83a3-4686-bb07-7add0f3a7a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418361014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1418361014
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.4205055153
Short name T780
Test name
Test status
Simulation time 44475585 ps
CPU time 1.4 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 217812 kb
Host smart-f22daa26-59f2-4059-9132-8d57564bb78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205055153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4205055153
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.2880222243
Short name T437
Test name
Test status
Simulation time 57379870 ps
CPU time 0.96 seconds
Started Jun 04 01:44:00 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 214876 kb
Host smart-45c16686-8585-4457-bb7b-e08c9ae398be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880222243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2880222243
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3678394944
Short name T455
Test name
Test status
Simulation time 67498921 ps
CPU time 1.37 seconds
Started Jun 04 01:44:03 PM PDT 24
Finished Jun 04 01:44:05 PM PDT 24
Peak memory 214876 kb
Host smart-53924fe1-bfbd-4bfe-bd1f-48692c2b8709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678394944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3678394944
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1662457738
Short name T346
Test name
Test status
Simulation time 51859597682 ps
CPU time 1187.05 seconds
Started Jun 04 01:44:03 PM PDT 24
Finished Jun 04 02:03:51 PM PDT 24
Peak memory 219596 kb
Host smart-f935480e-016a-424d-abcb-23e4ea9df4da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662457738 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1662457738
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.1162423143
Short name T786
Test name
Test status
Simulation time 40626960 ps
CPU time 1.41 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 217844 kb
Host smart-43e9f043-7cbd-4825-a529-67c5a00e8164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162423143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1162423143
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.188566420
Short name T569
Test name
Test status
Simulation time 46707772 ps
CPU time 1.11 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216776 kb
Host smart-aab30f25-8459-466e-b4b2-06e8ab5588bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188566420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.188566420
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.57204062
Short name T727
Test name
Test status
Simulation time 70632646 ps
CPU time 1.22 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:22 PM PDT 24
Peak memory 219380 kb
Host smart-2b81d618-6808-449f-bf33-126bbd603a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57204062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.57204062
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2353312109
Short name T515
Test name
Test status
Simulation time 38105649 ps
CPU time 1.44 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 216816 kb
Host smart-ce823034-d430-4152-8d86-95b9e05ec47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353312109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2353312109
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.424685376
Short name T743
Test name
Test status
Simulation time 49445742 ps
CPU time 1.26 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216616 kb
Host smart-0fb3fb94-5fa8-41f3-a70d-2831451df6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424685376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.424685376
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3965253723
Short name T576
Test name
Test status
Simulation time 55798820 ps
CPU time 1.31 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 218376 kb
Host smart-5fd3a8f1-c9cf-459c-8769-6999b1ac033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965253723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3965253723
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2706599831
Short name T666
Test name
Test status
Simulation time 53385083 ps
CPU time 1.29 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 219332 kb
Host smart-699da13d-adbb-4400-9edf-4925caed8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706599831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2706599831
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.107900996
Short name T430
Test name
Test status
Simulation time 46154671 ps
CPU time 1.42 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 216684 kb
Host smart-7efc9d66-0a72-413b-85ec-65fdb3af8cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107900996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.107900996
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.876086157
Short name T258
Test name
Test status
Simulation time 77380215 ps
CPU time 1.22 seconds
Started Jun 04 01:44:04 PM PDT 24
Finished Jun 04 01:44:07 PM PDT 24
Peak memory 215348 kb
Host smart-1ae2d08c-0bdd-43ef-9ed6-c651842ba98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876086157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.876086157
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2307409469
Short name T394
Test name
Test status
Simulation time 21181955 ps
CPU time 1.06 seconds
Started Jun 04 01:44:11 PM PDT 24
Finished Jun 04 01:44:12 PM PDT 24
Peak memory 214652 kb
Host smart-73ca8b0c-b67d-4e8a-af52-596ba8191f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307409469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2307409469
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.957130061
Short name T81
Test name
Test status
Simulation time 30967635 ps
CPU time 0.9 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:07 PM PDT 24
Peak memory 218020 kb
Host smart-608cea44-e855-4fe1-91ed-cd063ad291ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957130061 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.957130061
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.927448653
Short name T160
Test name
Test status
Simulation time 54562858 ps
CPU time 1.35 seconds
Started Jun 04 01:44:07 PM PDT 24
Finished Jun 04 01:44:10 PM PDT 24
Peak memory 217936 kb
Host smart-6a1fdf36-b955-4605-a486-6c48d8cc5146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927448653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.927448653
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2371093830
Short name T706
Test name
Test status
Simulation time 24637045 ps
CPU time 0.98 seconds
Started Jun 04 01:44:06 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 215344 kb
Host smart-e2c9a431-8039-4dc2-be13-8b9b1804ffb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371093830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2371093830
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2660800436
Short name T495
Test name
Test status
Simulation time 19089420 ps
CPU time 1.02 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 215028 kb
Host smart-118cf4e4-6b3d-4c90-bf6a-c15ffa593a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660800436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2660800436
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1486713336
Short name T451
Test name
Test status
Simulation time 294535493 ps
CPU time 1.06 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 206700 kb
Host smart-6bec0216-c690-494b-853e-a0890f2edfdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486713336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1486713336
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1653364893
Short name T203
Test name
Test status
Simulation time 380460375487 ps
CPU time 1316.95 seconds
Started Jun 04 01:44:10 PM PDT 24
Finished Jun 04 02:06:08 PM PDT 24
Peak memory 223308 kb
Host smart-5ae33ea6-4772-4979-aa06-5ba4efa50e9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653364893 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1653364893
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.687429793
Short name T325
Test name
Test status
Simulation time 44332572 ps
CPU time 1.12 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 216552 kb
Host smart-a9b1f09b-cab8-49e3-a85d-5099fdaf96f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687429793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.687429793
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.659777801
Short name T570
Test name
Test status
Simulation time 115445114 ps
CPU time 2.74 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 217016 kb
Host smart-f7260963-ee44-4844-ac56-183cd508939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659777801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.659777801
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.82022211
Short name T209
Test name
Test status
Simulation time 89020005 ps
CPU time 1.44 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 216932 kb
Host smart-69498910-e3c5-43d2-b8ff-0ac8fe4b8419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82022211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.82022211
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.874355299
Short name T789
Test name
Test status
Simulation time 196786915 ps
CPU time 1.48 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:23 PM PDT 24
Peak memory 218356 kb
Host smart-f171e16b-52b7-42d2-a26f-74d4bb08936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874355299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.874355299
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.4097813965
Short name T623
Test name
Test status
Simulation time 133785656 ps
CPU time 1 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 216940 kb
Host smart-63272a9d-74eb-4e79-b284-fe27a710b123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097813965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.4097813965
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2367094903
Short name T561
Test name
Test status
Simulation time 188476899 ps
CPU time 3.14 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:25 PM PDT 24
Peak memory 219532 kb
Host smart-e949951c-d505-43e8-9897-56ec9af8f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367094903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2367094903
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1622748492
Short name T19
Test name
Test status
Simulation time 42698915 ps
CPU time 1.46 seconds
Started Jun 04 01:45:19 PM PDT 24
Finished Jun 04 01:45:22 PM PDT 24
Peak memory 219380 kb
Host smart-d7442626-e3ba-40c4-a856-57541655eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622748492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1622748492
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.703106419
Short name T280
Test name
Test status
Simulation time 80545936 ps
CPU time 1.17 seconds
Started Jun 04 01:45:23 PM PDT 24
Finished Jun 04 01:45:26 PM PDT 24
Peak memory 216920 kb
Host smart-08fc2051-1ef8-47a6-b5cb-a30f35f7048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703106419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.703106419
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.540497069
Short name T193
Test name
Test status
Simulation time 26838969 ps
CPU time 1.21 seconds
Started Jun 04 01:44:09 PM PDT 24
Finished Jun 04 01:44:11 PM PDT 24
Peak memory 215408 kb
Host smart-3d6b7bc7-e690-4b66-b77d-f8e5847fdc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540497069 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.540497069
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3239727606
Short name T401
Test name
Test status
Simulation time 76569032 ps
CPU time 0.96 seconds
Started Jun 04 01:44:06 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 206336 kb
Host smart-2fdbf449-d6c7-41f3-80ff-959b3be647f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239727606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3239727606
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1463044363
Short name T787
Test name
Test status
Simulation time 13718665 ps
CPU time 1.03 seconds
Started Jun 04 01:44:10 PM PDT 24
Finished Jun 04 01:44:11 PM PDT 24
Peak memory 215380 kb
Host smart-1cecd240-3259-4942-b3be-87f79dadcba8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463044363 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1463044363
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1220460460
Short name T689
Test name
Test status
Simulation time 160957484 ps
CPU time 1.16 seconds
Started Jun 04 01:44:07 PM PDT 24
Finished Jun 04 01:44:09 PM PDT 24
Peak memory 216684 kb
Host smart-a846efa9-a8c7-407e-808a-ec631b9f46aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220460460 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1220460460
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1962324432
Short name T810
Test name
Test status
Simulation time 24184332 ps
CPU time 1.04 seconds
Started Jun 04 01:44:08 PM PDT 24
Finished Jun 04 01:44:10 PM PDT 24
Peak memory 223444 kb
Host smart-94e72881-87ab-4b5e-a834-fa931e8f2c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962324432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1962324432
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2066985797
Short name T150
Test name
Test status
Simulation time 68620492 ps
CPU time 1.76 seconds
Started Jun 04 01:44:09 PM PDT 24
Finished Jun 04 01:44:12 PM PDT 24
Peak memory 218128 kb
Host smart-1d75ae96-ac58-4500-9350-ca3f893da1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066985797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2066985797
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1589417002
Short name T837
Test name
Test status
Simulation time 22203364 ps
CPU time 1.2 seconds
Started Jun 04 01:44:09 PM PDT 24
Finished Jun 04 01:44:11 PM PDT 24
Peak memory 223660 kb
Host smart-34b44cc5-f0c1-4169-865d-6747036844b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589417002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1589417002
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.879052848
Short name T568
Test name
Test status
Simulation time 16655577 ps
CPU time 1.01 seconds
Started Jun 04 01:44:08 PM PDT 24
Finished Jun 04 01:44:10 PM PDT 24
Peak memory 215040 kb
Host smart-18337c6a-8f44-4e37-b4b9-23e1e8ff4c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879052848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.879052848
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2939570227
Short name T422
Test name
Test status
Simulation time 123624543 ps
CPU time 3.02 seconds
Started Jun 04 01:44:06 PM PDT 24
Finished Jun 04 01:44:11 PM PDT 24
Peak memory 215128 kb
Host smart-21bbaec0-d29d-4936-8900-f503fbc42ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939570227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2939570227
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4038558359
Short name T565
Test name
Test status
Simulation time 49466302937 ps
CPU time 1048.47 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 02:01:35 PM PDT 24
Peak memory 220140 kb
Host smart-d048f1da-8ad0-40cc-9f1b-aea5ea00f8e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038558359 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4038558359
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2121925331
Short name T729
Test name
Test status
Simulation time 62414297 ps
CPU time 1.13 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:26 PM PDT 24
Peak memory 216744 kb
Host smart-bdc0fbfe-1eba-4e91-a087-6d82f672b7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121925331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2121925331
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.2034468250
Short name T551
Test name
Test status
Simulation time 52504337 ps
CPU time 1.21 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 216820 kb
Host smart-950d122a-f4c9-4b12-a7a7-1d08513a97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034468250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.2034468250
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.163971469
Short name T516
Test name
Test status
Simulation time 89239065 ps
CPU time 2.28 seconds
Started Jun 04 01:45:18 PM PDT 24
Finished Jun 04 01:45:21 PM PDT 24
Peak memory 218164 kb
Host smart-4c049c7f-22cb-4ab9-9cfd-a80c3c8927e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163971469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.163971469
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.639263116
Short name T372
Test name
Test status
Simulation time 66895057 ps
CPU time 1.07 seconds
Started Jun 04 01:45:23 PM PDT 24
Finished Jun 04 01:45:25 PM PDT 24
Peak memory 216816 kb
Host smart-f4145dda-2a99-4c96-a58e-f785211d1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639263116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.639263116
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2267089398
Short name T616
Test name
Test status
Simulation time 66661911 ps
CPU time 1.04 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216696 kb
Host smart-874c8db1-7a0d-4aae-9ffd-5dbc75f10f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267089398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2267089398
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3119303378
Short name T643
Test name
Test status
Simulation time 186241884 ps
CPU time 1.18 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216840 kb
Host smart-c59a315e-8fc8-4693-aaa9-324fa398ff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119303378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3119303378
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.592600388
Short name T120
Test name
Test status
Simulation time 70699743 ps
CPU time 1.97 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 218184 kb
Host smart-1ad2d1a0-7f4b-4cc1-b534-d8ee07fac2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592600388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.592600388
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3030076071
Short name T162
Test name
Test status
Simulation time 135798549 ps
CPU time 2.91 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 217956 kb
Host smart-abf4c381-acf9-474d-a2ea-54d4fe3ae047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030076071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3030076071
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1516589696
Short name T825
Test name
Test status
Simulation time 46468670 ps
CPU time 1.86 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 218092 kb
Host smart-7a4e6feb-09a9-4495-b6b5-b27fc4bcee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516589696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1516589696
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1659826599
Short name T152
Test name
Test status
Simulation time 62011569 ps
CPU time 1.22 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 218064 kb
Host smart-e5935e6d-385b-4dee-9ab3-871fffd841a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659826599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1659826599
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.3352481388
Short name T543
Test name
Test status
Simulation time 20076094 ps
CPU time 1.03 seconds
Started Jun 04 01:44:13 PM PDT 24
Finished Jun 04 01:44:16 PM PDT 24
Peak memory 214560 kb
Host smart-66a1f778-02a3-497f-8670-7887fc8ecac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352481388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3352481388
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3273760410
Short name T85
Test name
Test status
Simulation time 40456155 ps
CPU time 0.87 seconds
Started Jun 04 01:44:24 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 216196 kb
Host smart-78155b0c-d04f-4411-a7f3-8fbcd538e992
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273760410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3273760410
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.1313330551
Short name T598
Test name
Test status
Simulation time 43237500 ps
CPU time 0.88 seconds
Started Jun 04 01:44:13 PM PDT 24
Finished Jun 04 01:44:15 PM PDT 24
Peak memory 217864 kb
Host smart-51d62198-ce54-4302-8e83-3c4b136984ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313330551 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1313330551
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2953725174
Short name T584
Test name
Test status
Simulation time 30763053 ps
CPU time 1.3 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 216800 kb
Host smart-b6c3d78d-3b24-47cd-aa3a-f27b0c4b79d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953725174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2953725174
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.1128482245
Short name T773
Test name
Test status
Simulation time 29656488 ps
CPU time 0.89 seconds
Started Jun 04 01:44:07 PM PDT 24
Finished Jun 04 01:44:09 PM PDT 24
Peak memory 215412 kb
Host smart-cb9017d4-f2fa-4cc3-9106-5c5c242a3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128482245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1128482245
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1997979169
Short name T510
Test name
Test status
Simulation time 23078197 ps
CPU time 0.9 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:08 PM PDT 24
Peak memory 206676 kb
Host smart-274fbdce-fbbe-4f30-870b-b20bdd44591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997979169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1997979169
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3164264961
Short name T756
Test name
Test status
Simulation time 421903282 ps
CPU time 2.74 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 01:44:09 PM PDT 24
Peak memory 206880 kb
Host smart-f8d97210-8353-470e-9d45-f22e708dbb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164264961 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3164264961
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1350628250
Short name T655
Test name
Test status
Simulation time 46291474419 ps
CPU time 1031.95 seconds
Started Jun 04 01:44:05 PM PDT 24
Finished Jun 04 02:01:19 PM PDT 24
Peak memory 223368 kb
Host smart-832a004d-64b8-4568-a455-042c109518e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350628250 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1350628250
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3089508116
Short name T126
Test name
Test status
Simulation time 202475749 ps
CPU time 1.34 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 216632 kb
Host smart-16463c3d-2295-41aa-9737-f63388e62786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089508116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3089508116
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1040888248
Short name T331
Test name
Test status
Simulation time 42601430 ps
CPU time 1.49 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 217980 kb
Host smart-1cfa19db-e6df-4bf2-868e-9a7c9bcc3556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040888248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1040888248
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2862087265
Short name T512
Test name
Test status
Simulation time 55627742 ps
CPU time 0.97 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216768 kb
Host smart-0915f6ee-36ff-4a72-9b3e-e6fae05ba7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862087265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2862087265
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3870764766
Short name T273
Test name
Test status
Simulation time 33043639 ps
CPU time 1.36 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 216812 kb
Host smart-9aae53d7-b5c5-4b1b-b88f-78e1c6a0f037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870764766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3870764766
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.98862305
Short name T521
Test name
Test status
Simulation time 44065221 ps
CPU time 1.42 seconds
Started Jun 04 01:45:32 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 219484 kb
Host smart-4c21e2d3-f22c-46b3-87c2-517431fffd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98862305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.98862305
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.883136206
Short name T708
Test name
Test status
Simulation time 23878530 ps
CPU time 1.25 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 217852 kb
Host smart-c08131c4-b954-4947-aaa6-c33adbeee0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883136206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.883136206
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.764933432
Short name T626
Test name
Test status
Simulation time 29683118 ps
CPU time 1.31 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 219240 kb
Host smart-0f88bce7-eaea-42b6-a1f5-fca852b33b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764933432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.764933432
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.899384703
Short name T744
Test name
Test status
Simulation time 45459507 ps
CPU time 1.2 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 01:44:18 PM PDT 24
Peak memory 215372 kb
Host smart-05d06b2c-17cf-40e2-9e74-98afe488ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899384703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.899384703
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3440823867
Short name T319
Test name
Test status
Simulation time 43024298 ps
CPU time 0.9 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 214500 kb
Host smart-4bf36ed6-0d8e-4ea8-93a5-caccdbbb84ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440823867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3440823867
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_err.2687152415
Short name T65
Test name
Test status
Simulation time 35305390 ps
CPU time 1.02 seconds
Started Jun 04 01:44:17 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 223356 kb
Host smart-e114a7e9-fa2b-4bf4-8cca-66f99466baf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687152415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2687152415
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3608522729
Short name T783
Test name
Test status
Simulation time 43169672 ps
CPU time 1.57 seconds
Started Jun 04 01:44:12 PM PDT 24
Finished Jun 04 01:44:15 PM PDT 24
Peak memory 219344 kb
Host smart-5e525e88-302f-470d-b35e-8fd162d57a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608522729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3608522729
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.338646227
Short name T546
Test name
Test status
Simulation time 21577294 ps
CPU time 1.16 seconds
Started Jun 04 01:44:17 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 215504 kb
Host smart-dbb1f1b6-7938-4e78-b52e-751a65ea9375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338646227 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.338646227
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.18692720
Short name T528
Test name
Test status
Simulation time 19505758 ps
CPU time 0.96 seconds
Started Jun 04 01:44:17 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 214992 kb
Host smart-ea986f90-0197-45d2-95d9-94bccb96c611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18692720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.18692720
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3150353708
Short name T326
Test name
Test status
Simulation time 587205250 ps
CPU time 3.6 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:20 PM PDT 24
Peak memory 214956 kb
Host smart-94ea9594-5f15-46cd-97f7-39e3f8afb38e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150353708 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3150353708
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3060527592
Short name T208
Test name
Test status
Simulation time 87219594137 ps
CPU time 2228.69 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 02:21:25 PM PDT 24
Peak memory 229872 kb
Host smart-10382473-3be2-4e9f-897f-504475eb9eb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060527592 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3060527592
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3063852430
Short name T306
Test name
Test status
Simulation time 62240771 ps
CPU time 1.03 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 216652 kb
Host smart-62295695-00d5-4b12-9396-2750ce75d5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063852430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3063852430
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.376582687
Short name T759
Test name
Test status
Simulation time 28236950 ps
CPU time 1.15 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:22 PM PDT 24
Peak memory 218032 kb
Host smart-e102d77f-20d3-4591-ad46-9ddcb056dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376582687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.376582687
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.897837438
Short name T423
Test name
Test status
Simulation time 37272193 ps
CPU time 1.1 seconds
Started Jun 04 01:45:18 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 216668 kb
Host smart-d69216bb-3144-43b9-bb07-9f076a85fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897837438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.897837438
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1458251617
Short name T639
Test name
Test status
Simulation time 34832356 ps
CPU time 1.62 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 216788 kb
Host smart-c524336d-9e50-44b9-bac3-6510df8eb57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458251617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1458251617
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.607567234
Short name T634
Test name
Test status
Simulation time 25946562 ps
CPU time 1.27 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 216612 kb
Host smart-2d3015db-1384-4348-8565-14c1267d26e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607567234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.607567234
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2213642913
Short name T815
Test name
Test status
Simulation time 70018955 ps
CPU time 1.52 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218056 kb
Host smart-a5c0f5b6-b7d2-482a-afde-303cac6e44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213642913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2213642913
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.4215201732
Short name T571
Test name
Test status
Simulation time 37721518 ps
CPU time 1.25 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 218168 kb
Host smart-0eab0aa0-37da-4c1b-9c77-ee8f6961aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215201732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.4215201732
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2003773211
Short name T352
Test name
Test status
Simulation time 41791138 ps
CPU time 1.28 seconds
Started Jun 04 01:45:23 PM PDT 24
Finished Jun 04 01:45:26 PM PDT 24
Peak memory 217884 kb
Host smart-b6e59cfc-360b-4b8a-8735-b582a9e3e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003773211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2003773211
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2339211647
Short name T292
Test name
Test status
Simulation time 43199463 ps
CPU time 1.52 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 218044 kb
Host smart-bf97da6e-188f-4765-9eeb-437a744e8d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339211647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2339211647
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3004883482
Short name T572
Test name
Test status
Simulation time 90410948 ps
CPU time 1.21 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 216580 kb
Host smart-57769922-ab33-4167-b59a-5aeb008e3984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004883482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3004883482
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.2997499484
Short name T662
Test name
Test status
Simulation time 63120565 ps
CPU time 0.85 seconds
Started Jun 04 01:44:12 PM PDT 24
Finished Jun 04 01:44:13 PM PDT 24
Peak memory 206572 kb
Host smart-33e91d14-d798-41fc-908d-45c4471ec29a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997499484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2997499484
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2197269386
Short name T433
Test name
Test status
Simulation time 37336404 ps
CPU time 0.87 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 215672 kb
Host smart-70c70792-99be-48b5-9842-d681260f0087
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197269386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2197269386
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3988049004
Short name T59
Test name
Test status
Simulation time 32201269 ps
CPU time 1.18 seconds
Started Jun 04 01:44:16 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 216908 kb
Host smart-421557ec-9434-4c3b-a2f9-ee208fc7b3d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988049004 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3988049004
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.662640819
Short name T91
Test name
Test status
Simulation time 23508709 ps
CPU time 1.04 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 223472 kb
Host smart-5bc72ede-e47a-42fb-a4b5-0992fc72e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662640819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.662640819
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.712959828
Short name T760
Test name
Test status
Simulation time 42576141 ps
CPU time 1.15 seconds
Started Jun 04 01:44:18 PM PDT 24
Finished Jun 04 01:44:20 PM PDT 24
Peak memory 219212 kb
Host smart-fbac361c-1afc-4a1a-b3e9-9f934a5e4260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712959828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.712959828
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.148456958
Short name T725
Test name
Test status
Simulation time 46176777 ps
CPU time 0.87 seconds
Started Jun 04 01:44:13 PM PDT 24
Finished Jun 04 01:44:16 PM PDT 24
Peak memory 215276 kb
Host smart-dcda5c39-5cc5-48c9-b626-b9d0f1e6464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148456958 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.148456958
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1604409191
Short name T552
Test name
Test status
Simulation time 19527318 ps
CPU time 1.03 seconds
Started Jun 04 01:44:25 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 214996 kb
Host smart-c3a93cdc-5e7e-46ba-9c8f-fced7d1644bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604409191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1604409191
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4141880449
Short name T771
Test name
Test status
Simulation time 492225266 ps
CPU time 2.94 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 218084 kb
Host smart-977939fd-dd60-413c-b857-1db4b1703d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141880449 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4141880449
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3234168446
Short name T619
Test name
Test status
Simulation time 15429685197 ps
CPU time 342.83 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 01:50:00 PM PDT 24
Peak memory 222408 kb
Host smart-176e9313-0c14-4f0c-bbea-45b55ad90023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234168446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3234168446
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.edn_genbits.612246872
Short name T293
Test name
Test status
Simulation time 46208587 ps
CPU time 1.58 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 216968 kb
Host smart-a6b666d1-5c84-417c-b3ce-54d068e64ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612246872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.612246872
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3884294278
Short name T562
Test name
Test status
Simulation time 71150185 ps
CPU time 1.82 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 219780 kb
Host smart-1260da36-2707-49e0-a9bc-2936788fff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884294278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3884294278
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1955666302
Short name T624
Test name
Test status
Simulation time 76243124 ps
CPU time 1.37 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 218260 kb
Host smart-d3656c1d-eccb-406e-9d52-7419c73cb8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955666302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1955666302
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1848458105
Short name T358
Test name
Test status
Simulation time 209092377 ps
CPU time 1.82 seconds
Started Jun 04 01:45:32 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 218380 kb
Host smart-aac92174-219f-4e8e-b4de-6d03ca2d4f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848458105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1848458105
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1721503028
Short name T503
Test name
Test status
Simulation time 67518343 ps
CPU time 1.93 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 218068 kb
Host smart-fca21848-0b69-4d0b-9bbf-04b8abc006d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721503028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1721503028
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1002569741
Short name T242
Test name
Test status
Simulation time 78729721 ps
CPU time 1.29 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 216712 kb
Host smart-052035cc-311a-4a87-a3cf-a6e1cd0c4f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002569741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1002569741
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3139001151
Short name T410
Test name
Test status
Simulation time 152190968 ps
CPU time 3.35 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 218444 kb
Host smart-0aeff02c-d9c2-42ac-a53c-bcbb7f22d0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139001151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3139001151
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3416959874
Short name T171
Test name
Test status
Simulation time 77922523 ps
CPU time 1.17 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 215412 kb
Host smart-a0267bdb-5005-4c2a-9520-0318570600c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416959874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3416959874
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2411012205
Short name T321
Test name
Test status
Simulation time 12708672 ps
CPU time 0.9 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 214512 kb
Host smart-bc2e39dc-ca67-4a89-980c-6335399f5a6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411012205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2411012205
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.1410117964
Short name T68
Test name
Test status
Simulation time 11349498 ps
CPU time 0.89 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 216180 kb
Host smart-1d02694c-475f-471d-8e01-8724ccd87b4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410117964 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1410117964
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.387017377
Short name T694
Test name
Test status
Simulation time 34346089 ps
CPU time 1.27 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 216796 kb
Host smart-ee554236-ce52-4db4-b02d-d2ccd24edcb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387017377 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_di
sable_auto_req_mode.387017377
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.202269820
Short name T800
Test name
Test status
Simulation time 19787859 ps
CPU time 1.09 seconds
Started Jun 04 01:44:20 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 218936 kb
Host smart-ca6bfba9-8e09-48cb-a1c1-655eb470f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202269820 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.202269820
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.775789603
Short name T243
Test name
Test status
Simulation time 55053933 ps
CPU time 1.38 seconds
Started Jun 04 01:44:19 PM PDT 24
Finished Jun 04 01:44:22 PM PDT 24
Peak memory 219512 kb
Host smart-8c4c90c7-b42f-4889-85a4-4260b5aecbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775789603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.775789603
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2073537679
Short name T714
Test name
Test status
Simulation time 31765425 ps
CPU time 0.91 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 215480 kb
Host smart-0d8b3ed5-edc6-4c4e-94bc-6221a7328fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073537679 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2073537679
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1426433917
Short name T416
Test name
Test status
Simulation time 27301664 ps
CPU time 1.01 seconds
Started Jun 04 01:44:14 PM PDT 24
Finished Jun 04 01:44:17 PM PDT 24
Peak memory 214980 kb
Host smart-a33b0236-b77b-4d91-ba71-b2a717fb6f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426433917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1426433917
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.239009153
Short name T371
Test name
Test status
Simulation time 93060660 ps
CPU time 1.63 seconds
Started Jun 04 01:44:16 PM PDT 24
Finished Jun 04 01:44:19 PM PDT 24
Peak memory 216472 kb
Host smart-2bac2b27-3480-459e-9c0e-68ca7a5c3f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239009153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.239009153
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.4001252009
Short name T116
Test name
Test status
Simulation time 261069669275 ps
CPU time 1323.01 seconds
Started Jun 04 01:44:15 PM PDT 24
Finished Jun 04 02:06:20 PM PDT 24
Peak memory 223408 kb
Host smart-ecff65c4-bec3-42d6-a4cc-0aed996ca3ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001252009 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4001252009
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.338214952
Short name T159
Test name
Test status
Simulation time 78173273 ps
CPU time 1.4 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 219540 kb
Host smart-2e1408bd-dd71-440d-a7d2-36feb7c01dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338214952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.338214952
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3057730862
Short name T405
Test name
Test status
Simulation time 256819571 ps
CPU time 3.83 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 216948 kb
Host smart-4051a70b-8d4d-40ca-8dab-569aa1eec1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057730862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3057730862
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.471343890
Short name T757
Test name
Test status
Simulation time 69293371 ps
CPU time 1.4 seconds
Started Jun 04 01:45:27 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 219308 kb
Host smart-41afd003-8135-4ece-9d7e-e2901ba14cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471343890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.471343890
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2042175968
Short name T646
Test name
Test status
Simulation time 39864398 ps
CPU time 1.15 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216768 kb
Host smart-b256a0df-2bbf-4681-9243-5c8106de3932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042175968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2042175968
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.739481505
Short name T460
Test name
Test status
Simulation time 47998877 ps
CPU time 1.61 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 217928 kb
Host smart-001ad739-3915-40d4-8588-1be8eaebde81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739481505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.739481505
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1595416623
Short name T135
Test name
Test status
Simulation time 42289257 ps
CPU time 1.2 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 219212 kb
Host smart-dc8c1ab2-ce4f-4311-b768-ea97a9eb2630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595416623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1595416623
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2266546033
Short name T97
Test name
Test status
Simulation time 80212507 ps
CPU time 1.22 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 215412 kb
Host smart-f3ffedfa-7cd2-4fcd-9104-9e4ed4d793ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266546033 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2266546033
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2909345668
Short name T485
Test name
Test status
Simulation time 18904486 ps
CPU time 0.96 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 206328 kb
Host smart-cc40e22e-ff8a-47c1-9ab1-bc05812588d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909345668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2909345668
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.902931953
Short name T817
Test name
Test status
Simulation time 18736817 ps
CPU time 0.86 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 215136 kb
Host smart-2adb7645-39dd-42ff-8306-4ccefb59df5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902931953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.902931953
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2743491649
Short name T777
Test name
Test status
Simulation time 34808139 ps
CPU time 1.25 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 216636 kb
Host smart-c339e85c-faa6-4ae1-b0f8-6975081b57d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743491649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2743491649
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1174321295
Short name T704
Test name
Test status
Simulation time 23631506 ps
CPU time 1.1 seconds
Started Jun 04 01:44:20 PM PDT 24
Finished Jun 04 01:44:23 PM PDT 24
Peak memory 218192 kb
Host smart-e8f19d60-b427-40b6-ab15-b052a31b8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174321295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1174321295
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2240805452
Short name T559
Test name
Test status
Simulation time 54201418 ps
CPU time 1.09 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 216652 kb
Host smart-5c71f20e-2484-4daf-b398-54a37359cd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240805452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2240805452
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3301706300
Short name T129
Test name
Test status
Simulation time 22425336 ps
CPU time 1.23 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 223564 kb
Host smart-cfbea96a-f032-4613-9260-e9a923bd86e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301706300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3301706300
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3509896626
Short name T434
Test name
Test status
Simulation time 31130074 ps
CPU time 0.97 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 215004 kb
Host smart-6a516b86-6c39-4440-b7b8-b28f33e559a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509896626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3509896626
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1126818895
Short name T677
Test name
Test status
Simulation time 475246676 ps
CPU time 3.3 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:28 PM PDT 24
Peak memory 216772 kb
Host smart-8e68aaa4-2ae4-4739-a032-e610255af218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126818895 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1126818895
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3604224193
Short name T429
Test name
Test status
Simulation time 72903148657 ps
CPU time 896.32 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:59:21 PM PDT 24
Peak memory 223416 kb
Host smart-03bd3d51-7243-4032-920f-4475608f410f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604224193 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3604224193
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.123114194
Short name T658
Test name
Test status
Simulation time 39042038 ps
CPU time 1.12 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 216712 kb
Host smart-449110ca-4e87-4f5c-8bac-ffa4b9fa24ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123114194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.123114194
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.447002842
Short name T141
Test name
Test status
Simulation time 74679523 ps
CPU time 1.43 seconds
Started Jun 04 01:45:27 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 217884 kb
Host smart-05a06ae7-19f9-4f77-876e-4aa22c57d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447002842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.447002842
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3308970494
Short name T665
Test name
Test status
Simulation time 46992159 ps
CPU time 1.15 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 216720 kb
Host smart-1737d156-68ec-4aea-a9f4-8a04de81badc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308970494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3308970494
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.610035779
Short name T329
Test name
Test status
Simulation time 55469214 ps
CPU time 1.63 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218092 kb
Host smart-9c56351e-a5a8-4a95-9de2-2b47e04b12de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610035779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.610035779
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1724118976
Short name T294
Test name
Test status
Simulation time 77200560 ps
CPU time 1.07 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 216712 kb
Host smart-d865d0b1-ba1b-479e-8185-580fedd89be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724118976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1724118976
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1515131260
Short name T723
Test name
Test status
Simulation time 155597632 ps
CPU time 1.62 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 218472 kb
Host smart-3c7814e2-39c8-414c-9586-7c1c5cb1be99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515131260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1515131260
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.603660916
Short name T360
Test name
Test status
Simulation time 20610795 ps
CPU time 1.1 seconds
Started Jun 04 01:45:32 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 217952 kb
Host smart-ebd2d3ea-6e99-43cf-ac7e-393c3e6a3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603660916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.603660916
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.385781229
Short name T501
Test name
Test status
Simulation time 58199736 ps
CPU time 1.03 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 216680 kb
Host smart-86038cdb-51f0-4844-89eb-ce67123d6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385781229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.385781229
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3443811690
Short name T688
Test name
Test status
Simulation time 145295204 ps
CPU time 2.97 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 219216 kb
Host smart-9409aa58-47f7-423a-92f4-414533c67920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443811690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3443811690
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2291641203
Short name T751
Test name
Test status
Simulation time 22929976 ps
CPU time 0.88 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 214452 kb
Host smart-2beed8de-8dad-4922-a909-4065933a38e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291641203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2291641203
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.819301536
Short name T177
Test name
Test status
Simulation time 27989910 ps
CPU time 0.84 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 216076 kb
Host smart-75363be0-d1cd-4e20-baaa-035e1823c8ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819301536 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.819301536
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3383853196
Short name T58
Test name
Test status
Simulation time 40722618 ps
CPU time 1.35 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 216568 kb
Host smart-37815ba9-8983-4ea3-9286-41a213b2c91c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383853196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3383853196
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4260457883
Short name T43
Test name
Test status
Simulation time 59043717 ps
CPU time 1.14 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 229128 kb
Host smart-c953bbce-c25f-47ea-86bc-3129777e5290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260457883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4260457883
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.323655736
Short name T328
Test name
Test status
Simulation time 70456516 ps
CPU time 1.4 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 219360 kb
Host smart-d218638e-08a5-4f81-afd2-03917a1b82d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323655736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.323655736
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.3255466350
Short name T330
Test name
Test status
Simulation time 15878257 ps
CPU time 1.02 seconds
Started Jun 04 01:44:24 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 214976 kb
Host smart-34f0f989-25ae-4447-a965-fc6db6214ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255466350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3255466350
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3546145833
Short name T715
Test name
Test status
Simulation time 549611082 ps
CPU time 3.13 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 215040 kb
Host smart-56ed1644-dc99-4a4f-8e2f-077111906371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546145833 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3546145833
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1665143580
Short name T200
Test name
Test status
Simulation time 314311552869 ps
CPU time 2509.47 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 02:26:14 PM PDT 24
Peak memory 227752 kb
Host smart-9b926ea9-5525-4e8c-96bf-73aa1e490313
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665143580 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1665143580
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.422446142
Short name T456
Test name
Test status
Simulation time 144906950 ps
CPU time 1.85 seconds
Started Jun 04 01:45:46 PM PDT 24
Finished Jun 04 01:45:49 PM PDT 24
Peak memory 218144 kb
Host smart-dc2a097e-19ba-4ab7-8d81-03f0d4828fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422446142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.422446142
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.221822022
Short name T566
Test name
Test status
Simulation time 29322596 ps
CPU time 1.35 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 216676 kb
Host smart-5a246f79-d527-49c5-b840-de5c97ae8293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221822022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.221822022
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.233661972
Short name T424
Test name
Test status
Simulation time 100604831 ps
CPU time 2.33 seconds
Started Jun 04 01:45:32 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218004 kb
Host smart-76cf4fbd-b8c1-44b6-8fbb-86b11ce4dc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233661972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.233661972
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.25806797
Short name T138
Test name
Test status
Simulation time 42620992 ps
CPU time 1.37 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217900 kb
Host smart-1425c2e9-11d2-4962-8b9e-8538846add2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25806797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.25806797
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.4249630210
Short name T384
Test name
Test status
Simulation time 77167028 ps
CPU time 1.45 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 217992 kb
Host smart-543629e2-ebd7-4cf3-9eb4-029832e19cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249630210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.4249630210
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1798936432
Short name T474
Test name
Test status
Simulation time 199143281 ps
CPU time 1.45 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217984 kb
Host smart-748f90af-c71a-4608-9306-e2db9e3aefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798936432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1798936432
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.4033748062
Short name T315
Test name
Test status
Simulation time 65331480 ps
CPU time 1.15 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 216844 kb
Host smart-bc8a3b2f-0ddc-43af-982a-f16967bc417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033748062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.4033748062
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3612455005
Short name T803
Test name
Test status
Simulation time 54577536 ps
CPU time 1.25 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 217936 kb
Host smart-629499b3-1925-4d4a-b6c0-355f70efb980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612455005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3612455005
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3182689769
Short name T297
Test name
Test status
Simulation time 59073681 ps
CPU time 1.26 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 219456 kb
Host smart-a200def7-c91d-4499-9df0-f9f9953d100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182689769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3182689769
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.735593490
Short name T419
Test name
Test status
Simulation time 51574532 ps
CPU time 1.88 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 217996 kb
Host smart-dce3944c-059b-4a55-ac41-b86b7e7b2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735593490 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.735593490
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1047334673
Short name T746
Test name
Test status
Simulation time 69566892 ps
CPU time 1.12 seconds
Started Jun 04 01:44:20 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 215400 kb
Host smart-8b303def-fdd2-472f-924a-7d0914d03206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047334673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1047334673
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.301163495
Short name T620
Test name
Test status
Simulation time 14343847 ps
CPU time 0.96 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 206420 kb
Host smart-e0a843ab-f196-4211-9c6a-5c75e84a0c55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301163495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.301163495
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3207961294
Short name T74
Test name
Test status
Simulation time 16046910 ps
CPU time 0.9 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 216088 kb
Host smart-7473cb9f-2275-4922-84f0-733e3a720a56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207961294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3207961294
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.586375922
Short name T497
Test name
Test status
Simulation time 225533114 ps
CPU time 1.2 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 218164 kb
Host smart-63978581-412b-45eb-8f92-46a42221b978
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586375922 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.586375922
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3413200382
Short name T45
Test name
Test status
Simulation time 50215309 ps
CPU time 1.12 seconds
Started Jun 04 01:44:19 PM PDT 24
Finished Jun 04 01:44:22 PM PDT 24
Peak memory 229044 kb
Host smart-ee38215b-1246-4656-960f-37602b68b379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413200382 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3413200382
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3496382443
Short name T287
Test name
Test status
Simulation time 33627880 ps
CPU time 1.38 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:27 PM PDT 24
Peak memory 215000 kb
Host smart-6e910bda-1612-4367-b283-61705c7adbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496382443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3496382443
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.651385632
Short name T678
Test name
Test status
Simulation time 19492046 ps
CPU time 1.05 seconds
Started Jun 04 01:44:20 PM PDT 24
Finished Jun 04 01:44:23 PM PDT 24
Peak memory 215460 kb
Host smart-9f066c5e-95d1-4aad-b224-b3e4d00d4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651385632 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.651385632
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3714098170
Short name T534
Test name
Test status
Simulation time 26439720 ps
CPU time 0.93 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:24 PM PDT 24
Peak memory 206808 kb
Host smart-b1b2bbf1-19ae-46b2-be03-7e3e3b732efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714098170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3714098170
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.4197682329
Short name T381
Test name
Test status
Simulation time 478349973 ps
CPU time 3.02 seconds
Started Jun 04 01:44:20 PM PDT 24
Finished Jun 04 01:44:25 PM PDT 24
Peak memory 215032 kb
Host smart-310910eb-dd07-4d26-9843-f4b0d9cbf2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197682329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.4197682329
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2987875546
Short name T198
Test name
Test status
Simulation time 51794518066 ps
CPU time 1183.64 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 02:04:09 PM PDT 24
Peak memory 223412 kb
Host smart-8b0d0a0e-4661-48ae-a677-8c9f776ef0e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987875546 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2987875546
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.316489593
Short name T145
Test name
Test status
Simulation time 105610158 ps
CPU time 1.45 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 218292 kb
Host smart-053d6019-68a0-4b99-9ead-5030d6e4722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316489593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.316489593
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3484005404
Short name T716
Test name
Test status
Simulation time 87595620 ps
CPU time 1.55 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 218184 kb
Host smart-bbbe4daf-1c95-43b8-9f55-4d3c8e156463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484005404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3484005404
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2055246534
Short name T418
Test name
Test status
Simulation time 115206131 ps
CPU time 1.64 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 216952 kb
Host smart-c338a46f-9a0d-47cf-8852-615f514a9ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055246534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2055246534
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3786726316
Short name T151
Test name
Test status
Simulation time 149328941 ps
CPU time 1.64 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 218088 kb
Host smart-76908c1b-0c35-43e0-9761-09e36574460e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786726316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3786726316
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2259522253
Short name T809
Test name
Test status
Simulation time 33655114 ps
CPU time 1.51 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216820 kb
Host smart-7125ed90-909c-44e2-8eb8-27716403d232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259522253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2259522253
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1208260879
Short name T635
Test name
Test status
Simulation time 31399084 ps
CPU time 1.35 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 219348 kb
Host smart-8806c131-fb0e-497c-8658-2b2bc8e0a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208260879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1208260879
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2910307941
Short name T707
Test name
Test status
Simulation time 92806904 ps
CPU time 1.9 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217996 kb
Host smart-03c9826e-f98f-4218-90d4-1b6d6e385dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910307941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2910307941
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4182723583
Short name T161
Test name
Test status
Simulation time 25969126 ps
CPU time 1.09 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:25 PM PDT 24
Peak memory 216824 kb
Host smart-dd8545e6-4eed-4369-9501-042d07729966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182723583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4182723583
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2788017578
Short name T792
Test name
Test status
Simulation time 47794228 ps
CPU time 1.64 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 218004 kb
Host smart-9d15efb3-c2df-42e7-b531-22fa2a397c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788017578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2788017578
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.310993999
Short name T527
Test name
Test status
Simulation time 288650903 ps
CPU time 3.89 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 219744 kb
Host smart-665ceb53-49da-46e3-8924-766925851f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310993999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.310993999
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.3024064794
Short name T490
Test name
Test status
Simulation time 29507521 ps
CPU time 1.3 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:43:48 PM PDT 24
Peak memory 215340 kb
Host smart-43dbec92-5c88-4bad-81e0-0c9c381d2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024064794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3024064794
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3396063967
Short name T379
Test name
Test status
Simulation time 40528860 ps
CPU time 0.86 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 214484 kb
Host smart-2953a9aa-9057-40d2-a2c4-3ee515729533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396063967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3396063967
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1899070318
Short name T618
Test name
Test status
Simulation time 12441719 ps
CPU time 0.93 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:51 PM PDT 24
Peak memory 215356 kb
Host smart-8e9ceb5d-b0f8-488a-9d6c-3728649ce5ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899070318 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1899070318
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.21752916
Short name T77
Test name
Test status
Simulation time 18869221 ps
CPU time 1.03 seconds
Started Jun 04 01:43:42 PM PDT 24
Finished Jun 04 01:43:44 PM PDT 24
Peak memory 217944 kb
Host smart-2b717eff-e28d-4a29-9e38-04abbe95df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21752916 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.21752916
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.343826116
Short name T446
Test name
Test status
Simulation time 46226550 ps
CPU time 1.17 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 217836 kb
Host smart-251d6974-6e85-4a40-ae03-24760547cd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343826116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.343826116
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.837393091
Short name T764
Test name
Test status
Simulation time 30594494 ps
CPU time 0.95 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 206808 kb
Host smart-955c4324-4822-425b-9114-e308cf93d4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837393091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.837393091
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.958783424
Short name T15
Test name
Test status
Simulation time 1897013357 ps
CPU time 5.44 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:49 PM PDT 24
Peak memory 241580 kb
Host smart-b20506b3-d812-44ac-b482-9d409a63e098
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958783424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.958783424
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.215024633
Short name T428
Test name
Test status
Simulation time 44300451 ps
CPU time 0.95 seconds
Started Jun 04 01:43:49 PM PDT 24
Finished Jun 04 01:43:51 PM PDT 24
Peak memory 215004 kb
Host smart-63d8e4b0-edb9-4720-82ba-018f1a095399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215024633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.215024633
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.4189964657
Short name T175
Test name
Test status
Simulation time 209271394 ps
CPU time 4.03 seconds
Started Jun 04 01:43:42 PM PDT 24
Finished Jun 04 01:43:47 PM PDT 24
Peak memory 216516 kb
Host smart-6faf866b-24f2-47a4-b5f1-498701be72ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189964657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.4189964657
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.490498214
Short name T415
Test name
Test status
Simulation time 53790015145 ps
CPU time 967.6 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:59:54 PM PDT 24
Peak memory 218380 kb
Host smart-ac93bbd8-6ee1-4afe-bea2-1ee5e9cb6a0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490498214 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.490498214
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1528005024
Short name T533
Test name
Test status
Simulation time 34469117 ps
CPU time 0.99 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:30 PM PDT 24
Peak memory 214892 kb
Host smart-49019016-aa93-4f7e-b4cb-5c19ccf6de4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528005024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1528005024
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2642098056
Short name T42
Test name
Test status
Simulation time 33660771 ps
CPU time 1.23 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 216796 kb
Host smart-84c61a58-b05b-4b6b-88d8-3f9ecbb4c1a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642098056 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2642098056
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2554788586
Short name T87
Test name
Test status
Simulation time 54620384 ps
CPU time 0.87 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:29 PM PDT 24
Peak memory 217856 kb
Host smart-73a9f535-9ade-4569-af8d-0ef1da0096bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554788586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2554788586
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1789710923
Short name T383
Test name
Test status
Simulation time 28637711 ps
CPU time 1.19 seconds
Started Jun 04 01:44:22 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 216616 kb
Host smart-b23c11aa-4a46-48ad-bf42-cf939e4be264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789710923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1789710923
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3581734036
Short name T174
Test name
Test status
Simulation time 26779406 ps
CPU time 0.97 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 215348 kb
Host smart-e48c4205-43be-4e2a-bbf7-58506d166b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581734036 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3581734036
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.434364099
Short name T536
Test name
Test status
Simulation time 28669065 ps
CPU time 0.96 seconds
Started Jun 04 01:44:23 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 215000 kb
Host smart-a7470308-2708-4dcf-a22d-865b2a00c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434364099 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.434364099
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2097098175
Short name T302
Test name
Test status
Simulation time 294904846 ps
CPU time 2.09 seconds
Started Jun 04 01:44:21 PM PDT 24
Finished Jun 04 01:44:26 PM PDT 24
Peak memory 215060 kb
Host smart-7bc47fba-6dca-4f88-98dd-ec279c39b1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097098175 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2097098175
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3444648260
Short name T334
Test name
Test status
Simulation time 108459084807 ps
CPU time 697.49 seconds
Started Jun 04 01:44:24 PM PDT 24
Finished Jun 04 01:56:03 PM PDT 24
Peak memory 220364 kb
Host smart-cf1c85fb-4b26-4cf7-87c9-a38435f51a7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444648260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3444648260
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3098433496
Short name T414
Test name
Test status
Simulation time 92448811 ps
CPU time 1.14 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 216464 kb
Host smart-f2fdd00e-73e8-4728-9619-78b63447c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098433496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3098433496
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4040098621
Short name T621
Test name
Test status
Simulation time 54157242 ps
CPU time 1.25 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 217816 kb
Host smart-76d4c4f3-7832-4b1f-b423-8ee594e705e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040098621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4040098621
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3714554377
Short name T313
Test name
Test status
Simulation time 68456807 ps
CPU time 1.04 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 216720 kb
Host smart-9e67076e-993d-433c-ae16-2d5665671306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714554377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3714554377
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3583314067
Short name T679
Test name
Test status
Simulation time 23676882 ps
CPU time 1.18 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 218852 kb
Host smart-25cd365e-17a5-40b5-96fe-f4722b3268aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583314067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3583314067
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.448353427
Short name T692
Test name
Test status
Simulation time 44975700 ps
CPU time 1.53 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217772 kb
Host smart-28ee0fc1-092f-452e-8c3b-6d8043b71fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448353427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.448353427
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3413679875
Short name T447
Test name
Test status
Simulation time 68512218 ps
CPU time 1.24 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 217740 kb
Host smart-d978a068-a906-4657-92d2-3559195b8ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413679875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3413679875
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2548859904
Short name T368
Test name
Test status
Simulation time 44808572 ps
CPU time 1.18 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 216868 kb
Host smart-3b2794dc-8e3c-4d5a-8503-931170c6d810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548859904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2548859904
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2265662063
Short name T482
Test name
Test status
Simulation time 49594904 ps
CPU time 1.88 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 216860 kb
Host smart-26ba9b1d-f66a-4515-af11-9af4b9c89412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265662063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2265662063
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2316274573
Short name T555
Test name
Test status
Simulation time 98231763 ps
CPU time 1.19 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 216568 kb
Host smart-22e2cddc-b61b-437d-8eea-374e74c15f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316274573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2316274573
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.478778789
Short name T538
Test name
Test status
Simulation time 62769947 ps
CPU time 1.1 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 218180 kb
Host smart-992f883b-c967-4319-bb74-4dda0572b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478778789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.478778789
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3712279245
Short name T34
Test name
Test status
Simulation time 96077088 ps
CPU time 1.29 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 215396 kb
Host smart-af33ec5d-fae1-45ac-8cf7-bbd6286c88f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712279245 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3712279245
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3158452457
Short name T396
Test name
Test status
Simulation time 12540031 ps
CPU time 0.94 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:30 PM PDT 24
Peak memory 206284 kb
Host smart-1d74bec3-659f-412f-ab72-623d16c67c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158452457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3158452457
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2105952612
Short name T417
Test name
Test status
Simulation time 18794262 ps
CPU time 0.85 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 215720 kb
Host smart-a08b5e92-b474-42e2-a022-47d96bbc0bd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105952612 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2105952612
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.34585249
Short name T575
Test name
Test status
Simulation time 40033287 ps
CPU time 1.25 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 216656 kb
Host smart-45716e42-1bfc-41db-9e45-e72d14c085ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34585249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_dis
able_auto_req_mode.34585249
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3066862191
Short name T687
Test name
Test status
Simulation time 26850172 ps
CPU time 0.9 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:29 PM PDT 24
Peak memory 218176 kb
Host smart-4d58afb9-63d7-4cbd-bc6a-f8ef7ae2d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066862191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3066862191
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.172880347
Short name T735
Test name
Test status
Simulation time 37974212 ps
CPU time 1.73 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 218204 kb
Host smart-2c336dba-ed6b-4826-b139-cc21612b8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172880347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.172880347
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4284923613
Short name T102
Test name
Test status
Simulation time 33621179 ps
CPU time 0.91 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 215132 kb
Host smart-4d7eeeaf-030c-4858-a4ab-fe5c71cad1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284923613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4284923613
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1999342218
Short name T676
Test name
Test status
Simulation time 57311769 ps
CPU time 0.92 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 215040 kb
Host smart-4c2c7e0e-b00d-41c4-a806-a5184c0aefee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999342218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1999342218
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2115910013
Short name T563
Test name
Test status
Simulation time 50965966 ps
CPU time 1.1 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 206312 kb
Host smart-01573c6b-88d8-4b03-9eb4-235e8e79b56f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115910013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2115910013
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.4288169394
Short name T511
Test name
Test status
Simulation time 25315455580 ps
CPU time 677.37 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:55:50 PM PDT 24
Peak memory 217396 kb
Host smart-6d4b016e-0cba-4033-b996-af919e3b4872
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288169394 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.4288169394
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1125503998
Short name T305
Test name
Test status
Simulation time 63160461 ps
CPU time 1.22 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 218028 kb
Host smart-09f3da5f-36fb-4a0e-ade5-9d6ce0934666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125503998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1125503998
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2949168306
Short name T844
Test name
Test status
Simulation time 20876818 ps
CPU time 1.14 seconds
Started Jun 04 01:45:25 PM PDT 24
Finished Jun 04 01:45:28 PM PDT 24
Peak memory 216808 kb
Host smart-71b4ce2f-5930-427f-b1ea-a1e96ac9037c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949168306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2949168306
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3021109912
Short name T684
Test name
Test status
Simulation time 82675666 ps
CPU time 1.42 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:32 PM PDT 24
Peak memory 218596 kb
Host smart-8144899b-5cb4-4c5b-94b9-57de0b16ebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021109912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3021109912
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.571771931
Short name T819
Test name
Test status
Simulation time 35741191 ps
CPU time 1.31 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 214988 kb
Host smart-377d0fbb-8dfd-45a2-8b45-3c719da94b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571771931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.571771931
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.885076328
Short name T763
Test name
Test status
Simulation time 46847388 ps
CPU time 1.9 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217856 kb
Host smart-760f7be3-7317-4e74-8dec-16a2bd697076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885076328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.885076328
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3473220734
Short name T824
Test name
Test status
Simulation time 39050483 ps
CPU time 1 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 216672 kb
Host smart-bda8d645-8c68-4163-a45b-648e47dd547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473220734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3473220734
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.3499677242
Short name T668
Test name
Test status
Simulation time 38369288 ps
CPU time 1.03 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216816 kb
Host smart-0cd96430-4193-46a1-9c7c-703cc1360dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499677242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.3499677242
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.651380069
Short name T121
Test name
Test status
Simulation time 76193066 ps
CPU time 1.24 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 216936 kb
Host smart-d6e61d98-f041-4372-9646-16f1a6e35a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651380069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.651380069
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2666266298
Short name T703
Test name
Test status
Simulation time 28864138 ps
CPU time 1.28 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 216616 kb
Host smart-1cb8adef-7d23-4e6f-8a6c-27b66d4d4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666266298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2666266298
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3689710665
Short name T798
Test name
Test status
Simulation time 55551138 ps
CPU time 1.62 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 216740 kb
Host smart-0b1fdcd1-762b-4bea-8fcd-5f9f44dcd570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689710665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3689710665
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.910489493
Short name T835
Test name
Test status
Simulation time 46504389 ps
CPU time 1.22 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 215400 kb
Host smart-b68ddc91-7611-4f21-a141-482e0c009ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910489493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.910489493
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1586833232
Short name T312
Test name
Test status
Simulation time 38219485 ps
CPU time 0.89 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 206596 kb
Host smart-ca64df48-efd8-4890-bfd1-6a8747b16515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586833232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1586833232
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.3577839655
Short name T254
Test name
Test status
Simulation time 32277096 ps
CPU time 1.11 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 216756 kb
Host smart-c8ec6d1b-2355-42a8-8f33-c40d620284f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577839655 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.3577839655
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2417914969
Short name T426
Test name
Test status
Simulation time 28670019 ps
CPU time 0.85 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 218128 kb
Host smart-c36c496d-f138-4153-9687-7c176cbeef2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417914969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2417914969
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.465011954
Short name T124
Test name
Test status
Simulation time 48279154 ps
CPU time 1.93 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 216828 kb
Host smart-67a665d0-c454-4a05-82f3-6d07e7fb91d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465011954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.465011954
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3655081701
Short name T826
Test name
Test status
Simulation time 46790143 ps
CPU time 0.84 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 214916 kb
Host smart-0246b2ef-1997-4236-b18f-8b18e0aa7e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655081701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3655081701
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2179160145
Short name T790
Test name
Test status
Simulation time 43084881 ps
CPU time 0.96 seconds
Started Jun 04 01:44:26 PM PDT 24
Finished Jun 04 01:44:28 PM PDT 24
Peak memory 214972 kb
Host smart-331e8bb0-c627-4c95-97de-8070ee099ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179160145 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2179160145
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2820476172
Short name T207
Test name
Test status
Simulation time 1300874499 ps
CPU time 4.18 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 216772 kb
Host smart-eebc1046-5146-43fd-ac88-989922c541a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820476172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2820476172
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1609588250
Short name T202
Test name
Test status
Simulation time 55360525303 ps
CPU time 1115.21 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 02:03:07 PM PDT 24
Peak memory 219376 kb
Host smart-63affefe-a2c5-4a52-9c6d-2bd33be95558
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609588250 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1609588250
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.4045077265
Short name T740
Test name
Test status
Simulation time 48800284 ps
CPU time 1.64 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 217888 kb
Host smart-88825c05-e1d2-4d3e-90b0-638fb869a06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045077265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4045077265
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4278191180
Short name T323
Test name
Test status
Simulation time 41051450 ps
CPU time 1.28 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 216888 kb
Host smart-3410ec67-4f75-4997-a8df-a280af01ca83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278191180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4278191180
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.127362577
Short name T480
Test name
Test status
Simulation time 28382259 ps
CPU time 1.34 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 218156 kb
Host smart-d0067474-f6cc-4eca-9e4b-a2d89aff026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127362577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.127362577
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3172019199
Short name T682
Test name
Test status
Simulation time 36995943 ps
CPU time 1.07 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 216860 kb
Host smart-66047d29-5343-4af5-9ce1-0a82ccf07731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172019199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3172019199
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2799445338
Short name T754
Test name
Test status
Simulation time 116527896 ps
CPU time 2.5 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 219528 kb
Host smart-7f7aff05-24f9-4735-815e-be792983f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799445338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2799445338
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1283319332
Short name T724
Test name
Test status
Simulation time 70837276 ps
CPU time 2.45 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 219488 kb
Host smart-88f90a01-d2ec-4985-bbb5-5e72567a0161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283319332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1283319332
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.1298495215
Short name T272
Test name
Test status
Simulation time 36133108 ps
CPU time 1.28 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 217932 kb
Host smart-cd4a4e29-c354-4bc8-a85a-5f8ff550be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298495215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.1298495215
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1138942322
Short name T695
Test name
Test status
Simulation time 81727897 ps
CPU time 1.24 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 215000 kb
Host smart-f745264e-f7a0-471d-8a50-85891d1317a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138942322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1138942322
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2222442747
Short name T586
Test name
Test status
Simulation time 99423083 ps
CPU time 1.06 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216876 kb
Host smart-44e9bc75-f317-4491-8ad7-f64d1dde05b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222442747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2222442747
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1089133066
Short name T11
Test name
Test status
Simulation time 294283776 ps
CPU time 1.16 seconds
Started Jun 04 01:45:28 PM PDT 24
Finished Jun 04 01:45:31 PM PDT 24
Peak memory 219500 kb
Host smart-5c613924-41bb-4523-b3a8-768eb4367191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089133066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1089133066
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.1250966573
Short name T697
Test name
Test status
Simulation time 13406313 ps
CPU time 0.9 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 206772 kb
Host smart-962e93cc-9191-4c0e-9da6-c225a8a97149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250966573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1250966573
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1292094043
Short name T403
Test name
Test status
Simulation time 23813857 ps
CPU time 0.94 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 215836 kb
Host smart-0c8ffacf-98a1-4b63-aa47-62e554466227
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292094043 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1292094043
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3880217963
Short name T60
Test name
Test status
Simulation time 104211799 ps
CPU time 1.15 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 216532 kb
Host smart-b44fbc36-1222-4e35-91c9-dd3d07440aba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880217963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3880217963
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3800893025
Short name T48
Test name
Test status
Simulation time 70994287 ps
CPU time 1.18 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 225044 kb
Host smart-deb119df-8b53-48e4-8d86-476423a116ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800893025 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3800893025
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1993324383
Short name T657
Test name
Test status
Simulation time 62272209 ps
CPU time 1.41 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:30 PM PDT 24
Peak memory 217864 kb
Host smart-c0aabd12-32cc-4000-a740-b394c800ee68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993324383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1993324383
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4063159885
Short name T661
Test name
Test status
Simulation time 33844218 ps
CPU time 0.86 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 215260 kb
Host smart-a81ac05f-7e21-478c-b4b4-e7768c9f8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063159885 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4063159885
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1708140822
Short name T640
Test name
Test status
Simulation time 26705256 ps
CPU time 0.95 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 206836 kb
Host smart-b14fcb5f-e3c6-4fb7-9348-e50767e2e39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708140822 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1708140822
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1232720206
Short name T465
Test name
Test status
Simulation time 659040922 ps
CPU time 3.83 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 216724 kb
Host smart-f4ffb20f-abd2-40fa-ad58-6496ec54a295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232720206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1232720206
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.542327976
Short name T357
Test name
Test status
Simulation time 149791449863 ps
CPU time 1098.99 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 02:02:49 PM PDT 24
Peak memory 223428 kb
Host smart-4405e41c-45bc-45d8-af8a-71269e0d6d63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542327976 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.542327976
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/231.edn_genbits.3498105123
Short name T118
Test name
Test status
Simulation time 43023496 ps
CPU time 1.54 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 219264 kb
Host smart-f4daa963-970c-400b-9fee-2ad15b7eb4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498105123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3498105123
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4196104858
Short name T540
Test name
Test status
Simulation time 62195907 ps
CPU time 1.16 seconds
Started Jun 04 01:45:38 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 219304 kb
Host smart-152311a0-aa3d-4de5-a6e0-d212d4429958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196104858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4196104858
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1172161168
Short name T348
Test name
Test status
Simulation time 41693769 ps
CPU time 1.16 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 216692 kb
Host smart-153631ac-07cf-4f6a-a941-713f34d87615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172161168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1172161168
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3199856755
Short name T603
Test name
Test status
Simulation time 172737711 ps
CPU time 1.73 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:47 PM PDT 24
Peak memory 218216 kb
Host smart-b7828619-25b1-4430-b933-c8c0a8d6c4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199856755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3199856755
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2769189898
Short name T509
Test name
Test status
Simulation time 64836234 ps
CPU time 1.08 seconds
Started Jun 04 01:45:46 PM PDT 24
Finished Jun 04 01:45:48 PM PDT 24
Peak memory 216560 kb
Host smart-3dffcb84-c037-4638-a0ed-72d14554e2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769189898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2769189898
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2983092030
Short name T712
Test name
Test status
Simulation time 72278240 ps
CPU time 1.41 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 216636 kb
Host smart-c0ed432c-d08e-440d-8aef-0244374e6e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983092030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2983092030
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3584194677
Short name T2
Test name
Test status
Simulation time 59119452 ps
CPU time 1.23 seconds
Started Jun 04 01:45:35 PM PDT 24
Finished Jun 04 01:45:38 PM PDT 24
Peak memory 217000 kb
Host smart-a72b1c28-03ab-4bd4-8535-cddd01a09418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584194677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3584194677
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1616638589
Short name T492
Test name
Test status
Simulation time 73735588 ps
CPU time 1.16 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 216744 kb
Host smart-402a6725-f4b8-4f83-b8a4-b98c51065758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616638589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1616638589
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.201484333
Short name T769
Test name
Test status
Simulation time 51980048 ps
CPU time 1.51 seconds
Started Jun 04 01:45:31 PM PDT 24
Finished Jun 04 01:45:35 PM PDT 24
Peak memory 216896 kb
Host smart-30739b0b-ed25-415c-a685-fd2c316907bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201484333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.201484333
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.717119165
Short name T845
Test name
Test status
Simulation time 63221096 ps
CPU time 1.26 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 215416 kb
Host smart-9075d9c8-82c8-4dfd-a473-a297fc77b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717119165 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.717119165
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3785814837
Short name T507
Test name
Test status
Simulation time 47286537 ps
CPU time 0.96 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 206340 kb
Host smart-ebfdc8e9-e17d-40cf-9995-633b68b25270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785814837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3785814837
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1908563969
Short name T210
Test name
Test status
Simulation time 16236867 ps
CPU time 0.87 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 215652 kb
Host smart-0b1eac02-5366-4ee8-b1c6-2e3e46008ea5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908563969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1908563969
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3888795281
Short name T7
Test name
Test status
Simulation time 94485408 ps
CPU time 1.02 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:33 PM PDT 24
Peak memory 219236 kb
Host smart-b15b1266-48cb-48ac-ba2f-279162f3df21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888795281 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3888795281
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.1576735950
Short name T611
Test name
Test status
Simulation time 51045885 ps
CPU time 1.51 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 218088 kb
Host smart-56b742cd-72b1-4dc3-970d-ce2b44bef1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576735950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1576735950
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3257074920
Short name T110
Test name
Test status
Simulation time 52300282 ps
CPU time 0.86 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 215276 kb
Host smart-6447d3ce-0084-4ec6-ad7a-93ec3890ac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257074920 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3257074920
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1281032942
Short name T469
Test name
Test status
Simulation time 25372486 ps
CPU time 0.99 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 214888 kb
Host smart-95bdda71-f070-44fb-badd-702a6c713b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281032942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1281032942
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.210341376
Short name T487
Test name
Test status
Simulation time 1045871750 ps
CPU time 5.33 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 216708 kb
Host smart-14ba0639-eac8-400d-b8de-c52b36e80f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210341376 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.210341376
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3755846314
Short name T821
Test name
Test status
Simulation time 85689015679 ps
CPU time 381.36 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:50:50 PM PDT 24
Peak memory 218284 kb
Host smart-b6cb4dec-2bc1-415f-b013-22e2a4f9250f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755846314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3755846314
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.264557247
Short name T594
Test name
Test status
Simulation time 51938471 ps
CPU time 1.78 seconds
Started Jun 04 01:45:40 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 216836 kb
Host smart-f69cfad9-197a-4d02-bdfd-5724c1fe87ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264557247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.264557247
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2813838621
Short name T420
Test name
Test status
Simulation time 85718352 ps
CPU time 1.1 seconds
Started Jun 04 01:45:47 PM PDT 24
Finished Jun 04 01:45:49 PM PDT 24
Peak memory 214956 kb
Host smart-e01601a7-60d9-4f4e-b24a-81fb8b919c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813838621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2813838621
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1098998546
Short name T281
Test name
Test status
Simulation time 59540894 ps
CPU time 1.48 seconds
Started Jun 04 01:45:53 PM PDT 24
Finished Jun 04 01:45:55 PM PDT 24
Peak memory 218032 kb
Host smart-476c565e-1c52-4813-b220-581b77d8ec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098998546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1098998546
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2204661115
Short name T796
Test name
Test status
Simulation time 92728824 ps
CPU time 1.94 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 218020 kb
Host smart-389ce4ce-a6bc-4160-93d1-bfc9a4b823ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204661115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2204661115
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.833299360
Short name T412
Test name
Test status
Simulation time 44175932 ps
CPU time 1.43 seconds
Started Jun 04 01:45:34 PM PDT 24
Finished Jun 04 01:45:37 PM PDT 24
Peak memory 218108 kb
Host smart-99dffd16-86ef-4306-9ea8-3c707f9fa5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833299360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.833299360
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3390849600
Short name T702
Test name
Test status
Simulation time 267282369 ps
CPU time 3.8 seconds
Started Jun 04 01:45:39 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 219636 kb
Host smart-05c3bfd5-1f75-4996-8e63-d691856d5238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390849600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3390849600
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1430727248
Short name T402
Test name
Test status
Simulation time 24269575 ps
CPU time 1.27 seconds
Started Jun 04 01:45:33 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 216924 kb
Host smart-ea530f39-d9c1-415c-955b-c4e8309d3117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430727248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1430727248
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4084725100
Short name T432
Test name
Test status
Simulation time 37991581 ps
CPU time 1.22 seconds
Started Jun 04 01:45:56 PM PDT 24
Finished Jun 04 01:45:59 PM PDT 24
Peak memory 218176 kb
Host smart-fe1b5e65-757e-4ede-bda2-c983f6785c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084725100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4084725100
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2732838194
Short name T693
Test name
Test status
Simulation time 119210557 ps
CPU time 2.74 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 218292 kb
Host smart-1d8064f4-e99b-4986-b4d9-0fbb874f5784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732838194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2732838194
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3316242948
Short name T794
Test name
Test status
Simulation time 75945411 ps
CPU time 1.16 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 215400 kb
Host smart-e9bdba7e-0fac-45bd-acab-8550a3f2b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316242948 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3316242948
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.496866267
Short name T363
Test name
Test status
Simulation time 17161733 ps
CPU time 0.98 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 01:44:30 PM PDT 24
Peak memory 214604 kb
Host smart-5d341012-851c-4bbd-9bf9-8ef66c670c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496866267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.496866267
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.4288289966
Short name T667
Test name
Test status
Simulation time 54671875 ps
CPU time 0.88 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 216036 kb
Host smart-eaa34e8a-0022-489c-ba59-47a9241e8449
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288289966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.4288289966
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1393714889
Short name T35
Test name
Test status
Simulation time 22322755 ps
CPU time 1.04 seconds
Started Jun 04 01:44:29 PM PDT 24
Finished Jun 04 01:44:32 PM PDT 24
Peak memory 219168 kb
Host smart-cda1f41b-81d5-4387-af52-6ede046698ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393714889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1393714889
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.382678771
Short name T275
Test name
Test status
Simulation time 48944436 ps
CPU time 1.62 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 218084 kb
Host smart-0f4a8d31-c0af-4cac-b2bf-8ed431e4751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382678771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.382678771
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.907120565
Short name T841
Test name
Test status
Simulation time 21270905 ps
CPU time 1.18 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 223560 kb
Host smart-aefa3b39-cc12-47da-9642-e3c0910d00b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907120565 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.907120565
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.351120615
Short name T342
Test name
Test status
Simulation time 94072516 ps
CPU time 0.97 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:30 PM PDT 24
Peak memory 214944 kb
Host smart-2ba777fb-4c7c-417a-87e9-19e3cf1540ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351120615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.351120615
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.826255278
Short name T349
Test name
Test status
Simulation time 83798163 ps
CPU time 1.79 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 206812 kb
Host smart-8b9105b8-813b-4b91-b2f2-dc28006d8ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826255278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.826255278
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1917493901
Short name T366
Test name
Test status
Simulation time 56579086845 ps
CPU time 1313.29 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 02:06:27 PM PDT 24
Peak memory 221596 kb
Host smart-c1f53105-6cbd-41d4-8bb2-840da40dab82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917493901 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1917493901
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2197051604
Short name T788
Test name
Test status
Simulation time 33426483 ps
CPU time 1.44 seconds
Started Jun 04 01:45:38 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 217836 kb
Host smart-a485a326-f238-4a02-85ad-41fd452056fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197051604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2197051604
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.778238713
Short name T411
Test name
Test status
Simulation time 50112334 ps
CPU time 1.28 seconds
Started Jun 04 01:45:41 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 219504 kb
Host smart-6bf1cebe-479e-4410-8b11-d0af0fcbd4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778238713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.778238713
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3727023955
Short name T296
Test name
Test status
Simulation time 35204144 ps
CPU time 1.44 seconds
Started Jun 04 01:45:40 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 218044 kb
Host smart-321f83e7-91b4-4df7-91ca-3d597519584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727023955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3727023955
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3728169249
Short name T445
Test name
Test status
Simulation time 166871327 ps
CPU time 3.45 seconds
Started Jun 04 01:45:39 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 219696 kb
Host smart-53ec0c4a-49f3-4a3b-9de8-77d7df721fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728169249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3728169249
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3477772146
Short name T608
Test name
Test status
Simulation time 270828463 ps
CPU time 3.79 seconds
Started Jun 04 01:45:37 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 216904 kb
Host smart-22e2b8f9-6ba3-43ff-9656-847d8b98c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477772146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3477772146
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3902746128
Short name T283
Test name
Test status
Simulation time 43789780 ps
CPU time 1.29 seconds
Started Jun 04 01:45:38 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 216604 kb
Host smart-9dada268-40c4-48e4-b1d3-c2bdafa1111d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902746128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3902746128
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2102244850
Short name T529
Test name
Test status
Simulation time 161887389 ps
CPU time 2.09 seconds
Started Jun 04 01:45:39 PM PDT 24
Finished Jun 04 01:45:42 PM PDT 24
Peak memory 218932 kb
Host smart-38906508-632a-4d98-957c-d4307a8d252b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102244850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2102244850
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.930734101
Short name T343
Test name
Test status
Simulation time 188235005 ps
CPU time 1.17 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 216964 kb
Host smart-4d9c834c-3982-4ca6-9b14-367b02572f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930734101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.930734101
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2537006096
Short name T119
Test name
Test status
Simulation time 45387099 ps
CPU time 1.4 seconds
Started Jun 04 01:45:38 PM PDT 24
Finished Jun 04 01:45:40 PM PDT 24
Peak memory 217784 kb
Host smart-6b46f350-0fff-418c-a9e7-8df6d58e18ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537006096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2537006096
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4005671886
Short name T250
Test name
Test status
Simulation time 103268322 ps
CPU time 1.29 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 215404 kb
Host smart-62fe0db7-a368-45dd-ac48-69106f20495c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005671886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4005671886
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3754655191
Short name T609
Test name
Test status
Simulation time 23529131 ps
CPU time 0.82 seconds
Started Jun 04 01:44:32 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 206592 kb
Host smart-f96c0d3a-1c95-4ba0-a54a-4406ddb6259a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754655191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3754655191
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.4123134472
Short name T793
Test name
Test status
Simulation time 38323405 ps
CPU time 1.33 seconds
Started Jun 04 01:44:28 PM PDT 24
Finished Jun 04 01:44:31 PM PDT 24
Peak memory 219184 kb
Host smart-af5f29e0-6f57-475d-9c72-80fad550d49f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123134472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.4123134472
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.442019595
Short name T522
Test name
Test status
Simulation time 21285976 ps
CPU time 1.07 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 218272 kb
Host smart-184269fb-427f-4781-8c10-bddb9cb08f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442019595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.442019595
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_intr.3374732238
Short name T393
Test name
Test status
Simulation time 69755064 ps
CPU time 0.87 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 214916 kb
Host smart-94139cbf-ce2c-4065-8168-3b67f870a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374732238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3374732238
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.476498651
Short name T317
Test name
Test status
Simulation time 19506745 ps
CPU time 1.03 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 214448 kb
Host smart-835cb892-01d0-4cbf-864a-049fd1a6a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476498651 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.476498651
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3107267242
Short name T318
Test name
Test status
Simulation time 213373975 ps
CPU time 1.78 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:35 PM PDT 24
Peak memory 216228 kb
Host smart-94603c57-6f79-4946-a8f2-9b4ac98dc167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107267242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3107267242
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1853006949
Short name T717
Test name
Test status
Simulation time 40726308950 ps
CPU time 1033.9 seconds
Started Jun 04 01:44:27 PM PDT 24
Finished Jun 04 02:01:43 PM PDT 24
Peak memory 220600 kb
Host smart-3532ed25-be6d-4420-8af3-65c6d1097ef1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853006949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1853006949
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4239103154
Short name T628
Test name
Test status
Simulation time 72255173 ps
CPU time 1.22 seconds
Started Jun 04 01:45:49 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 216640 kb
Host smart-04fd49bd-0364-4650-b9be-42fd4d23d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239103154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4239103154
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1406777159
Short name T308
Test name
Test status
Simulation time 36635101 ps
CPU time 1.22 seconds
Started Jun 04 01:45:39 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 216600 kb
Host smart-5e709caf-f07d-4a88-a45f-157bd6774912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406777159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1406777159
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3369385745
Short name T288
Test name
Test status
Simulation time 95232707 ps
CPU time 1.23 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 219348 kb
Host smart-fc0e01ee-bca1-4ae4-aedd-0d8165addba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369385745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3369385745
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3046698224
Short name T255
Test name
Test status
Simulation time 82755740 ps
CPU time 1.5 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:45 PM PDT 24
Peak memory 218444 kb
Host smart-9c173be0-cd65-43ac-81cd-01e2fd5d7eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046698224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3046698224
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.517730930
Short name T711
Test name
Test status
Simulation time 29998751 ps
CPU time 1.39 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 218032 kb
Host smart-cc0eb80f-bf9e-4e95-8aef-781296c186d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517730930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.517730930
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1402163846
Short name T307
Test name
Test status
Simulation time 144646384 ps
CPU time 2.6 seconds
Started Jun 04 01:45:45 PM PDT 24
Finished Jun 04 01:45:48 PM PDT 24
Peak memory 218944 kb
Host smart-dd8685d1-de97-4677-96a7-0cb72b3e51e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402163846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1402163846
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3684042890
Short name T278
Test name
Test status
Simulation time 185457074 ps
CPU time 1.01 seconds
Started Jun 04 01:45:50 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 216576 kb
Host smart-1fde4b68-0319-4a8e-839a-f964b24a944e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684042890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3684042890
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3781399418
Short name T450
Test name
Test status
Simulation time 34488306 ps
CPU time 1.28 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 216780 kb
Host smart-9905995d-c0ba-42b8-af74-b2ed00cc2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781399418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3781399418
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2420018757
Short name T471
Test name
Test status
Simulation time 130846623 ps
CPU time 2.98 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:41 PM PDT 24
Peak memory 219604 kb
Host smart-66c7c7fb-59df-4ed6-9f9f-5f9c8b48e467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420018757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2420018757
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4036358980
Short name T602
Test name
Test status
Simulation time 55178557 ps
CPU time 1.08 seconds
Started Jun 04 01:45:36 PM PDT 24
Finished Jun 04 01:45:39 PM PDT 24
Peak memory 216696 kb
Host smart-f85b9eac-edc0-4b6f-9047-06d46687e3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036358980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4036358980
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1754889020
Short name T69
Test name
Test status
Simulation time 38909659 ps
CPU time 1.1 seconds
Started Jun 04 01:44:33 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 215388 kb
Host smart-eca3d40d-3fe9-46a7-a97d-01f01da38606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754889020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1754889020
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.851153199
Short name T448
Test name
Test status
Simulation time 17005558 ps
CPU time 1 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 214916 kb
Host smart-3aed14ae-8763-4535-bc56-8bffe75fbb27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851153199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.851153199
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3843726046
Short name T63
Test name
Test status
Simulation time 131582864 ps
CPU time 0.86 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215180 kb
Host smart-270aabf0-718d-485f-9632-3719ab69cce9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843726046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3843726046
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2809661522
Short name T13
Test name
Test status
Simulation time 19843093 ps
CPU time 1.17 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 223420 kb
Host smart-985f19d2-da5a-4df8-890a-bcce93c4fb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809661522 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2809661522
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.526098502
Short name T289
Test name
Test status
Simulation time 39025466 ps
CPU time 1.36 seconds
Started Jun 04 01:44:30 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 218164 kb
Host smart-e16a32d0-aeba-47ca-a20f-f6ce255497f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526098502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.526098502
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2555976625
Short name T517
Test name
Test status
Simulation time 42191734 ps
CPU time 0.88 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 215180 kb
Host smart-592e815c-08e8-42c9-a617-8740a2581443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555976625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2555976625
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2363112749
Short name T823
Test name
Test status
Simulation time 20363502 ps
CPU time 0.95 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 215032 kb
Host smart-325b6dbc-91ac-4598-a140-0ae027c8f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363112749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2363112749
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1397886447
Short name T782
Test name
Test status
Simulation time 119179883 ps
CPU time 1.86 seconds
Started Jun 04 01:44:31 PM PDT 24
Finished Jun 04 01:44:34 PM PDT 24
Peak memory 216732 kb
Host smart-7ad8acc3-5ba7-4fa7-8a8b-6cc73bdf58fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397886447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1397886447
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2224715609
Short name T600
Test name
Test status
Simulation time 59286270057 ps
CPU time 635.39 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:55:13 PM PDT 24
Peak memory 218464 kb
Host smart-b3877515-726e-4741-99b3-905cc5f8cfc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224715609 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2224715609
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.891001946
Short name T386
Test name
Test status
Simulation time 44988517 ps
CPU time 1.74 seconds
Started Jun 04 01:45:47 PM PDT 24
Finished Jun 04 01:45:50 PM PDT 24
Peak memory 218188 kb
Host smart-e3d77ea5-f266-470e-b479-99069fd2ffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891001946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.891001946
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.303474598
Short name T481
Test name
Test status
Simulation time 41827017 ps
CPU time 1.41 seconds
Started Jun 04 01:45:45 PM PDT 24
Finished Jun 04 01:45:47 PM PDT 24
Peak memory 218032 kb
Host smart-a3e121df-2609-4509-84c0-d8837ae5bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303474598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.303474598
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.378965194
Short name T413
Test name
Test status
Simulation time 79236104 ps
CPU time 1.12 seconds
Started Jun 04 01:45:58 PM PDT 24
Finished Jun 04 01:46:00 PM PDT 24
Peak memory 216632 kb
Host smart-2fbf5449-e9db-475a-8f94-d611c209d3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378965194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.378965194
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2113653554
Short name T599
Test name
Test status
Simulation time 39132554 ps
CPU time 1.67 seconds
Started Jun 04 01:45:42 PM PDT 24
Finished Jun 04 01:45:45 PM PDT 24
Peak memory 219256 kb
Host smart-4928a415-5039-49f5-8bae-f10b44bca822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113653554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2113653554
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1747114566
Short name T761
Test name
Test status
Simulation time 100329025 ps
CPU time 2.39 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 216832 kb
Host smart-f742561e-f3ea-4d58-a5ff-2dac931c037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747114566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1747114566
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1337861067
Short name T350
Test name
Test status
Simulation time 94508544 ps
CPU time 1.11 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:45 PM PDT 24
Peak memory 215076 kb
Host smart-984c3177-3a3f-4a05-b84a-2a9d603edee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337861067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1337861067
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3944862520
Short name T340
Test name
Test status
Simulation time 39871046 ps
CPU time 1.41 seconds
Started Jun 04 01:45:45 PM PDT 24
Finished Jun 04 01:45:47 PM PDT 24
Peak memory 218004 kb
Host smart-77858dec-e124-4880-bbfb-9a45d73b1427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944862520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3944862520
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1544338446
Short name T525
Test name
Test status
Simulation time 103268884 ps
CPU time 1.32 seconds
Started Jun 04 01:45:55 PM PDT 24
Finished Jun 04 01:45:58 PM PDT 24
Peak memory 216624 kb
Host smart-c5a69a96-35a0-4f85-96b0-89722edf1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544338446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1544338446
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2449082066
Short name T467
Test name
Test status
Simulation time 60721191 ps
CPU time 1.23 seconds
Started Jun 04 01:45:41 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 218328 kb
Host smart-fa7f5487-833d-4369-aea8-1c9a8f1993c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449082066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2449082066
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3419194097
Short name T291
Test name
Test status
Simulation time 244635147 ps
CPU time 1.96 seconds
Started Jun 04 01:45:48 PM PDT 24
Finished Jun 04 01:45:51 PM PDT 24
Peak memory 218196 kb
Host smart-1282bd8a-40f8-45ad-b1f3-c1009d41e5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419194097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3419194097
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1627072684
Short name T33
Test name
Test status
Simulation time 151772589 ps
CPU time 1.33 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:39 PM PDT 24
Peak memory 215372 kb
Host smart-762b63e3-0d98-41c6-b631-55a37cd23409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627072684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1627072684
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3317217902
Short name T316
Test name
Test status
Simulation time 16223365 ps
CPU time 0.99 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 214460 kb
Host smart-3f78012e-6f6c-497b-aab1-5c239f35a5ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317217902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3317217902
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.4156909208
Short name T806
Test name
Test status
Simulation time 11433429 ps
CPU time 0.95 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215684 kb
Host smart-6516fff1-f78d-4e25-82aa-73aafcf3a0b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156909208 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.4156909208
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1035291829
Short name T56
Test name
Test status
Simulation time 27183012 ps
CPU time 1.12 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 216612 kb
Host smart-bc58b500-cee4-4ca7-a94e-e12e47e82b09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035291829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1035291829
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2416609234
Short name T404
Test name
Test status
Simulation time 80086819 ps
CPU time 0.98 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 223300 kb
Host smart-da3fdaf9-a5b5-4340-928c-eaf2a59c2053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416609234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2416609234
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.3985726279
Short name T310
Test name
Test status
Simulation time 68164206 ps
CPU time 1.12 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 216892 kb
Host smart-b023f570-8d24-4faa-aba1-3cc6c2bc17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985726279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3985726279
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1538431486
Short name T438
Test name
Test status
Simulation time 42441326 ps
CPU time 0.94 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 215040 kb
Host smart-131c16fd-7fcc-4148-a8bf-ca138aceecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538431486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1538431486
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.897373797
Short name T504
Test name
Test status
Simulation time 119745297 ps
CPU time 0.85 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 215036 kb
Host smart-ab13c22c-49fe-497c-b05a-83fd0f699c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897373797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.897373797
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.89345279
Short name T734
Test name
Test status
Simulation time 200685201 ps
CPU time 3.36 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:42 PM PDT 24
Peak memory 217992 kb
Host smart-c639a21b-9fb8-4746-bb23-ad568b748d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89345279 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.89345279
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3307803975
Short name T322
Test name
Test status
Simulation time 70866652171 ps
CPU time 1490.27 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 02:09:28 PM PDT 24
Peak memory 222064 kb
Host smart-c15b580f-f665-479a-b4ae-86092076a6df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307803975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3307803975
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.4258992260
Short name T477
Test name
Test status
Simulation time 78720636 ps
CPU time 1.15 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:45 PM PDT 24
Peak memory 219384 kb
Host smart-43bbcdc8-d49b-421d-b8cc-f7359c2e14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258992260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.4258992260
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1443062658
Short name T840
Test name
Test status
Simulation time 42387833 ps
CPU time 1.4 seconds
Started Jun 04 01:45:50 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 217724 kb
Host smart-c344cc7c-5e76-4fe3-90ba-846cdd61ef80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443062658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1443062658
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.4021642606
Short name T157
Test name
Test status
Simulation time 49621544 ps
CPU time 1.28 seconds
Started Jun 04 01:45:41 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 215068 kb
Host smart-961dec3d-2847-480c-86cc-e5aed434d60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021642606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.4021642606
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2623287461
Short name T244
Test name
Test status
Simulation time 52397357 ps
CPU time 1.2 seconds
Started Jun 04 01:45:51 PM PDT 24
Finished Jun 04 01:45:53 PM PDT 24
Peak memory 216712 kb
Host smart-3b9d44a1-feb9-4deb-9d9a-0bcae9e1d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623287461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2623287461
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1366599248
Short name T140
Test name
Test status
Simulation time 108117404 ps
CPU time 1.71 seconds
Started Jun 04 01:45:49 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 218880 kb
Host smart-03526d58-d89b-48b1-8856-fcca0ece101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366599248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1366599248
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3888679400
Short name T629
Test name
Test status
Simulation time 26484927 ps
CPU time 1.35 seconds
Started Jun 04 01:45:40 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 217992 kb
Host smart-eacd296f-a866-4f1f-b4c2-4bf1f5d44181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888679400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3888679400
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3959506231
Short name T499
Test name
Test status
Simulation time 123630043 ps
CPU time 1.39 seconds
Started Jun 04 01:45:50 PM PDT 24
Finished Jun 04 01:45:52 PM PDT 24
Peak memory 219116 kb
Host smart-5606031d-f88b-4043-bf2c-5d252f4fd7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959506231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3959506231
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1016475633
Short name T772
Test name
Test status
Simulation time 104103937 ps
CPU time 1.2 seconds
Started Jun 04 01:45:46 PM PDT 24
Finished Jun 04 01:45:48 PM PDT 24
Peak memory 217780 kb
Host smart-6d868392-d4b3-4656-8641-16c0079760e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016475633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1016475633
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4277360906
Short name T656
Test name
Test status
Simulation time 52759529 ps
CPU time 1.52 seconds
Started Jun 04 01:45:43 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 218280 kb
Host smart-5517a14e-ccb0-4e99-bb3d-bccb69d7d522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277360906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4277360906
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1296048337
Short name T814
Test name
Test status
Simulation time 56270781 ps
CPU time 1.29 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 219576 kb
Host smart-452b9ed7-1db4-4142-ab26-d46728eecb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296048337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1296048337
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.1197820175
Short name T558
Test name
Test status
Simulation time 17958037 ps
CPU time 1 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 206424 kb
Host smart-3be541b7-58b5-43e0-863d-36eef9b1f649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197820175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1197820175
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.4067775372
Short name T710
Test name
Test status
Simulation time 31703283 ps
CPU time 0.85 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 216200 kb
Host smart-3c1fa0c3-2529-4914-9b49-e08c204ff843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067775372 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.4067775372
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2660918254
Short name T574
Test name
Test status
Simulation time 145184963 ps
CPU time 1.08 seconds
Started Jun 04 01:44:39 PM PDT 24
Finished Jun 04 01:44:42 PM PDT 24
Peak memory 219048 kb
Host smart-1a663761-8a32-46d8-b557-f9a8b53cadf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660918254 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2660918254
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3924686223
Short name T519
Test name
Test status
Simulation time 86730448 ps
CPU time 0.84 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 217912 kb
Host smart-e44916fe-d8f9-4470-bdda-31b977dfef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924686223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3924686223
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.470553691
Short name T125
Test name
Test status
Simulation time 208245844 ps
CPU time 3.18 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:41 PM PDT 24
Peak memory 217132 kb
Host smart-0840272f-6acf-4676-8671-f786ddb7802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470553691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.470553691
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1718099156
Short name T560
Test name
Test status
Simulation time 21520287 ps
CPU time 1.15 seconds
Started Jun 04 01:44:33 PM PDT 24
Finished Jun 04 01:44:36 PM PDT 24
Peak memory 223600 kb
Host smart-1443ab0c-18dd-42fb-8f4f-690ea02e0ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718099156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1718099156
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3424236095
Short name T541
Test name
Test status
Simulation time 36710064 ps
CPU time 0.96 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215068 kb
Host smart-4b2dd1c0-7564-4a80-9e7a-834c7f1d0c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424236095 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3424236095
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2059525172
Short name T542
Test name
Test status
Simulation time 138418812 ps
CPU time 3.2 seconds
Started Jun 04 01:44:33 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 216588 kb
Host smart-e6f89b1f-5dbe-4bb0-9c30-9b7e7a7f5c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059525172 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2059525172
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.390146586
Short name T804
Test name
Test status
Simulation time 40769240690 ps
CPU time 748.85 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:57:12 PM PDT 24
Peak memory 223532 kb
Host smart-798a7530-953f-47fd-8d6c-4a68cc0c79d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390146586 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.390146586
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1321505956
Short name T473
Test name
Test status
Simulation time 67863740 ps
CPU time 1.66 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:46 PM PDT 24
Peak memory 218152 kb
Host smart-f8a9ea18-0a3c-4d5c-9ff4-922229001f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321505956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1321505956
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.4224709459
Short name T605
Test name
Test status
Simulation time 122069017 ps
CPU time 2.59 seconds
Started Jun 04 01:45:44 PM PDT 24
Finished Jun 04 01:45:48 PM PDT 24
Peak memory 218480 kb
Host smart-a4a852d6-c6c0-45a4-a54e-d039fdb40714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224709459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4224709459
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1577600974
Short name T214
Test name
Test status
Simulation time 37187353 ps
CPU time 1.31 seconds
Started Jun 04 01:45:41 PM PDT 24
Finished Jun 04 01:45:43 PM PDT 24
Peak memory 217948 kb
Host smart-e7c957a1-ea95-4653-8a8c-ca596051e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577600974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1577600974
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1533299521
Short name T211
Test name
Test status
Simulation time 76210153 ps
CPU time 1.21 seconds
Started Jun 04 01:45:42 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 218420 kb
Host smart-53957d70-d9c4-45b7-9d68-bc45bcdff931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533299521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1533299521
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2139639786
Short name T805
Test name
Test status
Simulation time 751550860 ps
CPU time 5.5 seconds
Started Jun 04 01:45:53 PM PDT 24
Finished Jun 04 01:46:00 PM PDT 24
Peak memory 218008 kb
Host smart-c4ff64a1-9d5e-4e45-b931-41881ac85f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139639786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2139639786
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.830191411
Short name T290
Test name
Test status
Simulation time 169004416 ps
CPU time 1.44 seconds
Started Jun 04 01:45:48 PM PDT 24
Finished Jun 04 01:45:51 PM PDT 24
Peak memory 218192 kb
Host smart-c0001c8c-34d5-422c-99be-94c746c077f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830191411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.830191411
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2019370239
Short name T117
Test name
Test status
Simulation time 95153217 ps
CPU time 1.04 seconds
Started Jun 04 01:45:42 PM PDT 24
Finished Jun 04 01:45:44 PM PDT 24
Peak memory 216928 kb
Host smart-8785b881-775b-4055-95e8-860dfdd44aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019370239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2019370239
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3834646806
Short name T595
Test name
Test status
Simulation time 62248293 ps
CPU time 1.36 seconds
Started Jun 04 01:45:54 PM PDT 24
Finished Jun 04 01:45:57 PM PDT 24
Peak memory 219168 kb
Host smart-367cd2f4-3c88-4e0b-bc24-f3518112f1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834646806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3834646806
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1893046447
Short name T535
Test name
Test status
Simulation time 81099621 ps
CPU time 1.15 seconds
Started Jun 04 01:45:47 PM PDT 24
Finished Jun 04 01:45:49 PM PDT 24
Peak memory 216744 kb
Host smart-d5833c4f-79fa-4e52-bb47-6b0e9175a32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893046447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1893046447
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1693735636
Short name T613
Test name
Test status
Simulation time 75755154 ps
CPU time 1.53 seconds
Started Jun 04 01:45:46 PM PDT 24
Finished Jun 04 01:45:48 PM PDT 24
Peak memory 218088 kb
Host smart-2ea3e2dc-68b4-4d21-8498-cc7e325e6a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693735636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1693735636
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1325435714
Short name T513
Test name
Test status
Simulation time 25336009 ps
CPU time 1.31 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:47 PM PDT 24
Peak memory 215340 kb
Host smart-6a4aca26-1e21-4ab6-8185-f5a633517c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325435714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1325435714
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.818134623
Short name T531
Test name
Test status
Simulation time 19071503 ps
CPU time 0.9 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:52 PM PDT 24
Peak memory 214500 kb
Host smart-42708aba-21d9-4091-a955-fbb4228aff7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818134623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.818134623
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.915695828
Short name T395
Test name
Test status
Simulation time 11451305 ps
CPU time 0.88 seconds
Started Jun 04 01:43:46 PM PDT 24
Finished Jun 04 01:43:48 PM PDT 24
Peak memory 216184 kb
Host smart-9a09e0bd-1f86-4e2f-a766-7038b5bf4521
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915695828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.915695828
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.541454957
Short name T32
Test name
Test status
Simulation time 74018587 ps
CPU time 1.08 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:43:47 PM PDT 24
Peak memory 217884 kb
Host smart-0fc136df-d67a-419e-b36c-bd15f3258e79
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541454957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.541454957
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2730722237
Short name T807
Test name
Test status
Simulation time 46410167 ps
CPU time 1.04 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:43:48 PM PDT 24
Peak memory 217992 kb
Host smart-18121c70-c39a-491a-8d9c-5494a7888bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730722237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2730722237
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.143424104
Short name T549
Test name
Test status
Simulation time 41748112 ps
CPU time 1.03 seconds
Started Jun 04 01:43:43 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 216700 kb
Host smart-20c710ff-2e5a-4d4f-a806-59a56e26d79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143424104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.143424104
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1929002706
Short name T554
Test name
Test status
Simulation time 38725330 ps
CPU time 1 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:51 PM PDT 24
Peak memory 223440 kb
Host smart-df2261ea-bd18-41be-865e-a3aad0e39cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929002706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1929002706
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2362094463
Short name T256
Test name
Test status
Simulation time 44886122 ps
CPU time 0.98 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 01:43:47 PM PDT 24
Peak memory 206836 kb
Host smart-7a935059-ad2b-4043-830e-e90bde719cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362094463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2362094463
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3560763846
Short name T132
Test name
Test status
Simulation time 923973676 ps
CPU time 7.11 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:52 PM PDT 24
Peak memory 235324 kb
Host smart-c61fcddd-9134-4a53-91c1-0718fe57cd0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560763846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3560763846
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2801575802
Short name T775
Test name
Test status
Simulation time 29216816 ps
CPU time 0.98 seconds
Started Jun 04 01:43:41 PM PDT 24
Finished Jun 04 01:43:43 PM PDT 24
Peak memory 215000 kb
Host smart-313505aa-b291-4bad-8340-dc64cda96734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801575802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2801575802
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1463082676
Short name T681
Test name
Test status
Simulation time 898972968 ps
CPU time 4.72 seconds
Started Jun 04 01:43:42 PM PDT 24
Finished Jun 04 01:43:48 PM PDT 24
Peak memory 216488 kb
Host smart-4dc8a5e3-3531-49e6-92e7-4e73a04d7d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463082676 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1463082676
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1469723668
Short name T470
Test name
Test status
Simulation time 173185563977 ps
CPU time 1020.85 seconds
Started Jun 04 01:43:46 PM PDT 24
Finished Jun 04 02:00:48 PM PDT 24
Peak memory 222164 kb
Host smart-b541e936-bd7a-47f4-8437-73120ced1f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469723668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1469723668
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.131557777
Short name T766
Test name
Test status
Simulation time 23792850 ps
CPU time 1.22 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 215384 kb
Host smart-f341db0f-9a73-4eeb-9ce5-f49dbaadb380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131557777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.131557777
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2246550461
Short name T128
Test name
Test status
Simulation time 11138074 ps
CPU time 0.87 seconds
Started Jun 04 01:44:38 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 206548 kb
Host smart-5ef17947-4f4e-4305-81b3-c5c16a5b77aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246550461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2246550461
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3268232837
Short name T86
Test name
Test status
Simulation time 11331747 ps
CPU time 0.91 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 215952 kb
Host smart-9ad58087-0f9e-4c7e-944b-b6b7bd6342ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268232837 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3268232837
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3918959743
Short name T39
Test name
Test status
Simulation time 33432321 ps
CPU time 1.24 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 216464 kb
Host smart-5f93c6d0-7535-459a-9e13-4790b0403052
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918959743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3918959743
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_genbits.1460594138
Short name T758
Test name
Test status
Simulation time 72573053 ps
CPU time 1.07 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:37 PM PDT 24
Peak memory 216548 kb
Host smart-234d9ca7-f896-42fa-95d2-d5480b54f42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460594138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1460594138
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3593521324
Short name T439
Test name
Test status
Simulation time 21543290 ps
CPU time 1.05 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215068 kb
Host smart-c3377708-ec73-4699-80d3-6e6152e68a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593521324 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3593521324
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1222788383
Short name T797
Test name
Test status
Simulation time 64363498 ps
CPU time 0.91 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215068 kb
Host smart-02851c7c-9458-4120-8fe0-49bad377bc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222788383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1222788383
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.897924003
Short name T431
Test name
Test status
Simulation time 448560312 ps
CPU time 5.14 seconds
Started Jun 04 01:44:34 PM PDT 24
Finished Jun 04 01:44:41 PM PDT 24
Peak memory 216680 kb
Host smart-7e7e7341-624e-4742-978a-6ab2531d3e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897924003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.897924003
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3266838195
Short name T388
Test name
Test status
Simulation time 179167936154 ps
CPU time 1123.43 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 02:03:21 PM PDT 24
Peak memory 222864 kb
Host smart-f9b3d89c-17cc-4d87-bd6b-15c0037fb8e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266838195 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3266838195
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1532493674
Short name T834
Test name
Test status
Simulation time 32199892 ps
CPU time 1.32 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:39 PM PDT 24
Peak memory 215420 kb
Host smart-0dac0ffb-88fe-4348-8777-985eabef8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532493674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1532493674
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.184590592
Short name T778
Test name
Test status
Simulation time 30472201 ps
CPU time 0.93 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 206288 kb
Host smart-0481bf9a-2830-43d3-81c0-fb448aac5334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184590592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.184590592
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.4291230820
Short name T183
Test name
Test status
Simulation time 34308599 ps
CPU time 0.87 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 215988 kb
Host smart-6e57ce0c-09ff-4937-a370-1f4d4f4d2d1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291230820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4291230820
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2305054619
Short name T765
Test name
Test status
Simulation time 55658637 ps
CPU time 1.21 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 217928 kb
Host smart-4469f20e-27da-4397-b61e-a21c272cca60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305054619 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2305054619
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3824371100
Short name T736
Test name
Test status
Simulation time 27532689 ps
CPU time 0.87 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 217876 kb
Host smart-f824acba-58da-40b1-85bd-3d075600002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824371100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3824371100
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.848354732
Short name T361
Test name
Test status
Simulation time 88498945 ps
CPU time 1.22 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 216536 kb
Host smart-4bdaf60e-27cd-4be0-8dea-0b59483085c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848354732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.848354732
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3986756973
Short name T442
Test name
Test status
Simulation time 20949220 ps
CPU time 1.19 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 223512 kb
Host smart-5bf23f7a-04e0-487c-9e47-02c96d704cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986756973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3986756973
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3829633787
Short name T636
Test name
Test status
Simulation time 18525475 ps
CPU time 1.03 seconds
Started Jun 04 01:44:38 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215088 kb
Host smart-e13a3b35-5528-43ae-8ec6-eb42897d26a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829633787 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3829633787
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1569126896
Short name T377
Test name
Test status
Simulation time 65954839 ps
CPU time 1.29 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 206776 kb
Host smart-0c246739-ef2e-4f28-ad5c-aaf925485fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569126896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1569126896
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4248710944
Short name T486
Test name
Test status
Simulation time 169697273533 ps
CPU time 1942.24 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 02:17:06 PM PDT 24
Peak memory 226300 kb
Host smart-4b8d21d1-c47d-4c2b-9f62-4557c5360b57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248710944 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4248710944
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3445741708
Short name T172
Test name
Test status
Simulation time 39220372 ps
CPU time 1.14 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 215388 kb
Host smart-76dabcc6-91bf-4ec3-8c0e-7067126997d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445741708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3445741708
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3523921712
Short name T143
Test name
Test status
Simulation time 30566671 ps
CPU time 0.95 seconds
Started Jun 04 01:44:36 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 206268 kb
Host smart-2edd811f-c9c3-4d39-886f-8c21a56f45bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523921712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3523921712
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3706797488
Short name T376
Test name
Test status
Simulation time 14739545 ps
CPU time 0.94 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 216204 kb
Host smart-12532377-87df-439e-85d4-d99a39ea01d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706797488 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3706797488
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1826490461
Short name T46
Test name
Test status
Simulation time 54231225 ps
CPU time 1.09 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 218112 kb
Host smart-0baf205e-d90d-4272-8195-594f5fbb585f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826490461 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1826490461
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3527734964
Short name T705
Test name
Test status
Simulation time 27032434 ps
CPU time 1.37 seconds
Started Jun 04 01:44:38 PM PDT 24
Finished Jun 04 01:44:42 PM PDT 24
Peak memory 229388 kb
Host smart-6f7729ed-5453-4eb0-b301-2184af8e9e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527734964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3527734964
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2805634667
Short name T502
Test name
Test status
Simulation time 55802818 ps
CPU time 1.08 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:44:40 PM PDT 24
Peak memory 217944 kb
Host smart-b9e0ee48-f52a-4188-8f19-e237049ff7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805634667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2805634667
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.326483238
Short name T112
Test name
Test status
Simulation time 21071548 ps
CPU time 1.11 seconds
Started Jun 04 01:44:38 PM PDT 24
Finished Jun 04 01:44:41 PM PDT 24
Peak memory 215376 kb
Host smart-04af7852-7811-4b04-bfbe-0a2e8b4359c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326483238 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.326483238
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3660743589
Short name T375
Test name
Test status
Simulation time 56635543 ps
CPU time 0.9 seconds
Started Jun 04 01:44:35 PM PDT 24
Finished Jun 04 01:44:38 PM PDT 24
Peak memory 214968 kb
Host smart-e7008c1b-bd22-4eca-bbdb-9394647ea7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660743589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3660743589
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.141169054
Short name T142
Test name
Test status
Simulation time 539208280 ps
CPU time 3.63 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:48 PM PDT 24
Peak memory 215012 kb
Host smart-44ded198-b45b-48ac-ab08-156fc7982fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141169054 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.141169054
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1033997498
Short name T196
Test name
Test status
Simulation time 33805772399 ps
CPU time 883.67 seconds
Started Jun 04 01:44:37 PM PDT 24
Finished Jun 04 01:59:23 PM PDT 24
Peak memory 218224 kb
Host smart-cd2e53cb-1ccb-4377-9de8-dd7446805acc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033997498 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1033997498
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.3729724690
Short name T400
Test name
Test status
Simulation time 40427812 ps
CPU time 1.04 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 206308 kb
Host smart-df6164a7-d96a-4a23-bb92-bd822f3920e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729724690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3729724690
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3523714679
Short name T62
Test name
Test status
Simulation time 35342890 ps
CPU time 0.86 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 215220 kb
Host smart-c25231ef-f322-4fcd-bb8d-099f19da3d4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523714679 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3523714679
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.288323714
Short name T362
Test name
Test status
Simulation time 44411111 ps
CPU time 1.11 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 217968 kb
Host smart-f04f57c5-1986-4441-aab0-caa794359c07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288323714 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.288323714
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.301178654
Short name T1
Test name
Test status
Simulation time 34894193 ps
CPU time 1.07 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 220000 kb
Host smart-cec42723-c5ac-45e4-bb52-97a1873c98a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301178654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.301178654
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1629182608
Short name T614
Test name
Test status
Simulation time 28377037 ps
CPU time 1.46 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 219488 kb
Host smart-70d58c78-4875-4d66-ab4e-5ad4e3b4e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629182608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1629182608
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1467956119
Short name T163
Test name
Test status
Simulation time 27147033 ps
CPU time 0.96 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 215408 kb
Host smart-2306eced-49c9-4ee7-b7ed-e067f30c92e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467956119 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1467956119
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2952562962
Short name T444
Test name
Test status
Simulation time 34136529 ps
CPU time 0.96 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 215008 kb
Host smart-b40c1fbe-661d-4058-bf40-f138d44a0935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952562962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2952562962
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1831062252
Short name T597
Test name
Test status
Simulation time 457868263 ps
CPU time 2.82 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:56 PM PDT 24
Peak memory 215156 kb
Host smart-a7c2e7f5-4100-42f0-8d63-25050b8e93e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831062252 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1831062252
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3824183492
Short name T728
Test name
Test status
Simulation time 214857465847 ps
CPU time 1256.18 seconds
Started Jun 04 01:44:45 PM PDT 24
Finished Jun 04 02:05:43 PM PDT 24
Peak memory 222956 kb
Host smart-2e8f973f-9020-463b-aaa7-a97e48a16bfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824183492 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3824183492
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.898702143
Short name T70
Test name
Test status
Simulation time 185445830 ps
CPU time 1.31 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 215348 kb
Host smart-53a5e6ef-4fc6-41f7-99e3-1f60e7eee7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898702143 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.898702143
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.677665036
Short name T564
Test name
Test status
Simulation time 101791748 ps
CPU time 0.88 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:43 PM PDT 24
Peak memory 214544 kb
Host smart-962e3965-2fc8-4ffe-a174-cdfd7ba8a792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677665036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.677665036
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2511120705
Short name T523
Test name
Test status
Simulation time 13176912 ps
CPU time 0.91 seconds
Started Jun 04 01:44:40 PM PDT 24
Finished Jun 04 01:44:42 PM PDT 24
Peak memory 216232 kb
Host smart-c1a360e1-f509-49d6-8dab-a00c8ccf8e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511120705 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2511120705
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.4031470293
Short name T755
Test name
Test status
Simulation time 31957311 ps
CPU time 1.23 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 217900 kb
Host smart-95d1442b-226e-4a3d-8ef2-75e709a82aae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031470293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.4031470293
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3764698951
Short name T364
Test name
Test status
Simulation time 33365396 ps
CPU time 0.86 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:54 PM PDT 24
Peak memory 217852 kb
Host smart-b2b7a407-4547-4bed-8299-f916cb2eb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764698951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3764698951
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1981329426
Short name T673
Test name
Test status
Simulation time 78129511 ps
CPU time 1.5 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 218104 kb
Host smart-ac4d019a-d54e-4687-89a5-0bf51d48c077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981329426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1981329426
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1460657587
Short name T539
Test name
Test status
Simulation time 21723900 ps
CPU time 1.2 seconds
Started Jun 04 01:44:44 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 224452 kb
Host smart-1fd32a3c-0638-4b6d-bad3-b1108503d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460657587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1460657587
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3705895478
Short name T532
Test name
Test status
Simulation time 50580335 ps
CPU time 0.93 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 214948 kb
Host smart-a90c9739-d85e-472f-97f0-c030e775fd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705895478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3705895478
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2265617922
Short name T201
Test name
Test status
Simulation time 39149282891 ps
CPU time 734.55 seconds
Started Jun 04 01:44:40 PM PDT 24
Finished Jun 04 01:56:56 PM PDT 24
Peak memory 223404 kb
Host smart-289d4f3a-3e9b-421c-b3e9-c6994b079eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265617922 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2265617922
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2953929519
Short name T173
Test name
Test status
Simulation time 101387920 ps
CPU time 1.2 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 215412 kb
Host smart-2c1b1c08-0871-4830-92cb-8375ba8f7585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953929519 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2953929519
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3659834673
Short name T644
Test name
Test status
Simulation time 22450122 ps
CPU time 0.94 seconds
Started Jun 04 01:44:46 PM PDT 24
Finished Jun 04 01:44:48 PM PDT 24
Peak memory 206192 kb
Host smart-a678bcc6-0645-46db-b22e-e1708c0b15b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659834673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3659834673
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3077847448
Short name T489
Test name
Test status
Simulation time 27652582 ps
CPU time 0.8 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 215728 kb
Host smart-0b01b1c5-b9cf-4f26-8ea6-c5b20564c710
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077847448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3077847448
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.1912329614
Short name T299
Test name
Test status
Simulation time 42203346 ps
CPU time 1.17 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 216660 kb
Host smart-59a4901b-44e1-4777-b7e4-04cfaca684a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912329614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.1912329614
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2951727380
Short name T79
Test name
Test status
Simulation time 34202780 ps
CPU time 0.93 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 218004 kb
Host smart-bf721d26-af8c-4970-bf55-5ce52ff8c83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951727380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2951727380
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1097064216
Short name T463
Test name
Test status
Simulation time 44034354 ps
CPU time 1.54 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 217916 kb
Host smart-96e688b5-66ff-424e-94ed-ce7a91f5ec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097064216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1097064216
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2135817133
Short name T382
Test name
Test status
Simulation time 26018356 ps
CPU time 0.96 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:44:49 PM PDT 24
Peak memory 215052 kb
Host smart-0ed42910-c882-4fff-898c-54bdd48b7222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135817133 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2135817133
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2709881149
Short name T671
Test name
Test status
Simulation time 18351423 ps
CPU time 1.01 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:44:49 PM PDT 24
Peak memory 214884 kb
Host smart-3ceb7d7f-9f4d-4bec-b2f8-4547ce86e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709881149 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2709881149
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.373580738
Short name T550
Test name
Test status
Simulation time 319984905 ps
CPU time 6.12 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:59 PM PDT 24
Peak memory 216504 kb
Host smart-d472923b-b139-4b47-9c1b-60278ecb5c46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373580738 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.373580738
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.4176772791
Short name T461
Test name
Test status
Simulation time 1296031360649 ps
CPU time 2558.72 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 02:27:24 PM PDT 24
Peak memory 228176 kb
Host smart-2e2a8fa9-ecfa-41e7-998f-1dcab7573729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176772791 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.4176772791
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3253222876
Short name T686
Test name
Test status
Simulation time 38717870 ps
CPU time 1.17 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 215388 kb
Host smart-d79b0d72-71c4-40a0-98cb-b6bd79b75c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253222876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3253222876
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1691021233
Short name T127
Test name
Test status
Simulation time 16657341 ps
CPU time 1.01 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:43 PM PDT 24
Peak memory 206316 kb
Host smart-b7c1e907-499f-4f54-91df-2ee6f43d24c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691021233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1691021233
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.921878927
Short name T336
Test name
Test status
Simulation time 96669187 ps
CPU time 0.86 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:43 PM PDT 24
Peak memory 215864 kb
Host smart-6d4d15e9-56b7-491a-a5a9-020bbced1dba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921878927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.921878927
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.352863169
Short name T591
Test name
Test status
Simulation time 46718589 ps
CPU time 1.03 seconds
Started Jun 04 01:44:45 PM PDT 24
Finished Jun 04 01:44:48 PM PDT 24
Peak memory 217776 kb
Host smart-d74662c9-fcc6-4055-8211-bad71d3149f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352863169 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.352863169
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.3627158932
Short name T726
Test name
Test status
Simulation time 20997221 ps
CPU time 1.2 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:54 PM PDT 24
Peak memory 229124 kb
Host smart-f51833c8-f5ac-43ed-ab54-83702ed5b996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627158932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3627158932
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1076532747
Short name T122
Test name
Test status
Simulation time 43913692 ps
CPU time 1.65 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 218332 kb
Host smart-45e8abc2-e1c8-4160-86c9-7e26ad6d51ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076532747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1076532747
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.246697063
Short name T476
Test name
Test status
Simulation time 27574656 ps
CPU time 0.98 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 215288 kb
Host smart-b48b7224-b5e2-49fe-97b3-ac356f694bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246697063 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.246697063
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.593967961
Short name T581
Test name
Test status
Simulation time 38010051 ps
CPU time 0.9 seconds
Started Jun 04 01:44:44 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 214976 kb
Host smart-df1703cd-0e84-48b8-b506-bf4a9a95be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593967961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.593967961
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.890634913
Short name T206
Test name
Test status
Simulation time 37306689 ps
CPU time 1.31 seconds
Started Jun 04 01:44:44 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 206424 kb
Host smart-a7b66571-9670-48b7-99db-d6476a6b14b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890634913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.890634913
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3908292313
Short name T633
Test name
Test status
Simulation time 412648853498 ps
CPU time 2389.49 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 02:24:33 PM PDT 24
Peak memory 234552 kb
Host smart-5942c40d-9e30-4891-ad6b-d97f7f9584fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908292313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3908292313
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3977437608
Short name T730
Test name
Test status
Simulation time 149760636 ps
CPU time 1.19 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:54 PM PDT 24
Peak memory 215416 kb
Host smart-9cdf9197-213a-48f3-9e35-9e222b362747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977437608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3977437608
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.307426442
Short name T407
Test name
Test status
Simulation time 22449371 ps
CPU time 0.84 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 206152 kb
Host smart-de1b427d-677b-4749-8aff-7be658e7998c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307426442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.307426442
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1622966665
Short name T25
Test name
Test status
Simulation time 11268462 ps
CPU time 0.88 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 215264 kb
Host smart-089ecfb5-84e1-475a-8d79-0c168d450cdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622966665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1622966665
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.219528532
Short name T466
Test name
Test status
Simulation time 46091548 ps
CPU time 1.11 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 216688 kb
Host smart-41229ac6-5179-409a-a386-03f9b5f5c1c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219528532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.219528532
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2474259277
Short name T64
Test name
Test status
Simulation time 21550715 ps
CPU time 1.02 seconds
Started Jun 04 01:44:45 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 217936 kb
Host smart-923928c4-9c98-4c17-be9b-22c29561e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474259277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2474259277
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.404711024
Short name T298
Test name
Test status
Simulation time 45355465 ps
CPU time 1.42 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 218004 kb
Host smart-bb243d85-1738-4743-a9ec-11b81c0ae3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404711024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.404711024
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3863201893
Short name T612
Test name
Test status
Simulation time 21260780 ps
CPU time 1.29 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 223632 kb
Host smart-d101f772-3238-49d7-81ab-7926c56d8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863201893 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3863201893
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2069526362
Short name T567
Test name
Test status
Simulation time 19099625 ps
CPU time 1.03 seconds
Started Jun 04 01:44:43 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 214904 kb
Host smart-707b82ba-3069-4b8f-8eac-95589c6313dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069526362 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2069526362
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1480151793
Short name T491
Test name
Test status
Simulation time 233252409 ps
CPU time 4.94 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:49 PM PDT 24
Peak memory 216564 kb
Host smart-e8109cfb-b492-4f42-85fe-e4d3870380be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480151793 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1480151793
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3429577030
Short name T813
Test name
Test status
Simulation time 16729725110 ps
CPU time 193.63 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:48:02 PM PDT 24
Peak memory 220724 kb
Host smart-a0d9f4f9-5113-4abc-90b9-4fbfd6fd8083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429577030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3429577030
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2147616147
Short name T271
Test name
Test status
Simulation time 87629995 ps
CPU time 1.16 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 215260 kb
Host smart-e08a08d9-5170-4a06-b95a-3b1ef397524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147616147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2147616147
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.686619655
Short name T213
Test name
Test status
Simulation time 62381058 ps
CPU time 0.91 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 206308 kb
Host smart-21b2a504-4486-4396-b3c4-01a0a31efe16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686619655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.686619655
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1404014355
Short name T781
Test name
Test status
Simulation time 12069509 ps
CPU time 0.88 seconds
Started Jun 04 01:44:44 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 215708 kb
Host smart-adad6ebf-cd12-497e-9816-03ba2231dd7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404014355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1404014355
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1851522139
Short name T748
Test name
Test status
Simulation time 55335272 ps
CPU time 1.18 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:46 PM PDT 24
Peak memory 216656 kb
Host smart-9ba4462c-5586-4ac0-a17e-88e118298743
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851522139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1851522139
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1097746430
Short name T391
Test name
Test status
Simulation time 30537407 ps
CPU time 0.87 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:45 PM PDT 24
Peak memory 218908 kb
Host smart-3c8abe38-4a69-4e4b-8f0a-f8ca5460e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097746430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1097746430
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.642404266
Short name T750
Test name
Test status
Simulation time 64931278 ps
CPU time 1.43 seconds
Started Jun 04 01:44:45 PM PDT 24
Finished Jun 04 01:44:48 PM PDT 24
Peak memory 217968 kb
Host smart-1effed10-6a4d-4285-a53b-f4d0f36b62b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642404266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.642404266
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.490333329
Short name T168
Test name
Test status
Simulation time 22834669 ps
CPU time 1.01 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:43 PM PDT 24
Peak memory 215516 kb
Host smart-8f0281d1-0ae6-48a2-aa56-2cace9b4005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490333329 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.490333329
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1432841991
Short name T347
Test name
Test status
Simulation time 29398990 ps
CPU time 0.97 seconds
Started Jun 04 01:44:41 PM PDT 24
Finished Jun 04 01:44:44 PM PDT 24
Peak memory 215028 kb
Host smart-87023ccb-c510-494e-a303-b3fc12e7743d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432841991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1432841991
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2507818264
Short name T464
Test name
Test status
Simulation time 460530579 ps
CPU time 1.95 seconds
Started Jun 04 01:44:42 PM PDT 24
Finished Jun 04 01:44:47 PM PDT 24
Peak memory 216736 kb
Host smart-d832f929-7b20-4633-80ed-05e3ffa39d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507818264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2507818264
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2658471925
Short name T544
Test name
Test status
Simulation time 33578944507 ps
CPU time 756.11 seconds
Started Jun 04 01:44:40 PM PDT 24
Finished Jun 04 01:57:18 PM PDT 24
Peak memory 216820 kb
Host smart-9001094f-dc21-4e36-9322-780c15bb4cce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658471925 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2658471925
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3063990540
Short name T253
Test name
Test status
Simulation time 98546025 ps
CPU time 1.23 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:56 PM PDT 24
Peak memory 215412 kb
Host smart-bec3b092-7e62-4309-97f2-87ad8e13726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063990540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3063990540
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3771288531
Short name T625
Test name
Test status
Simulation time 41290777 ps
CPU time 0.84 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 206148 kb
Host smart-9bc007dd-9f35-4d5e-be82-051649814d73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771288531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3771288531
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2729931915
Short name T389
Test name
Test status
Simulation time 12425362 ps
CPU time 0.87 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:54 PM PDT 24
Peak memory 215872 kb
Host smart-428c915c-f8d2-4b91-b68b-c06767379fa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729931915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2729931915
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1354838477
Short name T582
Test name
Test status
Simulation time 84971104 ps
CPU time 1.08 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 219120 kb
Host smart-7bea807d-9c9c-4543-92b8-414023815896
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354838477 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1354838477
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3129347637
Short name T732
Test name
Test status
Simulation time 33220870 ps
CPU time 0.99 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 228448 kb
Host smart-3e5ace6b-a41f-442c-86d9-7a1e14e72f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129347637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3129347637
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1117657053
Short name T548
Test name
Test status
Simulation time 85641500 ps
CPU time 1.07 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 01:44:59 PM PDT 24
Peak memory 216608 kb
Host smart-4367c468-4d10-41d8-8cb8-3bc17a155217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117657053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1117657053
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1446391430
Short name T767
Test name
Test status
Simulation time 26231892 ps
CPU time 1.11 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:58 PM PDT 24
Peak memory 223576 kb
Host smart-82cbd844-8546-4d1c-9ef0-a81b4ab3fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446391430 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1446391430
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3237096197
Short name T311
Test name
Test status
Simulation time 20254437 ps
CPU time 1.05 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 215000 kb
Host smart-e5fb58ca-4940-4ca5-9a6e-b315c8f2da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237096197 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3237096197
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.661984438
Short name T720
Test name
Test status
Simulation time 553193262 ps
CPU time 5.76 seconds
Started Jun 04 01:44:54 PM PDT 24
Finished Jun 04 01:45:01 PM PDT 24
Peak memory 216584 kb
Host smart-8ee3842d-f387-4150-abaa-1c520efccd1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661984438 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.661984438
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2670715072
Short name T204
Test name
Test status
Simulation time 317973509283 ps
CPU time 684.51 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:56:15 PM PDT 24
Peak memory 219476 kb
Host smart-61dea57d-8658-4ff8-a09e-926657dc6eb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670715072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2670715072
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3167268063
Short name T28
Test name
Test status
Simulation time 27544353 ps
CPU time 1.29 seconds
Started Jun 04 01:43:46 PM PDT 24
Finished Jun 04 01:43:48 PM PDT 24
Peak memory 215512 kb
Host smart-79c34036-c0e7-4472-946a-ad70c9a48205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167268063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3167268063
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3952445642
Short name T421
Test name
Test status
Simulation time 49300287 ps
CPU time 0.89 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:54 PM PDT 24
Peak memory 206340 kb
Host smart-53c4be98-d900-4b9f-b98e-32d5f7a8c715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952445642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3952445642
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1908449308
Short name T749
Test name
Test status
Simulation time 38417121 ps
CPU time 0.87 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:52 PM PDT 24
Peak memory 216052 kb
Host smart-d018ba18-9c7d-45c9-a593-6537b1b9dca1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908449308 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1908449308
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.820461607
Short name T47
Test name
Test status
Simulation time 107487523 ps
CPU time 1.07 seconds
Started Jun 04 01:43:57 PM PDT 24
Finished Jun 04 01:43:59 PM PDT 24
Peak memory 219200 kb
Host smart-f004b554-32b8-4d11-9011-6190588db657
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820461607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.820461607
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.1317190792
Short name T66
Test name
Test status
Simulation time 19356026 ps
CPU time 1.13 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:52 PM PDT 24
Peak memory 223448 kb
Host smart-8675a0ae-1da1-482c-aa68-3f72ea101451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317190792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1317190792
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3702883963
Short name T638
Test name
Test status
Simulation time 165954484 ps
CPU time 2.41 seconds
Started Jun 04 01:43:41 PM PDT 24
Finished Jun 04 01:43:45 PM PDT 24
Peak memory 218092 kb
Host smart-35ee52eb-9e2e-4b21-9d2f-d38d06e5e15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702883963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3702883963
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2132995293
Short name T167
Test name
Test status
Simulation time 20637233 ps
CPU time 1.06 seconds
Started Jun 04 01:43:48 PM PDT 24
Finished Jun 04 01:43:50 PM PDT 24
Peak memory 215384 kb
Host smart-49fdd5ba-db97-42ef-b557-62bb42251456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132995293 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2132995293
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1023104725
Short name T675
Test name
Test status
Simulation time 16056338 ps
CPU time 1 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 206080 kb
Host smart-4d38ed50-e2e1-4756-96dc-113e3a101c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023104725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1023104725
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3413218491
Short name T462
Test name
Test status
Simulation time 44487534 ps
CPU time 0.91 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:46 PM PDT 24
Peak memory 215024 kb
Host smart-d4082a3b-dc2b-4ef5-a4c1-9845cff35142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413218491 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3413218491
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.351187798
Short name T205
Test name
Test status
Simulation time 143772549 ps
CPU time 3.18 seconds
Started Jun 04 01:43:44 PM PDT 24
Finished Jun 04 01:43:49 PM PDT 24
Peak memory 214992 kb
Host smart-2c995c3e-1fec-43bc-ada4-b23255a10aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351187798 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.351187798
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.4080779859
Short name T650
Test name
Test status
Simulation time 335091857039 ps
CPU time 2071.03 seconds
Started Jun 04 01:43:45 PM PDT 24
Finished Jun 04 02:18:17 PM PDT 24
Peak memory 226344 kb
Host smart-a26a7c4c-5fcd-4d7b-b782-467a23997c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080779859 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.4080779859
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.271488178
Short name T268
Test name
Test status
Simulation time 234652041 ps
CPU time 1.29 seconds
Started Jun 04 01:44:52 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 215424 kb
Host smart-3a355ef3-9e33-4b31-b503-e3c198762d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271488178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.271488178
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3348903685
Short name T332
Test name
Test status
Simulation time 17563755 ps
CPU time 1 seconds
Started Jun 04 01:44:46 PM PDT 24
Finished Jun 04 01:44:48 PM PDT 24
Peak memory 214520 kb
Host smart-2fc262e1-7e6c-4df0-a0da-033a1153f694
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348903685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3348903685
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.3787559552
Short name T449
Test name
Test status
Simulation time 36092558 ps
CPU time 0.89 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 215812 kb
Host smart-030e4570-9abb-4ae0-adae-6a5259c4d9c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787559552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.3787559552
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.465962649
Short name T478
Test name
Test status
Simulation time 27494485 ps
CPU time 1.29 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:53 PM PDT 24
Peak memory 219576 kb
Host smart-88915ac9-41c7-4e28-bd62-eabe7905a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465962649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.465962649
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3298814192
Short name T573
Test name
Test status
Simulation time 30140895 ps
CPU time 1.3 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:53 PM PDT 24
Peak memory 216888 kb
Host smart-a818f129-c503-465c-ad42-cadb351a1f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298814192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3298814192
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3039033385
Short name T108
Test name
Test status
Simulation time 26467117 ps
CPU time 0.97 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 215512 kb
Host smart-bcba5e43-248e-491d-b9b4-c50659abe302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039033385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3039033385
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1060488919
Short name T733
Test name
Test status
Simulation time 27029190 ps
CPU time 0.95 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 214908 kb
Host smart-2d9fd274-ce1b-4519-868e-7f6fb88c4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060488919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1060488919
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.514895661
Short name T713
Test name
Test status
Simulation time 106074417 ps
CPU time 2.52 seconds
Started Jun 04 01:44:54 PM PDT 24
Finished Jun 04 01:44:58 PM PDT 24
Peak memory 217800 kb
Host smart-cdc4ad9c-e96b-42ae-bffe-25defd398ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514895661 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.514895661
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.41009334
Short name T454
Test name
Test status
Simulation time 99913614842 ps
CPU time 1487.95 seconds
Started Jun 04 01:44:51 PM PDT 24
Finished Jun 04 02:09:40 PM PDT 24
Peak memory 224388 kb
Host smart-57906a69-f73a-4863-b905-8255046f0bd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41009334 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.41009334
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3551424277
Short name T265
Test name
Test status
Simulation time 25619726 ps
CPU time 1.26 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 215384 kb
Host smart-fdc69b2e-c4ed-4e81-a581-aabe47dd2a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551424277 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3551424277
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3261603156
Short name T779
Test name
Test status
Simulation time 53166503 ps
CPU time 0.89 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 214020 kb
Host smart-22bc2f1c-8b1c-4e73-a869-d4cd7d974c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261603156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3261603156
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3868521399
Short name T155
Test name
Test status
Simulation time 33465172 ps
CPU time 0.88 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 216192 kb
Host smart-5433892f-4f0d-469f-8ad1-c45f7c9fa83b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868521399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3868521399
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.1466786177
Short name T836
Test name
Test status
Simulation time 24948862 ps
CPU time 0.97 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 219336 kb
Host smart-a461e8f5-e943-4ee1-a14d-2b2bbe3628a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466786177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1466786177
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3164005395
Short name T147
Test name
Test status
Simulation time 67171152 ps
CPU time 1.26 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 218356 kb
Host smart-b0997d7a-2e53-4fd6-8f8d-3bd3c79ffd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164005395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3164005395
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_smoke.3659501534
Short name T338
Test name
Test status
Simulation time 33111836 ps
CPU time 0.99 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 01:44:59 PM PDT 24
Peak memory 214992 kb
Host smart-c1ea7549-ffb4-49a9-aa08-2cbb589a2c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659501534 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3659501534
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.993195806
Short name T453
Test name
Test status
Simulation time 177787485 ps
CPU time 3.73 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 215068 kb
Host smart-27fdc835-16a7-41b9-bd8d-3af0764218d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993195806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.993195806
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.670202974
Short name T144
Test name
Test status
Simulation time 85202840548 ps
CPU time 2213.34 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 02:21:52 PM PDT 24
Peak memory 229844 kb
Host smart-ad547d68-ca35-47f3-b0ab-2bd05f01dc11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670202974 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.670202974
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2206245319
Short name T264
Test name
Test status
Simulation time 93064809 ps
CPU time 1.24 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:44:49 PM PDT 24
Peak memory 215368 kb
Host smart-9bf65227-8858-46e0-ae5c-03d4af7a202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206245319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2206245319
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1474435093
Short name T354
Test name
Test status
Simulation time 179547835 ps
CPU time 0.94 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 206300 kb
Host smart-529e6475-e7ff-4982-9ff7-6f605228255c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474435093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1474435093
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.206446893
Short name T829
Test name
Test status
Simulation time 156869004 ps
CPU time 1.33 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 216684 kb
Host smart-ab0eceae-7f30-4233-ab68-3ad7b9f9e7cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206446893 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.206446893
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_genbits.1139362588
Short name T632
Test name
Test status
Simulation time 61112090 ps
CPU time 1.17 seconds
Started Jun 04 01:44:53 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 218388 kb
Host smart-3e5054db-5490-408e-b5be-1e47c6972f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139362588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1139362588
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.4064367116
Short name T374
Test name
Test status
Simulation time 22454236 ps
CPU time 1.19 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:53 PM PDT 24
Peak memory 223612 kb
Host smart-5bca43a5-c6b3-4b52-9bee-27505fd81d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064367116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4064367116
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1385732108
Short name T356
Test name
Test status
Simulation time 44470746 ps
CPU time 0.97 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 214864 kb
Host smart-6d50776c-c0e7-4a1d-b309-d86ddedcd953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385732108 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1385732108
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3312962249
Short name T752
Test name
Test status
Simulation time 496909760 ps
CPU time 6.05 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:05 PM PDT 24
Peak memory 219596 kb
Host smart-94be437d-28e3-4fe2-99de-dc95a433181d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312962249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3312962249
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3928169209
Short name T115
Test name
Test status
Simulation time 84118498442 ps
CPU time 533.06 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:53:44 PM PDT 24
Peak memory 218692 kb
Host smart-7bf0d787-ba56-48d9-9999-f397810d7fbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928169209 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3928169209
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2540925202
Short name T830
Test name
Test status
Simulation time 51960386 ps
CPU time 1.29 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 215420 kb
Host smart-b7e339d0-2515-4a2b-ade4-733bb5dfdebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540925202 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2540925202
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2211556911
Short name T833
Test name
Test status
Simulation time 17637450 ps
CPU time 0.9 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 206292 kb
Host smart-8b705953-4346-4e26-bb5f-c7ed144f8c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211556911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2211556911
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3055446424
Short name T457
Test name
Test status
Simulation time 84092832 ps
CPU time 1.26 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 218004 kb
Host smart-e495e4ca-5502-4c1b-95e4-edf1fe7ed059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055446424 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3055446424
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3291582439
Short name T99
Test name
Test status
Simulation time 61955096 ps
CPU time 0.8 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:57 PM PDT 24
Peak memory 218844 kb
Host smart-070e41c4-626e-4fd7-8db9-790a85521e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291582439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3291582439
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3364138172
Short name T212
Test name
Test status
Simulation time 143191121 ps
CPU time 1.14 seconds
Started Jun 04 01:44:49 PM PDT 24
Finished Jun 04 01:44:52 PM PDT 24
Peak memory 216888 kb
Host smart-d83477b7-2c01-4757-85c7-cb45487d8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364138172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3364138172
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3446122457
Short name T387
Test name
Test status
Simulation time 23681244 ps
CPU time 1.05 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:44:51 PM PDT 24
Peak memory 223500 kb
Host smart-d1e596e3-5ced-4e29-afa6-03c60dab049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446122457 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3446122457
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.734971170
Short name T505
Test name
Test status
Simulation time 24804505 ps
CPU time 0.9 seconds
Started Jun 04 01:44:47 PM PDT 24
Finished Jun 04 01:44:50 PM PDT 24
Peak memory 214992 kb
Host smart-02305dd2-be48-414c-a222-ecf181a3c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734971170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.734971170
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1837642993
Short name T842
Test name
Test status
Simulation time 603368584 ps
CPU time 4.17 seconds
Started Jun 04 01:44:50 PM PDT 24
Finished Jun 04 01:44:55 PM PDT 24
Peak memory 214940 kb
Host smart-33b9b43a-2fdf-4b09-b125-c9ffeb2bf749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837642993 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1837642993
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1982498049
Short name T170
Test name
Test status
Simulation time 83205142711 ps
CPU time 886.21 seconds
Started Jun 04 01:44:48 PM PDT 24
Finished Jun 04 01:59:35 PM PDT 24
Peak memory 223392 kb
Host smart-99aee2c9-d7ce-4b3d-b2dc-2aca622639b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982498049 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1982498049
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.3464809147
Short name T839
Test name
Test status
Simulation time 37825417 ps
CPU time 1.4 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:01 PM PDT 24
Peak memory 215484 kb
Host smart-5de1b65d-5e07-4aa3-8dba-7ee1a72e52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464809147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3464809147
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2242098511
Short name T441
Test name
Test status
Simulation time 13201541 ps
CPU time 0.92 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 206228 kb
Host smart-4b62ee12-190a-48b0-b265-ce5449a16e3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242098511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2242098511
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1967805467
Short name T674
Test name
Test status
Simulation time 21757015 ps
CPU time 0.85 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 01:45:06 PM PDT 24
Peak memory 215868 kb
Host smart-8bd3e961-6444-4f8f-9778-00710c751bea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967805467 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1967805467
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2637188322
Short name T38
Test name
Test status
Simulation time 25347217 ps
CPU time 1.09 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 216776 kb
Host smart-dcf1f154-6960-4a76-b51f-30520681a9dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637188322 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2637188322
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3596634276
Short name T89
Test name
Test status
Simulation time 29464539 ps
CPU time 0.87 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 217892 kb
Host smart-dc98b53f-0ad4-4ae9-b2f2-9ec6c7c30ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596634276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3596634276
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2132128015
Short name T409
Test name
Test status
Simulation time 77843421 ps
CPU time 1.6 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:58 PM PDT 24
Peak memory 218168 kb
Host smart-b9d1fd4d-6692-40a4-bd38-a0d0b97cf14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132128015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2132128015
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2455246805
Short name T113
Test name
Test status
Simulation time 20881574 ps
CPU time 1.09 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 215480 kb
Host smart-313bce06-76ac-4a69-b553-321457276131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455246805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2455246805
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3237843917
Short name T795
Test name
Test status
Simulation time 48581765 ps
CPU time 0.97 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 215036 kb
Host smart-4d33ad90-d298-4753-95dc-e4f41bea025e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237843917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3237843917
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.618781855
Short name T436
Test name
Test status
Simulation time 40753490 ps
CPU time 1.01 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 206164 kb
Host smart-11d4763c-1718-4dc8-817e-dd0db88ed979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618781855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.618781855
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.281739989
Short name T737
Test name
Test status
Simulation time 13191188159 ps
CPU time 154.2 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 01:47:32 PM PDT 24
Peak memory 217528 kb
Host smart-5cd758f4-7d48-457c-b01b-fb955657bf0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281739989 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.281739989
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2191670063
Short name T699
Test name
Test status
Simulation time 52105364 ps
CPU time 1.33 seconds
Started Jun 04 01:44:55 PM PDT 24
Finished Jun 04 01:44:59 PM PDT 24
Peak memory 215360 kb
Host smart-92b60d41-d5a0-4578-b7d2-4cad2ab09903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191670063 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2191670063
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.75911693
Short name T537
Test name
Test status
Simulation time 83562299 ps
CPU time 1.01 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 206340 kb
Host smart-e938a618-9a83-4c38-849a-c2318f52a04b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75911693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.75911693
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3643206118
Short name T637
Test name
Test status
Simulation time 21615299 ps
CPU time 0.92 seconds
Started Jun 04 01:44:56 PM PDT 24
Finished Jun 04 01:44:59 PM PDT 24
Peak memory 215212 kb
Host smart-03970780-f8d4-46fd-b9d8-66a144acab68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643206118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3643206118
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2060524098
Short name T828
Test name
Test status
Simulation time 164490457 ps
CPU time 1.17 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 216616 kb
Host smart-7abd8f01-af0d-4a81-a1e4-5a22d6bc9aa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060524098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2060524098
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3421525021
Short name T181
Test name
Test status
Simulation time 20918718 ps
CPU time 1.09 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 219032 kb
Host smart-9034cda5-e4e1-49bd-af6f-2fc27e0e00f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421525021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3421525021
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2252389336
Short name T610
Test name
Test status
Simulation time 34029171 ps
CPU time 1.08 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 01:45:05 PM PDT 24
Peak memory 216616 kb
Host smart-8f3971d6-a94c-42e9-9840-834234ce5e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252389336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2252389336
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.136748033
Short name T739
Test name
Test status
Simulation time 21521644 ps
CPU time 1.12 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 215380 kb
Host smart-da9981b4-eba7-4adf-86df-e40b592ad82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136748033 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.136748033
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3889381064
Short name T653
Test name
Test status
Simulation time 49713196 ps
CPU time 1.03 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 214892 kb
Host smart-d7c6115c-0a98-452a-8b51-af981dfafff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889381064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3889381064
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1099847291
Short name T745
Test name
Test status
Simulation time 432298559 ps
CPU time 2.95 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 214968 kb
Host smart-5a61f7ff-abb3-4513-a197-c27e0c56113a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099847291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1099847291
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2283678690
Short name T601
Test name
Test status
Simulation time 83402111994 ps
CPU time 905.48 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 02:00:09 PM PDT 24
Peak memory 220968 kb
Host smart-512b90c3-a9b1-4007-91e0-5f35b0660970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283678690 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2283678690
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.534761906
Short name T263
Test name
Test status
Simulation time 45307465 ps
CPU time 1.28 seconds
Started Jun 04 01:44:54 PM PDT 24
Finished Jun 04 01:44:56 PM PDT 24
Peak memory 215416 kb
Host smart-1950f262-bc0d-45b8-a1a3-ad5153b60d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534761906 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.534761906
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1778069315
Short name T680
Test name
Test status
Simulation time 48544424 ps
CPU time 0.91 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 206324 kb
Host smart-7646e19f-88b4-41c6-a8e6-d876263458f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778069315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1778069315
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3171134384
Short name T596
Test name
Test status
Simulation time 18416232 ps
CPU time 0.87 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 215896 kb
Host smart-8bf375a5-23de-4465-ba1e-a6cc91cbb514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171134384 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3171134384
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3949335393
Short name T41
Test name
Test status
Simulation time 68298849 ps
CPU time 1.33 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:01 PM PDT 24
Peak memory 216652 kb
Host smart-02f9a58b-b164-4d71-9412-8cf80e1ef9a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949335393 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3949335393
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3269529243
Short name T36
Test name
Test status
Simulation time 37725340 ps
CPU time 0.97 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 219024 kb
Host smart-2cb35048-278d-45a7-b92d-cdad4e787f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269529243 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3269529243
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3766267370
Short name T506
Test name
Test status
Simulation time 234251155 ps
CPU time 3.4 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 219712 kb
Host smart-8ad4840c-5344-4548-9cb8-df8c6479da3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766267370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3766267370
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.452296638
Short name T3
Test name
Test status
Simulation time 39456494 ps
CPU time 0.96 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 215372 kb
Host smart-e2c7533c-889b-407e-a06c-a7e5a6902e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452296638 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.452296638
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.4279499261
Short name T483
Test name
Test status
Simulation time 15618191 ps
CPU time 1.02 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 215004 kb
Host smart-e777c064-b766-48d6-ab2f-f12fa63da9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279499261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.4279499261
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1869805384
Short name T23
Test name
Test status
Simulation time 27103615 ps
CPU time 1.13 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 01:45:05 PM PDT 24
Peak memory 215044 kb
Host smart-0ded008b-0640-473a-84c3-30107af9aa31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869805384 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1869805384
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3989648053
Short name T365
Test name
Test status
Simulation time 92247828244 ps
CPU time 2110.98 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 02:20:13 PM PDT 24
Peak memory 226960 kb
Host smart-505914fd-ed24-4081-9db7-aceb2e08eaaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989648053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3989648053
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2159233503
Short name T631
Test name
Test status
Simulation time 25928925 ps
CPU time 1.27 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:03 PM PDT 24
Peak memory 215396 kb
Host smart-1e592719-b5a3-4227-ada4-e18444e07de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159233503 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2159233503
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.728296310
Short name T822
Test name
Test status
Simulation time 19992278 ps
CPU time 1.14 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 214492 kb
Host smart-bd0ae865-6060-4105-9d7e-26509d6d92f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728296310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.728296310
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4203724485
Short name T475
Test name
Test status
Simulation time 13512007 ps
CPU time 0.91 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:01 PM PDT 24
Peak memory 215880 kb
Host smart-def9c017-6af2-4b56-8a11-1230b528ea9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203724485 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4203724485
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.571060229
Short name T578
Test name
Test status
Simulation time 36035028 ps
CPU time 1.27 seconds
Started Jun 04 01:45:03 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 217768 kb
Host smart-8bfc1ae6-3007-4e44-8085-7e3917f64c5f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571060229 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.571060229
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1985225000
Short name T51
Test name
Test status
Simulation time 34569889 ps
CPU time 1.09 seconds
Started Jun 04 01:44:57 PM PDT 24
Finished Jun 04 01:45:00 PM PDT 24
Peak memory 220008 kb
Host smart-db9ce38e-5854-48fc-8fbf-c0599055f76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985225000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1985225000
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3844640739
Short name T399
Test name
Test status
Simulation time 154840988 ps
CPU time 3.56 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 01:45:08 PM PDT 24
Peak memory 219732 kb
Host smart-9a80d1ad-29ad-447c-9434-23fcfd636684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844640739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3844640739
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2573548300
Short name T351
Test name
Test status
Simulation time 22210764 ps
CPU time 1.1 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 01:45:06 PM PDT 24
Peak memory 215336 kb
Host smart-5c4ccfe2-a972-45ad-ad05-aa303186636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573548300 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2573548300
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2954751587
Short name T398
Test name
Test status
Simulation time 17710237 ps
CPU time 1.04 seconds
Started Jun 04 01:44:58 PM PDT 24
Finished Jun 04 01:45:02 PM PDT 24
Peak memory 214840 kb
Host smart-58aa1e57-b8e2-4a2b-87c4-c9b2cc7bc0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954751587 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2954751587
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1432516612
Short name T459
Test name
Test status
Simulation time 159657106 ps
CPU time 3.58 seconds
Started Jun 04 01:44:59 PM PDT 24
Finished Jun 04 01:45:06 PM PDT 24
Peak memory 215020 kb
Host smart-9a0faaea-b88f-4c7e-a115-a176199f5f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432516612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1432516612
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.3449555343
Short name T801
Test name
Test status
Simulation time 229650722 ps
CPU time 1.35 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 215404 kb
Host smart-79f4f530-0b19-431d-b27e-41d366deb868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449555343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3449555343
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.604171682
Short name T309
Test name
Test status
Simulation time 24011975 ps
CPU time 1.06 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 206348 kb
Host smart-c32c1139-2cfa-46e2-a1d2-ea9cb02a48f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604171682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.604171682
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3535443073
Short name T185
Test name
Test status
Simulation time 57138936 ps
CPU time 0.83 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 216040 kb
Host smart-451ea5aa-ccf4-408c-a962-0f3deadda13b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535443073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3535443073
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1353367016
Short name T799
Test name
Test status
Simulation time 78919991 ps
CPU time 0.92 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 216504 kb
Host smart-a9d2942a-ec8b-468e-8439-4eb9509d0035
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353367016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1353367016
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3133010805
Short name T169
Test name
Test status
Simulation time 54092180 ps
CPU time 0.82 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 218104 kb
Host smart-59fc7cd7-05f8-45bf-9e33-0d42533c7bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133010805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3133010805
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1465772311
Short name T286
Test name
Test status
Simulation time 86241120 ps
CPU time 2.09 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 219380 kb
Host smart-045f12b0-12e2-4b2c-b7ef-65b9cabc44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465772311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1465772311
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3759858408
Short name T130
Test name
Test status
Simulation time 21734684 ps
CPU time 1.19 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 223612 kb
Host smart-fecf6e84-a46c-4478-b5d1-16fd3990ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759858408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3759858408
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3185232989
Short name T589
Test name
Test status
Simulation time 30402429 ps
CPU time 0.98 seconds
Started Jun 04 01:45:06 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 206800 kb
Host smart-7f654f5d-5695-46e0-a707-f0a66a15ab1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185232989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3185232989
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1428766557
Short name T103
Test name
Test status
Simulation time 376871663 ps
CPU time 2.74 seconds
Started Jun 04 01:45:06 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 216584 kb
Host smart-50813cde-5149-49f9-b74c-beeba1049efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428766557 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1428766557
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1479519226
Short name T526
Test name
Test status
Simulation time 99369726239 ps
CPU time 577.77 seconds
Started Jun 04 01:45:06 PM PDT 24
Finished Jun 04 01:54:47 PM PDT 24
Peak memory 219168 kb
Host smart-d6ad3855-6e73-4603-a3ea-cc8900507788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479519226 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1479519226
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1088168931
Short name T75
Test name
Test status
Simulation time 56877269 ps
CPU time 1.06 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 215328 kb
Host smart-25c1c55c-4bc3-44ef-9ea9-1dc9a973cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088168931 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1088168931
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.2899984171
Short name T314
Test name
Test status
Simulation time 18423641 ps
CPU time 0.98 seconds
Started Jun 04 01:45:00 PM PDT 24
Finished Jun 04 01:45:04 PM PDT 24
Peak memory 206388 kb
Host smart-c2fae026-854b-4b9c-979c-44f01f11a038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899984171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2899984171
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.927870874
Short name T80
Test name
Test status
Simulation time 13170532 ps
CPU time 0.92 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 216232 kb
Host smart-0bf08e9a-8bfd-48a2-92e9-1836275ac4aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927870874 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.927870874
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.91157887
Short name T40
Test name
Test status
Simulation time 43892955 ps
CPU time 1.17 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 216452 kb
Host smart-cd2c4edb-603f-45d1-afbd-1a9506b23e02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91157887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_dis
able_auto_req_mode.91157887
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2522186797
Short name T672
Test name
Test status
Simulation time 18764021 ps
CPU time 1.05 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 218240 kb
Host smart-c8eb4523-5611-4998-b13d-7e2222759a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522186797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2522186797
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.222027655
Short name T583
Test name
Test status
Simulation time 228112907 ps
CPU time 1.67 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 218328 kb
Host smart-929fe0c0-629b-476d-8058-9e91470d0c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222027655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.222027655
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2037777232
Short name T111
Test name
Test status
Simulation time 55496445 ps
CPU time 0.85 seconds
Started Jun 04 01:45:05 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 215116 kb
Host smart-913b0fcc-888b-4840-90f5-3c876239660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037777232 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2037777232
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3831645296
Short name T301
Test name
Test status
Simulation time 21414889 ps
CPU time 0.97 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:11 PM PDT 24
Peak memory 214988 kb
Host smart-5956bcc3-f256-4b95-abd1-3012367d32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831645296 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3831645296
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1135610254
Short name T137
Test name
Test status
Simulation time 242905275 ps
CPU time 1.65 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 214948 kb
Host smart-700471fe-360b-40af-91e2-e8b0d647a68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135610254 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1135610254
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1869503139
Short name T197
Test name
Test status
Simulation time 69081485885 ps
CPU time 1597.5 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 02:11:50 PM PDT 24
Peak memory 223240 kb
Host smart-a52d1dfa-97ae-4935-a7ca-99291131a0d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869503139 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1869503139
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.292936981
Short name T98
Test name
Test status
Simulation time 51883712 ps
CPU time 1.13 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215472 kb
Host smart-4d8cc9e9-2535-4753-b08f-13c7146e05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292936981 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.292936981
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.44285362
Short name T722
Test name
Test status
Simulation time 14690394 ps
CPU time 0.92 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 214480 kb
Host smart-c2f706bf-e7e5-4868-b61a-c25a72ae48b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44285362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.44285362
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2131761472
Short name T373
Test name
Test status
Simulation time 24118145 ps
CPU time 1.02 seconds
Started Jun 04 01:43:57 PM PDT 24
Finished Jun 04 01:43:59 PM PDT 24
Peak memory 216544 kb
Host smart-46f58de8-1ccd-4f47-813b-9b4bbf715083
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131761472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2131761472
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.1969890156
Short name T71
Test name
Test status
Simulation time 19257091 ps
CPU time 1.02 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:54 PM PDT 24
Peak memory 217760 kb
Host smart-0535ac7e-2f0f-4a10-befa-fc4d5a838190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969890156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1969890156
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1172990127
Short name T300
Test name
Test status
Simulation time 302982804 ps
CPU time 4.04 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:57 PM PDT 24
Peak memory 218032 kb
Host smart-88cd6974-422c-4f98-80c2-daaa2261e730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172990127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1172990127
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.2395719450
Short name T107
Test name
Test status
Simulation time 30473308 ps
CPU time 0.91 seconds
Started Jun 04 01:43:53 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215432 kb
Host smart-35bbe5ac-3d01-4928-8fe8-952999793d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395719450 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2395719450
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.939650672
Short name T22
Test name
Test status
Simulation time 19347528 ps
CPU time 0.99 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 206800 kb
Host smart-261f936d-544d-44a9-b315-88fd695b1305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939650672 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.939650672
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4122362324
Short name T577
Test name
Test status
Simulation time 45225730 ps
CPU time 0.94 seconds
Started Jun 04 01:43:57 PM PDT 24
Finished Jun 04 01:43:59 PM PDT 24
Peak memory 214932 kb
Host smart-2bc60365-653d-4776-92f8-7f4047729b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122362324 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4122362324
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1947979686
Short name T776
Test name
Test status
Simulation time 117029444 ps
CPU time 1.82 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 216668 kb
Host smart-25fe619a-9e76-4306-94a2-24f0d499a8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947979686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1947979686
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3024298765
Short name T327
Test name
Test status
Simulation time 53354857358 ps
CPU time 1388.1 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 02:07:02 PM PDT 24
Peak memory 223532 kb
Host smart-abffb203-7e1e-4c9c-9590-3f0f3870b59a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024298765 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3024298765
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3897346952
Short name T808
Test name
Test status
Simulation time 25885770 ps
CPU time 1.18 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 219084 kb
Host smart-982ae760-dee5-40a7-b804-d7e3954a19ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897346952 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3897346952
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3090651897
Short name T593
Test name
Test status
Simulation time 65744282 ps
CPU time 1.05 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 216532 kb
Host smart-03f43aae-3bc6-42cf-993f-255413128058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090651897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3090651897
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.3349010022
Short name T78
Test name
Test status
Simulation time 19449414 ps
CPU time 1.14 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 223412 kb
Host smart-f7570e1e-b46a-4f53-9450-2a0f574488e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349010022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3349010022
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.801047221
Short name T353
Test name
Test status
Simulation time 52007211 ps
CPU time 1.81 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:08 PM PDT 24
Peak memory 216812 kb
Host smart-b1dfd4b2-be1f-4edb-9990-90fb6939adfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801047221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.801047221
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3904994357
Short name T192
Test name
Test status
Simulation time 163266265 ps
CPU time 1.11 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 219352 kb
Host smart-3a1e1d3e-670f-456d-818f-5a396ae27bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904994357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3904994357
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2471891646
Short name T606
Test name
Test status
Simulation time 113138554 ps
CPU time 1.4 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 219564 kb
Host smart-20edcf37-97df-47cb-a1d6-ff379538d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471891646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2471891646
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2516489171
Short name T622
Test name
Test status
Simulation time 21979284 ps
CPU time 1.02 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 218048 kb
Host smart-de553ee8-b7d7-4514-9e94-ff0afc0ea1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516489171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2516489171
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.764803902
Short name T500
Test name
Test status
Simulation time 22952851 ps
CPU time 1.14 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 216584 kb
Host smart-07584992-4f37-437e-9ac0-97ac0705cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764803902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.764803902
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.101453997
Short name T52
Test name
Test status
Simulation time 34291184 ps
CPU time 1.09 seconds
Started Jun 04 01:45:03 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 220212 kb
Host smart-374cfb4e-8a90-4f28-8d6f-82f2f75cc077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101453997 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.101453997
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3193572574
Short name T344
Test name
Test status
Simulation time 49060893 ps
CPU time 1.59 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 01:45:06 PM PDT 24
Peak memory 218000 kb
Host smart-58549f84-d42f-4ad8-a02f-b237095c112d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193572574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3193572574
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1959167932
Short name T27
Test name
Test status
Simulation time 19263233 ps
CPU time 1.06 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:07 PM PDT 24
Peak memory 219288 kb
Host smart-1516bda1-8e90-43aa-9cbe-66653f425e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959167932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1959167932
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.4044018090
Short name T683
Test name
Test status
Simulation time 37337729 ps
CPU time 1.15 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 219204 kb
Host smart-bad43a35-08c4-49ff-8644-a41a8dd4eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044018090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.4044018090
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1858590890
Short name T721
Test name
Test status
Simulation time 30343322 ps
CPU time 0.86 seconds
Started Jun 04 01:45:01 PM PDT 24
Finished Jun 04 01:45:05 PM PDT 24
Peak memory 217512 kb
Host smart-f1ab667b-34d8-45bf-b63b-f44ea194ecf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858590890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1858590890
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3751156674
Short name T832
Test name
Test status
Simulation time 92026844 ps
CPU time 1.16 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 216804 kb
Host smart-c8a7158b-6195-4730-ba7b-ccf1b2991a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751156674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3751156674
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.4259369212
Short name T186
Test name
Test status
Simulation time 77955435 ps
CPU time 0.9 seconds
Started Jun 04 01:45:07 PM PDT 24
Finished Jun 04 01:45:11 PM PDT 24
Peak memory 217944 kb
Host smart-dd65b212-afe2-4e2b-9ee0-0e7f2f0ab161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259369212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4259369212
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3848785894
Short name T158
Test name
Test status
Simulation time 48435334 ps
CPU time 1.11 seconds
Started Jun 04 01:45:03 PM PDT 24
Finished Jun 04 01:45:08 PM PDT 24
Peak memory 219460 kb
Host smart-754a2720-af4f-4b65-8196-9d58506fe534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848785894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3848785894
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2641008482
Short name T827
Test name
Test status
Simulation time 18572731 ps
CPU time 1.02 seconds
Started Jun 04 01:45:03 PM PDT 24
Finished Jun 04 01:45:08 PM PDT 24
Peak memory 217776 kb
Host smart-b397558a-2699-431c-9829-debace7b57b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641008482 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2641008482
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.789955249
Short name T304
Test name
Test status
Simulation time 62047194 ps
CPU time 1.39 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 216484 kb
Host smart-122a356f-725c-49c5-b5a1-204dc8fd978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789955249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.789955249
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2646615094
Short name T690
Test name
Test status
Simulation time 23963874 ps
CPU time 1.03 seconds
Started Jun 04 01:45:04 PM PDT 24
Finished Jun 04 01:45:09 PM PDT 24
Peak memory 223424 kb
Host smart-c0516305-aac4-4299-90bd-f6c8d3f74454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646615094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2646615094
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3954604636
Short name T579
Test name
Test status
Simulation time 112326709 ps
CPU time 1.43 seconds
Started Jun 04 01:45:02 PM PDT 24
Finished Jun 04 01:45:08 PM PDT 24
Peak memory 217220 kb
Host smart-a50b2951-89ed-426d-942d-a083fb2f84ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954604636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3954604636
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.122357270
Short name T660
Test name
Test status
Simulation time 39271542 ps
CPU time 1.21 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215376 kb
Host smart-2c0a66c9-9ea6-4871-99d2-9f2e2383ceae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122357270 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.122357270
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1670505839
Short name T648
Test name
Test status
Simulation time 26622781 ps
CPU time 0.87 seconds
Started Jun 04 01:43:53 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 206296 kb
Host smart-64405a51-be8e-4e63-bb28-abc4a7765a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670505839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1670505839
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2502781890
Short name T359
Test name
Test status
Simulation time 23542162 ps
CPU time 0.83 seconds
Started Jun 04 01:43:53 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215712 kb
Host smart-8664dd56-c34e-490d-b5be-a6522964ae52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502781890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2502781890
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3613148271
Short name T557
Test name
Test status
Simulation time 122799015 ps
CPU time 1.28 seconds
Started Jun 04 01:43:50 PM PDT 24
Finished Jun 04 01:43:52 PM PDT 24
Peak memory 216552 kb
Host smart-184ddd9c-d52e-405a-9f66-5aa06df1be54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613148271 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3613148271
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.722442344
Short name T90
Test name
Test status
Simulation time 29328628 ps
CPU time 1.03 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 223236 kb
Host smart-3fff89b3-b017-49df-a9c6-f398b5f401af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722442344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.722442344
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3420288725
Short name T649
Test name
Test status
Simulation time 290284544 ps
CPU time 1.42 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 216812 kb
Host smart-747beb8d-c7f7-489b-b52c-8a1876db9604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420288725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3420288725
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2625467030
Short name T698
Test name
Test status
Simulation time 33375731 ps
CPU time 0.85 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 215160 kb
Host smart-8d254933-eed0-43b6-8797-239207c5b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625467030 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2625467030
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.1290236389
Short name T146
Test name
Test status
Simulation time 38039903 ps
CPU time 0.87 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:54 PM PDT 24
Peak memory 215076 kb
Host smart-ddadfcc9-0195-4b28-a995-d2859b2bbe40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290236389 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1290236389
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1034182613
Short name T493
Test name
Test status
Simulation time 744592046 ps
CPU time 2.45 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 216636 kb
Host smart-5c36d855-afa6-4de5-900a-9f08276ab79e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034182613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1034182613
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.662742318
Short name T199
Test name
Test status
Simulation time 27301698697 ps
CPU time 581.31 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:53:33 PM PDT 24
Peak memory 221816 kb
Host smart-7fda266d-227b-4a6d-900d-3a021b9edd1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662742318 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.662742318
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2545308457
Short name T718
Test name
Test status
Simulation time 25764929 ps
CPU time 1.2 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 218028 kb
Host smart-7a64454a-220d-41f9-9338-315e1f69c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545308457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2545308457
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.356531663
Short name T284
Test name
Test status
Simulation time 69446067 ps
CPU time 1.27 seconds
Started Jun 04 01:45:05 PM PDT 24
Finished Jun 04 01:45:10 PM PDT 24
Peak memory 218352 kb
Host smart-9e32b200-c52b-4e6e-a050-2e5db6d57c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356531663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.356531663
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.4234982986
Short name T339
Test name
Test status
Simulation time 29099715 ps
CPU time 0.86 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 217980 kb
Host smart-6dda3717-da51-44cb-be19-3392a13df06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234982986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.4234982986
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2900096375
Short name T520
Test name
Test status
Simulation time 83713250 ps
CPU time 1.13 seconds
Started Jun 04 01:45:08 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 216664 kb
Host smart-25b8b53f-80bb-4313-981f-8acb17b0b854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900096375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2900096375
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2742429183
Short name T187
Test name
Test status
Simulation time 34519239 ps
CPU time 0.98 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 223252 kb
Host smart-98a7cd94-c4b6-4986-ae95-137296bb2d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742429183 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2742429183
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.532505511
Short name T592
Test name
Test status
Simulation time 74164766 ps
CPU time 1.09 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 216664 kb
Host smart-7cf87f96-e9f7-41df-a78d-00c90b8c237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532505511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.532505511
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.211203432
Short name T443
Test name
Test status
Simulation time 33477024 ps
CPU time 1.05 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 218364 kb
Host smart-6f316de8-4c8b-4393-af7a-dadb79b78179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211203432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.211203432
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2272299776
Short name T341
Test name
Test status
Simulation time 35508314 ps
CPU time 1.3 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 218152 kb
Host smart-0b3864dd-f4f8-46b7-b838-c5104f45d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272299776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2272299776
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1224971545
Short name T607
Test name
Test status
Simulation time 34947161 ps
CPU time 0.95 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 218196 kb
Host smart-0c97349e-5af4-46fd-a5cf-5deb3635408c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224971545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1224971545
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.4164407303
Short name T762
Test name
Test status
Simulation time 48233721 ps
CPU time 1.22 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 219544 kb
Host smart-a05f6278-f82e-49fc-8410-c2c13acf347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164407303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.4164407303
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4139272927
Short name T179
Test name
Test status
Simulation time 25914161 ps
CPU time 0.96 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 219520 kb
Host smart-ebf3c645-ce83-4121-a942-1943b3835482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139272927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4139272927
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3063553907
Short name T791
Test name
Test status
Simulation time 93059013 ps
CPU time 1.03 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 216664 kb
Host smart-c89da1e3-4e03-4a7a-8aca-4c1d7150d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063553907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3063553907
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.2670008585
Short name T652
Test name
Test status
Simulation time 119976610 ps
CPU time 1.35 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 219572 kb
Host smart-92ce0307-45aa-4d3e-82f5-ff8a417e8b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670008585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2670008585
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2980979808
Short name T440
Test name
Test status
Simulation time 20934717 ps
CPU time 1.18 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 229044 kb
Host smart-288af599-06f9-4789-bc3e-5b48516bbfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980979808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2980979808
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2719822110
Short name T458
Test name
Test status
Simulation time 60301966 ps
CPU time 1.29 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 218924 kb
Host smart-e34ac311-022d-40be-b3af-a8ff481e3dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719822110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2719822110
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1354512438
Short name T742
Test name
Test status
Simulation time 28831112 ps
CPU time 1.26 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 219284 kb
Host smart-f3810ba1-724b-48df-80c0-df139c4b6f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354512438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1354512438
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.4200229374
Short name T642
Test name
Test status
Simulation time 63221834 ps
CPU time 1.77 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 217924 kb
Host smart-7bcd2d56-b64d-417d-80e1-246720e1bfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200229374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.4200229374
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.4185319898
Short name T50
Test name
Test status
Simulation time 19705184 ps
CPU time 1.21 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 223400 kb
Host smart-0bb86f50-4f83-48b9-a385-292b6aca81c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185319898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.4185319898
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2267351967
Short name T472
Test name
Test status
Simulation time 79257178 ps
CPU time 1.54 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 218220 kb
Host smart-3d26c967-de7f-418f-9059-8929ae47dc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267351967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2267351967
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1342204343
Short name T261
Test name
Test status
Simulation time 24687568 ps
CPU time 1.17 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 01:43:55 PM PDT 24
Peak memory 215416 kb
Host smart-455002aa-d828-4142-8db3-4ef814dd4ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342204343 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1342204343
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.3471922994
Short name T518
Test name
Test status
Simulation time 39146665 ps
CPU time 0.97 seconds
Started Jun 04 01:44:00 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 206328 kb
Host smart-587d4989-3b64-4f42-87c7-8694d23ce2b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471922994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3471922994
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.539452616
Short name T180
Test name
Test status
Simulation time 35401308 ps
CPU time 1.35 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 216780 kb
Host smart-7ee4ec1a-6cf1-4f06-8f76-a802551c9e0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539452616 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.539452616
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.760092297
Short name T335
Test name
Test status
Simulation time 29786281 ps
CPU time 0.97 seconds
Started Jun 04 01:43:54 PM PDT 24
Finished Jun 04 01:43:56 PM PDT 24
Peak memory 217656 kb
Host smart-c39dda93-c939-4faf-b0ae-13c52aaf9690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760092297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.760092297
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.330314052
Short name T514
Test name
Test status
Simulation time 56665910 ps
CPU time 1.02 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 216812 kb
Host smart-7231986c-aa92-4a0b-b68c-65a3c363b07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330314052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.330314052
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2285427956
Short name T508
Test name
Test status
Simulation time 40323387 ps
CPU time 0.86 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 214924 kb
Host smart-bc85998d-7cd9-46c3-8d7b-54f927129327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285427956 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2285427956
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.139238687
Short name T812
Test name
Test status
Simulation time 25727288 ps
CPU time 1 seconds
Started Jun 04 01:43:51 PM PDT 24
Finished Jun 04 01:43:53 PM PDT 24
Peak memory 215032 kb
Host smart-2246dad7-d94a-4d7e-a5ea-ee67d42278af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139238687 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.139238687
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1123204206
Short name T496
Test name
Test status
Simulation time 165439941 ps
CPU time 3.65 seconds
Started Jun 04 01:43:53 PM PDT 24
Finished Jun 04 01:43:58 PM PDT 24
Peak memory 216448 kb
Host smart-cff9163f-bbac-4b65-8d78-c0d9b30782bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123204206 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1123204206
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2725714943
Short name T647
Test name
Test status
Simulation time 155923973196 ps
CPU time 1899.97 seconds
Started Jun 04 01:43:52 PM PDT 24
Finished Jun 04 02:15:34 PM PDT 24
Peak memory 225668 kb
Host smart-c73dcdb0-799f-4aba-b31c-c5737bc1cd51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725714943 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2725714943
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2417125112
Short name T100
Test name
Test status
Simulation time 25861922 ps
CPU time 0.95 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 219032 kb
Host smart-2d7d1ef0-e4f9-48c4-9be4-d7afafe6e7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417125112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2417125112
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.819587125
Short name T669
Test name
Test status
Simulation time 74585855 ps
CPU time 1.44 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 217988 kb
Host smart-7e68562e-9ada-45e3-a5cc-bbde7310a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819587125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.819587125
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.4008491073
Short name T479
Test name
Test status
Simulation time 27601230 ps
CPU time 1.24 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 220256 kb
Host smart-62d5f263-60e1-4fab-86bb-2ab55f83fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008491073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.4008491073
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.841108505
Short name T29
Test name
Test status
Simulation time 90553959 ps
CPU time 1.23 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 218000 kb
Host smart-70ef38ac-1f21-4413-b75d-c04b044e83b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841108505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.841108505
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3236490543
Short name T719
Test name
Test status
Simulation time 21896561 ps
CPU time 1.06 seconds
Started Jun 04 01:45:14 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 223504 kb
Host smart-cf36569c-2b1c-46ac-9b19-a9586b1f5d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236490543 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3236490543
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3956949493
Short name T641
Test name
Test status
Simulation time 74478202 ps
CPU time 1.12 seconds
Started Jun 04 01:45:14 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 216700 kb
Host smart-b6f4e36b-b26e-4a10-9144-389dd8fc78b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956949493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3956949493
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2325636109
Short name T320
Test name
Test status
Simulation time 43933276 ps
CPU time 1.16 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 219260 kb
Host smart-b1fc3916-ee11-4035-8148-71859aa7f993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325636109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2325636109
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.3839649230
Short name T279
Test name
Test status
Simulation time 43055334 ps
CPU time 1.13 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 217864 kb
Host smart-1c4a864a-3b64-465f-8903-19fd5f1d0dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839649230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.3839649230
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1014070839
Short name T425
Test name
Test status
Simulation time 22675694 ps
CPU time 0.93 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 218360 kb
Host smart-3b5c4c03-112b-4ded-b91b-dcf656e6f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014070839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1014070839
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2104920880
Short name T397
Test name
Test status
Simulation time 125180787 ps
CPU time 1.89 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 219648 kb
Host smart-6ce39f93-98b8-44a3-9ab3-d99ca35127be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104920880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2104920880
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3094595795
Short name T12
Test name
Test status
Simulation time 19049280 ps
CPU time 1.15 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:13 PM PDT 24
Peak memory 223424 kb
Host smart-38333934-ad31-4625-bc17-5e689b20fe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094595795 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3094595795
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.527346121
Short name T378
Test name
Test status
Simulation time 93031655 ps
CPU time 1.99 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 219376 kb
Host smart-93fbf4b5-2168-4b41-8ddf-0cbf33f2ccd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527346121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.527346121
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3226049710
Short name T553
Test name
Test status
Simulation time 29858348 ps
CPU time 0.87 seconds
Started Jun 04 01:45:18 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 217860 kb
Host smart-c4454100-7d47-4820-ad63-3f2de4426707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226049710 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3226049710
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.305179884
Short name T345
Test name
Test status
Simulation time 45182157 ps
CPU time 1.7 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 218064 kb
Host smart-9a249eba-6c73-4947-a3ed-82b2b79e01f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305179884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.305179884
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1393123577
Short name T580
Test name
Test status
Simulation time 60700023 ps
CPU time 1.34 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 219420 kb
Host smart-e04d23b1-2a05-44f0-b06c-e07dd42e384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393123577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1393123577
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3673553445
Short name T524
Test name
Test status
Simulation time 50504605 ps
CPU time 1.16 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 216764 kb
Host smart-4a7f95eb-315a-432e-9008-9719e0d5b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673553445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3673553445
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2278739198
Short name T370
Test name
Test status
Simulation time 49554124 ps
CPU time 0.85 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 217832 kb
Host smart-4311ed4b-ac45-4d98-97b2-92c4e0a6a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278739198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2278739198
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2523877951
Short name T545
Test name
Test status
Simulation time 44100514 ps
CPU time 1.43 seconds
Started Jun 04 01:45:23 PM PDT 24
Finished Jun 04 01:45:25 PM PDT 24
Peak memory 218680 kb
Host smart-e08ed4f0-8999-4627-af01-ce32e871110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523877951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2523877951
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2023981071
Short name T61
Test name
Test status
Simulation time 32619329 ps
CPU time 0.87 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 217936 kb
Host smart-dfd417dc-76cb-4472-b04a-ddddcdead6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023981071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2023981071
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2137084368
Short name T701
Test name
Test status
Simulation time 94393616 ps
CPU time 1.31 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 218256 kb
Host smart-1c70854d-e60a-4227-b396-9713e3c210c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137084368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2137084368
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert_test.3387923401
Short name T818
Test name
Test status
Simulation time 47364447 ps
CPU time 0.94 seconds
Started Jun 04 01:44:01 PM PDT 24
Finished Jun 04 01:44:03 PM PDT 24
Peak memory 214928 kb
Host smart-56eca804-e00a-4910-80ab-71e8da5c6a35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387923401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3387923401
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2597861794
Short name T838
Test name
Test status
Simulation time 28072901 ps
CPU time 0.88 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 215924 kb
Host smart-a9dc531f-6f05-4c20-b4c5-ffa7b4f2ea7a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597861794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2597861794
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.874728006
Short name T189
Test name
Test status
Simulation time 59587400 ps
CPU time 1.13 seconds
Started Jun 04 01:44:02 PM PDT 24
Finished Jun 04 01:44:04 PM PDT 24
Peak memory 216548 kb
Host smart-a38073e2-662f-4597-9586-96d681222951
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874728006 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.874728006
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2015148212
Short name T44
Test name
Test status
Simulation time 20596232 ps
CPU time 1.25 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 229008 kb
Host smart-1acced51-f4a5-4ce0-9511-fc7e6996eadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015148212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2015148212
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.142276285
Short name T774
Test name
Test status
Simulation time 110869275 ps
CPU time 1.1 seconds
Started Jun 04 01:44:03 PM PDT 24
Finished Jun 04 01:44:05 PM PDT 24
Peak memory 219568 kb
Host smart-08acea6b-ad23-4803-a2b4-839099f474fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142276285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.142276285
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1767039997
Short name T498
Test name
Test status
Simulation time 21724120 ps
CPU time 1.24 seconds
Started Jun 04 01:44:02 PM PDT 24
Finished Jun 04 01:44:04 PM PDT 24
Peak memory 224784 kb
Host smart-f53f9cad-2684-4df1-a03f-88c19b831d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767039997 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1767039997
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.563111310
Short name T134
Test name
Test status
Simulation time 14065176 ps
CPU time 0.96 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:01 PM PDT 24
Peak memory 214992 kb
Host smart-05bf5af5-01b6-43fb-b3bf-686f2636a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563111310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.563111310
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3861583964
Short name T811
Test name
Test status
Simulation time 171793243 ps
CPU time 3.76 seconds
Started Jun 04 01:44:04 PM PDT 24
Finished Jun 04 01:44:09 PM PDT 24
Peak memory 215152 kb
Host smart-9c686806-e3ba-4ece-8675-d9fb5112934f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861583964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3861583964
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1301062513
Short name T494
Test name
Test status
Simulation time 232766710272 ps
CPU time 1505.86 seconds
Started Jun 04 01:43:58 PM PDT 24
Finished Jun 04 02:09:05 PM PDT 24
Peak memory 225152 kb
Host smart-26b51c5b-fd23-4eb8-8cf8-607c1c9c7703
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301062513 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1301062513
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3420903198
Short name T770
Test name
Test status
Simulation time 22531616 ps
CPU time 0.94 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 218120 kb
Host smart-709f961c-55bf-406b-a0a9-b5c88dac821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420903198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3420903198
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.708469116
Short name T303
Test name
Test status
Simulation time 32675225 ps
CPU time 1.47 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 216940 kb
Host smart-803af6c1-af9f-41d7-8670-851b8eb2e5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708469116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.708469116
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3587382036
Short name T57
Test name
Test status
Simulation time 38989981 ps
CPU time 0.97 seconds
Started Jun 04 01:45:19 PM PDT 24
Finished Jun 04 01:45:21 PM PDT 24
Peak memory 219408 kb
Host smart-b8b5374d-9d87-4c23-9137-748131e4b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587382036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3587382036
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3186331437
Short name T843
Test name
Test status
Simulation time 221657356 ps
CPU time 2.82 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:26 PM PDT 24
Peak memory 219160 kb
Host smart-dfcfee80-e562-4f17-984e-cc8f9ee9c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186331437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3186331437
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2825913381
Short name T685
Test name
Test status
Simulation time 31589221 ps
CPU time 1.06 seconds
Started Jun 04 01:45:08 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 223540 kb
Host smart-3170d714-ef03-4cf9-8f16-5aa056393921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825913381 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2825913381
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3329922359
Short name T18
Test name
Test status
Simulation time 100390956 ps
CPU time 2.04 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 219612 kb
Host smart-071f37d8-ce69-4f4a-a21d-f987bfccaeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329922359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3329922359
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4136272674
Short name T88
Test name
Test status
Simulation time 20562652 ps
CPU time 1.04 seconds
Started Jun 04 01:45:09 PM PDT 24
Finished Jun 04 01:45:12 PM PDT 24
Peak memory 217952 kb
Host smart-16eb447b-7e0f-4de3-83fa-ed73552a53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136272674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4136272674
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.907752441
Short name T385
Test name
Test status
Simulation time 44259701 ps
CPU time 1.44 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 217860 kb
Host smart-3431e341-8706-44ff-88d8-48ec419d4ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907752441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.907752441
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.4099461048
Short name T588
Test name
Test status
Simulation time 26432264 ps
CPU time 0.98 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:15 PM PDT 24
Peak memory 223280 kb
Host smart-6bc07c5a-5a0a-4e02-9db3-6d3d3c2741e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099461048 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.4099461048
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3525605991
Short name T276
Test name
Test status
Simulation time 62187459 ps
CPU time 1.13 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 218092 kb
Host smart-6cdf66a4-e38f-4d7c-93f6-207059651195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525605991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3525605991
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1995946601
Short name T83
Test name
Test status
Simulation time 23769912 ps
CPU time 1.01 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 223432 kb
Host smart-01c44f6c-79ec-4759-862f-1a54e65361a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995946601 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1995946601
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1962953087
Short name T741
Test name
Test status
Simulation time 60351582 ps
CPU time 1.56 seconds
Started Jun 04 01:45:10 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 217840 kb
Host smart-ad056abf-9883-4025-a1b2-72c249766ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962953087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1962953087
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1333625756
Short name T105
Test name
Test status
Simulation time 29078360 ps
CPU time 1.29 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:17 PM PDT 24
Peak memory 219320 kb
Host smart-dfb09596-582b-4e12-95f5-150cfa4acf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333625756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1333625756
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.83308758
Short name T696
Test name
Test status
Simulation time 443787327 ps
CPU time 4.96 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:36 PM PDT 24
Peak memory 216972 kb
Host smart-0a71ba74-89d2-4314-9efd-a15c463efe00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83308758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.83308758
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2490790645
Short name T333
Test name
Test status
Simulation time 35712962 ps
CPU time 0.87 seconds
Started Jun 04 01:45:22 PM PDT 24
Finished Jun 04 01:45:24 PM PDT 24
Peak memory 219144 kb
Host smart-6d43fe11-70d0-479b-bee6-4daeb5066667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490790645 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2490790645
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4027871232
Short name T9
Test name
Test status
Simulation time 61744757 ps
CPU time 1.07 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 217104 kb
Host smart-7999b6d0-9b33-4702-94e3-70e6c012d8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027871232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4027871232
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.864297554
Short name T191
Test name
Test status
Simulation time 32323116 ps
CPU time 1.06 seconds
Started Jun 04 01:45:11 PM PDT 24
Finished Jun 04 01:45:14 PM PDT 24
Peak memory 220392 kb
Host smart-b9e3aa7d-73e5-478b-8f65-1825c72827d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864297554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.864297554
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.741794514
Short name T452
Test name
Test status
Simulation time 31907442 ps
CPU time 1.24 seconds
Started Jun 04 01:45:17 PM PDT 24
Finished Jun 04 01:45:20 PM PDT 24
Peak memory 218992 kb
Host smart-ac1ade08-b1f0-4f2b-ae4a-09327d4f1d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741794514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.741794514
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1544002652
Short name T49
Test name
Test status
Simulation time 26647130 ps
CPU time 1.18 seconds
Started Jun 04 01:45:18 PM PDT 24
Finished Jun 04 01:45:21 PM PDT 24
Peak memory 223432 kb
Host smart-7c8e58f5-ed6a-481c-89ed-c4fc63608451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544002652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1544002652
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.506193632
Short name T590
Test name
Test status
Simulation time 29838828 ps
CPU time 1.28 seconds
Started Jun 04 01:45:21 PM PDT 24
Finished Jun 04 01:45:23 PM PDT 24
Peak memory 219360 kb
Host smart-57548774-8445-4a6a-b249-2c18eb750347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506193632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.506193632
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.4030912535
Short name T785
Test name
Test status
Simulation time 45169565 ps
CPU time 1.3 seconds
Started Jun 04 01:44:00 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 215340 kb
Host smart-6611da60-9803-470b-9ee2-7aabf4d5cc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030912535 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.4030912535
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1435610593
Short name T380
Test name
Test status
Simulation time 40617195 ps
CPU time 0.83 seconds
Started Jun 04 01:43:58 PM PDT 24
Finished Jun 04 01:44:00 PM PDT 24
Peak memory 214544 kb
Host smart-01ef037f-39ce-48e4-96d8-70ab19a9a3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435610593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1435610593
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4187798672
Short name T700
Test name
Test status
Simulation time 26292204 ps
CPU time 0.83 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:01 PM PDT 24
Peak memory 215872 kb
Host smart-a83435ff-ecbc-4f1a-9127-d929398ea5f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187798672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4187798672
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3721202986
Short name T392
Test name
Test status
Simulation time 70593158 ps
CPU time 1.09 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 219140 kb
Host smart-52cceb75-09a5-4d6b-84c4-a8ef6d28d294
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721202986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3721202986
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.4229334159
Short name T369
Test name
Test status
Simulation time 31612775 ps
CPU time 0.88 seconds
Started Jun 04 01:44:03 PM PDT 24
Finished Jun 04 01:44:05 PM PDT 24
Peak memory 218900 kb
Host smart-271e5716-2316-4630-856c-c1d39e385877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229334159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.4229334159
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2582369321
Short name T149
Test name
Test status
Simulation time 83079320 ps
CPU time 1.34 seconds
Started Jun 04 01:43:59 PM PDT 24
Finished Jun 04 01:44:02 PM PDT 24
Peak memory 218304 kb
Host smart-4369d7d0-716b-417c-8766-fb91ebdf164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582369321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2582369321
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3092286531
Short name T215
Test name
Test status
Simulation time 31626712 ps
CPU time 0.88 seconds
Started Jun 04 01:44:02 PM PDT 24
Finished Jun 04 01:44:04 PM PDT 24
Peak memory 215072 kb
Host smart-0816a6bd-f52c-4225-bcd0-6df725ed86de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092286531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3092286531
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.945590218
Short name T753
Test name
Test status
Simulation time 18800930 ps
CPU time 1.02 seconds
Started Jun 04 01:44:01 PM PDT 24
Finished Jun 04 01:44:03 PM PDT 24
Peak memory 206840 kb
Host smart-310de51b-606b-421f-be33-c63ef129042a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945590218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.945590218
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1831745295
Short name T355
Test name
Test status
Simulation time 62363692 ps
CPU time 1.91 seconds
Started Jun 04 01:44:03 PM PDT 24
Finished Jun 04 01:44:06 PM PDT 24
Peak memory 216772 kb
Host smart-2e10b6e2-46f0-4b4b-84bb-c65615abfc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831745295 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1831745295
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3191904458
Short name T664
Test name
Test status
Simulation time 92293512042 ps
CPU time 1031.24 seconds
Started Jun 04 01:43:58 PM PDT 24
Finished Jun 04 02:01:10 PM PDT 24
Peak memory 220660 kb
Host smart-d2d27e34-2160-48fa-b405-efafc1b3621c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191904458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3191904458
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1507775910
Short name T176
Test name
Test status
Simulation time 30286044 ps
CPU time 0.82 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:18 PM PDT 24
Peak memory 217872 kb
Host smart-a35a3ecd-55e4-48cb-bd44-a2f364c986cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507775910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1507775910
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.798831291
Short name T154
Test name
Test status
Simulation time 50589918 ps
CPU time 1.44 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 218056 kb
Host smart-a7f3b127-9697-420b-93e2-4bb99b02dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798831291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.798831291
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3419964018
Short name T53
Test name
Test status
Simulation time 46908864 ps
CPU time 1.08 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 220240 kb
Host smart-8108a42f-afbd-473f-a491-bcad7b2a44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419964018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3419964018
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.513334410
Short name T670
Test name
Test status
Simulation time 25479823 ps
CPU time 1.17 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216628 kb
Host smart-9494b2d6-51c2-41f0-92db-ce7c5305e042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513334410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.513334410
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2646106770
Short name T73
Test name
Test status
Simulation time 25632336 ps
CPU time 0.94 seconds
Started Jun 04 01:45:13 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 218160 kb
Host smart-42fda16f-c4c2-47fb-8968-e6d0e5029775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646106770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2646106770
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3735188477
Short name T131
Test name
Test status
Simulation time 49535651 ps
CPU time 1.11 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 216772 kb
Host smart-8c79ef20-bc35-4c3e-a185-c2aa79654eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735188477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3735188477
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.131174873
Short name T645
Test name
Test status
Simulation time 27570206 ps
CPU time 1.22 seconds
Started Jun 04 01:45:30 PM PDT 24
Finished Jun 04 01:45:34 PM PDT 24
Peak memory 220412 kb
Host smart-1c8fefd3-9b65-48e9-81bb-6f8866871b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131174873 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.131174873
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1465167511
Short name T324
Test name
Test status
Simulation time 29941649 ps
CPU time 1.33 seconds
Started Jun 04 01:45:15 PM PDT 24
Finished Jun 04 01:45:18 PM PDT 24
Peak memory 217976 kb
Host smart-e06ad17e-aba4-42a0-89d6-0d441c0b4114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465167511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1465167511
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2914804058
Short name T547
Test name
Test status
Simulation time 43076848 ps
CPU time 1.22 seconds
Started Jun 04 01:45:12 PM PDT 24
Finished Jun 04 01:45:16 PM PDT 24
Peak memory 225044 kb
Host smart-6ef1b562-a1d4-4c21-9852-c4f9f722eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914804058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2914804058
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1368972411
Short name T367
Test name
Test status
Simulation time 46788659 ps
CPU time 1.44 seconds
Started Jun 04 01:45:15 PM PDT 24
Finished Jun 04 01:45:18 PM PDT 24
Peak memory 216820 kb
Host smart-463a463e-0c20-41a5-b7db-c1ac70502164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368972411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1368972411
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1683035378
Short name T468
Test name
Test status
Simulation time 17906621 ps
CPU time 1.03 seconds
Started Jun 04 01:45:16 PM PDT 24
Finished Jun 04 01:45:19 PM PDT 24
Peak memory 217900 kb
Host smart-6c6492c1-b461-4173-8fea-47428877f520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683035378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1683035378
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3211240520
Short name T802
Test name
Test status
Simulation time 67928900 ps
CPU time 1.62 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:30 PM PDT 24
Peak memory 218100 kb
Host smart-14815109-e980-4081-951a-65a39893aca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211240520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3211240520
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2219753880
Short name T82
Test name
Test status
Simulation time 19107314 ps
CPU time 1.04 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 217916 kb
Host smart-ca74ddcb-e10f-46ce-be4b-9d1c1596564b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219753880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2219753880
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2545672741
Short name T337
Test name
Test status
Simulation time 49346551 ps
CPU time 1.68 seconds
Started Jun 04 01:45:20 PM PDT 24
Finished Jun 04 01:45:23 PM PDT 24
Peak memory 216852 kb
Host smart-6e1b3759-6465-4124-bfa4-e24ce5aeed30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545672741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2545672741
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3529146014
Short name T30
Test name
Test status
Simulation time 29832447 ps
CPU time 1.14 seconds
Started Jun 04 01:45:19 PM PDT 24
Finished Jun 04 01:45:21 PM PDT 24
Peak memory 219460 kb
Host smart-0ad4ad66-470b-4440-9b4b-8118525b4fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529146014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3529146014
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2747409757
Short name T488
Test name
Test status
Simulation time 63435769 ps
CPU time 1.08 seconds
Started Jun 04 01:45:29 PM PDT 24
Finished Jun 04 01:45:33 PM PDT 24
Peak memory 216776 kb
Host smart-ddea7113-dd35-46aa-9bf1-9191142c91ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747409757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2747409757
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.4196127109
Short name T72
Test name
Test status
Simulation time 31815324 ps
CPU time 0.97 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 223324 kb
Host smart-c5d89a88-c7a9-41d8-9fcf-9fa2f62f7624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196127109 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4196127109
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2620269397
Short name T691
Test name
Test status
Simulation time 84791089 ps
CPU time 1.33 seconds
Started Jun 04 01:45:26 PM PDT 24
Finished Jun 04 01:45:29 PM PDT 24
Peak memory 218220 kb
Host smart-2456125e-da42-45dd-81b3-ee35f173f8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620269397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2620269397
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.444246180
Short name T182
Test name
Test status
Simulation time 36333642 ps
CPU time 1.1 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 220168 kb
Host smart-b4b757d9-77e5-4d43-ad77-8a558472d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444246180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.444246180
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3043190891
Short name T406
Test name
Test status
Simulation time 70568335 ps
CPU time 1.09 seconds
Started Jun 04 01:45:24 PM PDT 24
Finished Jun 04 01:45:27 PM PDT 24
Peak memory 216632 kb
Host smart-1b6bf258-8b46-4902-8a7d-9bc479cab1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043190891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3043190891
Directory /workspace/99.edn_genbits/latest
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