Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
113737 |
1 |
|
|
T2 |
283 |
|
T3 |
32 |
|
T8 |
26 |
all_pins[1] |
113737 |
1 |
|
|
T2 |
283 |
|
T3 |
32 |
|
T8 |
26 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
217941 |
1 |
|
|
T2 |
566 |
|
T3 |
64 |
|
T8 |
52 |
values[0x1] |
9533 |
1 |
|
|
T102 |
36 |
|
T103 |
37 |
|
T116 |
275 |
transitions[0x0=>0x1] |
8725 |
1 |
|
|
T102 |
28 |
|
T103 |
34 |
|
T116 |
259 |
transitions[0x1=>0x0] |
8734 |
1 |
|
|
T102 |
28 |
|
T103 |
34 |
|
T116 |
259 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
105958 |
1 |
|
|
T2 |
283 |
|
T3 |
32 |
|
T8 |
26 |
all_pins[0] |
values[0x1] |
7779 |
1 |
|
|
T102 |
19 |
|
T103 |
24 |
|
T116 |
238 |
all_pins[0] |
transitions[0x0=>0x1] |
7327 |
1 |
|
|
T102 |
15 |
|
T103 |
22 |
|
T116 |
226 |
all_pins[0] |
transitions[0x1=>0x0] |
1302 |
1 |
|
|
T102 |
13 |
|
T103 |
11 |
|
T116 |
25 |
all_pins[1] |
values[0x0] |
111983 |
1 |
|
|
T2 |
283 |
|
T3 |
32 |
|
T8 |
26 |
all_pins[1] |
values[0x1] |
1754 |
1 |
|
|
T102 |
17 |
|
T103 |
13 |
|
T116 |
37 |
all_pins[1] |
transitions[0x0=>0x1] |
1398 |
1 |
|
|
T102 |
13 |
|
T103 |
12 |
|
T116 |
33 |
all_pins[1] |
transitions[0x1=>0x0] |
7432 |
1 |
|
|
T102 |
15 |
|
T103 |
23 |
|
T116 |
234 |