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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.27 98.24 93.80 97.02 83.14 96.62 99.77 91.31


Total test records in report: 980
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T791 /workspace/coverage/default/0.edn_smoke.541567861 Jun 05 05:56:41 PM PDT 24 Jun 05 05:56:43 PM PDT 24 48513996 ps
T792 /workspace/coverage/default/133.edn_genbits.2088864795 Jun 05 05:57:51 PM PDT 24 Jun 05 05:57:54 PM PDT 24 109403647 ps
T793 /workspace/coverage/default/31.edn_smoke.3142610888 Jun 05 05:57:07 PM PDT 24 Jun 05 05:57:09 PM PDT 24 58307846 ps
T794 /workspace/coverage/default/207.edn_genbits.1255400500 Jun 05 05:58:13 PM PDT 24 Jun 05 05:58:15 PM PDT 24 274712880 ps
T795 /workspace/coverage/default/43.edn_smoke.1122174035 Jun 05 05:58:54 PM PDT 24 Jun 05 05:58:56 PM PDT 24 19129265 ps
T796 /workspace/coverage/default/17.edn_alert_test.2664014217 Jun 05 05:57:05 PM PDT 24 Jun 05 05:57:07 PM PDT 24 39175000 ps
T797 /workspace/coverage/default/25.edn_disable.3256576401 Jun 05 05:57:28 PM PDT 24 Jun 05 05:57:29 PM PDT 24 40350647 ps
T798 /workspace/coverage/default/266.edn_genbits.1220653555 Jun 05 05:58:29 PM PDT 24 Jun 05 05:58:31 PM PDT 24 88685035 ps
T799 /workspace/coverage/default/165.edn_genbits.3643661292 Jun 05 05:57:51 PM PDT 24 Jun 05 05:57:54 PM PDT 24 154551335 ps
T800 /workspace/coverage/default/84.edn_genbits.2615506771 Jun 05 05:58:04 PM PDT 24 Jun 05 05:58:06 PM PDT 24 108558651 ps
T801 /workspace/coverage/default/19.edn_intr.1367612029 Jun 05 05:56:55 PM PDT 24 Jun 05 05:56:57 PM PDT 24 23140657 ps
T802 /workspace/coverage/default/28.edn_err.3769098676 Jun 05 05:57:25 PM PDT 24 Jun 05 05:57:27 PM PDT 24 59980248 ps
T803 /workspace/coverage/default/218.edn_genbits.2356164340 Jun 05 05:58:22 PM PDT 24 Jun 05 05:58:24 PM PDT 24 50421610 ps
T163 /workspace/coverage/default/21.edn_disable_auto_req_mode.3863758180 Jun 05 05:56:46 PM PDT 24 Jun 05 05:56:48 PM PDT 24 90324536 ps
T187 /workspace/coverage/default/3.edn_disable.3832136573 Jun 05 05:56:51 PM PDT 24 Jun 05 05:56:54 PM PDT 24 13193331 ps
T804 /workspace/coverage/default/32.edn_genbits.95684659 Jun 05 05:57:12 PM PDT 24 Jun 05 05:57:13 PM PDT 24 69539719 ps
T805 /workspace/coverage/default/40.edn_alert.1819438317 Jun 05 05:57:41 PM PDT 24 Jun 05 05:57:44 PM PDT 24 29183930 ps
T806 /workspace/coverage/default/23.edn_genbits.4022716925 Jun 05 05:57:12 PM PDT 24 Jun 05 05:57:14 PM PDT 24 49561423 ps
T807 /workspace/coverage/default/264.edn_genbits.294769969 Jun 05 05:58:31 PM PDT 24 Jun 05 05:58:33 PM PDT 24 67085386 ps
T154 /workspace/coverage/default/23.edn_disable.3811214608 Jun 05 05:56:48 PM PDT 24 Jun 05 05:56:50 PM PDT 24 11572872 ps
T808 /workspace/coverage/default/2.edn_disable_auto_req_mode.2883101090 Jun 05 05:56:50 PM PDT 24 Jun 05 05:56:53 PM PDT 24 36161858 ps
T809 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4101817747 Jun 05 05:56:54 PM PDT 24 Jun 05 06:06:27 PM PDT 24 50345457140 ps
T810 /workspace/coverage/default/75.edn_err.253070453 Jun 05 05:57:45 PM PDT 24 Jun 05 05:57:48 PM PDT 24 18181032 ps
T811 /workspace/coverage/default/82.edn_genbits.3685997570 Jun 05 05:57:43 PM PDT 24 Jun 05 05:57:46 PM PDT 24 40703483 ps
T812 /workspace/coverage/default/0.edn_alert.2967438636 Jun 05 05:56:43 PM PDT 24 Jun 05 05:56:44 PM PDT 24 27279636 ps
T813 /workspace/coverage/default/3.edn_stress_all.2940954591 Jun 05 05:56:51 PM PDT 24 Jun 05 05:56:58 PM PDT 24 562962227 ps
T814 /workspace/coverage/default/34.edn_disable_auto_req_mode.1096051297 Jun 05 05:57:26 PM PDT 24 Jun 05 05:57:28 PM PDT 24 119001856 ps
T815 /workspace/coverage/default/73.edn_err.2251788013 Jun 05 05:57:46 PM PDT 24 Jun 05 05:57:49 PM PDT 24 26623452 ps
T816 /workspace/coverage/default/262.edn_genbits.860559234 Jun 05 05:58:31 PM PDT 24 Jun 05 05:58:33 PM PDT 24 45329336 ps
T817 /workspace/coverage/default/26.edn_smoke.364891424 Jun 05 05:57:01 PM PDT 24 Jun 05 05:57:03 PM PDT 24 26862878 ps
T818 /workspace/coverage/default/270.edn_genbits.3515880470 Jun 05 05:58:16 PM PDT 24 Jun 05 05:58:17 PM PDT 24 77990185 ps
T819 /workspace/coverage/default/3.edn_intr.1746776183 Jun 05 05:56:42 PM PDT 24 Jun 05 05:56:44 PM PDT 24 24254484 ps
T820 /workspace/coverage/default/4.edn_smoke.2181141012 Jun 05 05:56:53 PM PDT 24 Jun 05 05:56:55 PM PDT 24 23030716 ps
T145 /workspace/coverage/default/31.edn_intr.2031482629 Jun 05 05:57:18 PM PDT 24 Jun 05 05:57:20 PM PDT 24 19806472 ps
T821 /workspace/coverage/default/235.edn_genbits.3522647103 Jun 05 05:58:29 PM PDT 24 Jun 05 05:58:31 PM PDT 24 104167785 ps
T822 /workspace/coverage/default/3.edn_smoke.3202680557 Jun 05 05:56:50 PM PDT 24 Jun 05 05:56:53 PM PDT 24 22943879 ps
T823 /workspace/coverage/default/0.edn_disable.2652318603 Jun 05 05:56:48 PM PDT 24 Jun 05 05:56:51 PM PDT 24 12375753 ps
T824 /workspace/coverage/default/42.edn_genbits.2856491904 Jun 05 05:58:56 PM PDT 24 Jun 05 05:58:58 PM PDT 24 26335222 ps
T825 /workspace/coverage/default/211.edn_genbits.1984929542 Jun 05 05:58:12 PM PDT 24 Jun 05 05:58:14 PM PDT 24 27899473 ps
T826 /workspace/coverage/default/21.edn_err.1930532625 Jun 05 05:56:49 PM PDT 24 Jun 05 05:56:52 PM PDT 24 18033927 ps
T162 /workspace/coverage/default/88.edn_err.824016132 Jun 05 05:57:47 PM PDT 24 Jun 05 05:57:49 PM PDT 24 24880753 ps
T827 /workspace/coverage/default/271.edn_genbits.874275095 Jun 05 05:58:11 PM PDT 24 Jun 05 05:58:14 PM PDT 24 51227133 ps
T828 /workspace/coverage/default/201.edn_genbits.1558976036 Jun 05 05:57:54 PM PDT 24 Jun 05 05:57:56 PM PDT 24 35407519 ps
T829 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3791575246 Jun 05 05:57:46 PM PDT 24 Jun 05 06:02:37 PM PDT 24 20934885436 ps
T830 /workspace/coverage/default/35.edn_genbits.3225122350 Jun 05 05:57:17 PM PDT 24 Jun 05 05:57:19 PM PDT 24 39857607 ps
T831 /workspace/coverage/default/40.edn_genbits.1377765380 Jun 05 05:57:34 PM PDT 24 Jun 05 05:57:37 PM PDT 24 29835877 ps
T56 /workspace/coverage/default/3.edn_disable_auto_req_mode.519720018 Jun 05 05:56:45 PM PDT 24 Jun 05 05:56:47 PM PDT 24 91118168 ps
T832 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3770450047 Jun 05 05:57:39 PM PDT 24 Jun 05 06:08:14 PM PDT 24 28285007648 ps
T833 /workspace/coverage/default/49.edn_genbits.3580807679 Jun 05 05:57:46 PM PDT 24 Jun 05 05:57:49 PM PDT 24 73135909 ps
T834 /workspace/coverage/default/9.edn_intr.2100234998 Jun 05 05:56:49 PM PDT 24 Jun 05 05:56:51 PM PDT 24 22488207 ps
T835 /workspace/coverage/default/9.edn_err.1328281433 Jun 05 05:56:55 PM PDT 24 Jun 05 05:56:57 PM PDT 24 36048428 ps
T836 /workspace/coverage/default/142.edn_genbits.2612328592 Jun 05 05:58:14 PM PDT 24 Jun 05 05:58:16 PM PDT 24 63645513 ps
T837 /workspace/coverage/default/96.edn_genbits.1689668119 Jun 05 05:57:45 PM PDT 24 Jun 05 05:57:47 PM PDT 24 57336728 ps
T265 /workspace/coverage/default/43.edn_alert.616733619 Jun 05 05:58:56 PM PDT 24 Jun 05 05:58:58 PM PDT 24 91528375 ps
T838 /workspace/coverage/default/146.edn_genbits.1749708510 Jun 05 05:57:48 PM PDT 24 Jun 05 05:57:51 PM PDT 24 45145221 ps
T839 /workspace/coverage/default/18.edn_alert.553808122 Jun 05 05:57:00 PM PDT 24 Jun 05 05:57:01 PM PDT 24 32709790 ps
T840 /workspace/coverage/default/82.edn_err.732107111 Jun 05 05:58:15 PM PDT 24 Jun 05 05:58:16 PM PDT 24 20204990 ps
T46 /workspace/coverage/default/6.edn_err.3296749164 Jun 05 05:56:59 PM PDT 24 Jun 05 05:57:01 PM PDT 24 41639186 ps
T841 /workspace/coverage/default/28.edn_alert_test.1709895015 Jun 05 05:57:17 PM PDT 24 Jun 05 05:57:18 PM PDT 24 21196951 ps
T842 /workspace/coverage/default/136.edn_genbits.3658286167 Jun 05 05:57:51 PM PDT 24 Jun 05 05:57:54 PM PDT 24 91731411 ps
T62 /workspace/coverage/default/67.edn_err.2998504052 Jun 05 05:57:45 PM PDT 24 Jun 05 05:57:48 PM PDT 24 22367608 ps
T843 /workspace/coverage/default/39.edn_genbits.1483842585 Jun 05 05:57:40 PM PDT 24 Jun 05 05:57:43 PM PDT 24 43065613 ps
T844 /workspace/coverage/default/27.edn_alert.296703557 Jun 05 05:57:16 PM PDT 24 Jun 05 05:57:18 PM PDT 24 78797984 ps
T845 /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3585758814 Jun 05 05:57:39 PM PDT 24 Jun 05 06:10:48 PM PDT 24 34739860344 ps
T846 /workspace/coverage/default/13.edn_disable.2445211243 Jun 05 05:56:47 PM PDT 24 Jun 05 05:56:49 PM PDT 24 11978528 ps
T847 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3146880329 Jun 05 05:55:06 PM PDT 24 Jun 05 05:55:13 PM PDT 24 85504101 ps
T234 /workspace/coverage/cover_reg_top/13.edn_csr_rw.3507216756 Jun 05 05:55:30 PM PDT 24 Jun 05 05:55:31 PM PDT 24 28186485 ps
T848 /workspace/coverage/cover_reg_top/49.edn_intr_test.444584552 Jun 05 05:55:51 PM PDT 24 Jun 05 05:55:52 PM PDT 24 19394718 ps
T206 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2870837420 Jun 05 05:55:17 PM PDT 24 Jun 05 05:55:20 PM PDT 24 40561588 ps
T849 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1258289523 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:14 PM PDT 24 77535236 ps
T850 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1916219189 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:16 PM PDT 24 551442551 ps
T236 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3126156598 Jun 05 05:55:05 PM PDT 24 Jun 05 05:55:09 PM PDT 24 102409019 ps
T237 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1439375558 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:18 PM PDT 24 70948084 ps
T222 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1572635820 Jun 05 05:55:25 PM PDT 24 Jun 05 05:55:27 PM PDT 24 34452853 ps
T851 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2651902517 Jun 05 05:55:37 PM PDT 24 Jun 05 05:55:39 PM PDT 24 51140579 ps
T238 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3623727636 Jun 05 05:55:50 PM PDT 24 Jun 05 05:55:54 PM PDT 24 337648091 ps
T852 /workspace/coverage/cover_reg_top/13.edn_intr_test.587566662 Jun 05 05:55:25 PM PDT 24 Jun 05 05:55:26 PM PDT 24 28661038 ps
T235 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3104170613 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 27434743 ps
T207 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2034867362 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:14 PM PDT 24 51118749 ps
T223 /workspace/coverage/cover_reg_top/2.edn_csr_rw.432926326 Jun 05 05:55:13 PM PDT 24 Jun 05 05:55:15 PM PDT 24 47355540 ps
T853 /workspace/coverage/cover_reg_top/11.edn_tl_errors.303744348 Jun 05 05:55:26 PM PDT 24 Jun 05 05:55:29 PM PDT 24 228440084 ps
T224 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.880523336 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:17 PM PDT 24 95828786 ps
T854 /workspace/coverage/cover_reg_top/3.edn_csr_rw.572659814 Jun 05 05:55:13 PM PDT 24 Jun 05 05:55:15 PM PDT 24 81383882 ps
T225 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1702817507 Jun 05 05:55:22 PM PDT 24 Jun 05 05:55:24 PM PDT 24 85041230 ps
T855 /workspace/coverage/cover_reg_top/3.edn_tl_errors.454650234 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:16 PM PDT 24 74576211 ps
T856 /workspace/coverage/cover_reg_top/7.edn_csr_rw.2672433296 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:17 PM PDT 24 98813926 ps
T857 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.918667614 Jun 05 05:55:04 PM PDT 24 Jun 05 05:55:07 PM PDT 24 80056704 ps
T858 /workspace/coverage/cover_reg_top/12.edn_intr_test.1061672755 Jun 05 05:55:41 PM PDT 24 Jun 05 05:55:43 PM PDT 24 17569680 ps
T859 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.267950621 Jun 05 05:55:33 PM PDT 24 Jun 05 05:55:35 PM PDT 24 106979549 ps
T860 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2942722834 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:17 PM PDT 24 32019426 ps
T226 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.16477499 Jun 05 05:55:46 PM PDT 24 Jun 05 05:55:48 PM PDT 24 32466912 ps
T208 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2786816432 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:13 PM PDT 24 12833767 ps
T209 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1582576159 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:13 PM PDT 24 24689746 ps
T861 /workspace/coverage/cover_reg_top/23.edn_intr_test.2172896256 Jun 05 05:55:46 PM PDT 24 Jun 05 05:55:48 PM PDT 24 23719776 ps
T862 /workspace/coverage/cover_reg_top/17.edn_intr_test.3079994697 Jun 05 05:55:35 PM PDT 24 Jun 05 05:55:36 PM PDT 24 58647668 ps
T863 /workspace/coverage/cover_reg_top/15.edn_csr_rw.3506825592 Jun 05 05:55:43 PM PDT 24 Jun 05 05:55:45 PM PDT 24 104966473 ps
T864 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1323998374 Jun 05 05:55:04 PM PDT 24 Jun 05 05:55:08 PM PDT 24 373795982 ps
T865 /workspace/coverage/cover_reg_top/7.edn_intr_test.1401461537 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 23275885 ps
T210 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2436009357 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:16 PM PDT 24 15547946 ps
T243 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.372737627 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:14 PM PDT 24 66051910 ps
T866 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2615291994 Jun 05 05:55:24 PM PDT 24 Jun 05 05:55:28 PM PDT 24 238009039 ps
T867 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.712570264 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:11 PM PDT 24 78482796 ps
T868 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1368695518 Jun 05 05:55:40 PM PDT 24 Jun 05 05:55:42 PM PDT 24 117521186 ps
T211 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3793012489 Jun 05 05:55:46 PM PDT 24 Jun 05 05:55:48 PM PDT 24 40705977 ps
T869 /workspace/coverage/cover_reg_top/6.edn_intr_test.1128186167 Jun 05 05:55:32 PM PDT 24 Jun 05 05:55:34 PM PDT 24 23699133 ps
T870 /workspace/coverage/cover_reg_top/8.edn_intr_test.2520503618 Jun 05 05:55:27 PM PDT 24 Jun 05 05:55:29 PM PDT 24 12863681 ps
T871 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3340156711 Jun 05 05:55:37 PM PDT 24 Jun 05 05:55:39 PM PDT 24 145831093 ps
T872 /workspace/coverage/cover_reg_top/34.edn_intr_test.3699118354 Jun 05 05:55:52 PM PDT 24 Jun 05 05:55:54 PM PDT 24 17058812 ps
T873 /workspace/coverage/cover_reg_top/19.edn_tl_errors.4254879721 Jun 05 05:55:32 PM PDT 24 Jun 05 05:55:35 PM PDT 24 283070954 ps
T212 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1831470381 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:47 PM PDT 24 22955594 ps
T213 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1911983819 Jun 05 05:55:05 PM PDT 24 Jun 05 05:55:07 PM PDT 24 50537649 ps
T874 /workspace/coverage/cover_reg_top/11.edn_intr_test.2976536556 Jun 05 05:55:23 PM PDT 24 Jun 05 05:55:24 PM PDT 24 20244278 ps
T875 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2780112287 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 21041793 ps
T876 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2245601755 Jun 05 05:55:24 PM PDT 24 Jun 05 05:55:27 PM PDT 24 78387473 ps
T247 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.759894537 Jun 05 05:55:31 PM PDT 24 Jun 05 05:55:34 PM PDT 24 242041914 ps
T877 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2299106084 Jun 05 05:55:26 PM PDT 24 Jun 05 05:55:29 PM PDT 24 87389208 ps
T878 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1154508823 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:47 PM PDT 24 30043863 ps
T879 /workspace/coverage/cover_reg_top/2.edn_intr_test.1849796569 Jun 05 05:55:12 PM PDT 24 Jun 05 05:55:14 PM PDT 24 34807871 ps
T244 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3029500306 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:11 PM PDT 24 168538333 ps
T880 /workspace/coverage/cover_reg_top/10.edn_intr_test.788655357 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:16 PM PDT 24 35957075 ps
T881 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4008971096 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:13 PM PDT 24 22375669 ps
T882 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2195105812 Jun 05 05:55:50 PM PDT 24 Jun 05 05:55:53 PM PDT 24 48658287 ps
T883 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2988408233 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:18 PM PDT 24 112695738 ps
T884 /workspace/coverage/cover_reg_top/36.edn_intr_test.823701799 Jun 05 05:55:40 PM PDT 24 Jun 05 05:55:41 PM PDT 24 17015205 ps
T885 /workspace/coverage/cover_reg_top/45.edn_intr_test.2308368844 Jun 05 05:55:42 PM PDT 24 Jun 05 05:55:44 PM PDT 24 19195943 ps
T214 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.904937385 Jun 05 05:55:42 PM PDT 24 Jun 05 05:55:44 PM PDT 24 32617095 ps
T886 /workspace/coverage/cover_reg_top/38.edn_intr_test.1648549577 Jun 05 05:55:41 PM PDT 24 Jun 05 05:55:43 PM PDT 24 15172561 ps
T887 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.694365171 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:17 PM PDT 24 122117819 ps
T215 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1295171365 Jun 05 05:55:36 PM PDT 24 Jun 05 05:55:37 PM PDT 24 12594126 ps
T888 /workspace/coverage/cover_reg_top/18.edn_intr_test.3508180385 Jun 05 05:55:40 PM PDT 24 Jun 05 05:55:41 PM PDT 24 29272722 ps
T889 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.651676631 Jun 05 05:55:34 PM PDT 24 Jun 05 05:55:36 PM PDT 24 197857355 ps
T890 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2666114763 Jun 05 05:55:35 PM PDT 24 Jun 05 05:55:36 PM PDT 24 57209581 ps
T891 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2282607547 Jun 05 05:55:50 PM PDT 24 Jun 05 05:55:52 PM PDT 24 46771915 ps
T892 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2964656420 Jun 05 05:55:16 PM PDT 24 Jun 05 05:55:18 PM PDT 24 22916173 ps
T893 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4143174373 Jun 05 05:55:42 PM PDT 24 Jun 05 05:55:44 PM PDT 24 131648088 ps
T894 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1748550593 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:13 PM PDT 24 92630458 ps
T895 /workspace/coverage/cover_reg_top/46.edn_intr_test.3430296055 Jun 05 05:55:54 PM PDT 24 Jun 05 05:56:02 PM PDT 24 22097792 ps
T216 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3763914379 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:12 PM PDT 24 51331678 ps
T896 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2786033185 Jun 05 05:55:30 PM PDT 24 Jun 05 05:55:34 PM PDT 24 193415589 ps
T897 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1310607118 Jun 05 05:55:36 PM PDT 24 Jun 05 05:55:38 PM PDT 24 46732861 ps
T898 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2466851872 Jun 05 05:55:32 PM PDT 24 Jun 05 05:55:34 PM PDT 24 123771985 ps
T899 /workspace/coverage/cover_reg_top/43.edn_intr_test.1978369576 Jun 05 05:55:47 PM PDT 24 Jun 05 05:55:49 PM PDT 24 39196526 ps
T900 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1366149444 Jun 05 05:55:24 PM PDT 24 Jun 05 05:55:26 PM PDT 24 59175604 ps
T901 /workspace/coverage/cover_reg_top/28.edn_intr_test.3933450603 Jun 05 05:55:59 PM PDT 24 Jun 05 05:56:01 PM PDT 24 47084922 ps
T902 /workspace/coverage/cover_reg_top/32.edn_intr_test.392662511 Jun 05 05:55:54 PM PDT 24 Jun 05 05:55:56 PM PDT 24 14407509 ps
T903 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.471959170 Jun 05 05:55:29 PM PDT 24 Jun 05 05:55:31 PM PDT 24 86147921 ps
T904 /workspace/coverage/cover_reg_top/25.edn_intr_test.1103477544 Jun 05 05:55:55 PM PDT 24 Jun 05 05:55:57 PM PDT 24 79869391 ps
T905 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3632391610 Jun 05 05:55:44 PM PDT 24 Jun 05 05:55:46 PM PDT 24 69071719 ps
T906 /workspace/coverage/cover_reg_top/16.edn_intr_test.1408791626 Jun 05 05:55:44 PM PDT 24 Jun 05 05:55:45 PM PDT 24 42173540 ps
T907 /workspace/coverage/cover_reg_top/19.edn_intr_test.3976005256 Jun 05 05:55:46 PM PDT 24 Jun 05 05:55:48 PM PDT 24 15307820 ps
T908 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3546056410 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:13 PM PDT 24 58311726 ps
T909 /workspace/coverage/cover_reg_top/39.edn_intr_test.3245610105 Jun 05 05:55:48 PM PDT 24 Jun 05 05:55:50 PM PDT 24 51722633 ps
T910 /workspace/coverage/cover_reg_top/31.edn_intr_test.4212432394 Jun 05 05:55:47 PM PDT 24 Jun 05 05:55:49 PM PDT 24 14329093 ps
T911 /workspace/coverage/cover_reg_top/8.edn_csr_rw.760117039 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 39938791 ps
T912 /workspace/coverage/cover_reg_top/8.edn_tl_errors.902492447 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:15 PM PDT 24 69323757 ps
T913 /workspace/coverage/cover_reg_top/30.edn_intr_test.1863248708 Jun 05 05:55:56 PM PDT 24 Jun 05 05:55:58 PM PDT 24 28820016 ps
T914 /workspace/coverage/cover_reg_top/27.edn_intr_test.3821900068 Jun 05 05:55:51 PM PDT 24 Jun 05 05:55:52 PM PDT 24 59534068 ps
T915 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1278123425 Jun 05 05:55:04 PM PDT 24 Jun 05 05:55:07 PM PDT 24 25314314 ps
T916 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.962222623 Jun 05 05:55:40 PM PDT 24 Jun 05 05:55:42 PM PDT 24 50120583 ps
T917 /workspace/coverage/cover_reg_top/21.edn_intr_test.1061247775 Jun 05 05:55:57 PM PDT 24 Jun 05 05:55:59 PM PDT 24 40993730 ps
T918 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3059811674 Jun 05 05:55:06 PM PDT 24 Jun 05 05:55:08 PM PDT 24 47821342 ps
T919 /workspace/coverage/cover_reg_top/15.edn_intr_test.2942954528 Jun 05 05:55:42 PM PDT 24 Jun 05 05:55:44 PM PDT 24 36058744 ps
T920 /workspace/coverage/cover_reg_top/24.edn_intr_test.4244264424 Jun 05 05:55:47 PM PDT 24 Jun 05 05:55:49 PM PDT 24 55993040 ps
T921 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1091098404 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:18 PM PDT 24 148428801 ps
T922 /workspace/coverage/cover_reg_top/37.edn_intr_test.315652528 Jun 05 05:55:51 PM PDT 24 Jun 05 05:55:52 PM PDT 24 14630697 ps
T923 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3783048954 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:16 PM PDT 24 30739179 ps
T924 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2712811118 Jun 05 05:55:41 PM PDT 24 Jun 05 05:55:43 PM PDT 24 19295473 ps
T925 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.267035063 Jun 05 05:55:22 PM PDT 24 Jun 05 05:55:24 PM PDT 24 373851592 ps
T926 /workspace/coverage/cover_reg_top/9.edn_intr_test.1946656774 Jun 05 05:55:20 PM PDT 24 Jun 05 05:55:22 PM PDT 24 17001239 ps
T927 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3653082303 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:18 PM PDT 24 736476001 ps
T928 /workspace/coverage/cover_reg_top/18.edn_tl_errors.359338780 Jun 05 05:55:40 PM PDT 24 Jun 05 05:55:44 PM PDT 24 226654197 ps
T929 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4168503474 Jun 05 05:55:39 PM PDT 24 Jun 05 05:55:41 PM PDT 24 26920578 ps
T930 /workspace/coverage/cover_reg_top/42.edn_intr_test.545122584 Jun 05 05:55:51 PM PDT 24 Jun 05 05:55:53 PM PDT 24 13611001 ps
T931 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2597334313 Jun 05 05:55:12 PM PDT 24 Jun 05 05:55:16 PM PDT 24 35917086 ps
T221 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1524117352 Jun 05 05:55:06 PM PDT 24 Jun 05 05:55:08 PM PDT 24 14367344 ps
T245 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1051770790 Jun 05 05:55:22 PM PDT 24 Jun 05 05:55:25 PM PDT 24 96941414 ps
T932 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2860071983 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:14 PM PDT 24 38430853 ps
T933 /workspace/coverage/cover_reg_top/47.edn_intr_test.285766474 Jun 05 05:55:43 PM PDT 24 Jun 05 05:55:45 PM PDT 24 26305999 ps
T934 /workspace/coverage/cover_reg_top/26.edn_intr_test.3787806219 Jun 05 05:55:44 PM PDT 24 Jun 05 05:55:45 PM PDT 24 29238921 ps
T935 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1978787541 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:12 PM PDT 24 107263910 ps
T936 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3003847168 Jun 05 05:55:04 PM PDT 24 Jun 05 05:55:06 PM PDT 24 44367416 ps
T937 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3236558972 Jun 05 05:55:51 PM PDT 24 Jun 05 05:55:53 PM PDT 24 18963597 ps
T938 /workspace/coverage/cover_reg_top/0.edn_intr_test.1974798062 Jun 05 05:55:12 PM PDT 24 Jun 05 05:55:14 PM PDT 24 50379598 ps
T939 /workspace/coverage/cover_reg_top/44.edn_intr_test.1145430849 Jun 05 05:55:41 PM PDT 24 Jun 05 05:55:43 PM PDT 24 15649506 ps
T940 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.861229462 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:13 PM PDT 24 49568806 ps
T941 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1403822213 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:16 PM PDT 24 151223482 ps
T942 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1320916140 Jun 05 05:55:07 PM PDT 24 Jun 05 05:55:10 PM PDT 24 140990064 ps
T943 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.967656986 Jun 05 05:55:36 PM PDT 24 Jun 05 05:55:38 PM PDT 24 937585520 ps
T944 /workspace/coverage/cover_reg_top/4.edn_intr_test.2237806906 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:10 PM PDT 24 12691467 ps
T945 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2421163767 Jun 05 05:55:27 PM PDT 24 Jun 05 05:55:30 PM PDT 24 32744811 ps
T946 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1538044747 Jun 05 05:55:43 PM PDT 24 Jun 05 05:55:45 PM PDT 24 57157601 ps
T947 /workspace/coverage/cover_reg_top/14.edn_intr_test.183463015 Jun 05 05:55:27 PM PDT 24 Jun 05 05:55:28 PM PDT 24 18559338 ps
T948 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.389469917 Jun 05 05:55:06 PM PDT 24 Jun 05 05:55:10 PM PDT 24 109796476 ps
T217 /workspace/coverage/cover_reg_top/12.edn_csr_rw.4055847228 Jun 05 05:55:33 PM PDT 24 Jun 05 05:55:34 PM PDT 24 21383342 ps
T949 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4099393210 Jun 05 05:55:26 PM PDT 24 Jun 05 05:55:29 PM PDT 24 94925918 ps
T950 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3769704043 Jun 05 05:55:19 PM PDT 24 Jun 05 05:55:22 PM PDT 24 309571513 ps
T951 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3555750990 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:10 PM PDT 24 31220480 ps
T952 /workspace/coverage/cover_reg_top/33.edn_intr_test.3213091773 Jun 05 05:55:55 PM PDT 24 Jun 05 05:55:57 PM PDT 24 22554761 ps
T953 /workspace/coverage/cover_reg_top/48.edn_intr_test.2513936170 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:47 PM PDT 24 34605745 ps
T954 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2788877449 Jun 05 05:55:17 PM PDT 24 Jun 05 05:55:20 PM PDT 24 71298863 ps
T955 /workspace/coverage/cover_reg_top/35.edn_intr_test.711164790 Jun 05 05:55:41 PM PDT 24 Jun 05 05:55:42 PM PDT 24 30971810 ps
T956 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3417539792 Jun 05 05:55:37 PM PDT 24 Jun 05 05:55:39 PM PDT 24 12421933 ps
T218 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1159401852 Jun 05 05:55:03 PM PDT 24 Jun 05 05:55:06 PM PDT 24 16711470 ps
T246 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3358050523 Jun 05 05:55:47 PM PDT 24 Jun 05 05:55:50 PM PDT 24 283086292 ps
T957 /workspace/coverage/cover_reg_top/20.edn_intr_test.984250458 Jun 05 05:55:52 PM PDT 24 Jun 05 05:55:53 PM PDT 24 13580969 ps
T958 /workspace/coverage/cover_reg_top/1.edn_intr_test.1556068211 Jun 05 05:55:15 PM PDT 24 Jun 05 05:55:17 PM PDT 24 14322862 ps
T959 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.350365844 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 66572397 ps
T960 /workspace/coverage/cover_reg_top/29.edn_intr_test.1197612753 Jun 05 05:55:50 PM PDT 24 Jun 05 05:55:52 PM PDT 24 12487060 ps
T961 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.401537281 Jun 05 05:55:32 PM PDT 24 Jun 05 05:55:33 PM PDT 24 74300460 ps
T962 /workspace/coverage/cover_reg_top/41.edn_intr_test.2443516678 Jun 05 05:55:55 PM PDT 24 Jun 05 05:55:56 PM PDT 24 14559896 ps
T963 /workspace/coverage/cover_reg_top/3.edn_intr_test.4231998952 Jun 05 05:55:13 PM PDT 24 Jun 05 05:55:15 PM PDT 24 52323178 ps
T964 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2231787869 Jun 05 05:55:14 PM PDT 24 Jun 05 05:55:16 PM PDT 24 56014968 ps
T965 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2623645585 Jun 05 05:55:06 PM PDT 24 Jun 05 05:55:09 PM PDT 24 67035691 ps
T966 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2234407149 Jun 05 05:55:29 PM PDT 24 Jun 05 05:55:31 PM PDT 24 11823215 ps
T967 /workspace/coverage/cover_reg_top/5.edn_intr_test.1610007317 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:12 PM PDT 24 33355389 ps
T968 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1794679124 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:48 PM PDT 24 39057723 ps
T969 /workspace/coverage/cover_reg_top/22.edn_intr_test.3295006069 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:47 PM PDT 24 87551786 ps
T219 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1596780643 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:14 PM PDT 24 96057724 ps
T970 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1288822542 Jun 05 05:55:12 PM PDT 24 Jun 05 05:55:17 PM PDT 24 91869166 ps
T971 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1955275867 Jun 05 05:55:09 PM PDT 24 Jun 05 05:55:12 PM PDT 24 84949011 ps
T972 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3843434115 Jun 05 05:55:12 PM PDT 24 Jun 05 05:55:14 PM PDT 24 58860212 ps
T973 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1550080124 Jun 05 05:55:24 PM PDT 24 Jun 05 05:55:25 PM PDT 24 42616094 ps
T974 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.933623585 Jun 05 05:55:37 PM PDT 24 Jun 05 05:55:39 PM PDT 24 30029185 ps
T975 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3948841385 Jun 05 05:55:11 PM PDT 24 Jun 05 05:55:13 PM PDT 24 25407336 ps
T976 /workspace/coverage/cover_reg_top/40.edn_intr_test.135069414 Jun 05 05:55:45 PM PDT 24 Jun 05 05:55:47 PM PDT 24 15098174 ps
T977 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2825062510 Jun 05 05:55:08 PM PDT 24 Jun 05 05:55:12 PM PDT 24 44852643 ps
T220 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1804744866 Jun 05 05:55:10 PM PDT 24 Jun 05 05:55:13 PM PDT 24 46969328 ps
T978 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.596594228 Jun 05 05:55:50 PM PDT 24 Jun 05 05:55:52 PM PDT 24 21317696 ps
T979 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1555009638 Jun 05 05:55:03 PM PDT 24 Jun 05 05:55:05 PM PDT 24 32788905 ps
T980 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2806534817 Jun 05 05:55:07 PM PDT 24 Jun 05 05:55:09 PM PDT 24 18479137 ps

Test location /workspace/coverage/default/79.edn_genbits.1253699873
Short name T2
Test name
Test status
Simulation time 71760912 ps
CPU time 2.51 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 219364 kb
Host smart-ac1a4570-444c-47c5-8228-33df0f7d6b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253699873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1253699873
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2930512555
Short name T116
Test name
Test status
Simulation time 571336248831 ps
CPU time 1257.21 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 06:17:49 PM PDT 24
Peak memory 223272 kb
Host smart-2e221844-14fe-4b99-b454-db204624449b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930512555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2930512555
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4203512791
Short name T4
Test name
Test status
Simulation time 1046150570 ps
CPU time 7.92 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 235808 kb
Host smart-6ebbda51-0853-4d7e-a25d-f753e1c39cb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203512791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4203512791
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/68.edn_err.3899580690
Short name T22
Test name
Test status
Simulation time 22558527 ps
CPU time 1.08 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:40 PM PDT 24
Peak memory 218224 kb
Host smart-b7206c84-7a33-4bb1-aa25-3058e2c06b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899580690 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3899580690
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.2762148553
Short name T97
Test name
Test status
Simulation time 35414184 ps
CPU time 1.07 seconds
Started Jun 05 05:56:46 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 215428 kb
Host smart-cde8e55e-6461-46e9-9878-571fdecb55a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762148553 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2762148553
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1156680728
Short name T14
Test name
Test status
Simulation time 1200815204 ps
CPU time 4.23 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 234424 kb
Host smart-7a59f033-2983-4f1c-a104-6128f44a767d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156680728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1156680728
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/27.edn_disable.3085702367
Short name T84
Test name
Test status
Simulation time 16703828 ps
CPU time 0.86 seconds
Started Jun 05 05:57:04 PM PDT 24
Finished Jun 05 05:57:06 PM PDT 24
Peak memory 216096 kb
Host smart-d90bc246-a5a8-4e04-9a66-8f6c40ee174d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085702367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3085702367
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.3234047822
Short name T8
Test name
Test status
Simulation time 28809110 ps
CPU time 1.08 seconds
Started Jun 05 05:57:11 PM PDT 24
Finished Jun 05 05:57:13 PM PDT 24
Peak memory 216740 kb
Host smart-c78c744f-01d3-48cb-a2ae-0b570affd3cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234047822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.3234047822
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_alert.3627142681
Short name T71
Test name
Test status
Simulation time 77371558 ps
CPU time 1.12 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 215432 kb
Host smart-cf0ac28d-94eb-406a-a580-22f05dbb9570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627142681 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3627142681
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.852980632
Short name T253
Test name
Test status
Simulation time 72001302 ps
CPU time 1.22 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 215436 kb
Host smart-21606786-7e61-485d-a25a-3276b182e6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852980632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.852980632
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/18.edn_err.1261859494
Short name T100
Test name
Test status
Simulation time 26714741 ps
CPU time 1 seconds
Started Jun 05 05:57:08 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 228724 kb
Host smart-555233b6-06d4-403a-abaa-f11480a03e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261859494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1261859494
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/48.edn_alert.678650056
Short name T24
Test name
Test status
Simulation time 24084396 ps
CPU time 1.2 seconds
Started Jun 05 05:58:02 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 215408 kb
Host smart-5887f622-a5c3-4371-8174-cc8a612ba4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678650056 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.678650056
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2278118289
Short name T117
Test name
Test status
Simulation time 170497469192 ps
CPU time 1933.45 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 06:30:00 PM PDT 24
Peak memory 225872 kb
Host smart-f4a473fe-d346-468e-958e-1d32728e5e2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278118289 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2278118289
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.edn_regwen.2391775815
Short name T254
Test name
Test status
Simulation time 19269351 ps
CPU time 1.11 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 206856 kb
Host smart-78661647-b0fe-49e7-919c-d238be820694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391775815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2391775815
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/115.edn_genbits.1762357238
Short name T26
Test name
Test status
Simulation time 65948593 ps
CPU time 1.55 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 218140 kb
Host smart-cc458d22-6704-4d5e-a560-b75ee5c8ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762357238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1762357238
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.4143174373
Short name T893
Test name
Test status
Simulation time 131648088 ps
CPU time 1.62 seconds
Started Jun 05 05:55:42 PM PDT 24
Finished Jun 05 05:55:44 PM PDT 24
Peak memory 206720 kb
Host smart-9b5093a6-a14f-435e-ae42-dcffbe9f7895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143174373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.4143174373
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1295171365
Short name T215
Test name
Test status
Simulation time 12594126 ps
CPU time 0.87 seconds
Started Jun 05 05:55:36 PM PDT 24
Finished Jun 05 05:55:37 PM PDT 24
Peak memory 206648 kb
Host smart-57c90660-2ff5-4107-bab2-e9e526771fc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295171365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1295171365
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.519720018
Short name T56
Test name
Test status
Simulation time 91118168 ps
CPU time 1.17 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 216752 kb
Host smart-d6216cc2-215a-4af5-9c82-e0f85a30b4ea
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519720018 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.519720018
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_disable.848610260
Short name T165
Test name
Test status
Simulation time 12502630 ps
CPU time 0.9 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215356 kb
Host smart-d8997123-82ab-4160-afea-4d7df414099c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848610260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.848610260
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.1017602670
Short name T149
Test name
Test status
Simulation time 29346454 ps
CPU time 0.86 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215992 kb
Host smart-b09b94ac-3e78-4f1a-871b-57259a0ae72f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017602670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1017602670
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3863758180
Short name T163
Test name
Test status
Simulation time 90324536 ps
CPU time 1.1 seconds
Started Jun 05 05:56:46 PM PDT 24
Finished Jun 05 05:56:48 PM PDT 24
Peak memory 216648 kb
Host smart-2276df19-7b5d-49f8-ad9e-9638c7bad30e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863758180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3863758180
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_disable.1302608248
Short name T81
Test name
Test status
Simulation time 15994410 ps
CPU time 0.92 seconds
Started Jun 05 05:57:31 PM PDT 24
Finished Jun 05 05:57:32 PM PDT 24
Peak memory 216240 kb
Host smart-e5c55c73-26a9-4e8a-aec1-c488a3e1b94f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302608248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1302608248
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/91.edn_genbits.1697823883
Short name T130
Test name
Test status
Simulation time 74611896 ps
CPU time 1.14 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 219324 kb
Host smart-61ec44af-61b9-4af0-ae1c-a53b73727b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697823883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1697823883
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_genbits.3266744427
Short name T133
Test name
Test status
Simulation time 381688517 ps
CPU time 2.57 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218200 kb
Host smart-0b8219f1-d05d-401d-a215-249ecba34722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266744427 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3266744427
Directory /workspace/99.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3549875322
Short name T248
Test name
Test status
Simulation time 62652479 ps
CPU time 1.2 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 215428 kb
Host smart-91b85c87-d6a0-4a23-bb0b-af4c23c9418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549875322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3549875322
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1335246351
Short name T48
Test name
Test status
Simulation time 87921226 ps
CPU time 1.09 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 217972 kb
Host smart-cb7b2ac6-8a7f-40d8-aa49-747bbf423267
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335246351 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1335246351
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_intr.2652239882
Short name T112
Test name
Test status
Simulation time 26383984 ps
CPU time 0.97 seconds
Started Jun 05 05:57:20 PM PDT 24
Finished Jun 05 05:57:21 PM PDT 24
Peak memory 215368 kb
Host smart-fceaa285-f295-484b-ad84-45f9a4c7a8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652239882 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2652239882
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/172.edn_genbits.3205357547
Short name T271
Test name
Test status
Simulation time 62306322 ps
CPU time 1.51 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218092 kb
Host smart-1dfb1fcf-de0d-405c-b778-baf637aaa1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205357547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3205357547
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_disable.519318722
Short name T93
Test name
Test status
Simulation time 42968332 ps
CPU time 0.84 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 216080 kb
Host smart-f249c0f9-ea21-4d55-b8a9-6814c54b92d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519318722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.519318722
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/0.edn_intr.4253994209
Short name T714
Test name
Test status
Simulation time 22936286 ps
CPU time 0.93 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:39 PM PDT 24
Peak memory 215484 kb
Host smart-031dea97-55fd-4ba3-9250-426338daa119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253994209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4253994209
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4238129911
Short name T59
Test name
Test status
Simulation time 135847490 ps
CPU time 1.19 seconds
Started Jun 05 05:56:33 PM PDT 24
Finished Jun 05 05:56:35 PM PDT 24
Peak memory 216728 kb
Host smart-30152bac-ca97-4e47-9f03-32d1412dbb7d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238129911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4238129911
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable.248529907
Short name T151
Test name
Test status
Simulation time 24035562 ps
CPU time 0.91 seconds
Started Jun 05 05:57:15 PM PDT 24
Finished Jun 05 05:57:17 PM PDT 24
Peak memory 216232 kb
Host smart-24f0f1a2-18e9-48f5-9e67-5688244fde59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248529907 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.248529907
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3316978573
Short name T38
Test name
Test status
Simulation time 81756321 ps
CPU time 1.03 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:26 PM PDT 24
Peak memory 216620 kb
Host smart-5818ba44-807f-4908-b00d-8036be12a4d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316978573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3316978573
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/51.edn_err.3143799476
Short name T88
Test name
Test status
Simulation time 30934571 ps
CPU time 1 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 223556 kb
Host smart-388ebce4-f4ee-46f1-9893-eddc9a4fc2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143799476 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.3143799476
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.3190849889
Short name T94
Test name
Test status
Simulation time 19021337 ps
CPU time 1.17 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 223512 kb
Host smart-6364e1f0-b24d-401b-8a02-1194eb2a46df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190849889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3190849889
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/189.edn_genbits.3971626695
Short name T275
Test name
Test status
Simulation time 87771942 ps
CPU time 1.17 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 219464 kb
Host smart-68255451-f515-427c-88da-7aedab96a78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971626695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3971626695
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.702597102
Short name T175
Test name
Test status
Simulation time 27464663 ps
CPU time 1.06 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 206344 kb
Host smart-40d2d5f1-7aa0-420a-9bb5-526362fde75f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702597102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.702597102
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_regwen.3630573921
Short name T255
Test name
Test status
Simulation time 19235525 ps
CPU time 1.01 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 206856 kb
Host smart-cb2edb53-8707-4bd3-b634-56d1ddea7772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630573921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3630573921
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/127.edn_genbits.361922647
Short name T284
Test name
Test status
Simulation time 47497642 ps
CPU time 1.79 seconds
Started Jun 05 05:57:58 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 217960 kb
Host smart-b4b0dc62-d655-4cf2-ba82-8fa74e139828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361922647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.361922647
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_alert.1996540740
Short name T33
Test name
Test status
Simulation time 47402337 ps
CPU time 1.16 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 215212 kb
Host smart-3c7cdd10-d925-4138-b47c-9b0324f32d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996540740 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1996540740
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/7.edn_regwen.2028012971
Short name T266
Test name
Test status
Simulation time 49741859 ps
CPU time 0.86 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 206848 kb
Host smart-458cffd2-d153-4d3f-8f6d-a59600dd23e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028012971 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2028012971
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_genbits.2082458822
Short name T286
Test name
Test status
Simulation time 61016118 ps
CPU time 1.34 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 219380 kb
Host smart-b9327dda-5a83-4254-966b-864e5fd56640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082458822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2082458822
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.729660063
Short name T18
Test name
Test status
Simulation time 31132788 ps
CPU time 1.27 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 217000 kb
Host smart-8f29a598-dcd3-49f2-9929-a7787a22dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729660063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.729660063
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.285645511
Short name T141
Test name
Test status
Simulation time 22264678 ps
CPU time 0.98 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 215500 kb
Host smart-5feaeebc-ebdf-4544-900c-ad02e085ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285645511 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.285645511
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.3448027743
Short name T72
Test name
Test status
Simulation time 85907064 ps
CPU time 1.22 seconds
Started Jun 05 05:56:41 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 215360 kb
Host smart-d10e5857-a632-4ebb-85d0-430cccf07eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448027743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3448027743
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/134.edn_genbits.3473706418
Short name T451
Test name
Test status
Simulation time 77990360 ps
CPU time 1.4 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216820 kb
Host smart-5fcb349e-abf4-4355-aec1-496d54ac2ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473706418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3473706418
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1401652475
Short name T781
Test name
Test status
Simulation time 46418085 ps
CPU time 1.48 seconds
Started Jun 05 05:58:26 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 219388 kb
Host smart-1096a510-7655-4fe8-9657-12552d38ee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401652475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1401652475
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1911983819
Short name T213
Test name
Test status
Simulation time 50537649 ps
CPU time 0.97 seconds
Started Jun 05 05:55:05 PM PDT 24
Finished Jun 05 05:55:07 PM PDT 24
Peak memory 206644 kb
Host smart-1c4e7620-0332-4b76-ad33-2eaec2a748fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911983819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1911983819
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1051770790
Short name T245
Test name
Test status
Simulation time 96941414 ps
CPU time 2.54 seconds
Started Jun 05 05:55:22 PM PDT 24
Finished Jun 05 05:55:25 PM PDT 24
Peak memory 206644 kb
Host smart-efc0dac6-dd09-4ceb-894e-8167dbae7f82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051770790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1051770790
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_regwen.62844247
Short name T107
Test name
Test status
Simulation time 16253315 ps
CPU time 0.99 seconds
Started Jun 05 05:56:39 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 206856 kb
Host smart-7e763944-74cc-42dc-925d-13128fb3780a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62844247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.62844247
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/104.edn_genbits.216675711
Short name T241
Test name
Test status
Simulation time 98399578 ps
CPU time 2.62 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 219624 kb
Host smart-0e9ac308-ecca-47a1-95d3-22b10046ce7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216675711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.216675711
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.4139378910
Short name T386
Test name
Test status
Simulation time 41898059 ps
CPU time 1.12 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:02 PM PDT 24
Peak memory 216592 kb
Host smart-b16d9f2a-3ce6-46cf-93fd-e5a5b1ad437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139378910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.4139378910
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.532877629
Short name T293
Test name
Test status
Simulation time 131252886 ps
CPU time 1.15 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 216720 kb
Host smart-91382577-0dac-4d08-8893-4a3eca0cb519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532877629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.532877629
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3907773583
Short name T259
Test name
Test status
Simulation time 25134949 ps
CPU time 1.17 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215248 kb
Host smart-98b50918-5e2d-41fa-b92f-9359afe222d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907773583 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3907773583
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/16.edn_genbits.2370491735
Short name T278
Test name
Test status
Simulation time 58487527 ps
CPU time 1.31 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 218020 kb
Host smart-af0f5b83-ab83-486c-9fbf-c5a131414727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370491735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.2370491735
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all.2881396071
Short name T616
Test name
Test status
Simulation time 269026948 ps
CPU time 5.32 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 216724 kb
Host smart-fd504d16-bf3d-4977-a7ec-d3a39b3515a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881396071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2881396071
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/162.edn_genbits.1701885007
Short name T567
Test name
Test status
Simulation time 46997440 ps
CPU time 1.28 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 217928 kb
Host smart-123fb2d9-cc9a-4d25-b580-37e754c96972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701885007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1701885007
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.4286199126
Short name T273
Test name
Test status
Simulation time 83841237 ps
CPU time 1.37 seconds
Started Jun 05 05:58:21 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 218336 kb
Host smart-c4d54cfd-7040-4e4f-af44-087064a47006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286199126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.4286199126
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/220.edn_genbits.4036259292
Short name T282
Test name
Test status
Simulation time 55899561 ps
CPU time 1.39 seconds
Started Jun 05 05:58:22 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 217948 kb
Host smart-7ece785d-61fe-4703-aaeb-907aa156d6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036259292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.4036259292
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1985829643
Short name T287
Test name
Test status
Simulation time 30823101 ps
CPU time 1.19 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 217764 kb
Host smart-c04f4c3e-bcbe-41ab-8f3c-a85ae6ee65c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985829643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1985829643
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_alert.3849136950
Short name T264
Test name
Test status
Simulation time 85741144 ps
CPU time 1.25 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215352 kb
Host smart-0c3bf070-8d4c-4f9d-b203-ec35eb169529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849136950 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3849136950
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1503841136
Short name T242
Test name
Test status
Simulation time 76295342 ps
CPU time 1.03 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 218224 kb
Host smart-0ada3276-41a9-46e3-904d-ec22ce70d5e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503841136 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1503841136
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_intr.2031482629
Short name T145
Test name
Test status
Simulation time 19806472 ps
CPU time 1.08 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215432 kb
Host smart-7b3437c8-202b-4ba3-b442-b6fb9b1dd559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031482629 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2031482629
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/11.edn_alert.881015974
Short name T256
Test name
Test status
Simulation time 22861516 ps
CPU time 1.14 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 215428 kb
Host smart-4a687821-2053-4b78-8bf1-e751d7ac242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881015974 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.881015974
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2690525318
Short name T138
Test name
Test status
Simulation time 78873885 ps
CPU time 1.07 seconds
Started Jun 05 05:57:19 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 219300 kb
Host smart-66e609d0-b9ab-4009-bfbf-9812c11f3399
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690525318 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2690525318
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1659017872
Short name T51
Test name
Test status
Simulation time 22538031 ps
CPU time 1.24 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 229268 kb
Host smart-55ae9767-6812-4033-b47d-216c1946456c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659017872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1659017872
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/271.edn_genbits.874275095
Short name T827
Test name
Test status
Simulation time 51227133 ps
CPU time 1.93 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 219552 kb
Host smart-c8b3ae56-7d2c-4056-8e53-8ac9a7ef97d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874275095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.874275095
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3104170613
Short name T235
Test name
Test status
Simulation time 27434743 ps
CPU time 1.22 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206572 kb
Host smart-b72e1408-ee76-400f-bcb8-a202bbbbc75a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104170613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3104170613
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.694365171
Short name T887
Test name
Test status
Simulation time 122117819 ps
CPU time 1.99 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 206596 kb
Host smart-752fcbe7-5c75-4fb1-9470-623c8fd11c1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694365171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.694365171
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3003847168
Short name T936
Test name
Test status
Simulation time 44367416 ps
CPU time 0.87 seconds
Started Jun 05 05:55:04 PM PDT 24
Finished Jun 05 05:55:06 PM PDT 24
Peak memory 206660 kb
Host smart-5cdf02b7-36c6-4513-bc20-1772f4f9e115
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003847168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3003847168
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3146880329
Short name T847
Test name
Test status
Simulation time 85504101 ps
CPU time 1.25 seconds
Started Jun 05 05:55:06 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 215148 kb
Host smart-339b9cd9-8518-495d-8338-30b384a9ed76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146880329 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3146880329
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1524117352
Short name T221
Test name
Test status
Simulation time 14367344 ps
CPU time 0.93 seconds
Started Jun 05 05:55:06 PM PDT 24
Finished Jun 05 05:55:08 PM PDT 24
Peak memory 206648 kb
Host smart-fae86166-3fa5-412f-a75f-9f9e7a17f011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524117352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1524117352
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1974798062
Short name T938
Test name
Test status
Simulation time 50379598 ps
CPU time 0.79 seconds
Started Jun 05 05:55:12 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206420 kb
Host smart-beaef499-f4f0-4e87-b2ef-706d444b3fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974798062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1974798062
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1748550593
Short name T894
Test name
Test status
Simulation time 92630458 ps
CPU time 1.89 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 214840 kb
Host smart-7e67c4c1-3746-4df6-bb3a-8af440d7bbdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748550593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1748550593
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1978787541
Short name T935
Test name
Test status
Simulation time 107263910 ps
CPU time 2.45 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 214884 kb
Host smart-8e9a67fa-4ddf-4dab-b940-8577470440d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978787541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1978787541
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1596780643
Short name T219
Test name
Test status
Simulation time 96057724 ps
CPU time 1.18 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206604 kb
Host smart-036c984c-3b25-4512-9d38-4098a8adddfc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596780643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1596780643
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1288822542
Short name T970
Test name
Test status
Simulation time 91869166 ps
CPU time 3.48 seconds
Started Jun 05 05:55:12 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 206700 kb
Host smart-4a1a2267-3c0c-4d4e-9d67-04c4e6b438ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288822542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1288822542
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3059811674
Short name T918
Test name
Test status
Simulation time 47821342 ps
CPU time 0.89 seconds
Started Jun 05 05:55:06 PM PDT 24
Finished Jun 05 05:55:08 PM PDT 24
Peak memory 206644 kb
Host smart-13f36ff4-0f79-4868-89a3-e01ce178296d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059811674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3059811674
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2806534817
Short name T980
Test name
Test status
Simulation time 18479137 ps
CPU time 1.1 seconds
Started Jun 05 05:55:07 PM PDT 24
Finished Jun 05 05:55:09 PM PDT 24
Peak memory 214868 kb
Host smart-37cf2a8a-d6aa-41e8-9137-3f0a3a0f41b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806534817 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2806534817
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1278123425
Short name T915
Test name
Test status
Simulation time 25314314 ps
CPU time 0.88 seconds
Started Jun 05 05:55:04 PM PDT 24
Finished Jun 05 05:55:07 PM PDT 24
Peak memory 206588 kb
Host smart-569ce55e-19c3-4f68-b55f-62f1df99ac4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278123425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1278123425
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1556068211
Short name T958
Test name
Test status
Simulation time 14322862 ps
CPU time 0.93 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 206512 kb
Host smart-cc4c9d5a-806a-4f63-89fe-b7f53bd4e4d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556068211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1556068211
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2623645585
Short name T965
Test name
Test status
Simulation time 67035691 ps
CPU time 1.3 seconds
Started Jun 05 05:55:06 PM PDT 24
Finished Jun 05 05:55:09 PM PDT 24
Peak memory 206696 kb
Host smart-182ab431-5b2d-4c81-828d-061936cf4600
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623645585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2623645585
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2825062510
Short name T977
Test name
Test status
Simulation time 44852643 ps
CPU time 2.93 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 218712 kb
Host smart-631573f6-1e27-4df6-9782-28c948d87327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825062510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2825062510
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1366149444
Short name T900
Test name
Test status
Simulation time 59175604 ps
CPU time 1.7 seconds
Started Jun 05 05:55:24 PM PDT 24
Finished Jun 05 05:55:26 PM PDT 24
Peak memory 206652 kb
Host smart-c872ec0e-4ac3-45f4-9a53-6da64519c744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366149444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1366149444
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2988408233
Short name T883
Test name
Test status
Simulation time 112695738 ps
CPU time 2.17 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:18 PM PDT 24
Peak memory 214920 kb
Host smart-1eb12b06-3efc-49cd-a2e3-9ef748a1d0e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988408233 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2988408233
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2436009357
Short name T210
Test name
Test status
Simulation time 15547946 ps
CPU time 0.96 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 206648 kb
Host smart-35bbae2e-07e0-4852-bc17-133807fa4e5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436009357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2436009357
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.788655357
Short name T880
Test name
Test status
Simulation time 35957075 ps
CPU time 0.83 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 206444 kb
Host smart-bdcd8b6d-e9f3-4f6b-b597-2a827ce93ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788655357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.788655357
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1403822213
Short name T941
Test name
Test status
Simulation time 151223482 ps
CPU time 1.25 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 206732 kb
Host smart-332465fb-0294-4fd4-8e5a-ad444d3c82c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403822213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1403822213
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2245601755
Short name T876
Test name
Test status
Simulation time 78387473 ps
CPU time 2.73 seconds
Started Jun 05 05:55:24 PM PDT 24
Finished Jun 05 05:55:27 PM PDT 24
Peak memory 214816 kb
Host smart-af8bea3d-3907-4642-a331-b9b86b7771fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245601755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2245601755
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1439375558
Short name T237
Test name
Test status
Simulation time 70948084 ps
CPU time 1.84 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:18 PM PDT 24
Peak memory 206848 kb
Host smart-5c61eeff-bcbd-4f58-aae0-e71c5c2bf9a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439375558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1439375558
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.267950621
Short name T859
Test name
Test status
Simulation time 106979549 ps
CPU time 1.42 seconds
Started Jun 05 05:55:33 PM PDT 24
Finished Jun 05 05:55:35 PM PDT 24
Peak memory 214880 kb
Host smart-d90bb766-6e40-468f-8c42-78f4990d157f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267950621 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.267950621
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2976536556
Short name T874
Test name
Test status
Simulation time 20244278 ps
CPU time 0.94 seconds
Started Jun 05 05:55:23 PM PDT 24
Finished Jun 05 05:55:24 PM PDT 24
Peak memory 206464 kb
Host smart-d90943e0-d88e-428f-9188-45efbfa8dff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976536556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2976536556
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3236558972
Short name T937
Test name
Test status
Simulation time 18963597 ps
CPU time 1.16 seconds
Started Jun 05 05:55:51 PM PDT 24
Finished Jun 05 05:55:53 PM PDT 24
Peak memory 206576 kb
Host smart-17d3adc4-bf1a-440d-957c-d8fc4925d124
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236558972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3236558972
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.303744348
Short name T853
Test name
Test status
Simulation time 228440084 ps
CPU time 2.36 seconds
Started Jun 05 05:55:26 PM PDT 24
Finished Jun 05 05:55:29 PM PDT 24
Peak memory 214944 kb
Host smart-c471763d-0a4f-461b-9a6c-b70d2ba5dc16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303744348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.303744348
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3340156711
Short name T871
Test name
Test status
Simulation time 145831093 ps
CPU time 1.58 seconds
Started Jun 05 05:55:37 PM PDT 24
Finished Jun 05 05:55:39 PM PDT 24
Peak memory 214804 kb
Host smart-75d0893e-9b23-4f2c-a91e-d6ebf8e2ec88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340156711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3340156711
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.471959170
Short name T903
Test name
Test status
Simulation time 86147921 ps
CPU time 1.27 seconds
Started Jun 05 05:55:29 PM PDT 24
Finished Jun 05 05:55:31 PM PDT 24
Peak memory 223164 kb
Host smart-d4e26df1-1522-4915-a9d6-ce5560a3e6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471959170 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.471959170
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.4055847228
Short name T217
Test name
Test status
Simulation time 21383342 ps
CPU time 0.86 seconds
Started Jun 05 05:55:33 PM PDT 24
Finished Jun 05 05:55:34 PM PDT 24
Peak memory 206804 kb
Host smart-2e995d55-aad0-4e6e-9e21-bc86fae12c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055847228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.4055847228
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1061672755
Short name T858
Test name
Test status
Simulation time 17569680 ps
CPU time 0.8 seconds
Started Jun 05 05:55:41 PM PDT 24
Finished Jun 05 05:55:43 PM PDT 24
Peak memory 206588 kb
Host smart-576a063b-e54f-45c7-8fbc-75444b83f94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061672755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1061672755
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3793012489
Short name T211
Test name
Test status
Simulation time 40705977 ps
CPU time 1.18 seconds
Started Jun 05 05:55:46 PM PDT 24
Finished Jun 05 05:55:48 PM PDT 24
Peak memory 206744 kb
Host smart-fda007b0-9271-4ee0-b477-c9bbc4663801
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793012489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3793012489
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2299106084
Short name T877
Test name
Test status
Simulation time 87389208 ps
CPU time 2.55 seconds
Started Jun 05 05:55:26 PM PDT 24
Finished Jun 05 05:55:29 PM PDT 24
Peak memory 214852 kb
Host smart-af43e0e9-53e3-4ec6-9353-9a6eb4be1493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299106084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2299106084
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3623727636
Short name T238
Test name
Test status
Simulation time 337648091 ps
CPU time 3.55 seconds
Started Jun 05 05:55:50 PM PDT 24
Finished Jun 05 05:55:54 PM PDT 24
Peak memory 206696 kb
Host smart-a3ce7b3f-5165-4aeb-90d5-d39808a5a3ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623727636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3623727636
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.267035063
Short name T925
Test name
Test status
Simulation time 373851592 ps
CPU time 1.43 seconds
Started Jun 05 05:55:22 PM PDT 24
Finished Jun 05 05:55:24 PM PDT 24
Peak memory 215188 kb
Host smart-258618e1-d54b-4eba-a29f-90d02841dec0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267035063 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.267035063
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.3507216756
Short name T234
Test name
Test status
Simulation time 28186485 ps
CPU time 0.82 seconds
Started Jun 05 05:55:30 PM PDT 24
Finished Jun 05 05:55:31 PM PDT 24
Peak memory 206536 kb
Host smart-d1ea1db0-7ace-47d0-8881-bb1c4bfe00e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507216756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.3507216756
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.587566662
Short name T852
Test name
Test status
Simulation time 28661038 ps
CPU time 0.91 seconds
Started Jun 05 05:55:25 PM PDT 24
Finished Jun 05 05:55:26 PM PDT 24
Peak memory 206356 kb
Host smart-98b12c02-cb6c-4aa9-ad9b-550fb40e07a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587566662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.587566662
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.401537281
Short name T961
Test name
Test status
Simulation time 74300460 ps
CPU time 1.04 seconds
Started Jun 05 05:55:32 PM PDT 24
Finished Jun 05 05:55:33 PM PDT 24
Peak memory 206736 kb
Host smart-d2224e87-b6bc-4e94-b34a-84a6f9f4c256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401537281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_ou
tstanding.401537281
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2282607547
Short name T891
Test name
Test status
Simulation time 46771915 ps
CPU time 1.97 seconds
Started Jun 05 05:55:50 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 214800 kb
Host smart-4da8904b-35d3-4b48-9d6b-3169f0e14392
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282607547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2282607547
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.4099393210
Short name T949
Test name
Test status
Simulation time 94925918 ps
CPU time 2.52 seconds
Started Jun 05 05:55:26 PM PDT 24
Finished Jun 05 05:55:29 PM PDT 24
Peak memory 215388 kb
Host smart-17775197-07cd-41e5-ad1e-f7c3813733e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099393210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.4099393210
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2666114763
Short name T890
Test name
Test status
Simulation time 57209581 ps
CPU time 1.06 seconds
Started Jun 05 05:55:35 PM PDT 24
Finished Jun 05 05:55:36 PM PDT 24
Peak memory 216324 kb
Host smart-06204382-8a1d-44df-9936-cbb59f8996bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666114763 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2666114763
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2234407149
Short name T966
Test name
Test status
Simulation time 11823215 ps
CPU time 0.88 seconds
Started Jun 05 05:55:29 PM PDT 24
Finished Jun 05 05:55:31 PM PDT 24
Peak memory 206584 kb
Host smart-aa8966dd-ede6-4c7d-b3e6-a51c67af5051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234407149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2234407149
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.183463015
Short name T947
Test name
Test status
Simulation time 18559338 ps
CPU time 0.87 seconds
Started Jun 05 05:55:27 PM PDT 24
Finished Jun 05 05:55:28 PM PDT 24
Peak memory 206528 kb
Host smart-e105eedb-00d4-4cc5-9d8e-0434c81b7d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183463015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.183463015
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.1702817507
Short name T225
Test name
Test status
Simulation time 85041230 ps
CPU time 1.24 seconds
Started Jun 05 05:55:22 PM PDT 24
Finished Jun 05 05:55:24 PM PDT 24
Peak memory 206640 kb
Host smart-1dd20fc0-e616-4ae4-b185-87f482a876a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702817507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.1702817507
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2421163767
Short name T945
Test name
Test status
Simulation time 32744811 ps
CPU time 1.97 seconds
Started Jun 05 05:55:27 PM PDT 24
Finished Jun 05 05:55:30 PM PDT 24
Peak memory 214912 kb
Host smart-b1a2c3ce-9244-4527-9a3b-8e0343936697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421163767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2421163767
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1368695518
Short name T868
Test name
Test status
Simulation time 117521186 ps
CPU time 1.2 seconds
Started Jun 05 05:55:40 PM PDT 24
Finished Jun 05 05:55:42 PM PDT 24
Peak memory 216436 kb
Host smart-e4338258-3c12-4baf-bdf2-b1e31c98ae0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368695518 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1368695518
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3506825592
Short name T863
Test name
Test status
Simulation time 104966473 ps
CPU time 0.81 seconds
Started Jun 05 05:55:43 PM PDT 24
Finished Jun 05 05:55:45 PM PDT 24
Peak memory 206488 kb
Host smart-1448deb5-e8f3-4d29-83cf-b8f962e6220a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506825592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3506825592
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2942954528
Short name T919
Test name
Test status
Simulation time 36058744 ps
CPU time 0.83 seconds
Started Jun 05 05:55:42 PM PDT 24
Finished Jun 05 05:55:44 PM PDT 24
Peak memory 206412 kb
Host smart-f5d97e8b-8400-48c1-a800-a649266c3ac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942954528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2942954528
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1310607118
Short name T897
Test name
Test status
Simulation time 46732861 ps
CPU time 1.02 seconds
Started Jun 05 05:55:36 PM PDT 24
Finished Jun 05 05:55:38 PM PDT 24
Peak memory 206644 kb
Host smart-bbe6e81a-78ea-478a-873d-e815397f1327
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310607118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1310607118
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2615291994
Short name T866
Test name
Test status
Simulation time 238009039 ps
CPU time 3.66 seconds
Started Jun 05 05:55:24 PM PDT 24
Finished Jun 05 05:55:28 PM PDT 24
Peak memory 214824 kb
Host smart-59d05dd8-2559-4be8-9c03-e8f586d052f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615291994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2615291994
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.596594228
Short name T978
Test name
Test status
Simulation time 21317696 ps
CPU time 1.16 seconds
Started Jun 05 05:55:50 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 214816 kb
Host smart-540464e7-f6dc-4141-871d-1bd0e9103520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596594228 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.596594228
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1831470381
Short name T212
Test name
Test status
Simulation time 22955594 ps
CPU time 0.91 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:47 PM PDT 24
Peak memory 206648 kb
Host smart-684aa087-7693-47a9-9969-f08dad5d99ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831470381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1831470381
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1408791626
Short name T906
Test name
Test status
Simulation time 42173540 ps
CPU time 0.86 seconds
Started Jun 05 05:55:44 PM PDT 24
Finished Jun 05 05:55:45 PM PDT 24
Peak memory 206500 kb
Host smart-32bed7e9-c857-4af6-8e36-77d4f99da7bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408791626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1408791626
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4168503474
Short name T929
Test name
Test status
Simulation time 26920578 ps
CPU time 1.24 seconds
Started Jun 05 05:55:39 PM PDT 24
Finished Jun 05 05:55:41 PM PDT 24
Peak memory 206640 kb
Host smart-d9bbdf7f-f60b-47a4-acb4-6986d9dd1450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168503474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4168503474
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2195105812
Short name T882
Test name
Test status
Simulation time 48658287 ps
CPU time 2.47 seconds
Started Jun 05 05:55:50 PM PDT 24
Finished Jun 05 05:55:53 PM PDT 24
Peak memory 214908 kb
Host smart-42765b2e-7705-42a9-a1dc-70ee832f7ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195105812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2195105812
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.759894537
Short name T247
Test name
Test status
Simulation time 242041914 ps
CPU time 2.05 seconds
Started Jun 05 05:55:31 PM PDT 24
Finished Jun 05 05:55:34 PM PDT 24
Peak memory 206724 kb
Host smart-40e64289-82f0-4af2-a5a5-2e5b09f2cda2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759894537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.759894537
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1794679124
Short name T968
Test name
Test status
Simulation time 39057723 ps
CPU time 1.4 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:48 PM PDT 24
Peak memory 214920 kb
Host smart-318ac1cd-17ad-4871-b04f-d8eb41e26911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794679124 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1794679124
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1538044747
Short name T946
Test name
Test status
Simulation time 57157601 ps
CPU time 0.88 seconds
Started Jun 05 05:55:43 PM PDT 24
Finished Jun 05 05:55:45 PM PDT 24
Peak memory 206524 kb
Host smart-84386e84-fc47-4d4b-9e0e-3fe2be04f64c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538044747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1538044747
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3079994697
Short name T862
Test name
Test status
Simulation time 58647668 ps
CPU time 0.86 seconds
Started Jun 05 05:55:35 PM PDT 24
Finished Jun 05 05:55:36 PM PDT 24
Peak memory 206500 kb
Host smart-0fa1bb54-5a7a-4775-a2dd-b90c4cb04114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079994697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3079994697
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.16477499
Short name T226
Test name
Test status
Simulation time 32466912 ps
CPU time 0.97 seconds
Started Jun 05 05:55:46 PM PDT 24
Finished Jun 05 05:55:48 PM PDT 24
Peak memory 206456 kb
Host smart-04e68ec8-62ef-4c9d-bf6f-5b9dd5ff4079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16477499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_out
standing.16477499
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2651902517
Short name T851
Test name
Test status
Simulation time 51140579 ps
CPU time 1.78 seconds
Started Jun 05 05:55:37 PM PDT 24
Finished Jun 05 05:55:39 PM PDT 24
Peak memory 214848 kb
Host smart-1fec326b-69d8-4814-ac40-1174c1d30f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651902517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2651902517
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3358050523
Short name T246
Test name
Test status
Simulation time 283086292 ps
CPU time 2.26 seconds
Started Jun 05 05:55:47 PM PDT 24
Finished Jun 05 05:55:50 PM PDT 24
Peak memory 206692 kb
Host smart-9d0bd97a-d6bb-487c-9d32-289f280e487d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358050523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3358050523
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3632391610
Short name T905
Test name
Test status
Simulation time 69071719 ps
CPU time 1.1 seconds
Started Jun 05 05:55:44 PM PDT 24
Finished Jun 05 05:55:46 PM PDT 24
Peak memory 216440 kb
Host smart-b2334a39-e922-4fc7-a690-316394741cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632391610 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3632391610
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3417539792
Short name T956
Test name
Test status
Simulation time 12421933 ps
CPU time 0.85 seconds
Started Jun 05 05:55:37 PM PDT 24
Finished Jun 05 05:55:39 PM PDT 24
Peak memory 206644 kb
Host smart-93bd7787-bf1b-4652-b7a0-e8052cd2d61f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417539792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3417539792
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3508180385
Short name T888
Test name
Test status
Simulation time 29272722 ps
CPU time 0.83 seconds
Started Jun 05 05:55:40 PM PDT 24
Finished Jun 05 05:55:41 PM PDT 24
Peak memory 206428 kb
Host smart-67d3e94f-5c9b-4593-a2be-6ff990254422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508180385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3508180385
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.904937385
Short name T214
Test name
Test status
Simulation time 32617095 ps
CPU time 1.2 seconds
Started Jun 05 05:55:42 PM PDT 24
Finished Jun 05 05:55:44 PM PDT 24
Peak memory 206636 kb
Host smart-a0265b3b-0d23-4f38-b14b-07fefd478342
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904937385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.904937385
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.359338780
Short name T928
Test name
Test status
Simulation time 226654197 ps
CPU time 3.64 seconds
Started Jun 05 05:55:40 PM PDT 24
Finished Jun 05 05:55:44 PM PDT 24
Peak memory 214800 kb
Host smart-49be237a-9710-4192-b671-4e90715bdd27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359338780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.359338780
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.967656986
Short name T943
Test name
Test status
Simulation time 937585520 ps
CPU time 2.32 seconds
Started Jun 05 05:55:36 PM PDT 24
Finished Jun 05 05:55:38 PM PDT 24
Peak memory 206648 kb
Host smart-b042ea20-f9dd-464c-ac2d-50ffc0f7078f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967656986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.967656986
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2712811118
Short name T924
Test name
Test status
Simulation time 19295473 ps
CPU time 1.27 seconds
Started Jun 05 05:55:41 PM PDT 24
Finished Jun 05 05:55:43 PM PDT 24
Peak memory 215012 kb
Host smart-79285aef-3365-4368-8d02-baa2c4f93924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712811118 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2712811118
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1154508823
Short name T878
Test name
Test status
Simulation time 30043863 ps
CPU time 0.93 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:47 PM PDT 24
Peak memory 206632 kb
Host smart-cebe0868-7a5e-41fb-857e-e872dcab23d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154508823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1154508823
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3976005256
Short name T907
Test name
Test status
Simulation time 15307820 ps
CPU time 1 seconds
Started Jun 05 05:55:46 PM PDT 24
Finished Jun 05 05:55:48 PM PDT 24
Peak memory 206396 kb
Host smart-d786e7e8-c1ea-4fc0-a46c-824a56836248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976005256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3976005256
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.962222623
Short name T916
Test name
Test status
Simulation time 50120583 ps
CPU time 1.14 seconds
Started Jun 05 05:55:40 PM PDT 24
Finished Jun 05 05:55:42 PM PDT 24
Peak memory 206652 kb
Host smart-0a2ee875-b27f-4bc6-99d8-3715047fd6a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962222623 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.962222623
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.4254879721
Short name T873
Test name
Test status
Simulation time 283070954 ps
CPU time 2.89 seconds
Started Jun 05 05:55:32 PM PDT 24
Finished Jun 05 05:55:35 PM PDT 24
Peak memory 214860 kb
Host smart-ed3edd83-75ef-42b2-aa07-ca51e23915ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254879721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.4254879721
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.651676631
Short name T889
Test name
Test status
Simulation time 197857355 ps
CPU time 2.42 seconds
Started Jun 05 05:55:34 PM PDT 24
Finished Jun 05 05:55:36 PM PDT 24
Peak memory 206932 kb
Host smart-96573c65-8931-45a1-8399-2d00755430ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651676631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.651676631
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.918667614
Short name T857
Test name
Test status
Simulation time 80056704 ps
CPU time 1.1 seconds
Started Jun 05 05:55:04 PM PDT 24
Finished Jun 05 05:55:07 PM PDT 24
Peak memory 206736 kb
Host smart-02e0bf13-28ea-47a5-b786-15a62eed32ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918667614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.918667614
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1320916140
Short name T942
Test name
Test status
Simulation time 140990064 ps
CPU time 2.71 seconds
Started Jun 05 05:55:07 PM PDT 24
Finished Jun 05 05:55:10 PM PDT 24
Peak memory 206660 kb
Host smart-61b0347c-3062-42fb-8806-d04928e28c76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320916140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1320916140
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2231787869
Short name T964
Test name
Test status
Simulation time 56014968 ps
CPU time 0.95 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 206644 kb
Host smart-7b7992be-bad4-40a0-b77f-f867ac8117f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231787869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2231787869
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3783048954
Short name T923
Test name
Test status
Simulation time 30739179 ps
CPU time 1.35 seconds
Started Jun 05 05:55:14 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 214872 kb
Host smart-a74ed4e3-5f50-4c9b-be4d-351c9e859a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783048954 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3783048954
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.432926326
Short name T223
Test name
Test status
Simulation time 47355540 ps
CPU time 0.9 seconds
Started Jun 05 05:55:13 PM PDT 24
Finished Jun 05 05:55:15 PM PDT 24
Peak memory 206592 kb
Host smart-1f6cdd59-ad5f-4021-a390-d3693995ebea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432926326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.432926326
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1849796569
Short name T879
Test name
Test status
Simulation time 34807871 ps
CPU time 0.8 seconds
Started Jun 05 05:55:12 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206408 kb
Host smart-28d26919-1b0d-46df-8d89-e80c94a8c093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849796569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1849796569
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2034867362
Short name T207
Test name
Test status
Simulation time 51118749 ps
CPU time 1.09 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206704 kb
Host smart-bab8d485-6356-4925-889e-0bad953a3e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034867362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2034867362
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1916219189
Short name T850
Test name
Test status
Simulation time 551442551 ps
CPU time 3.56 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 214844 kb
Host smart-1b72ba01-6659-438b-8772-fc59ef85c604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916219189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1916219189
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.712570264
Short name T867
Test name
Test status
Simulation time 78482796 ps
CPU time 2.32 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:11 PM PDT 24
Peak memory 206828 kb
Host smart-dcb997f4-28e1-4d7f-9c65-1df9d5fb36bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712570264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.712570264
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.984250458
Short name T957
Test name
Test status
Simulation time 13580969 ps
CPU time 0.84 seconds
Started Jun 05 05:55:52 PM PDT 24
Finished Jun 05 05:55:53 PM PDT 24
Peak memory 206464 kb
Host smart-9b56c756-3047-4311-9df8-ea0dd449eedd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984250458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.984250458
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1061247775
Short name T917
Test name
Test status
Simulation time 40993730 ps
CPU time 0.84 seconds
Started Jun 05 05:55:57 PM PDT 24
Finished Jun 05 05:55:59 PM PDT 24
Peak memory 206616 kb
Host smart-5e4ad432-c558-4d69-a03c-13fde6689187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061247775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1061247775
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3295006069
Short name T969
Test name
Test status
Simulation time 87551786 ps
CPU time 0.84 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:47 PM PDT 24
Peak memory 206428 kb
Host smart-b0322893-206e-4832-a861-74798aaf857a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295006069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3295006069
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2172896256
Short name T861
Test name
Test status
Simulation time 23719776 ps
CPU time 0.86 seconds
Started Jun 05 05:55:46 PM PDT 24
Finished Jun 05 05:55:48 PM PDT 24
Peak memory 206520 kb
Host smart-f16473e9-b0af-48a3-86ba-6590322368c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172896256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2172896256
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4244264424
Short name T920
Test name
Test status
Simulation time 55993040 ps
CPU time 0.89 seconds
Started Jun 05 05:55:47 PM PDT 24
Finished Jun 05 05:55:49 PM PDT 24
Peak memory 206532 kb
Host smart-3c63c782-b2d7-4162-8a4d-cc2d5b58879d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244264424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4244264424
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1103477544
Short name T904
Test name
Test status
Simulation time 79869391 ps
CPU time 0.78 seconds
Started Jun 05 05:55:55 PM PDT 24
Finished Jun 05 05:55:57 PM PDT 24
Peak memory 206384 kb
Host smart-dfaf8246-6ec2-4b83-b52b-c3b7912b15fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103477544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1103477544
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3787806219
Short name T934
Test name
Test status
Simulation time 29238921 ps
CPU time 0.89 seconds
Started Jun 05 05:55:44 PM PDT 24
Finished Jun 05 05:55:45 PM PDT 24
Peak memory 206612 kb
Host smart-1c14f269-ae0a-480f-86e0-2217bafce78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787806219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3787806219
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3821900068
Short name T914
Test name
Test status
Simulation time 59534068 ps
CPU time 0.81 seconds
Started Jun 05 05:55:51 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 206440 kb
Host smart-38f5735d-3b82-4287-bc43-857d1c047c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821900068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3821900068
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3933450603
Short name T901
Test name
Test status
Simulation time 47084922 ps
CPU time 0.83 seconds
Started Jun 05 05:55:59 PM PDT 24
Finished Jun 05 05:56:01 PM PDT 24
Peak memory 206516 kb
Host smart-a874934d-87aa-4cc6-8180-97eb4be77803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933450603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3933450603
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1197612753
Short name T960
Test name
Test status
Simulation time 12487060 ps
CPU time 0.85 seconds
Started Jun 05 05:55:50 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 206532 kb
Host smart-bfb126e6-4a91-458e-b340-646bdaab75d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197612753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1197612753
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.1955275867
Short name T971
Test name
Test status
Simulation time 84949011 ps
CPU time 1.1 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206528 kb
Host smart-ec6c283b-3996-4d1e-b149-9417e3f3b766
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955275867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.1955275867
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1323998374
Short name T864
Test name
Test status
Simulation time 373795982 ps
CPU time 2.99 seconds
Started Jun 05 05:55:04 PM PDT 24
Finished Jun 05 05:55:08 PM PDT 24
Peak memory 206904 kb
Host smart-62af6ba3-d9b7-4632-8287-877002feee0f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323998374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1323998374
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1804744866
Short name T220
Test name
Test status
Simulation time 46969328 ps
CPU time 0.91 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206648 kb
Host smart-97a087fb-4405-489b-9a2c-a8d949004e05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804744866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1804744866
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1555009638
Short name T979
Test name
Test status
Simulation time 32788905 ps
CPU time 1.23 seconds
Started Jun 05 05:55:03 PM PDT 24
Finished Jun 05 05:55:05 PM PDT 24
Peak memory 214816 kb
Host smart-e6bb1767-2040-4b90-ad92-081564943313
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555009638 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1555009638
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.572659814
Short name T854
Test name
Test status
Simulation time 81383882 ps
CPU time 0.85 seconds
Started Jun 05 05:55:13 PM PDT 24
Finished Jun 05 05:55:15 PM PDT 24
Peak memory 206572 kb
Host smart-dc974a76-822c-41b2-921e-563b50b56fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572659814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.572659814
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.4231998952
Short name T963
Test name
Test status
Simulation time 52323178 ps
CPU time 0.88 seconds
Started Jun 05 05:55:13 PM PDT 24
Finished Jun 05 05:55:15 PM PDT 24
Peak memory 206512 kb
Host smart-081f7aad-790f-40fe-92cd-1f735b31ced8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231998952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.4231998952
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3555750990
Short name T951
Test name
Test status
Simulation time 31220480 ps
CPU time 1.37 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:10 PM PDT 24
Peak memory 206640 kb
Host smart-9ff0e506-0175-4411-a0ac-ab0df149b10e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555750990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3555750990
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.454650234
Short name T855
Test name
Test status
Simulation time 74576211 ps
CPU time 2.73 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 214924 kb
Host smart-1c7639c9-543e-4635-b432-ff4e608819a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454650234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.454650234
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3653082303
Short name T927
Test name
Test status
Simulation time 736476001 ps
CPU time 2.28 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:18 PM PDT 24
Peak memory 214780 kb
Host smart-0999d10c-cdfc-4171-969f-c12778dc5a2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653082303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3653082303
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1863248708
Short name T913
Test name
Test status
Simulation time 28820016 ps
CPU time 0.89 seconds
Started Jun 05 05:55:56 PM PDT 24
Finished Jun 05 05:55:58 PM PDT 24
Peak memory 206604 kb
Host smart-c7fa9b66-ec23-406a-b848-dd9fddd37a62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863248708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1863248708
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4212432394
Short name T910
Test name
Test status
Simulation time 14329093 ps
CPU time 0.88 seconds
Started Jun 05 05:55:47 PM PDT 24
Finished Jun 05 05:55:49 PM PDT 24
Peak memory 206520 kb
Host smart-f8a73729-11c1-4dc3-b539-221813131017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212432394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4212432394
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.392662511
Short name T902
Test name
Test status
Simulation time 14407509 ps
CPU time 0.88 seconds
Started Jun 05 05:55:54 PM PDT 24
Finished Jun 05 05:55:56 PM PDT 24
Peak memory 206512 kb
Host smart-38f87a35-237e-4481-8803-c5b7ade0a44f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392662511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.392662511
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3213091773
Short name T952
Test name
Test status
Simulation time 22554761 ps
CPU time 0.87 seconds
Started Jun 05 05:55:55 PM PDT 24
Finished Jun 05 05:55:57 PM PDT 24
Peak memory 206520 kb
Host smart-cb332a96-f2df-4f0b-a9b8-73dba6438d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213091773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3213091773
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3699118354
Short name T872
Test name
Test status
Simulation time 17058812 ps
CPU time 0.96 seconds
Started Jun 05 05:55:52 PM PDT 24
Finished Jun 05 05:55:54 PM PDT 24
Peak memory 206516 kb
Host smart-0174f6c8-24e5-49e0-be10-d58a36091cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699118354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3699118354
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.711164790
Short name T955
Test name
Test status
Simulation time 30971810 ps
CPU time 0.88 seconds
Started Jun 05 05:55:41 PM PDT 24
Finished Jun 05 05:55:42 PM PDT 24
Peak memory 206456 kb
Host smart-3094e581-af7c-4bc9-aff9-1a0b25b47cf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711164790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.711164790
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.823701799
Short name T884
Test name
Test status
Simulation time 17015205 ps
CPU time 0.94 seconds
Started Jun 05 05:55:40 PM PDT 24
Finished Jun 05 05:55:41 PM PDT 24
Peak memory 206516 kb
Host smart-78e2e59d-9c05-4d69-bd17-4a89c62426e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823701799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.823701799
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.315652528
Short name T922
Test name
Test status
Simulation time 14630697 ps
CPU time 0.88 seconds
Started Jun 05 05:55:51 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 206500 kb
Host smart-ea2a6a5e-bfda-496c-b40b-ba9e44ab99e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315652528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.315652528
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1648549577
Short name T886
Test name
Test status
Simulation time 15172561 ps
CPU time 0.9 seconds
Started Jun 05 05:55:41 PM PDT 24
Finished Jun 05 05:55:43 PM PDT 24
Peak memory 206464 kb
Host smart-b232a389-d3be-4529-88ed-1edd659f5d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648549577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1648549577
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3245610105
Short name T909
Test name
Test status
Simulation time 51722633 ps
CPU time 0.84 seconds
Started Jun 05 05:55:48 PM PDT 24
Finished Jun 05 05:55:50 PM PDT 24
Peak memory 206384 kb
Host smart-4e2a608f-bf36-401c-9931-0b5655d7e6d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245610105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3245610105
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1582576159
Short name T209
Test name
Test status
Simulation time 24689746 ps
CPU time 1.19 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206644 kb
Host smart-a331d3bc-fef4-4cff-bcd0-697056c40b26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582576159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1582576159
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.389469917
Short name T948
Test name
Test status
Simulation time 109796476 ps
CPU time 3.1 seconds
Started Jun 05 05:55:06 PM PDT 24
Finished Jun 05 05:55:10 PM PDT 24
Peak memory 206836 kb
Host smart-83a4875f-f4db-44c7-a205-25d353803341
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389469917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.389469917
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3843434115
Short name T972
Test name
Test status
Simulation time 58860212 ps
CPU time 0.95 seconds
Started Jun 05 05:55:12 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206632 kb
Host smart-785931d7-db37-4462-936a-9c2a6b5cbcfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843434115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3843434115
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2860071983
Short name T932
Test name
Test status
Simulation time 38430853 ps
CPU time 1.52 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 214952 kb
Host smart-72b965c8-837a-40ea-97ae-b9df245670f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860071983 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2860071983
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1159401852
Short name T218
Test name
Test status
Simulation time 16711470 ps
CPU time 0.85 seconds
Started Jun 05 05:55:03 PM PDT 24
Finished Jun 05 05:55:06 PM PDT 24
Peak memory 206656 kb
Host smart-23283701-c637-47db-997c-5711e4903e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159401852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1159401852
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2237806906
Short name T944
Test name
Test status
Simulation time 12691467 ps
CPU time 0.88 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:10 PM PDT 24
Peak memory 206520 kb
Host smart-ec373732-0df6-4e9c-a4de-5b03f13278cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237806906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2237806906
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3948841385
Short name T975
Test name
Test status
Simulation time 25407336 ps
CPU time 1.15 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206600 kb
Host smart-9c482b1c-b1ff-481a-b98a-7b40804c34df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948841385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3948841385
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2597334313
Short name T931
Test name
Test status
Simulation time 35917086 ps
CPU time 2.46 seconds
Started Jun 05 05:55:12 PM PDT 24
Finished Jun 05 05:55:16 PM PDT 24
Peak memory 214948 kb
Host smart-951c84ca-55a7-4c3f-994a-29a740ba8488
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597334313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2597334313
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.372737627
Short name T243
Test name
Test status
Simulation time 66051910 ps
CPU time 1.86 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 206656 kb
Host smart-12ae36a4-094c-45d7-9460-b02866edd800
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372737627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.372737627
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.135069414
Short name T976
Test name
Test status
Simulation time 15098174 ps
CPU time 0.86 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:47 PM PDT 24
Peak memory 206536 kb
Host smart-dbf62781-6ae9-4c8b-b4d4-096cb08a8dab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135069414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.135069414
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2443516678
Short name T962
Test name
Test status
Simulation time 14559896 ps
CPU time 0.87 seconds
Started Jun 05 05:55:55 PM PDT 24
Finished Jun 05 05:55:56 PM PDT 24
Peak memory 206520 kb
Host smart-e0768f8a-307d-4367-b7a2-73db5ac8da3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443516678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2443516678
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.545122584
Short name T930
Test name
Test status
Simulation time 13611001 ps
CPU time 0.86 seconds
Started Jun 05 05:55:51 PM PDT 24
Finished Jun 05 05:55:53 PM PDT 24
Peak memory 206456 kb
Host smart-5b70b457-c5c7-4344-ba13-102e86109395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545122584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.545122584
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1978369576
Short name T899
Test name
Test status
Simulation time 39196526 ps
CPU time 0.8 seconds
Started Jun 05 05:55:47 PM PDT 24
Finished Jun 05 05:55:49 PM PDT 24
Peak memory 206520 kb
Host smart-2bfc77bc-ab3a-44a1-9d9f-3759746a14f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978369576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1978369576
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1145430849
Short name T939
Test name
Test status
Simulation time 15649506 ps
CPU time 0.9 seconds
Started Jun 05 05:55:41 PM PDT 24
Finished Jun 05 05:55:43 PM PDT 24
Peak memory 206524 kb
Host smart-25e788b6-3733-4409-96a8-10fd1f94e95b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145430849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1145430849
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2308368844
Short name T885
Test name
Test status
Simulation time 19195943 ps
CPU time 0.88 seconds
Started Jun 05 05:55:42 PM PDT 24
Finished Jun 05 05:55:44 PM PDT 24
Peak memory 206524 kb
Host smart-3979e0da-112c-42b9-980b-e0997ddf61ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308368844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2308368844
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3430296055
Short name T895
Test name
Test status
Simulation time 22097792 ps
CPU time 0.84 seconds
Started Jun 05 05:55:54 PM PDT 24
Finished Jun 05 05:56:02 PM PDT 24
Peak memory 206688 kb
Host smart-f7ea09e7-ce7c-4f56-abe1-ee86213dfc3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430296055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3430296055
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.285766474
Short name T933
Test name
Test status
Simulation time 26305999 ps
CPU time 0.87 seconds
Started Jun 05 05:55:43 PM PDT 24
Finished Jun 05 05:55:45 PM PDT 24
Peak memory 206520 kb
Host smart-b685f4d2-5739-4e83-9328-296e199f13b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285766474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.285766474
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2513936170
Short name T953
Test name
Test status
Simulation time 34605745 ps
CPU time 0.81 seconds
Started Jun 05 05:55:45 PM PDT 24
Finished Jun 05 05:55:47 PM PDT 24
Peak memory 206392 kb
Host smart-c9299329-be78-4655-a886-84019b74722a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513936170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2513936170
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.444584552
Short name T848
Test name
Test status
Simulation time 19394718 ps
CPU time 0.82 seconds
Started Jun 05 05:55:51 PM PDT 24
Finished Jun 05 05:55:52 PM PDT 24
Peak memory 206432 kb
Host smart-6b4bcc39-b0f8-46f8-8d35-d4de5219ccc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444584552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.444584552
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2780112287
Short name T875
Test name
Test status
Simulation time 21041793 ps
CPU time 1.37 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 214892 kb
Host smart-98134400-24cb-4986-94fa-0f2e167fd77a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780112287 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2780112287
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2786816432
Short name T208
Test name
Test status
Simulation time 12833767 ps
CPU time 0.86 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206668 kb
Host smart-9e448829-1871-4bc7-9076-5c1ca8ca3ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786816432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2786816432
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1610007317
Short name T967
Test name
Test status
Simulation time 33355389 ps
CPU time 0.82 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206460 kb
Host smart-4c27144f-6eb9-4746-8e22-9b74c628f159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610007317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1610007317
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1550080124
Short name T973
Test name
Test status
Simulation time 42616094 ps
CPU time 1.13 seconds
Started Jun 05 05:55:24 PM PDT 24
Finished Jun 05 05:55:25 PM PDT 24
Peak memory 206644 kb
Host smart-dff4a929-4ebc-4c27-ae2b-10e2219d51a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550080124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1550080124
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4008971096
Short name T881
Test name
Test status
Simulation time 22375669 ps
CPU time 1.47 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 214852 kb
Host smart-b23664da-c8ff-46c0-a935-1c18b474f55f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008971096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4008971096
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3126156598
Short name T236
Test name
Test status
Simulation time 102409019 ps
CPU time 2.76 seconds
Started Jun 05 05:55:05 PM PDT 24
Finished Jun 05 05:55:09 PM PDT 24
Peak memory 206652 kb
Host smart-51070661-eacd-4bf4-aec9-1541a680212f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126156598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3126156598
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2942722834
Short name T860
Test name
Test status
Simulation time 32019426 ps
CPU time 1.17 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 216752 kb
Host smart-a54f5d3d-d726-4192-88fc-fc00dbcce721
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942722834 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2942722834
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2964656420
Short name T892
Test name
Test status
Simulation time 22916173 ps
CPU time 0.84 seconds
Started Jun 05 05:55:16 PM PDT 24
Finished Jun 05 05:55:18 PM PDT 24
Peak memory 206580 kb
Host smart-97a73757-55b5-4901-9078-05f390b2e5f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964656420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2964656420
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1128186167
Short name T869
Test name
Test status
Simulation time 23699133 ps
CPU time 0.87 seconds
Started Jun 05 05:55:32 PM PDT 24
Finished Jun 05 05:55:34 PM PDT 24
Peak memory 206452 kb
Host smart-1b733f86-aaeb-4758-959b-f6063517993d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128186167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1128186167
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2870837420
Short name T206
Test name
Test status
Simulation time 40561588 ps
CPU time 1.49 seconds
Started Jun 05 05:55:17 PM PDT 24
Finished Jun 05 05:55:20 PM PDT 24
Peak memory 206644 kb
Host smart-d2e8d0f4-2342-4500-aa77-4ac4a0f3c900
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870837420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2870837420
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3769704043
Short name T950
Test name
Test status
Simulation time 309571513 ps
CPU time 2.42 seconds
Started Jun 05 05:55:19 PM PDT 24
Finished Jun 05 05:55:22 PM PDT 24
Peak memory 214844 kb
Host smart-54a2469b-92b9-445d-9956-b6ceb2cc4fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769704043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3769704043
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3546056410
Short name T908
Test name
Test status
Simulation time 58311726 ps
CPU time 1.75 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206652 kb
Host smart-635215a6-e871-4d03-b122-f4436fd05d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546056410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3546056410
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.933623585
Short name T974
Test name
Test status
Simulation time 30029185 ps
CPU time 1.39 seconds
Started Jun 05 05:55:37 PM PDT 24
Finished Jun 05 05:55:39 PM PDT 24
Peak memory 214932 kb
Host smart-e717e93a-7f35-49cf-b7ac-3c22e0c103cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933623585 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.933623585
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2672433296
Short name T856
Test name
Test status
Simulation time 98813926 ps
CPU time 0.86 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 206508 kb
Host smart-7864b21d-c47a-4bdc-a040-2d9f9e67380e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672433296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2672433296
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1401461537
Short name T865
Test name
Test status
Simulation time 23275885 ps
CPU time 0.85 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206532 kb
Host smart-ba4cf2c2-d514-4386-b500-86666bdc63db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401461537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1401461537
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.880523336
Short name T224
Test name
Test status
Simulation time 95828786 ps
CPU time 1.21 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:17 PM PDT 24
Peak memory 206640 kb
Host smart-2c4e5dee-9776-4d37-8ee0-083b6244d51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880523336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.880523336
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2466851872
Short name T898
Test name
Test status
Simulation time 123771985 ps
CPU time 1.53 seconds
Started Jun 05 05:55:32 PM PDT 24
Finished Jun 05 05:55:34 PM PDT 24
Peak memory 214884 kb
Host smart-0591d160-9e67-4429-9614-0197e847c864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466851872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2466851872
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1091098404
Short name T921
Test name
Test status
Simulation time 148428801 ps
CPU time 1.43 seconds
Started Jun 05 05:55:15 PM PDT 24
Finished Jun 05 05:55:18 PM PDT 24
Peak memory 206744 kb
Host smart-2ac18e58-8cc0-4fe6-befe-a67f158cec34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091098404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1091098404
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1258289523
Short name T849
Test name
Test status
Simulation time 77535236 ps
CPU time 1.15 seconds
Started Jun 05 05:55:11 PM PDT 24
Finished Jun 05 05:55:14 PM PDT 24
Peak memory 216476 kb
Host smart-ce36bb83-51a2-4416-a835-97a20bad47d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258289523 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1258289523
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.760117039
Short name T911
Test name
Test status
Simulation time 39938791 ps
CPU time 0.89 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206532 kb
Host smart-a2651354-abef-4d7f-b6bf-74817bbf0d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760117039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.760117039
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2520503618
Short name T870
Test name
Test status
Simulation time 12863681 ps
CPU time 0.95 seconds
Started Jun 05 05:55:27 PM PDT 24
Finished Jun 05 05:55:29 PM PDT 24
Peak memory 206512 kb
Host smart-707f7357-717d-4343-8bfe-920f936f05aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520503618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2520503618
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1572635820
Short name T222
Test name
Test status
Simulation time 34452853 ps
CPU time 1.48 seconds
Started Jun 05 05:55:25 PM PDT 24
Finished Jun 05 05:55:27 PM PDT 24
Peak memory 206692 kb
Host smart-8baf8952-688d-4225-9071-ee9cd4b0e581
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572635820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1572635820
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.902492447
Short name T912
Test name
Test status
Simulation time 69323757 ps
CPU time 2.55 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:15 PM PDT 24
Peak memory 218572 kb
Host smart-067a0026-1316-404c-aa1e-fd371a33c542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902492447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.902492447
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2788877449
Short name T954
Test name
Test status
Simulation time 71298863 ps
CPU time 2.13 seconds
Started Jun 05 05:55:17 PM PDT 24
Finished Jun 05 05:55:20 PM PDT 24
Peak memory 206844 kb
Host smart-de34bba2-368d-4e09-ae87-1cd8969f7ca1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788877449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2788877449
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.350365844
Short name T959
Test name
Test status
Simulation time 66572397 ps
CPU time 1.07 seconds
Started Jun 05 05:55:09 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 223012 kb
Host smart-c0d2af77-592b-49c7-a088-d3832ccf111b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350365844 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.350365844
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3763914379
Short name T216
Test name
Test status
Simulation time 51331678 ps
CPU time 0.89 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:12 PM PDT 24
Peak memory 206644 kb
Host smart-70d910df-dbb9-451c-953b-1eeb0501e42a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763914379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3763914379
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1946656774
Short name T926
Test name
Test status
Simulation time 17001239 ps
CPU time 0.84 seconds
Started Jun 05 05:55:20 PM PDT 24
Finished Jun 05 05:55:22 PM PDT 24
Peak memory 206536 kb
Host smart-e4e06262-2473-4a68-a197-cddb29663313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946656774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1946656774
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.861229462
Short name T940
Test name
Test status
Simulation time 49568806 ps
CPU time 1.45 seconds
Started Jun 05 05:55:10 PM PDT 24
Finished Jun 05 05:55:13 PM PDT 24
Peak memory 206644 kb
Host smart-1924d93e-0258-4e32-af95-292ca62000b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861229462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.861229462
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2786033185
Short name T896
Test name
Test status
Simulation time 193415589 ps
CPU time 3.16 seconds
Started Jun 05 05:55:30 PM PDT 24
Finished Jun 05 05:55:34 PM PDT 24
Peak memory 214920 kb
Host smart-52c568d7-93cb-4c5c-8472-c58e1febe782
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786033185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2786033185
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3029500306
Short name T244
Test name
Test status
Simulation time 168538333 ps
CPU time 2.37 seconds
Started Jun 05 05:55:08 PM PDT 24
Finished Jun 05 05:55:11 PM PDT 24
Peak memory 206644 kb
Host smart-178c7302-9d2a-4a94-ae2e-17a4accb2310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029500306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3029500306
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2967438636
Short name T812
Test name
Test status
Simulation time 27279636 ps
CPU time 1.24 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 215464 kb
Host smart-76031814-46a5-49dd-aa3e-8e9e05fc97a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967438636 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2967438636
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2935420808
Short name T631
Test name
Test status
Simulation time 61065239 ps
CPU time 0.8 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:39 PM PDT 24
Peak memory 206208 kb
Host smart-4772faac-47df-4dec-b7ff-7734e1b928d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935420808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2935420808
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2652318603
Short name T823
Test name
Test status
Simulation time 12375753 ps
CPU time 0.91 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215896 kb
Host smart-bf3be2fe-2a9d-472d-8422-79e41511e3d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652318603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2652318603
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2343603417
Short name T412
Test name
Test status
Simulation time 134482352 ps
CPU time 1 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 217980 kb
Host smart-721122fe-c175-432c-a208-7d6ea6a0f2b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343603417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2343603417
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.1965297030
Short name T53
Test name
Test status
Simulation time 30599513 ps
CPU time 1.15 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 229316 kb
Host smart-876c9c1c-feb8-4ed9-9777-26e0b5ca620b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965297030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.1965297030
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1677940914
Short name T390
Test name
Test status
Simulation time 50347962 ps
CPU time 1.77 seconds
Started Jun 05 05:56:34 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 217788 kb
Host smart-2c0df0c3-1f93-41f7-af89-e01f88f57f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677940914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1677940914
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_smoke.541567861
Short name T791
Test name
Test status
Simulation time 48513996 ps
CPU time 0.91 seconds
Started Jun 05 05:56:41 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 215036 kb
Host smart-5024be7f-744e-4d04-8166-cbd86d6b6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541567861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.541567861
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.4021957226
Short name T335
Test name
Test status
Simulation time 464504419 ps
CPU time 5.24 seconds
Started Jun 05 05:56:46 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 216804 kb
Host smart-57e1285a-06fe-446b-9ac0-27b387411b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021957226 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.4021957226
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3658598236
Short name T569
Test name
Test status
Simulation time 66477850009 ps
CPU time 1592.43 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 06:23:05 PM PDT 24
Peak memory 225196 kb
Host smart-6cead287-a1c3-45d8-9c21-2c37f2d02a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658598236 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3658598236
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.396013133
Short name T649
Test name
Test status
Simulation time 28537444 ps
CPU time 0.9 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 206352 kb
Host smart-54231799-d13b-4293-9e21-ff6094cf4678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396013133 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.396013133
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1555399036
Short name T720
Test name
Test status
Simulation time 31724569 ps
CPU time 0.85 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 05:56:34 PM PDT 24
Peak memory 216072 kb
Host smart-ab9259b6-80e5-4433-b125-8d7ff7a15438
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555399036 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1555399036
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_genbits.3158959464
Short name T126
Test name
Test status
Simulation time 66760212 ps
CPU time 2.55 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 219132 kb
Host smart-a7b08bad-b08a-4130-b696-738e43b04d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158959464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3158959464
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2291856835
Short name T686
Test name
Test status
Simulation time 27994556 ps
CPU time 0.96 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215352 kb
Host smart-23022124-276c-4630-83b2-d49c6c068a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291856835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2291856835
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_smoke.1487313309
Short name T314
Test name
Test status
Simulation time 159741508 ps
CPU time 0.9 seconds
Started Jun 05 05:56:36 PM PDT 24
Finished Jun 05 05:56:38 PM PDT 24
Peak memory 215036 kb
Host smart-bbeddd0b-15d3-4fa7-a088-ebee43d7c2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487313309 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1487313309
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1756765453
Short name T381
Test name
Test status
Simulation time 1024875910 ps
CPU time 3.76 seconds
Started Jun 05 05:56:37 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 216512 kb
Host smart-afc092f7-a5e1-42b1-b19b-b266df8e3590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756765453 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1756765453
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.149779517
Short name T124
Test name
Test status
Simulation time 23078596055 ps
CPU time 334.55 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 06:02:07 PM PDT 24
Peak memory 216352 kb
Host smart-f7e3ffd9-17d2-416e-ad71-9ba470c2ce97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149779517 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.149779517
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.783998231
Short name T785
Test name
Test status
Simulation time 15604818 ps
CPU time 0.94 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 214556 kb
Host smart-9261bbb7-0101-4deb-a11c-17599e966a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783998231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.783998231
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1315773192
Short name T63
Test name
Test status
Simulation time 58316624 ps
CPU time 0.95 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 215248 kb
Host smart-1e1a9b39-befc-47fc-91c0-c003e14c7d48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315773192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1315773192
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2647268821
Short name T233
Test name
Test status
Simulation time 53676290 ps
CPU time 1.07 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 217908 kb
Host smart-fc12356f-30b0-4760-9a7f-351eafc4e41d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647268821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2647268821
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3990214015
Short name T44
Test name
Test status
Simulation time 91999143 ps
CPU time 0.95 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 219268 kb
Host smart-ed876d01-d8a2-4b01-8100-f196ab9f9a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990214015 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3990214015
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.824804530
Short name T291
Test name
Test status
Simulation time 60527767 ps
CPU time 2.01 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 218268 kb
Host smart-55e8c567-4e4b-402d-9d5d-b7cbf1d57c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824804530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.824804530
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.440603941
Short name T316
Test name
Test status
Simulation time 27987974 ps
CPU time 0.97 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 215112 kb
Host smart-37407297-f469-4c63-b3ad-6eb5fd72d89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440603941 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.440603941
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3645710943
Short name T624
Test name
Test status
Simulation time 18146909 ps
CPU time 1.04 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215084 kb
Host smart-ed5c8404-7b34-430d-a74b-c2de87417dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645710943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3645710943
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2695013862
Short name T596
Test name
Test status
Simulation time 273050819 ps
CPU time 5.61 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 217940 kb
Host smart-ee079074-58ef-49de-8c5f-eef6a5ee4e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695013862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2695013862
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3192230249
Short name T102
Test name
Test status
Simulation time 25305526022 ps
CPU time 628.9 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 06:07:21 PM PDT 24
Peak memory 217676 kb
Host smart-db12108c-5f13-4c9b-b946-f8b9670d08d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192230249 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3192230249
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1669777358
Short name T639
Test name
Test status
Simulation time 63797179 ps
CPU time 1.24 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 216636 kb
Host smart-fc3f17da-af55-4c65-82b7-d113fabb5843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669777358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1669777358
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.999424763
Short name T632
Test name
Test status
Simulation time 71495649 ps
CPU time 1.31 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:57 PM PDT 24
Peak memory 218000 kb
Host smart-f843db5a-13b4-4362-8b69-469306d30a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999424763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.999424763
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1325347538
Short name T353
Test name
Test status
Simulation time 71186034 ps
CPU time 1.18 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 219504 kb
Host smart-58e5c097-8d77-45f8-baa4-e10b85dce081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325347538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1325347538
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2145163669
Short name T134
Test name
Test status
Simulation time 50412870 ps
CPU time 1.55 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218520 kb
Host smart-afd98495-01ed-4e61-8276-ca5ce9d03997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145163669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2145163669
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.844798571
Short name T452
Test name
Test status
Simulation time 41118775 ps
CPU time 1.68 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 216812 kb
Host smart-6e5b18ba-a0d9-4c81-91ce-d1cb5def9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844798571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.844798571
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.839936397
Short name T229
Test name
Test status
Simulation time 52481633 ps
CPU time 1.28 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216660 kb
Host smart-4163a4b5-0d61-4549-bf2a-9e61fe660f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839936397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.839936397
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.4216096780
Short name T443
Test name
Test status
Simulation time 53373768 ps
CPU time 1.73 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 217944 kb
Host smart-6eea9c44-2f4e-45cc-bba2-61319716365f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216096780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.4216096780
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1627328744
Short name T127
Test name
Test status
Simulation time 44305731 ps
CPU time 1.51 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 216708 kb
Host smart-0cbf3f7c-d8c0-49c9-a4df-fee958448627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627328744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1627328744
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2599081902
Short name T405
Test name
Test status
Simulation time 35745560 ps
CPU time 0.79 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 205620 kb
Host smart-0ad69f99-05cb-42e5-b2a3-26149e31914b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599081902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2599081902
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.4209144263
Short name T69
Test name
Test status
Simulation time 26650557 ps
CPU time 0.91 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 216212 kb
Host smart-17cceaf4-d909-429c-8a28-f0c5f264cc56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209144263 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.4209144263
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1934468282
Short name T184
Test name
Test status
Simulation time 326455922 ps
CPU time 1.01 seconds
Started Jun 05 05:57:02 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 219140 kb
Host smart-7491b62f-bb44-4b80-9f48-ff979c46d782
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934468282 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1934468282
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3265588063
Short name T50
Test name
Test status
Simulation time 24042023 ps
CPU time 1.11 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 218108 kb
Host smart-a17ac182-7fcc-45bb-912e-e20f68ed0e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265588063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3265588063
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1347366916
Short name T377
Test name
Test status
Simulation time 49955559 ps
CPU time 1.44 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 218116 kb
Host smart-10dd264d-9475-4e3a-b3eb-e17cd47915d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347366916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1347366916
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2615243328
Short name T408
Test name
Test status
Simulation time 27139347 ps
CPU time 0.96 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 215008 kb
Host smart-555cbe8d-8649-4a3a-b53a-d3b48502253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615243328 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2615243328
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4082108961
Short name T786
Test name
Test status
Simulation time 16407755 ps
CPU time 1 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215036 kb
Host smart-11157b6f-27f8-43ab-b127-a2e6d76c6c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082108961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4082108961
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1799400899
Short name T521
Test name
Test status
Simulation time 642483203 ps
CPU time 3.21 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 216656 kb
Host smart-538fcb66-b2cf-40c1-9fb3-da0198c81502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799400899 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1799400899
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.903459951
Short name T199
Test name
Test status
Simulation time 40544376741 ps
CPU time 904.02 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 06:11:56 PM PDT 24
Peak memory 217360 kb
Host smart-301166d4-852a-4de6-b052-8840c14b3f39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903459951 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.903459951
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3686279504
Short name T626
Test name
Test status
Simulation time 37485726 ps
CPU time 1.4 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 216772 kb
Host smart-2f00cb22-6a28-4788-a347-05be9029457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686279504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3686279504
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1761510863
Short name T562
Test name
Test status
Simulation time 31622615 ps
CPU time 1.09 seconds
Started Jun 05 05:58:03 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 219292 kb
Host smart-8a94bd5e-52af-4cca-8786-ea37e0ee85d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761510863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1761510863
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.241934355
Short name T334
Test name
Test status
Simulation time 48374769 ps
CPU time 1.26 seconds
Started Jun 05 05:58:18 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 217988 kb
Host smart-50a88487-0b37-4903-ac2d-71e0cce448b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241934355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.241934355
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.2908448480
Short name T774
Test name
Test status
Simulation time 43582700 ps
CPU time 1.12 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 216468 kb
Host smart-db76298a-866a-4ad7-b5f0-56ddc1be5826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908448480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.2908448480
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1324300887
Short name T656
Test name
Test status
Simulation time 410590852 ps
CPU time 3.44 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 219672 kb
Host smart-9bddfca0-71b4-4485-bdee-ee7740267fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324300887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1324300887
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.280437520
Short name T494
Test name
Test status
Simulation time 37626574 ps
CPU time 1.55 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 217840 kb
Host smart-fd79f58e-2be4-4734-a4ee-c18b7cafca06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280437520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.280437520
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1592082515
Short name T615
Test name
Test status
Simulation time 75091799 ps
CPU time 1.12 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 216892 kb
Host smart-cc773f6f-ee85-4023-af28-7f0c44b3366c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592082515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1592082515
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2663000327
Short name T515
Test name
Test status
Simulation time 142378224 ps
CPU time 1.4 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 219152 kb
Host smart-aa2179c0-13d8-404f-9faf-2b5003d7eac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663000327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2663000327
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2744906225
Short name T475
Test name
Test status
Simulation time 66128300 ps
CPU time 0.99 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 216656 kb
Host smart-ae80b5de-cc7c-4d18-b3a7-81a184503cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744906225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2744906225
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3093946153
Short name T650
Test name
Test status
Simulation time 38506468 ps
CPU time 1.19 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215428 kb
Host smart-5fe96b32-2b91-4040-9f68-17dd6cccf877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093946153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3093946153
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1688283106
Short name T536
Test name
Test status
Simulation time 17516407 ps
CPU time 0.96 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:06 PM PDT 24
Peak memory 214492 kb
Host smart-f13caa69-c893-47c2-8a2b-bf4db5621f44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688283106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1688283106
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1613499277
Short name T640
Test name
Test status
Simulation time 32356314 ps
CPU time 1.01 seconds
Started Jun 05 05:57:33 PM PDT 24
Finished Jun 05 05:57:35 PM PDT 24
Peak memory 216780 kb
Host smart-7295264a-d637-4064-9839-1ee84e63c77a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613499277 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1613499277
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3053879788
Short name T168
Test name
Test status
Simulation time 35122719 ps
CPU time 0.98 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 219576 kb
Host smart-efb480cc-a2dc-4eaf-8887-39e1d4a190f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053879788 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3053879788
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1004151181
Short name T758
Test name
Test status
Simulation time 44192428 ps
CPU time 1.54 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 217808 kb
Host smart-b51d8e3d-f5c5-41cd-87b5-c5cf3f0795ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004151181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1004151181
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3604621028
Short name T519
Test name
Test status
Simulation time 22503990 ps
CPU time 1.18 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 223636 kb
Host smart-b40ea37d-ecd0-42c5-80a2-150952750dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604621028 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3604621028
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.939246537
Short name T537
Test name
Test status
Simulation time 39468494 ps
CPU time 0.88 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:48 PM PDT 24
Peak memory 214884 kb
Host smart-e5712cf2-3c28-4dfe-9bda-d2a87ecf6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939246537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.939246537
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3063248003
Short name T337
Test name
Test status
Simulation time 1705181674 ps
CPU time 2.88 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 215016 kb
Host smart-18fe1f23-5af4-4d62-9cc0-ee15ba9db34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063248003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3063248003
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2974597652
Short name T190
Test name
Test status
Simulation time 18669364483 ps
CPU time 494.97 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 06:04:59 PM PDT 24
Peak memory 217436 kb
Host smart-09e7f11f-63c0-438a-a4f0-cc0ee8b4db48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974597652 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2974597652
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2590848048
Short name T119
Test name
Test status
Simulation time 49879889 ps
CPU time 1.53 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 217812 kb
Host smart-dc4ae52e-1814-4fa8-b8b6-34ca67af3300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590848048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2590848048
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.19022172
Short name T636
Test name
Test status
Simulation time 38062661 ps
CPU time 1.44 seconds
Started Jun 05 05:57:59 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 216676 kb
Host smart-732751bb-7818-4384-9798-ecb9802497e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19022172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.19022172
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1120942605
Short name T457
Test name
Test status
Simulation time 185618070 ps
CPU time 2.29 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 219716 kb
Host smart-e07a7c39-ed36-4f66-9008-d1338546ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120942605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1120942605
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.881196953
Short name T762
Test name
Test status
Simulation time 53758783 ps
CPU time 2.07 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 219616 kb
Host smart-fb95f4b6-044e-4ca4-9be4-0c7ad863c04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881196953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.881196953
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2661635129
Short name T630
Test name
Test status
Simulation time 50799645 ps
CPU time 1.84 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:03 PM PDT 24
Peak memory 219552 kb
Host smart-f0bea5dc-6678-439b-abd3-75d0c6e08716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661635129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2661635129
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1636650443
Short name T449
Test name
Test status
Simulation time 276832612 ps
CPU time 3.89 seconds
Started Jun 05 05:58:22 PM PDT 24
Finished Jun 05 05:58:27 PM PDT 24
Peak memory 219500 kb
Host smart-da737959-767d-45cf-a790-a4fe46de01cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636650443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1636650443
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.197400715
Short name T341
Test name
Test status
Simulation time 30296545 ps
CPU time 1.23 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 217952 kb
Host smart-d6c3eab6-aa5a-47d9-aacf-37e244227378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197400715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.197400715
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_disable.2445211243
Short name T846
Test name
Test status
Simulation time 11978528 ps
CPU time 0.88 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 216384 kb
Host smart-783bd73e-1273-4541-a3da-b0f8874a8afa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445211243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2445211243
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3181493171
Short name T231
Test name
Test status
Simulation time 138210165 ps
CPU time 1.14 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 219476 kb
Host smart-402d1e4f-c973-4527-8978-b4567ffcbe1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181493171 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3181493171
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2377511093
Short name T701
Test name
Test status
Simulation time 30331147 ps
CPU time 1.31 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 231736 kb
Host smart-d6c99e7a-18aa-499d-85c2-c1b2bcdf3033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377511093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2377511093
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.4177157905
Short name T780
Test name
Test status
Simulation time 118381051 ps
CPU time 1.39 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 216872 kb
Host smart-be1a9d97-4f67-4b01-aac3-5cc612c11f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177157905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.4177157905
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2463418558
Short name T705
Test name
Test status
Simulation time 20707134 ps
CPU time 1.11 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215520 kb
Host smart-d2cc8817-2b49-48ea-a2b6-6e39387605d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463418558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2463418558
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2821479383
Short name T323
Test name
Test status
Simulation time 41006963 ps
CPU time 0.9 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215032 kb
Host smart-2e508fe3-ea28-4e4e-8046-7119d8c2cf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821479383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2821479383
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3477080141
Short name T684
Test name
Test status
Simulation time 210727762 ps
CPU time 4.16 seconds
Started Jun 05 05:56:59 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 217904 kb
Host smart-303f208d-c4d4-4414-9444-ca38a98693aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477080141 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3477080141
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3487814521
Short name T679
Test name
Test status
Simulation time 27425731815 ps
CPU time 716.91 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 06:08:48 PM PDT 24
Peak memory 217296 kb
Host smart-c9b6c100-f0f6-43ee-9f8c-2bf9468edfd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487814521 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3487814521
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.3321550757
Short name T535
Test name
Test status
Simulation time 29560886 ps
CPU time 1.21 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 217756 kb
Host smart-78fb5d22-7357-470a-9daa-6178c0683401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321550757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3321550757
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3935031498
Short name T723
Test name
Test status
Simulation time 73867829 ps
CPU time 1.23 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 218252 kb
Host smart-716d100a-eb00-499c-a1d7-6e7c5482a1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935031498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3935031498
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3835397252
Short name T455
Test name
Test status
Simulation time 54552837 ps
CPU time 1.6 seconds
Started Jun 05 05:58:08 PM PDT 24
Finished Jun 05 05:58:10 PM PDT 24
Peak memory 217960 kb
Host smart-a6e05d88-ad88-4233-8f58-594832fb3dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835397252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3835397252
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.2088864795
Short name T792
Test name
Test status
Simulation time 109403647 ps
CPU time 1.51 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218172 kb
Host smart-c131a73f-1e45-4541-85da-071e57238b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088864795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.2088864795
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.229605855
Short name T307
Test name
Test status
Simulation time 130514416 ps
CPU time 3.04 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 218088 kb
Host smart-bce7755b-ccc4-46e2-977b-3dafd03d66aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229605855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.229605855
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3658286167
Short name T842
Test name
Test status
Simulation time 91731411 ps
CPU time 1.43 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218408 kb
Host smart-ac0657d1-02fa-4a34-9021-c4a53dc14d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658286167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3658286167
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.4174908227
Short name T669
Test name
Test status
Simulation time 67437722 ps
CPU time 1.26 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 218172 kb
Host smart-74cf47bc-9377-477e-8254-419125c2dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174908227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.4174908227
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2146021136
Short name T373
Test name
Test status
Simulation time 42688844 ps
CPU time 1.53 seconds
Started Jun 05 05:58:02 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 217948 kb
Host smart-05ab83f6-bd9d-4ef7-bdb1-43acfb4352d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146021136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2146021136
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3256006275
Short name T380
Test name
Test status
Simulation time 38043010 ps
CPU time 1.22 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:58:00 PM PDT 24
Peak memory 218996 kb
Host smart-09943b1b-c1d0-4eef-bd00-8a0b086ef329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256006275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3256006275
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.833777071
Short name T368
Test name
Test status
Simulation time 55232266 ps
CPU time 0.89 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 206172 kb
Host smart-5bc9f059-6efc-4658-beb9-56155da9dc77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833777071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.833777071
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1336703491
Short name T727
Test name
Test status
Simulation time 70459021 ps
CPU time 0.85 seconds
Started Jun 05 05:57:02 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 215260 kb
Host smart-1329f546-c117-4f59-a090-e9300b2019f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336703491 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1336703491
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3198653628
Short name T146
Test name
Test status
Simulation time 21603504 ps
CPU time 1.02 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 216576 kb
Host smart-cdd94def-6511-46bc-a134-f9420708b43d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198653628 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3198653628
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1610162593
Short name T513
Test name
Test status
Simulation time 28154335 ps
CPU time 0.91 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 219200 kb
Host smart-0152a92f-90ee-4171-bc99-32bace819cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610162593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1610162593
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1097830982
Short name T346
Test name
Test status
Simulation time 116727427 ps
CPU time 2.86 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 218092 kb
Host smart-134ff08e-ce87-4559-90b4-dd4593a4d99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097830982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1097830982
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3915925546
Short name T444
Test name
Test status
Simulation time 24208944 ps
CPU time 1.05 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 215328 kb
Host smart-f26cfe15-af4b-4765-88c6-dc6208b927c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915925546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3915925546
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3569632580
Short name T659
Test name
Test status
Simulation time 19370548 ps
CPU time 0.99 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 206848 kb
Host smart-7f4a2bb1-5f2e-40e4-a067-208f6811d837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569632580 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3569632580
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.902411891
Short name T424
Test name
Test status
Simulation time 63918205 ps
CPU time 1.85 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 216696 kb
Host smart-cb8fea27-6e4d-4a75-9754-e9d6df8d0323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902411891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.902411891
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.2598609877
Short name T252
Test name
Test status
Simulation time 80897328 ps
CPU time 3.29 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 219172 kb
Host smart-4493495d-6a90-46cc-84d8-0a41ca64fa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598609877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2598609877
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1792638051
Short name T748
Test name
Test status
Simulation time 49371162 ps
CPU time 1.4 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 217772 kb
Host smart-1f5185f5-8963-4752-99c9-f5ff65a61526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792638051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1792638051
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2612328592
Short name T836
Test name
Test status
Simulation time 63645513 ps
CPU time 1.56 seconds
Started Jun 05 05:58:14 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 218076 kb
Host smart-9aab3a77-e74e-43a0-ae16-4f5643bcd28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612328592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2612328592
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.921736908
Short name T623
Test name
Test status
Simulation time 123623869 ps
CPU time 1.66 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218256 kb
Host smart-89383e7e-9037-44a1-ae0e-7ff5b246913c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921736908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.921736908
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2150997269
Short name T327
Test name
Test status
Simulation time 111823001 ps
CPU time 1.21 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 217896 kb
Host smart-6eefea9f-c951-40a3-b2d8-171fb49bcb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150997269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2150997269
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3014328601
Short name T581
Test name
Test status
Simulation time 150016793 ps
CPU time 3.15 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218080 kb
Host smart-eed98473-d6ad-4cf0-a99a-a761073e3dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014328601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3014328601
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1749708510
Short name T838
Test name
Test status
Simulation time 45145221 ps
CPU time 1.38 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 217792 kb
Host smart-1db95b45-7229-4236-ab39-37ec0cc89aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749708510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1749708510
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3613315337
Short name T566
Test name
Test status
Simulation time 94959703 ps
CPU time 1.69 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 215016 kb
Host smart-19c2cc38-cc07-4320-8bbc-4e81f6246523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613315337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3613315337
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.258719430
Short name T345
Test name
Test status
Simulation time 48112177 ps
CPU time 1.55 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218868 kb
Host smart-dad6a6f2-9931-437d-90a2-bdfca880f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258719430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.258719430
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.267229639
Short name T708
Test name
Test status
Simulation time 157152731 ps
CPU time 1.23 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 219528 kb
Host smart-b09e5534-5fbf-4d7a-a9e0-a856219dd4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267229639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.267229639
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.907371600
Short name T142
Test name
Test status
Simulation time 27946851 ps
CPU time 1.28 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215428 kb
Host smart-356ad91f-117a-45ce-808c-8f6f07aacb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907371600 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.907371600
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2172111844
Short name T490
Test name
Test status
Simulation time 20647879 ps
CPU time 1.04 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 206312 kb
Host smart-31de65b0-5d1b-4d05-9476-14c718966587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172111844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2172111844
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4045469810
Short name T92
Test name
Test status
Simulation time 14443455 ps
CPU time 0.9 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 216380 kb
Host smart-b0e33b1e-8e50-44b3-917c-f9ae5d64efd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045469810 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4045469810
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3048284910
Short name T41
Test name
Test status
Simulation time 31637800 ps
CPU time 1.08 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 216400 kb
Host smart-535fc39c-4428-4ae7-9444-c3545f0e8eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048284910 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3048284910
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3147735254
Short name T57
Test name
Test status
Simulation time 37244810 ps
CPU time 0.95 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 219208 kb
Host smart-ae6d0ead-1745-4dde-a9eb-f1813fc85079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147735254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3147735254
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.820482904
Short name T660
Test name
Test status
Simulation time 44148717 ps
CPU time 1.23 seconds
Started Jun 05 05:57:10 PM PDT 24
Finished Jun 05 05:57:12 PM PDT 24
Peak memory 218100 kb
Host smart-5ce2a81e-47ae-4867-9ffe-df200ee60814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820482904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.820482904
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1014097805
Short name T577
Test name
Test status
Simulation time 23817604 ps
CPU time 0.92 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 215436 kb
Host smart-f52b78e6-b23d-482c-b0dc-7bba67ce03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014097805 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1014097805
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3224251911
Short name T528
Test name
Test status
Simulation time 28952567 ps
CPU time 0.95 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215036 kb
Host smart-0919ff9d-80a8-4b1d-baaa-16d6a50603cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224251911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3224251911
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3573336730
Short name T201
Test name
Test status
Simulation time 665357142 ps
CPU time 3.69 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 214996 kb
Host smart-dd7448a0-c168-46c8-b903-e03835923a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573336730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3573336730
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4066991561
Short name T354
Test name
Test status
Simulation time 36206507367 ps
CPU time 346.16 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 06:02:48 PM PDT 24
Peak memory 217444 kb
Host smart-7a8d0b6b-b5c0-46f4-96c9-25d78b80a285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066991561 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4066991561
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.950657994
Short name T364
Test name
Test status
Simulation time 46191790 ps
CPU time 1.08 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 216616 kb
Host smart-398d0d24-583b-4674-886a-cc4eaa7e63de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950657994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.950657994
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.515651406
Short name T285
Test name
Test status
Simulation time 49050279 ps
CPU time 1.4 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 215056 kb
Host smart-daab1eda-a096-4d29-959c-ba4774897e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515651406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.515651406
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3485360938
Short name T28
Test name
Test status
Simulation time 58073443 ps
CPU time 1.85 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 217828 kb
Host smart-edfecea9-4451-412d-bd0f-a06c01285673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485360938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3485360938
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.4278530161
Short name T268
Test name
Test status
Simulation time 39398066 ps
CPU time 1.34 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 216780 kb
Host smart-16537a92-3efb-447c-8417-310ed3413447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278530161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.4278530161
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1110308777
Short name T576
Test name
Test status
Simulation time 184068284 ps
CPU time 1.09 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 216664 kb
Host smart-c5d8cedf-95de-4114-9cb9-0a48c5e412cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110308777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1110308777
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1811204166
Short name T516
Test name
Test status
Simulation time 62249562 ps
CPU time 1.06 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 216728 kb
Host smart-4189e2b9-f209-4666-b331-360fab577c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811204166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1811204166
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.4018015625
Short name T294
Test name
Test status
Simulation time 74640910 ps
CPU time 1.13 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 216708 kb
Host smart-88930266-f89d-46b5-b7ad-b916ad78a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018015625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.4018015625
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.4201512011
Short name T464
Test name
Test status
Simulation time 41387635 ps
CPU time 1 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 216700 kb
Host smart-42f0b46f-0570-4a17-ac50-542d62615e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201512011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.4201512011
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3465361313
Short name T722
Test name
Test status
Simulation time 139336882 ps
CPU time 1.89 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 218820 kb
Host smart-f787e81e-fa41-4cd6-9859-b3c15b0626fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465361313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3465361313
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4145155182
Short name T389
Test name
Test status
Simulation time 53457246 ps
CPU time 0.96 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 217004 kb
Host smart-87b20d45-f44e-46c8-8358-f34148538244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145155182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4145155182
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2411377260
Short name T587
Test name
Test status
Simulation time 123837690 ps
CPU time 1.22 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 215412 kb
Host smart-433b473d-7a23-4d4b-83cf-e832628ecf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411377260 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2411377260
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1607443439
Short name T682
Test name
Test status
Simulation time 28808267 ps
CPU time 0.89 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 206336 kb
Host smart-f049f147-fcf1-43b2-9918-b45009c798c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607443439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1607443439
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.755048490
Short name T592
Test name
Test status
Simulation time 21551385 ps
CPU time 0.86 seconds
Started Jun 05 05:56:59 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 216096 kb
Host smart-3f0a4e6d-a908-4a1b-a6b8-3290e08d9e89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755048490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.755048490
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2678886433
Short name T55
Test name
Test status
Simulation time 28370746 ps
CPU time 1.16 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:06 PM PDT 24
Peak memory 216556 kb
Host smart-b100a001-0ba1-4a1b-8a7f-abc3daf31722
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678886433 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2678886433
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2293486722
Short name T152
Test name
Test status
Simulation time 23923981 ps
CPU time 0.96 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 219196 kb
Host smart-0a4eca8c-7210-4420-8f2a-382fc415731c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293486722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2293486722
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.3287498165
Short name T169
Test name
Test status
Simulation time 27286019 ps
CPU time 0.85 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215276 kb
Host smart-6e992bcf-6d6a-4002-9a32-a3367ad6580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287498165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3287498165
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.99392498
Short name T339
Test name
Test status
Simulation time 24216165 ps
CPU time 0.91 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 215036 kb
Host smart-8faca279-e8e6-49ec-98eb-d3ae51ff238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99392498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.99392498
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.4037266385
Short name T744
Test name
Test status
Simulation time 152388091386 ps
CPU time 830.89 seconds
Started Jun 05 05:56:46 PM PDT 24
Finished Jun 05 06:10:38 PM PDT 24
Peak memory 220164 kb
Host smart-b346d3d4-a14b-40b5-8e08-72ac3491a7bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037266385 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.4037266385
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1668377926
Short name T674
Test name
Test status
Simulation time 191929980 ps
CPU time 1.02 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216640 kb
Host smart-3560a5bd-0b7b-4124-89cb-edaaa6652b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668377926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1668377926
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1619924526
Short name T614
Test name
Test status
Simulation time 31318784 ps
CPU time 1.37 seconds
Started Jun 05 05:58:05 PM PDT 24
Finished Jun 05 05:58:07 PM PDT 24
Peak memory 218064 kb
Host smart-375c140b-3990-4212-ab94-19d6e9cba513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619924526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1619924526
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1167220872
Short name T579
Test name
Test status
Simulation time 30752192 ps
CPU time 1.48 seconds
Started Jun 05 05:58:04 PM PDT 24
Finished Jun 05 05:58:06 PM PDT 24
Peak memory 218068 kb
Host smart-15f67af3-3cbd-48a9-b90d-876acc2b1b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167220872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1167220872
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2727171258
Short name T448
Test name
Test status
Simulation time 79719821 ps
CPU time 1.09 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 216588 kb
Host smart-15e240e0-fb77-4cc5-b30b-d1c08778b177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727171258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2727171258
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3643661292
Short name T799
Test name
Test status
Simulation time 154551335 ps
CPU time 1.27 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218236 kb
Host smart-b8b3247c-0134-468e-8793-64e2586f545c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643661292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3643661292
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.4054571459
Short name T715
Test name
Test status
Simulation time 244046556 ps
CPU time 3.34 seconds
Started Jun 05 05:57:58 PM PDT 24
Finished Jun 05 05:58:03 PM PDT 24
Peak memory 218112 kb
Host smart-6d4e84a8-b2da-4fe0-b8f3-862b92048d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054571459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.4054571459
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.607095486
Short name T387
Test name
Test status
Simulation time 43396853 ps
CPU time 1.17 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 219368 kb
Host smart-9d419cc8-7f96-492b-8ade-20081678f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607095486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.607095486
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1428684827
Short name T750
Test name
Test status
Simulation time 28180115 ps
CPU time 1.36 seconds
Started Jun 05 05:58:04 PM PDT 24
Finished Jun 05 05:58:06 PM PDT 24
Peak memory 217960 kb
Host smart-6b7a03f4-153c-4fad-a13b-983f51b1999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428684827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1428684827
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1048020442
Short name T790
Test name
Test status
Simulation time 62212460 ps
CPU time 1.26 seconds
Started Jun 05 05:58:10 PM PDT 24
Finished Jun 05 05:58:12 PM PDT 24
Peak memory 218304 kb
Host smart-0ac69bc4-b1a4-40c1-b82f-08e4b92ef42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048020442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1048020442
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2867751930
Short name T79
Test name
Test status
Simulation time 45290130 ps
CPU time 1.16 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 215384 kb
Host smart-9c9166eb-7845-4b3f-83b3-398d01b1d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867751930 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2867751930
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2664014217
Short name T796
Test name
Test status
Simulation time 39175000 ps
CPU time 0.84 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 214552 kb
Host smart-a989b64d-8244-4dd4-ae5f-7dac82eddcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664014217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2664014217
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3504517785
Short name T644
Test name
Test status
Simulation time 161797860 ps
CPU time 0.87 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 216096 kb
Host smart-97a9e725-d166-447d-84fb-d14394c13f0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504517785 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3504517785
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.2784238121
Short name T777
Test name
Test status
Simulation time 60897759 ps
CPU time 1.2 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 216488 kb
Host smart-3d76429a-3e03-4e40-adf9-32e1f01d5f10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784238121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.2784238121
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.2363710654
Short name T788
Test name
Test status
Simulation time 21278793 ps
CPU time 0.88 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 217972 kb
Host smart-7a9a1cac-d9c3-4c4e-9eef-5a8bb587fd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363710654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2363710654
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3115235147
Short name T717
Test name
Test status
Simulation time 33482987 ps
CPU time 1.35 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 217936 kb
Host smart-49dd54ce-4690-4230-a305-3462978a0203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115235147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3115235147
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3343918698
Short name T113
Test name
Test status
Simulation time 34449182 ps
CPU time 0.96 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215260 kb
Host smart-1754a2dd-7615-4672-b3a3-212f0a9b38ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343918698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3343918698
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.318823828
Short name T522
Test name
Test status
Simulation time 26652311 ps
CPU time 0.94 seconds
Started Jun 05 05:57:15 PM PDT 24
Finished Jun 05 05:57:16 PM PDT 24
Peak memory 214884 kb
Host smart-2f7c8e60-b920-4d7c-9f20-cc2f9a2dbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318823828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.318823828
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3015976451
Short name T554
Test name
Test status
Simulation time 91305439 ps
CPU time 0.98 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 215012 kb
Host smart-69154069-e7e8-4c0d-874e-31171ad431af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015976451 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3015976451
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1454094212
Short name T125
Test name
Test status
Simulation time 36098381179 ps
CPU time 396.93 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 06:03:25 PM PDT 24
Peak memory 217612 kb
Host smart-e003cd1f-619b-4c5e-9652-7983c25d7289
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454094212 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1454094212
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1918356964
Short name T10
Test name
Test status
Simulation time 37548191 ps
CPU time 1.48 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 219476 kb
Host smart-3a3e0fe2-e879-46f5-8d3e-41d5c3cfc429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918356964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1918356964
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3478884765
Short name T652
Test name
Test status
Simulation time 108131913 ps
CPU time 1.16 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 218136 kb
Host smart-512dab83-4478-44b8-9f4d-8a3b7ca7567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478884765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3478884765
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3844465998
Short name T417
Test name
Test status
Simulation time 37517573 ps
CPU time 1.21 seconds
Started Jun 05 05:57:58 PM PDT 24
Finished Jun 05 05:58:00 PM PDT 24
Peak memory 218008 kb
Host smart-96256319-f128-41b4-8af5-fa5d8e00f9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844465998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3844465998
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2685848461
Short name T361
Test name
Test status
Simulation time 29789120 ps
CPU time 1.45 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 218096 kb
Host smart-1eff606c-148b-4547-b3eb-b43be0dbb3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685848461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2685848461
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3415511825
Short name T426
Test name
Test status
Simulation time 141933225 ps
CPU time 2.95 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 217992 kb
Host smart-4c2559d1-38d1-4358-87be-8932909b81ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415511825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3415511825
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1579774448
Short name T670
Test name
Test status
Simulation time 41641295 ps
CPU time 1.63 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 217908 kb
Host smart-45a43511-d286-493b-ae90-389f00a7f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579774448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1579774448
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.623217736
Short name T764
Test name
Test status
Simulation time 54420522 ps
CPU time 1.13 seconds
Started Jun 05 05:58:06 PM PDT 24
Finished Jun 05 05:58:08 PM PDT 24
Peak memory 216628 kb
Host smart-494656b3-843d-4d62-a09b-06b3fc9065b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623217736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.623217736
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2480830372
Short name T9
Test name
Test status
Simulation time 53891469 ps
CPU time 1.69 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 219588 kb
Host smart-7eca85f9-6c77-44fb-94e6-c16f6248b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480830372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2480830372
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1051014946
Short name T406
Test name
Test status
Simulation time 35394714 ps
CPU time 1.35 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 216708 kb
Host smart-c4a310d2-84c3-49c8-9d50-6cb42316e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051014946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1051014946
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.553808122
Short name T839
Test name
Test status
Simulation time 32709790 ps
CPU time 1.2 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:01 PM PDT 24
Peak memory 215464 kb
Host smart-32581793-9b0b-478f-a152-3c7286ab277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553808122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.553808122
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3665305910
Short name T767
Test name
Test status
Simulation time 27251464 ps
CPU time 0.86 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 206308 kb
Host smart-bcdb8659-4a9f-4131-bfcb-64bd6c85a43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665305910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3665305910
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.3020775353
Short name T414
Test name
Test status
Simulation time 12727364 ps
CPU time 0.94 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 216384 kb
Host smart-cfa0f91c-69b6-4396-b639-3d1366fb8ae3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020775353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3020775353
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3326142452
Short name T54
Test name
Test status
Simulation time 42506998 ps
CPU time 1.16 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 216540 kb
Host smart-c1cef06b-9e2c-43d0-854a-25ffcc670c98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326142452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3326142452
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_genbits.428927919
Short name T432
Test name
Test status
Simulation time 44806601 ps
CPU time 1.05 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 216600 kb
Host smart-83670af2-b8d5-4f2d-95ba-878abbd672b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428927919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.428927919
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.4283758601
Short name T613
Test name
Test status
Simulation time 22516324 ps
CPU time 1.08 seconds
Started Jun 05 05:57:14 PM PDT 24
Finished Jun 05 05:57:16 PM PDT 24
Peak memory 215128 kb
Host smart-058b41f7-d522-43e2-ad12-937b160d919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283758601 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.4283758601
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4122463071
Short name T450
Test name
Test status
Simulation time 16152318 ps
CPU time 0.99 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:48 PM PDT 24
Peak memory 215056 kb
Host smart-f707a918-f206-4ae5-b022-0304e60951a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122463071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4122463071
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1670028871
Short name T204
Test name
Test status
Simulation time 419103534 ps
CPU time 2.6 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 216696 kb
Host smart-b4cac1de-6c9d-4186-95af-a68ba6d5aced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670028871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1670028871
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2981908203
Short name T272
Test name
Test status
Simulation time 72431749094 ps
CPU time 449.13 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 06:04:20 PM PDT 24
Peak memory 223472 kb
Host smart-5ecc7076-45a6-427d-9d88-d3d9ff6927a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981908203 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2981908203
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3619490394
Short name T419
Test name
Test status
Simulation time 27263328 ps
CPU time 1.16 seconds
Started Jun 05 05:58:01 PM PDT 24
Finished Jun 05 05:58:03 PM PDT 24
Peak memory 216872 kb
Host smart-d81443c2-47e9-44fb-af3a-9107eece0a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619490394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3619490394
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.564186712
Short name T228
Test name
Test status
Simulation time 38928703 ps
CPU time 1.41 seconds
Started Jun 05 05:58:05 PM PDT 24
Finished Jun 05 05:58:07 PM PDT 24
Peak memory 218120 kb
Host smart-d66b97cd-f9e9-4409-90eb-e45df84aee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564186712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.564186712
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1540583684
Short name T401
Test name
Test status
Simulation time 111141399 ps
CPU time 2.4 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 216984 kb
Host smart-af6274bd-9ddc-447a-85a9-6accee5007a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540583684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1540583684
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2360358104
Short name T721
Test name
Test status
Simulation time 48671313 ps
CPU time 1.64 seconds
Started Jun 05 05:58:01 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 217848 kb
Host smart-01d69d68-73de-4238-901b-de2830eb3a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360358104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2360358104
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3110771014
Short name T741
Test name
Test status
Simulation time 74261834 ps
CPU time 1.01 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216892 kb
Host smart-8e44f995-283e-4cf4-89c6-3d3bced0e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110771014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3110771014
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1894051577
Short name T15
Test name
Test status
Simulation time 57986521 ps
CPU time 1.93 seconds
Started Jun 05 05:58:16 PM PDT 24
Finished Jun 05 05:58:19 PM PDT 24
Peak memory 219536 kb
Host smart-58e1fbb5-4f72-49d8-b5f1-ebb9f4219609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894051577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1894051577
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1899349100
Short name T611
Test name
Test status
Simulation time 72074779 ps
CPU time 1.12 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 218172 kb
Host smart-d511391e-0783-45d0-9b79-1a3ca0c6af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899349100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1899349100
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.2264315595
Short name T689
Test name
Test status
Simulation time 28932959 ps
CPU time 1.2 seconds
Started Jun 05 05:58:01 PM PDT 24
Finished Jun 05 05:58:03 PM PDT 24
Peak memory 219336 kb
Host smart-57ae774c-1ace-4794-808c-59f1afe3ce29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264315595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2264315595
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1471479924
Short name T357
Test name
Test status
Simulation time 107540694 ps
CPU time 1.33 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 216980 kb
Host smart-8939adeb-29e6-45b4-8b7e-d40f22342b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471479924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1471479924
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.3399738873
Short name T78
Test name
Test status
Simulation time 41935455 ps
CPU time 1.21 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:05 PM PDT 24
Peak memory 215428 kb
Host smart-a68263be-824a-4459-b2c5-045520252d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399738873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3399738873
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3531841423
Short name T318
Test name
Test status
Simulation time 51743406 ps
CPU time 1.1 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 206412 kb
Host smart-231c3391-60b2-4567-9647-3e443e9ca2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531841423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3531841423
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.2996038469
Short name T185
Test name
Test status
Simulation time 13807708 ps
CPU time 0.95 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 215400 kb
Host smart-0f1bce10-8d8c-4a49-9a5f-7cdd1756c5b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996038469 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2996038469
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1753468216
Short name T61
Test name
Test status
Simulation time 51601756 ps
CPU time 1.26 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 216596 kb
Host smart-ab11b7bd-4ddc-488f-89ed-f2a50347799a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753468216 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1753468216
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3565134401
Short name T487
Test name
Test status
Simulation time 19335581 ps
CPU time 1.02 seconds
Started Jun 05 05:57:08 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 218888 kb
Host smart-3c4a895b-3536-416e-8959-9c12cf43b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565134401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3565134401
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4209582201
Short name T609
Test name
Test status
Simulation time 363469942 ps
CPU time 1.25 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 216784 kb
Host smart-393c5337-00aa-4e0a-92f0-35b603cc15cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209582201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4209582201
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1367612029
Short name T801
Test name
Test status
Simulation time 23140657 ps
CPU time 0.91 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 215568 kb
Host smart-e6a25005-d07d-40a7-9323-70dcc9595fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367612029 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1367612029
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.567773164
Short name T589
Test name
Test status
Simulation time 39751862 ps
CPU time 0.88 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215032 kb
Host smart-1a1729ee-c660-47a9-9b1e-e9b83844b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567773164 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.567773164
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1849788292
Short name T672
Test name
Test status
Simulation time 1151569233 ps
CPU time 2.36 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215068 kb
Host smart-236270c4-d2c4-468c-a19c-d630bc3b481b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849788292 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1849788292
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3364060605
Short name T189
Test name
Test status
Simulation time 235954907905 ps
CPU time 1598.25 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 06:23:55 PM PDT 24
Peak memory 224012 kb
Host smart-b7559616-0c1c-41ec-9d60-016c9267da15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364060605 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3364060605
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.928866624
Short name T365
Test name
Test status
Simulation time 97348852 ps
CPU time 1.11 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 217896 kb
Host smart-f77703ab-a7dc-4ee6-a83b-be57e9158f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928866624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.928866624
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2915444843
Short name T601
Test name
Test status
Simulation time 72272077 ps
CPU time 1.03 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:03 PM PDT 24
Peak memory 216824 kb
Host smart-f294dda5-52e2-4c06-a01a-c417b742763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915444843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2915444843
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2814752486
Short name T330
Test name
Test status
Simulation time 30678050 ps
CPU time 1.31 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218984 kb
Host smart-7a2c628c-3c2a-4a6e-9ad7-c9308976e804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814752486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2814752486
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3468507137
Short name T600
Test name
Test status
Simulation time 36779635 ps
CPU time 1.49 seconds
Started Jun 05 05:58:04 PM PDT 24
Finished Jun 05 05:58:06 PM PDT 24
Peak memory 217916 kb
Host smart-6a860489-a2e5-42be-9b4c-2c9353da24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468507137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3468507137
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2288601120
Short name T397
Test name
Test status
Simulation time 126007112 ps
CPU time 1.06 seconds
Started Jun 05 05:58:07 PM PDT 24
Finished Jun 05 05:58:08 PM PDT 24
Peak memory 215032 kb
Host smart-a092046d-dcf3-4e59-af74-2ceb35bd5adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288601120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2288601120
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.934415407
Short name T719
Test name
Test status
Simulation time 42647950 ps
CPU time 1.68 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:13 PM PDT 24
Peak memory 217836 kb
Host smart-f728f7d9-c17f-4ced-a5a5-190c14160775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934415407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.934415407
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1673440486
Short name T470
Test name
Test status
Simulation time 122847932 ps
CPU time 1.04 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 216692 kb
Host smart-725df33d-fd18-429b-a2ef-ca1fa66ef700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673440486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1673440486
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2184062476
Short name T641
Test name
Test status
Simulation time 48096002 ps
CPU time 1.25 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216744 kb
Host smart-adbc414a-cbc2-430b-b406-435acbe880fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184062476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2184062476
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2393139639
Short name T276
Test name
Test status
Simulation time 46522042 ps
CPU time 1.38 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 219364 kb
Host smart-05cb9167-9ff4-4719-bd9f-66cc90537455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393139639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2393139639
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1242529389
Short name T413
Test name
Test status
Simulation time 41615048 ps
CPU time 1.11 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 216852 kb
Host smart-59633db6-f6fa-40f8-9011-2d006511e04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242529389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1242529389
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4269981965
Short name T263
Test name
Test status
Simulation time 41459233 ps
CPU time 1.2 seconds
Started Jun 05 05:56:41 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 215408 kb
Host smart-bd24bd90-f365-4696-aff7-745ef2e4bc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269981965 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4269981965
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3342006805
Short name T752
Test name
Test status
Simulation time 66150883 ps
CPU time 0.96 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 206176 kb
Host smart-6520de5a-35ab-4b3c-b7f0-c4001aa0419a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342006805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3342006805
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2139900998
Short name T153
Test name
Test status
Simulation time 12305563 ps
CPU time 0.87 seconds
Started Jun 05 05:56:31 PM PDT 24
Finished Jun 05 05:56:32 PM PDT 24
Peak memory 216244 kb
Host smart-82960ade-2624-4c2b-9718-0403e2e781aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139900998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2139900998
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2883101090
Short name T808
Test name
Test status
Simulation time 36161858 ps
CPU time 1.04 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 219244 kb
Host smart-5491a2a5-40ee-4f57-97bc-6857c4ddb5f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883101090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2883101090
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.4117826666
Short name T58
Test name
Test status
Simulation time 38088515 ps
CPU time 1.08 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 220252 kb
Host smart-778d524d-3fc4-45a6-97fd-afa3bf2c2523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117826666 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4117826666
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2629311797
Short name T298
Test name
Test status
Simulation time 53932588 ps
CPU time 1.31 seconds
Started Jun 05 05:56:40 PM PDT 24
Finished Jun 05 05:56:42 PM PDT 24
Peak memory 219620 kb
Host smart-2922f6c8-c0f1-417a-abdd-cdae30fe0021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629311797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2629311797
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2772357262
Short name T571
Test name
Test status
Simulation time 33648470 ps
CPU time 0.9 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 215452 kb
Host smart-2f61d395-7c36-4f55-acee-a1874d7885f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772357262 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2772357262
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2179775339
Short name T122
Test name
Test status
Simulation time 455910791 ps
CPU time 4.19 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 236244 kb
Host smart-c5206153-f0ca-4110-b51c-bd63ac09d7cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179775339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2179775339
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3258175430
Short name T428
Test name
Test status
Simulation time 41522892 ps
CPU time 0.94 seconds
Started Jun 05 05:56:34 PM PDT 24
Finished Jun 05 05:56:36 PM PDT 24
Peak memory 215036 kb
Host smart-3b7a0711-9317-4b2b-b155-dbb9ccd5378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258175430 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3258175430
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.237467881
Short name T525
Test name
Test status
Simulation time 277180310 ps
CPU time 2.05 seconds
Started Jun 05 05:56:39 PM PDT 24
Finished Jun 05 05:56:41 PM PDT 24
Peak memory 215044 kb
Host smart-7d0dd549-42f8-4a20-b698-005172b1ba0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237467881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.237467881
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.505258029
Short name T622
Test name
Test status
Simulation time 120872768875 ps
CPU time 844.73 seconds
Started Jun 05 05:56:39 PM PDT 24
Finished Jun 05 06:10:44 PM PDT 24
Peak memory 222256 kb
Host smart-2b40965e-6bee-417b-9e53-ac73105cfd2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505258029 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.505258029
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.2262701206
Short name T393
Test name
Test status
Simulation time 23647388 ps
CPU time 0.93 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 206336 kb
Host smart-87255341-a111-4903-bbee-a5d8ba390bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262701206 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2262701206
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3305929168
Short name T64
Test name
Test status
Simulation time 34583072 ps
CPU time 0.86 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215240 kb
Host smart-ea005b8c-6529-4354-9641-14cae3461994
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305929168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3305929168
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3764869510
Short name T131
Test name
Test status
Simulation time 80440024 ps
CPU time 1.12 seconds
Started Jun 05 05:57:08 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 216660 kb
Host smart-5f9724de-82f0-42cc-88a8-307c665ff3d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764869510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3764869510
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3541160231
Short name T629
Test name
Test status
Simulation time 19890791 ps
CPU time 0.96 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 218100 kb
Host smart-3c0783f1-b8b3-4e5a-8fd6-941b5d521166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541160231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3541160231
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3302773147
Short name T239
Test name
Test status
Simulation time 91715536 ps
CPU time 1.24 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 218604 kb
Host smart-886b9c45-7b69-4ef8-ab2f-daa40b098db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302773147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3302773147
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2097112318
Short name T755
Test name
Test status
Simulation time 26325121 ps
CPU time 0.99 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 215364 kb
Host smart-81057790-5c2a-4041-aa16-620e97f00a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097112318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2097112318
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2081080969
Short name T309
Test name
Test status
Simulation time 35887270 ps
CPU time 0.95 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 214960 kb
Host smart-aa0d0297-8d0a-44ec-88fe-dea28b31bf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081080969 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2081080969
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2968791342
Short name T483
Test name
Test status
Simulation time 436705958 ps
CPU time 4.52 seconds
Started Jun 05 05:56:59 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 218900 kb
Host smart-2856888a-43aa-465c-b126-df03483dfbc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968791342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2968791342
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.475425783
Short name T399
Test name
Test status
Simulation time 43722953238 ps
CPU time 1020.49 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 06:13:58 PM PDT 24
Peak memory 223536 kb
Host smart-056d4579-cd26-45ee-b2ad-8719e9d5dcbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475425783 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.475425783
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2309798868
Short name T3
Test name
Test status
Simulation time 341900808 ps
CPU time 1.25 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 219040 kb
Host smart-bc8d799a-2508-4e7f-8d1d-8e20ccf6245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309798868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2309798868
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1558976036
Short name T828
Test name
Test status
Simulation time 35407519 ps
CPU time 1.19 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 217828 kb
Host smart-1238e070-7ba5-48e2-b4d2-2d00349e0f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558976036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1558976036
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.1642307529
Short name T783
Test name
Test status
Simulation time 67723383 ps
CPU time 1.08 seconds
Started Jun 05 05:58:19 PM PDT 24
Finished Jun 05 05:58:21 PM PDT 24
Peak memory 216816 kb
Host smart-dc2c6048-103e-4f6a-b615-b4e45242444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642307529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.1642307529
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2959109642
Short name T459
Test name
Test status
Simulation time 57744001 ps
CPU time 1.22 seconds
Started Jun 05 05:58:28 PM PDT 24
Finished Jun 05 05:58:29 PM PDT 24
Peak memory 218140 kb
Host smart-a7600173-bbfa-45c6-a6a8-cadb3c89de2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959109642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2959109642
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2571605915
Short name T498
Test name
Test status
Simulation time 37258746 ps
CPU time 1.15 seconds
Started Jun 05 05:58:21 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 219392 kb
Host smart-c9c214bd-8bb1-4eb4-87ae-aeca60c25a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571605915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2571605915
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2312963357
Short name T16
Test name
Test status
Simulation time 263340664 ps
CPU time 3.81 seconds
Started Jun 05 05:58:10 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 219508 kb
Host smart-0409747e-2e53-49d3-b334-b1f065d66cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312963357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2312963357
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.155528988
Short name T431
Test name
Test status
Simulation time 62639351 ps
CPU time 1.15 seconds
Started Jun 05 05:58:25 PM PDT 24
Finished Jun 05 05:58:27 PM PDT 24
Peak memory 219216 kb
Host smart-ec380cb9-65aa-4a76-8495-b222b9b2bd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155528988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.155528988
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1255400500
Short name T794
Test name
Test status
Simulation time 274712880 ps
CPU time 1.78 seconds
Started Jun 05 05:58:13 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 218288 kb
Host smart-072b4d4d-5c8d-40e4-85c3-ab62b1d3142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255400500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1255400500
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1548973617
Short name T227
Test name
Test status
Simulation time 56719414 ps
CPU time 1.07 seconds
Started Jun 05 05:58:23 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 216860 kb
Host smart-3b329ef5-9a0b-4576-981e-93f8d3b6aab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548973617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1548973617
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.101831493
Short name T407
Test name
Test status
Simulation time 32991389 ps
CPU time 1.27 seconds
Started Jun 05 05:58:10 PM PDT 24
Finished Jun 05 05:58:13 PM PDT 24
Peak memory 218008 kb
Host smart-502b8ec2-9ba7-4433-bcf8-be6e842df5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101831493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.101831493
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3991869769
Short name T580
Test name
Test status
Simulation time 42993095 ps
CPU time 1.21 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 215428 kb
Host smart-9a8a04ac-4c0a-4297-919d-3a04b5fc2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991869769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3991869769
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.837158978
Short name T310
Test name
Test status
Simulation time 55590878 ps
CPU time 0.95 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 214596 kb
Host smart-812cee32-52e2-44b6-be40-9802bb41f559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837158978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.837158978
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3414452075
Short name T565
Test name
Test status
Simulation time 18127076 ps
CPU time 0.81 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 216088 kb
Host smart-b081b28e-ccfd-49ed-a8f2-85bf9d0042bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414452075 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3414452075
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1930532625
Short name T826
Test name
Test status
Simulation time 18033927 ps
CPU time 1.06 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 218160 kb
Host smart-66e5de03-92c7-4d22-b060-c8c369067768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930532625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1930532625
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2958803144
Short name T348
Test name
Test status
Simulation time 51844657 ps
CPU time 1.38 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 218268 kb
Host smart-ba97afbb-7227-4c4a-b8d5-57593b9d1196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958803144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2958803144
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3468042113
Short name T620
Test name
Test status
Simulation time 26925095 ps
CPU time 0.94 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 215308 kb
Host smart-b925a1d1-9696-4124-aab7-0e9b6ac8be73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468042113 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3468042113
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1651336789
Short name T678
Test name
Test status
Simulation time 48506825 ps
CPU time 0.88 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 214848 kb
Host smart-e1e26f26-4f60-4c26-a4ea-7ab7e4d7ea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651336789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1651336789
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.538295641
Short name T205
Test name
Test status
Simulation time 1230947060 ps
CPU time 3.79 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:57:01 PM PDT 24
Peak memory 215040 kb
Host smart-df503a38-ef45-4f60-94e4-e6a6f2c3d73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538295641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.538295641
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1843578892
Short name T197
Test name
Test status
Simulation time 169323511061 ps
CPU time 942.47 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 06:12:33 PM PDT 24
Peak memory 221948 kb
Host smart-4ba86db5-67fa-45c9-a5a5-b5166e1df75c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843578892 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1843578892
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1801678666
Short name T398
Test name
Test status
Simulation time 57709253 ps
CPU time 1.27 seconds
Started Jun 05 05:58:24 PM PDT 24
Finished Jun 05 05:58:25 PM PDT 24
Peak memory 218000 kb
Host smart-50725748-5b60-4b1b-a0fc-b42b78bb0fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801678666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1801678666
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1984929542
Short name T825
Test name
Test status
Simulation time 27899473 ps
CPU time 1.29 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 217780 kb
Host smart-31087eec-ce4e-4d8e-bc68-212d94c1ccea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984929542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1984929542
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.1291162893
Short name T771
Test name
Test status
Simulation time 65041069 ps
CPU time 1.21 seconds
Started Jun 05 05:58:20 PM PDT 24
Finished Jun 05 05:58:22 PM PDT 24
Peak memory 216928 kb
Host smart-bd0514ae-8787-48bd-9235-1045b104c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291162893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1291162893
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.668903768
Short name T118
Test name
Test status
Simulation time 383585053 ps
CPU time 4.47 seconds
Started Jun 05 05:58:28 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 218560 kb
Host smart-99f8afda-89b8-4ec7-8664-d9c4051f93d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668903768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.668903768
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3594070530
Short name T512
Test name
Test status
Simulation time 62503420 ps
CPU time 1.22 seconds
Started Jun 05 05:58:16 PM PDT 24
Finished Jun 05 05:58:18 PM PDT 24
Peak memory 216792 kb
Host smart-7a0f5f5d-d614-47e7-899b-b7a177c448b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594070530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3594070530
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1072944191
Short name T384
Test name
Test status
Simulation time 133173965 ps
CPU time 1.21 seconds
Started Jun 05 05:58:14 PM PDT 24
Finished Jun 05 05:58:15 PM PDT 24
Peak memory 219120 kb
Host smart-d05cd5a5-1b30-4504-ac14-d1ce4bbbbcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072944191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1072944191
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2579654642
Short name T529
Test name
Test status
Simulation time 95882140 ps
CPU time 1.4 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:13 PM PDT 24
Peak memory 218116 kb
Host smart-005d4a68-a8db-4418-9a1d-51457cb1b02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579654642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2579654642
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.385521698
Short name T469
Test name
Test status
Simulation time 54761781 ps
CPU time 1.42 seconds
Started Jun 05 05:58:23 PM PDT 24
Finished Jun 05 05:58:25 PM PDT 24
Peak memory 218224 kb
Host smart-ea769b3c-186b-436a-8176-b09722990985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385521698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.385521698
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2356164340
Short name T803
Test name
Test status
Simulation time 50421610 ps
CPU time 1.67 seconds
Started Jun 05 05:58:22 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 217972 kb
Host smart-55ebd6df-b328-4cb8-ae15-b1e2639d4b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356164340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2356164340
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2333135125
Short name T262
Test name
Test status
Simulation time 28185049 ps
CPU time 1.19 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 215244 kb
Host smart-9e996cc1-cb80-46aa-8230-822a0114aef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333135125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2333135125
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3338758306
Short name T606
Test name
Test status
Simulation time 19279032 ps
CPU time 0.99 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 05:57:06 PM PDT 24
Peak memory 206328 kb
Host smart-bcac5c8b-e848-404b-a025-1b667c6282d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338758306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3338758306
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1476974853
Short name T438
Test name
Test status
Simulation time 10703954 ps
CPU time 0.87 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 216244 kb
Host smart-76378fd5-6986-4fc4-9620-c393dab67a82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476974853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1476974853
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1398852542
Short name T591
Test name
Test status
Simulation time 112360432 ps
CPU time 1.17 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 219524 kb
Host smart-c2157d85-ec41-4e43-8cfa-7b3f2cd1605c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398852542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1398852542
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3847797891
Short name T156
Test name
Test status
Simulation time 35222857 ps
CPU time 0.98 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 223340 kb
Host smart-526d62f5-847f-47fd-89b8-d6b831f8ce75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847797891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3847797891
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2021365648
Short name T575
Test name
Test status
Simulation time 66460850 ps
CPU time 1.16 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 218412 kb
Host smart-a8182662-a51c-4698-888c-426858915c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021365648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2021365648
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1754959763
Short name T110
Test name
Test status
Simulation time 19550146 ps
CPU time 1.09 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 215476 kb
Host smart-5fc82a54-8219-4a96-b475-0048667dfe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754959763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1754959763
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1677881634
Short name T643
Test name
Test status
Simulation time 24792537 ps
CPU time 0.92 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 215036 kb
Host smart-0e9d6673-b092-41bc-bb4c-51997f2ea1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677881634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1677881634
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.412524267
Short name T203
Test name
Test status
Simulation time 1779161226 ps
CPU time 3.47 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 216776 kb
Host smart-73b09406-bf13-4859-a074-258b1351d966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412524267 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.412524267
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3407125727
Short name T775
Test name
Test status
Simulation time 78520258876 ps
CPU time 462.8 seconds
Started Jun 05 05:57:05 PM PDT 24
Finished Jun 05 06:04:49 PM PDT 24
Peak memory 218424 kb
Host smart-4b6ff4f7-7feb-412c-b4ae-ed4de50ecd99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407125727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3407125727
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/221.edn_genbits.1992244169
Short name T664
Test name
Test status
Simulation time 57622968 ps
CPU time 1.37 seconds
Started Jun 05 05:58:09 PM PDT 24
Finished Jun 05 05:58:12 PM PDT 24
Peak memory 218100 kb
Host smart-12ba9eba-aafe-4832-b574-b87406712f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992244169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1992244169
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.957243336
Short name T27
Test name
Test status
Simulation time 43297699 ps
CPU time 1.58 seconds
Started Jun 05 05:58:07 PM PDT 24
Finished Jun 05 05:58:09 PM PDT 24
Peak memory 218168 kb
Host smart-035ece45-abbf-47f1-95d0-6d79d75280b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957243336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.957243336
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2638138599
Short name T779
Test name
Test status
Simulation time 57019751 ps
CPU time 1.48 seconds
Started Jun 05 05:58:16 PM PDT 24
Finished Jun 05 05:58:18 PM PDT 24
Peak memory 218260 kb
Host smart-48112593-03c8-4a3b-82f2-73a0f2cd9654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638138599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2638138599
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3323649848
Short name T135
Test name
Test status
Simulation time 192644571 ps
CPU time 1.49 seconds
Started Jun 05 05:58:17 PM PDT 24
Finished Jun 05 05:58:19 PM PDT 24
Peak memory 218304 kb
Host smart-6c54852a-e0cd-4ccf-a364-40ece505dc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323649848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3323649848
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2994175538
Short name T251
Test name
Test status
Simulation time 213913573 ps
CPU time 3.08 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 219008 kb
Host smart-a5686ec8-ead7-4aa3-bd53-843bb168ff14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994175538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2994175538
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.954437654
Short name T306
Test name
Test status
Simulation time 40075730 ps
CPU time 1.44 seconds
Started Jun 05 05:58:24 PM PDT 24
Finished Jun 05 05:58:26 PM PDT 24
Peak memory 217772 kb
Host smart-c8f39178-ab8f-4f01-98ba-bd2c3864d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954437654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.954437654
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1461470553
Short name T344
Test name
Test status
Simulation time 59572141 ps
CPU time 1.95 seconds
Started Jun 05 05:58:18 PM PDT 24
Finished Jun 05 05:58:21 PM PDT 24
Peak memory 219396 kb
Host smart-03c2a02d-c100-4fd6-9f50-8f9f99f01d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461470553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1461470553
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1885081512
Short name T296
Test name
Test status
Simulation time 121413983 ps
CPU time 1.27 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:19 PM PDT 24
Peak memory 218148 kb
Host smart-9836b2ca-f042-490f-b8fd-28e779ecea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885081512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1885081512
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3845471553
Short name T539
Test name
Test status
Simulation time 75860359 ps
CPU time 1.12 seconds
Started Jun 05 05:58:10 PM PDT 24
Finished Jun 05 05:58:12 PM PDT 24
Peak memory 216848 kb
Host smart-d0e0066d-963a-4393-9de1-2231165c6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845471553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3845471553
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.4293297861
Short name T491
Test name
Test status
Simulation time 25253785 ps
CPU time 1.2 seconds
Started Jun 05 05:57:03 PM PDT 24
Finished Jun 05 05:57:05 PM PDT 24
Peak memory 215428 kb
Host smart-9d40e61b-26ec-4392-a5c4-d1c699f42574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293297861 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.4293297861
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.93039915
Short name T312
Test name
Test status
Simulation time 25825033 ps
CPU time 0.83 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 206616 kb
Host smart-e1edbbae-b04e-479c-8918-f5ad0c27cecc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93039915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.93039915
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3811214608
Short name T154
Test name
Test status
Simulation time 11572872 ps
CPU time 0.87 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 216092 kb
Host smart-19b51027-3ec9-408f-8623-c05a043254d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811214608 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3811214608
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.922682017
Short name T559
Test name
Test status
Simulation time 86280709 ps
CPU time 1.03 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 215428 kb
Host smart-d1f17266-d5db-4646-895f-447213dc819b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922682017 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_di
sable_auto_req_mode.922682017
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.2441375481
Short name T725
Test name
Test status
Simulation time 19271724 ps
CPU time 0.97 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 218108 kb
Host smart-f168e06d-d7c1-4c44-b387-afe1ab1f8887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441375481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.2441375481
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4022716925
Short name T806
Test name
Test status
Simulation time 49561423 ps
CPU time 1.56 seconds
Started Jun 05 05:57:12 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 217988 kb
Host smart-66649e2e-c4f5-452d-8508-165784876929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022716925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4022716925
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1360135722
Short name T340
Test name
Test status
Simulation time 37581211 ps
CPU time 0.85 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 215116 kb
Host smart-39d844c0-3f29-4c4d-b233-693697a24c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360135722 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1360135722
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2349377276
Short name T556
Test name
Test status
Simulation time 27740339 ps
CPU time 0.98 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:50 PM PDT 24
Peak memory 215052 kb
Host smart-9a17ae63-f4de-4565-b82b-efb712ff95b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349377276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2349377276
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1091133141
Short name T716
Test name
Test status
Simulation time 141500866 ps
CPU time 1.42 seconds
Started Jun 05 05:57:08 PM PDT 24
Finished Jun 05 05:57:10 PM PDT 24
Peak memory 216824 kb
Host smart-9b28ea17-ca39-47e3-a33a-f6f6c2ac1e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091133141 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1091133141
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1491169141
Short name T433
Test name
Test status
Simulation time 262754939934 ps
CPU time 1359.54 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 06:19:39 PM PDT 24
Peak memory 224160 kb
Host smart-8f741692-971d-4ffd-8adc-e1edc425c57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491169141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1491169141
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1371010448
Short name T463
Test name
Test status
Simulation time 91467455 ps
CPU time 1.51 seconds
Started Jun 05 05:58:07 PM PDT 24
Finished Jun 05 05:58:09 PM PDT 24
Peak memory 218240 kb
Host smart-1cee2d40-f66b-4684-8adc-899b83ae1a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371010448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1371010448
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3925162001
Short name T706
Test name
Test status
Simulation time 70109336 ps
CPU time 1.26 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 218424 kb
Host smart-bd52a23c-74de-45c2-b2c4-dd6d45deaa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925162001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3925162001
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4246534750
Short name T520
Test name
Test status
Simulation time 47773713 ps
CPU time 1.22 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:13 PM PDT 24
Peak memory 219272 kb
Host smart-d2b5049c-3391-4f0e-930a-123e63ded502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246534750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4246534750
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1519174720
Short name T280
Test name
Test status
Simulation time 154030233 ps
CPU time 1.4 seconds
Started Jun 05 05:58:11 PM PDT 24
Finished Jun 05 05:58:13 PM PDT 24
Peak memory 218504 kb
Host smart-9cbf4a62-1505-46c3-badd-c21052f92778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519174720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1519174720
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.4026781389
Short name T385
Test name
Test status
Simulation time 70475259 ps
CPU time 1.34 seconds
Started Jun 05 05:57:59 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 216696 kb
Host smart-7174a466-f6c6-4a75-b0cb-fda66a2778de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026781389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.4026781389
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3522647103
Short name T821
Test name
Test status
Simulation time 104167785 ps
CPU time 1.39 seconds
Started Jun 05 05:58:29 PM PDT 24
Finished Jun 05 05:58:31 PM PDT 24
Peak memory 216840 kb
Host smart-b08ffc4a-c2d7-4ad9-a313-0875a7ec97c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522647103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3522647103
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.4156646093
Short name T11
Test name
Test status
Simulation time 58846534 ps
CPU time 1.53 seconds
Started Jun 05 05:58:24 PM PDT 24
Finished Jun 05 05:58:26 PM PDT 24
Peak memory 219132 kb
Host smart-9c9f6f54-ae76-4a49-af07-1448e8637e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156646093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.4156646093
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1208378494
Short name T466
Test name
Test status
Simulation time 185370682 ps
CPU time 1.2 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:02 PM PDT 24
Peak memory 216784 kb
Host smart-ccd922d8-d527-46fa-b25e-35190ef6b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208378494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1208378494
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3617455
Short name T120
Test name
Test status
Simulation time 205172073 ps
CPU time 1.2 seconds
Started Jun 05 05:58:27 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 216992 kb
Host smart-de63dbc9-ae12-479a-ae26-8a8900354106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3617455
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3949557286
Short name T98
Test name
Test status
Simulation time 97335213 ps
CPU time 1.15 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 215404 kb
Host smart-a3148fd3-49c7-46f0-b4e7-4cdb02c23fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949557286 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3949557286
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1391089159
Short name T485
Test name
Test status
Simulation time 110216286 ps
CPU time 0.9 seconds
Started Jun 05 05:57:20 PM PDT 24
Finished Jun 05 05:57:22 PM PDT 24
Peak memory 214508 kb
Host smart-712720d4-d2cb-482a-a097-1564c7bd7fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391089159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1391089159
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2991043734
Short name T39
Test name
Test status
Simulation time 110234970 ps
CPU time 1.14 seconds
Started Jun 05 05:57:13 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 216744 kb
Host smart-78507ce4-c82e-41f9-82fa-70b55ce12123
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991043734 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2991043734
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3176587201
Short name T782
Test name
Test status
Simulation time 43977855 ps
CPU time 0.99 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 219560 kb
Host smart-032b8aa5-6c8c-4f66-9181-374f14c9611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176587201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3176587201
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2180753414
Short name T552
Test name
Test status
Simulation time 103210870 ps
CPU time 2.33 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 217028 kb
Host smart-5327f8b2-d934-49fb-a3fd-324e2c11b354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180753414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2180753414
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2817068907
Short name T144
Test name
Test status
Simulation time 34102377 ps
CPU time 0.87 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215388 kb
Host smart-de832e5c-8bd5-402a-903a-b3039ca170d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817068907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2817068907
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.866296371
Short name T546
Test name
Test status
Simulation time 17590056 ps
CPU time 1 seconds
Started Jun 05 05:57:32 PM PDT 24
Finished Jun 05 05:57:34 PM PDT 24
Peak memory 214788 kb
Host smart-afa95371-02f1-4ede-8842-21be82758cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866296371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.866296371
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2250452427
Short name T148
Test name
Test status
Simulation time 136801761 ps
CPU time 2.38 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 216628 kb
Host smart-03ae95ae-72b1-43fd-8ea2-df35daf8293b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250452427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2250452427
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4101817747
Short name T809
Test name
Test status
Simulation time 50345457140 ps
CPU time 572.49 seconds
Started Jun 05 05:56:54 PM PDT 24
Finished Jun 05 06:06:27 PM PDT 24
Peak memory 218084 kb
Host smart-985dbe8a-65d0-4164-9ab1-de47f0dd5f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101817747 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4101817747
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3731560181
Short name T338
Test name
Test status
Simulation time 145404544 ps
CPU time 1.06 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 216760 kb
Host smart-443caef6-1935-42cb-84ae-2cc8f9e73fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731560181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3731560181
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2303438862
Short name T274
Test name
Test status
Simulation time 107121267 ps
CPU time 1.2 seconds
Started Jun 05 05:58:30 PM PDT 24
Finished Jun 05 05:58:32 PM PDT 24
Peak memory 218228 kb
Host smart-edaf14f6-6659-4c0f-b93b-2cc9ec428066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303438862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2303438862
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1170678633
Short name T311
Test name
Test status
Simulation time 74180485 ps
CPU time 1.28 seconds
Started Jun 05 05:58:26 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 218036 kb
Host smart-649a589e-59fa-4241-b73d-3f2e63dca913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170678633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1170678633
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.3924482989
Short name T416
Test name
Test status
Simulation time 65120512 ps
CPU time 1.35 seconds
Started Jun 05 05:58:25 PM PDT 24
Finished Jun 05 05:58:26 PM PDT 24
Peak memory 217772 kb
Host smart-5f211bb0-3ace-4b40-a426-d643d31caf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924482989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.3924482989
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.1377323184
Short name T467
Test name
Test status
Simulation time 60931276 ps
CPU time 1.03 seconds
Started Jun 05 05:58:14 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 216744 kb
Host smart-31c003b8-9000-484f-8358-f2351773289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377323184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.1377323184
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.496574721
Short name T422
Test name
Test status
Simulation time 38811432 ps
CPU time 1.07 seconds
Started Jun 05 05:58:26 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 216800 kb
Host smart-40a44d5e-01f5-4903-ba53-1e08aec33868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496574721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.496574721
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.94924977
Short name T505
Test name
Test status
Simulation time 47951086 ps
CPU time 1.46 seconds
Started Jun 05 05:58:24 PM PDT 24
Finished Jun 05 05:58:26 PM PDT 24
Peak memory 217944 kb
Host smart-52a2aecb-b3ef-4aa2-8369-57dca49d6b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94924977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.94924977
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2773553462
Short name T396
Test name
Test status
Simulation time 53541057 ps
CPU time 1.13 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 216764 kb
Host smart-78603eac-5e88-4749-8f25-542e1f34cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773553462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2773553462
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1405857199
Short name T395
Test name
Test status
Simulation time 38036295 ps
CPU time 1.26 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 217880 kb
Host smart-f63b9c8a-8cba-4c40-a01c-477d3e54cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405857199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1405857199
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1874974495
Short name T737
Test name
Test status
Simulation time 161275797 ps
CPU time 1.22 seconds
Started Jun 05 05:58:20 PM PDT 24
Finished Jun 05 05:58:21 PM PDT 24
Peak memory 216752 kb
Host smart-9f4feb52-6372-4570-9546-50d8bbda893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874974495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1874974495
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1314012799
Short name T618
Test name
Test status
Simulation time 26979242 ps
CPU time 1.3 seconds
Started Jun 05 05:57:02 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 215412 kb
Host smart-82b22a5f-885b-44f4-b6fe-9601eee848e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314012799 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1314012799
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1563741707
Short name T477
Test name
Test status
Simulation time 19309148 ps
CPU time 0.82 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 206128 kb
Host smart-63967749-ca37-41af-b6f9-5fe3284bea1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563741707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1563741707
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3256576401
Short name T797
Test name
Test status
Simulation time 40350647 ps
CPU time 0.84 seconds
Started Jun 05 05:57:28 PM PDT 24
Finished Jun 05 05:57:29 PM PDT 24
Peak memory 216176 kb
Host smart-88bb1273-94f5-4fac-a46d-b6ddc975a284
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256576401 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3256576401
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2133607321
Short name T446
Test name
Test status
Simulation time 84660414 ps
CPU time 1.13 seconds
Started Jun 05 05:57:13 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 215484 kb
Host smart-d8eda4df-5f4a-4207-a0b2-7014dc511682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133607321 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2133607321
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3294108585
Short name T77
Test name
Test status
Simulation time 36153201 ps
CPU time 0.88 seconds
Started Jun 05 05:57:03 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 217964 kb
Host smart-fcaf9a0a-9910-4846-81f1-e8dbc65c9ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294108585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3294108585
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2425833223
Short name T760
Test name
Test status
Simulation time 228590191 ps
CPU time 3.25 seconds
Started Jun 05 05:57:15 PM PDT 24
Finished Jun 05 05:57:19 PM PDT 24
Peak memory 219732 kb
Host smart-c0ea88d3-94e3-4232-9ebf-1e3d49d7b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425833223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2425833223
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.888533868
Short name T109
Test name
Test status
Simulation time 20123882 ps
CPU time 1.02 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215500 kb
Host smart-f7b9302a-5e00-4de9-963d-b2f1f4311bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888533868 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.888533868
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.634701537
Short name T612
Test name
Test status
Simulation time 17606589 ps
CPU time 1 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 214876 kb
Host smart-4b95d725-c64a-4e8d-a378-c474963cc5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634701537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.634701537
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2683746691
Short name T342
Test name
Test status
Simulation time 114698326 ps
CPU time 2.72 seconds
Started Jun 05 05:57:03 PM PDT 24
Finished Jun 05 05:57:06 PM PDT 24
Peak memory 216828 kb
Host smart-a8e87ffc-67fa-4c95-853b-68b1613750ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683746691 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2683746691
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3241595198
Short name T188
Test name
Test status
Simulation time 16508228023 ps
CPU time 93.84 seconds
Started Jun 05 05:57:04 PM PDT 24
Finished Jun 05 05:58:39 PM PDT 24
Peak memory 217008 kb
Host smart-a92cedc3-e8cb-43ce-b37b-9f9bffa86032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241595198 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3241595198
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3282078618
Short name T728
Test name
Test status
Simulation time 82428153 ps
CPU time 1.95 seconds
Started Jun 05 05:58:21 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 217148 kb
Host smart-3937d4bd-f0d0-478c-af59-3e41d312ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282078618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3282078618
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1331092849
Short name T315
Test name
Test status
Simulation time 62509113 ps
CPU time 2.18 seconds
Started Jun 05 05:58:20 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 218024 kb
Host smart-a5c94275-cd85-4380-bc21-9f9da93858f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331092849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1331092849
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2362794241
Short name T757
Test name
Test status
Simulation time 54485290 ps
CPU time 1.16 seconds
Started Jun 05 05:58:20 PM PDT 24
Finished Jun 05 05:58:21 PM PDT 24
Peak memory 216772 kb
Host smart-8020fbb7-2b59-437f-af35-6021ee434fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362794241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2362794241
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1943721010
Short name T297
Test name
Test status
Simulation time 108739853 ps
CPU time 1.55 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 218092 kb
Host smart-3f514840-6ff0-42a1-88ce-a7179012466d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943721010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1943721010
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.511472533
Short name T749
Test name
Test status
Simulation time 236017803 ps
CPU time 0.96 seconds
Started Jun 05 05:58:12 PM PDT 24
Finished Jun 05 05:58:14 PM PDT 24
Peak memory 216740 kb
Host smart-b367fa14-1732-4159-8393-128674af3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511472533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.511472533
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.3422078849
Short name T277
Test name
Test status
Simulation time 122674838 ps
CPU time 1.2 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 219228 kb
Host smart-1270c6dc-cf40-4e36-b2c5-0099fc8b848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422078849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.3422078849
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1610923059
Short name T633
Test name
Test status
Simulation time 85133337 ps
CPU time 1.25 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 218192 kb
Host smart-e98869fc-3422-4fd2-a140-cfa7fee050f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610923059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1610923059
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4142877136
Short name T136
Test name
Test status
Simulation time 38546628 ps
CPU time 1.49 seconds
Started Jun 05 05:58:17 PM PDT 24
Finished Jun 05 05:58:19 PM PDT 24
Peak memory 215088 kb
Host smart-513c1a9d-55fa-4584-b3c8-5f419f16ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142877136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4142877136
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2981192188
Short name T269
Test name
Test status
Simulation time 28255188 ps
CPU time 1.29 seconds
Started Jun 05 05:58:25 PM PDT 24
Finished Jun 05 05:58:27 PM PDT 24
Peak memory 217888 kb
Host smart-44aa75f7-d24b-45b5-90b7-67214205a6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981192188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2981192188
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.469641458
Short name T319
Test name
Test status
Simulation time 122040710 ps
CPU time 1.08 seconds
Started Jun 05 05:58:14 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 216832 kb
Host smart-56c4b920-b276-40df-b5ad-939da477aeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469641458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.469641458
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3079829726
Short name T249
Test name
Test status
Simulation time 99519680 ps
CPU time 1.26 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215400 kb
Host smart-8b5da4d6-6a65-4a81-843a-a7c3f325efba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079829726 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3079829726
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3342275964
Short name T325
Test name
Test status
Simulation time 19848349 ps
CPU time 1.01 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:19 PM PDT 24
Peak memory 214588 kb
Host smart-2578d77d-7221-4422-9d90-accced645f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342275964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3342275964
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.3088030236
Short name T699
Test name
Test status
Simulation time 45147403 ps
CPU time 0.83 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 215660 kb
Host smart-a22b8fcc-37fb-4390-8c85-2adf3e4509ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088030236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3088030236
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1200849953
Short name T754
Test name
Test status
Simulation time 31863539 ps
CPU time 0.93 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 218488 kb
Host smart-a94be893-0415-464f-bada-410b78f4b049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200849953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1200849953
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3363188788
Short name T290
Test name
Test status
Simulation time 404492374 ps
CPU time 2.04 seconds
Started Jun 05 05:57:12 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 218140 kb
Host smart-c837c7ad-8c1b-4068-b9eb-1d8f75f44712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363188788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3363188788
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.901720848
Short name T468
Test name
Test status
Simulation time 22011101 ps
CPU time 1.22 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 223548 kb
Host smart-91f1fd8f-6f59-401a-9069-c5e98c9bbdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901720848 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.901720848
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.364891424
Short name T817
Test name
Test status
Simulation time 26862878 ps
CPU time 0.93 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 214976 kb
Host smart-88511746-6f47-438f-a652-51d73c5283ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364891424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.364891424
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.2627424381
Short name T731
Test name
Test status
Simulation time 875022568 ps
CPU time 4.89 seconds
Started Jun 05 05:57:07 PM PDT 24
Finished Jun 05 05:57:13 PM PDT 24
Peak memory 216436 kb
Host smart-30d5563e-a99b-48f2-b9d6-2d8c0d3841f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627424381 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.2627424381
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2737844662
Short name T738
Test name
Test status
Simulation time 135701103903 ps
CPU time 2794.5 seconds
Started Jun 05 05:57:09 PM PDT 24
Finished Jun 05 06:43:45 PM PDT 24
Peak memory 233040 kb
Host smart-cfb4717c-8793-4287-bc71-914153090d47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737844662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2737844662
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2790381957
Short name T460
Test name
Test status
Simulation time 47563271 ps
CPU time 1.7 seconds
Started Jun 05 05:58:20 PM PDT 24
Finished Jun 05 05:58:22 PM PDT 24
Peak memory 216816 kb
Host smart-51ec34ac-c8f5-4252-a2e1-a4a9411f0901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790381957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2790381957
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1540233690
Short name T474
Test name
Test status
Simulation time 187514988 ps
CPU time 0.97 seconds
Started Jun 05 05:58:06 PM PDT 24
Finished Jun 05 05:58:08 PM PDT 24
Peak memory 216860 kb
Host smart-00944126-5a8b-4952-a1b2-9ba30f5407a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540233690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1540233690
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.860559234
Short name T816
Test name
Test status
Simulation time 45329336 ps
CPU time 1.35 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 216856 kb
Host smart-073ad040-a750-4bef-b8ad-c6716cc27865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860559234 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.860559234
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2629958194
Short name T743
Test name
Test status
Simulation time 56588715 ps
CPU time 1.27 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:22 PM PDT 24
Peak memory 216748 kb
Host smart-84be44fd-73e6-4d81-92eb-a9f5e610da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629958194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2629958194
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.294769969
Short name T807
Test name
Test status
Simulation time 67085386 ps
CPU time 1.39 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 215048 kb
Host smart-d2a88a64-ad0d-4913-8a54-32d44fd80c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294769969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.294769969
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3362619590
Short name T17
Test name
Test status
Simulation time 52605961 ps
CPU time 1.55 seconds
Started Jun 05 05:58:18 PM PDT 24
Finished Jun 05 05:58:20 PM PDT 24
Peak memory 215056 kb
Host smart-92f6ae47-eab0-43a0-ad09-18a7ef616320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362619590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3362619590
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1220653555
Short name T798
Test name
Test status
Simulation time 88685035 ps
CPU time 1.55 seconds
Started Jun 05 05:58:29 PM PDT 24
Finished Jun 05 05:58:31 PM PDT 24
Peak memory 218056 kb
Host smart-8f533d84-ffb3-4034-8aa3-d30974ada783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220653555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1220653555
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1919155619
Short name T484
Test name
Test status
Simulation time 88768305 ps
CPU time 1.11 seconds
Started Jun 05 05:58:16 PM PDT 24
Finished Jun 05 05:58:18 PM PDT 24
Peak memory 216820 kb
Host smart-17c256e6-4f79-4c29-a650-67cae7562b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919155619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1919155619
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.863042424
Short name T371
Test name
Test status
Simulation time 52580456 ps
CPU time 1.71 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:18 PM PDT 24
Peak memory 217948 kb
Host smart-68951e02-9949-4c2a-b4d7-032670b6ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863042424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.863042424
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.296703557
Short name T844
Test name
Test status
Simulation time 78797984 ps
CPU time 1.27 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 215328 kb
Host smart-f79d8599-6a14-47cc-85c1-7b0e63d90de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296703557 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.296703557
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.3483239140
Short name T331
Test name
Test status
Simulation time 24704352 ps
CPU time 0.87 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:26 PM PDT 24
Peak memory 206272 kb
Host smart-40f1267c-5d42-47f5-bddf-858905eb706c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483239140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3483239140
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_err.4001706010
Short name T158
Test name
Test status
Simulation time 73747208 ps
CPU time 1.17 seconds
Started Jun 05 05:57:13 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 225268 kb
Host smart-b4567ecd-f352-4fd7-8ab8-bd334df2f06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001706010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.4001706010
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.3856494734
Short name T128
Test name
Test status
Simulation time 73281709 ps
CPU time 1.1 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:17 PM PDT 24
Peak memory 216656 kb
Host smart-5c2a2837-5a85-42b9-b2ac-6d312fb470bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856494734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3856494734
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2903614536
Short name T499
Test name
Test status
Simulation time 42501874 ps
CPU time 0.99 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 215332 kb
Host smart-3dddb0f3-0947-4031-bb0a-90a3f9b37268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903614536 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2903614536
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.3928550744
Short name T409
Test name
Test status
Simulation time 16056787 ps
CPU time 0.99 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215028 kb
Host smart-6177cd1b-ea37-46a4-ab36-17f1c032accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928550744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.3928550744
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3007464428
Short name T510
Test name
Test status
Simulation time 259381796 ps
CPU time 5.44 seconds
Started Jun 05 05:57:06 PM PDT 24
Finished Jun 05 05:57:12 PM PDT 24
Peak memory 215080 kb
Host smart-cbc7bd60-7722-430f-b1ef-73b45e3cf68a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007464428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3007464428
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.327124868
Short name T530
Test name
Test status
Simulation time 67322850276 ps
CPU time 574.91 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 06:06:29 PM PDT 24
Peak memory 219628 kb
Host smart-1f75b1c9-c2b0-432d-b62b-218bfe9529c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327124868 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.327124868
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.3515880470
Short name T818
Test name
Test status
Simulation time 77990185 ps
CPU time 1.08 seconds
Started Jun 05 05:58:16 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 217080 kb
Host smart-54ac0c77-d360-48ce-94fc-81077325518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515880470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.3515880470
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.901542445
Short name T456
Test name
Test status
Simulation time 79330700 ps
CPU time 1.11 seconds
Started Jun 05 05:58:09 PM PDT 24
Finished Jun 05 05:58:11 PM PDT 24
Peak memory 216872 kb
Host smart-89db2750-254c-4642-834f-f68ae3281b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901542445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.901542445
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2471092860
Short name T281
Test name
Test status
Simulation time 102283061 ps
CPU time 2.68 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 219612 kb
Host smart-104476f3-25a3-4214-aa6e-98f59a579219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471092860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2471092860
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1013696345
Short name T356
Test name
Test status
Simulation time 43981394 ps
CPU time 1.27 seconds
Started Jun 05 05:58:25 PM PDT 24
Finished Jun 05 05:58:27 PM PDT 24
Peak memory 218044 kb
Host smart-176af8af-157d-43bd-b795-d381eee36613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013696345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1013696345
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2728367192
Short name T653
Test name
Test status
Simulation time 72935925 ps
CPU time 1.53 seconds
Started Jun 05 05:58:28 PM PDT 24
Finished Jun 05 05:58:30 PM PDT 24
Peak memory 218200 kb
Host smart-780f8ed6-dbf4-4ce2-94a1-9cafb3a12620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728367192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2728367192
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1983985743
Short name T305
Test name
Test status
Simulation time 67796952 ps
CPU time 2.37 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:58:35 PM PDT 24
Peak memory 219292 kb
Host smart-92255c57-585b-4032-91b5-e9e6e7177e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983985743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1983985743
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1039963965
Short name T509
Test name
Test status
Simulation time 68190024 ps
CPU time 1.09 seconds
Started Jun 05 05:58:18 PM PDT 24
Finished Jun 05 05:58:19 PM PDT 24
Peak memory 216812 kb
Host smart-5962feab-cead-4516-a6fe-b5347ff5667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039963965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1039963965
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3577685869
Short name T308
Test name
Test status
Simulation time 33158012 ps
CPU time 1.24 seconds
Started Jun 05 05:58:26 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 216772 kb
Host smart-525fb579-1f8b-4a2a-ad1e-56aa31049301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577685869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3577685869
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.88490759
Short name T772
Test name
Test status
Simulation time 70080373 ps
CPU time 1.58 seconds
Started Jun 05 05:58:31 PM PDT 24
Finished Jun 05 05:58:33 PM PDT 24
Peak memory 219748 kb
Host smart-e2817ed9-de7a-4358-a9d8-f1583b9e831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88490759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.88490759
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.1709895015
Short name T841
Test name
Test status
Simulation time 21196951 ps
CPU time 0.84 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 206612 kb
Host smart-eab6b52a-6447-47ab-a4c3-e97ca46f0f1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709895015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1709895015
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2681813559
Short name T619
Test name
Test status
Simulation time 22068105 ps
CPU time 0.85 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 215728 kb
Host smart-9366aaea-57ef-4f0d-a3b0-ef671ac1b229
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681813559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2681813559
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.4236254248
Short name T374
Test name
Test status
Simulation time 33835327 ps
CPU time 1.15 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 216516 kb
Host smart-9b106df5-d18b-411a-b9c0-b7f7d9219d30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236254248 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.4236254248
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3769098676
Short name T802
Test name
Test status
Simulation time 59980248 ps
CPU time 0.97 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 223300 kb
Host smart-9b7601b1-cfdf-4b1e-9cd0-71bb69fc3681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769098676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3769098676
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.216948468
Short name T347
Test name
Test status
Simulation time 79919811 ps
CPU time 1.5 seconds
Started Jun 05 05:57:14 PM PDT 24
Finished Jun 05 05:57:16 PM PDT 24
Peak memory 218496 kb
Host smart-3faeff02-f731-4441-b179-47af05f33e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216948468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.216948468
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2228874754
Short name T105
Test name
Test status
Simulation time 23207937 ps
CPU time 1.19 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 223536 kb
Host smart-e0ea425a-5b99-46d6-93cb-6a2d7aa5bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228874754 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2228874754
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3276619980
Short name T441
Test name
Test status
Simulation time 26320380 ps
CPU time 0.95 seconds
Started Jun 05 05:57:11 PM PDT 24
Finished Jun 05 05:57:12 PM PDT 24
Peak memory 206856 kb
Host smart-fec5327c-3761-43c1-b1c1-a6924a72b3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276619980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3276619980
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1576643222
Short name T351
Test name
Test status
Simulation time 289097571 ps
CPU time 2.78 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 216476 kb
Host smart-e6ff684d-f4be-45e6-98b4-ecd2ead4c1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576643222 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1576643222
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3098947848
Short name T558
Test name
Test status
Simulation time 104659336667 ps
CPU time 670.17 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 06:08:06 PM PDT 24
Peak memory 221632 kb
Host smart-1afc2c01-e5be-42d1-802a-eb625c59e0e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098947848 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3098947848
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3715071099
Short name T770
Test name
Test status
Simulation time 48284050 ps
CPU time 1.6 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:35 PM PDT 24
Peak memory 218208 kb
Host smart-85ac9036-6b8f-4a23-b279-d53b81539f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715071099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3715071099
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1475469353
Short name T663
Test name
Test status
Simulation time 43295527 ps
CPU time 1.23 seconds
Started Jun 05 05:58:37 PM PDT 24
Finished Jun 05 05:58:39 PM PDT 24
Peak memory 216756 kb
Host smart-193e83e5-aa51-4c61-8baa-e0e5848de773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475469353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1475469353
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3961143309
Short name T288
Test name
Test status
Simulation time 188075425 ps
CPU time 1.19 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 216540 kb
Host smart-99b90df6-bb76-4ad9-aa4b-badecf5ab621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961143309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3961143309
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2617147783
Short name T299
Test name
Test status
Simulation time 311511951 ps
CPU time 3.79 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:41 PM PDT 24
Peak memory 219892 kb
Host smart-a0ee6e5e-631b-4487-b91d-91cb07f21b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617147783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2617147783
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1111983240
Short name T383
Test name
Test status
Simulation time 27248229 ps
CPU time 1.17 seconds
Started Jun 05 05:58:32 PM PDT 24
Finished Jun 05 05:58:34 PM PDT 24
Peak memory 218052 kb
Host smart-6dfdf817-e4a9-4082-bca5-d1fd666c7773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111983240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1111983240
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3542077640
Short name T349
Test name
Test status
Simulation time 66791395 ps
CPU time 1.71 seconds
Started Jun 05 05:58:21 PM PDT 24
Finished Jun 05 05:58:23 PM PDT 24
Peak memory 218072 kb
Host smart-f64cc0a9-4f74-4e19-b689-3876ee3e4616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542077640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3542077640
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2471751253
Short name T471
Test name
Test status
Simulation time 45500504 ps
CPU time 1.14 seconds
Started Jun 05 05:58:29 PM PDT 24
Finished Jun 05 05:58:31 PM PDT 24
Peak memory 216920 kb
Host smart-2998f829-24d8-4b66-89f8-622096e84482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471751253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2471751253
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3871436963
Short name T139
Test name
Test status
Simulation time 55686297 ps
CPU time 1.51 seconds
Started Jun 05 05:58:26 PM PDT 24
Finished Jun 05 05:58:28 PM PDT 24
Peak memory 216912 kb
Host smart-8290e724-fa9a-44c7-838f-ee325a7d72cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871436963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3871436963
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3819377354
Short name T648
Test name
Test status
Simulation time 129653855 ps
CPU time 1.69 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 216924 kb
Host smart-68bb2431-e1d0-4f6f-a56a-c838ad807205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819377354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3819377354
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2969531189
Short name T279
Test name
Test status
Simulation time 110834661 ps
CPU time 1.65 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:35 PM PDT 24
Peak memory 218040 kb
Host smart-99b218c4-a5c1-4bbb-8926-396f8d3b3324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969531189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2969531189
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2939376732
Short name T171
Test name
Test status
Simulation time 32558306 ps
CPU time 1.33 seconds
Started Jun 05 05:57:02 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 215428 kb
Host smart-da05843b-9d61-475e-8283-69e04a241fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939376732 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2939376732
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.4151015958
Short name T461
Test name
Test status
Simulation time 16518349 ps
CPU time 0.91 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 206332 kb
Host smart-dfc298e8-f3e7-44c3-be58-5175387cba96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151015958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.4151015958
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3089062757
Short name T598
Test name
Test status
Simulation time 18534286 ps
CPU time 0.85 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 216064 kb
Host smart-d1cfe422-85bb-4413-9ec0-2321b684fe3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089062757 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3089062757
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1022984309
Short name T132
Test name
Test status
Simulation time 31781351 ps
CPU time 1.2 seconds
Started Jun 05 05:57:32 PM PDT 24
Finished Jun 05 05:57:33 PM PDT 24
Peak memory 216956 kb
Host smart-81a25d9f-b4d4-484e-8423-ac1a718f0ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022984309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1022984309
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.642535248
Short name T178
Test name
Test status
Simulation time 27540693 ps
CPU time 0.86 seconds
Started Jun 05 05:57:03 PM PDT 24
Finished Jun 05 05:57:04 PM PDT 24
Peak memory 217732 kb
Host smart-0e793309-9aa8-45e7-a8a5-311c5913ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642535248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.642535248
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1190970923
Short name T369
Test name
Test status
Simulation time 67521561 ps
CPU time 2.51 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 219732 kb
Host smart-8e4dc404-d3c9-4018-958a-fe865ccb2240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190970923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1190970923
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3986040470
Short name T726
Test name
Test status
Simulation time 23079076 ps
CPU time 1.09 seconds
Started Jun 05 05:56:59 PM PDT 24
Finished Jun 05 05:57:01 PM PDT 24
Peak memory 215112 kb
Host smart-497f57cd-116d-4928-ba83-72a4a0550cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986040470 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3986040470
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1151678763
Short name T543
Test name
Test status
Simulation time 16729862 ps
CPU time 0.99 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:25 PM PDT 24
Peak memory 215048 kb
Host smart-b89fed15-a0d4-444b-a11c-04750e4dcf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151678763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1151678763
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2068031799
Short name T526
Test name
Test status
Simulation time 89766412 ps
CPU time 1.37 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 216592 kb
Host smart-3d2238f3-7be8-4173-b487-f12d4ecb2305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068031799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2068031799
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2661866446
Short name T193
Test name
Test status
Simulation time 15798083064 ps
CPU time 343.02 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 219916 kb
Host smart-d7a56cff-aabe-47f3-8537-7c9c46874afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661866446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2661866446
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2990905747
Short name T692
Test name
Test status
Simulation time 43679574 ps
CPU time 1.5 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 217860 kb
Host smart-7b690e37-2cc5-400b-bc7f-660c9605647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990905747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2990905747
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2795626694
Short name T295
Test name
Test status
Simulation time 44520683 ps
CPU time 1.66 seconds
Started Jun 05 05:58:14 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 216800 kb
Host smart-b6210a87-c869-43ab-a108-e052de8aefaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795626694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2795626694
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2318943591
Short name T709
Test name
Test status
Simulation time 81264180 ps
CPU time 1.46 seconds
Started Jun 05 05:58:22 PM PDT 24
Finished Jun 05 05:58:24 PM PDT 24
Peak memory 214976 kb
Host smart-77287a5c-5bb3-4fe0-b375-1784d784a543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318943591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2318943591
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2865424446
Short name T542
Test name
Test status
Simulation time 50895532 ps
CPU time 1.61 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:39 PM PDT 24
Peak memory 218036 kb
Host smart-f6ef42f8-f802-425b-b99f-77fff405f594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865424446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2865424446
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1999461515
Short name T625
Test name
Test status
Simulation time 109431842 ps
CPU time 1.41 seconds
Started Jun 05 05:58:33 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 216856 kb
Host smart-63318035-4b0a-453f-8923-dbcc97d2b5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999461515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1999461515
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1253483230
Short name T478
Test name
Test status
Simulation time 53436687 ps
CPU time 1.2 seconds
Started Jun 05 05:58:34 PM PDT 24
Finished Jun 05 05:58:36 PM PDT 24
Peak memory 219236 kb
Host smart-3b8f1cfb-3713-4a66-ac7c-a5f7ac707318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253483230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1253483230
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.248960648
Short name T732
Test name
Test status
Simulation time 45210112 ps
CPU time 1.72 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:37 PM PDT 24
Peak memory 217916 kb
Host smart-a8329ca6-ad4d-4dfb-aa44-3497a5365436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248960648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.248960648
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.135247283
Short name T360
Test name
Test status
Simulation time 80106759 ps
CPU time 1.29 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 216792 kb
Host smart-745bf087-48b3-4852-89ce-b0545c71bdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135247283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.135247283
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1623818696
Short name T698
Test name
Test status
Simulation time 309253007 ps
CPU time 2.02 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 219548 kb
Host smart-d0014df9-ab61-4fed-a5c4-a37b7f00660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623818696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1623818696
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2252523276
Short name T696
Test name
Test status
Simulation time 39178543 ps
CPU time 1.08 seconds
Started Jun 05 05:58:35 PM PDT 24
Finished Jun 05 05:58:38 PM PDT 24
Peak memory 219380 kb
Host smart-b06bedca-5c66-43b6-b970-4a36b4bff08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252523276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2252523276
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.3368909634
Short name T258
Test name
Test status
Simulation time 31832549 ps
CPU time 1.23 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215428 kb
Host smart-c9ad9e32-d15e-4046-b299-307067c9aa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368909634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3368909634
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4138998266
Short name T322
Test name
Test status
Simulation time 20637099 ps
CPU time 0.91 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 214548 kb
Host smart-d5de3c96-d73c-4f33-8a1c-1b5ce44cf942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138998266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4138998266
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3832136573
Short name T187
Test name
Test status
Simulation time 13193331 ps
CPU time 0.84 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215240 kb
Host smart-602f959a-83f6-43c6-b898-c7a0d54b6557
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832136573 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3832136573
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.3038754249
Short name T661
Test name
Test status
Simulation time 74085110 ps
CPU time 0.89 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 218180 kb
Host smart-64c6df25-9691-462c-b830-8262c45a3199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038754249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3038754249
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2284031306
Short name T392
Test name
Test status
Simulation time 64864786 ps
CPU time 1.34 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 218156 kb
Host smart-cde41f74-bdde-4464-b56e-3faa4040a8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284031306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2284031306
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1746776183
Short name T819
Test name
Test status
Simulation time 24254484 ps
CPU time 1.02 seconds
Started Jun 05 05:56:42 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 223620 kb
Host smart-2f627e79-12f0-4eec-9ba9-af5818eb00c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746776183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1746776183
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3277214532
Short name T257
Test name
Test status
Simulation time 16510492 ps
CPU time 1.04 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 206856 kb
Host smart-1fa19177-304a-4bca-a4df-8f9b447fcd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277214532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3277214532
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.7448198
Short name T13
Test name
Test status
Simulation time 452744361 ps
CPU time 7.13 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 235564 kb
Host smart-10f9d1f6-0e1e-461b-8efd-df3cf7956b25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7448198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.7448198
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3202680557
Short name T822
Test name
Test status
Simulation time 22943879 ps
CPU time 1.01 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 215020 kb
Host smart-a2bc503e-a228-4c04-bb56-288015590e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202680557 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3202680557
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2940954591
Short name T813
Test name
Test status
Simulation time 562962227 ps
CPU time 5.64 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 214944 kb
Host smart-09487089-9c5a-421d-b893-a20d2e87a4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940954591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2940954591
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2096313008
Short name T768
Test name
Test status
Simulation time 29499196452 ps
CPU time 623.09 seconds
Started Jun 05 05:56:32 PM PDT 24
Finished Jun 05 06:06:55 PM PDT 24
Peak memory 220276 kb
Host smart-f7947dbb-1211-480a-98cf-022c2186cfc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096313008 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2096313008
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1448555322
Short name T595
Test name
Test status
Simulation time 27051109 ps
CPU time 1.18 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215404 kb
Host smart-5153c56c-deb4-4b3e-9cbc-fb748f23a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448555322 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1448555322
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4245883547
Short name T578
Test name
Test status
Simulation time 21709387 ps
CPU time 0.84 seconds
Started Jun 05 05:57:21 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 206324 kb
Host smart-95c5afad-91d8-4b21-b309-0ff89ff6062c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245883547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4245883547
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2638592913
Short name T628
Test name
Test status
Simulation time 14123208 ps
CPU time 1 seconds
Started Jun 05 05:57:08 PM PDT 24
Finished Jun 05 05:57:10 PM PDT 24
Peak memory 216244 kb
Host smart-eb298506-5d74-4710-8762-a98fd140cad6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638592913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2638592913
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1709455729
Short name T588
Test name
Test status
Simulation time 53542582 ps
CPU time 1.06 seconds
Started Jun 05 05:57:09 PM PDT 24
Finished Jun 05 05:57:11 PM PDT 24
Peak memory 216484 kb
Host smart-72141f13-5bf7-4c0c-8347-249108b9490e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709455729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1709455729
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.982285220
Short name T35
Test name
Test status
Simulation time 39215153 ps
CPU time 1.09 seconds
Started Jun 05 05:57:22 PM PDT 24
Finished Jun 05 05:57:23 PM PDT 24
Peak memory 220260 kb
Host smart-aad10d96-708d-4b94-acac-f01ac3212587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982285220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.982285220
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1597271094
Short name T638
Test name
Test status
Simulation time 110395811 ps
CPU time 1.68 seconds
Started Jun 05 05:57:04 PM PDT 24
Finished Jun 05 05:57:07 PM PDT 24
Peak memory 218096 kb
Host smart-c0c440c1-ab6a-4c17-9689-ff21f0e1e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597271094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1597271094
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3105269387
Short name T1
Test name
Test status
Simulation time 53736256 ps
CPU time 1.01 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:08 PM PDT 24
Peak memory 223632 kb
Host smart-c1e0d282-f41c-4e71-b967-9e83fc62070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105269387 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3105269387
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3864997480
Short name T230
Test name
Test status
Simulation time 24525168 ps
CPU time 0.96 seconds
Started Jun 05 05:57:13 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 215032 kb
Host smart-f01ef711-f3af-48ff-9037-3abd9283e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864997480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3864997480
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1937328643
Short name T700
Test name
Test status
Simulation time 455382171 ps
CPU time 2.77 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:21 PM PDT 24
Peak memory 216508 kb
Host smart-07b231fe-7beb-48f3-ac9b-7a30ce98e617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937328643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1937328643
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.959039206
Short name T776
Test name
Test status
Simulation time 104537917325 ps
CPU time 1566.66 seconds
Started Jun 05 05:57:31 PM PDT 24
Finished Jun 05 06:23:39 PM PDT 24
Peak memory 226632 kb
Host smart-8f9f1377-21b5-4f82-a98d-b9f8ed6fc4c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959039206 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.959039206
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3323829397
Short name T172
Test name
Test status
Simulation time 60365473 ps
CPU time 1.12 seconds
Started Jun 05 05:57:11 PM PDT 24
Finished Jun 05 05:57:13 PM PDT 24
Peak memory 215396 kb
Host smart-6a7c5696-557f-4f3c-b94d-ddd421afbfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323829397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3323829397
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.4254866166
Short name T506
Test name
Test status
Simulation time 24899133 ps
CPU time 1.11 seconds
Started Jun 05 05:57:24 PM PDT 24
Finished Jun 05 05:57:31 PM PDT 24
Peak memory 206276 kb
Host smart-f137111d-dfa6-4011-a00d-34242b34271a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254866166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.4254866166
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.723276737
Short name T183
Test name
Test status
Simulation time 13816341 ps
CPU time 0.93 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:18 PM PDT 24
Peak memory 215408 kb
Host smart-c83d599a-cae6-4817-ac57-33f048e809d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723276737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.723276737
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2065284530
Short name T31
Test name
Test status
Simulation time 69607854 ps
CPU time 1.12 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 219208 kb
Host smart-dd330154-495a-4ac0-b512-df6a98783fb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065284530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2065284530
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.1135823168
Short name T617
Test name
Test status
Simulation time 60250664 ps
CPU time 1.16 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:26 PM PDT 24
Peak memory 219324 kb
Host smart-bd51a2a2-897b-4dbf-887f-9c19031bdee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135823168 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1135823168
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.4021761553
Short name T642
Test name
Test status
Simulation time 87132877 ps
CPU time 1.33 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:19 PM PDT 24
Peak memory 216732 kb
Host smart-000a4951-62a3-45b1-a60e-0a9fb1bfcf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021761553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.4021761553
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_smoke.3142610888
Short name T793
Test name
Test status
Simulation time 58307846 ps
CPU time 0.91 seconds
Started Jun 05 05:57:07 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 215052 kb
Host smart-b8965f01-d438-435f-858a-fd2a1882e78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142610888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3142610888
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.679126214
Short name T289
Test name
Test status
Simulation time 171279971 ps
CPU time 2.51 seconds
Started Jun 05 05:57:20 PM PDT 24
Finished Jun 05 05:57:23 PM PDT 24
Peak memory 215232 kb
Host smart-62a7348d-ee09-45d5-9901-f63d871fef73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679126214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.679126214
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.558063353
Short name T352
Test name
Test status
Simulation time 44120265806 ps
CPU time 280.13 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 06:01:58 PM PDT 24
Peak memory 217780 kb
Host smart-68fc03d1-e986-493a-89f4-80039c80fd56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558063353 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.558063353
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.199678362
Short name T267
Test name
Test status
Simulation time 85954912 ps
CPU time 1.17 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215432 kb
Host smart-6091b280-a3a7-46c5-89dc-89ea7bf3f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199678362 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.199678362
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.1075172919
Short name T458
Test name
Test status
Simulation time 31379247 ps
CPU time 0.99 seconds
Started Jun 05 05:57:31 PM PDT 24
Finished Jun 05 05:57:32 PM PDT 24
Peak memory 206388 kb
Host smart-a5495bb1-7c92-4e99-b782-5157e061276f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075172919 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.1075172919
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3535600778
Short name T508
Test name
Test status
Simulation time 28635342 ps
CPU time 0.81 seconds
Started Jun 05 05:57:34 PM PDT 24
Finished Jun 05 05:57:36 PM PDT 24
Peak memory 216016 kb
Host smart-f122d3f2-157d-4ee3-b34c-a86bf7777118
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535600778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3535600778
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.629353785
Short name T47
Test name
Test status
Simulation time 55253321 ps
CPU time 1.07 seconds
Started Jun 05 05:57:06 PM PDT 24
Finished Jun 05 05:57:08 PM PDT 24
Peak memory 218128 kb
Host smart-901245b8-3607-4297-8775-e45250fb79a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629353785 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.629353785
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1148680563
Short name T453
Test name
Test status
Simulation time 33766683 ps
CPU time 1.06 seconds
Started Jun 05 05:57:07 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 219400 kb
Host smart-6e5b4385-d076-4c06-8ff0-78e6cf0733ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148680563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1148680563
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.95684659
Short name T804
Test name
Test status
Simulation time 69539719 ps
CPU time 1.06 seconds
Started Jun 05 05:57:12 PM PDT 24
Finished Jun 05 05:57:13 PM PDT 24
Peak memory 216700 kb
Host smart-45f5fa93-e136-4e0b-9829-388ed0878658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95684659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.95684659
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3798355689
Short name T437
Test name
Test status
Simulation time 20674582 ps
CPU time 1.08 seconds
Started Jun 05 05:57:25 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 215128 kb
Host smart-bf8c6f90-82ce-4b13-9dd6-bd0c87f386bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798355689 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3798355689
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3335446892
Short name T695
Test name
Test status
Simulation time 29682081 ps
CPU time 0.94 seconds
Started Jun 05 05:57:30 PM PDT 24
Finished Jun 05 05:57:32 PM PDT 24
Peak memory 207020 kb
Host smart-eafc7408-ec33-4278-a385-58e916828c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335446892 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3335446892
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.30446828
Short name T388
Test name
Test status
Simulation time 345470572 ps
CPU time 6.97 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:24 PM PDT 24
Peak memory 219552 kb
Host smart-ee6872c8-0c4c-4898-b5dd-81593bdf39cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30446828 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.30446828
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3125525087
Short name T736
Test name
Test status
Simulation time 14064706275 ps
CPU time 370.52 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 06:03:28 PM PDT 24
Peak memory 223120 kb
Host smart-d253c162-5b80-4bbc-a82f-fe7605752926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125525087 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3125525087
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.281018357
Short name T635
Test name
Test status
Simulation time 288165495 ps
CPU time 1.39 seconds
Started Jun 05 05:57:30 PM PDT 24
Finished Jun 05 05:57:32 PM PDT 24
Peak memory 215424 kb
Host smart-7c30b30f-f0da-4f9c-81f6-b970074fbef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281018357 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.281018357
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1967987676
Short name T174
Test name
Test status
Simulation time 125626818 ps
CPU time 0.86 seconds
Started Jun 05 05:57:29 PM PDT 24
Finished Jun 05 05:57:31 PM PDT 24
Peak memory 206088 kb
Host smart-2d316ded-c179-4142-8299-0903a5bad6aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967987676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1967987676
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3172328006
Short name T665
Test name
Test status
Simulation time 11232944 ps
CPU time 0.88 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:20 PM PDT 24
Peak memory 215168 kb
Host smart-9e93242f-8b55-4e3a-b9e3-3fb2777bfd00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172328006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3172328006
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3974622438
Short name T32
Test name
Test status
Simulation time 196000639 ps
CPU time 1.24 seconds
Started Jun 05 05:57:26 PM PDT 24
Finished Jun 05 05:57:28 PM PDT 24
Peak memory 216804 kb
Host smart-3c4dfe84-0e44-41d5-b0b4-29a04ec604eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974622438 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3974622438
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.4259994038
Short name T147
Test name
Test status
Simulation time 24395998 ps
CPU time 1.13 seconds
Started Jun 05 05:57:22 PM PDT 24
Finished Jun 05 05:57:23 PM PDT 24
Peak memory 219520 kb
Host smart-4f8c39b8-4805-4a4a-821b-8b49080bfe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259994038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.4259994038
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3932644115
Short name T673
Test name
Test status
Simulation time 44159021 ps
CPU time 1.32 seconds
Started Jun 05 05:57:30 PM PDT 24
Finished Jun 05 05:57:32 PM PDT 24
Peak memory 218188 kb
Host smart-bf35c111-36ae-42e3-ab8f-aee80ff802a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932644115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3932644115
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1562937656
Short name T560
Test name
Test status
Simulation time 21723030 ps
CPU time 1.07 seconds
Started Jun 05 05:57:28 PM PDT 24
Finished Jun 05 05:57:30 PM PDT 24
Peak memory 215140 kb
Host smart-30864650-5567-4785-b672-3dc05a35c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562937656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1562937656
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3777902791
Short name T544
Test name
Test status
Simulation time 42005821 ps
CPU time 0.92 seconds
Started Jun 05 05:57:13 PM PDT 24
Finished Jun 05 05:57:15 PM PDT 24
Peak memory 215012 kb
Host smart-8315e933-bf4f-477c-a4af-c2cb15427229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777902791 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3777902791
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1062353264
Short name T734
Test name
Test status
Simulation time 283019944 ps
CPU time 2.08 seconds
Started Jun 05 05:57:24 PM PDT 24
Finished Jun 05 05:57:27 PM PDT 24
Peak memory 215100 kb
Host smart-0021355a-25fd-4921-aafa-16ae847cebf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062353264 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1062353264
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3837629285
Short name T191
Test name
Test status
Simulation time 871765691472 ps
CPU time 1400.9 seconds
Started Jun 05 05:57:22 PM PDT 24
Finished Jun 05 06:20:43 PM PDT 24
Peak memory 223164 kb
Host smart-5fdc2bb9-d7b7-4bae-a9de-8a1587bb9593
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837629285 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3837629285
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1885658982
Short name T181
Test name
Test status
Simulation time 41162693 ps
CPU time 1.18 seconds
Started Jun 05 05:57:12 PM PDT 24
Finished Jun 05 05:57:14 PM PDT 24
Peak memory 215324 kb
Host smart-d02fa9a5-f88e-4dc6-8607-23abc8aa0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885658982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1885658982
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2910034419
Short name T534
Test name
Test status
Simulation time 66775927 ps
CPU time 0.98 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 214920 kb
Host smart-f384bbcb-6e19-47af-beb3-7a915825b412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910034419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2910034419
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1096051297
Short name T814
Test name
Test status
Simulation time 119001856 ps
CPU time 1.12 seconds
Started Jun 05 05:57:26 PM PDT 24
Finished Jun 05 05:57:28 PM PDT 24
Peak memory 216684 kb
Host smart-0436785b-0efd-492f-8dfe-1cf45b1d092e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096051297 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1096051297
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.4250172042
Short name T161
Test name
Test status
Simulation time 57027140 ps
CPU time 1.02 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:19 PM PDT 24
Peak memory 220500 kb
Host smart-3b00f75d-e4d9-494c-a648-fac40003a1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250172042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.4250172042
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.4288772678
Short name T355
Test name
Test status
Simulation time 57345774 ps
CPU time 1.26 seconds
Started Jun 05 05:57:27 PM PDT 24
Finished Jun 05 05:57:29 PM PDT 24
Peak memory 217248 kb
Host smart-a82711cd-88b8-4bad-a3a3-4a1a739834fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288772678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.4288772678
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.2436930233
Short name T763
Test name
Test status
Simulation time 52924765 ps
CPU time 0.92 seconds
Started Jun 05 05:57:32 PM PDT 24
Finished Jun 05 05:57:34 PM PDT 24
Peak memory 215004 kb
Host smart-c8b07369-1aba-43c2-8623-9092f6b96946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436930233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2436930233
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1056206214
Short name T574
Test name
Test status
Simulation time 94600513 ps
CPU time 1.12 seconds
Started Jun 05 05:57:11 PM PDT 24
Finished Jun 05 05:57:12 PM PDT 24
Peak memory 216676 kb
Host smart-df193ba0-1d4f-454e-b08a-3c876b8338be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056206214 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1056206214
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2547256294
Short name T479
Test name
Test status
Simulation time 45305288027 ps
CPU time 544.58 seconds
Started Jun 05 05:57:27 PM PDT 24
Finished Jun 05 06:06:32 PM PDT 24
Peak memory 217620 kb
Host smart-61a921e1-7b88-4a25-bcb4-24c985720e88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547256294 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2547256294
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.1628060547
Short name T662
Test name
Test status
Simulation time 86959994 ps
CPU time 1.22 seconds
Started Jun 05 05:57:29 PM PDT 24
Finished Jun 05 05:57:31 PM PDT 24
Peak memory 215428 kb
Host smart-767548c1-4a7b-4e95-9457-901311d28304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628060547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1628060547
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3310805912
Short name T465
Test name
Test status
Simulation time 17850878 ps
CPU time 0.95 seconds
Started Jun 05 05:57:18 PM PDT 24
Finished Jun 05 05:57:24 PM PDT 24
Peak memory 214584 kb
Host smart-d4f9a639-7b77-4b10-a51f-89814a5f82fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310805912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3310805912
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1851851927
Short name T677
Test name
Test status
Simulation time 23006155 ps
CPU time 0.89 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:22 PM PDT 24
Peak memory 216116 kb
Host smart-1fb71bca-0c0c-4e38-95f0-0b5688e5fd51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851851927 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1851851927
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.914650306
Short name T370
Test name
Test status
Simulation time 28631372 ps
CPU time 1.27 seconds
Started Jun 05 05:57:28 PM PDT 24
Finished Jun 05 05:57:30 PM PDT 24
Peak memory 219328 kb
Host smart-9524288f-b63e-44c2-bf1e-d0623eb4eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914650306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.914650306
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3225122350
Short name T830
Test name
Test status
Simulation time 39857607 ps
CPU time 1.33 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:19 PM PDT 24
Peak memory 215044 kb
Host smart-27ec9ee3-949d-437d-8307-c80ddbfdf98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225122350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3225122350
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2988976912
Short name T627
Test name
Test status
Simulation time 20948098 ps
CPU time 1.06 seconds
Started Jun 05 05:57:17 PM PDT 24
Finished Jun 05 05:57:24 PM PDT 24
Peak memory 215112 kb
Host smart-6adbb9ed-68d9-4510-8567-764f97512f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988976912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2988976912
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.314754162
Short name T328
Test name
Test status
Simulation time 45808074 ps
CPU time 0.94 seconds
Started Jun 05 05:57:29 PM PDT 24
Finished Jun 05 05:57:30 PM PDT 24
Peak memory 215028 kb
Host smart-7e975b53-2fbd-4e39-817a-9791f9a085f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314754162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.314754162
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2484732517
Short name T518
Test name
Test status
Simulation time 188012856 ps
CPU time 3.91 seconds
Started Jun 05 05:57:30 PM PDT 24
Finished Jun 05 05:57:35 PM PDT 24
Peak memory 216832 kb
Host smart-759d5a58-051c-458e-84eb-ae2d2687ff0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484732517 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2484732517
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3314924378
Short name T198
Test name
Test status
Simulation time 20580109631 ps
CPU time 241.1 seconds
Started Jun 05 05:57:23 PM PDT 24
Finished Jun 05 06:01:25 PM PDT 24
Peak memory 219532 kb
Host smart-40463f9c-d29e-4525-9291-8d28b07b0da6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314924378 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3314924378
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.4001964178
Short name T473
Test name
Test status
Simulation time 29115597 ps
CPU time 1.25 seconds
Started Jun 05 05:57:36 PM PDT 24
Finished Jun 05 05:57:38 PM PDT 24
Peak memory 215432 kb
Host smart-fb6e55ca-da55-4dde-95be-8aeab95f46c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001964178 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.4001964178
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3652462951
Short name T681
Test name
Test status
Simulation time 36511446 ps
CPU time 0.83 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 206220 kb
Host smart-a33745ef-a40a-471d-96f1-e07d9d24da82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652462951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3652462951
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.510960548
Short name T86
Test name
Test status
Simulation time 41225552 ps
CPU time 0.86 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 216092 kb
Host smart-5753e6d4-50a6-4119-9a03-8755e818f1f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510960548 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.510960548
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1708407986
Short name T517
Test name
Test status
Simulation time 30223265 ps
CPU time 1.09 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 219412 kb
Host smart-32e84e66-2fdd-4dcf-bca5-91430d14a63c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708407986 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1708407986
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.2661750102
Short name T159
Test name
Test status
Simulation time 25089149 ps
CPU time 1.05 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 229088 kb
Host smart-a275a3e5-5a25-46b6-87c8-be4700bd8d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661750102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2661750102
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.485737909
Short name T651
Test name
Test status
Simulation time 52261174 ps
CPU time 1.71 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218020 kb
Host smart-a7917c6e-4bbc-4173-87b4-cc1683e7305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485737909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.485737909
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3134781246
Short name T563
Test name
Test status
Simulation time 28842229 ps
CPU time 0.92 seconds
Started Jun 05 05:57:36 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 215120 kb
Host smart-cab1bf48-2b2c-4cc5-97c8-abb1544925a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134781246 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3134781246
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.95494255
Short name T707
Test name
Test status
Simulation time 42057170 ps
CPU time 0.96 seconds
Started Jun 05 05:57:16 PM PDT 24
Finished Jun 05 05:57:17 PM PDT 24
Peak memory 215052 kb
Host smart-23d94f44-bd22-4219-92a5-584f34a36a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95494255 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.95494255
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3725614284
Short name T549
Test name
Test status
Simulation time 361443112 ps
CPU time 3.91 seconds
Started Jun 05 05:57:26 PM PDT 24
Finished Jun 05 05:57:31 PM PDT 24
Peak memory 218076 kb
Host smart-71723572-6815-4951-bfd7-7e01e25f80f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725614284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3725614284
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3770450047
Short name T832
Test name
Test status
Simulation time 28285007648 ps
CPU time 633.18 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 06:08:14 PM PDT 24
Peak memory 217060 kb
Host smart-9ff0a17d-59db-47c9-87d9-189adffdcb61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770450047 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3770450047
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.2127421929
Short name T439
Test name
Test status
Simulation time 143479707 ps
CPU time 0.95 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 206332 kb
Host smart-7afe409a-0ac9-4a62-bb52-651ebd4dea6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127421929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2127421929
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.268755190
Short name T80
Test name
Test status
Simulation time 37185263 ps
CPU time 0.82 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 216036 kb
Host smart-8a662ff1-92a5-4036-8969-fd8960a70cd8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268755190 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.268755190
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2556852754
Short name T482
Test name
Test status
Simulation time 103797784 ps
CPU time 1.08 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 216624 kb
Host smart-e9e710f9-9c0b-493b-9082-e8ad5a0ed58d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556852754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2556852754
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4149941635
Short name T76
Test name
Test status
Simulation time 28316365 ps
CPU time 0.85 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 217892 kb
Host smart-7b95815f-e004-4a2d-945c-f23438e9a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149941635 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4149941635
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1182347301
Short name T730
Test name
Test status
Simulation time 77278101 ps
CPU time 1.4 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 218660 kb
Host smart-c17271eb-42cf-403d-8b00-36d06c86e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182347301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1182347301
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1910575967
Short name T115
Test name
Test status
Simulation time 43298650 ps
CPU time 0.9 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 215300 kb
Host smart-c352687c-3e8b-4ebf-b4c7-fbf117aea785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910575967 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1910575967
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3443467694
Short name T647
Test name
Test status
Simulation time 15536747 ps
CPU time 0.99 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 215216 kb
Host smart-f8378064-9a0b-4b8b-8f14-7f6fd6984fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443467694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3443467694
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3984799078
Short name T756
Test name
Test status
Simulation time 524754645 ps
CPU time 1.6 seconds
Started Jun 05 05:57:33 PM PDT 24
Finished Jun 05 05:57:35 PM PDT 24
Peak memory 215052 kb
Host smart-4c99d7aa-12e1-4adb-982b-3463746aaaa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984799078 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3984799078
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1152492104
Short name T480
Test name
Test status
Simulation time 16685581532 ps
CPU time 424.58 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 06:04:43 PM PDT 24
Peak memory 222796 kb
Host smart-cef9a2cc-de2a-46e7-a8b0-0e575ec29705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152492104 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1152492104
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1380679958
Short name T34
Test name
Test status
Simulation time 222360532 ps
CPU time 1.25 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 215424 kb
Host smart-d8eb2f46-e3cf-4b80-b5f4-f33fe330a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380679958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1380679958
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1842732203
Short name T551
Test name
Test status
Simulation time 12849737 ps
CPU time 0.86 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 206628 kb
Host smart-deb50314-49f6-45b6-8a7f-3c688db1395a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842732203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1842732203
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3764132187
Short name T160
Test name
Test status
Simulation time 14710246 ps
CPU time 0.93 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 216404 kb
Host smart-ed92a2e6-bbf8-4709-9943-60f3e110d2d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764132187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3764132187
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4010780848
Short name T447
Test name
Test status
Simulation time 37403508 ps
CPU time 1.15 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 216588 kb
Host smart-4d8d018b-e718-46db-aa3f-e0042cad2a19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010780848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4010780848
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2091152807
Short name T773
Test name
Test status
Simulation time 48736471 ps
CPU time 1.35 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 225180 kb
Host smart-0dac49b4-dcb1-4bce-80c5-12fb4f8b0bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091152807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2091152807
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4287012987
Short name T688
Test name
Test status
Simulation time 79192264 ps
CPU time 1.12 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 216720 kb
Host smart-e64561cb-f465-47c7-bdd3-73845990dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287012987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4287012987
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2985822663
Short name T702
Test name
Test status
Simulation time 34289035 ps
CPU time 0.81 seconds
Started Jun 05 05:57:33 PM PDT 24
Finished Jun 05 05:57:34 PM PDT 24
Peak memory 215228 kb
Host smart-3fd628c0-6925-4ea9-8241-6fb993635859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985822663 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2985822663
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3624483932
Short name T402
Test name
Test status
Simulation time 34781810 ps
CPU time 0.92 seconds
Started Jun 05 05:57:34 PM PDT 24
Finished Jun 05 05:57:36 PM PDT 24
Peak memory 215008 kb
Host smart-bf52f9c3-fe66-4ff9-9a6c-6251fc68afc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624483932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3624483932
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1773516285
Short name T784
Test name
Test status
Simulation time 185886117 ps
CPU time 3 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 216812 kb
Host smart-c9c3710d-76af-408d-b1c5-7aa1edf24c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773516285 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1773516285
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2840438347
Short name T194
Test name
Test status
Simulation time 53883075225 ps
CPU time 235.48 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 06:01:39 PM PDT 24
Peak memory 220948 kb
Host smart-59c00d51-d447-456f-98cb-7b358f7a7365
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840438347 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2840438347
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.4199042127
Short name T177
Test name
Test status
Simulation time 26834319 ps
CPU time 1.2 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 215412 kb
Host smart-90410321-6d7b-485e-86bc-f3477594253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199042127 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.4199042127
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.376114284
Short name T583
Test name
Test status
Simulation time 17590284 ps
CPU time 0.87 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 214536 kb
Host smart-f80475f0-fff7-4d9f-97e3-d5d556ad580d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376114284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.376114284
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3357280580
Short name T538
Test name
Test status
Simulation time 35309933 ps
CPU time 0.9 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 215740 kb
Host smart-949ad17d-8b4a-42b5-b33f-55d690cf98b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357280580 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3357280580
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2671698442
Short name T753
Test name
Test status
Simulation time 43474919 ps
CPU time 1.26 seconds
Started Jun 05 05:58:36 PM PDT 24
Finished Jun 05 05:58:39 PM PDT 24
Peak memory 217060 kb
Host smart-ff0f05c1-3a8d-4270-9b29-0202573356c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671698442 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2671698442
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2192759184
Short name T787
Test name
Test status
Simulation time 54915502 ps
CPU time 1 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 218184 kb
Host smart-34e38dc5-1a0e-4c44-abbb-509654443078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192759184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2192759184
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1483842585
Short name T843
Test name
Test status
Simulation time 43065613 ps
CPU time 1.29 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 216636 kb
Host smart-32ef6e0e-efde-4dbb-80bd-4153fbdf1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483842585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1483842585
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.694836086
Short name T140
Test name
Test status
Simulation time 33911806 ps
CPU time 0.87 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215356 kb
Host smart-924c7396-4dce-4cf9-a528-1fd4665fd16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694836086 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.694836086
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1746603399
Short name T376
Test name
Test status
Simulation time 15420146 ps
CPU time 0.96 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 215016 kb
Host smart-90d17899-44b7-44db-b0db-fa01d7cd4c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746603399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1746603399
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3154012251
Short name T697
Test name
Test status
Simulation time 653787027 ps
CPU time 5.76 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 217884 kb
Host smart-6f4fdc3c-60ce-4804-847f-da395e6aa0f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154012251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3154012251
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1253847547
Short name T735
Test name
Test status
Simulation time 31534048502 ps
CPU time 344 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 06:03:23 PM PDT 24
Peak memory 223392 kb
Host smart-8efddb1a-1a84-4255-8b38-33370b8cc1c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253847547 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1253847547
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1761873142
Short name T232
Test name
Test status
Simulation time 43254096 ps
CPU time 1.29 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 215360 kb
Host smart-beadba27-b331-4f31-8dc5-79824c154559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761873142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1761873142
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1265476489
Short name T573
Test name
Test status
Simulation time 43207612 ps
CPU time 0.96 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 214568 kb
Host smart-a3cc9863-b921-4bbc-aafb-a62f42f73c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265476489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1265476489
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.418220296
Short name T372
Test name
Test status
Simulation time 28069756 ps
CPU time 1.2 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 217784 kb
Host smart-127c30c4-be6c-4e1a-88a1-81bac7820f1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418220296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.418220296
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.177218890
Short name T418
Test name
Test status
Simulation time 23624360 ps
CPU time 0.92 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:56 PM PDT 24
Peak memory 218100 kb
Host smart-3d449822-4625-416f-8bff-91beac6f52b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177218890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.177218890
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1125428987
Short name T129
Test name
Test status
Simulation time 41623809 ps
CPU time 1.43 seconds
Started Jun 05 05:56:43 PM PDT 24
Finished Jun 05 05:56:45 PM PDT 24
Peak memory 217824 kb
Host smart-581eadff-3731-467a-be5d-3ec968c5bd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125428987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1125428987
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1551844774
Short name T367
Test name
Test status
Simulation time 21081947 ps
CPU time 1.17 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 223652 kb
Host smart-ed6518aa-6184-4afd-946b-814ee8d22c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551844774 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1551844774
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.973268780
Short name T261
Test name
Test status
Simulation time 14547574 ps
CPU time 0.95 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:48 PM PDT 24
Peak memory 206848 kb
Host smart-c560f85b-2961-486c-a57d-c903a5b0eaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973268780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.973268780
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.348489877
Short name T123
Test name
Test status
Simulation time 950630710 ps
CPU time 4.2 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 237044 kb
Host smart-805c2a3d-20d9-4e0b-b6fc-616bc19aa6e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348489877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.348489877
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2181141012
Short name T820
Test name
Test status
Simulation time 23030716 ps
CPU time 1.04 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 206820 kb
Host smart-c9af4e1a-0e0b-42a6-8ce0-c580f8910abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181141012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2181141012
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2235870901
Short name T366
Test name
Test status
Simulation time 133261388 ps
CPU time 1.13 seconds
Started Jun 05 05:56:41 PM PDT 24
Finished Jun 05 05:56:43 PM PDT 24
Peak memory 206700 kb
Host smart-b07b7dbd-3332-4d73-9fa1-3e0d7bd70b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235870901 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2235870901
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1205258399
Short name T192
Test name
Test status
Simulation time 232171384011 ps
CPU time 1638.11 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 06:24:12 PM PDT 24
Peak memory 225972 kb
Host smart-fc9476c2-4ca9-41a0-bc17-e23c7336ad10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205258399 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1205258399
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1819438317
Short name T805
Test name
Test status
Simulation time 29183930 ps
CPU time 1.25 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215428 kb
Host smart-e7ac2d50-96cc-4e54-bfb4-5cc29387dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819438317 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1819438317
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2495836693
Short name T523
Test name
Test status
Simulation time 109730156 ps
CPU time 0.91 seconds
Started Jun 05 05:57:36 PM PDT 24
Finished Jun 05 05:57:38 PM PDT 24
Peak memory 206252 kb
Host smart-c1959293-7b37-4ed0-ba63-71dc26f096ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495836693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2495836693
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1892079882
Short name T150
Test name
Test status
Simulation time 134840476 ps
CPU time 0.9 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 216092 kb
Host smart-4eb02e49-b960-44fe-bf44-e2a5fda9a949
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892079882 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1892079882
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2944209081
Short name T250
Test name
Test status
Simulation time 90354363 ps
CPU time 1.19 seconds
Started Jun 05 05:57:32 PM PDT 24
Finished Jun 05 05:57:34 PM PDT 24
Peak memory 216488 kb
Host smart-a1c28d46-bde9-45ef-bf68-7d15fd61ff39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944209081 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2944209081
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2879007453
Short name T462
Test name
Test status
Simulation time 32331779 ps
CPU time 0.93 seconds
Started Jun 05 05:57:35 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 217920 kb
Host smart-43de6b12-14c2-4ab0-9145-86a1e39b9a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879007453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2879007453
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1377765380
Short name T831
Test name
Test status
Simulation time 29835877 ps
CPU time 1.31 seconds
Started Jun 05 05:57:34 PM PDT 24
Finished Jun 05 05:57:37 PM PDT 24
Peak memory 218268 kb
Host smart-3bb7ab59-a81c-4874-ad0b-42cf53cd63b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377765380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1377765380
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2838669930
Short name T423
Test name
Test status
Simulation time 22505912 ps
CPU time 0.93 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 215392 kb
Host smart-a59aa37c-ede0-49cc-843f-174f12f6beed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838669930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2838669930
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.656777596
Short name T586
Test name
Test status
Simulation time 38217011 ps
CPU time 0.85 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215032 kb
Host smart-29467858-de09-4004-b09d-d6c037698274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656777596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.656777596
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3382286926
Short name T568
Test name
Test status
Simulation time 327661886 ps
CPU time 3.17 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 216276 kb
Host smart-cf221b91-e052-4704-a265-ed8cee9097f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382286926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3382286926
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3791575246
Short name T829
Test name
Test status
Simulation time 20934885436 ps
CPU time 289.92 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 06:02:37 PM PDT 24
Peak memory 217904 kb
Host smart-bda4aad6-6188-4135-87f3-77c0b765d237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791575246 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3791575246
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2545583409
Short name T778
Test name
Test status
Simulation time 76138018 ps
CPU time 1.07 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:40 PM PDT 24
Peak memory 215464 kb
Host smart-3c2d3290-7193-46c4-b9f0-2c45321c2b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545583409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2545583409
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.4280605048
Short name T329
Test name
Test status
Simulation time 73446530 ps
CPU time 0.95 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:38 PM PDT 24
Peak memory 206304 kb
Host smart-3f8bc860-a6c2-4054-8676-07b3922e9e6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280605048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.4280605048
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.87508629
Short name T658
Test name
Test status
Simulation time 15622847 ps
CPU time 0.84 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 215188 kb
Host smart-4b9abdbe-3256-45f6-baa9-c462c772f7ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87508629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.87508629
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1920571492
Short name T143
Test name
Test status
Simulation time 97112807 ps
CPU time 1.07 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 216488 kb
Host smart-2ed82864-fbfd-45f8-8619-dafc5eca4383
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920571492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1920571492
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2261641301
Short name T303
Test name
Test status
Simulation time 30263272 ps
CPU time 0.88 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 218264 kb
Host smart-115e3094-63a6-4616-9ede-ad795eb2027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261641301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2261641301
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1164385349
Short name T488
Test name
Test status
Simulation time 99757040 ps
CPU time 1.58 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 218204 kb
Host smart-cce75427-3951-4019-abe7-864225de562f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164385349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1164385349
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2677005670
Short name T114
Test name
Test status
Simulation time 25371588 ps
CPU time 0.9 seconds
Started Jun 05 05:58:57 PM PDT 24
Finished Jun 05 05:58:59 PM PDT 24
Peak memory 215204 kb
Host smart-a4e44a47-2438-4c06-a95e-c1520cdbfa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677005670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2677005670
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4265340767
Short name T729
Test name
Test status
Simulation time 51172797 ps
CPU time 0.95 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 215140 kb
Host smart-db41e048-9f13-4eed-8168-1d660bf23085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265340767 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4265340767
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3817377925
Short name T511
Test name
Test status
Simulation time 95484733 ps
CPU time 1.2 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 215000 kb
Host smart-a52bd9f7-3acc-4d6d-8dec-d8d08b29138f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817377925 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3817377925
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2881866616
Short name T411
Test name
Test status
Simulation time 126934848027 ps
CPU time 1568.98 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 06:23:47 PM PDT 24
Peak memory 226796 kb
Host smart-f1f799b5-130e-424a-a6db-b4dfbd2ea6b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881866616 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2881866616
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1916198034
Short name T73
Test name
Test status
Simulation time 45463841 ps
CPU time 1.11 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 215428 kb
Host smart-f9b6dd95-599c-4bf7-9f0a-fe3954f6c326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916198034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1916198034
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.3255161353
Short name T533
Test name
Test status
Simulation time 41260593 ps
CPU time 0.88 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 206320 kb
Host smart-11307915-a30c-474c-96f4-c360d37c3fee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255161353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3255161353
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.793244988
Short name T710
Test name
Test status
Simulation time 108345985 ps
CPU time 0.87 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 216096 kb
Host smart-7334073e-84ca-423b-8f95-be9ab54b649d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793244988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.793244988
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3921275539
Short name T37
Test name
Test status
Simulation time 39000951 ps
CPU time 1.22 seconds
Started Jun 05 05:57:36 PM PDT 24
Finished Jun 05 05:57:38 PM PDT 24
Peak memory 216536 kb
Host smart-0c41ad51-0851-465f-a99e-c97e85cbe284
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921275539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3921275539
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3074746355
Short name T101
Test name
Test status
Simulation time 68401991 ps
CPU time 0.81 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 218752 kb
Host smart-053e81d0-c0b9-4fa4-b777-8c5d80f71b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074746355 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3074746355
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2856491904
Short name T824
Test name
Test status
Simulation time 26335222 ps
CPU time 1.14 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 217320 kb
Host smart-d638ca48-e32e-45c5-9651-0c7055909055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856491904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2856491904
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1537565727
Short name T362
Test name
Test status
Simulation time 71638173 ps
CPU time 0.91 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 215216 kb
Host smart-55e63459-fc84-4d85-85e4-f12a6ff623ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537565727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1537565727
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.276498541
Short name T435
Test name
Test status
Simulation time 30799302 ps
CPU time 0.96 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 215032 kb
Host smart-b284e012-11b6-4c71-9a4c-c646bfcdc1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276498541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.276498541
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3555513758
Short name T507
Test name
Test status
Simulation time 310900719 ps
CPU time 3.84 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 216772 kb
Host smart-3d12e3bd-13b4-4319-b0ba-80e526a90933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555513758 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3555513758
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1691924993
Short name T403
Test name
Test status
Simulation time 156947786342 ps
CPU time 1659.26 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 06:25:20 PM PDT 24
Peak memory 226572 kb
Host smart-b38f2c74-0af1-424e-8840-39f175860511
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691924993 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1691924993
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.616733619
Short name T265
Test name
Test status
Simulation time 91528375 ps
CPU time 1.17 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 215228 kb
Host smart-cd508c9b-0646-46f9-a340-ea653d6af5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616733619 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.616733619
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3234638095
Short name T378
Test name
Test status
Simulation time 44960786 ps
CPU time 0.88 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 214196 kb
Host smart-644af86f-6c46-463f-a938-5e478727b52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234638095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3234638095
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2829391367
Short name T166
Test name
Test status
Simulation time 13881695 ps
CPU time 0.92 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 216380 kb
Host smart-90db623d-b6b7-41e5-aee9-d2504d244830
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829391367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2829391367
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.812788733
Short name T654
Test name
Test status
Simulation time 173963532 ps
CPU time 1.12 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218244 kb
Host smart-6e410365-4727-4ead-ba7c-dd027eaa0c8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812788733 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.812788733
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2719615171
Short name T167
Test name
Test status
Simulation time 35129997 ps
CPU time 1.04 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 220124 kb
Host smart-982a4a67-81a7-4b8f-b685-4836bc8a2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719615171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2719615171
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2587282398
Short name T769
Test name
Test status
Simulation time 32790931 ps
CPU time 1.18 seconds
Started Jun 05 05:58:56 PM PDT 24
Finished Jun 05 05:58:58 PM PDT 24
Peak memory 216036 kb
Host smart-d837b562-6b57-4115-a362-eab07c8110c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587282398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2587282398
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.784095550
Short name T492
Test name
Test status
Simulation time 26853493 ps
CPU time 1.02 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 223652 kb
Host smart-2bd644c4-2616-4955-9999-bb65441551dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784095550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.784095550
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1122174035
Short name T795
Test name
Test status
Simulation time 19129265 ps
CPU time 0.99 seconds
Started Jun 05 05:58:54 PM PDT 24
Finished Jun 05 05:58:56 PM PDT 24
Peak memory 214564 kb
Host smart-1a0a43e3-a626-4980-af80-536b06dca0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122174035 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1122174035
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.698647105
Short name T400
Test name
Test status
Simulation time 76143660 ps
CPU time 1.37 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 214928 kb
Host smart-a81fa82c-b536-40bd-ad75-de483d546ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698647105 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.698647105
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2461277290
Short name T751
Test name
Test status
Simulation time 129184977642 ps
CPU time 746.36 seconds
Started Jun 05 05:57:33 PM PDT 24
Finished Jun 05 06:10:00 PM PDT 24
Peak memory 219440 kb
Host smart-9945597e-55d5-4b5f-a681-84ddb56e59e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461277290 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2461277290
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2631168550
Short name T179
Test name
Test status
Simulation time 26441890 ps
CPU time 1.14 seconds
Started Jun 05 05:58:53 PM PDT 24
Finished Jun 05 05:58:55 PM PDT 24
Peak memory 215216 kb
Host smart-70eead19-1a43-425a-9b59-0483d6872257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631168550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2631168550
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.735977415
Short name T176
Test name
Test status
Simulation time 50481484 ps
CPU time 0.91 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 206348 kb
Host smart-f7d2fda5-b291-49cf-b943-395144498972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735977415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.735977415
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3271548258
Short name T186
Test name
Test status
Simulation time 133890128 ps
CPU time 0.86 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 216096 kb
Host smart-c1f6b0e2-afe4-429c-9453-229be401fc3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271548258 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3271548258
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.212429219
Short name T675
Test name
Test status
Simulation time 54126908 ps
CPU time 1.17 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 217868 kb
Host smart-9c1b79e1-087b-4e48-ab9b-d43c39d812a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212429219 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.212429219
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2052833808
Short name T30
Test name
Test status
Simulation time 41559157 ps
CPU time 0.96 seconds
Started Jun 05 05:57:38 PM PDT 24
Finished Jun 05 05:57:40 PM PDT 24
Peak memory 219308 kb
Host smart-b7b14b7a-01c8-4912-9335-4fca9b059674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052833808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2052833808
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.292780530
Short name T548
Test name
Test status
Simulation time 8759242082 ps
CPU time 121.78 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:59:44 PM PDT 24
Peak memory 220056 kb
Host smart-ddf24654-d29f-45b5-ad25-56843c80635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292780530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.292780530
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.104684667
Short name T180
Test name
Test status
Simulation time 21586888 ps
CPU time 1.07 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 215492 kb
Host smart-c6384c85-d9d9-489a-8832-b39144c49a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104684667 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.104684667
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3915180018
Short name T761
Test name
Test status
Simulation time 40019438 ps
CPU time 0.92 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 215036 kb
Host smart-54414af7-587b-4d34-a83b-dedb3989ea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915180018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3915180018
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2180226138
Short name T765
Test name
Test status
Simulation time 491614557 ps
CPU time 5.28 seconds
Started Jun 05 05:57:33 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 216796 kb
Host smart-66836578-7b24-437b-98c5-cc0a17c8225a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180226138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2180226138
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.395887707
Short name T195
Test name
Test status
Simulation time 123389475064 ps
CPU time 2851.22 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 06:45:14 PM PDT 24
Peak memory 228944 kb
Host smart-933229a0-0ab1-45e3-ada1-dac08aee7572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395887707 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.395887707
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.2057207172
Short name T99
Test name
Test status
Simulation time 56227583 ps
CPU time 1.18 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 215476 kb
Host smart-6c3aa621-e2be-4c96-b3ac-a9dbc4735b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057207172 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.2057207172
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2754432186
Short name T358
Test name
Test status
Simulation time 63045401 ps
CPU time 0.92 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 214580 kb
Host smart-3ab0fa58-efb9-4c81-abf8-8ae4414b308a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754432186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2754432186
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2211578348
Short name T476
Test name
Test status
Simulation time 91269794 ps
CPU time 1.08 seconds
Started Jun 05 05:57:55 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 216740 kb
Host smart-adc83ff4-5ad3-46a9-9af3-cf47ffdc9a49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211578348 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2211578348
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.514055077
Short name T590
Test name
Test status
Simulation time 19136313 ps
CPU time 1.04 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 214996 kb
Host smart-bda68224-40d7-4385-8992-a11faa3754af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514055077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.514055077
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.631692790
Short name T304
Test name
Test status
Simulation time 36511465 ps
CPU time 1.24 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 219272 kb
Host smart-bb4ea202-5741-4df6-b2bf-fec5eb1a25c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631692790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.631692790
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.1506900491
Short name T111
Test name
Test status
Simulation time 36723492 ps
CPU time 0.82 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 215184 kb
Host smart-5158e350-2168-4dd8-aa02-1eeecf268a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506900491 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1506900491
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2428082045
Short name T333
Test name
Test status
Simulation time 18241063 ps
CPU time 0.98 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 215032 kb
Host smart-9594ba51-01ae-49fd-82d7-eeb9495a3bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428082045 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2428082045
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1830432242
Short name T326
Test name
Test status
Simulation time 224077029 ps
CPU time 0.96 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 215048 kb
Host smart-2cf8c2c9-367e-404f-b766-96bd63c213a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830432242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1830432242
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.1149676568
Short name T196
Test name
Test status
Simulation time 27793654070 ps
CPU time 633.43 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 06:08:24 PM PDT 24
Peak memory 217508 kb
Host smart-753b205e-a106-4dbc-93e5-7c8e4573832a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149676568 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.1149676568
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.3677884342
Short name T25
Test name
Test status
Simulation time 70142251 ps
CPU time 1.19 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 215396 kb
Host smart-fb8431cb-14b5-4d09-abae-52074cfcafba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677884342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3677884342
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1886271676
Short name T610
Test name
Test status
Simulation time 58219180 ps
CPU time 1.01 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 214552 kb
Host smart-1a8686cd-e40f-4bca-ad30-633f831b7da5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886271676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1886271676
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3618599913
Short name T711
Test name
Test status
Simulation time 40483345 ps
CPU time 0.82 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 215244 kb
Host smart-a5393c21-fbda-45dd-863c-135370c59690
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618599913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3618599913
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3118573086
Short name T493
Test name
Test status
Simulation time 31368249 ps
CPU time 1.09 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 217672 kb
Host smart-4c191e70-8783-4b88-9882-fde4b7b71684
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118573086 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3118573086
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2584342446
Short name T67
Test name
Test status
Simulation time 22587942 ps
CPU time 1 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:57 PM PDT 24
Peak memory 223452 kb
Host smart-9fe0ea15-4830-4064-941e-1b62c72da60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584342446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2584342446
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.1140113469
Short name T496
Test name
Test status
Simulation time 154615407 ps
CPU time 1.14 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 216832 kb
Host smart-67d409b6-13dc-4e0e-bab6-f48e47b4e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140113469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1140113469
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2785556726
Short name T427
Test name
Test status
Simulation time 25877056 ps
CPU time 0.91 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 214980 kb
Host smart-dea1f58e-eef8-4c30-a0f8-d7ff6da961c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785556726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2785556726
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2108673916
Short name T502
Test name
Test status
Simulation time 26928909 ps
CPU time 1.02 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 214992 kb
Host smart-721e308a-1cca-4925-9139-eac5e71ce31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108673916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2108673916
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3078039595
Short name T332
Test name
Test status
Simulation time 91342728 ps
CPU time 1.14 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 216960 kb
Host smart-ae93dcd3-b6ea-4f00-9639-dcf11c4d9b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078039595 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3078039595
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1481781090
Short name T607
Test name
Test status
Simulation time 129504740505 ps
CPU time 684.11 seconds
Started Jun 05 05:57:30 PM PDT 24
Finished Jun 05 06:08:55 PM PDT 24
Peak memory 221336 kb
Host smart-7078622b-b8c1-497d-b189-e2be7cdc5b27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481781090 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1481781090
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2367432579
Short name T173
Test name
Test status
Simulation time 49147103 ps
CPU time 1.22 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 215300 kb
Host smart-4d55a849-11f5-424a-b587-d044f1b02fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367432579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2367432579
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.914901082
Short name T442
Test name
Test status
Simulation time 19143217 ps
CPU time 1.01 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 205240 kb
Host smart-c4a455bb-005d-4d8a-8824-2587c350b1af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914901082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.914901082
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.449020600
Short name T91
Test name
Test status
Simulation time 21440243 ps
CPU time 0.89 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 216396 kb
Host smart-79a664f1-2608-49a1-a46a-73c369ca400e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449020600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.449020600
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.3906675721
Short name T20
Test name
Test status
Simulation time 22952081 ps
CPU time 0.91 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 219100 kb
Host smart-71e3b779-8ec8-4d84-84b4-386c26877ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906675721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3906675721
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2709590543
Short name T608
Test name
Test status
Simulation time 67961686 ps
CPU time 1.4 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 216732 kb
Host smart-04ac80eb-6a47-4cfd-a399-440cb5df1d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709590543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2709590543
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2607304337
Short name T550
Test name
Test status
Simulation time 21695230 ps
CPU time 1.11 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 215344 kb
Host smart-e137f710-2242-4e66-9abb-0f2bec21d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607304337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2607304337
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1052522311
Short name T712
Test name
Test status
Simulation time 15731682 ps
CPU time 0.92 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 215024 kb
Host smart-57ef0297-bf15-45f5-af3c-edb056f2ab36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052522311 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1052522311
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3018984704
Short name T671
Test name
Test status
Simulation time 111276686 ps
CPU time 1.76 seconds
Started Jun 05 05:57:55 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 215100 kb
Host smart-22e26516-2359-4124-b66f-3d6f318e30b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018984704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3018984704
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3585758814
Short name T845
Test name
Test status
Simulation time 34739860344 ps
CPU time 787.53 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 06:10:48 PM PDT 24
Peak memory 216768 kb
Host smart-89de8c46-5e19-4d6c-9f8e-02288bc5c68b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585758814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3585758814
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.410032957
Short name T740
Test name
Test status
Simulation time 12697319 ps
CPU time 0.88 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 206784 kb
Host smart-bfb70886-3874-4a41-83e5-a9842c092c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410032957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.410032957
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2473355459
Short name T85
Test name
Test status
Simulation time 42962206 ps
CPU time 0.89 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 216096 kb
Host smart-ab5e0b17-10c7-4c71-bb86-f8d83af8a173
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473355459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2473355459
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1364795464
Short name T593
Test name
Test status
Simulation time 20137084 ps
CPU time 0.97 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 216656 kb
Host smart-0cc06f21-56c5-40f9-a9c0-3d5fbac5c993
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364795464 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1364795464
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3825367933
Short name T718
Test name
Test status
Simulation time 22726345 ps
CPU time 0.94 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 217748 kb
Host smart-71c05b69-32cc-4740-a088-841a17fabd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825367933 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3825367933
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3254163834
Short name T415
Test name
Test status
Simulation time 122099545 ps
CPU time 1.14 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 216860 kb
Host smart-ec862152-cf5f-4b6f-85ea-53c42dd6a1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254163834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3254163834
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2218312959
Short name T541
Test name
Test status
Simulation time 20665438 ps
CPU time 1.05 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 215436 kb
Host smart-4bd7a077-3bf5-4231-ad6c-9eee9cdfe12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218312959 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2218312959
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3887547068
Short name T685
Test name
Test status
Simulation time 22902064 ps
CPU time 0.94 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 215036 kb
Host smart-5c5e14aa-6eac-432b-927a-315760f387d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887547068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3887547068
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3164674688
Short name T320
Test name
Test status
Simulation time 281207546 ps
CPU time 3.3 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 216972 kb
Host smart-9e237a5d-32e5-4a9e-92de-27a0b1a577e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164674688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3164674688
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3002476141
Short name T691
Test name
Test status
Simulation time 454597766613 ps
CPU time 1440.3 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 06:21:47 PM PDT 24
Peak memory 222840 kb
Host smart-7fc678bb-5d1c-4316-8415-40749f180ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002476141 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3002476141
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1286808755
Short name T182
Test name
Test status
Simulation time 38215056 ps
CPU time 1.16 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 215408 kb
Host smart-3a67edbf-3168-4383-80f9-b90d6e4f7505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286808755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1286808755
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3721405725
Short name T582
Test name
Test status
Simulation time 61772306 ps
CPU time 0.93 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 206332 kb
Host smart-7888f573-4fe2-4954-b02c-d996f9cd2a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721405725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3721405725
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1629777939
Short name T524
Test name
Test status
Simulation time 56247392 ps
CPU time 0.82 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:41 PM PDT 24
Peak memory 217976 kb
Host smart-a3a02e5b-e586-43f4-9736-9b8539d2f21b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629777939 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1629777939
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.4145403830
Short name T410
Test name
Test status
Simulation time 118024509 ps
CPU time 1.18 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 216488 kb
Host smart-1389d9c5-34df-4831-a27f-1a812c3e29e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145403830 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.4145403830
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.2137789094
Short name T429
Test name
Test status
Simulation time 26130658 ps
CPU time 1.19 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 215236 kb
Host smart-487def3f-5db7-416d-b22b-e1ff69d01735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137789094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.2137789094
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3580807679
Short name T833
Test name
Test status
Simulation time 73135909 ps
CPU time 1.42 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 217856 kb
Host smart-0eb35a35-2e5a-4a22-8343-5f41b1dc3103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580807679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3580807679
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2990137569
Short name T481
Test name
Test status
Simulation time 85745880 ps
CPU time 0.85 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 214924 kb
Host smart-90d815ff-9a4a-4189-9b75-2d6f344896e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990137569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2990137569
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1020589931
Short name T540
Test name
Test status
Simulation time 16330546 ps
CPU time 0.97 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 215036 kb
Host smart-a11a2309-4744-43bd-a664-6d05e4ae0817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020589931 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1020589931
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.335800049
Short name T425
Test name
Test status
Simulation time 351724668 ps
CPU time 4.05 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 215048 kb
Host smart-e2a82693-b5ba-4056-b591-76b1be1f9f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335800049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.335800049
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_alert.1964695832
Short name T430
Test name
Test status
Simulation time 72237003 ps
CPU time 1.12 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215416 kb
Host smart-628a39c1-d5a4-4618-842f-c2a8552d77b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964695832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1964695832
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3803697412
Short name T497
Test name
Test status
Simulation time 37307946 ps
CPU time 0.81 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 206616 kb
Host smart-d85f4d78-2443-4d9a-9885-ec2ac2ff67fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803697412 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3803697412
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2021606735
Short name T70
Test name
Test status
Simulation time 22933402 ps
CPU time 0.89 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 216048 kb
Host smart-fa1d4dca-1bf4-4481-9f6e-ad283e333c18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021606735 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2021606735
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.253817981
Short name T527
Test name
Test status
Simulation time 96002473 ps
CPU time 1.1 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 05:56:46 PM PDT 24
Peak memory 216752 kb
Host smart-de10f4f4-1870-4df8-9852-492e63e7dc06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253817981 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_dis
able_auto_req_mode.253817981
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2690117737
Short name T436
Test name
Test status
Simulation time 23460813 ps
CPU time 1.04 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 223508 kb
Host smart-ed737c98-cb5e-4aac-ba87-40450607117e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690117737 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2690117737
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.887174257
Short name T634
Test name
Test status
Simulation time 25521856 ps
CPU time 1.26 seconds
Started Jun 05 05:56:38 PM PDT 24
Finished Jun 05 05:56:40 PM PDT 24
Peak memory 218760 kb
Host smart-27bdfb4a-b906-4d2f-bc7f-15d3de52b405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887174257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.887174257
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1987720928
Short name T666
Test name
Test status
Simulation time 25389067 ps
CPU time 0.97 seconds
Started Jun 05 05:56:42 PM PDT 24
Finished Jun 05 05:56:44 PM PDT 24
Peak memory 215372 kb
Host smart-e4a78708-def0-4002-b908-59124024f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987720928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1987720928
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.925612714
Short name T745
Test name
Test status
Simulation time 18260387 ps
CPU time 0.98 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 206760 kb
Host smart-7958902b-bb08-4b2d-aa9d-d6f5197fcf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925612714 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.925612714
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.4241043132
Short name T646
Test name
Test status
Simulation time 16876211 ps
CPU time 0.98 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 215064 kb
Host smart-3bbef5a2-97a3-4a75-8b78-a21328d9d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241043132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.4241043132
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3775479884
Short name T676
Test name
Test status
Simulation time 156088252 ps
CPU time 2.1 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 206744 kb
Host smart-8fc66b76-bac3-4766-9597-a43ed8f4268a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775479884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3775479884
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4138339802
Short name T657
Test name
Test status
Simulation time 38628171704 ps
CPU time 529.05 seconds
Started Jun 05 05:56:46 PM PDT 24
Finished Jun 05 06:05:36 PM PDT 24
Peak memory 217752 kb
Host smart-c37ca5ea-1e13-4b18-aa5b-3e62dc9078ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138339802 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4138339802
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3025708093
Short name T49
Test name
Test status
Simulation time 72782432 ps
CPU time 1.17 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 225004 kb
Host smart-23295f35-d427-4706-a4bb-fc7656f3424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025708093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3025708093
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.940086372
Short name T375
Test name
Test status
Simulation time 26956860 ps
CPU time 1.16 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 216900 kb
Host smart-a8bfc12c-e408-4daa-9bf3-e89b694976e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940086372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.940086372
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_genbits.693183805
Short name T713
Test name
Test status
Simulation time 53246900 ps
CPU time 1.23 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 217864 kb
Host smart-7a335f35-098b-40b4-9db4-a3a6375f5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693183805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.693183805
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3281554283
Short name T40
Test name
Test status
Simulation time 91558133 ps
CPU time 1.03 seconds
Started Jun 05 05:57:37 PM PDT 24
Finished Jun 05 05:57:39 PM PDT 24
Peak memory 220228 kb
Host smart-a54da694-a9bc-4811-b8be-59fa032a04cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281554283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3281554283
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2441487789
Short name T317
Test name
Test status
Simulation time 140789106 ps
CPU time 2.71 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 219496 kb
Host smart-eee8a94f-8a59-4673-a6a4-79dca92170ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441487789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2441487789
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1065734655
Short name T36
Test name
Test status
Simulation time 46660339 ps
CPU time 1.01 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 228964 kb
Host smart-344e43d7-af2b-4e20-b4de-4c403bb4de78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065734655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1065734655
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.201042128
Short name T570
Test name
Test status
Simulation time 62938614 ps
CPU time 2 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 218040 kb
Host smart-58582e14-7890-4efd-8c57-7998939017d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201042128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.201042128
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.4260264508
Short name T555
Test name
Test status
Simulation time 26323366 ps
CPU time 1.13 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 218384 kb
Host smart-5b9444af-5899-447b-a084-0191de7e7770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260264508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.4260264508
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2046591429
Short name T394
Test name
Test status
Simulation time 78071160 ps
CPU time 1.33 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 216988 kb
Host smart-1f39615a-731c-404f-99cc-88e7a900ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046591429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2046591429
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.930237549
Short name T89
Test name
Test status
Simulation time 24677194 ps
CPU time 1.03 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 223744 kb
Host smart-9e44641e-aa3e-4e23-903a-bdcff69d12c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930237549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.930237549
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3257798405
Short name T759
Test name
Test status
Simulation time 215226195 ps
CPU time 3.19 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 218336 kb
Host smart-f18fc368-001b-4231-b87b-68bd98d6e831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257798405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3257798405
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1802631981
Short name T65
Test name
Test status
Simulation time 38350028 ps
CPU time 0.85 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 217828 kb
Host smart-10b84ac1-e99c-4aaf-86f8-c20fc0b64f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802631981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1802631981
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1561096501
Short name T545
Test name
Test status
Simulation time 81448001 ps
CPU time 1.01 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 216688 kb
Host smart-a1aa0a93-316a-4f67-8102-03ccfa39d868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561096501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1561096501
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3509728691
Short name T7
Test name
Test status
Simulation time 57841941 ps
CPU time 1.06 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 231556 kb
Host smart-87fdf4d4-8fd2-4e01-b6fd-cefbff575abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509728691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3509728691
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3899247420
Short name T137
Test name
Test status
Simulation time 24614401 ps
CPU time 1.18 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 216676 kb
Host smart-684a3f28-52b6-4840-a2cb-5aa335f82c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899247420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3899247420
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.65105903
Short name T421
Test name
Test status
Simulation time 124750767 ps
CPU time 1.05 seconds
Started Jun 05 05:57:50 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 220524 kb
Host smart-6b589598-8fa0-4307-86a1-0059885ca13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65105903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.65105903
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.70356294
Short name T363
Test name
Test status
Simulation time 70751197 ps
CPU time 0.96 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 215900 kb
Host smart-bb23cdf2-868a-4a3a-9048-290993926c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70356294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.70356294
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2696327989
Short name T514
Test name
Test status
Simulation time 18825105 ps
CPU time 1.01 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218008 kb
Host smart-6b886c52-d630-4757-bb42-094b894b46a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696327989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2696327989
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2830579385
Short name T121
Test name
Test status
Simulation time 259053624 ps
CPU time 2.54 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 216888 kb
Host smart-d9ee4c60-a976-458a-a494-fde5efb55736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830579385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2830579385
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3532612135
Short name T260
Test name
Test status
Simulation time 142907313 ps
CPU time 1.26 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:54 PM PDT 24
Peak memory 215172 kb
Host smart-dedaedb0-0142-450b-8447-f0c4a1f6c48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532612135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3532612135
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2469265191
Short name T594
Test name
Test status
Simulation time 30269824 ps
CPU time 0.91 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 206268 kb
Host smart-8d6338c5-8257-4d09-9d40-3e2089a4d6f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469265191 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2469265191
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3077414778
Short name T21
Test name
Test status
Simulation time 21739130 ps
CPU time 0.86 seconds
Started Jun 05 05:56:50 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 216216 kb
Host smart-98804d64-2d30-43d9-8fbb-f49d89c09fe5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077414778 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3077414778
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.3296749164
Short name T46
Test name
Test status
Simulation time 41639186 ps
CPU time 1.1 seconds
Started Jun 05 05:56:59 PM PDT 24
Finished Jun 05 05:57:01 PM PDT 24
Peak memory 215020 kb
Host smart-c334d928-94ac-4de6-9ec2-251a2f18fea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296749164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3296749164
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3470542006
Short name T599
Test name
Test status
Simulation time 33909085 ps
CPU time 1.3 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 219432 kb
Host smart-d916c957-deb5-4aa6-96e1-446fd789b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470542006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3470542006
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.2531824951
Short name T106
Test name
Test status
Simulation time 19315241 ps
CPU time 1.08 seconds
Started Jun 05 05:57:01 PM PDT 24
Finished Jun 05 05:57:03 PM PDT 24
Peak memory 206896 kb
Host smart-f98b4091-e89c-44e9-9675-8b28dc55d5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531824951 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2531824951
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.2037678732
Short name T597
Test name
Test status
Simulation time 18711257 ps
CPU time 1.05 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 214984 kb
Host smart-bf739bbf-f3a5-4eb9-a44a-e3ae5ab58ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037678732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2037678732
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3390147620
Short name T202
Test name
Test status
Simulation time 282008726 ps
CPU time 5.38 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215064 kb
Host smart-8c19929d-d0e9-46d2-b4db-b30f7e1329f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390147620 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3390147620
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.4014694288
Short name T440
Test name
Test status
Simulation time 39183337915 ps
CPU time 297.93 seconds
Started Jun 05 05:56:44 PM PDT 24
Finished Jun 05 06:01:43 PM PDT 24
Peak memory 217720 kb
Host smart-5d7447a7-822d-4a25-ad0e-50aab6f66c88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014694288 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.4014694288
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.803746941
Short name T655
Test name
Test status
Simulation time 32450278 ps
CPU time 0.99 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 217868 kb
Host smart-f4115cd2-2148-4184-96b3-19e1cbc305bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803746941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.803746941
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2524334525
Short name T789
Test name
Test status
Simulation time 57088120 ps
CPU time 1.41 seconds
Started Jun 05 05:57:55 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 218156 kb
Host smart-901a500e-9d05-43f2-8ab8-47f1ce1c5827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524334525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2524334525
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.650255532
Short name T564
Test name
Test status
Simulation time 28680164 ps
CPU time 0.86 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 218196 kb
Host smart-9b3a4751-cc5c-4115-8d5b-060103f796d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650255532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.650255532
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1662211623
Short name T504
Test name
Test status
Simulation time 37731808 ps
CPU time 1.33 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 218120 kb
Host smart-38387a12-b8d5-428b-a931-7dc41285367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662211623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1662211623
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1493249204
Short name T602
Test name
Test status
Simulation time 20137003 ps
CPU time 1.1 seconds
Started Jun 05 05:57:53 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 219540 kb
Host smart-7de161a1-16ff-4736-9dcc-5a6304b13da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493249204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1493249204
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2757431504
Short name T704
Test name
Test status
Simulation time 41887467 ps
CPU time 1.18 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 218200 kb
Host smart-2ed5bab3-3efd-4e00-91b2-1de970e09d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757431504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2757431504
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.4194464582
Short name T66
Test name
Test status
Simulation time 22041306 ps
CPU time 1.02 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 223524 kb
Host smart-fd6dadb3-9e1e-48a1-adcb-764cc455f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194464582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.4194464582
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.400031403
Short name T283
Test name
Test status
Simulation time 32908313 ps
CPU time 1.16 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:54 PM PDT 24
Peak memory 217912 kb
Host smart-c3a5bd5e-ee7a-40fb-a545-9bd70dfb4a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400031403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.400031403
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4243392132
Short name T5
Test name
Test status
Simulation time 25530643 ps
CPU time 0.94 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 219036 kb
Host smart-465b3d71-a92b-4f53-816d-46bf5db50be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243392132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4243392132
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1904745104
Short name T321
Test name
Test status
Simulation time 27481486 ps
CPU time 1.16 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 216676 kb
Host smart-59c3c971-1f9a-40af-8f8b-139d3961218f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904745104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1904745104
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_genbits.1442983550
Short name T302
Test name
Test status
Simulation time 65711750 ps
CPU time 1.13 seconds
Started Jun 05 05:57:55 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 219484 kb
Host smart-6c549846-607d-48c0-9e61-3bb9220a17da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442983550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1442983550
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3403986947
Short name T74
Test name
Test status
Simulation time 20648063 ps
CPU time 1.04 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218016 kb
Host smart-f8d2d6d3-db8f-4f4f-97a4-61e9b6ec8e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403986947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3403986947
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3802896488
Short name T240
Test name
Test status
Simulation time 39679819 ps
CPU time 1.29 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 216876 kb
Host smart-8f2ce4f7-70f9-43c7-a1b6-9ce5ac3e4426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802896488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3802896488
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2998504052
Short name T62
Test name
Test status
Simulation time 22367608 ps
CPU time 1.06 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 218112 kb
Host smart-03ea3773-4629-4be8-af8b-0b2fd48f84a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998504052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2998504052
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3038641658
Short name T343
Test name
Test status
Simulation time 44262625 ps
CPU time 1.41 seconds
Started Jun 05 05:57:41 PM PDT 24
Finished Jun 05 05:57:44 PM PDT 24
Peak memory 218880 kb
Host smart-73a9f75b-418d-406d-9b66-e5b201871c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038641658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3038641658
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_genbits.623414255
Short name T584
Test name
Test status
Simulation time 60795526 ps
CPU time 1.37 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 218120 kb
Host smart-93335167-c0b0-43b3-8d17-04ead38da2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623414255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.623414255
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1001855569
Short name T155
Test name
Test status
Simulation time 18446302 ps
CPU time 1.08 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 218520 kb
Host smart-d5f55013-fd99-432f-9ab5-0f9c3781bb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001855569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1001855569
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2425768667
Short name T19
Test name
Test status
Simulation time 83714800 ps
CPU time 3.07 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 219640 kb
Host smart-1ec67aa1-40f1-46c2-9256-d606c0c0f536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425768667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2425768667
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1043723554
Short name T680
Test name
Test status
Simulation time 32117864 ps
CPU time 1.27 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 215404 kb
Host smart-cc7a26ac-3846-4f30-9fcf-a2776cc6656c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043723554 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1043723554
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.4045209732
Short name T420
Test name
Test status
Simulation time 21221125 ps
CPU time 1.06 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 206400 kb
Host smart-0d12a64c-eea7-4f14-8d3a-2b3901608a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045209732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4045209732
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.463083100
Short name T553
Test name
Test status
Simulation time 12006141 ps
CPU time 0.94 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 215372 kb
Host smart-5bff27ac-be41-46b1-8236-3121d5abfe8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463083100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.463083100
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.2184805215
Short name T379
Test name
Test status
Simulation time 100724411 ps
CPU time 0.99 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 219276 kb
Host smart-2c49849b-8196-49da-b035-38a4c9a6544d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184805215 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.2184805215
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2533553337
Short name T164
Test name
Test status
Simulation time 46433330 ps
CPU time 0.87 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 218080 kb
Host smart-0425bd05-c77c-4f38-bdc1-0af6d7809e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533553337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2533553337
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3183011743
Short name T270
Test name
Test status
Simulation time 34561286 ps
CPU time 1.56 seconds
Started Jun 05 05:57:00 PM PDT 24
Finished Jun 05 05:57:02 PM PDT 24
Peak memory 216812 kb
Host smart-0a6bb7ea-a6b3-483f-b5e1-d688fcae8279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183011743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3183011743
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.880621054
Short name T683
Test name
Test status
Simulation time 86769277 ps
CPU time 0.85 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 215140 kb
Host smart-57e8a687-8883-4894-ae2b-e15acead4dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880621054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.880621054
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.2151568209
Short name T547
Test name
Test status
Simulation time 16980258 ps
CPU time 0.96 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 215048 kb
Host smart-6b728cfa-ced3-4078-a1f5-9dab5c0a059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151568209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2151568209
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.986212554
Short name T103
Test name
Test status
Simulation time 789516553 ps
CPU time 4.21 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 219060 kb
Host smart-6c696735-7c03-48ea-89fe-fda5cfef684f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986212554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.986212554
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.727733996
Short name T500
Test name
Test status
Simulation time 85937102643 ps
CPU time 1107.63 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 06:15:35 PM PDT 24
Peak memory 223476 kb
Host smart-b4b82180-1fbb-4f84-973f-fb67063c8596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727733996 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.727733996
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2373977856
Short name T434
Test name
Test status
Simulation time 58780193 ps
CPU time 1.02 seconds
Started Jun 05 05:57:55 PM PDT 24
Finished Jun 05 05:57:57 PM PDT 24
Peak memory 218088 kb
Host smart-4a821dee-a577-48e6-a8d4-c2bb95c9a8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373977856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2373977856
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2410976980
Short name T637
Test name
Test status
Simulation time 29591498 ps
CPU time 1.21 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 219356 kb
Host smart-cd4bceac-b588-4563-9aae-760074751caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410976980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2410976980
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2432362970
Short name T45
Test name
Test status
Simulation time 20172464 ps
CPU time 1.21 seconds
Started Jun 05 05:58:02 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 229056 kb
Host smart-edcdb47f-1fe4-48dd-a7ca-ad03970e2f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432362970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2432362970
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.806246285
Short name T359
Test name
Test status
Simulation time 20804914 ps
CPU time 1.12 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 219396 kb
Host smart-42b1b50e-fb64-4c5c-aafe-a6d734096af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806246285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.806246285
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1511707904
Short name T52
Test name
Test status
Simulation time 40123183 ps
CPU time 1.14 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:02 PM PDT 24
Peak memory 220268 kb
Host smart-d7006171-48dc-4220-a009-6bf28a97eee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511707904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1511707904
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.519024255
Short name T603
Test name
Test status
Simulation time 36351491 ps
CPU time 1.56 seconds
Started Jun 05 05:57:57 PM PDT 24
Finished Jun 05 05:58:00 PM PDT 24
Peak memory 219912 kb
Host smart-2d0c56d6-dcb7-4390-a5de-5fb257ab279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519024255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.519024255
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2251788013
Short name T815
Test name
Test status
Simulation time 26623452 ps
CPU time 0.96 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 228876 kb
Host smart-3f5421ad-710a-404c-ab23-fe98160e59bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251788013 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2251788013
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4200761928
Short name T404
Test name
Test status
Simulation time 37142260 ps
CPU time 1.31 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 216860 kb
Host smart-eb443e7f-807d-40da-a7b8-ee6f53a8748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200761928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4200761928
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.675928417
Short name T104
Test name
Test status
Simulation time 20056654 ps
CPU time 1.11 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 219124 kb
Host smart-916006d9-61f2-4eb0-aa52-ee8582f60176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675928417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.675928417
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.731185291
Short name T495
Test name
Test status
Simulation time 89804365 ps
CPU time 1.31 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 218096 kb
Host smart-805566c7-7ee2-4d66-86cb-071e706faf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731185291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.731185291
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.253070453
Short name T810
Test name
Test status
Simulation time 18181032 ps
CPU time 1 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 218004 kb
Host smart-5e8d488f-3f34-435f-ab11-711fe8ecb22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253070453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.253070453
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.250114971
Short name T301
Test name
Test status
Simulation time 40628224 ps
CPU time 1.59 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 216904 kb
Host smart-a803ec5f-ae25-4cac-abd7-1012b36741ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250114971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.250114971
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2253363021
Short name T170
Test name
Test status
Simulation time 18560964 ps
CPU time 1.06 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 217928 kb
Host smart-cecd9109-cf4b-43df-bf87-cf7160f08718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253363021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2253363021
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1308061273
Short name T486
Test name
Test status
Simulation time 119310135 ps
CPU time 1.07 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 216792 kb
Host smart-1cdc6d9c-3038-46a2-992f-bbf5bd9fbdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308061273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1308061273
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3070645837
Short name T12
Test name
Test status
Simulation time 30136944 ps
CPU time 0.95 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 223284 kb
Host smart-ce1e8887-e7ba-4973-8bf4-e13b69fb7f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070645837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3070645837
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2167222732
Short name T300
Test name
Test status
Simulation time 46071092 ps
CPU time 1.06 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 218096 kb
Host smart-33d142c6-2e7c-47b5-a760-c2e43b3feb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167222732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2167222732
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.14475792
Short name T82
Test name
Test status
Simulation time 20768045 ps
CPU time 1.24 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 223480 kb
Host smart-82a37593-0209-4b4e-a575-1d7478b563f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14475792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.14475792
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2652782767
Short name T668
Test name
Test status
Simulation time 89849497 ps
CPU time 1.15 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 219400 kb
Host smart-f15d6a0e-2a2f-4299-bd19-d5f5b30323b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652782767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2652782767
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2528653190
Short name T90
Test name
Test status
Simulation time 19441148 ps
CPU time 1.16 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 223472 kb
Host smart-3b0aa3ab-8767-4a88-9e41-e0fbd78eec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528653190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2528653190
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert_test.1144622234
Short name T503
Test name
Test status
Simulation time 19070070 ps
CPU time 0.99 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 206352 kb
Host smart-f8434e18-9c98-4462-939d-4ce38b39d702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144622234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.1144622234
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.911124915
Short name T621
Test name
Test status
Simulation time 11147141 ps
CPU time 0.89 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 216240 kb
Host smart-c82b8c50-acab-449c-8add-75ae482e1d4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911124915 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.911124915
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3215327373
Short name T60
Test name
Test status
Simulation time 63068781 ps
CPU time 1.18 seconds
Started Jun 05 05:56:53 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 216720 kb
Host smart-c32937f2-d144-4614-8751-afa828e197d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215327373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3215327373
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3619646956
Short name T75
Test name
Test status
Simulation time 20348878 ps
CPU time 0.93 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 215008 kb
Host smart-9ebad6bb-d70d-4c0b-b191-81784715f936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619646956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3619646956
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.3500016325
Short name T585
Test name
Test status
Simulation time 19897959 ps
CPU time 1.08 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 215360 kb
Host smart-43eebf55-7449-4d38-bb97-27bbad294005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500016325 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3500016325
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.4125324559
Short name T557
Test name
Test status
Simulation time 44887714 ps
CPU time 0.93 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 05:56:49 PM PDT 24
Peak memory 206832 kb
Host smart-2d00f76c-5eec-4324-a17b-b6574f3a822e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125324559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4125324559
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2438176992
Short name T336
Test name
Test status
Simulation time 53416082 ps
CPU time 0.9 seconds
Started Jun 05 05:56:58 PM PDT 24
Finished Jun 05 05:57:00 PM PDT 24
Peak memory 215036 kb
Host smart-5ecef696-60d1-46e5-9c8f-59bc9c513eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438176992 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2438176992
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2558278280
Short name T445
Test name
Test status
Simulation time 554432952 ps
CPU time 2.12 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:52 PM PDT 24
Peak memory 215052 kb
Host smart-8ad40cd4-6df6-4f96-b549-af3779a75b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558278280 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2558278280
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3856279402
Short name T667
Test name
Test status
Simulation time 90112353809 ps
CPU time 1117.09 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 06:15:27 PM PDT 24
Peak memory 224220 kb
Host smart-327694be-c500-4562-beaa-28ea7a25edc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856279402 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3856279402
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.3340123286
Short name T29
Test name
Test status
Simulation time 24264040 ps
CPU time 1.22 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 229104 kb
Host smart-856fce42-6c02-43e5-8868-ce6d2a89e7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340123286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3340123286
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4097810967
Short name T489
Test name
Test status
Simulation time 61975802 ps
CPU time 1.62 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 217976 kb
Host smart-f41fcd47-c153-45e4-9d9d-edb385e14c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097810967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4097810967
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2805920449
Short name T157
Test name
Test status
Simulation time 37550542 ps
CPU time 1.24 seconds
Started Jun 05 05:58:03 PM PDT 24
Finished Jun 05 05:58:04 PM PDT 24
Peak memory 219180 kb
Host smart-c9f343ec-6277-4233-9a05-ecde12510b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805920449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2805920449
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3008088183
Short name T742
Test name
Test status
Simulation time 84861061 ps
CPU time 2.65 seconds
Started Jun 05 05:58:06 PM PDT 24
Finished Jun 05 05:58:09 PM PDT 24
Peak memory 218052 kb
Host smart-b09b4151-7a58-48ab-9a94-a210eb9dfc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008088183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3008088183
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.732107111
Short name T840
Test name
Test status
Simulation time 20204990 ps
CPU time 1.09 seconds
Started Jun 05 05:58:15 PM PDT 24
Finished Jun 05 05:58:16 PM PDT 24
Peak memory 219336 kb
Host smart-a59809c7-3028-4008-91c4-b876eec85092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732107111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.732107111
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3685997570
Short name T811
Test name
Test status
Simulation time 40703483 ps
CPU time 1.73 seconds
Started Jun 05 05:57:43 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 219508 kb
Host smart-bfd6756e-7c3a-44f3-a9fd-678451717470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685997570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3685997570
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1787207882
Short name T472
Test name
Test status
Simulation time 20222527 ps
CPU time 0.9 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 217716 kb
Host smart-19d5dbc9-ae5e-45f3-a67c-2a6b3296231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787207882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1787207882
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2488122278
Short name T454
Test name
Test status
Simulation time 40112185 ps
CPU time 1.15 seconds
Started Jun 05 05:57:58 PM PDT 24
Finished Jun 05 05:58:00 PM PDT 24
Peak memory 216772 kb
Host smart-c35dcfe4-ce62-4ba4-86d9-65ae2c4071d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488122278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2488122278
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.311095021
Short name T645
Test name
Test status
Simulation time 20509649 ps
CPU time 1.14 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:50 PM PDT 24
Peak memory 219332 kb
Host smart-dce6a335-3fee-429c-863b-fa8aafa6c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311095021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.311095021
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2615506771
Short name T800
Test name
Test status
Simulation time 108558651 ps
CPU time 1.28 seconds
Started Jun 05 05:58:04 PM PDT 24
Finished Jun 05 05:58:06 PM PDT 24
Peak memory 216624 kb
Host smart-18791e21-ef09-437a-8581-0f66f4fa6a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615506771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2615506771
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3444692481
Short name T68
Test name
Test status
Simulation time 32657065 ps
CPU time 0.83 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 217908 kb
Host smart-3f10f4aa-bdac-4dc6-abec-583eb0135b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444692481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3444692481
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3368761359
Short name T382
Test name
Test status
Simulation time 95234344 ps
CPU time 1.03 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 216952 kb
Host smart-d3980944-778d-4f41-b347-78801054124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368761359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3368761359
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3081290859
Short name T95
Test name
Test status
Simulation time 32014787 ps
CPU time 0.82 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 217844 kb
Host smart-443b5d45-ea2b-48a4-899a-048d1feb3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081290859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3081290859
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1766191497
Short name T733
Test name
Test status
Simulation time 168241616 ps
CPU time 1.3 seconds
Started Jun 05 05:57:40 PM PDT 24
Finished Jun 05 05:57:43 PM PDT 24
Peak memory 216644 kb
Host smart-6aec8d40-d222-4912-a51d-f45f43da475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766191497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1766191497
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.814750673
Short name T96
Test name
Test status
Simulation time 28876263 ps
CPU time 1.01 seconds
Started Jun 05 05:57:39 PM PDT 24
Finished Jun 05 05:57:42 PM PDT 24
Peak memory 218208 kb
Host smart-f0e7a71c-e9f8-4f94-be2e-cb78fb37a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814750673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.814750673
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2839314811
Short name T739
Test name
Test status
Simulation time 36457387 ps
CPU time 1.34 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:52 PM PDT 24
Peak memory 216868 kb
Host smart-abad27fe-cbe9-492d-b805-3d20e561e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839314811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2839314811
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.824016132
Short name T162
Test name
Test status
Simulation time 24880753 ps
CPU time 0.95 seconds
Started Jun 05 05:57:47 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218296 kb
Host smart-ce96ffd8-e7f3-4b8e-a43e-8deded9482ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824016132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.824016132
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1047337337
Short name T561
Test name
Test status
Simulation time 81073088 ps
CPU time 1.46 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 217908 kb
Host smart-0c65bcf7-b9ae-4cdb-9445-aa7c9cef19dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047337337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1047337337
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.678501524
Short name T690
Test name
Test status
Simulation time 29195076 ps
CPU time 0.91 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 218316 kb
Host smart-c4516f20-8bee-47c8-a4fe-441d6c34c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678501524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.678501524
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3731607080
Short name T694
Test name
Test status
Simulation time 44291731 ps
CPU time 1.49 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 218096 kb
Host smart-90e59b20-7d8a-476a-a97f-663a93728a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731607080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3731607080
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1925130304
Short name T703
Test name
Test status
Simulation time 197251823 ps
CPU time 1.36 seconds
Started Jun 05 05:56:52 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 215324 kb
Host smart-9405cc76-d6a5-4253-9459-33d1d4b4fbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925130304 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1925130304
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.3145088020
Short name T687
Test name
Test status
Simulation time 43324519 ps
CPU time 0.91 seconds
Started Jun 05 05:56:57 PM PDT 24
Finished Jun 05 05:56:59 PM PDT 24
Peak memory 214940 kb
Host smart-118f4a53-4334-4f10-86af-277d68b25de8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145088020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.3145088020
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1798112585
Short name T605
Test name
Test status
Simulation time 11047777 ps
CPU time 0.85 seconds
Started Jun 05 05:56:45 PM PDT 24
Finished Jun 05 05:56:47 PM PDT 24
Peak memory 216096 kb
Host smart-4afe0697-15a8-48e6-a33d-588f6054f94b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798112585 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1798112585
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3564911295
Short name T391
Test name
Test status
Simulation time 32845955 ps
CPU time 1.08 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 218044 kb
Host smart-a3dac12b-ee3d-435a-8adc-ffe0fac48661
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564911295 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3564911295
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1328281433
Short name T835
Test name
Test status
Simulation time 36048428 ps
CPU time 0.86 seconds
Started Jun 05 05:56:55 PM PDT 24
Finished Jun 05 05:56:57 PM PDT 24
Peak memory 218192 kb
Host smart-0d7c9af2-1a51-4d72-8516-42dee7567606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328281433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1328281433
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3640636495
Short name T324
Test name
Test status
Simulation time 80709378 ps
CPU time 1.11 seconds
Started Jun 05 05:56:56 PM PDT 24
Finished Jun 05 05:56:58 PM PDT 24
Peak memory 216580 kb
Host smart-485183d4-49dd-4221-bc14-22b0a47c4d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640636495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3640636495
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2100234998
Short name T834
Test name
Test status
Simulation time 22488207 ps
CPU time 1.06 seconds
Started Jun 05 05:56:49 PM PDT 24
Finished Jun 05 05:56:51 PM PDT 24
Peak memory 215360 kb
Host smart-7d56a52b-dcd2-4a80-bf3c-caff66aa905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100234998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2100234998
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1378476915
Short name T108
Test name
Test status
Simulation time 44303425 ps
CPU time 0.9 seconds
Started Jun 05 05:56:51 PM PDT 24
Finished Jun 05 05:56:53 PM PDT 24
Peak memory 206852 kb
Host smart-db1261e5-d748-4dc4-8e99-e4c0cc3e63c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378476915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1378476915
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2464281995
Short name T501
Test name
Test status
Simulation time 43774581 ps
CPU time 0.9 seconds
Started Jun 05 05:57:07 PM PDT 24
Finished Jun 05 05:57:09 PM PDT 24
Peak memory 215032 kb
Host smart-78ce8c7a-9719-4ea1-85d5-681d2cc508bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464281995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2464281995
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.281294439
Short name T572
Test name
Test status
Simulation time 784089226 ps
CPU time 5.11 seconds
Started Jun 05 05:56:48 PM PDT 24
Finished Jun 05 05:56:55 PM PDT 24
Peak memory 216800 kb
Host smart-04d07bea-bbdf-4b18-8012-359df994cda2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281294439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.281294439
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2784702703
Short name T200
Test name
Test status
Simulation time 169982088117 ps
CPU time 756.39 seconds
Started Jun 05 05:56:47 PM PDT 24
Finished Jun 05 06:09:30 PM PDT 24
Peak memory 219696 kb
Host smart-9f9bc3c5-2c03-4cc9-abe3-527d5aa77c4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784702703 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2784702703
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1291170800
Short name T6
Test name
Test status
Simulation time 21119087 ps
CPU time 1.25 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 219580 kb
Host smart-f1ad68e3-9cdb-4999-8dd9-9d006e266f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291170800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1291170800
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.757809114
Short name T313
Test name
Test status
Simulation time 21646670 ps
CPU time 1.17 seconds
Started Jun 05 05:58:05 PM PDT 24
Finished Jun 05 05:58:17 PM PDT 24
Peak memory 216848 kb
Host smart-0a7a2d94-6c5b-4ed5-9a3e-629f89f753b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757809114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.757809114
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3762130271
Short name T43
Test name
Test status
Simulation time 48738183 ps
CPU time 0.96 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:48 PM PDT 24
Peak memory 219312 kb
Host smart-32b32556-6642-4220-9c97-fef0b0018c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762130271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3762130271
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/92.edn_err.3116498722
Short name T87
Test name
Test status
Simulation time 18600178 ps
CPU time 1.16 seconds
Started Jun 05 05:57:51 PM PDT 24
Finished Jun 05 05:57:53 PM PDT 24
Peak memory 223516 kb
Host smart-86740866-cbf5-4654-b5e9-9c71acc0df4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116498722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3116498722
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.940495635
Short name T746
Test name
Test status
Simulation time 224664789 ps
CPU time 1.46 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218700 kb
Host smart-c6dc7da8-2b16-49ee-969a-2e3f874c8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940495635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.940495635
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2326764761
Short name T724
Test name
Test status
Simulation time 54696348 ps
CPU time 1 seconds
Started Jun 05 05:57:44 PM PDT 24
Finished Jun 05 05:57:46 PM PDT 24
Peak memory 219464 kb
Host smart-06a9d18b-afc7-4736-878a-271de9c804df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326764761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2326764761
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3578317920
Short name T532
Test name
Test status
Simulation time 61018699 ps
CPU time 1.1 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 218772 kb
Host smart-f189e270-be83-434c-acdc-b3a9cc5c775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578317920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3578317920
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1927396553
Short name T531
Test name
Test status
Simulation time 19908814 ps
CPU time 1.08 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:02 PM PDT 24
Peak memory 218156 kb
Host smart-ad85fb15-d70d-4d38-9cae-81f86d4caaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927396553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1927396553
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.110166702
Short name T350
Test name
Test status
Simulation time 89258546 ps
CPU time 2.85 seconds
Started Jun 05 05:57:54 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 216976 kb
Host smart-f43f9668-e03d-48f9-8d49-4520c12b1932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110166702 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.110166702
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2844904853
Short name T42
Test name
Test status
Simulation time 20774455 ps
CPU time 1.25 seconds
Started Jun 05 05:57:46 PM PDT 24
Finished Jun 05 05:57:49 PM PDT 24
Peak memory 229104 kb
Host smart-16ead8be-fce3-4e78-aeb7-e343b7691a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844904853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2844904853
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.499993823
Short name T693
Test name
Test status
Simulation time 141262984 ps
CPU time 1.34 seconds
Started Jun 05 05:57:42 PM PDT 24
Finished Jun 05 05:57:45 PM PDT 24
Peak memory 219348 kb
Host smart-e62cee63-9202-4de2-ad5f-26addd5be281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499993823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.499993823
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.693451973
Short name T604
Test name
Test status
Simulation time 24336620 ps
CPU time 0.94 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:55 PM PDT 24
Peak memory 219072 kb
Host smart-896e9f33-5e58-42c7-a9bc-b718bcb48648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693451973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.693451973
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1689668119
Short name T837
Test name
Test status
Simulation time 57336728 ps
CPU time 1.21 seconds
Started Jun 05 05:57:45 PM PDT 24
Finished Jun 05 05:57:47 PM PDT 24
Peak memory 216744 kb
Host smart-55c53aec-ca5c-49c9-9415-4ab7b2ecb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689668119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1689668119
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2882725678
Short name T23
Test name
Test status
Simulation time 18771086 ps
CPU time 1.09 seconds
Started Jun 05 05:57:48 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 218148 kb
Host smart-4d95ec52-ed95-4bd0-875c-10a7864cc2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882725678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2882725678
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.453701169
Short name T292
Test name
Test status
Simulation time 26340044 ps
CPU time 1.21 seconds
Started Jun 05 05:57:56 PM PDT 24
Finished Jun 05 05:57:58 PM PDT 24
Peak memory 219224 kb
Host smart-873a4639-54bf-4708-8a16-f27b5d61c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453701169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.453701169
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.164221655
Short name T747
Test name
Test status
Simulation time 52262090 ps
CPU time 1.01 seconds
Started Jun 05 05:57:49 PM PDT 24
Finished Jun 05 05:57:51 PM PDT 24
Peak memory 223500 kb
Host smart-63947d99-e0f2-46e0-8e47-b4f5cbb5143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164221655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.164221655
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.233474668
Short name T766
Test name
Test status
Simulation time 310137468 ps
CPU time 2.03 seconds
Started Jun 05 05:57:52 PM PDT 24
Finished Jun 05 05:57:56 PM PDT 24
Peak memory 218480 kb
Host smart-8d5d3526-6fc7-4c6f-925e-575987320dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233474668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.233474668
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1377728475
Short name T83
Test name
Test status
Simulation time 30177789 ps
CPU time 0.97 seconds
Started Jun 05 05:58:00 PM PDT 24
Finished Jun 05 05:58:01 PM PDT 24
Peak memory 223372 kb
Host smart-27aebd89-b65d-4b2b-92b3-1b594b6d92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377728475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1377728475
Directory /workspace/99.edn_err/latest
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