Unified Coverage Report :: Cond split page

Go back

 LINE       295
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode)
             ------------1------------    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T23,T24,T26
1	1	Covered	T1,T3,T6

 LINE       300
 EXPRESSION (sfifo_rescmd_int_err || sfifo_gencmd_int_err || edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             ----------1---------    ----------2---------    --------3-------    ---------4---------    ---------5--------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T16,T36,T8
0	0	0	1	0	Covered	T16,T7,T9
0	0	1	0	0	Covered	T16,T17,T18
0	1	0	0	0	Covered	T16,T19,T20
1	0	0	0	0	Covered	T16,T19,T20

 LINE       307
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T36
1	0	Covered	T33,T34,T35

 LINE       307
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T33,T34
1	0	Covered	T1,T3,T6
1	1	Covered	T16,T33,T34

 LINE       307
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T35,T19
1	0	Covered	T16,T33,T34

 LINE       313
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T33,T34

 LINE       315
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T35,T19

 LINE       317
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T36

 LINE       319
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T36

 LINE       321
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       324
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T37,T38,T39
1	0	0	Covered	T79

 LINE       328
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T40,T41,T78
1	0	0	Covered	T34,T77

 LINE       332
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T16,T35,T19
1	0	0	Covered	T16,T33,T19

 LINE       340
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T33,T34
1	0	Covered	T1,T3,T6
1	1	Covered	T16,T33,T34

 LINE       343
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T35,T19
1	0	Covered	T1,T3,T6
1	1	Covered	T16,T35,T19

 LINE       360
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T37,T38,T39
1	0	Covered	T1,T3,T6
1	1	Covered	T37,T38,T39

 LINE       363
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T34,T40,T41
1	0	Covered	T1,T3,T6
1	1	Covered	T34,T40,T41

 LINE       366
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T16,T33,T35
1	0	Covered	T1,T3,T6
1	1	Covered	T16,T33,T35

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T26
1	0	Covered	T1,T24,T42
1	1	Covered	T1,T24,T42

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T24,T42

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T42,T43,T66
1	1	Covered	T42,T43,T66

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T42,T43,T66

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T65,T80,T66
1	1	Covered	T65,T80,T66

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T65,T80,T66

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T64,T42
1	1	Covered	T1,T64,T42

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T64,T42

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T65,T66
1	1	Covered	T1,T65,T66

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T65,T66

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T26,T5
1	1	Covered	T1,T26,T5

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T26,T5

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T5,T17
1	1	Covered	T1,T5,T17

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T17

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T43,T81,T71
1	1	Covered	T43,T81,T71

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T43,T81,T71

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T7,T43
1	1	Covered	T1,T7,T43

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T43

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T27,T5
1	1	Covered	T1,T27,T5

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T27,T5

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T26
1	0	Covered	T1,T23,T46
1	1	Covered	T1,T23,T46

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T46

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T64,T17
1	1	Covered	T1,T64,T17

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T64,T17

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T61,T43,T48
1	1	Covered	T61,T43,T48

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T61,T43,T48

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T42,T61
1	1	Covered	T1,T42,T61

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T42,T61

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T42,T50
1	1	Covered	T1,T42,T50

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T42,T50

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T5,T61
1	1	Covered	T1,T5,T61

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T61

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T45,T47,T43
1	1	Covered	T45,T47,T43

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T45,T47,T43

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T68,T42
1	1	Covered	T1,T68,T42

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T68,T42

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T5,T11,T75
1	1	Covered	T5,T11,T75

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T11,T75

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T64,T42,T7
1	1	Covered	T64,T42,T7

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T42,T7

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T1,T42,T81
1	1	Covered	T1,T42,T81

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T42,T81

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T64,T43,T66
1	1	Covered	T64,T43,T66

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T43,T66

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Covered	T64,T42,T61
1	1	Covered	T64,T42,T61

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T64,T42,T61

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       371
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T23,T24
1	0	Not Covered
1	1	Not Covered

 LINE       371
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       375
 EXPRESSION (edn_enable_fo[CsrngAckErr] && csrng_cmd_i.csrng_rsp_ack && (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS))
             -------------1------------    ------------2------------    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T82,T83,T54
1	0	1	Not Covered
1	1	0	Covered	T1,T3,T6
1	1	1	Covered	T11,T31,T32

 LINE       375
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T31,T32

 LINE       381
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa || csrng_ack_err)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------    ------6------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Covered	T11,T31,T32
0	0	0	0	1	0	Covered	T82,T83,T84
0	0	0	1	0	0	Covered	T11,T85,T86
0	0	1	0	0	0	Covered	T54,T87,T88
0	1	0	0	0	0	Covered	T31,T32,T89
1	0	0	0	0	0	Covered	T11,T31,T32

 LINE       400
 EXPRESSION (event_edn_fatal_err || sfifo_rescmd_int_err || sfifo_gencmd_int_err)
             ---------1---------    ----------2---------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T16,T17,T36

 LINE       403
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T90,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T90,T91

 LINE       407
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T90,T91
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T90,T91

 LINE       483
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T10,T21,T22
1	1	Covered	T1,T3,T6

 LINE       495
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       496
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T6
1	1	Covered	T10,T11,T12

 LINE       497
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T6
1	1	Covered	T10,T12,T21

 LINE       500
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       500
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       500
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       500
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T27

 LINE       500
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       509
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       509
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       509
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       509
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T3,T6
0	0	0	1	Covered	T23,T24,T27
0	0	1	0	Covered	T23,T24,T26
0	1	0	0	Covered	T23,T24,T26
1	0	0	0	Covered	T1,T3,T6

 LINE       516
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       520
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       520
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       520
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T12,T21

 LINE       520
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T10,T12,T21
1	Covered	T10,T11,T12

 LINE       520
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       520
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       520
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T10,T11,T12
1	Covered	T10,T11,T12

 LINE       520
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       520
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       536
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       536
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       536
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       536
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T12,T21

 LINE       536
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       536
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       536
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       544
 EXPRESSION (cs_cmd_req_vld_out_q && ((!reject_csrng_entropy)))
             ----------1---------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T82,T83,T84
1	1	Covered	T1,T3,T6

 LINE       551
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T82,T83,T85
1	1	1	Covered	T1,T3,T6

 LINE       555
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       555
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       555
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Not Covered

 LINE       555
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       555
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       555
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       567
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       567
 SUB-EXPRESSION 
 Number  Term
      1  ((!sw_cmd_mode)) ? 1'b0 : (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       567
 SUB-EXPRESSION (reject_csrng_entropy ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Not Covered

 LINE       567
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       567
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       567
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       579
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       579
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       579
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy)))
                 ------------1------------    -----2-----    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T23,T24,T26
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       588
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       588
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       588
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy))) ? 1'b1 : csrng_sw_cmd_ack_q)
                 -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T3,T6

 LINE       588
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_mode && ((!reject_csrng_entropy)))
                 ------------1------------    -----2-----    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T23,T24,T26
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T6

 LINE       597
 EXPRESSION (edn_main_sm_state == Idle)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       598
 EXPRESSION (((!sw_cmd_mode)) && csrng_cmd_o.csrng_req_valid && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T23,T24,T26
1	1	1	Covered	T23,T24,T26

 LINE       603
 EXPRESSION ((main_sm_done_pulse || main_sm_idle) ? 1'b0 : ((boot_send_ins_cmd && cs_hw_cmd_handshake) ? 1'b1 : boot_mode_q))
             ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       603
 SUB-EXPRESSION (main_sm_done_pulse || main_sm_idle)
                 ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T24,T26

 LINE       603
 SUB-EXPRESSION ((boot_send_ins_cmd && cs_hw_cmd_handshake) ? 1'b1 : boot_mode_q)
                 ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       603
 SUB-EXPRESSION (boot_send_ins_cmd && cs_hw_cmd_handshake)
                 --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T26
1	0	Covered	T23,T24,T26
1	1	Covered	T23,T24,T26

 LINE       609
 EXPRESSION ((main_sm_done_pulse || main_sm_idle) ? 1'b0 : ((auto_req_mode_busy && cs_hw_cmd_handshake) ? 1'b1 : auto_mode_q))
             ------------------1-----------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       609
 SUB-EXPRESSION (main_sm_done_pulse || main_sm_idle)
                 ---------1--------    ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T24,T26

 LINE       609
 SUB-EXPRESSION ((auto_req_mode_busy && cs_hw_cmd_handshake) ? 1'b1 : auto_mode_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T10,T11,T12

 LINE       609
 SUB-EXPRESSION (auto_req_mode_busy && cs_hw_cmd_handshake)
                 ---------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T26
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       616
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? CMD_STS_SUCCESS : ((csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       616
 SUB-EXPRESSION 
 Number  Term
      1  (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? csrng_cmd_i.csrng_rsp_sts : (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       616
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy)))
                 ------------1------------    --------2-------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T24,T26
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T11,T31,T32
1	1	1	Covered	T23,T24,T26

 LINE       616
 SUB-EXPRESSION (cs_hw_cmd_handshake ? CMD_STS_SUCCESS : csrng_hw_cmd_sts_q)
                 ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       626
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[HwCmdSts])) ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? 1'b1 : (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q)))

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       626
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy))) ? 1'b1 : (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q))
                 --------------------------------------1-------------------------------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       626
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && ((!sw_cmd_mode)) && ((!reject_csrng_entropy)))
                 ------------1------------    --------2-------    ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T23,T24,T26
1	0	1	Covered	T1,T3,T6
1	1	0	Covered	T11,T31,T32
1	1	1	Covered	T23,T24,T26

 LINE       626
 SUB-EXPRESSION (cs_hw_cmd_handshake ? 1'b0 : csrng_hw_cmd_ack_q)
                 ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       635
 EXPRESSION (((!edn_enable_fo[HwCmdSts])) ? ({1'b0, INV}) : (cs_hw_cmd_handshake ? cs_cmd_req_out_q[3:0] : cmd_type_q))
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       635
 SUB-EXPRESSION (cs_hw_cmd_handshake ? cs_cmd_req_out_q[3:0] : cmd_type_q)
                 ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T23,T24,T26

 LINE       663
 EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T10,T11,T12

 LINE       663
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T12,T21

 LINE       665
 EXPRESSION (rescmd_handshake ? 1'b1 : reseed_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T12,T21

 LINE       669
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T12

 LINE       673
 EXPRESSION ((rescmd_handshake && ((!cmd_sent))) || capt_rescmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T12,T21,T22

 LINE       673
 SUB-EXPRESSION (rescmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T12,T21
1	1	Covered	T12,T21,T22

 LINE       675
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T6
1	0	Covered	T10,T11,T12

 LINE       677
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T11,T16,T33
1	0	Covered	T10,T11,T12
1	1	Covered	T79

 LINE       677
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T10,T11,T12
1	1	Covered	T34,T77

 LINE       677
 SUB-EXPRESSION ((sfifo_rescmd_full && ((!sfifo_rescmd_not_empty))) || sfifo_rescmd_int_err)
                 -------------------------1------------------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T20
1	0	Covered	T33,T92,T93

 LINE       677
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T16,T76
1	1	Covered	T33,T92,T93