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LINE 706
EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
------------------1------------------ -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T10,T11,T12 |
LINE 706
SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
-----1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Covered | T10,T11,T12 |
LINE 708
EXPRESSION (gencmd_handshake ? 1'b1 : generate_cmd_load)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T12 |
LINE 712
EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T12 |
LINE 716
EXPRESSION ((gencmd_handshake && ((!cmd_sent))) || capt_gencmd_fifo_cnt)
-----------------1----------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Covered | T10,T12,T21 |
LINE 716
SUB-EXPRESSION (gencmd_handshake && ((!cmd_sent)))
--------1------- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T10,T12,T21 |
LINE 718
EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T10,T11,T12 |
LINE 720
SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T37,T38,T39 |
LINE 720
SUB-EXPRESSION (sfifo_gencmd_pop && ((!sfifo_gencmd_not_empty)))
--------1------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T40,T41,T78 |
LINE 720
SUB-EXPRESSION ((sfifo_gencmd_full && ((!sfifo_gencmd_not_empty))) || sfifo_gencmd_int_err)
-------------------------1------------------------ ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T16,T19,T20 |
1 | 0 | Covered | T35,T37,T94 |
LINE 720
SUB-EXPRESSION (sfifo_gencmd_full && ((!sfifo_gencmd_not_empty)))
--------1-------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T35,T37,T94 |
LINE 764
EXPRESSION (send_gencmd && cmd_sent)
-----1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T12,T21 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T10,T11,T12 |
LINE 780
EXPRESSION (max_reqs_between_reseed_load || (send_rescmd && cmd_sent) || main_sm_done_pulse)
--------------1------------- ------------2------------ ---------3--------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T3,T6 |
0 | 1 | 0 | Covered | T10,T12,T21 |
1 | 0 | 0 | Covered | T10,T11,T21 |
LINE 780
SUB-EXPRESSION (send_rescmd && cmd_sent)
-----1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T11,T12 |
1 | 0 | Covered | T10,T12,T21 |
1 | 1 | Covered | T10,T12,T21 |
LINE 784
EXPRESSION (max_reqs_cnt == '0)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 787
EXPRESSION
Number Term
1 ((!edn_enable_fo[CmdFifoCnt])) ? '0 : ((cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))))
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 787
SUB-EXPRESSION
Number Term
1 (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T3,T6 |
LINE 787
SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T6 |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T11,T85,T54 |
LINE 787
SUB-EXPRESSION
Number Term
1 capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T10,T11,T12 |
LINE 787
SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T10,T11,T12 |
LINE 787
SUB-EXPRESSION ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
-------------------1------------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T10,T12,T21 |
LINE 787
SUB-EXPRESSION (sfifo_gencmd_pop || sfifo_rescmd_pop)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T3,T6 |
0 | 1 | Covered | T12,T21,T22 |
1 | 0 | Covered | T10,T12,T21 |
LINE 797
EXPRESSION ((cmd_fifo_cnt_q == 4'(1)) && (gencmd_handshake || rescmd_handshake))
------------1------------ -------------------2------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T12,T21 |
1 | 0 | Covered | T10,T11,T12 |
1 | 1 | Covered | T10,T11,T12 |
LINE 797
SUB-EXPRESSION (cmd_fifo_cnt_q == 4'(1))
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T12 |
LINE 797
SUB-EXPRESSION (gencmd_handshake || rescmd_handshake)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T10,T12,T21 |
1 | 0 | Covered | T10,T11,T12 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T6,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T6,T4 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T44,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T44,T12 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T10,T11 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T10,T45,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T10,T45,T36 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T46,T45,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T46,T45,T47 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T46,T45,T47 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T46,T45,T47 |
LINE 844
EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T46,T45 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T26,T46,T45 |
LINE 869
EXPRESSION (csrng_cmd_i.genbits_valid && ((!reject_csrng_entropy)) && ( ! ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack) ))
------------1------------ ------------2------------ -----------------------------------------3-----------------------------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Covered | T11,T31,T32 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T6 |
LINE 869
SUB-EXPRESSION ( ! ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack) )
--------------------------------------1--------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T31,T32 |
LINE 869
SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS) && csrng_cmd_i.csrng_rsp_ack)
-----------------------1---------------------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T11,T31,T32 |
LINE 869
SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_sts != CMD_STS_SUCCESS)
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T11,T31,T32 |
LINE 873
EXPRESSION (packer_cs_wready && ((!reject_csrng_entropy)))
--------1------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T11,T31,T32 |
1 | 1 | Covered | T1,T3,T6 |
LINE 877
EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 877
SUB-EXPRESSION ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T3,T6 |
LINE 877
SUB-EXPRESSION (packer_cs_push && packer_cs_wready)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T3,T6 |
LINE 892
EXPRESSION (packer_cs_rvalid && packer_cs_rready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T6 |
1 | 0 | Covered | T24,T26,T44 |
1 | 1 | Covered | T1,T3,T6 |
LINE 894
EXPRESSION (cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 896
EXPRESSION (((!edn_enable_fo[CsrngDataVld])) ? 1'b0 : (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T2,T3 |
LINE 896
SUB-EXPRESSION (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T3,T6 |
1 | Covered | T1,T3,T6 |
LINE 902
EXPRESSION (cs_rdata_capt_vld && cs_rdata_capt_vld_q && (cs_rdata_capt_q == packer_cs_rdata[63:0]))
--------1-------- ---------2--------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T6 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T23 |
1 | 1 | 1 | Covered | T11,T31,T32 |
LINE 902
SUB-EXPRESSION (cs_rdata_capt_q == packer_cs_rdata[63:0])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[0] && packer_arb_gnt[0])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T1,T6,T4 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[1] && packer_arb_gnt[1])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T3,T44,T12 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[2] && packer_arb_gnt[2])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T3,T10,T11 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[3] && packer_arb_gnt[3])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T10,T45,T47 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[4] && packer_arb_gnt[4])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T46,T45,T47 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[5] && packer_arb_gnt[5])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T46,T45,T47 |
LINE 930
EXPRESSION (packer_arb_valid && packer_ep_wready[6] && packer_arb_gnt[6])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T3,T6 |
1 | 1 | 1 | Covered | T26,T46,T45 |
LINE 934
EXPRESSION (packer_ep_clr[0] ? 1'b0 : ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T6,T4 |
LINE 934
SUB-EXPRESSION (packer_ep_push[0] && packer_ep_wready[0])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T6,T4 |
LINE 934
EXPRESSION (packer_ep_clr[1] ? 1'b0 : ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T44,T12 |
LINE 934
SUB-EXPRESSION (packer_ep_push[1] && packer_ep_wready[1])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T44,T12 |
LINE 934
EXPRESSION (packer_ep_clr[2] ? 1'b0 : ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T10,T11 |
LINE 934
SUB-EXPRESSION (packer_ep_push[2] && packer_ep_wready[2])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T10,T11 |
LINE 934
EXPRESSION (packer_ep_clr[3] ? 1'b0 : ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[3] && packer_ep_wready[3]) ? csrng_fips_q : edn_fips_q[3])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T45,T47 |
LINE 934
SUB-EXPRESSION (packer_ep_push[3] && packer_ep_wready[3])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T10,T45,T47 |
LINE 934
EXPRESSION (packer_ep_clr[4] ? 1'b0 : ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[4] && packer_ep_wready[4]) ? csrng_fips_q : edn_fips_q[4])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T46,T45,T47 |
LINE 934
SUB-EXPRESSION (packer_ep_push[4] && packer_ep_wready[4])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T46,T45,T47 |
LINE 934
EXPRESSION (packer_ep_clr[5] ? 1'b0 : ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[5] && packer_ep_wready[5]) ? csrng_fips_q : edn_fips_q[5])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T46,T45,T47 |
LINE 934
SUB-EXPRESSION (packer_ep_push[5] && packer_ep_wready[5])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T46,T45,T47 |
LINE 934
EXPRESSION (packer_ep_clr[6] ? 1'b0 : ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T6 |
LINE 934
SUB-EXPRESSION ((packer_ep_push[6] && packer_ep_wready[6]) ? csrng_fips_q : edn_fips_q[6])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T26,T46,T45 |
LINE 934
SUB-EXPRESSION (packer_ep_push[6] && packer_ep_wready[6])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T26,T46,T45 |
LINE 977
EXPRESSION (((|err_code_test_bit[19:2])) || ((|err_code_test_bit[27:22])))
--------------1------------- --------------2--------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T5,T11 |
1 | 0 | Covered | T1,T23,T24 |