Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.49 98.24 93.72 97.02 92.44 96.33 99.77 90.93


Total test records in report: 972
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T790 /workspace/coverage/default/149.edn_genbits.1160245699 Jun 06 02:40:35 PM PDT 24 Jun 06 02:40:38 PM PDT 24 28850696 ps
T791 /workspace/coverage/default/99.edn_genbits.31545795 Jun 06 02:40:25 PM PDT 24 Jun 06 02:40:29 PM PDT 24 46296776 ps
T792 /workspace/coverage/default/20.edn_alert_test.2150223763 Jun 06 02:39:21 PM PDT 24 Jun 06 02:39:23 PM PDT 24 13481990 ps
T793 /workspace/coverage/default/32.edn_genbits.1080234815 Jun 06 02:39:40 PM PDT 24 Jun 06 02:39:43 PM PDT 24 90613301 ps
T794 /workspace/coverage/default/72.edn_genbits.2262813045 Jun 06 02:40:18 PM PDT 24 Jun 06 02:40:24 PM PDT 24 54896185 ps
T795 /workspace/coverage/default/209.edn_genbits.2076476592 Jun 06 02:40:47 PM PDT 24 Jun 06 02:40:50 PM PDT 24 49216832 ps
T796 /workspace/coverage/default/16.edn_intr.4178608342 Jun 06 02:39:13 PM PDT 24 Jun 06 02:39:15 PM PDT 24 38373169 ps
T797 /workspace/coverage/default/35.edn_alert_test.1078572735 Jun 06 02:39:47 PM PDT 24 Jun 06 02:39:50 PM PDT 24 14886054 ps
T798 /workspace/coverage/default/1.edn_alert_test.1027722987 Jun 06 02:38:35 PM PDT 24 Jun 06 02:38:37 PM PDT 24 12074908 ps
T799 /workspace/coverage/default/219.edn_genbits.1056664301 Jun 06 02:40:46 PM PDT 24 Jun 06 02:40:50 PM PDT 24 108663293 ps
T800 /workspace/coverage/default/57.edn_err.4154074746 Jun 06 02:40:11 PM PDT 24 Jun 06 02:40:17 PM PDT 24 19629054 ps
T801 /workspace/coverage/default/14.edn_intr.2059145049 Jun 06 02:39:07 PM PDT 24 Jun 06 02:39:11 PM PDT 24 23345218 ps
T802 /workspace/coverage/default/13.edn_genbits.475394637 Jun 06 02:39:05 PM PDT 24 Jun 06 02:39:09 PM PDT 24 46603610 ps
T803 /workspace/coverage/default/43.edn_alert_test.2642354645 Jun 06 02:39:58 PM PDT 24 Jun 06 02:40:03 PM PDT 24 31241444 ps
T804 /workspace/coverage/default/179.edn_genbits.2405142933 Jun 06 02:40:41 PM PDT 24 Jun 06 02:40:44 PM PDT 24 62326259 ps
T805 /workspace/coverage/default/69.edn_err.59329042 Jun 06 02:40:16 PM PDT 24 Jun 06 02:40:22 PM PDT 24 21522263 ps
T806 /workspace/coverage/default/40.edn_err.3853290971 Jun 06 02:39:51 PM PDT 24 Jun 06 02:39:54 PM PDT 24 23241895 ps
T807 /workspace/coverage/default/90.edn_err.1103508298 Jun 06 02:40:19 PM PDT 24 Jun 06 02:40:24 PM PDT 24 25609314 ps
T808 /workspace/coverage/default/13.edn_alert_test.4222607043 Jun 06 02:39:06 PM PDT 24 Jun 06 02:39:10 PM PDT 24 28419050 ps
T809 /workspace/coverage/default/33.edn_smoke.3781679111 Jun 06 02:39:40 PM PDT 24 Jun 06 02:39:43 PM PDT 24 27271074 ps
T139 /workspace/coverage/default/25.edn_alert.1330730303 Jun 06 02:39:28 PM PDT 24 Jun 06 02:39:31 PM PDT 24 26347194 ps
T810 /workspace/coverage/default/21.edn_err.3553095776 Jun 06 02:39:21 PM PDT 24 Jun 06 02:39:23 PM PDT 24 26123608 ps
T811 /workspace/coverage/default/70.edn_err.3244379174 Jun 06 02:40:28 PM PDT 24 Jun 06 02:40:32 PM PDT 24 29457127 ps
T812 /workspace/coverage/default/33.edn_disable_auto_req_mode.2241758117 Jun 06 02:39:40 PM PDT 24 Jun 06 02:39:43 PM PDT 24 122139077 ps
T813 /workspace/coverage/default/101.edn_genbits.429749917 Jun 06 02:40:36 PM PDT 24 Jun 06 02:40:39 PM PDT 24 38639264 ps
T814 /workspace/coverage/default/249.edn_genbits.1666973741 Jun 06 02:40:44 PM PDT 24 Jun 06 02:40:48 PM PDT 24 38197905 ps
T815 /workspace/coverage/default/211.edn_genbits.2777760608 Jun 06 02:40:43 PM PDT 24 Jun 06 02:40:46 PM PDT 24 49476564 ps
T816 /workspace/coverage/default/48.edn_err.3494555252 Jun 06 02:40:14 PM PDT 24 Jun 06 02:40:18 PM PDT 24 23916493 ps
T817 /workspace/coverage/default/63.edn_genbits.3021735568 Jun 06 02:40:19 PM PDT 24 Jun 06 02:40:25 PM PDT 24 86930885 ps
T818 /workspace/coverage/default/26.edn_smoke.698857988 Jun 06 02:39:26 PM PDT 24 Jun 06 02:39:28 PM PDT 24 52734258 ps
T819 /workspace/coverage/default/162.edn_genbits.2576065449 Jun 06 02:40:37 PM PDT 24 Jun 06 02:40:40 PM PDT 24 35292706 ps
T300 /workspace/coverage/default/4.edn_regwen.1905390420 Jun 06 02:38:46 PM PDT 24 Jun 06 02:38:48 PM PDT 24 45511348 ps
T820 /workspace/coverage/default/30.edn_genbits.3301460178 Jun 06 02:39:39 PM PDT 24 Jun 06 02:39:45 PM PDT 24 159784201 ps
T821 /workspace/coverage/default/236.edn_genbits.1184583299 Jun 06 02:40:45 PM PDT 24 Jun 06 02:40:49 PM PDT 24 44581284 ps
T78 /workspace/coverage/default/29.edn_intr.2481123005 Jun 06 02:39:42 PM PDT 24 Jun 06 02:39:45 PM PDT 24 25810809 ps
T822 /workspace/coverage/default/112.edn_genbits.300968023 Jun 06 02:40:37 PM PDT 24 Jun 06 02:40:40 PM PDT 24 42849794 ps
T201 /workspace/coverage/default/24.edn_disable.1516710877 Jun 06 02:39:26 PM PDT 24 Jun 06 02:39:28 PM PDT 24 12973322 ps
T823 /workspace/coverage/default/24.edn_disable_auto_req_mode.3089206776 Jun 06 02:39:26 PM PDT 24 Jun 06 02:39:29 PM PDT 24 32727625 ps
T824 /workspace/coverage/default/10.edn_smoke.4039217433 Jun 06 02:38:56 PM PDT 24 Jun 06 02:38:59 PM PDT 24 45034536 ps
T825 /workspace/coverage/default/61.edn_genbits.1210697633 Jun 06 02:40:16 PM PDT 24 Jun 06 02:40:23 PM PDT 24 151619820 ps
T826 /workspace/coverage/default/21.edn_smoke.2712982465 Jun 06 02:39:16 PM PDT 24 Jun 06 02:39:20 PM PDT 24 57846000 ps
T827 /workspace/coverage/default/255.edn_genbits.1444401733 Jun 06 02:41:02 PM PDT 24 Jun 06 02:41:06 PM PDT 24 37508260 ps
T134 /workspace/coverage/default/36.edn_disable_auto_req_mode.1497687180 Jun 06 02:39:47 PM PDT 24 Jun 06 02:39:49 PM PDT 24 138512291 ps
T299 /workspace/coverage/default/9.edn_regwen.352323766 Jun 06 02:39:01 PM PDT 24 Jun 06 02:39:04 PM PDT 24 33378541 ps
T828 /workspace/coverage/default/210.edn_genbits.2792940607 Jun 06 02:40:43 PM PDT 24 Jun 06 02:40:46 PM PDT 24 139212791 ps
T829 /workspace/coverage/default/15.edn_alert_test.3599565987 Jun 06 02:39:07 PM PDT 24 Jun 06 02:39:11 PM PDT 24 30734552 ps
T830 /workspace/coverage/default/176.edn_genbits.2362024972 Jun 06 02:40:34 PM PDT 24 Jun 06 02:40:37 PM PDT 24 62440407 ps
T189 /workspace/coverage/default/11.edn_disable.2838803898 Jun 06 02:39:11 PM PDT 24 Jun 06 02:39:14 PM PDT 24 16433247 ps
T831 /workspace/coverage/default/24.edn_err.4011345405 Jun 06 02:39:31 PM PDT 24 Jun 06 02:39:35 PM PDT 24 36116050 ps
T832 /workspace/coverage/default/156.edn_genbits.254433969 Jun 06 02:40:38 PM PDT 24 Jun 06 02:40:42 PM PDT 24 60668978 ps
T833 /workspace/coverage/default/39.edn_genbits.2947375717 Jun 06 02:39:47 PM PDT 24 Jun 06 02:39:51 PM PDT 24 67938708 ps
T834 /workspace/coverage/default/41.edn_intr.3846275143 Jun 06 02:39:59 PM PDT 24 Jun 06 02:40:06 PM PDT 24 27999165 ps
T835 /workspace/coverage/default/34.edn_stress_all.3987110667 Jun 06 02:39:46 PM PDT 24 Jun 06 02:39:52 PM PDT 24 331340188 ps
T836 /workspace/coverage/default/213.edn_genbits.3235459023 Jun 06 02:40:46 PM PDT 24 Jun 06 02:40:50 PM PDT 24 263156952 ps
T837 /workspace/coverage/default/8.edn_genbits.3984558033 Jun 06 02:38:56 PM PDT 24 Jun 06 02:39:00 PM PDT 24 66440024 ps
T838 /workspace/coverage/default/259.edn_genbits.559502811 Jun 06 02:40:49 PM PDT 24 Jun 06 02:40:53 PM PDT 24 66905469 ps
T171 /workspace/coverage/default/23.edn_err.3910216894 Jun 06 02:39:26 PM PDT 24 Jun 06 02:39:28 PM PDT 24 64641338 ps
T839 /workspace/coverage/cover_reg_top/24.edn_intr_test.916551276 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 40649260 ps
T237 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4148135581 Jun 06 02:19:47 PM PDT 24 Jun 06 02:19:49 PM PDT 24 38720783 ps
T840 /workspace/coverage/cover_reg_top/23.edn_intr_test.753190043 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:04 PM PDT 24 14859890 ps
T224 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3412986130 Jun 06 02:19:39 PM PDT 24 Jun 06 02:19:41 PM PDT 24 15222754 ps
T841 /workspace/coverage/cover_reg_top/28.edn_intr_test.4176743504 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 107124374 ps
T842 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2732280219 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:58 PM PDT 24 17341816 ps
T238 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2932214101 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 19508044 ps
T843 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3628063096 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:39 PM PDT 24 35348457 ps
T844 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3808229869 Jun 06 02:19:50 PM PDT 24 Jun 06 02:19:53 PM PDT 24 153950346 ps
T845 /workspace/coverage/cover_reg_top/22.edn_intr_test.3298243127 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 22122483 ps
T239 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3842305579 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 38666410 ps
T846 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2164758843 Jun 06 02:19:32 PM PDT 24 Jun 06 02:19:37 PM PDT 24 78525489 ps
T240 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4180531784 Jun 06 02:19:51 PM PDT 24 Jun 06 02:19:53 PM PDT 24 143812182 ps
T257 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1816923511 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:58 PM PDT 24 84193254 ps
T225 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.966066528 Jun 06 02:19:46 PM PDT 24 Jun 06 02:19:49 PM PDT 24 152773123 ps
T847 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2795219852 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:40 PM PDT 24 37160319 ps
T848 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3797477446 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:45 PM PDT 24 46561901 ps
T258 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1812155676 Jun 06 02:19:50 PM PDT 24 Jun 06 02:19:52 PM PDT 24 125920548 ps
T259 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2965477771 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 74689477 ps
T849 /workspace/coverage/cover_reg_top/16.edn_intr_test.2823940611 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:53 PM PDT 24 46739205 ps
T226 /workspace/coverage/cover_reg_top/8.edn_csr_rw.425310902 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 37363811 ps
T850 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3199843660 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:40 PM PDT 24 41542277 ps
T241 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1374844336 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:46 PM PDT 24 15700037 ps
T851 /workspace/coverage/cover_reg_top/30.edn_intr_test.75386066 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:57 PM PDT 24 19034302 ps
T227 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.10823445 Jun 06 02:19:44 PM PDT 24 Jun 06 02:19:47 PM PDT 24 70313227 ps
T852 /workspace/coverage/cover_reg_top/32.edn_intr_test.83420956 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:05 PM PDT 24 17222870 ps
T228 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3422528867 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:40 PM PDT 24 17843667 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1834793026 Jun 06 02:19:37 PM PDT 24 Jun 06 02:19:40 PM PDT 24 42337808 ps
T270 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.992074457 Jun 06 02:19:37 PM PDT 24 Jun 06 02:19:40 PM PDT 24 47820649 ps
T853 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2070607299 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:56 PM PDT 24 141492437 ps
T854 /workspace/coverage/cover_reg_top/17.edn_intr_test.421960653 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:58 PM PDT 24 14986055 ps
T855 /workspace/coverage/cover_reg_top/45.edn_intr_test.3066607786 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 22755363 ps
T266 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.521336598 Jun 06 02:19:51 PM PDT 24 Jun 06 02:19:56 PM PDT 24 179205837 ps
T856 /workspace/coverage/cover_reg_top/29.edn_intr_test.1147613095 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:05 PM PDT 24 52235454 ps
T857 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1972845474 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 49817584 ps
T858 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1917706622 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:50 PM PDT 24 43739016 ps
T242 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.366149286 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:41 PM PDT 24 36646202 ps
T859 /workspace/coverage/cover_reg_top/7.edn_intr_test.2031339866 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:40 PM PDT 24 19478254 ps
T860 /workspace/coverage/cover_reg_top/10.edn_intr_test.962515658 Jun 06 02:19:47 PM PDT 24 Jun 06 02:19:49 PM PDT 24 31421063 ps
T861 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3826013886 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:52 PM PDT 24 138348684 ps
T862 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4187782728 Jun 06 02:19:36 PM PDT 24 Jun 06 02:19:39 PM PDT 24 322973492 ps
T863 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1043883051 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:45 PM PDT 24 84356924 ps
T864 /workspace/coverage/cover_reg_top/2.edn_intr_test.237778607 Jun 06 02:19:50 PM PDT 24 Jun 06 02:19:52 PM PDT 24 20825430 ps
T865 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2699962287 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:53 PM PDT 24 201720174 ps
T866 /workspace/coverage/cover_reg_top/40.edn_intr_test.1682668652 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:10 PM PDT 24 43025903 ps
T867 /workspace/coverage/cover_reg_top/39.edn_intr_test.990203648 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:03 PM PDT 24 20100532 ps
T868 /workspace/coverage/cover_reg_top/18.edn_tl_errors.739290454 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:59 PM PDT 24 71530754 ps
T869 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2866823780 Jun 06 02:19:46 PM PDT 24 Jun 06 02:19:49 PM PDT 24 143424732 ps
T870 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3414384874 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:57 PM PDT 24 47373731 ps
T871 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.160953724 Jun 06 02:19:44 PM PDT 24 Jun 06 02:19:46 PM PDT 24 601559529 ps
T872 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1241457675 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:47 PM PDT 24 271345727 ps
T873 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1122700531 Jun 06 02:19:42 PM PDT 24 Jun 06 02:19:50 PM PDT 24 193512188 ps
T230 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1179908810 Jun 06 02:19:37 PM PDT 24 Jun 06 02:19:39 PM PDT 24 13940494 ps
T874 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3798918645 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 97982892 ps
T875 /workspace/coverage/cover_reg_top/9.edn_intr_test.1434976837 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:00 PM PDT 24 11740149 ps
T876 /workspace/coverage/cover_reg_top/33.edn_intr_test.1077684295 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:08 PM PDT 24 14445554 ps
T877 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4058422108 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:46 PM PDT 24 15496733 ps
T878 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.843008547 Jun 06 02:19:36 PM PDT 24 Jun 06 02:19:39 PM PDT 24 23214056 ps
T879 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3992470745 Jun 06 02:19:42 PM PDT 24 Jun 06 02:19:44 PM PDT 24 27090012 ps
T243 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3905811176 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:02 PM PDT 24 33829898 ps
T244 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3285421121 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:50 PM PDT 24 27772247 ps
T880 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3211986298 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 37255026 ps
T881 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4020978109 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 76205087 ps
T882 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1138362386 Jun 06 02:19:58 PM PDT 24 Jun 06 02:20:05 PM PDT 24 519921043 ps
T883 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.295885002 Jun 06 02:19:45 PM PDT 24 Jun 06 02:19:47 PM PDT 24 98716132 ps
T231 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1483864226 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 68336739 ps
T884 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.61409266 Jun 06 02:19:34 PM PDT 24 Jun 06 02:19:36 PM PDT 24 50986680 ps
T885 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3093854094 Jun 06 02:19:50 PM PDT 24 Jun 06 02:19:51 PM PDT 24 40340138 ps
T245 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.122692775 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:57 PM PDT 24 43210074 ps
T886 /workspace/coverage/cover_reg_top/6.edn_intr_test.1739719954 Jun 06 02:19:34 PM PDT 24 Jun 06 02:19:36 PM PDT 24 25081353 ps
T887 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.636835210 Jun 06 02:19:39 PM PDT 24 Jun 06 02:19:42 PM PDT 24 36734989 ps
T888 /workspace/coverage/cover_reg_top/20.edn_intr_test.825486704 Jun 06 02:19:47 PM PDT 24 Jun 06 02:19:48 PM PDT 24 26864272 ps
T889 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2874435457 Jun 06 02:19:36 PM PDT 24 Jun 06 02:19:39 PM PDT 24 58588689 ps
T890 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.549026819 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:57 PM PDT 24 142723482 ps
T891 /workspace/coverage/cover_reg_top/0.edn_csr_rw.3264963262 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 98757052 ps
T892 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1387454951 Jun 06 02:19:44 PM PDT 24 Jun 06 02:19:46 PM PDT 24 72571784 ps
T893 /workspace/coverage/cover_reg_top/49.edn_intr_test.1409880788 Jun 06 02:19:57 PM PDT 24 Jun 06 02:19:59 PM PDT 24 19625611 ps
T894 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1780823 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:46 PM PDT 24 22911275 ps
T895 /workspace/coverage/cover_reg_top/1.edn_csr_rw.2554247917 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 52318193 ps
T896 /workspace/coverage/cover_reg_top/34.edn_intr_test.3204810380 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:58 PM PDT 24 18679537 ps
T897 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1641426949 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:51 PM PDT 24 74215062 ps
T898 /workspace/coverage/cover_reg_top/25.edn_intr_test.3168475736 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:09 PM PDT 24 33977358 ps
T232 /workspace/coverage/cover_reg_top/2.edn_csr_rw.4154112799 Jun 06 02:19:28 PM PDT 24 Jun 06 02:19:29 PM PDT 24 21995282 ps
T899 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1477474839 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:03 PM PDT 24 95158480 ps
T900 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2574980041 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:54 PM PDT 24 281029038 ps
T901 /workspace/coverage/cover_reg_top/15.edn_csr_rw.552067805 Jun 06 02:20:05 PM PDT 24 Jun 06 02:20:09 PM PDT 24 53493824 ps
T902 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1214661277 Jun 06 02:19:44 PM PDT 24 Jun 06 02:19:48 PM PDT 24 486696855 ps
T903 /workspace/coverage/cover_reg_top/0.edn_intr_test.2339739997 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:50 PM PDT 24 12385954 ps
T904 /workspace/coverage/cover_reg_top/21.edn_intr_test.1947686599 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:51 PM PDT 24 26589815 ps
T905 /workspace/coverage/cover_reg_top/27.edn_intr_test.551645178 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:10 PM PDT 24 15453892 ps
T906 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3138665823 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 90548058 ps
T907 /workspace/coverage/cover_reg_top/41.edn_intr_test.3737195165 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:10 PM PDT 24 14946161 ps
T908 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2165704044 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:57 PM PDT 24 23411572 ps
T909 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1116711463 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:12 PM PDT 24 273273801 ps
T910 /workspace/coverage/cover_reg_top/14.edn_csr_rw.4056986755 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:58 PM PDT 24 51465158 ps
T911 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3698008431 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:10 PM PDT 24 1656563603 ps
T912 /workspace/coverage/cover_reg_top/1.edn_intr_test.1567724923 Jun 06 02:19:37 PM PDT 24 Jun 06 02:19:40 PM PDT 24 39586688 ps
T913 /workspace/coverage/cover_reg_top/18.edn_intr_test.232632789 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 16096789 ps
T914 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2487968432 Jun 06 02:19:30 PM PDT 24 Jun 06 02:19:31 PM PDT 24 64896582 ps
T915 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1664413557 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:02 PM PDT 24 17993483 ps
T916 /workspace/coverage/cover_reg_top/46.edn_intr_test.1513259775 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 17365611 ps
T917 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.682547138 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:41 PM PDT 24 157314937 ps
T918 /workspace/coverage/cover_reg_top/19.edn_tl_errors.777540248 Jun 06 02:19:56 PM PDT 24 Jun 06 02:19:59 PM PDT 24 31504868 ps
T919 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2739494628 Jun 06 02:19:42 PM PDT 24 Jun 06 02:19:44 PM PDT 24 21040117 ps
T920 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3780946189 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:59 PM PDT 24 114121974 ps
T921 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.627882092 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 17245305 ps
T922 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3571919528 Jun 06 02:19:32 PM PDT 24 Jun 06 02:19:39 PM PDT 24 711500195 ps
T923 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3050935336 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 13723462 ps
T924 /workspace/coverage/cover_reg_top/5.edn_intr_test.1291244992 Jun 06 02:19:33 PM PDT 24 Jun 06 02:19:35 PM PDT 24 18502674 ps
T925 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2446633168 Jun 06 02:19:33 PM PDT 24 Jun 06 02:19:35 PM PDT 24 87148735 ps
T926 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2607555541 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 16525241 ps
T927 /workspace/coverage/cover_reg_top/3.edn_intr_test.3886199490 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:57 PM PDT 24 25407196 ps
T271 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3200495625 Jun 06 02:19:45 PM PDT 24 Jun 06 02:19:48 PM PDT 24 367066699 ps
T928 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.300675869 Jun 06 02:20:04 PM PDT 24 Jun 06 02:20:08 PM PDT 24 52409808 ps
T929 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1637712736 Jun 06 02:19:48 PM PDT 24 Jun 06 02:19:50 PM PDT 24 46199710 ps
T930 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3908622833 Jun 06 02:19:37 PM PDT 24 Jun 06 02:19:40 PM PDT 24 182534540 ps
T931 /workspace/coverage/cover_reg_top/37.edn_intr_test.1655269364 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:03 PM PDT 24 17180622 ps
T267 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3087773384 Jun 06 02:19:47 PM PDT 24 Jun 06 02:19:51 PM PDT 24 496975443 ps
T932 /workspace/coverage/cover_reg_top/31.edn_intr_test.4125690842 Jun 06 02:19:58 PM PDT 24 Jun 06 02:19:59 PM PDT 24 25199895 ps
T933 /workspace/coverage/cover_reg_top/13.edn_intr_test.1199317031 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 13264387 ps
T934 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3669151944 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 36611786 ps
T233 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3877403378 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:57 PM PDT 24 21308424 ps
T935 /workspace/coverage/cover_reg_top/43.edn_intr_test.2041606003 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:04 PM PDT 24 16858118 ps
T268 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1665333430 Jun 06 02:19:51 PM PDT 24 Jun 06 02:19:54 PM PDT 24 78921025 ps
T936 /workspace/coverage/cover_reg_top/19.edn_intr_test.2682358180 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:50 PM PDT 24 16943163 ps
T937 /workspace/coverage/cover_reg_top/6.edn_tl_errors.65460760 Jun 06 02:19:33 PM PDT 24 Jun 06 02:19:36 PM PDT 24 196539282 ps
T938 /workspace/coverage/cover_reg_top/48.edn_intr_test.688295433 Jun 06 02:20:11 PM PDT 24 Jun 06 02:20:14 PM PDT 24 45336682 ps
T939 /workspace/coverage/cover_reg_top/26.edn_intr_test.1324945864 Jun 06 02:19:59 PM PDT 24 Jun 06 02:20:00 PM PDT 24 13866063 ps
T940 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.161543804 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:57 PM PDT 24 20901667 ps
T941 /workspace/coverage/cover_reg_top/47.edn_intr_test.1047070089 Jun 06 02:20:07 PM PDT 24 Jun 06 02:20:10 PM PDT 24 11878088 ps
T942 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2039319815 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:41 PM PDT 24 181792560 ps
T943 /workspace/coverage/cover_reg_top/15.edn_intr_test.769580274 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:55 PM PDT 24 36945764 ps
T944 /workspace/coverage/cover_reg_top/14.edn_intr_test.4258840654 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:56 PM PDT 24 69474193 ps
T269 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3670691473 Jun 06 02:19:34 PM PDT 24 Jun 06 02:19:47 PM PDT 24 183948486 ps
T945 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1547532693 Jun 06 02:19:40 PM PDT 24 Jun 06 02:19:45 PM PDT 24 92844806 ps
T234 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2737061255 Jun 06 02:19:39 PM PDT 24 Jun 06 02:19:41 PM PDT 24 43481084 ps
T946 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.986198620 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:08 PM PDT 24 186637188 ps
T947 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.538434742 Jun 06 02:20:06 PM PDT 24 Jun 06 02:20:09 PM PDT 24 21176113 ps
T948 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1517629918 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:45 PM PDT 24 33783359 ps
T949 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3164594232 Jun 06 02:19:40 PM PDT 24 Jun 06 02:19:45 PM PDT 24 70784719 ps
T950 /workspace/coverage/cover_reg_top/11.edn_intr_test.2031162928 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 59618862 ps
T951 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2928830430 Jun 06 02:19:47 PM PDT 24 Jun 06 02:19:48 PM PDT 24 12145255 ps
T952 /workspace/coverage/cover_reg_top/8.edn_intr_test.786756810 Jun 06 02:19:43 PM PDT 24 Jun 06 02:19:44 PM PDT 24 12764831 ps
T953 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2379015035 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:39 PM PDT 24 53348296 ps
T954 /workspace/coverage/cover_reg_top/9.edn_tl_errors.578269081 Jun 06 02:19:39 PM PDT 24 Jun 06 02:19:43 PM PDT 24 154773314 ps
T955 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2402608753 Jun 06 02:19:32 PM PDT 24 Jun 06 02:19:36 PM PDT 24 93854884 ps
T956 /workspace/coverage/cover_reg_top/35.edn_intr_test.140674501 Jun 06 02:20:00 PM PDT 24 Jun 06 02:20:01 PM PDT 24 50325219 ps
T235 /workspace/coverage/cover_reg_top/13.edn_csr_rw.4138909443 Jun 06 02:19:54 PM PDT 24 Jun 06 02:19:56 PM PDT 24 36291155 ps
T957 /workspace/coverage/cover_reg_top/16.edn_csr_rw.148162284 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:05 PM PDT 24 22221484 ps
T958 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.476942959 Jun 06 02:19:38 PM PDT 24 Jun 06 02:19:41 PM PDT 24 207118017 ps
T959 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2470043593 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:52 PM PDT 24 40038511 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1355626160 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:56 PM PDT 24 229716624 ps
T960 /workspace/coverage/cover_reg_top/8.edn_tl_errors.939945800 Jun 06 02:19:49 PM PDT 24 Jun 06 02:19:52 PM PDT 24 76855814 ps
T961 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3865206606 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:05 PM PDT 24 76155117 ps
T962 /workspace/coverage/cover_reg_top/36.edn_intr_test.1505344093 Jun 06 02:20:03 PM PDT 24 Jun 06 02:20:06 PM PDT 24 38616435 ps
T963 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3294818434 Jun 06 02:19:35 PM PDT 24 Jun 06 02:19:38 PM PDT 24 149435054 ps
T964 /workspace/coverage/cover_reg_top/42.edn_intr_test.2367112740 Jun 06 02:20:01 PM PDT 24 Jun 06 02:20:02 PM PDT 24 12926633 ps
T965 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.37107814 Jun 06 02:19:52 PM PDT 24 Jun 06 02:19:54 PM PDT 24 16994929 ps
T966 /workspace/coverage/cover_reg_top/12.edn_intr_test.1052868673 Jun 06 02:19:59 PM PDT 24 Jun 06 02:20:01 PM PDT 24 28558146 ps
T967 /workspace/coverage/cover_reg_top/38.edn_intr_test.1041010156 Jun 06 02:19:55 PM PDT 24 Jun 06 02:19:57 PM PDT 24 24435387 ps
T968 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1734526652 Jun 06 02:19:28 PM PDT 24 Jun 06 02:19:32 PM PDT 24 262966545 ps
T969 /workspace/coverage/cover_reg_top/4.edn_intr_test.1920560892 Jun 06 02:19:41 PM PDT 24 Jun 06 02:19:43 PM PDT 24 14138914 ps
T970 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2901148783 Jun 06 02:19:53 PM PDT 24 Jun 06 02:19:57 PM PDT 24 161241367 ps
T971 /workspace/coverage/cover_reg_top/44.edn_intr_test.1339246850 Jun 06 02:20:02 PM PDT 24 Jun 06 02:20:04 PM PDT 24 44449795 ps
T972 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3739361229 Jun 06 02:19:34 PM PDT 24 Jun 06 02:19:37 PM PDT 24 25227159 ps

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3264372693
Short name T1
Test name
Test status
Simulation time 62842541219 ps
CPU time 1355.66 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 03:02:34 PM PDT 24
Peak memory 224052 kb
Host smart-c46ac546-4384-44bc-9c7f-80c3b2d46355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264372693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3264372693
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.edn_genbits.3990752946
Short name T21
Test name
Test status
Simulation time 651424855 ps
CPU time 4.14 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 219840 kb
Host smart-227c2edb-1bdd-4481-bfdc-f4ec8216e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990752946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3990752946
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.929993922
Short name T16
Test name
Test status
Simulation time 1933358911 ps
CPU time 8.01 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:38:51 PM PDT 24
Peak memory 243992 kb
Host smart-79966b89-cd58-460f-8d46-ac91191f439a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929993922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.929993922
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/134.edn_genbits.1399932338
Short name T46
Test name
Test status
Simulation time 45832158 ps
CPU time 1.37 seconds
Started Jun 06 02:40:22 PM PDT 24
Finished Jun 06 02:40:27 PM PDT 24
Peak memory 218360 kb
Host smart-fdbd1009-faff-4937-9b10-758febbf8cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399932338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1399932338
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_alert.2469565678
Short name T11
Test name
Test status
Simulation time 25484061 ps
CPU time 1.2 seconds
Started Jun 06 02:40:13 PM PDT 24
Finished Jun 06 02:40:18 PM PDT 24
Peak memory 220180 kb
Host smart-0d29b295-7248-47e7-9474-927f9995bc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469565678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2469565678
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1757198756
Short name T12
Test name
Test status
Simulation time 63664893 ps
CPU time 1.19 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:06 PM PDT 24
Peak memory 218000 kb
Host smart-0f511afb-5c7a-42ae-a3e1-b72a75568d6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757198756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1757198756
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/80.edn_err.924803561
Short name T56
Test name
Test status
Simulation time 66560099 ps
CPU time 1.22 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 225712 kb
Host smart-508b5991-3bbc-411e-8785-cd016a245b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924803561 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.924803561
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2767222073
Short name T178
Test name
Test status
Simulation time 35581253209 ps
CPU time 775.96 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:52:13 PM PDT 24
Peak memory 218920 kb
Host smart-ae73b291-d80a-481f-85de-5719b859bb43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767222073 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2767222073
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3139076478
Short name T82
Test name
Test status
Simulation time 62511836 ps
CPU time 1.31 seconds
Started Jun 06 02:39:41 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215544 kb
Host smart-af5398e1-1d9e-4cd1-9120-6cfdf541caf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139076478 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3139076478
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.2124237428
Short name T26
Test name
Test status
Simulation time 27584867 ps
CPU time 0.8 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 216172 kb
Host smart-81b63d6b-5ff5-4ba1-af6d-2a9280138ec9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124237428 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.2124237428
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_alert.3073801624
Short name T640
Test name
Test status
Simulation time 24774685 ps
CPU time 1.24 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 218756 kb
Host smart-ea2f5a7f-f5eb-4e2f-96f6-1da2f0214b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073801624 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3073801624
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.913713916
Short name T213
Test name
Test status
Simulation time 17415007 ps
CPU time 0.98 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 206992 kb
Host smart-d3f1ab5d-2ea0-4af8-b491-3f6c746ea236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913713916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.913713916
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1791294517
Short name T98
Test name
Test status
Simulation time 63253701 ps
CPU time 1.22 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 216884 kb
Host smart-cc0ba4ab-47c5-440b-927b-c48dfb6549e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791294517 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1791294517
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_alert.1478225728
Short name T31
Test name
Test status
Simulation time 21424585 ps
CPU time 1.09 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:39:42 PM PDT 24
Peak memory 217928 kb
Host smart-f73a0639-eb5f-4a74-8fb3-d7a3c38c8db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478225728 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1478225728
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.3422528867
Short name T228
Test name
Test status
Simulation time 17843667 ps
CPU time 0.99 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 206180 kb
Host smart-58e39ee7-e6e7-413d-8822-7ce42e56d454
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422528867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.3422528867
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.521336598
Short name T266
Test name
Test status
Simulation time 179205837 ps
CPU time 3.69 seconds
Started Jun 06 02:19:51 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 206376 kb
Host smart-0f07b19c-a17f-49ec-8087-56a3b381dcb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521336598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.521336598
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/5.edn_disable.3844167210
Short name T149
Test name
Test status
Simulation time 34401255 ps
CPU time 0.81 seconds
Started Jun 06 02:38:45 PM PDT 24
Finished Jun 06 02:38:47 PM PDT 24
Peak memory 216264 kb
Host smart-a98250e2-f98a-4819-a78c-d72d6fde538d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844167210 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3844167210
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2618421065
Short name T193
Test name
Test status
Simulation time 19549098 ps
CPU time 1.04 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 216900 kb
Host smart-7ea3c253-53a0-4cef-b0ba-bf464dae02c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618421065 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2618421065
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/59.edn_err.2474212320
Short name T53
Test name
Test status
Simulation time 26181077 ps
CPU time 1.08 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 229616 kb
Host smart-ade30537-45e7-4cfa-94e4-6cfceab7754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474212320 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2474212320
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/19.edn_alert.1841370971
Short name T163
Test name
Test status
Simulation time 28232745 ps
CPU time 1.23 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 219312 kb
Host smart-d6afc2f0-9790-4068-9bf1-639f47b7a544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841370971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1841370971
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.2709125409
Short name T101
Test name
Test status
Simulation time 29542552 ps
CPU time 1.35 seconds
Started Jun 06 02:38:59 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 219476 kb
Host smart-fe93a7a3-75a2-48a3-a57d-8023f07b32f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709125409 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.2709125409
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/153.edn_genbits.3553163555
Short name T280
Test name
Test status
Simulation time 69577316 ps
CPU time 1.36 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218848 kb
Host smart-f6b34ee0-e4c5-4460-8ca2-4eadd3d930f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553163555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3553163555
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1330730303
Short name T139
Test name
Test status
Simulation time 26347194 ps
CPU time 1.19 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 215600 kb
Host smart-1c94adb7-5418-470a-821b-ad3ea6666b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330730303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1330730303
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/41.edn_disable.2633273319
Short name T195
Test name
Test status
Simulation time 13908050 ps
CPU time 0.92 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 216352 kb
Host smart-650f5156-a480-4d66-affa-27f47256b8f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633273319 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2633273319
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/11.edn_intr.4171256304
Short name T38
Test name
Test status
Simulation time 27812250 ps
CPU time 0.92 seconds
Started Jun 06 02:39:01 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 215796 kb
Host smart-4c52e5e5-7513-4852-8a1d-150dfe8992e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171256304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4171256304
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/2.edn_alert.3775647274
Short name T89
Test name
Test status
Simulation time 74496905 ps
CPU time 1.06 seconds
Started Jun 06 02:38:34 PM PDT 24
Finished Jun 06 02:38:36 PM PDT 24
Peak memory 218116 kb
Host smart-578b0112-7840-4ecc-a9c3-391faaf8a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775647274 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.3775647274
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.867339107
Short name T117
Test name
Test status
Simulation time 106555357 ps
CPU time 1.25 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 218048 kb
Host smart-e22d5a6e-d729-4e35-94fe-16732cfb0417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867339107 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.867339107
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert.3129088582
Short name T153
Test name
Test status
Simulation time 39711157 ps
CPU time 1.09 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 215532 kb
Host smart-aa3a6978-f58c-4b47-bf3b-95062fd40cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129088582 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3129088582
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/226.edn_genbits.2031698541
Short name T273
Test name
Test status
Simulation time 48306732 ps
CPU time 1.29 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 216824 kb
Host smart-9d787fc7-52a9-4dee-8c9a-556539679ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031698541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2031698541
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3435844294
Short name T34
Test name
Test status
Simulation time 25226233 ps
CPU time 0.85 seconds
Started Jun 06 02:39:46 PM PDT 24
Finished Jun 06 02:39:49 PM PDT 24
Peak memory 215544 kb
Host smart-fceed50a-9651-4286-a944-7ad2fe6afa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435844294 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3435844294
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/30.edn_disable.1039289002
Short name T177
Test name
Test status
Simulation time 29003992 ps
CPU time 0.8 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 216176 kb
Host smart-c83f66a8-89e3-4906-bafb-16addcf2b724
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039289002 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1039289002
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable.1069242850
Short name T200
Test name
Test status
Simulation time 11436698 ps
CPU time 0.9 seconds
Started Jun 06 02:39:55 PM PDT 24
Finished Jun 06 02:39:58 PM PDT 24
Peak memory 215520 kb
Host smart-bba193f4-521e-4860-a727-513bc842d754
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069242850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1069242850
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.2231563688
Short name T157
Test name
Test status
Simulation time 10522895 ps
CPU time 0.89 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:38 PM PDT 24
Peak memory 216144 kb
Host smart-46af69d5-85cd-4b79-b308-cf75d69f69ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231563688 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2231563688
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.677466100
Short name T519
Test name
Test status
Simulation time 106682417 ps
CPU time 1.04 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:39 PM PDT 24
Peak memory 218440 kb
Host smart-f040f903-22af-486e-8be7-63daed0e8c1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677466100 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.677466100
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_alert.611058128
Short name T96
Test name
Test status
Simulation time 40138066 ps
CPU time 1.2 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 218288 kb
Host smart-6be766d5-9036-4beb-86a4-2390d1c3b525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611058128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.611058128
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable.1348396588
Short name T179
Test name
Test status
Simulation time 53762915 ps
CPU time 0.86 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 216284 kb
Host smart-f2f2d2b1-a567-4b80-ad17-c9b18df5a929
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348396588 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1348396588
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_alert.1782383200
Short name T123
Test name
Test status
Simulation time 23169608 ps
CPU time 1.14 seconds
Started Jun 06 02:39:04 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 220136 kb
Host smart-c1cfcb37-7c66-4fb7-8dbe-e9a5ce43215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782383200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1782383200
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2838803898
Short name T189
Test name
Test status
Simulation time 16433247 ps
CPU time 0.84 seconds
Started Jun 06 02:39:11 PM PDT 24
Finished Jun 06 02:39:14 PM PDT 24
Peak memory 216128 kb
Host smart-755192d6-754f-4b72-a7f3-c2b71b2dcf60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838803898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2838803898
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.2430371344
Short name T191
Test name
Test status
Simulation time 14398217 ps
CPU time 0.86 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 216292 kb
Host smart-fa2f4c17-465b-44af-a2eb-179ea6ee7769
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430371344 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2430371344
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2792233607
Short name T132
Test name
Test status
Simulation time 47092389 ps
CPU time 1.05 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 216764 kb
Host smart-19b25edf-09f0-4ca8-8a69-0a810d613cd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792233607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2792233607
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3199213319
Short name T106
Test name
Test status
Simulation time 47564518 ps
CPU time 1.47 seconds
Started Jun 06 02:39:18 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 216656 kb
Host smart-8cc9e482-f51e-4a66-95c4-9372e0f76035
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199213319 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3199213319
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3296755911
Short name T176
Test name
Test status
Simulation time 53964351 ps
CPU time 1.1 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 219156 kb
Host smart-f95b830e-7658-492b-ac72-394dfbcc012e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296755911 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3296755911
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3910216894
Short name T171
Test name
Test status
Simulation time 64641338 ps
CPU time 0.85 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:28 PM PDT 24
Peak memory 218312 kb
Host smart-0fd17e5f-dc4b-4ca7-9786-e086126c0121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910216894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3910216894
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/26.edn_alert.3876899401
Short name T85
Test name
Test status
Simulation time 41559959 ps
CPU time 1.19 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 218808 kb
Host smart-17093233-beca-4d57-89c0-e55acd770bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876899401 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3876899401
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/27.edn_disable.441793408
Short name T185
Test name
Test status
Simulation time 53073335 ps
CPU time 0.84 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 216136 kb
Host smart-89850896-da72-4881-970b-2fa0f6c6cdda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441793408 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.441793408
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/44.edn_alert.4194152752
Short name T169
Test name
Test status
Simulation time 47735572 ps
CPU time 1.16 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 218320 kb
Host smart-ead894d8-2e04-46f9-8239-fec8c70dd476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194152752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4194152752
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/63.edn_err.1347835874
Short name T162
Test name
Test status
Simulation time 28930051 ps
CPU time 0.9 seconds
Started Jun 06 02:40:14 PM PDT 24
Finished Jun 06 02:40:19 PM PDT 24
Peak memory 218444 kb
Host smart-c148b283-f1c2-4268-9bb2-ccdac7e6c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347835874 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1347835874
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.3655731773
Short name T54
Test name
Test status
Simulation time 49906559 ps
CPU time 1.24 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 218712 kb
Host smart-02b32446-5a9a-47f0-82cc-8a4c32aa89ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655731773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3655731773
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/77.edn_genbits.1999654476
Short name T48
Test name
Test status
Simulation time 39080240 ps
CPU time 1.71 seconds
Started Jun 06 02:40:15 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 218132 kb
Host smart-0792ed08-b0f8-403b-a016-5f42b7e1e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999654476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1999654476
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1164382025
Short name T70
Test name
Test status
Simulation time 69029214 ps
CPU time 2.26 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 219812 kb
Host smart-da0383b0-5e03-457a-833a-70cbc4f3789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164382025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1164382025
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.738260771
Short name T380
Test name
Test status
Simulation time 13369597 ps
CPU time 0.87 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 214664 kb
Host smart-0ec0bf1a-6af8-415c-8e38-59831a266e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738260771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.738260771
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_genbits.3063619465
Short name T15
Test name
Test status
Simulation time 55909178 ps
CPU time 1.32 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 218480 kb
Host smart-7f7d15de-f9cf-45ce-9158-f09eca75dc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063619465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3063619465
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3087773384
Short name T267
Test name
Test status
Simulation time 496975443 ps
CPU time 2.83 seconds
Started Jun 06 02:19:47 PM PDT 24
Finished Jun 06 02:19:51 PM PDT 24
Peak memory 206448 kb
Host smart-5048f692-2145-4658-bd43-bbc0ad9e4017
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087773384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3087773384
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/139.edn_genbits.818516772
Short name T3
Test name
Test status
Simulation time 88428673 ps
CPU time 1.16 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 216820 kb
Host smart-c4378c7a-718e-4d91-bf99-d1d46251fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818516772 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.818516772
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1290426643
Short name T288
Test name
Test status
Simulation time 31302309 ps
CPU time 1.15 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218212 kb
Host smart-e260c6af-6af3-4df8-b39a-fd81c2658bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290426643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1290426643
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3516796560
Short name T308
Test name
Test status
Simulation time 47316426 ps
CPU time 1.14 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 216816 kb
Host smart-d2dd62f7-1684-4048-8d24-ec0429d7a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516796560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3516796560
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.240355689
Short name T79
Test name
Test status
Simulation time 19822374 ps
CPU time 1.04 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 215724 kb
Host smart-10a2e109-a0fa-464e-ba2f-5a55cfeb216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240355689 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.240355689
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/208.edn_genbits.112824541
Short name T284
Test name
Test status
Simulation time 45744462 ps
CPU time 1.54 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 218072 kb
Host smart-bab7f1b5-167a-4419-ae8f-c2707c1cc2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112824541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.112824541
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3842305579
Short name T239
Test name
Test status
Simulation time 38666410 ps
CPU time 0.86 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206360 kb
Host smart-7c451cfb-8928-4564-9040-7c59aab4eafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842305579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3842305579
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/default/104.edn_genbits.1627544973
Short name T783
Test name
Test status
Simulation time 60518185 ps
CPU time 1.37 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218248 kb
Host smart-5534dfb8-2561-49ad-8445-9d2940cce40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627544973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1627544973
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.300968023
Short name T822
Test name
Test status
Simulation time 42849794 ps
CPU time 1.38 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 216928 kb
Host smart-2b220842-94fa-469c-971a-99681db29f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300968023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.300968023
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2097990717
Short name T515
Test name
Test status
Simulation time 41384811 ps
CPU time 1.56 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218004 kb
Host smart-2e9fd574-df50-4228-8eb5-00e81fed902e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097990717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2097990717
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3497178164
Short name T275
Test name
Test status
Simulation time 116755472 ps
CPU time 1.75 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 217256 kb
Host smart-7a2622d7-a8b8-4bf6-8124-e5d027b4b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497178164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3497178164
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3727288791
Short name T84
Test name
Test status
Simulation time 26687979 ps
CPU time 1.28 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 218204 kb
Host smart-49f506e2-0d8c-4486-a8c4-62f8bb3372fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727288791 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3727288791
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/227.edn_genbits.3461078188
Short name T285
Test name
Test status
Simulation time 47137006 ps
CPU time 1.29 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 218252 kb
Host smart-a85b129d-7cfd-411f-9318-9ec1ae2110ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461078188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3461078188
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_genbits.161895610
Short name T287
Test name
Test status
Simulation time 71737503 ps
CPU time 1.54 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:29 PM PDT 24
Peak memory 218252 kb
Host smart-3e4d9e65-8b50-4d03-a423-ba6b4095f90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161895610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.161895610
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_alert.1937680918
Short name T87
Test name
Test status
Simulation time 27278679 ps
CPU time 1.22 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 218660 kb
Host smart-94db3e7f-ea2f-4e7a-9322-e23c6275b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937680918 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1937680918
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/64.edn_genbits.2744216398
Short name T281
Test name
Test status
Simulation time 34752664 ps
CPU time 1.56 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 218224 kb
Host smart-4b2beeea-51eb-41fb-a50a-e3b9c9c75722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744216398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2744216398
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.352323766
Short name T299
Test name
Test status
Simulation time 33378541 ps
CPU time 0.99 seconds
Started Jun 06 02:39:01 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 206968 kb
Host smart-70ca47b9-9da4-40db-b9d3-bba92365859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352323766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.352323766
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/19.edn_intr.2434098438
Short name T41
Test name
Test status
Simulation time 48354697 ps
CPU time 0.84 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 215556 kb
Host smart-d4e4d420-02af-4dcc-be2d-d847a053219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434098438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2434098438
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/10.edn_err.2406389652
Short name T125
Test name
Test status
Simulation time 32434231 ps
CPU time 1.03 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 219664 kb
Host smart-8a56d712-72a8-49f1-92ec-0982f471fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406389652 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2406389652
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/101.edn_genbits.429749917
Short name T813
Test name
Test status
Simulation time 38639264 ps
CPU time 1.53 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:39 PM PDT 24
Peak memory 219168 kb
Host smart-77d7c6b2-9960-4006-ae73-1ece5805b25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429749917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.429749917
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1387454951
Short name T892
Test name
Test status
Simulation time 72571784 ps
CPU time 1.08 seconds
Started Jun 06 02:19:44 PM PDT 24
Finished Jun 06 02:19:46 PM PDT 24
Peak memory 206248 kb
Host smart-35b9368d-a025-427d-b1b2-0be5ec04fad2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387454951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1387454951
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1355626160
Short name T236
Test name
Test status
Simulation time 229716624 ps
CPU time 3.18 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 206312 kb
Host smart-063b14af-4eb9-42d7-bad5-f3e8674bfaae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355626160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1355626160
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1834793026
Short name T229
Test name
Test status
Simulation time 42337808 ps
CPU time 0.83 seconds
Started Jun 06 02:19:37 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 205952 kb
Host smart-daad0f5f-3937-4f79-bb54-5089b5eeac08
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834793026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1834793026
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.843008547
Short name T878
Test name
Test status
Simulation time 23214056 ps
CPU time 1.09 seconds
Started Jun 06 02:19:36 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 214808 kb
Host smart-3cd6f2c5-1172-4c7a-9db0-588025db7a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843008547 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.843008547
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3264963262
Short name T891
Test name
Test status
Simulation time 98757052 ps
CPU time 0.87 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206176 kb
Host smart-bd9ab8f5-202d-4160-a4ab-5706e5ed193a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264963262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3264963262
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2339739997
Short name T903
Test name
Test status
Simulation time 12385954 ps
CPU time 0.83 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 206060 kb
Host smart-3dee74d1-bfd5-43ac-947d-2fbda3f87122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339739997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2339739997
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3294818434
Short name T963
Test name
Test status
Simulation time 149435054 ps
CPU time 1.37 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206352 kb
Host smart-018de0fc-9978-4b85-bab9-9a12356bec3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294818434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3294818434
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2446633168
Short name T925
Test name
Test status
Simulation time 87148735 ps
CPU time 1.53 seconds
Started Jun 06 02:19:33 PM PDT 24
Finished Jun 06 02:19:35 PM PDT 24
Peak memory 214504 kb
Host smart-1bb91fb1-f133-4b75-abc1-5fb4e96bc61a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446633168 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2446633168
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.992074457
Short name T270
Test name
Test status
Simulation time 47820649 ps
CPU time 1.55 seconds
Started Jun 06 02:19:37 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 206496 kb
Host smart-15983485-8733-4356-8217-c0be2a006bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992074457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.992074457
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2737061255
Short name T234
Test name
Test status
Simulation time 43481084 ps
CPU time 1.15 seconds
Started Jun 06 02:19:39 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 206204 kb
Host smart-59d8a403-e228-4270-a367-294b8ac2a8c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737061255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2737061255
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3571919528
Short name T922
Test name
Test status
Simulation time 711500195 ps
CPU time 5.83 seconds
Started Jun 06 02:19:32 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 206240 kb
Host smart-f33547b7-03e0-42e0-a186-f373421bdf53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571919528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3571919528
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.4020978109
Short name T881
Test name
Test status
Simulation time 76205087 ps
CPU time 0.98 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206360 kb
Host smart-94efd31c-4868-433f-a5f7-d753ec3e4abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020978109 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.4020978109
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.2554247917
Short name T895
Test name
Test status
Simulation time 52318193 ps
CPU time 0.89 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206160 kb
Host smart-a5743e6a-1e01-4cc8-b095-a58111eec581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554247917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.2554247917
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1567724923
Short name T912
Test name
Test status
Simulation time 39586688 ps
CPU time 0.82 seconds
Started Jun 06 02:19:37 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 205928 kb
Host smart-2edb2f75-6316-4835-81b5-8f02244b1efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567724923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1567724923
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2379015035
Short name T953
Test name
Test status
Simulation time 53348296 ps
CPU time 1.42 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 206324 kb
Host smart-a8184765-c41e-4899-bf35-c322d03fc973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379015035 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2379015035
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3628063096
Short name T843
Test name
Test status
Simulation time 35348457 ps
CPU time 2.27 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 222696 kb
Host smart-3df8ed24-3ec5-486b-a30c-e2a9ca94607c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628063096 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3628063096
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2070607299
Short name T853
Test name
Test status
Simulation time 141492437 ps
CPU time 1.41 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 214612 kb
Host smart-20e7e5d2-7eae-448f-ab77-43d40e54e0f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070607299 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2070607299
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3199843660
Short name T850
Test name
Test status
Simulation time 41542277 ps
CPU time 0.82 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 205924 kb
Host smart-4f40731c-eded-40a7-9087-15b981324596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199843660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3199843660
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.962515658
Short name T860
Test name
Test status
Simulation time 31421063 ps
CPU time 0.76 seconds
Started Jun 06 02:19:47 PM PDT 24
Finished Jun 06 02:19:49 PM PDT 24
Peak memory 205920 kb
Host smart-eed95705-6afc-4114-b03b-518baa2b3be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962515658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.962515658
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1517629918
Short name T948
Test name
Test status
Simulation time 33783359 ps
CPU time 1.43 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:45 PM PDT 24
Peak memory 206428 kb
Host smart-51fc2bc5-6893-4bff-a758-0dc6fabb6522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517629918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.1517629918
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1547532693
Short name T945
Test name
Test status
Simulation time 92844806 ps
CPU time 3.41 seconds
Started Jun 06 02:19:40 PM PDT 24
Finished Jun 06 02:19:45 PM PDT 24
Peak memory 214484 kb
Host smart-07a44f1a-acf8-4301-ab53-c2957831e67c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547532693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1547532693
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1816923511
Short name T257
Test name
Test status
Simulation time 84193254 ps
CPU time 1.52 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 214544 kb
Host smart-f3306af2-b5ba-4715-bd6c-0bbef520a47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816923511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1816923511
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2732280219
Short name T842
Test name
Test status
Simulation time 17341816 ps
CPU time 1.07 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 214620 kb
Host smart-8d1a637f-cec5-4d81-a7f3-dc32362714fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732280219 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2732280219
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3093854094
Short name T885
Test name
Test status
Simulation time 40340138 ps
CPU time 0.84 seconds
Started Jun 06 02:19:50 PM PDT 24
Finished Jun 06 02:19:51 PM PDT 24
Peak memory 205988 kb
Host smart-d57eea03-83f7-40e3-b19f-9bee4097c71d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093854094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3093854094
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2031162928
Short name T950
Test name
Test status
Simulation time 59618862 ps
CPU time 0.88 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 206132 kb
Host smart-ce482941-5301-4f91-aa0a-d42a9087b378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031162928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2031162928
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3669151944
Short name T934
Test name
Test status
Simulation time 36611786 ps
CPU time 1.11 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206504 kb
Host smart-50051c65-d950-45d4-b48b-792e32254f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669151944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3669151944
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2699962287
Short name T865
Test name
Test status
Simulation time 201720174 ps
CPU time 2.22 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:53 PM PDT 24
Peak memory 214516 kb
Host smart-6fe6e981-08bb-43a2-bb4c-132db32e2a38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699962287 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2699962287
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.986198620
Short name T946
Test name
Test status
Simulation time 186637188 ps
CPU time 1.68 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 206328 kb
Host smart-624dc342-d5e3-44d3-a425-610af40765be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986198620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.986198620
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1637712736
Short name T929
Test name
Test status
Simulation time 46199710 ps
CPU time 1.21 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 214580 kb
Host smart-a24f1871-8222-4ad6-b60d-bf7a7860a01a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637712736 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1637712736
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1052868673
Short name T966
Test name
Test status
Simulation time 28558146 ps
CPU time 0.76 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 205920 kb
Host smart-da78f27c-a657-4f12-8882-d48d64df65dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052868673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1052868673
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2470043593
Short name T959
Test name
Test status
Simulation time 40038511 ps
CPU time 1.49 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:52 PM PDT 24
Peak memory 206484 kb
Host smart-3f29528d-051e-47af-a92f-039115ebd687
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470043593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2470043593
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2795219852
Short name T847
Test name
Test status
Simulation time 37160319 ps
CPU time 2.41 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 214636 kb
Host smart-bb9b9641-99d3-4773-b40d-aa877f57b92a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795219852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2795219852
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.295885002
Short name T883
Test name
Test status
Simulation time 98716132 ps
CPU time 1.32 seconds
Started Jun 06 02:19:45 PM PDT 24
Finished Jun 06 02:19:47 PM PDT 24
Peak memory 214660 kb
Host smart-75dcfd02-61ce-4fe7-8d7e-38426694ced2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295885002 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.295885002
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.4138909443
Short name T235
Test name
Test status
Simulation time 36291155 ps
CPU time 0.85 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 206260 kb
Host smart-67fadaa5-4fb8-4b74-8674-d4689be2dde0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138909443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.4138909443
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1199317031
Short name T933
Test name
Test status
Simulation time 13264387 ps
CPU time 0.9 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206084 kb
Host smart-0b97bc27-ee4b-4193-9978-df3b7026b0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199317031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1199317031
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3285421121
Short name T244
Test name
Test status
Simulation time 27772247 ps
CPU time 1.04 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 206220 kb
Host smart-02532e0b-28c7-4494-8673-1db564606e1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285421121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3285421121
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3698008431
Short name T911
Test name
Test status
Simulation time 1656563603 ps
CPU time 3.95 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 214576 kb
Host smart-bae321ba-c6f7-40a9-a801-f9f12e7a0556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698008431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3698008431
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1122700531
Short name T873
Test name
Test status
Simulation time 193512188 ps
CPU time 2.62 seconds
Started Jun 06 02:19:42 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 206356 kb
Host smart-a67ef389-e251-4ee5-b37b-cba7a196a9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122700531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1122700531
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.161543804
Short name T940
Test name
Test status
Simulation time 20901667 ps
CPU time 1.38 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 214544 kb
Host smart-9b43c87d-6167-4856-acf7-5dddfb848635
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161543804 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.161543804
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.4056986755
Short name T910
Test name
Test status
Simulation time 51465158 ps
CPU time 0.86 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 206144 kb
Host smart-24c1dd0f-1fa0-4b2e-9cf4-8b4dd4c52bba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056986755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.4056986755
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4258840654
Short name T944
Test name
Test status
Simulation time 69474193 ps
CPU time 0.85 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:56 PM PDT 24
Peak memory 205856 kb
Host smart-03b9e5ef-5ced-4b7f-a39d-e00eca55afab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258840654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4258840654
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2739494628
Short name T919
Test name
Test status
Simulation time 21040117 ps
CPU time 1.13 seconds
Started Jun 06 02:19:42 PM PDT 24
Finished Jun 06 02:19:44 PM PDT 24
Peak memory 206356 kb
Host smart-287729a1-264a-4cd6-acd6-a467ae277265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739494628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2739494628
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2574980041
Short name T900
Test name
Test status
Simulation time 281029038 ps
CPU time 4.31 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 214528 kb
Host smart-d370322a-7d51-415f-9954-17bf983e1f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574980041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2574980041
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3200495625
Short name T271
Test name
Test status
Simulation time 367066699 ps
CPU time 2.11 seconds
Started Jun 06 02:19:45 PM PDT 24
Finished Jun 06 02:19:48 PM PDT 24
Peak memory 214512 kb
Host smart-a271acb9-d6f7-4e8e-b33a-1bb73448b50e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200495625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3200495625
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.37107814
Short name T965
Test name
Test status
Simulation time 16994929 ps
CPU time 1.04 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206344 kb
Host smart-0fd27b68-47bb-4147-b80f-1c019017acba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37107814 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.37107814
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.552067805
Short name T901
Test name
Test status
Simulation time 53493824 ps
CPU time 0.99 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 206212 kb
Host smart-b32b9dbb-685b-4dbf-9974-f23ba3b88fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552067805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.552067805
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.769580274
Short name T943
Test name
Test status
Simulation time 36945764 ps
CPU time 0.84 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206056 kb
Host smart-6ccf1511-7d86-438c-8bc0-75109bc3c61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769580274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.769580274
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1374844336
Short name T241
Test name
Test status
Simulation time 15700037 ps
CPU time 0.98 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:46 PM PDT 24
Peak memory 206224 kb
Host smart-e0235e72-abf9-4798-a393-71d5971a7c5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374844336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1374844336
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1116711463
Short name T909
Test name
Test status
Simulation time 273273801 ps
CPU time 3.34 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:12 PM PDT 24
Peak memory 214596 kb
Host smart-d5723f49-ed06-408c-a644-f163312e8521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116711463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1116711463
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.549026819
Short name T890
Test name
Test status
Simulation time 142723482 ps
CPU time 2.22 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206332 kb
Host smart-45a4205c-1e2b-4e02-b8ac-ec807590bbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549026819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.549026819
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.538434742
Short name T947
Test name
Test status
Simulation time 21176113 ps
CPU time 1.17 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 216448 kb
Host smart-2f82fb87-b152-4f5b-b18f-bf1571041f60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538434742 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.538434742
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.148162284
Short name T957
Test name
Test status
Simulation time 22221484 ps
CPU time 0.83 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 206228 kb
Host smart-451691e0-9b0a-43c3-abbf-aa3f7a875266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148162284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.148162284
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2823940611
Short name T849
Test name
Test status
Simulation time 46739205 ps
CPU time 0.87 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:53 PM PDT 24
Peak memory 206156 kb
Host smart-e10bdc30-d042-40fb-a934-7959a76b4fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823940611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2823940611
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3865206606
Short name T961
Test name
Test status
Simulation time 76155117 ps
CPU time 1.48 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 206452 kb
Host smart-490e0aa9-4c0f-4b4e-85a7-9e45706a16cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865206606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3865206606
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3826013886
Short name T861
Test name
Test status
Simulation time 138348684 ps
CPU time 2.42 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:52 PM PDT 24
Peak memory 214548 kb
Host smart-75e538eb-3b45-4110-958e-290e2527c47a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826013886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3826013886
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2901148783
Short name T970
Test name
Test status
Simulation time 161241367 ps
CPU time 2.45 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 214532 kb
Host smart-ef1c0d8c-b05a-4f61-84f6-a93a4b3e153d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901148783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2901148783
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3414384874
Short name T870
Test name
Test status
Simulation time 47373731 ps
CPU time 1.41 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 217696 kb
Host smart-c935ee89-cefb-48e9-8b75-8ccc8d59b713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414384874 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3414384874
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3412986130
Short name T224
Test name
Test status
Simulation time 15222754 ps
CPU time 0.93 seconds
Started Jun 06 02:19:39 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 206224 kb
Host smart-f4b8cc45-140d-4858-97db-bf8714c04a0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412986130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3412986130
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.421960653
Short name T854
Test name
Test status
Simulation time 14986055 ps
CPU time 0.89 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 206132 kb
Host smart-447cb3cc-f615-46b0-af27-504577aea8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421960653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.421960653
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2165704044
Short name T908
Test name
Test status
Simulation time 23411572 ps
CPU time 1.18 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206496 kb
Host smart-c9b88e36-1bce-4153-b0b3-86371251cb48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165704044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2165704044
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1641426949
Short name T897
Test name
Test status
Simulation time 74215062 ps
CPU time 1.75 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:51 PM PDT 24
Peak memory 214696 kb
Host smart-4ba6ef82-b577-4cb4-8a60-630fec6e3d5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641426949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1641426949
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3780946189
Short name T920
Test name
Test status
Simulation time 114121974 ps
CPU time 2.77 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 206316 kb
Host smart-c9cf3ccd-df92-4747-85bf-59bf44885f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780946189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3780946189
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3798918645
Short name T874
Test name
Test status
Simulation time 97982892 ps
CPU time 1.39 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 222668 kb
Host smart-19b2a66d-fb20-4752-9675-c8a3b7a91c41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798918645 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3798918645
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3877403378
Short name T233
Test name
Test status
Simulation time 21308424 ps
CPU time 0.95 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206200 kb
Host smart-5fba8ab8-aa5c-491e-bead-ed2477049bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877403378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3877403378
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.232632789
Short name T913
Test name
Test status
Simulation time 16096789 ps
CPU time 0.88 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206088 kb
Host smart-daa9b4b5-8171-4ce9-8b9f-2c73badc3fac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232632789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.232632789
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3905811176
Short name T243
Test name
Test status
Simulation time 33829898 ps
CPU time 1.08 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:02 PM PDT 24
Peak memory 206316 kb
Host smart-a46dc234-eb27-4b71-b86b-d4db4f34fd41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905811176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3905811176
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.739290454
Short name T868
Test name
Test status
Simulation time 71530754 ps
CPU time 2.76 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 214540 kb
Host smart-db6331a2-585c-497f-955e-29098c2ef6e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739290454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.739290454
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1665333430
Short name T268
Test name
Test status
Simulation time 78921025 ps
CPU time 2.33 seconds
Started Jun 06 02:19:51 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 214560 kb
Host smart-c32a421f-3dae-4d1a-a62d-72a79ac119fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665333430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1665333430
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1972845474
Short name T857
Test name
Test status
Simulation time 49817584 ps
CPU time 0.97 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206416 kb
Host smart-1cdcb368-8d65-4c30-8fa2-8e682e1e71de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972845474 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1972845474
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4058422108
Short name T877
Test name
Test status
Simulation time 15496733 ps
CPU time 0.9 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:46 PM PDT 24
Peak memory 206200 kb
Host smart-f9716086-c940-4bac-b1ca-0288f9efd834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058422108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4058422108
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2682358180
Short name T936
Test name
Test status
Simulation time 16943163 ps
CPU time 0.96 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 206300 kb
Host smart-cd3c5560-60eb-425d-abb0-2fca81368aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682358180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2682358180
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.122692775
Short name T245
Test name
Test status
Simulation time 43210074 ps
CPU time 1.06 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206312 kb
Host smart-9916fb0c-5a1b-4cb6-b82b-1920b8fc72b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122692775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.122692775
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.777540248
Short name T918
Test name
Test status
Simulation time 31504868 ps
CPU time 2.07 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 214492 kb
Host smart-6bf0e1ea-daf6-4bfe-82b9-4843e0a27b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777540248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.777540248
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1477474839
Short name T899
Test name
Test status
Simulation time 95158480 ps
CPU time 1.65 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:03 PM PDT 24
Peak memory 206292 kb
Host smart-9f8c2c0e-4989-4e97-b071-3f4845a05200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477474839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1477474839
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.10823445
Short name T227
Test name
Test status
Simulation time 70313227 ps
CPU time 1.53 seconds
Started Jun 06 02:19:44 PM PDT 24
Finished Jun 06 02:19:47 PM PDT 24
Peak memory 206096 kb
Host smart-dd99250d-7619-44ea-94e4-7b0c5741bfe0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10823445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.10823445
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2402608753
Short name T955
Test name
Test status
Simulation time 93854884 ps
CPU time 2.96 seconds
Started Jun 06 02:19:32 PM PDT 24
Finished Jun 06 02:19:36 PM PDT 24
Peak memory 206196 kb
Host smart-ec62f742-13c3-4417-a605-95213fd951ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402608753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2402608753
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1780823
Short name T894
Test name
Test status
Simulation time 22911275 ps
CPU time 0.86 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:46 PM PDT 24
Peak memory 206416 kb
Host smart-7d461f63-2a77-4c04-b0d1-0375098664cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1780823
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1917706622
Short name T858
Test name
Test status
Simulation time 43739016 ps
CPU time 1.53 seconds
Started Jun 06 02:19:48 PM PDT 24
Finished Jun 06 02:19:50 PM PDT 24
Peak memory 214504 kb
Host smart-6b9b948f-7819-4404-9513-0c9135a2386f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917706622 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1917706622
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.4154112799
Short name T232
Test name
Test status
Simulation time 21995282 ps
CPU time 0.87 seconds
Started Jun 06 02:19:28 PM PDT 24
Finished Jun 06 02:19:29 PM PDT 24
Peak memory 206420 kb
Host smart-eded5f38-a519-4344-baf0-f3a34b823f15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154112799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.4154112799
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.237778607
Short name T864
Test name
Test status
Simulation time 20825430 ps
CPU time 0.85 seconds
Started Jun 06 02:19:50 PM PDT 24
Finished Jun 06 02:19:52 PM PDT 24
Peak memory 206168 kb
Host smart-be430100-85ee-49cb-85f3-117e9a3982d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237778607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.237778607
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2932214101
Short name T238
Test name
Test status
Simulation time 19508044 ps
CPU time 1.23 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206368 kb
Host smart-18627144-6d4e-4d55-ba01-44dfa94e5d63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932214101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2932214101
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3164594232
Short name T949
Test name
Test status
Simulation time 70784719 ps
CPU time 3.77 seconds
Started Jun 06 02:19:40 PM PDT 24
Finished Jun 06 02:19:45 PM PDT 24
Peak memory 214476 kb
Host smart-667a8b14-3c72-42c5-b218-a8ba9bd0b02a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164594232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3164594232
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.476942959
Short name T958
Test name
Test status
Simulation time 207118017 ps
CPU time 1.49 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 206392 kb
Host smart-1b351582-ff92-42fd-9a5b-0a83ac9efc88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476942959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.476942959
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.825486704
Short name T888
Test name
Test status
Simulation time 26864272 ps
CPU time 0.89 seconds
Started Jun 06 02:19:47 PM PDT 24
Finished Jun 06 02:19:48 PM PDT 24
Peak memory 206152 kb
Host smart-b84a5231-d472-43be-874f-d8e0e4092c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825486704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.825486704
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1947686599
Short name T904
Test name
Test status
Simulation time 26589815 ps
CPU time 0.87 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:51 PM PDT 24
Peak memory 206096 kb
Host smart-cab90dfb-414a-4255-a55c-027c71effcf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947686599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1947686599
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3298243127
Short name T845
Test name
Test status
Simulation time 22122483 ps
CPU time 0.86 seconds
Started Jun 06 02:19:53 PM PDT 24
Finished Jun 06 02:19:55 PM PDT 24
Peak memory 206116 kb
Host smart-a32eca7a-6c9a-466f-81c8-a4d575a4e664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298243127 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3298243127
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.753190043
Short name T840
Test name
Test status
Simulation time 14859890 ps
CPU time 0.91 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 206088 kb
Host smart-de57d601-d6db-4040-9887-2573134f5012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753190043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.753190043
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.916551276
Short name T839
Test name
Test status
Simulation time 40649260 ps
CPU time 0.86 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 206040 kb
Host smart-00957c82-128a-4926-aa5c-8b9a96463527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916551276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.916551276
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3168475736
Short name T898
Test name
Test status
Simulation time 33977358 ps
CPU time 0.8 seconds
Started Jun 06 02:20:06 PM PDT 24
Finished Jun 06 02:20:09 PM PDT 24
Peak memory 205956 kb
Host smart-010b44cc-bac6-4aa5-80a7-6792f45cd094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168475736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3168475736
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1324945864
Short name T939
Test name
Test status
Simulation time 13866063 ps
CPU time 0.85 seconds
Started Jun 06 02:19:59 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 206220 kb
Host smart-4b82a86c-f7b4-43cb-99cf-7f4f5625135e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324945864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1324945864
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.551645178
Short name T905
Test name
Test status
Simulation time 15453892 ps
CPU time 0.89 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 206256 kb
Host smart-f00fd6b6-911c-46b2-9820-b3285fc5edad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551645178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.551645178
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.4176743504
Short name T841
Test name
Test status
Simulation time 107124374 ps
CPU time 0.88 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 206100 kb
Host smart-6fc7fdb1-bf07-4110-95e9-30d9d6a13d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176743504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.4176743504
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1147613095
Short name T856
Test name
Test status
Simulation time 52235454 ps
CPU time 0.83 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 206116 kb
Host smart-b0274d63-5573-48a7-b5a8-10740a4a8a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147613095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1147613095
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3211986298
Short name T880
Test name
Test status
Simulation time 37255026 ps
CPU time 1.27 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206228 kb
Host smart-bf211f2f-dc23-4c52-a99b-ee6fab71073c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211986298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3211986298
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1138362386
Short name T882
Test name
Test status
Simulation time 519921043 ps
CPU time 6.23 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 206308 kb
Host smart-e08673f2-bd6a-43fb-a646-280bdb626e23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138362386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1138362386
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2607555541
Short name T926
Test name
Test status
Simulation time 16525241 ps
CPU time 0.92 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206184 kb
Host smart-c1a459e9-323e-4fa2-9987-468f5f1ccf88
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607555541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2607555541
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.627882092
Short name T921
Test name
Test status
Simulation time 17245305 ps
CPU time 1.03 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206284 kb
Host smart-8005c9b5-66b7-43b4-85c9-1e49d9d9731e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627882092 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.627882092
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2487968432
Short name T914
Test name
Test status
Simulation time 64896582 ps
CPU time 0.87 seconds
Started Jun 06 02:19:30 PM PDT 24
Finished Jun 06 02:19:31 PM PDT 24
Peak memory 206304 kb
Host smart-9e2327d5-df09-41e2-8124-4965d370f7e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487968432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2487968432
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3886199490
Short name T927
Test name
Test status
Simulation time 25407196 ps
CPU time 0.98 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206148 kb
Host smart-f5528919-bd6f-443b-9249-ff80c5e3e3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886199490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3886199490
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.2874435457
Short name T889
Test name
Test status
Simulation time 58588689 ps
CPU time 1.05 seconds
Started Jun 06 02:19:36 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 206292 kb
Host smart-381b826b-3eb9-4451-9578-5af066e6141c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874435457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.2874435457
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1241457675
Short name T872
Test name
Test status
Simulation time 271345727 ps
CPU time 2.88 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:47 PM PDT 24
Peak memory 214600 kb
Host smart-98cd8d8f-e8ac-4548-afcf-245ccc5a8606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241457675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1241457675
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3670691473
Short name T269
Test name
Test status
Simulation time 183948486 ps
CPU time 1.63 seconds
Started Jun 06 02:19:34 PM PDT 24
Finished Jun 06 02:19:47 PM PDT 24
Peak memory 206372 kb
Host smart-d437675a-850f-4af4-8956-17d5c8a1a41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670691473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3670691473
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.75386066
Short name T851
Test name
Test status
Simulation time 19034302 ps
CPU time 0.89 seconds
Started Jun 06 02:19:54 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206228 kb
Host smart-24d38142-4bf6-4a7c-bc9a-5c1fcebd61d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75386066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.75386066
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.4125690842
Short name T932
Test name
Test status
Simulation time 25199895 ps
CPU time 0.83 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 206132 kb
Host smart-0def3cf6-560a-4b41-81cb-2655eaa14ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125690842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.4125690842
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.83420956
Short name T852
Test name
Test status
Simulation time 17222870 ps
CPU time 0.91 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:05 PM PDT 24
Peak memory 206152 kb
Host smart-ce90780f-d29b-4d95-839e-c3a8a621752a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83420956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.83420956
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1077684295
Short name T876
Test name
Test status
Simulation time 14445554 ps
CPU time 0.82 seconds
Started Jun 06 02:20:05 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 206124 kb
Host smart-230ff588-b364-47a3-b55a-6c3a3d687b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077684295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1077684295
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3204810380
Short name T896
Test name
Test status
Simulation time 18679537 ps
CPU time 0.87 seconds
Started Jun 06 02:19:56 PM PDT 24
Finished Jun 06 02:19:58 PM PDT 24
Peak memory 206112 kb
Host smart-a568080a-d413-4801-9045-cfa98649996b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204810380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3204810380
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.140674501
Short name T956
Test name
Test status
Simulation time 50325219 ps
CPU time 0.77 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:01 PM PDT 24
Peak memory 205896 kb
Host smart-bce80f02-67e4-4d3b-b5e5-befb9df3085c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140674501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.140674501
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1505344093
Short name T962
Test name
Test status
Simulation time 38616435 ps
CPU time 0.89 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 206156 kb
Host smart-4a873385-a98d-4e57-89f9-34380240f4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505344093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1505344093
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1655269364
Short name T931
Test name
Test status
Simulation time 17180622 ps
CPU time 0.9 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:03 PM PDT 24
Peak memory 206284 kb
Host smart-ea7ad896-0435-421b-8414-f1631766d8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655269364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1655269364
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1041010156
Short name T967
Test name
Test status
Simulation time 24435387 ps
CPU time 0.87 seconds
Started Jun 06 02:19:55 PM PDT 24
Finished Jun 06 02:19:57 PM PDT 24
Peak memory 206160 kb
Host smart-dfe14962-0163-4cb4-b953-cb217cf4f8f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041010156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1041010156
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.990203648
Short name T867
Test name
Test status
Simulation time 20100532 ps
CPU time 0.78 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:03 PM PDT 24
Peak memory 205920 kb
Host smart-c50cf3c4-9107-44f2-a1b1-d5de577791e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990203648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.990203648
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.966066528
Short name T225
Test name
Test status
Simulation time 152773123 ps
CPU time 1.53 seconds
Started Jun 06 02:19:46 PM PDT 24
Finished Jun 06 02:19:49 PM PDT 24
Peak memory 206192 kb
Host smart-cb16caa0-1d80-40a7-beed-d69c0afcf61d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966066528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.966066528
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1734526652
Short name T968
Test name
Test status
Simulation time 262966545 ps
CPU time 3.53 seconds
Started Jun 06 02:19:28 PM PDT 24
Finished Jun 06 02:19:32 PM PDT 24
Peak memory 206156 kb
Host smart-60043305-dd24-40c5-921f-41ecfcc67c5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734526652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1734526652
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3797477446
Short name T848
Test name
Test status
Simulation time 46561901 ps
CPU time 0.86 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:45 PM PDT 24
Peak memory 206108 kb
Host smart-42b3b49f-c2f9-4415-bfbf-3605a7c983d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797477446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3797477446
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.61409266
Short name T884
Test name
Test status
Simulation time 50986680 ps
CPU time 1.01 seconds
Started Jun 06 02:19:34 PM PDT 24
Finished Jun 06 02:19:36 PM PDT 24
Peak memory 215644 kb
Host smart-22158049-40cb-45c7-8117-0349c496750e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61409266 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.61409266
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1179908810
Short name T230
Test name
Test status
Simulation time 13940494 ps
CPU time 0.89 seconds
Started Jun 06 02:19:37 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 206152 kb
Host smart-a0a1a454-3cd9-4db2-9e1a-1cf7ce41de21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179908810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1179908810
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1920560892
Short name T969
Test name
Test status
Simulation time 14138914 ps
CPU time 0.89 seconds
Started Jun 06 02:19:41 PM PDT 24
Finished Jun 06 02:19:43 PM PDT 24
Peak memory 206108 kb
Host smart-f0a585ff-7f97-4e01-809c-48e691558858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920560892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1920560892
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3908622833
Short name T930
Test name
Test status
Simulation time 182534540 ps
CPU time 1.02 seconds
Started Jun 06 02:19:37 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 206352 kb
Host smart-d4e90693-3775-4389-aebd-e402519e8815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908622833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3908622833
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2164758843
Short name T846
Test name
Test status
Simulation time 78525489 ps
CPU time 3.16 seconds
Started Jun 06 02:19:32 PM PDT 24
Finished Jun 06 02:19:37 PM PDT 24
Peak memory 214668 kb
Host smart-1b23bff2-a98e-46ea-af4d-b9cfad69320d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164758843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2164758843
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.4187782728
Short name T862
Test name
Test status
Simulation time 322973492 ps
CPU time 1.62 seconds
Started Jun 06 02:19:36 PM PDT 24
Finished Jun 06 02:19:39 PM PDT 24
Peak memory 206380 kb
Host smart-5987000c-413e-497d-b4b9-442792813b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187782728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.4187782728
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1682668652
Short name T866
Test name
Test status
Simulation time 43025903 ps
CPU time 0.85 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 206124 kb
Host smart-7761869b-7d70-4a68-a13e-3f504baf4f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682668652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1682668652
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3737195165
Short name T907
Test name
Test status
Simulation time 14946161 ps
CPU time 0.94 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 206296 kb
Host smart-aba652c1-a418-4025-8441-748e7840858e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737195165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3737195165
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2367112740
Short name T964
Test name
Test status
Simulation time 12926633 ps
CPU time 0.88 seconds
Started Jun 06 02:20:01 PM PDT 24
Finished Jun 06 02:20:02 PM PDT 24
Peak memory 206124 kb
Host smart-3ec68ec6-7318-455c-a4cd-040459a9a265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367112740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2367112740
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2041606003
Short name T935
Test name
Test status
Simulation time 16858118 ps
CPU time 0.93 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 206156 kb
Host smart-338e20ad-7f61-4081-971a-d182e800d6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041606003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2041606003
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1339246850
Short name T971
Test name
Test status
Simulation time 44449795 ps
CPU time 0.87 seconds
Started Jun 06 02:20:02 PM PDT 24
Finished Jun 06 02:20:04 PM PDT 24
Peak memory 206128 kb
Host smart-70430e26-0ffe-41c1-a387-42c27f64a1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339246850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1339246850
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3066607786
Short name T855
Test name
Test status
Simulation time 22755363 ps
CPU time 0.85 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 206360 kb
Host smart-5cf60064-435e-4196-8f05-6f4e273ef4a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066607786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3066607786
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1513259775
Short name T916
Test name
Test status
Simulation time 17365611 ps
CPU time 0.81 seconds
Started Jun 06 02:20:03 PM PDT 24
Finished Jun 06 02:20:06 PM PDT 24
Peak memory 205944 kb
Host smart-26aab043-4dd5-477f-a886-8030712415c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513259775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1513259775
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1047070089
Short name T941
Test name
Test status
Simulation time 11878088 ps
CPU time 0.88 seconds
Started Jun 06 02:20:07 PM PDT 24
Finished Jun 06 02:20:10 PM PDT 24
Peak memory 206116 kb
Host smart-68275562-e4a9-44a7-90af-d56cbb28f6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047070089 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1047070089
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.688295433
Short name T938
Test name
Test status
Simulation time 45336682 ps
CPU time 0.77 seconds
Started Jun 06 02:20:11 PM PDT 24
Finished Jun 06 02:20:14 PM PDT 24
Peak memory 205940 kb
Host smart-ac576d64-5fd4-43af-9489-16ff6999e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688295433 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.688295433
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1409880788
Short name T893
Test name
Test status
Simulation time 19625611 ps
CPU time 0.85 seconds
Started Jun 06 02:19:57 PM PDT 24
Finished Jun 06 02:19:59 PM PDT 24
Peak memory 206168 kb
Host smart-2b42f7ba-6e86-4882-855f-776f28a242a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409880788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1409880788
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.300675869
Short name T928
Test name
Test status
Simulation time 52409808 ps
CPU time 1.97 seconds
Started Jun 06 02:20:04 PM PDT 24
Finished Jun 06 02:20:08 PM PDT 24
Peak memory 214776 kb
Host smart-e223c827-20df-486b-b49a-fc007cfd7e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300675869 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.300675869
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1483864226
Short name T231
Test name
Test status
Simulation time 68336739 ps
CPU time 0.9 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206156 kb
Host smart-e499faab-eacf-4398-80fa-008b99138f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483864226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1483864226
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1291244992
Short name T924
Test name
Test status
Simulation time 18502674 ps
CPU time 0.84 seconds
Started Jun 06 02:19:33 PM PDT 24
Finished Jun 06 02:19:35 PM PDT 24
Peak memory 206088 kb
Host smart-d2145157-18b9-4e52-a6f3-98ab65a6d062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291244992 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1291244992
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4148135581
Short name T237
Test name
Test status
Simulation time 38720783 ps
CPU time 1.06 seconds
Started Jun 06 02:19:47 PM PDT 24
Finished Jun 06 02:19:49 PM PDT 24
Peak memory 206336 kb
Host smart-da29d67d-6730-4de7-8d41-fb30b34c600e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148135581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4148135581
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3808229869
Short name T844
Test name
Test status
Simulation time 153950346 ps
CPU time 2.8 seconds
Started Jun 06 02:19:50 PM PDT 24
Finished Jun 06 02:19:53 PM PDT 24
Peak memory 214528 kb
Host smart-4e3226a4-bbac-4fd2-9660-8f4a61a64ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808229869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3808229869
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2039319815
Short name T942
Test name
Test status
Simulation time 181792560 ps
CPU time 3.86 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 206388 kb
Host smart-4e6267a7-d71c-4985-a61e-7cc8e7d07b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039319815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2039319815
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3739361229
Short name T972
Test name
Test status
Simulation time 25227159 ps
CPU time 1.24 seconds
Started Jun 06 02:19:34 PM PDT 24
Finished Jun 06 02:19:37 PM PDT 24
Peak memory 214592 kb
Host smart-907e4e71-5634-4787-a68e-e603562d437d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739361229 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3739361229
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3992470745
Short name T879
Test name
Test status
Simulation time 27090012 ps
CPU time 0.92 seconds
Started Jun 06 02:19:42 PM PDT 24
Finished Jun 06 02:19:44 PM PDT 24
Peak memory 206216 kb
Host smart-dc284aa5-21a3-4fa9-80a2-91f853cce869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992470745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3992470745
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1739719954
Short name T886
Test name
Test status
Simulation time 25081353 ps
CPU time 0.87 seconds
Started Jun 06 02:19:34 PM PDT 24
Finished Jun 06 02:19:36 PM PDT 24
Peak memory 206132 kb
Host smart-8c71ab42-a011-4053-8c1d-e9e25904e711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739719954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1739719954
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1664413557
Short name T915
Test name
Test status
Simulation time 17993483 ps
CPU time 1.16 seconds
Started Jun 06 02:20:00 PM PDT 24
Finished Jun 06 02:20:02 PM PDT 24
Peak memory 206432 kb
Host smart-17533224-c2ae-496c-9b78-04ad622e2508
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664413557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1664413557
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.65460760
Short name T937
Test name
Test status
Simulation time 196539282 ps
CPU time 2.23 seconds
Started Jun 06 02:19:33 PM PDT 24
Finished Jun 06 02:19:36 PM PDT 24
Peak memory 214712 kb
Host smart-98198bde-458b-44e5-8811-76fa10bb24ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65460760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.65460760
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2965477771
Short name T259
Test name
Test status
Simulation time 74689477 ps
CPU time 1.58 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 206292 kb
Host smart-d4d87c7b-9968-4a4b-b800-f1b4083da0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965477771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2965477771
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1043883051
Short name T863
Test name
Test status
Simulation time 84356924 ps
CPU time 1.14 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:45 PM PDT 24
Peak memory 214712 kb
Host smart-bd3f8937-2906-428e-aa60-68312ba2775a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043883051 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1043883051
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3050935336
Short name T923
Test name
Test status
Simulation time 13723462 ps
CPU time 0.84 seconds
Started Jun 06 02:19:52 PM PDT 24
Finished Jun 06 02:19:54 PM PDT 24
Peak memory 206228 kb
Host smart-ded9ebf6-345b-44a4-8af0-e8916bcacbb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050935336 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3050935336
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2031339866
Short name T859
Test name
Test status
Simulation time 19478254 ps
CPU time 0.89 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:40 PM PDT 24
Peak memory 206124 kb
Host smart-fdcff4d0-155b-4d31-8452-1fee2b1bb227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031339866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2031339866
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.366149286
Short name T242
Test name
Test status
Simulation time 36646202 ps
CPU time 1.36 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 206448 kb
Host smart-f27876ee-2633-45a6-ae0c-192300169217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366149286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.366149286
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1214661277
Short name T902
Test name
Test status
Simulation time 486696855 ps
CPU time 2.81 seconds
Started Jun 06 02:19:44 PM PDT 24
Finished Jun 06 02:19:48 PM PDT 24
Peak memory 214476 kb
Host smart-f1d5e9ce-c912-4a1d-bea2-d904d0bc403f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214661277 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1214661277
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1812155676
Short name T258
Test name
Test status
Simulation time 125920548 ps
CPU time 1.63 seconds
Started Jun 06 02:19:50 PM PDT 24
Finished Jun 06 02:19:52 PM PDT 24
Peak memory 206712 kb
Host smart-228543ed-2ead-4924-bd98-fb50ee61ccd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812155676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1812155676
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3138665823
Short name T906
Test name
Test status
Simulation time 90548058 ps
CPU time 1.55 seconds
Started Jun 06 02:19:35 PM PDT 24
Finished Jun 06 02:19:38 PM PDT 24
Peak memory 214500 kb
Host smart-f2e854fd-2dfc-4f02-80d5-7c9f4bdaf2e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138665823 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3138665823
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.425310902
Short name T226
Test name
Test status
Simulation time 37363811 ps
CPU time 0.85 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 205924 kb
Host smart-e4c2ba59-4ea5-437b-9bce-f7a3b31cd600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425310902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.425310902
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.786756810
Short name T952
Test name
Test status
Simulation time 12764831 ps
CPU time 0.85 seconds
Started Jun 06 02:19:43 PM PDT 24
Finished Jun 06 02:19:44 PM PDT 24
Peak memory 206080 kb
Host smart-1b9f6d1a-22dc-4272-861b-c2818407f99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786756810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.786756810
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.4180531784
Short name T240
Test name
Test status
Simulation time 143812182 ps
CPU time 1.13 seconds
Started Jun 06 02:19:51 PM PDT 24
Finished Jun 06 02:19:53 PM PDT 24
Peak memory 206296 kb
Host smart-233549c8-231e-4b09-8795-912222c06ba6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180531784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.4180531784
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.939945800
Short name T960
Test name
Test status
Simulation time 76855814 ps
CPU time 1.86 seconds
Started Jun 06 02:19:49 PM PDT 24
Finished Jun 06 02:19:52 PM PDT 24
Peak memory 214656 kb
Host smart-b92a9f9a-42f3-469e-9e37-13315b5df5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939945800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.939945800
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.160953724
Short name T871
Test name
Test status
Simulation time 601559529 ps
CPU time 1.43 seconds
Started Jun 06 02:19:44 PM PDT 24
Finished Jun 06 02:19:46 PM PDT 24
Peak memory 206500 kb
Host smart-31a7ab01-2d69-4bfd-9630-208a25198279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160953724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.160953724
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.682547138
Short name T917
Test name
Test status
Simulation time 157314937 ps
CPU time 1.57 seconds
Started Jun 06 02:19:38 PM PDT 24
Finished Jun 06 02:19:41 PM PDT 24
Peak memory 214620 kb
Host smart-16a1bff4-d588-4447-af8d-d04ae6b9b2a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682547138 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.682547138
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2928830430
Short name T951
Test name
Test status
Simulation time 12145255 ps
CPU time 0.87 seconds
Started Jun 06 02:19:47 PM PDT 24
Finished Jun 06 02:19:48 PM PDT 24
Peak memory 206164 kb
Host smart-6cfc1dbd-b524-4313-8aab-0c8809f12500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928830430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2928830430
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1434976837
Short name T875
Test name
Test status
Simulation time 11740149 ps
CPU time 0.84 seconds
Started Jun 06 02:19:58 PM PDT 24
Finished Jun 06 02:20:00 PM PDT 24
Peak memory 206108 kb
Host smart-10a4f6f6-3ec1-4e60-a6a9-e0f6cb032f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434976837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1434976837
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.636835210
Short name T887
Test name
Test status
Simulation time 36734989 ps
CPU time 1.4 seconds
Started Jun 06 02:19:39 PM PDT 24
Finished Jun 06 02:19:42 PM PDT 24
Peak memory 206284 kb
Host smart-690cabd7-1e02-4b6a-b33f-a7792c121320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636835210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.636835210
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.578269081
Short name T954
Test name
Test status
Simulation time 154773314 ps
CPU time 2.75 seconds
Started Jun 06 02:19:39 PM PDT 24
Finished Jun 06 02:19:43 PM PDT 24
Peak memory 214488 kb
Host smart-92448c6b-29db-4dbd-9cf1-c5c19a6593f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578269081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.578269081
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2866823780
Short name T869
Test name
Test status
Simulation time 143424732 ps
CPU time 2.4 seconds
Started Jun 06 02:19:46 PM PDT 24
Finished Jun 06 02:19:49 PM PDT 24
Peak memory 206424 kb
Host smart-1829d291-9e43-4389-b32b-6e40a0fa7ae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866823780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2866823780
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3543904641
Short name T88
Test name
Test status
Simulation time 38175951 ps
CPU time 1.12 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 218184 kb
Host smart-67542276-d952-475f-b1fb-e43eaaa1272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543904641 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3543904641
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.2151505871
Short name T748
Test name
Test status
Simulation time 15933525 ps
CPU time 0.89 seconds
Started Jun 06 02:38:35 PM PDT 24
Finished Jun 06 02:38:37 PM PDT 24
Peak memory 206496 kb
Host smart-3e73a8ca-94e5-4cad-9b62-ad34d5b60f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151505871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2151505871
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.2015969361
Short name T568
Test name
Test status
Simulation time 51412640 ps
CPU time 0.87 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 219760 kb
Host smart-c13d7ba7-e09d-4bea-ba95-7eb2ef5ab1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015969361 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2015969361
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3583126439
Short name T725
Test name
Test status
Simulation time 33035144 ps
CPU time 1.29 seconds
Started Jun 06 02:38:40 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 216944 kb
Host smart-bfc2491e-13fd-4e84-b8d1-8a1d1123deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583126439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3583126439
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2871985858
Short name T758
Test name
Test status
Simulation time 21595810 ps
CPU time 1.27 seconds
Started Jun 06 02:38:40 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 224240 kb
Host smart-64ca1f7e-105c-4208-aa5e-b6845973384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871985858 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2871985858
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2360469940
Short name T28
Test name
Test status
Simulation time 31329111 ps
CPU time 0.95 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:39 PM PDT 24
Peak memory 207044 kb
Host smart-9451b4f9-5f07-4d89-a0ce-4db81066c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360469940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2360469940
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1573520642
Short name T63
Test name
Test status
Simulation time 378601814 ps
CPU time 4.4 seconds
Started Jun 06 02:38:35 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 236868 kb
Host smart-8347d005-5259-44b6-a7b2-47c7a530e10c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573520642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1573520642
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3347541901
Short name T388
Test name
Test status
Simulation time 25888319 ps
CPU time 0.87 seconds
Started Jun 06 02:38:40 PM PDT 24
Finished Jun 06 02:38:43 PM PDT 24
Peak memory 215504 kb
Host smart-cfc5e843-8996-4b7b-a15f-97ec22efc898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347541901 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3347541901
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.599042212
Short name T429
Test name
Test status
Simulation time 242161858 ps
CPU time 4 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 216812 kb
Host smart-9e082995-866b-4c44-95b2-ab9fedfec27f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599042212 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.599042212
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3609926702
Short name T448
Test name
Test status
Simulation time 191368229801 ps
CPU time 1032.85 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:55:57 PM PDT 24
Peak memory 221624 kb
Host smart-aadb8292-187f-4ec6-a982-70072f6c43b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609926702 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3609926702
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1027722987
Short name T798
Test name
Test status
Simulation time 12074908 ps
CPU time 0.82 seconds
Started Jun 06 02:38:35 PM PDT 24
Finished Jun 06 02:38:37 PM PDT 24
Peak memory 206288 kb
Host smart-0fae4bfc-8ce8-400c-9d3d-ae7f47fe1173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027722987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1027722987
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1913199431
Short name T223
Test name
Test status
Simulation time 94466216 ps
CPU time 1.09 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 218228 kb
Host smart-094dc776-0deb-423f-bec1-4bf29ce76f8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913199431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1913199431
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3709279241
Short name T143
Test name
Test status
Simulation time 30430759 ps
CPU time 1.34 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:38 PM PDT 24
Peak memory 225736 kb
Host smart-6275ddba-057b-450f-a577-d5c932528bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709279241 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3709279241
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2161162291
Short name T410
Test name
Test status
Simulation time 69166597 ps
CPU time 1.32 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:43 PM PDT 24
Peak memory 218344 kb
Host smart-a87196a5-1d7b-40c3-a498-8f04312d09d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161162291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2161162291
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3525203199
Short name T631
Test name
Test status
Simulation time 21792625 ps
CPU time 1.19 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 223944 kb
Host smart-a938d07e-f9c0-4bf0-b5f7-85241f71b52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525203199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3525203199
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1442267548
Short name T29
Test name
Test status
Simulation time 41109661 ps
CPU time 0.85 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 207000 kb
Host smart-0a9b6e00-87fa-4425-985e-b3884422f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442267548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1442267548
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4106288197
Short name T62
Test name
Test status
Simulation time 2387682072 ps
CPU time 5.18 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:43 PM PDT 24
Peak memory 237720 kb
Host smart-52e0534e-304f-4522-936e-1a912d67b76b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106288197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4106288197
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1246960852
Short name T400
Test name
Test status
Simulation time 52637139 ps
CPU time 0.95 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 215124 kb
Host smart-9be208cb-2fff-4f18-bd07-a11d59567964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246960852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1246960852
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.601867048
Short name T214
Test name
Test status
Simulation time 334465113 ps
CPU time 2.12 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 217120 kb
Host smart-954d3151-d2f8-489d-84ae-0454fa4ddd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601867048 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.601867048
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3602691988
Short name T555
Test name
Test status
Simulation time 46594876186 ps
CPU time 1260.64 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:59:40 PM PDT 24
Peak memory 223652 kb
Host smart-73835586-0504-4fc7-be98-3e2401f746a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602691988 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3602691988
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.3323026229
Short name T526
Test name
Test status
Simulation time 30668837 ps
CPU time 0.93 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:01 PM PDT 24
Peak memory 206512 kb
Host smart-aee04348-2f41-45ff-8ae8-a134c88c1ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323026229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3323026229
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2254363722
Short name T136
Test name
Test status
Simulation time 17734183 ps
CPU time 0.84 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 215320 kb
Host smart-ef4e9f2c-85b3-4f0c-95da-5fc41ace6813
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254363722 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2254363722
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_genbits.4125312391
Short name T781
Test name
Test status
Simulation time 32011609 ps
CPU time 1.27 seconds
Started Jun 06 02:38:58 PM PDT 24
Finished Jun 06 02:39:02 PM PDT 24
Peak memory 219220 kb
Host smart-c4d10c88-8a05-4b6a-8470-5436860c1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125312391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4125312391
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.44198619
Short name T633
Test name
Test status
Simulation time 22684354 ps
CPU time 1.13 seconds
Started Jun 06 02:39:00 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 215468 kb
Host smart-6c609617-50ff-40bd-a0a1-01c9f614a520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44198619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.44198619
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.4039217433
Short name T824
Test name
Test status
Simulation time 45034536 ps
CPU time 0.87 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 215168 kb
Host smart-33339954-8b64-4769-a14f-c5fa47b683ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039217433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.4039217433
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1787407492
Short name T470
Test name
Test status
Simulation time 378277182 ps
CPU time 7.19 seconds
Started Jun 06 02:39:01 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 216904 kb
Host smart-e81c6721-f6ea-4037-be19-b9dcd6aee446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787407492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1787407492
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1005030551
Short name T423
Test name
Test status
Simulation time 169871303045 ps
CPU time 517.71 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:47:37 PM PDT 24
Peak memory 218968 kb
Host smart-295ed9d1-791b-400f-8dfb-1ddd6aa6edef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005030551 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1005030551
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2004493193
Short name T490
Test name
Test status
Simulation time 48042461 ps
CPU time 1.73 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 216964 kb
Host smart-4e99cd07-7a66-45cb-8ee9-54d35b87b71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004493193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2004493193
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3428268369
Short name T378
Test name
Test status
Simulation time 630651591 ps
CPU time 4.14 seconds
Started Jun 06 02:40:23 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 217252 kb
Host smart-6a0bc952-5a33-4087-bee3-7ba0784d3b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428268369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3428268369
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1339323569
Short name T488
Test name
Test status
Simulation time 46625274 ps
CPU time 1.53 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218268 kb
Host smart-6821bcaa-e564-434e-9335-3c107c6cf806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339323569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1339323569
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.714579567
Short name T427
Test name
Test status
Simulation time 52585620 ps
CPU time 1.57 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218184 kb
Host smart-cb923fb2-bd63-4da8-bb0e-90c05cf6a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714579567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.714579567
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2049971695
Short name T775
Test name
Test status
Simulation time 25061660 ps
CPU time 1.23 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218064 kb
Host smart-c5914b0c-035a-4e11-9a47-93c9bbc55db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049971695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2049971695
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3985384753
Short name T445
Test name
Test status
Simulation time 54140134 ps
CPU time 1.4 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 219008 kb
Host smart-3ccbbb71-a1bc-42e4-b986-fe1a261b8af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985384753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3985384753
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2686164420
Short name T335
Test name
Test status
Simulation time 39129091 ps
CPU time 1.45 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218080 kb
Host smart-8ce9c0a2-c411-4d83-847a-291f5db3ea6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686164420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2686164420
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2975019563
Short name T733
Test name
Test status
Simulation time 66829323 ps
CPU time 2.08 seconds
Started Jun 06 02:40:22 PM PDT 24
Finished Jun 06 02:40:28 PM PDT 24
Peak memory 218980 kb
Host smart-0e6d7288-18db-44eb-96cc-12745c48d60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975019563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2975019563
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_err.3113987929
Short name T95
Test name
Test status
Simulation time 36989664 ps
CPU time 0.92 seconds
Started Jun 06 02:39:02 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 219496 kb
Host smart-21f5875c-0e00-472a-90fd-cba1c8420593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113987929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3113987929
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.336001608
Short name T24
Test name
Test status
Simulation time 42967727 ps
CPU time 1.75 seconds
Started Jun 06 02:38:58 PM PDT 24
Finished Jun 06 02:39:03 PM PDT 24
Peak memory 218272 kb
Host smart-dd18493f-13c2-49db-990b-e00778d7694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336001608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.336001608
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.1401471827
Short name T702
Test name
Test status
Simulation time 17907440 ps
CPU time 0.98 seconds
Started Jun 06 02:39:01 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 215176 kb
Host smart-3d2af85b-ffb9-4620-9dd0-d1385f718c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401471827 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1401471827
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2269382881
Short name T528
Test name
Test status
Simulation time 161041812 ps
CPU time 3.58 seconds
Started Jun 06 02:39:00 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 216636 kb
Host smart-6cc33f6f-072b-416a-9fa5-ddef09d517de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269382881 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2269382881
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.3532436245
Short name T653
Test name
Test status
Simulation time 52864613037 ps
CPU time 471.7 seconds
Started Jun 06 02:39:00 PM PDT 24
Finished Jun 06 02:46:55 PM PDT 24
Peak memory 221920 kb
Host smart-4187d5a7-a28d-4272-8530-ed0082a81566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532436245 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.3532436245
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.736532927
Short name T774
Test name
Test status
Simulation time 56036711 ps
CPU time 1.3 seconds
Started Jun 06 02:40:22 PM PDT 24
Finished Jun 06 02:40:28 PM PDT 24
Peak memory 218028 kb
Host smart-34d2936c-58e5-4e8f-adfa-d68f10a90fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736532927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.736532927
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.51254109
Short name T722
Test name
Test status
Simulation time 36105949 ps
CPU time 1.57 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218200 kb
Host smart-25326bf4-f923-475f-9b12-a68c6ae4e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51254109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.51254109
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.380019765
Short name T296
Test name
Test status
Simulation time 27657232 ps
CPU time 1.23 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 216916 kb
Host smart-512c1435-6792-40f8-8874-b1f05004cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380019765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.380019765
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1981584330
Short name T367
Test name
Test status
Simulation time 50083825 ps
CPU time 1.48 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 219652 kb
Host smart-5442d860-feae-4774-9779-26b40eeab625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981584330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1981584330
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.4272767768
Short name T581
Test name
Test status
Simulation time 26925600 ps
CPU time 1.22 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:28 PM PDT 24
Peak memory 219408 kb
Host smart-11fc6f37-cbd3-411c-ab4d-c7f9b5f59439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272767768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.4272767768
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.578542779
Short name T349
Test name
Test status
Simulation time 108392025 ps
CPU time 1.3 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 216952 kb
Host smart-c556193e-1c01-4370-a346-0deb8a916381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578542779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.578542779
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3849928714
Short name T521
Test name
Test status
Simulation time 38244084 ps
CPU time 1.44 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:39 PM PDT 24
Peak memory 218396 kb
Host smart-1c37ac75-6b61-4a2a-b768-72a4ae7f4d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849928714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3849928714
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1461133784
Short name T49
Test name
Test status
Simulation time 254397080 ps
CPU time 1.74 seconds
Started Jun 06 02:40:27 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 218564 kb
Host smart-c6ce98d7-35e1-4508-94ce-ee4604471251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461133784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1461133784
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3643007348
Short name T607
Test name
Test status
Simulation time 65682042 ps
CPU time 1.18 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218204 kb
Host smart-96401764-6edc-46a7-bb50-1eb32d900ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643007348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3643007348
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.401602049
Short name T255
Test name
Test status
Simulation time 58709171 ps
CPU time 1.31 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 215468 kb
Host smart-3aab278d-0850-4105-a5c3-30b3fad2f611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401602049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.401602049
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1915233879
Short name T597
Test name
Test status
Simulation time 34864292 ps
CPU time 0.79 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 205736 kb
Host smart-46714638-cbef-44a7-b619-d7f1cf317710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915233879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1915233879
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2811574956
Short name T252
Test name
Test status
Simulation time 41770700 ps
CPU time 1.24 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 217968 kb
Host smart-f776d535-ccbc-4812-ad3e-c4826d137135
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811574956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2811574956
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2040726817
Short name T146
Test name
Test status
Simulation time 68701029 ps
CPU time 0.86 seconds
Started Jun 06 02:39:04 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 218244 kb
Host smart-db5054b6-4ac3-4027-8f87-ad69d64bc7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040726817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2040726817
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.156946368
Short name T379
Test name
Test status
Simulation time 36473731 ps
CPU time 1.34 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 216940 kb
Host smart-98fcdfd5-db85-44a1-8683-546b7f3af60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156946368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.156946368
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.4123803656
Short name T387
Test name
Test status
Simulation time 29253203 ps
CPU time 0.92 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 215340 kb
Host smart-f551f57e-245a-434c-b690-4180ec2579b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123803656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4123803656
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3998208915
Short name T569
Test name
Test status
Simulation time 24954719 ps
CPU time 0.9 seconds
Started Jun 06 02:39:04 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 215212 kb
Host smart-76f2a749-9d05-4342-ab59-cdb60a201333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998208915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3998208915
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1324919339
Short name T529
Test name
Test status
Simulation time 2669989604 ps
CPU time 4.02 seconds
Started Jun 06 02:39:04 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 217196 kb
Host smart-ea878744-46e8-44bb-9051-449e6ab53718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324919339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1324919339
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3590179150
Short name T779
Test name
Test status
Simulation time 213674086223 ps
CPU time 1411.32 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 03:02:38 PM PDT 24
Peak memory 225872 kb
Host smart-05b3cb30-829a-4e5e-b224-21bc9d4d351a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590179150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3590179150
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2156795271
Short name T316
Test name
Test status
Simulation time 48035829 ps
CPU time 1.23 seconds
Started Jun 06 02:40:30 PM PDT 24
Finished Jun 06 02:40:33 PM PDT 24
Peak memory 218168 kb
Host smart-361ac316-4565-45ef-b411-1a8a4145fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156795271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2156795271
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.711765287
Short name T304
Test name
Test status
Simulation time 69786836 ps
CPU time 2.45 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 218208 kb
Host smart-1b6934c3-5675-4a33-9155-2c02fc54805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711765287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.711765287
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3019361392
Short name T788
Test name
Test status
Simulation time 74182446 ps
CPU time 1.09 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 216936 kb
Host smart-a50bf7c4-1f76-410d-9b6d-ae6ec12ce01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019361392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3019361392
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2810671761
Short name T562
Test name
Test status
Simulation time 301332252 ps
CPU time 4.19 seconds
Started Jun 06 02:40:33 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 219760 kb
Host smart-6ce33b77-3876-4439-849d-735b5cdf6a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810671761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2810671761
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1641598416
Short name T616
Test name
Test status
Simulation time 291356463 ps
CPU time 1.61 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 218376 kb
Host smart-bf4e4e69-f245-4d17-858e-62a52566c069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641598416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1641598416
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3746829442
Short name T354
Test name
Test status
Simulation time 101904496 ps
CPU time 1.3 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 216868 kb
Host smart-fe9c988c-bb79-4470-bab6-d8104250d3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746829442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3746829442
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1896478734
Short name T487
Test name
Test status
Simulation time 42962141 ps
CPU time 1.59 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 217968 kb
Host smart-a33b5473-4eb9-4525-9e5b-318a9deed74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896478734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1896478734
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.898159099
Short name T22
Test name
Test status
Simulation time 83289701 ps
CPU time 1.97 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218144 kb
Host smart-555533e1-d3ef-42ad-9d18-688b1565984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898159099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.898159099
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2278589783
Short name T626
Test name
Test status
Simulation time 48743072 ps
CPU time 1.64 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 215200 kb
Host smart-3db63153-dc86-446d-90c7-60dab3e74d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278589783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2278589783
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2969112265
Short name T326
Test name
Test status
Simulation time 42577718 ps
CPU time 1.24 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 217024 kb
Host smart-b863c7aa-8003-4cfc-a6a4-e9ca6ececa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969112265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2969112265
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3991499387
Short name T122
Test name
Test status
Simulation time 67417880 ps
CPU time 1.03 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 217960 kb
Host smart-bf8077b4-edb7-483b-817a-572d8e828d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991499387 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3991499387
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.4222607043
Short name T808
Test name
Test status
Simulation time 28419050 ps
CPU time 0.94 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 206428 kb
Host smart-b9364d2f-c8f8-4774-a563-28a0c75b519d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222607043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4222607043
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.1810897039
Short name T194
Test name
Test status
Simulation time 35714650 ps
CPU time 0.83 seconds
Started Jun 06 02:39:04 PM PDT 24
Finished Jun 06 02:39:07 PM PDT 24
Peak memory 216116 kb
Host smart-650768b1-d7fd-43e3-a5dd-0acdb54aa057
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810897039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1810897039
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.672338883
Short name T468
Test name
Test status
Simulation time 80954944 ps
CPU time 1.02 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:08 PM PDT 24
Peak memory 219520 kb
Host smart-282494bd-9919-402c-b22e-21eede5f1347
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672338883 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.672338883
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.24921912
Short name T456
Test name
Test status
Simulation time 31853669 ps
CPU time 0.82 seconds
Started Jun 06 02:39:03 PM PDT 24
Finished Jun 06 02:39:06 PM PDT 24
Peak memory 218196 kb
Host smart-b55d70e9-04e8-42e6-a17c-a465d082a84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24921912 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.24921912
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.475394637
Short name T802
Test name
Test status
Simulation time 46603610 ps
CPU time 1.77 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 218092 kb
Host smart-6879e26b-6f87-429c-9028-ce427d9ec689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475394637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.475394637
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.4224846354
Short name T578
Test name
Test status
Simulation time 27600150 ps
CPU time 1.04 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:09 PM PDT 24
Peak memory 224012 kb
Host smart-03d53b45-1bd7-467f-b52e-1cb6c448b52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224846354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4224846354
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.1812648167
Short name T449
Test name
Test status
Simulation time 25339732 ps
CPU time 0.95 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 215188 kb
Host smart-9df750a4-312c-4da2-ac6e-c0128cb46e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812648167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1812648167
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2220303514
Short name T719
Test name
Test status
Simulation time 375115845 ps
CPU time 6.73 seconds
Started Jun 06 02:39:11 PM PDT 24
Finished Jun 06 02:39:20 PM PDT 24
Peak memory 216848 kb
Host smart-8848f796-86b6-4d1e-af5d-ac8b18a49a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220303514 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2220303514
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1986501419
Short name T611
Test name
Test status
Simulation time 66209687876 ps
CPU time 394.94 seconds
Started Jun 06 02:39:05 PM PDT 24
Finished Jun 06 02:45:43 PM PDT 24
Peak memory 218812 kb
Host smart-21a1d7e2-edf3-4568-8614-0e8baa6450c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986501419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1986501419
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1534432646
Short name T703
Test name
Test status
Simulation time 85207766 ps
CPU time 1.13 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:28 PM PDT 24
Peak memory 216864 kb
Host smart-ffe8a92d-e6fb-4297-9efa-a5d759788744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534432646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1534432646
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1903425878
Short name T632
Test name
Test status
Simulation time 45350058 ps
CPU time 1.59 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218388 kb
Host smart-7799f4b8-780d-428f-8116-5bf3a3b436dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903425878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1903425878
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.771506964
Short name T504
Test name
Test status
Simulation time 33500480 ps
CPU time 1.43 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218152 kb
Host smart-f8bedca0-7479-474d-93d2-d1b10766ce8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771506964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.771506964
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.821531946
Short name T474
Test name
Test status
Simulation time 60960108 ps
CPU time 1.21 seconds
Started Jun 06 02:40:28 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 218476 kb
Host smart-4934adfd-44d9-4808-9946-7aca397be7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821531946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.821531946
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.881095064
Short name T685
Test name
Test status
Simulation time 36040045 ps
CPU time 1.15 seconds
Started Jun 06 02:40:32 PM PDT 24
Finished Jun 06 02:40:35 PM PDT 24
Peak memory 217072 kb
Host smart-5251eb72-fc5b-4af5-ae2c-3cc8c6c081ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881095064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.881095064
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.3641903745
Short name T272
Test name
Test status
Simulation time 76005093 ps
CPU time 1.09 seconds
Started Jun 06 02:40:32 PM PDT 24
Finished Jun 06 02:40:35 PM PDT 24
Peak memory 216864 kb
Host smart-5fa05390-a49b-45c5-8bf4-8b8751510f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641903745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3641903745
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1087564678
Short name T657
Test name
Test status
Simulation time 30147431 ps
CPU time 1.21 seconds
Started Jun 06 02:40:33 PM PDT 24
Finished Jun 06 02:40:35 PM PDT 24
Peak memory 216752 kb
Host smart-434f2181-0a84-4e38-bed7-1fad2a9d1c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087564678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1087564678
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.1758391614
Short name T786
Test name
Test status
Simulation time 34369269 ps
CPU time 1.17 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 206584 kb
Host smart-72e10241-c38d-4091-b660-a4c1b77d07c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758391614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1758391614
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2719474560
Short name T508
Test name
Test status
Simulation time 116645162 ps
CPU time 1.08 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 218016 kb
Host smart-cf0bb95e-682a-46b3-8053-dc6339d361d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719474560 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2719474560
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.3305986403
Short name T166
Test name
Test status
Simulation time 18985559 ps
CPU time 1.01 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 218396 kb
Host smart-0403dbfd-b6bb-4884-9a40-bc4691b8910a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305986403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.3305986403
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.1219481591
Short name T564
Test name
Test status
Simulation time 71426268 ps
CPU time 1.46 seconds
Started Jun 06 02:39:10 PM PDT 24
Finished Jun 06 02:39:14 PM PDT 24
Peak memory 218588 kb
Host smart-3140eb4a-da64-4628-9e08-1d544fdcee72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219481591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1219481591
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2059145049
Short name T801
Test name
Test status
Simulation time 23345218 ps
CPU time 1.17 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 215424 kb
Host smart-31f5de5a-3402-4545-9b6c-2d2b9a8ba136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059145049 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2059145049
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1048675621
Short name T404
Test name
Test status
Simulation time 49298967 ps
CPU time 0.94 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 215168 kb
Host smart-8e1b4b66-522e-44a7-a9bb-09da5018d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048675621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1048675621
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2575141723
Short name T746
Test name
Test status
Simulation time 486256745 ps
CPU time 5.52 seconds
Started Jun 06 02:39:09 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 216960 kb
Host smart-f43b629d-6410-4671-a76f-7d3dd9efa20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575141723 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2575141723
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1948708533
Short name T329
Test name
Test status
Simulation time 73624657059 ps
CPU time 874.42 seconds
Started Jun 06 02:39:10 PM PDT 24
Finished Jun 06 02:53:47 PM PDT 24
Peak memory 220208 kb
Host smart-2727c5e7-8dc6-4ab6-a4a9-c40f3b601018
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948708533 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1948708533
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3009289223
Short name T770
Test name
Test status
Simulation time 73903121 ps
CPU time 1.15 seconds
Started Jun 06 02:40:31 PM PDT 24
Finished Jun 06 02:40:34 PM PDT 24
Peak memory 216896 kb
Host smart-09374d2b-0094-44fe-8abc-84b29fff8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009289223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3009289223
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.156071521
Short name T711
Test name
Test status
Simulation time 32395920 ps
CPU time 1.41 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 219528 kb
Host smart-3b076a9e-ae30-4ab1-8a5c-a430e78f7cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156071521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.156071521
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.1047793802
Short name T699
Test name
Test status
Simulation time 51437464 ps
CPU time 1.77 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 218148 kb
Host smart-f8a99fed-5b37-4734-bc73-5abbaebe1c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047793802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1047793802
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.1718397034
Short name T471
Test name
Test status
Simulation time 51997912 ps
CPU time 1.97 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 218168 kb
Host smart-84698308-bac1-403e-9dae-b162610b9fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718397034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.1718397034
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2892120500
Short name T10
Test name
Test status
Simulation time 49837275 ps
CPU time 1.53 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218252 kb
Host smart-fcc677a6-474f-4538-991e-822194e915db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892120500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2892120500
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2709906150
Short name T451
Test name
Test status
Simulation time 33740202 ps
CPU time 1.46 seconds
Started Jun 06 02:40:32 PM PDT 24
Finished Jun 06 02:40:35 PM PDT 24
Peak memory 218148 kb
Host smart-42228794-d859-4970-b714-8d24124af92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709906150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2709906150
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2464589866
Short name T710
Test name
Test status
Simulation time 97932740 ps
CPU time 1.59 seconds
Started Jun 06 02:40:33 PM PDT 24
Finished Jun 06 02:40:36 PM PDT 24
Peak memory 218580 kb
Host smart-984f1278-ad2e-4c8f-9b20-7ec35846d9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464589866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2464589866
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1160245699
Short name T790
Test name
Test status
Simulation time 28850696 ps
CPU time 1.27 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 219532 kb
Host smart-686ed70a-c822-4a6b-ae16-c7d68955fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160245699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1160245699
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.446324443
Short name T154
Test name
Test status
Simulation time 29134909 ps
CPU time 1.09 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 219392 kb
Host smart-d7d8780d-ed99-4217-9db4-7a5385c74e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446324443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.446324443
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3599565987
Short name T829
Test name
Test status
Simulation time 30734552 ps
CPU time 1.01 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 214664 kb
Host smart-3fe2b767-6842-492b-ab5c-5bc17146693e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599565987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3599565987
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1602870848
Short name T167
Test name
Test status
Simulation time 14608685 ps
CPU time 0.92 seconds
Started Jun 06 02:39:10 PM PDT 24
Finished Jun 06 02:39:13 PM PDT 24
Peak memory 216300 kb
Host smart-b9cb8614-e0fc-4f0a-aa42-559d430e68cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602870848 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1602870848
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1874677686
Short name T115
Test name
Test status
Simulation time 36082090 ps
CPU time 1.2 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 218944 kb
Host smart-9cddd659-e091-4bd7-8f4d-769f3dc75c24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874677686 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1874677686
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3974180793
Short name T192
Test name
Test status
Simulation time 28346458 ps
CPU time 1.32 seconds
Started Jun 06 02:39:09 PM PDT 24
Finished Jun 06 02:39:13 PM PDT 24
Peak memory 229780 kb
Host smart-144562af-5009-45c5-aa7a-63b7dc7eb3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974180793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3974180793
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.3357572547
Short name T672
Test name
Test status
Simulation time 22717106 ps
CPU time 1.15 seconds
Started Jun 06 02:39:06 PM PDT 24
Finished Jun 06 02:39:10 PM PDT 24
Peak memory 223976 kb
Host smart-01597db9-2c89-47be-995c-f213d5608050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357572547 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3357572547
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2398695848
Short name T461
Test name
Test status
Simulation time 24403321 ps
CPU time 0.93 seconds
Started Jun 06 02:39:08 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 215248 kb
Host smart-e349060f-535b-4c73-8359-6aebf82e8e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398695848 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2398695848
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1806257202
Short name T608
Test name
Test status
Simulation time 487350916 ps
CPU time 5.03 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 216772 kb
Host smart-ce1bdf22-ee44-4ef6-8427-1974959c9e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806257202 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1806257202
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4029193881
Short name T207
Test name
Test status
Simulation time 282512312965 ps
CPU time 1804.46 seconds
Started Jun 06 02:39:11 PM PDT 24
Finished Jun 06 03:09:18 PM PDT 24
Peak memory 231844 kb
Host smart-5f28cbeb-55be-48a9-8ee4-6479a70910a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029193881 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4029193881
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2673013055
Short name T728
Test name
Test status
Simulation time 42571386 ps
CPU time 1.24 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 219572 kb
Host smart-054a6d38-e846-41c0-9ddc-61db73bd4aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673013055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2673013055
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.575447402
Short name T293
Test name
Test status
Simulation time 33492125 ps
CPU time 1.26 seconds
Started Jun 06 02:40:39 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 216864 kb
Host smart-7c0dac1d-c7cd-4259-9414-17e470724033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575447402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.575447402
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3447925233
Short name T558
Test name
Test status
Simulation time 37948141 ps
CPU time 1.17 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 216928 kb
Host smart-9fbe6387-ccfa-48c8-8671-9fc6932b80fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447925233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3447925233
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2784702229
Short name T513
Test name
Test status
Simulation time 72098948 ps
CPU time 1.16 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 216836 kb
Host smart-64a7d7e8-3c15-4753-8987-14559091796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784702229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2784702229
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3331114966
Short name T282
Test name
Test status
Simulation time 276365724 ps
CPU time 3.52 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 219668 kb
Host smart-edbf732b-861a-4b0d-99c0-e833feb0cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331114966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3331114966
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.254433969
Short name T832
Test name
Test status
Simulation time 60668978 ps
CPU time 1.46 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 218344 kb
Host smart-611f9590-6625-447f-b749-c087c7c8c5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254433969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.254433969
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2466806305
Short name T441
Test name
Test status
Simulation time 61222161 ps
CPU time 1.61 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:39 PM PDT 24
Peak memory 218200 kb
Host smart-efc7492e-03d6-4b30-9335-582d710df267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466806305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2466806305
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.716024685
Short name T658
Test name
Test status
Simulation time 128204585 ps
CPU time 1.8 seconds
Started Jun 06 02:40:34 PM PDT 24
Finished Jun 06 02:40:37 PM PDT 24
Peak memory 219856 kb
Host smart-4fb61e4c-c8db-4ce2-897d-ecd4a6877c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716024685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.716024685
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4241762148
Short name T23
Test name
Test status
Simulation time 38573446 ps
CPU time 1.64 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 218164 kb
Host smart-249991c1-814e-4db2-8f00-0e52c05497dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241762148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4241762148
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2178077798
Short name T130
Test name
Test status
Simulation time 86692292 ps
CPU time 1.24 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 215600 kb
Host smart-e1978be2-b0fa-4256-bc71-92d7f9643792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178077798 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2178077798
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1778064474
Short name T730
Test name
Test status
Simulation time 16855920 ps
CPU time 0.93 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 206904 kb
Host smart-418fe1f5-3d80-4c46-ba16-0f9a21797907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778064474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1778064474
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2911622740
Short name T749
Test name
Test status
Simulation time 14355117 ps
CPU time 0.92 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 216212 kb
Host smart-8c95d971-5fee-4c43-b994-7fe160bd78c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911622740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2911622740
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3408648822
Short name T116
Test name
Test status
Simulation time 48716951 ps
CPU time 1.07 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 218280 kb
Host smart-ee8ff1e7-a16d-43a2-9471-e9a71d34e604
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408648822 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3408648822
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.2589844720
Short name T700
Test name
Test status
Simulation time 23841488 ps
CPU time 1.1 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 223948 kb
Host smart-0bfd173c-7ad7-4dbd-ac3e-a0ad65ddb2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589844720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.2589844720
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1174193300
Short name T305
Test name
Test status
Simulation time 58848429 ps
CPU time 1.24 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:12 PM PDT 24
Peak memory 219564 kb
Host smart-a979d8c5-c96a-4838-b0ce-90ec1f318e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174193300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1174193300
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.4178608342
Short name T796
Test name
Test status
Simulation time 38373169 ps
CPU time 0.87 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 215676 kb
Host smart-de73f67b-ee96-4210-a07c-b747796eb333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178608342 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4178608342
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3091259668
Short name T345
Test name
Test status
Simulation time 74268629 ps
CPU time 0.89 seconds
Started Jun 06 02:39:07 PM PDT 24
Finished Jun 06 02:39:11 PM PDT 24
Peak memory 215224 kb
Host smart-3e5b9768-8a4c-404b-a900-80a5e0abe859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091259668 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3091259668
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.502324600
Short name T359
Test name
Test status
Simulation time 222996204 ps
CPU time 1.51 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 217112 kb
Host smart-a296adee-c078-4f7e-94c7-ef33d8e94b51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502324600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.502324600
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3595463924
Short name T533
Test name
Test status
Simulation time 50167116793 ps
CPU time 323.16 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:44:40 PM PDT 24
Peak memory 223640 kb
Host smart-6118c4f6-4bc4-46c1-bc86-ce4e8c563272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595463924 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3595463924
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.3047079169
Short name T535
Test name
Test status
Simulation time 62251422 ps
CPU time 1.28 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 218136 kb
Host smart-f6f7b7e6-f764-4d87-9b76-ec4442ea8ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047079169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.3047079169
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.1746625255
Short name T319
Test name
Test status
Simulation time 61512481 ps
CPU time 1.15 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218660 kb
Host smart-a6280335-f63c-4b37-b8b3-b480e06682fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746625255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1746625255
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2576065449
Short name T819
Test name
Test status
Simulation time 35292706 ps
CPU time 1.09 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 217056 kb
Host smart-512c7b82-26e6-4bdc-9710-96dab654ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576065449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2576065449
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.444893729
Short name T694
Test name
Test status
Simulation time 256068461 ps
CPU time 3.21 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 215328 kb
Host smart-572246a8-6ffb-43fb-ac4c-90121d715535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444893729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.444893729
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2570273413
Short name T262
Test name
Test status
Simulation time 167769295 ps
CPU time 1.12 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 216856 kb
Host smart-3457bd99-2cfc-4438-99a6-01ce2fb6047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570273413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2570273413
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.817330040
Short name T431
Test name
Test status
Simulation time 301921843 ps
CPU time 3.59 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 219916 kb
Host smart-ffefd3ae-95e8-42b5-b0c5-9996dee03a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817330040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.817330040
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3073935630
Short name T416
Test name
Test status
Simulation time 42002061 ps
CPU time 1.59 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 217968 kb
Host smart-f850a021-f6ea-4e4e-80fe-902b132ee96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073935630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3073935630
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1092409398
Short name T358
Test name
Test status
Simulation time 53052679 ps
CPU time 1.65 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 218292 kb
Host smart-f9de2edd-1944-4a3c-b897-e6e0d2d307f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092409398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1092409398
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3113708248
Short name T283
Test name
Test status
Simulation time 68388165 ps
CPU time 2.33 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 219772 kb
Host smart-9c4587a7-e8ca-4589-b8aa-cb45cdae04c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113708248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3113708248
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2357821631
Short name T610
Test name
Test status
Simulation time 44943882 ps
CPU time 1.74 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 217152 kb
Host smart-3ecc1d11-8c14-44fb-915c-c096d2c7d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357821631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2357821631
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2840056077
Short name T129
Test name
Test status
Simulation time 36887923 ps
CPU time 1.23 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 218848 kb
Host smart-405bff14-ba69-4ede-8522-ba73b4d39779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840056077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2840056077
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.4278413696
Short name T614
Test name
Test status
Simulation time 38280133 ps
CPU time 1.23 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 214808 kb
Host smart-059363f0-b5d2-4faf-b3f3-f2f7826c3573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278413696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.4278413696
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.112229341
Short name T142
Test name
Test status
Simulation time 145522532 ps
CPU time 0.83 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 216076 kb
Host smart-384037a1-4e8b-4ad8-b8f1-540ff1073089
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112229341 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.112229341
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1871529913
Short name T76
Test name
Test status
Simulation time 37438259 ps
CPU time 1.3 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 216876 kb
Host smart-6e8799a3-f58a-40f1-9e6c-5bacacfaabed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871529913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1871529913
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.690928516
Short name T662
Test name
Test status
Simulation time 24270142 ps
CPU time 0.92 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:16 PM PDT 24
Peak memory 218692 kb
Host smart-b9dafebd-915d-4633-a325-8ac0f33c9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690928516 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.690928516
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2127985356
Short name T498
Test name
Test status
Simulation time 46624416 ps
CPU time 1.67 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 218120 kb
Host smart-00cc633d-e0ec-4249-a48d-d44fbee5088d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127985356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2127985356
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.904989972
Short name T35
Test name
Test status
Simulation time 23550242 ps
CPU time 0.96 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 215692 kb
Host smart-889d8fb9-45ae-47b5-a9bb-4104c90922b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904989972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.904989972
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3905808991
Short name T60
Test name
Test status
Simulation time 15115174 ps
CPU time 0.94 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 215456 kb
Host smart-656db8ab-6520-486e-9617-05b12e922f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905808991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3905808991
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3865583468
Short name T64
Test name
Test status
Simulation time 4208916495 ps
CPU time 6.95 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 215348 kb
Host smart-fac9980e-a459-463f-a0d2-89917e46c61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865583468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3865583468
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.23881410
Short name T351
Test name
Test status
Simulation time 62525025205 ps
CPU time 1322.76 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 03:01:17 PM PDT 24
Peak memory 223800 kb
Host smart-71d26d8d-c581-48e4-b40a-62338777b555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23881410 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.23881410
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1398339746
Short name T732
Test name
Test status
Simulation time 36273186 ps
CPU time 1.49 seconds
Started Jun 06 02:40:34 PM PDT 24
Finished Jun 06 02:40:37 PM PDT 24
Peak memory 218060 kb
Host smart-244a1a09-ea64-46ca-b9b8-d2573b33520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398339746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1398339746
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1162589327
Short name T477
Test name
Test status
Simulation time 53730233 ps
CPU time 0.99 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 216940 kb
Host smart-64bf94dc-fb5c-4c1e-8340-e8bb374bc3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162589327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1162589327
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1754866161
Short name T294
Test name
Test status
Simulation time 63475577 ps
CPU time 1.12 seconds
Started Jun 06 02:40:39 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 217008 kb
Host smart-cf6ffd3e-1fea-4cc3-a1a2-2dce1ecfb11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754866161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1754866161
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3236188474
Short name T552
Test name
Test status
Simulation time 70346387 ps
CPU time 1.23 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:40 PM PDT 24
Peak memory 216820 kb
Host smart-29853b4e-90e5-40a1-93de-f5f72c1bebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236188474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3236188474
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2101992413
Short name T635
Test name
Test status
Simulation time 44244689 ps
CPU time 1.47 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 218324 kb
Host smart-263b2ebb-c9eb-42bf-8537-b21d8978fa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101992413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2101992413
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.70169825
Short name T412
Test name
Test status
Simulation time 46128664 ps
CPU time 1.36 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 218388 kb
Host smart-918eb504-a151-4e1d-ae69-092311fb29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70169825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.70169825
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2362024972
Short name T830
Test name
Test status
Simulation time 62440407 ps
CPU time 1.08 seconds
Started Jun 06 02:40:34 PM PDT 24
Finished Jun 06 02:40:37 PM PDT 24
Peak memory 219400 kb
Host smart-1c012cf5-a67c-43b9-98f8-94d21895d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362024972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2362024972
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.483097254
Short name T502
Test name
Test status
Simulation time 40217630 ps
CPU time 1.55 seconds
Started Jun 06 02:40:39 PM PDT 24
Finished Jun 06 02:40:43 PM PDT 24
Peak memory 217288 kb
Host smart-8ad3c13f-843b-467d-9ad8-8d191f9b65da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483097254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.483097254
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.880055070
Short name T342
Test name
Test status
Simulation time 100954571 ps
CPU time 1.47 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 218312 kb
Host smart-849fc1a5-2b5e-47eb-9531-d5bb8fca8b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880055070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.880055070
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2405142933
Short name T804
Test name
Test status
Simulation time 62326259 ps
CPU time 1.1 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 216828 kb
Host smart-3e04b543-1d4b-4871-aea7-097e646c5f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405142933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2405142933
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2676760559
Short name T102
Test name
Test status
Simulation time 74020518 ps
CPU time 1.11 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 218948 kb
Host smart-9378e8e4-a285-4b09-a661-18094bd99f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676760559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2676760559
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2251973742
Short name T330
Test name
Test status
Simulation time 93116394 ps
CPU time 0.86 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 205796 kb
Host smart-0c7a9500-7652-49cd-a09f-e4f01623fce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251973742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2251973742
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.30925257
Short name T627
Test name
Test status
Simulation time 27851306 ps
CPU time 0.81 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 216036 kb
Host smart-6068f646-5ee0-4bf3-9ec4-39826911a2cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30925257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.30925257
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.681477584
Short name T9
Test name
Test status
Simulation time 36282667 ps
CPU time 1.1 seconds
Started Jun 06 02:39:19 PM PDT 24
Finished Jun 06 02:39:22 PM PDT 24
Peak memory 217184 kb
Host smart-b8fc42c5-f470-4fcf-a9db-c421dc3553d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681477584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.681477584
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4199557094
Short name T584
Test name
Test status
Simulation time 218116876 ps
CPU time 1.14 seconds
Started Jun 06 02:39:35 PM PDT 24
Finished Jun 06 02:39:38 PM PDT 24
Peak memory 215272 kb
Host smart-dab1cd9f-6488-492e-86b4-379bcc3c96e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199557094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4199557094
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.161398191
Short name T393
Test name
Test status
Simulation time 37945716 ps
CPU time 0.91 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 215452 kb
Host smart-fe8b3ff9-8b96-46a7-9f9c-aa699e16a3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161398191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.161398191
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1929406938
Short name T479
Test name
Test status
Simulation time 16515671 ps
CPU time 1.02 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 215244 kb
Host smart-eabb00b6-59a3-4f90-995a-92044b9c62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929406938 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1929406938
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3055275772
Short name T671
Test name
Test status
Simulation time 273391032 ps
CPU time 5.63 seconds
Started Jun 06 02:39:13 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 218304 kb
Host smart-3dbd97fc-27c4-4570-9297-b028782c0277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055275772 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3055275772
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1024107975
Short name T208
Test name
Test status
Simulation time 147508762613 ps
CPU time 1689.61 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 03:07:29 PM PDT 24
Peak memory 224780 kb
Host smart-4f3f77d0-8a94-49de-bc39-256004aadd13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024107975 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1024107975
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2100718443
Short name T52
Test name
Test status
Simulation time 90967882 ps
CPU time 1.68 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 218292 kb
Host smart-7b2c71bd-735d-4b15-af5a-e698af0bd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100718443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2100718443
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.453455845
Short name T436
Test name
Test status
Simulation time 41731555 ps
CPU time 1.42 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 216948 kb
Host smart-8d0a52b9-947c-4443-8f21-60d4b6670ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453455845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.453455845
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.920176389
Short name T389
Test name
Test status
Simulation time 160020255 ps
CPU time 3 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 219920 kb
Host smart-59686b69-82d0-42df-b5ac-6ef654947d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920176389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.920176389
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3880704626
Short name T665
Test name
Test status
Simulation time 80119985 ps
CPU time 1.13 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 216996 kb
Host smart-987c8461-1c9e-43a3-8d66-32f4635a0401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880704626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3880704626
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.872679065
Short name T265
Test name
Test status
Simulation time 67788626 ps
CPU time 1.06 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 217212 kb
Host smart-0bfb0695-650f-4397-ba03-669a8e9502e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872679065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.872679065
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1520526305
Short name T331
Test name
Test status
Simulation time 58999073 ps
CPU time 1.4 seconds
Started Jun 06 02:40:34 PM PDT 24
Finished Jun 06 02:40:37 PM PDT 24
Peak memory 218348 kb
Host smart-33b27a1d-65fb-4105-b5a1-d77595e6c034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520526305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1520526305
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.885052555
Short name T537
Test name
Test status
Simulation time 49074964 ps
CPU time 1.82 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 218312 kb
Host smart-33ff8071-4ac8-41e3-a329-866fd835016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885052555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.885052555
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3327161013
Short name T531
Test name
Test status
Simulation time 73351749 ps
CPU time 1.08 seconds
Started Jun 06 02:40:36 PM PDT 24
Finished Jun 06 02:40:39 PM PDT 24
Peak memory 217024 kb
Host smart-2b586cb6-0e4a-400d-ad07-f61151fd5f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327161013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3327161013
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1236039869
Short name T462
Test name
Test status
Simulation time 101240905 ps
CPU time 1.1 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 217056 kb
Host smart-3823519c-f38a-41f5-be00-4982897f173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236039869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1236039869
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.2421312879
Short name T736
Test name
Test status
Simulation time 15197924 ps
CPU time 0.9 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:16 PM PDT 24
Peak memory 206540 kb
Host smart-1fa33a19-3b20-481a-a4e0-8b4663278213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421312879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2421312879
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3886469073
Short name T636
Test name
Test status
Simulation time 35395841 ps
CPU time 0.85 seconds
Started Jun 06 02:39:12 PM PDT 24
Finished Jun 06 02:39:15 PM PDT 24
Peak memory 216260 kb
Host smart-9a47e1fe-f11f-4413-a0fd-b986b856a6f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886469073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3886469073
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.4108553386
Short name T188
Test name
Test status
Simulation time 18337291 ps
CPU time 1.12 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 224020 kb
Host smart-d392ee0d-b6e0-4e35-a5c8-1e7d6ceee8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108553386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.4108553386
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.333341677
Short name T27
Test name
Test status
Simulation time 39956433 ps
CPU time 1.46 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 218136 kb
Host smart-df4b95ee-e578-40d7-bb46-e2f289725c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333341677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.333341677
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_smoke.2996870927
Short name T646
Test name
Test status
Simulation time 15766491 ps
CPU time 1.04 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:17 PM PDT 24
Peak memory 215208 kb
Host smart-3594fcb5-5b50-4fec-96fb-8319b14e29bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996870927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2996870927
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1507635097
Short name T534
Test name
Test status
Simulation time 123674915 ps
CPU time 1.76 seconds
Started Jun 06 02:39:14 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 218304 kb
Host smart-fb8acf13-f541-4b41-bc09-35e12d3d7574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507635097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1507635097
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_genbits.3996647177
Short name T291
Test name
Test status
Simulation time 206598576 ps
CPU time 1.34 seconds
Started Jun 06 02:40:33 PM PDT 24
Finished Jun 06 02:40:35 PM PDT 24
Peak memory 218352 kb
Host smart-b0fdb727-cbdd-47c9-812a-a095f166bf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996647177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3996647177
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3121255353
Short name T742
Test name
Test status
Simulation time 80716076 ps
CPU time 1.31 seconds
Started Jun 06 02:40:38 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218124 kb
Host smart-408c9d7e-dacc-438f-b964-841e6fd64717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121255353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3121255353
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2668081867
Short name T516
Test name
Test status
Simulation time 80693294 ps
CPU time 1.74 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 219644 kb
Host smart-7ef87924-9b3b-411f-90a5-7b2ad3cc1ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668081867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2668081867
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2791926388
Short name T485
Test name
Test status
Simulation time 46168777 ps
CPU time 1.86 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:38 PM PDT 24
Peak memory 218096 kb
Host smart-5493b906-e26e-4cb1-94ad-0d509ae0c3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791926388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2791926388
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1576665719
Short name T44
Test name
Test status
Simulation time 58420456 ps
CPU time 1.28 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218216 kb
Host smart-d373cdfc-7d2b-4a98-9e4d-559227ca1db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576665719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1576665719
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.763517787
Short name T545
Test name
Test status
Simulation time 120631109 ps
CPU time 1.37 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218664 kb
Host smart-ebc57c52-90fc-419c-8e81-1645835fe7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763517787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.763517787
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2056069543
Short name T297
Test name
Test status
Simulation time 34051882 ps
CPU time 1.53 seconds
Started Jun 06 02:40:35 PM PDT 24
Finished Jun 06 02:40:37 PM PDT 24
Peak memory 218048 kb
Host smart-d641dc20-b28e-4ae3-b83a-318db5277a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056069543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2056069543
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3033330790
Short name T764
Test name
Test status
Simulation time 64730396 ps
CPU time 1.26 seconds
Started Jun 06 02:40:37 PM PDT 24
Finished Jun 06 02:40:41 PM PDT 24
Peak memory 218596 kb
Host smart-74b63986-c437-4aad-9344-a615d7b85490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033330790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3033330790
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.572126859
Short name T745
Test name
Test status
Simulation time 54052408 ps
CPU time 0.94 seconds
Started Jun 06 02:40:39 PM PDT 24
Finished Jun 06 02:40:42 PM PDT 24
Peak memory 217000 kb
Host smart-6bc0e43e-c05c-4325-b743-70d366cfeb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572126859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.572126859
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.1210556990
Short name T343
Test name
Test status
Simulation time 54126055 ps
CPU time 0.9 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 214656 kb
Host smart-30af4ae0-7e08-400e-885f-ae881ad17d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210556990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1210556990
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1432085995
Short name T137
Test name
Test status
Simulation time 65492581 ps
CPU time 0.9 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 215260 kb
Host smart-6a1cc6c6-712f-4bfc-a101-53946d108ce1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432085995 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1432085995
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.592801506
Short name T246
Test name
Test status
Simulation time 35157489 ps
CPU time 1.21 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 218104 kb
Host smart-55f21cf6-fc81-4f86-aef7-5478039eaeb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592801506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.592801506
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.3057604662
Short name T103
Test name
Test status
Simulation time 33055066 ps
CPU time 1.03 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 219480 kb
Host smart-10ebc741-658e-48b6-b094-0253b1359fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057604662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3057604662
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1657783738
Short name T620
Test name
Test status
Simulation time 33764117 ps
CPU time 1.05 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:38:45 PM PDT 24
Peak memory 216984 kb
Host smart-d344a1e5-8e99-43b1-80c8-95b6c974ecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657783738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1657783738
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.1983328721
Short name T37
Test name
Test status
Simulation time 40367038 ps
CPU time 0.81 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:39 PM PDT 24
Peak memory 215440 kb
Host smart-109d0b5a-f62f-4821-9776-6cfb6bbf96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983328721 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1983328721
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.939072241
Short name T298
Test name
Test status
Simulation time 24850037 ps
CPU time 0.96 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 207044 kb
Host smart-2aa3798a-f9fe-4b2b-a7ff-ece9c304b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939072241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.939072241
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2940514571
Short name T669
Test name
Test status
Simulation time 21163832 ps
CPU time 1.04 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 215196 kb
Host smart-76f382b8-4eb6-413a-9848-d6084cb5ca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940514571 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2940514571
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.441903946
Short name T434
Test name
Test status
Simulation time 714361981 ps
CPU time 5.12 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 02:38:44 PM PDT 24
Peak memory 217008 kb
Host smart-e725005d-7029-4c5a-9c3d-ba3a6e31bba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441903946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.441903946
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3962019324
Short name T625
Test name
Test status
Simulation time 103844830283 ps
CPU time 1314.13 seconds
Started Jun 06 02:38:37 PM PDT 24
Finished Jun 06 03:00:33 PM PDT 24
Peak memory 225532 kb
Host smart-5f1c84b4-fbc6-4c7b-8bf8-3d005cc827a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962019324 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3962019324
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.2150223763
Short name T792
Test name
Test status
Simulation time 13481990 ps
CPU time 0.92 seconds
Started Jun 06 02:39:21 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 214692 kb
Host smart-d1c3a359-ca2b-47d4-89ad-836f47ebce54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150223763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2150223763
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.3510404922
Short name T119
Test name
Test status
Simulation time 19817513 ps
CPU time 1.19 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 224012 kb
Host smart-4c622e89-3280-4fd3-87b7-d1d5107d2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510404922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3510404922
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3299303956
Short name T322
Test name
Test status
Simulation time 37117108 ps
CPU time 1.34 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 218376 kb
Host smart-6b42221c-f5f3-475b-8c4f-aab4a91dcfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299303956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3299303956
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.2859858646
Short name T557
Test name
Test status
Simulation time 38270135 ps
CPU time 0.87 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 215168 kb
Host smart-8333453f-6406-4694-a168-94f31eb18922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859858646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2859858646
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2037678653
Short name T655
Test name
Test status
Simulation time 16523520 ps
CPU time 0.98 seconds
Started Jun 06 02:39:21 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 215048 kb
Host smart-dc7c6780-045c-496f-b657-5d0077e5c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037678653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2037678653
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.4035569249
Short name T659
Test name
Test status
Simulation time 375587468 ps
CPU time 7.31 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 02:39:27 PM PDT 24
Peak memory 219232 kb
Host smart-b2c1d4c5-e6ba-4c15-85b6-cf60abf6f339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035569249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4035569249
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3355071694
Short name T66
Test name
Test status
Simulation time 346130376233 ps
CPU time 1551.09 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 03:05:12 PM PDT 24
Peak memory 226444 kb
Host smart-ae0aa881-3f32-4fe2-9b59-d357094af7ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355071694 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3355071694
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2704891015
Short name T14
Test name
Test status
Simulation time 46680433 ps
CPU time 1.52 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 218196 kb
Host smart-6e3ebe01-d1f3-4c2b-848d-cc5ada21d422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704891015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2704891015
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2399174268
Short name T593
Test name
Test status
Simulation time 47108286 ps
CPU time 1.85 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 218124 kb
Host smart-deeabd0f-f8dd-4bfe-afd6-68b7953052fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399174268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2399174268
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3224726226
Short name T539
Test name
Test status
Simulation time 42357286 ps
CPU time 1.47 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 218248 kb
Host smart-71cb3c39-3565-4138-a475-ccc78d9bf79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224726226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3224726226
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.1999937032
Short name T323
Test name
Test status
Simulation time 40352197 ps
CPU time 1.56 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218108 kb
Host smart-f2e5bb4a-9f20-4531-98c8-4a601fdf206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999937032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.1999937032
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.539812589
Short name T664
Test name
Test status
Simulation time 74659713 ps
CPU time 1.17 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 218552 kb
Host smart-3cdd80cf-1c73-4b0a-a3ed-58305e6f9eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539812589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.539812589
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3992957652
Short name T276
Test name
Test status
Simulation time 33117594 ps
CPU time 1.33 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 216872 kb
Host smart-25101a24-bcde-45bc-9316-327516189057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992957652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3992957652
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.67955919
Short name T443
Test name
Test status
Simulation time 30215448 ps
CPU time 1.35 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 216964 kb
Host smart-d3c27203-0d15-41a7-9a77-142197a0e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67955919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.67955919
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1852133714
Short name T709
Test name
Test status
Simulation time 104303898 ps
CPU time 1.49 seconds
Started Jun 06 02:40:41 PM PDT 24
Finished Jun 06 02:40:44 PM PDT 24
Peak memory 218288 kb
Host smart-6205553b-176c-4ac3-b67f-1db5bca3515f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852133714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1852133714
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2076476592
Short name T795
Test name
Test status
Simulation time 49216832 ps
CPU time 1.48 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 216968 kb
Host smart-fd7dcdfa-3e21-433b-87a7-913f0cb614c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076476592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2076476592
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.1789091804
Short name T605
Test name
Test status
Simulation time 41165927 ps
CPU time 0.9 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 214684 kb
Host smart-5f2d7d15-f61d-4e42-ad1a-0a29ce3bde79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789091804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1789091804
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.3254129139
Short name T338
Test name
Test status
Simulation time 82449067 ps
CPU time 0.8 seconds
Started Jun 06 02:39:21 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 216100 kb
Host smart-d44b3311-415d-46c2-acc7-f3c8358d551b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254129139 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.3254129139
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.651441242
Short name T73
Test name
Test status
Simulation time 42504813 ps
CPU time 1.1 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:18 PM PDT 24
Peak memory 216744 kb
Host smart-87132fb9-9d45-4372-a675-020275ac4fa2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651441242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.651441242
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3553095776
Short name T810
Test name
Test status
Simulation time 26123608 ps
CPU time 0.89 seconds
Started Jun 06 02:39:21 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 219348 kb
Host smart-5b9ac178-b27a-4043-a001-2ad0121ed0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553095776 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3553095776
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.179275818
Short name T75
Test name
Test status
Simulation time 71595569 ps
CPU time 2.7 seconds
Started Jun 06 02:39:19 PM PDT 24
Finished Jun 06 02:39:24 PM PDT 24
Peak memory 219852 kb
Host smart-5c9f0eae-5561-428d-b10b-6ff69f287dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179275818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.179275818
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4038359705
Short name T580
Test name
Test status
Simulation time 53127448 ps
CPU time 0.93 seconds
Started Jun 06 02:39:17 PM PDT 24
Finished Jun 06 02:39:21 PM PDT 24
Peak memory 223808 kb
Host smart-12237eea-04e1-4388-8116-5a0226ca983d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038359705 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4038359705
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2712982465
Short name T826
Test name
Test status
Simulation time 57846000 ps
CPU time 0.95 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 02:39:20 PM PDT 24
Peak memory 215152 kb
Host smart-8cd4f04e-e449-49e8-89ba-f75187378878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712982465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2712982465
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.177943450
Short name T560
Test name
Test status
Simulation time 137677876 ps
CPU time 1.85 seconds
Started Jun 06 02:39:15 PM PDT 24
Finished Jun 06 02:39:19 PM PDT 24
Peak memory 216756 kb
Host smart-1ded090c-143d-4759-8aed-9afc80a60e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177943450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.177943450
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3318125773
Short name T602
Test name
Test status
Simulation time 210305583727 ps
CPU time 1443.31 seconds
Started Jun 06 02:39:16 PM PDT 24
Finished Jun 06 03:03:22 PM PDT 24
Peak memory 225428 kb
Host smart-71e219b7-1551-45a0-a7ae-4e3fb3c5fb24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318125773 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3318125773
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2792940607
Short name T828
Test name
Test status
Simulation time 139212791 ps
CPU time 1.17 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 219572 kb
Host smart-877770f6-bcc1-4656-adc7-1e71b3b60851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792940607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2792940607
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2777760608
Short name T815
Test name
Test status
Simulation time 49476564 ps
CPU time 1.22 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 216968 kb
Host smart-cfabbdcd-d497-4eb0-b4ad-eb339afd9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777760608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2777760608
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.792630235
Short name T220
Test name
Test status
Simulation time 52699685 ps
CPU time 1.95 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 217004 kb
Host smart-8006be6e-53a6-4032-b9f8-13e2b9afca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792630235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.792630235
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3235459023
Short name T836
Test name
Test status
Simulation time 263156952 ps
CPU time 1.21 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 216960 kb
Host smart-1f5b502d-97ac-42be-a38f-9d14d68e2ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235459023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3235459023
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.4054603338
Short name T442
Test name
Test status
Simulation time 81711481 ps
CPU time 1.61 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218352 kb
Host smart-235e46c0-e34b-493b-ada4-4ea5d8253057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054603338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.4054603338
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1694817167
Short name T357
Test name
Test status
Simulation time 32508867 ps
CPU time 1.38 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 216824 kb
Host smart-1c50deb0-5754-45c7-9c43-bf45a770840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694817167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1694817167
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1455597531
Short name T376
Test name
Test status
Simulation time 184585863 ps
CPU time 1.39 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 218416 kb
Host smart-956fca1c-eaa7-4b03-b444-d392f8a9fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455597531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1455597531
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3957890491
Short name T264
Test name
Test status
Simulation time 58780456 ps
CPU time 2.01 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 218196 kb
Host smart-601f3d33-a6b3-42b2-b3e4-193d695d788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957890491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3957890491
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.551691294
Short name T295
Test name
Test status
Simulation time 27933811 ps
CPU time 1.21 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 217884 kb
Host smart-b964ec9c-d37f-4079-9d9c-c560a22054b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551691294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.551691294
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1056664301
Short name T799
Test name
Test status
Simulation time 108663293 ps
CPU time 1.13 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 217012 kb
Host smart-de3202e1-9654-4f5a-9b7a-a98067e08148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056664301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1056664301
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.64026322
Short name T621
Test name
Test status
Simulation time 33478270 ps
CPU time 0.77 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 206684 kb
Host smart-9a09db84-fcb6-4aff-864b-2b94e539e997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64026322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.64026322
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1993200267
Short name T772
Test name
Test status
Simulation time 11867529 ps
CPU time 0.87 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 215872 kb
Host smart-879cc5ff-3bfd-41a6-9dce-8db3bb858abd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993200267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1993200267
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1351899116
Short name T495
Test name
Test status
Simulation time 35555011 ps
CPU time 0.95 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 219280 kb
Host smart-4ec7e3ec-4774-4cdd-bdc1-adf51ba1028e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351899116 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1351899116
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2077127195
Short name T104
Test name
Test status
Simulation time 235427548 ps
CPU time 1.07 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 219600 kb
Host smart-bf089a1b-d058-4226-9712-a0c6fc1fd403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077127195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2077127195
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3619699791
Short name T673
Test name
Test status
Simulation time 41203671 ps
CPU time 0.89 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:29 PM PDT 24
Peak memory 217040 kb
Host smart-987ec654-1acf-41ac-a6c7-f4a08109ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619699791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3619699791
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.387589019
Short name T77
Test name
Test status
Simulation time 27868861 ps
CPU time 0.95 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 215860 kb
Host smart-87375c0b-c0fb-455e-a78b-e9c22af607d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387589019 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.387589019
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.469296415
Short name T649
Test name
Test status
Simulation time 24306917 ps
CPU time 0.89 seconds
Started Jun 06 02:39:21 PM PDT 24
Finished Jun 06 02:39:23 PM PDT 24
Peak memory 215060 kb
Host smart-7f41fc99-b202-4af6-b644-7f3b8bc4426b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469296415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.469296415
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2375560775
Short name T458
Test name
Test status
Simulation time 454401914 ps
CPU time 2.98 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 216948 kb
Host smart-37772535-1f33-4cb4-8485-f38fac4b4f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375560775 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2375560775
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3791550610
Short name T617
Test name
Test status
Simulation time 33887152999 ps
CPU time 378.73 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:45:52 PM PDT 24
Peak memory 223684 kb
Host smart-a019a275-399d-4f7d-9f4d-df3d338a592f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791550610 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3791550610
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3556063244
Short name T476
Test name
Test status
Simulation time 21439715 ps
CPU time 1.07 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 216908 kb
Host smart-f0d3d568-ac1e-431b-b14f-dc6a951cc5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556063244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3556063244
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3343785707
Short name T337
Test name
Test status
Simulation time 95838358 ps
CPU time 1.4 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218228 kb
Host smart-23b4aede-ec50-4e35-ac08-29ffa5f9fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343785707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3343785707
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.4125540934
Short name T344
Test name
Test status
Simulation time 53317740 ps
CPU time 1.47 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218064 kb
Host smart-261a8d76-693c-40e6-93eb-020862fa0d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125540934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.4125540934
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.2022806804
Short name T713
Test name
Test status
Simulation time 254947661 ps
CPU time 2.72 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 219852 kb
Host smart-3a4f3f87-4502-435b-8f49-407e05964de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022806804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.2022806804
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1220360504
Short name T465
Test name
Test status
Simulation time 123413288 ps
CPU time 1.3 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 216792 kb
Host smart-aec8ab92-f82a-48a3-b4f1-a7c93e27ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220360504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1220360504
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3412550535
Short name T701
Test name
Test status
Simulation time 55804672 ps
CPU time 1.97 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 218324 kb
Host smart-717fed0f-c6c6-4b2d-8f44-e9fb79b049c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412550535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3412550535
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3454209485
Short name T411
Test name
Test status
Simulation time 57335116 ps
CPU time 1.6 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:07 PM PDT 24
Peak memory 217996 kb
Host smart-578bb6f2-ecf7-481e-bb8b-5b76d7c45309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454209485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3454209485
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1338787668
Short name T586
Test name
Test status
Simulation time 98425771 ps
CPU time 1.41 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 216904 kb
Host smart-002ae871-9cd7-414e-a2a8-9fe8e6f75d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338787668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1338787668
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.2286881014
Short name T415
Test name
Test status
Simulation time 14563599 ps
CPU time 0.9 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 206400 kb
Host smart-29783a87-2d39-4dab-9091-daf74cf37469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286881014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2286881014
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.2565309368
Short name T182
Test name
Test status
Simulation time 14176020 ps
CPU time 0.94 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 216352 kb
Host smart-08b51f09-9cfd-4841-94f1-2be0bf975570
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565309368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2565309368
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3703343106
Short name T254
Test name
Test status
Simulation time 36383006 ps
CPU time 1.04 seconds
Started Jun 06 02:39:25 PM PDT 24
Finished Jun 06 02:39:27 PM PDT 24
Peak memory 218204 kb
Host smart-6b8fed21-c255-4c1d-b844-4db55929bcac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703343106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3703343106
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_genbits.3804738818
Short name T729
Test name
Test status
Simulation time 98574204 ps
CPU time 1.16 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:28 PM PDT 24
Peak memory 217204 kb
Host smart-adcfcdff-212a-4bf3-8ddc-2f02752cefa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804738818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3804738818
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_smoke.2175079878
Short name T211
Test name
Test status
Simulation time 46027506 ps
CPU time 0.89 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 215208 kb
Host smart-63d1ff1a-ed06-4fe1-b243-b1a57a0fdf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175079878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2175079878
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.779980683
Short name T538
Test name
Test status
Simulation time 172664994 ps
CPU time 1.52 seconds
Started Jun 06 02:39:31 PM PDT 24
Finished Jun 06 02:39:36 PM PDT 24
Peak memory 214796 kb
Host smart-1b660685-c35e-45bb-aef6-67f33971694e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779980683 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.779980683
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3857931704
Short name T209
Test name
Test status
Simulation time 74198726749 ps
CPU time 1361.06 seconds
Started Jun 06 02:39:33 PM PDT 24
Finished Jun 06 03:02:16 PM PDT 24
Peak memory 222976 kb
Host smart-14d6c77e-0614-48a2-b4e2-064ec1a803f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857931704 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3857931704
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3036464875
Short name T520
Test name
Test status
Simulation time 40108913 ps
CPU time 1.48 seconds
Started Jun 06 02:40:42 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 218164 kb
Host smart-5bfeb690-41d3-4d7b-83f6-cc6af33b8e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036464875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3036464875
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.329064921
Short name T437
Test name
Test status
Simulation time 99058428 ps
CPU time 2.18 seconds
Started Jun 06 02:40:54 PM PDT 24
Finished Jun 06 02:40:58 PM PDT 24
Peak memory 219560 kb
Host smart-d22cd4b8-8f52-4a13-a187-9b7bb7a57f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329064921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.329064921
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2943041833
Short name T776
Test name
Test status
Simulation time 25540933 ps
CPU time 1.2 seconds
Started Jun 06 02:40:42 PM PDT 24
Finished Jun 06 02:40:45 PM PDT 24
Peak memory 215240 kb
Host smart-d6e6b1ab-1ea2-4d81-8bf2-1ee4fb2103bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943041833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2943041833
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3443694370
Short name T689
Test name
Test status
Simulation time 67378030 ps
CPU time 1.07 seconds
Started Jun 06 02:40:47 PM PDT 24
Finished Jun 06 02:40:51 PM PDT 24
Peak memory 216952 kb
Host smart-309019c4-ca93-43e2-a202-19eeb8032e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443694370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3443694370
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2449942546
Short name T374
Test name
Test status
Simulation time 192592769 ps
CPU time 2.34 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 215284 kb
Host smart-8773a3cc-bc26-4d0c-9647-35e68eeafb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449942546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2449942546
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.485144787
Short name T741
Test name
Test status
Simulation time 103396681 ps
CPU time 2.01 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218528 kb
Host smart-bf9a9e4b-5ea4-4c3b-a18e-48b5ffc9629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485144787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.485144787
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1184583299
Short name T821
Test name
Test status
Simulation time 44581284 ps
CPU time 1.58 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 216800 kb
Host smart-3dbceb51-3c10-4a90-92a4-b4954ecc0798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184583299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1184583299
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3289977755
Short name T334
Test name
Test status
Simulation time 38392746 ps
CPU time 1.45 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 218252 kb
Host smart-04cce5ee-bbc9-4588-9ffe-fe5c7eda3643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289977755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3289977755
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2068703500
Short name T511
Test name
Test status
Simulation time 43139068 ps
CPU time 1.55 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 219628 kb
Host smart-5f303904-f25d-47a5-9ac8-3dfb895bc310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068703500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2068703500
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2372646195
Short name T492
Test name
Test status
Simulation time 64814527 ps
CPU time 1.01 seconds
Started Jun 06 02:40:43 PM PDT 24
Finished Jun 06 02:40:46 PM PDT 24
Peak memory 216996 kb
Host smart-c42fa406-e0e4-43ca-bce2-54d371696c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372646195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2372646195
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.64044085
Short name T90
Test name
Test status
Simulation time 20491896 ps
CPU time 1.01 seconds
Started Jun 06 02:39:25 PM PDT 24
Finished Jun 06 02:39:27 PM PDT 24
Peak memory 206556 kb
Host smart-985ae77b-d78a-4782-971c-8f8961bd49f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64044085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.64044085
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.1516710877
Short name T201
Test name
Test status
Simulation time 12973322 ps
CPU time 0.86 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:28 PM PDT 24
Peak memory 215288 kb
Host smart-f5761e8f-e3ad-4502-878c-89793ecb902e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516710877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1516710877
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3089206776
Short name T823
Test name
Test status
Simulation time 32727625 ps
CPU time 1.05 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:29 PM PDT 24
Peak memory 218152 kb
Host smart-263e81c5-7496-4cb7-9875-73f37ccb1ddb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089206776 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3089206776
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.4011345405
Short name T831
Test name
Test status
Simulation time 36116050 ps
CPU time 0.9 seconds
Started Jun 06 02:39:31 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 218180 kb
Host smart-b0a3ca81-03cf-4450-ab95-9c940de4c1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011345405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4011345405
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_intr.1194924666
Short name T585
Test name
Test status
Simulation time 38945901 ps
CPU time 0.91 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 215352 kb
Host smart-96b0cb38-9b8a-4763-b1a6-2b33809ead20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194924666 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1194924666
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.292015905
Short name T373
Test name
Test status
Simulation time 15424514 ps
CPU time 0.96 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 215236 kb
Host smart-0c1f5692-b7f3-4ea4-a01e-d28afc6f0474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292015905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.292015905
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3262005701
Short name T312
Test name
Test status
Simulation time 671978499 ps
CPU time 4.3 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 216816 kb
Host smart-79c5dfa1-b6c8-4b4c-84e9-15492efbf4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262005701 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3262005701
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1920911260
Short name T43
Test name
Test status
Simulation time 164442641051 ps
CPU time 2232.93 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 03:16:43 PM PDT 24
Peak memory 229860 kb
Host smart-57035be9-17fd-42ca-83bd-8015f3463b78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920911260 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1920911260
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1019029549
Short name T216
Test name
Test status
Simulation time 93521040 ps
CPU time 3.19 seconds
Started Jun 06 02:40:42 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 218232 kb
Host smart-cb090be8-fa1a-44da-8638-20814ed043eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019029549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1019029549
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3097613843
Short name T341
Test name
Test status
Simulation time 42785804 ps
CPU time 1.32 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 216912 kb
Host smart-6f8be01f-da21-4500-bfc1-0fc2e0389e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097613843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3097613843
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.774460938
Short name T480
Test name
Test status
Simulation time 34156866 ps
CPU time 1.41 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 218508 kb
Host smart-745808ac-ed04-4166-bb56-e9ef78bc0a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774460938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.774460938
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.372809460
Short name T507
Test name
Test status
Simulation time 55609439 ps
CPU time 1.19 seconds
Started Jun 06 02:40:46 PM PDT 24
Finished Jun 06 02:40:50 PM PDT 24
Peak memory 218504 kb
Host smart-591a118a-b946-442d-a8e2-90a1931d74b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372809460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.372809460
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3351116398
Short name T565
Test name
Test status
Simulation time 85158351 ps
CPU time 1.54 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 218320 kb
Host smart-96ef915e-2381-43ac-b150-a4b92c6a8525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351116398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3351116398
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2914095137
Short name T591
Test name
Test status
Simulation time 34091401 ps
CPU time 1.45 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 218240 kb
Host smart-bbab1a83-b366-43d4-9962-829187d618cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914095137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2914095137
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.208977657
Short name T402
Test name
Test status
Simulation time 50389617 ps
CPU time 1.9 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 218036 kb
Host smart-cd89e531-1acb-4667-9da4-0f81cd11b3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208977657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.208977657
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.4150869373
Short name T469
Test name
Test status
Simulation time 95065769 ps
CPU time 1.46 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:07 PM PDT 24
Peak memory 217968 kb
Host smart-0b99a60c-93b1-4a78-9bc6-1a356cd67334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150869373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.4150869373
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1345664477
Short name T418
Test name
Test status
Simulation time 58580522 ps
CPU time 1.28 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218468 kb
Host smart-f0f5a778-8592-4b90-a7b2-24e6b40115ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345664477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1345664477
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1666973741
Short name T814
Test name
Test status
Simulation time 38197905 ps
CPU time 1.35 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 218048 kb
Host smart-c2c411dd-bd9e-4330-b4dd-98374bc003f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666973741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1666973741
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.1763606817
Short name T588
Test name
Test status
Simulation time 21750242 ps
CPU time 0.85 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 206244 kb
Host smart-7351c02c-ddfc-4d84-b8eb-276333552f59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763606817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1763606817
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3493596561
Short name T159
Test name
Test status
Simulation time 121983648 ps
CPU time 0.82 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 216272 kb
Host smart-07a87065-e29b-4ca4-b5dd-452a1e665779
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493596561 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3493596561
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2474847252
Short name T473
Test name
Test status
Simulation time 111554090 ps
CPU time 1.17 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 216652 kb
Host smart-c8ed9758-2d39-4abc-accf-12715868e79a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474847252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2474847252
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.4222994908
Short name T444
Test name
Test status
Simulation time 26348302 ps
CPU time 0.95 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 219600 kb
Host smart-36ad2390-387f-463e-bd17-850c1c93791f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222994908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4222994908
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3601618820
Short name T45
Test name
Test status
Simulation time 41986822 ps
CPU time 1.55 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:31 PM PDT 24
Peak memory 217084 kb
Host smart-71ae67a0-2483-474d-9b22-700ea6e83485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601618820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3601618820
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.4177788405
Short name T756
Test name
Test status
Simulation time 25053606 ps
CPU time 1 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 215300 kb
Host smart-5a1c95a6-ea1a-4493-baff-94f61d315a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177788405 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.4177788405
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3454367043
Short name T377
Test name
Test status
Simulation time 22233918 ps
CPU time 0.95 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 215220 kb
Host smart-d4574c66-1886-4933-973c-0b2d4089ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454367043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3454367043
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1951780760
Short name T61
Test name
Test status
Simulation time 377467816 ps
CPU time 3.45 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 215168 kb
Host smart-7cb37cd3-9e29-41d9-ae99-3cb4c1aca876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951780760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1951780760
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1563054497
Short name T67
Test name
Test status
Simulation time 34084521212 ps
CPU time 382.69 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:45:54 PM PDT 24
Peak memory 218620 kb
Host smart-d00fe635-1c34-42d2-a63f-e26ffc9b5252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563054497 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1563054497
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1654320811
Short name T752
Test name
Test status
Simulation time 65559622 ps
CPU time 1.09 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 216872 kb
Host smart-0d7492ae-f5c4-4711-a8f4-e9670a473481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654320811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1654320811
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2787502621
Short name T453
Test name
Test status
Simulation time 183278573 ps
CPU time 2.44 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 219424 kb
Host smart-0ab8057d-dee4-4d38-b69c-5056c92a688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787502621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2787502621
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.274288408
Short name T370
Test name
Test status
Simulation time 45805179 ps
CPU time 1.6 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 218136 kb
Host smart-529a31bd-303a-4a53-8518-ffca23b85e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274288408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.274288408
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1530270088
Short name T759
Test name
Test status
Simulation time 178426977 ps
CPU time 2.77 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:08 PM PDT 24
Peak memory 219692 kb
Host smart-0b77b571-5197-4da5-83d6-04e7325c02d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530270088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1530270088
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4050367599
Short name T542
Test name
Test status
Simulation time 122986075 ps
CPU time 1.92 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 219728 kb
Host smart-267dee0a-01c6-4a17-b434-cde2901c80ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050367599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4050367599
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1444401733
Short name T827
Test name
Test status
Simulation time 37508260 ps
CPU time 1.14 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:06 PM PDT 24
Peak memory 217016 kb
Host smart-80730b06-7836-4195-8baf-9b60dfa65352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444401733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1444401733
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1059256377
Short name T403
Test name
Test status
Simulation time 96499658 ps
CPU time 2 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:48 PM PDT 24
Peak memory 219788 kb
Host smart-25ad486b-ec6d-4b01-9511-021b1e6f0bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059256377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1059256377
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2641165790
Short name T731
Test name
Test status
Simulation time 27249767 ps
CPU time 1.29 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 216500 kb
Host smart-1460d797-8af5-4aa8-ab58-0c7be4c67aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641165790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2641165790
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2284331613
Short name T486
Test name
Test status
Simulation time 29854202 ps
CPU time 1.25 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 216916 kb
Host smart-16375174-668b-46fc-ae9e-91d0289e1b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284331613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2284331613
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.559502811
Short name T838
Test name
Test status
Simulation time 66905469 ps
CPU time 2.4 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 219760 kb
Host smart-c1b73af3-119d-4bf4-adbf-20c5ac217a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559502811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.559502811
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.925803973
Short name T784
Test name
Test status
Simulation time 35811294 ps
CPU time 0.8 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 214832 kb
Host smart-158fe756-9028-4bcd-af33-7ba6416b5e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925803973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.925803973
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2007067895
Short name T199
Test name
Test status
Simulation time 37063208 ps
CPU time 0.89 seconds
Started Jun 06 02:39:27 PM PDT 24
Finished Jun 06 02:39:30 PM PDT 24
Peak memory 216128 kb
Host smart-59f86e65-fdef-4d86-88ae-2bb2425600bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007067895 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2007067895
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.16002166
Short name T256
Test name
Test status
Simulation time 48704331 ps
CPU time 1.15 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 216880 kb
Host smart-4a50749e-1d62-455f-b69c-a86009bc9d10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16002166 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_dis
able_auto_req_mode.16002166
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1538816574
Short name T549
Test name
Test status
Simulation time 21986424 ps
CPU time 1.12 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 218384 kb
Host smart-da579a36-f643-418a-b4b1-1b88457d1a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538816574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1538816574
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2844055901
Short name T503
Test name
Test status
Simulation time 63622839 ps
CPU time 1.7 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:34 PM PDT 24
Peak memory 218260 kb
Host smart-fe9d0b8c-97cd-4d3a-9085-067a91066f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844055901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2844055901
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3597372267
Short name T618
Test name
Test status
Simulation time 44623079 ps
CPU time 0.89 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 215272 kb
Host smart-1dc686d2-41fa-469a-b62a-1027f567844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597372267 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3597372267
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.698857988
Short name T818
Test name
Test status
Simulation time 52734258 ps
CPU time 0.86 seconds
Started Jun 06 02:39:26 PM PDT 24
Finished Jun 06 02:39:28 PM PDT 24
Peak memory 215224 kb
Host smart-4146526f-5ae3-409f-933f-5a122cf7b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698857988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.698857988
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.445995116
Short name T628
Test name
Test status
Simulation time 424211265 ps
CPU time 1.76 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 216652 kb
Host smart-654f65fe-c016-415f-911b-4c57487483dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445995116 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.445995116
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1157800538
Short name T500
Test name
Test status
Simulation time 65947130109 ps
CPU time 1520.2 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 03:04:53 PM PDT 24
Peak memory 222060 kb
Host smart-7472a544-28d1-4272-9d29-0a41013e392e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157800538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1157800538
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1409598151
Short name T327
Test name
Test status
Simulation time 46672247 ps
CPU time 1.49 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:07 PM PDT 24
Peak memory 216840 kb
Host smart-19fb98e2-cd84-4389-afce-edb407d0a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409598151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1409598151
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1686825810
Short name T541
Test name
Test status
Simulation time 43940267 ps
CPU time 1.54 seconds
Started Jun 06 02:41:02 PM PDT 24
Finished Jun 06 02:41:07 PM PDT 24
Peak memory 218180 kb
Host smart-bcfdeef7-dbf2-4b72-b506-8a52b3d0d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686825810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1686825810
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3714078833
Short name T506
Test name
Test status
Simulation time 62076649 ps
CPU time 1.51 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 218140 kb
Host smart-a3cb1703-c6f8-4446-9247-65305852e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714078833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3714078833
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1155744934
Short name T522
Test name
Test status
Simulation time 59655027 ps
CPU time 1.01 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 217000 kb
Host smart-e4d7d181-ccb3-42cc-8b46-46fb2f273b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155744934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1155744934
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.333799153
Short name T680
Test name
Test status
Simulation time 236367161 ps
CPU time 1.09 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 216924 kb
Host smart-a543a2d6-55a2-444d-a6ad-4259f4f93fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333799153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.333799153
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.334024287
Short name T318
Test name
Test status
Simulation time 85135995 ps
CPU time 1.12 seconds
Started Jun 06 02:40:49 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 216780 kb
Host smart-0b30ee29-531f-4e27-95d6-ecdffea69b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334024287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.334024287
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2489465306
Short name T517
Test name
Test status
Simulation time 51719856 ps
CPU time 1.28 seconds
Started Jun 06 02:40:44 PM PDT 24
Finished Jun 06 02:40:47 PM PDT 24
Peak memory 219392 kb
Host smart-db228edd-a389-4efd-8336-0f8daa9176f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489465306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2489465306
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1924138523
Short name T279
Test name
Test status
Simulation time 92048332 ps
CPU time 1.6 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 217944 kb
Host smart-e4cdb433-d745-415d-aa2e-07ea4ce624b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924138523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1924138523
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.761557387
Short name T536
Test name
Test status
Simulation time 49152630 ps
CPU time 1.83 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 219628 kb
Host smart-70365454-38aa-4c7d-80f9-6a156b48834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761557387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.761557387
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3983442187
Short name T320
Test name
Test status
Simulation time 40765207 ps
CPU time 1.41 seconds
Started Jun 06 02:40:45 PM PDT 24
Finished Jun 06 02:40:49 PM PDT 24
Peak memory 218080 kb
Host smart-bbc30690-0752-4b08-8df7-9bdb2840f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983442187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3983442187
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.383211829
Short name T144
Test name
Test status
Simulation time 38417693 ps
CPU time 1.06 seconds
Started Jun 06 02:39:33 PM PDT 24
Finished Jun 06 02:39:37 PM PDT 24
Peak memory 218124 kb
Host smart-7e1155fb-cb5a-4548-8716-fd7b5deed2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383211829 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.383211829
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2237102794
Short name T613
Test name
Test status
Simulation time 43042780 ps
CPU time 1 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 206524 kb
Host smart-57718587-7203-41e7-8968-68bd0a0ecf6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237102794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2237102794
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1632303392
Short name T108
Test name
Test status
Simulation time 28461089 ps
CPU time 1.17 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 216828 kb
Host smart-a9065b31-2813-44e4-87d6-8ef06d487f13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632303392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1632303392
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.748764520
Short name T399
Test name
Test status
Simulation time 25990041 ps
CPU time 1.16 seconds
Started Jun 06 02:39:33 PM PDT 24
Finished Jun 06 02:39:36 PM PDT 24
Peak memory 220652 kb
Host smart-0d202be5-0552-46aa-8e90-a5cb64397b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748764520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.748764520
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1584709460
Short name T691
Test name
Test status
Simulation time 87011414 ps
CPU time 1.13 seconds
Started Jun 06 02:39:33 PM PDT 24
Finished Jun 06 02:39:37 PM PDT 24
Peak memory 216980 kb
Host smart-3162edd5-e423-4730-908b-704d95d54e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584709460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1584709460
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4046302739
Short name T93
Test name
Test status
Simulation time 25065074 ps
CPU time 0.97 seconds
Started Jun 06 02:39:28 PM PDT 24
Finished Jun 06 02:39:32 PM PDT 24
Peak memory 215756 kb
Host smart-be635441-d4b8-4cfa-9842-cf070016b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046302739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4046302739
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.670030777
Short name T750
Test name
Test status
Simulation time 28005937 ps
CPU time 0.95 seconds
Started Jun 06 02:39:31 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 215136 kb
Host smart-7333db1e-dd96-4b04-b482-56bcbabd13c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670030777 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.670030777
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.191378059
Short name T681
Test name
Test status
Simulation time 1022138853 ps
CPU time 3.37 seconds
Started Jun 06 02:39:33 PM PDT 24
Finished Jun 06 02:39:39 PM PDT 24
Peak memory 215240 kb
Host smart-12db4b21-5148-426f-b28d-e7106faf4183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191378059 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.191378059
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1071662210
Short name T789
Test name
Test status
Simulation time 120534261107 ps
CPU time 1905.68 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 03:11:19 PM PDT 24
Peak memory 226936 kb
Host smart-1d99f90a-645c-457e-8ddc-8eb9d16beee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071662210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1071662210
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4073972388
Short name T307
Test name
Test status
Simulation time 71460017 ps
CPU time 1.1 seconds
Started Jun 06 02:40:48 PM PDT 24
Finished Jun 06 02:40:52 PM PDT 24
Peak memory 219452 kb
Host smart-74519d0c-a353-4fd8-a4f8-d876fc8cacef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073972388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4073972388
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.4211121405
Short name T464
Test name
Test status
Simulation time 105874546 ps
CPU time 1.74 seconds
Started Jun 06 02:41:01 PM PDT 24
Finished Jun 06 02:41:05 PM PDT 24
Peak memory 218660 kb
Host smart-2d23fe58-d7f3-4846-8325-fdfec88269f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211121405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.4211121405
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1252919554
Short name T785
Test name
Test status
Simulation time 42037586 ps
CPU time 1.35 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 216948 kb
Host smart-a8f58610-26b2-4ff7-863d-7a9241f08eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252919554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1252919554
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2701981785
Short name T50
Test name
Test status
Simulation time 65361805 ps
CPU time 1.31 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:55 PM PDT 24
Peak memory 217228 kb
Host smart-90289d05-fada-4d0d-b0c2-75243630b58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701981785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2701981785
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3614539370
Short name T347
Test name
Test status
Simulation time 66015962 ps
CPU time 1.33 seconds
Started Jun 06 02:40:54 PM PDT 24
Finished Jun 06 02:40:58 PM PDT 24
Peak memory 217940 kb
Host smart-66648b71-66a4-4ac9-9335-3611a8cfeaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614539370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3614539370
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1822836021
Short name T372
Test name
Test status
Simulation time 63688578 ps
CPU time 1.1 seconds
Started Jun 06 02:40:50 PM PDT 24
Finished Jun 06 02:40:53 PM PDT 24
Peak memory 218420 kb
Host smart-cdfb7e96-c078-42c9-b639-87c320014a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822836021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1822836021
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.132545711
Short name T554
Test name
Test status
Simulation time 53076444 ps
CPU time 2.01 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 219832 kb
Host smart-67d7746f-c54b-490f-8b47-1abb0635af8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132545711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.132545711
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2260695832
Short name T505
Test name
Test status
Simulation time 84912379 ps
CPU time 2.92 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 218992 kb
Host smart-af2c5937-5b7e-425d-8ea8-a31d7a69ec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260695832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2260695832
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3203295893
Short name T677
Test name
Test status
Simulation time 43315586 ps
CPU time 1.5 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 218304 kb
Host smart-84ffa451-f3dd-411e-9b1a-ed8cdf7e37bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203295893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3203295893
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.847681995
Short name T450
Test name
Test status
Simulation time 93635276 ps
CPU time 1.45 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:55 PM PDT 24
Peak memory 218668 kb
Host smart-62d8de35-e8b6-42f2-99f7-be792c9ce6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847681995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.847681995
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.195420199
Short name T609
Test name
Test status
Simulation time 20555613 ps
CPU time 0.97 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 206560 kb
Host smart-010ba759-aa43-409f-bc1f-9ac9c24ac889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195420199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.195420199
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1925970018
Short name T638
Test name
Test status
Simulation time 13444370 ps
CPU time 0.91 seconds
Started Jun 06 02:39:41 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 216312 kb
Host smart-efdd82de-492e-439d-8108-ae02d669dc2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925970018 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1925970018
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2859857614
Short name T405
Test name
Test status
Simulation time 75254974 ps
CPU time 1.08 seconds
Started Jun 06 02:39:43 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 216780 kb
Host smart-8ccb3f5d-e908-43cb-949b-28d07b7a1586
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859857614 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2859857614
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.1229691614
Short name T156
Test name
Test status
Simulation time 20485248 ps
CPU time 1 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 223996 kb
Host smart-5ee2cf55-90a8-406a-9d80-3f922d4823c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229691614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1229691614
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4253245716
Short name T751
Test name
Test status
Simulation time 276909483 ps
CPU time 1.62 seconds
Started Jun 06 02:39:31 PM PDT 24
Finished Jun 06 02:39:36 PM PDT 24
Peak memory 218436 kb
Host smart-bfba03e9-3aff-445b-9308-b928deb3d133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253245716 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4253245716
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.1202122826
Short name T573
Test name
Test status
Simulation time 50757951 ps
CPU time 0.97 seconds
Started Jun 06 02:39:29 PM PDT 24
Finished Jun 06 02:39:33 PM PDT 24
Peak memory 223784 kb
Host smart-5056e55c-bfe2-4a9f-8e29-f6ac662d6ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202122826 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1202122826
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2453726495
Short name T478
Test name
Test status
Simulation time 28464950 ps
CPU time 0.92 seconds
Started Jun 06 02:39:31 PM PDT 24
Finished Jun 06 02:39:35 PM PDT 24
Peak memory 214776 kb
Host smart-7555216f-0b21-43ef-9423-759c4d0cf643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453726495 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2453726495
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.320822645
Short name T682
Test name
Test status
Simulation time 409210645 ps
CPU time 4.43 seconds
Started Jun 06 02:39:30 PM PDT 24
Finished Jun 06 02:39:38 PM PDT 24
Peak memory 215228 kb
Host smart-2d47163e-c20d-46b2-bc9f-f8e037ab923d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320822645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.320822645
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.721425027
Short name T472
Test name
Test status
Simulation time 22495187011 ps
CPU time 504.4 seconds
Started Jun 06 02:39:32 PM PDT 24
Finished Jun 06 02:47:59 PM PDT 24
Peak memory 223060 kb
Host smart-1500e173-7ae4-42af-9e33-8f8b53d944f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721425027 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.721425027
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1178600436
Short name T676
Test name
Test status
Simulation time 35750325 ps
CPU time 1.3 seconds
Started Jun 06 02:40:51 PM PDT 24
Finished Jun 06 02:40:54 PM PDT 24
Peak memory 217952 kb
Host smart-7b99bcf8-ca6c-471d-b1c6-c2b6e619bce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178600436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1178600436
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2008893123
Short name T551
Test name
Test status
Simulation time 50417511 ps
CPU time 1.25 seconds
Started Jun 06 02:40:54 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 219348 kb
Host smart-30cb13dc-1204-49a6-916f-f1da4a3c88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008893123 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2008893123
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1179067397
Short name T546
Test name
Test status
Simulation time 45395824 ps
CPU time 1.5 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 218056 kb
Host smart-f187d324-b54e-4038-8274-e1a5d797ce84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179067397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1179067397
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3454414492
Short name T432
Test name
Test status
Simulation time 42103293 ps
CPU time 1.57 seconds
Started Jun 06 02:41:01 PM PDT 24
Finished Jun 06 02:41:04 PM PDT 24
Peak memory 217840 kb
Host smart-3a5c2e04-23a5-4ce6-8a78-a008e89f81c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454414492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3454414492
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1174218031
Short name T674
Test name
Test status
Simulation time 85878135 ps
CPU time 1.25 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:55 PM PDT 24
Peak memory 217040 kb
Host smart-6a5225db-e400-4217-90e7-8673dbd870a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174218031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1174218031
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3075885926
Short name T514
Test name
Test status
Simulation time 42000662 ps
CPU time 1.4 seconds
Started Jun 06 02:40:51 PM PDT 24
Finished Jun 06 02:40:54 PM PDT 24
Peak memory 216940 kb
Host smart-c1a14edf-9f8c-4b25-86d9-34478b82c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075885926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3075885926
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3662716680
Short name T324
Test name
Test status
Simulation time 71163807 ps
CPU time 2.43 seconds
Started Jun 06 02:40:56 PM PDT 24
Finished Jun 06 02:41:00 PM PDT 24
Peak memory 219340 kb
Host smart-cfac9a4d-d29e-40f2-9d53-709d45a1feff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662716680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3662716680
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.41044990
Short name T494
Test name
Test status
Simulation time 42188965 ps
CPU time 1.5 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 218704 kb
Host smart-7ce7dc39-e883-491c-9a3f-b2b2bb477b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41044990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.41044990
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.589209171
Short name T678
Test name
Test status
Simulation time 60450062 ps
CPU time 2.28 seconds
Started Jun 06 02:40:56 PM PDT 24
Finished Jun 06 02:41:00 PM PDT 24
Peak memory 218128 kb
Host smart-6d2bbdad-879b-4729-b4a3-d9b67666d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589209171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.589209171
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.841926615
Short name T395
Test name
Test status
Simulation time 102958503 ps
CPU time 1.7 seconds
Started Jun 06 02:40:59 PM PDT 24
Finished Jun 06 02:41:03 PM PDT 24
Peak memory 218720 kb
Host smart-0161c124-eac3-487f-a94d-5b95a57a11ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841926615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.841926615
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2609360295
Short name T152
Test name
Test status
Simulation time 73666314 ps
CPU time 1.15 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 219072 kb
Host smart-710af9fe-0c74-4285-b8b3-d16b6023ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609360295 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2609360295
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.215472422
Short name T91
Test name
Test status
Simulation time 84062832 ps
CPU time 0.85 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 206260 kb
Host smart-ff8bbffb-97e1-4a79-aa1d-00a64c5c3c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215472422 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.215472422
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.3015080930
Short name T186
Test name
Test status
Simulation time 32510763 ps
CPU time 0.83 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 216120 kb
Host smart-218464fb-4f33-4f44-bc20-374bde545351
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015080930 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3015080930
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1663303936
Short name T718
Test name
Test status
Simulation time 52500975 ps
CPU time 1.16 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 216788 kb
Host smart-77ffaeca-a1fa-456d-affe-e997e74d98ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663303936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1663303936
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.704034697
Short name T165
Test name
Test status
Simulation time 19158356 ps
CPU time 1.08 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 218448 kb
Host smart-5c085eb7-9854-4455-971d-5208378d82aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704034697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.704034697
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.177037457
Short name T371
Test name
Test status
Simulation time 94527660 ps
CPU time 1.33 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 218400 kb
Host smart-90f0f2ea-08c4-43da-8e8d-1cdda21069f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177037457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.177037457
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2481123005
Short name T78
Test name
Test status
Simulation time 25810809 ps
CPU time 0.93 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215640 kb
Host smart-648fac85-40b7-473d-b6f2-d94824353104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481123005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2481123005
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3365881737
Short name T435
Test name
Test status
Simulation time 26589647 ps
CPU time 1 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 215200 kb
Host smart-4f5f62b8-6cd4-475f-9e22-34b82a173f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365881737 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3365881737
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.2946034619
Short name T544
Test name
Test status
Simulation time 319291083 ps
CPU time 2.21 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 219272 kb
Host smart-bbb07822-3bd5-47fb-8166-07049bd4abf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946034619 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2946034619
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1606263160
Short name T763
Test name
Test status
Simulation time 316961403201 ps
CPU time 1995.68 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 03:12:55 PM PDT 24
Peak memory 229196 kb
Host smart-58d933e3-20b8-47fe-9836-3bf0f6043c21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606263160 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1606263160
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2401520287
Short name T452
Test name
Test status
Simulation time 34211855 ps
CPU time 1.26 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:55 PM PDT 24
Peak memory 216848 kb
Host smart-fd9df9da-e622-4516-a1af-204403c4af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401520287 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2401520287
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3944438685
Short name T583
Test name
Test status
Simulation time 35464449 ps
CPU time 1.22 seconds
Started Jun 06 02:41:00 PM PDT 24
Finished Jun 06 02:41:04 PM PDT 24
Peak memory 218736 kb
Host smart-5f768c69-c6fe-4933-9efb-188a833a10c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944438685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3944438685
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3238246109
Short name T71
Test name
Test status
Simulation time 52612604 ps
CPU time 1.26 seconds
Started Jun 06 02:41:01 PM PDT 24
Finished Jun 06 02:41:04 PM PDT 24
Peak memory 218960 kb
Host smart-e5302bcd-7194-47ab-8d48-7c93f723ebc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238246109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3238246109
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2009205003
Short name T499
Test name
Test status
Simulation time 41833964 ps
CPU time 1.53 seconds
Started Jun 06 02:40:51 PM PDT 24
Finished Jun 06 02:40:55 PM PDT 24
Peak memory 218228 kb
Host smart-bb5972e1-9da5-461b-8d33-6ef385cfee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009205003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2009205003
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2182597254
Short name T697
Test name
Test status
Simulation time 126910718 ps
CPU time 1.68 seconds
Started Jun 06 02:40:53 PM PDT 24
Finished Jun 06 02:40:57 PM PDT 24
Peak memory 218384 kb
Host smart-b1df8c8b-7127-4307-a9b0-f5250c32b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182597254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2182597254
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.4219698637
Short name T398
Test name
Test status
Simulation time 42923376 ps
CPU time 1.42 seconds
Started Jun 06 02:40:52 PM PDT 24
Finished Jun 06 02:40:56 PM PDT 24
Peak memory 218236 kb
Host smart-eb82b768-a686-4bea-b2d5-f24cfe35d417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219698637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.4219698637
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.931845985
Short name T532
Test name
Test status
Simulation time 36015663 ps
CPU time 1.25 seconds
Started Jun 06 02:41:01 PM PDT 24
Finished Jun 06 02:41:04 PM PDT 24
Peak memory 219908 kb
Host smart-adafb590-2958-47d5-b2cd-af3bf2896e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931845985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.931845985
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1045648296
Short name T333
Test name
Test status
Simulation time 53967547 ps
CPU time 1.53 seconds
Started Jun 06 02:41:00 PM PDT 24
Finished Jun 06 02:41:03 PM PDT 24
Peak memory 218356 kb
Host smart-6d4b1f87-1793-4221-b51e-1564a41cffe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045648296 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1045648296
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3390272913
Short name T336
Test name
Test status
Simulation time 49216864 ps
CPU time 1.28 seconds
Started Jun 06 02:41:00 PM PDT 24
Finished Jun 06 02:41:04 PM PDT 24
Peak memory 217080 kb
Host smart-adb4c541-6b89-49c0-8831-b20654674cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390272913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3390272913
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1601086375
Short name T261
Test name
Test status
Simulation time 24903427 ps
CPU time 1.12 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:39 PM PDT 24
Peak memory 219040 kb
Host smart-9b3b350a-37fa-4e0c-96d9-9922c1e0e8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601086375 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1601086375
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.704601501
Short name T392
Test name
Test status
Simulation time 32925426 ps
CPU time 0.89 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 02:38:51 PM PDT 24
Peak memory 214696 kb
Host smart-8d7f9f21-1747-4dd6-a693-40ba0e27e285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704601501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.704601501
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.70717517
Short name T181
Test name
Test status
Simulation time 23250627 ps
CPU time 0.77 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 216132 kb
Host smart-5679838f-78e6-4d5a-a974-df6a3e0d4b0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70717517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.70717517
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.531455374
Short name T660
Test name
Test status
Simulation time 57191070 ps
CPU time 1.11 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:39 PM PDT 24
Peak memory 216652 kb
Host smart-aac05dee-f6e1-4ade-ba08-861b2ece9a21
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531455374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.531455374
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2555453540
Short name T615
Test name
Test status
Simulation time 18365820 ps
CPU time 1.07 seconds
Started Jun 06 02:38:41 PM PDT 24
Finished Jun 06 02:38:45 PM PDT 24
Peak memory 218628 kb
Host smart-6b19878b-ddda-4829-bfd0-2af73f2bf82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555453540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2555453540
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1896719753
Short name T460
Test name
Test status
Simulation time 83874232 ps
CPU time 1.51 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 02:38:40 PM PDT 24
Peak memory 218624 kb
Host smart-4a08d628-15c1-43dd-8a35-0605a1bae723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896719753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1896719753
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2652261392
Short name T720
Test name
Test status
Simulation time 19655992 ps
CPU time 1.17 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 215856 kb
Host smart-960fa89f-bfeb-4233-aeb0-ce5a4ee6da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652261392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2652261392
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.2975135630
Short name T19
Test name
Test status
Simulation time 511450759 ps
CPU time 4.45 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:45 PM PDT 24
Peak memory 235384 kb
Host smart-07fd16fd-5ffe-48e6-a329-a087a216436d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975135630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.2975135630
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1003462015
Short name T25
Test name
Test status
Simulation time 178531282 ps
CPU time 0.88 seconds
Started Jun 06 02:38:38 PM PDT 24
Finished Jun 06 02:38:41 PM PDT 24
Peak memory 214944 kb
Host smart-2c9402f6-ee8e-4ee3-a1dd-a1da2b1e7fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003462015 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1003462015
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.828252018
Short name T596
Test name
Test status
Simulation time 257705480 ps
CPU time 1.5 seconds
Started Jun 06 02:38:39 PM PDT 24
Finished Jun 06 02:38:42 PM PDT 24
Peak memory 217072 kb
Host smart-10ede2ee-01ec-494c-8e69-ea871655466e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828252018 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.828252018
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1614135496
Short name T716
Test name
Test status
Simulation time 226894622755 ps
CPU time 2315.27 seconds
Started Jun 06 02:38:36 PM PDT 24
Finished Jun 06 03:17:13 PM PDT 24
Peak memory 236104 kb
Host smart-b87d1881-d560-4de7-8186-6a36ed976c03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614135496 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1614135496
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.3066764462
Short name T385
Test name
Test status
Simulation time 54353806 ps
CPU time 0.91 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 215060 kb
Host smart-af7b6bd7-d56c-4814-b872-3fe4ce273ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066764462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3066764462
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3250114309
Short name T724
Test name
Test status
Simulation time 39593782 ps
CPU time 1.39 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:41 PM PDT 24
Peak memory 216796 kb
Host smart-5e72a483-cf22-49fc-bc03-9bd61fc078d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250114309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3250114309
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.482216495
Short name T600
Test name
Test status
Simulation time 20005652 ps
CPU time 1.02 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 218464 kb
Host smart-c3e2919c-b6d5-4561-912a-224c96bb4efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482216495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.482216495
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3301460178
Short name T820
Test name
Test status
Simulation time 159784201 ps
CPU time 3.09 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215236 kb
Host smart-9eb03782-d928-4094-b95d-79051818db6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301460178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3301460178
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3141676439
Short name T765
Test name
Test status
Simulation time 21118686 ps
CPU time 1.04 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 215360 kb
Host smart-935041ad-9a5a-4a44-b2db-9fea4214c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141676439 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3141676439
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3252781828
Short name T397
Test name
Test status
Simulation time 52073290 ps
CPU time 0.95 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 215168 kb
Host smart-5ee0c019-660d-44d0-a666-aef1ae7b2237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252781828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3252781828
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.676452630
Short name T381
Test name
Test status
Simulation time 544320361 ps
CPU time 6.09 seconds
Started Jun 06 02:39:45 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 216996 kb
Host smart-02fe7ceb-c8c3-4b4d-9b4b-231d22f918cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676452630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.676452630
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.814476953
Short name T579
Test name
Test status
Simulation time 79171690006 ps
CPU time 740.79 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:52:03 PM PDT 24
Peak memory 219600 kb
Host smart-b74fc406-4876-4876-97e0-dd16849851dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814476953 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.814476953
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.499971112
Short name T762
Test name
Test status
Simulation time 14318287 ps
CPU time 0.9 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 206508 kb
Host smart-29ec4908-1873-41a9-9ac7-8dc154bd5982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499971112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.499971112
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.161749926
Short name T475
Test name
Test status
Simulation time 55272126 ps
CPU time 0.88 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215944 kb
Host smart-ab85786e-1d1f-4066-a4d5-34debedb2801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161749926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.161749926
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1253174602
Short name T114
Test name
Test status
Simulation time 31795552 ps
CPU time 1.11 seconds
Started Jun 06 02:39:44 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 216656 kb
Host smart-865d7871-d1a7-43c6-aaad-2243a965dc8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253174602 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1253174602
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2819038458
Short name T97
Test name
Test status
Simulation time 22230934 ps
CPU time 1.13 seconds
Started Jun 06 02:39:41 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 229536 kb
Host smart-4949730a-3aaa-4000-a2af-62e8f9b36c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819038458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2819038458
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1385787202
Short name T306
Test name
Test status
Simulation time 84412761 ps
CPU time 1.18 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:39 PM PDT 24
Peak memory 219592 kb
Host smart-04af716a-be34-4a44-81b8-22dc8a1109db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385787202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1385787202
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.556111571
Short name T356
Test name
Test status
Simulation time 35972015 ps
CPU time 0.88 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 214992 kb
Host smart-172451de-a1d9-43cc-9ac0-4e473586f23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556111571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.556111571
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.3386720383
Short name T321
Test name
Test status
Simulation time 22504153 ps
CPU time 0.9 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 215236 kb
Host smart-600dbfe3-d89b-4adc-878f-b7db39f8da94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386720383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3386720383
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3209943870
Short name T619
Test name
Test status
Simulation time 656291006 ps
CPU time 6.39 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:18 PM PDT 24
Peak memory 215204 kb
Host smart-208a4969-38b3-4607-90a5-7adbe9c4751c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209943870 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3209943870
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1261687060
Short name T525
Test name
Test status
Simulation time 169649569111 ps
CPU time 1003.54 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:56:26 PM PDT 24
Peak memory 223908 kb
Host smart-62de3bfa-6da8-435d-878a-0c4b2c7a0d00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261687060 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1261687060
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2026631281
Short name T577
Test name
Test status
Simulation time 46849314 ps
CPU time 1.16 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:39:42 PM PDT 24
Peak memory 219264 kb
Host smart-9cc955e3-8a10-4139-85be-b033abcc763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026631281 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2026631281
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2435005837
Short name T643
Test name
Test status
Simulation time 17836399 ps
CPU time 0.94 seconds
Started Jun 06 02:39:43 PM PDT 24
Finished Jun 06 02:39:46 PM PDT 24
Peak memory 214644 kb
Host smart-1477e2bf-5742-4d57-95b0-ec66e99c3887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435005837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2435005837
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.3148111516
Short name T158
Test name
Test status
Simulation time 41503329 ps
CPU time 0.88 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 216124 kb
Host smart-ff92e562-a1a8-44cb-b10b-4562b6a9ffbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148111516 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.3148111516
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1015803964
Short name T739
Test name
Test status
Simulation time 99513049 ps
CPU time 1.16 seconds
Started Jun 06 02:39:37 PM PDT 24
Finished Jun 06 02:39:40 PM PDT 24
Peak memory 217016 kb
Host smart-d85db2b6-75a0-4d94-a6f0-20022b21d67b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015803964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1015803964
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2570819614
Short name T147
Test name
Test status
Simulation time 28689128 ps
CPU time 0.92 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 218124 kb
Host smart-686d11aa-89bc-4ef7-bd29-3f6747750932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570819614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2570819614
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1080234815
Short name T793
Test name
Test status
Simulation time 90613301 ps
CPU time 1.19 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 216892 kb
Host smart-880d3f76-36a9-4f3d-980d-92b5a1152dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080234815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1080234815
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1779572877
Short name T33
Test name
Test status
Simulation time 23600474 ps
CPU time 0.89 seconds
Started Jun 06 02:39:43 PM PDT 24
Finished Jun 06 02:39:46 PM PDT 24
Peak memory 215788 kb
Host smart-91802395-66ed-49f8-8f7b-a68fb12a8f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779572877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1779572877
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1011632388
Short name T311
Test name
Test status
Simulation time 18542368 ps
CPU time 1.03 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215168 kb
Host smart-8d574b24-9ba9-490d-b0b2-aeadb8038299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011632388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1011632388
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3366862060
Short name T212
Test name
Test status
Simulation time 207650818 ps
CPU time 0.92 seconds
Started Jun 06 02:39:41 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 206324 kb
Host smart-16b73bf6-9828-4cec-802e-494370f43c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366862060 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3366862060
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1425841223
Short name T692
Test name
Test status
Simulation time 20827487260 ps
CPU time 484.42 seconds
Started Jun 06 02:39:39 PM PDT 24
Finished Jun 06 02:47:45 PM PDT 24
Peak memory 223740 kb
Host smart-7d1b4e3f-8316-4f8b-ae43-29514d08659c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425841223 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1425841223
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.2429954655
Short name T118
Test name
Test status
Simulation time 120022827 ps
CPU time 1.07 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 219276 kb
Host smart-b82919e7-a4b0-4c2f-99b8-422242702ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429954655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.2429954655
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1917485075
Short name T328
Test name
Test status
Simulation time 19853557 ps
CPU time 0.95 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 206420 kb
Host smart-e4030986-027f-45ef-ab66-735c7240b35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917485075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1917485075
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1447136220
Short name T780
Test name
Test status
Simulation time 17653281 ps
CPU time 0.84 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215824 kb
Host smart-c7daf084-9e7c-44ea-aef3-a4eaaa4b51be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447136220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1447136220
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2241758117
Short name T812
Test name
Test status
Simulation time 122139077 ps
CPU time 1.18 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 216764 kb
Host smart-f61c198a-a262-4254-89ca-756a22dd4e44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241758117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2241758117
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.126246945
Short name T131
Test name
Test status
Simulation time 60854685 ps
CPU time 0.91 seconds
Started Jun 06 02:39:43 PM PDT 24
Finished Jun 06 02:39:46 PM PDT 24
Peak memory 219540 kb
Host smart-3831f159-fe06-483f-853a-806c58a96876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126246945 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.126246945
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.543327941
Short name T594
Test name
Test status
Simulation time 81788035 ps
CPU time 1.38 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 218136 kb
Host smart-f5601c18-1e6a-4d16-bb21-3548258cece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543327941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.543327941
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1606406067
Short name T768
Test name
Test status
Simulation time 20973789 ps
CPU time 1.17 seconds
Started Jun 06 02:39:41 PM PDT 24
Finished Jun 06 02:39:44 PM PDT 24
Peak memory 215340 kb
Host smart-2c13d09e-40fe-4c2f-a898-cb22923126f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606406067 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1606406067
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.3781679111
Short name T809
Test name
Test status
Simulation time 27271074 ps
CPU time 0.98 seconds
Started Jun 06 02:39:40 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 215168 kb
Host smart-1e44820d-6e23-4073-bdc4-4b6b926b3bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781679111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3781679111
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2231286361
Short name T421
Test name
Test status
Simulation time 193805532 ps
CPU time 3.29 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:39:43 PM PDT 24
Peak memory 219440 kb
Host smart-4d73a300-92f5-471a-94b5-7dee2557f78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231286361 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2231286361
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2322380918
Short name T206
Test name
Test status
Simulation time 369618095677 ps
CPU time 797.8 seconds
Started Jun 06 02:39:38 PM PDT 24
Finished Jun 06 02:52:58 PM PDT 24
Peak memory 229992 kb
Host smart-2f459de0-a24b-47b7-8d0b-549521392fb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322380918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2322380918
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1193853831
Short name T32
Test name
Test status
Simulation time 43531215 ps
CPU time 1.25 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 219264 kb
Host smart-33dede3b-29b4-4860-a5fc-62095cbfe531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193853831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1193853831
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2190030901
Short name T706
Test name
Test status
Simulation time 34054436 ps
CPU time 1.01 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 214704 kb
Host smart-b30c3c00-2112-4a4b-b11c-31f3047507a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190030901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2190030901
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.89285173
Short name T150
Test name
Test status
Simulation time 44291580 ps
CPU time 0.81 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 216216 kb
Host smart-b4de3e81-588c-42d6-998c-ad8fdaca0828
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89285173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.89285173
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1147978417
Short name T133
Test name
Test status
Simulation time 38346685 ps
CPU time 1.23 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 216840 kb
Host smart-f9879b5b-7601-40d8-b1ce-d303c6ac333c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147978417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1147978417
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.2324383494
Short name T164
Test name
Test status
Simulation time 40012669 ps
CPU time 0.85 seconds
Started Jun 06 02:39:45 PM PDT 24
Finished Jun 06 02:39:47 PM PDT 24
Peak memory 218396 kb
Host smart-d4bef9f8-38fe-4453-8390-591b4c57b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324383494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2324383494
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.166156352
Short name T439
Test name
Test status
Simulation time 100168777 ps
CPU time 1.2 seconds
Started Jun 06 02:39:45 PM PDT 24
Finished Jun 06 02:39:48 PM PDT 24
Peak memory 219484 kb
Host smart-f805f328-f988-4695-bebb-ddeecb11104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166156352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.166156352
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_smoke.2512866761
Short name T247
Test name
Test status
Simulation time 49887532 ps
CPU time 0.91 seconds
Started Jun 06 02:39:42 PM PDT 24
Finished Jun 06 02:39:45 PM PDT 24
Peak memory 215248 kb
Host smart-1c67985e-8e7e-4650-b80f-2e90e8ed1d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512866761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2512866761
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3987110667
Short name T835
Test name
Test status
Simulation time 331340188 ps
CPU time 3.83 seconds
Started Jun 06 02:39:46 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 216952 kb
Host smart-b0cf0442-de19-47bc-8337-3e7b7711aced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987110667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3987110667
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2214876447
Short name T202
Test name
Test status
Simulation time 60956036118 ps
CPU time 1468.77 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 03:04:19 PM PDT 24
Peak memory 224560 kb
Host smart-b9f584b4-a15b-4c54-b7a7-b339c9afeb36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214876447 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2214876447
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.2328950855
Short name T83
Test name
Test status
Simulation time 50984213 ps
CPU time 1.14 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 215544 kb
Host smart-a119a8b9-7a8b-43d4-ae41-fccbae50f921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328950855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2328950855
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1078572735
Short name T797
Test name
Test status
Simulation time 14886054 ps
CPU time 0.9 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 206416 kb
Host smart-be4db7bd-d1ba-4136-b775-83d4a30d7045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078572735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1078572735
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3554779820
Short name T430
Test name
Test status
Simulation time 34176334 ps
CPU time 0.84 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 215848 kb
Host smart-fdd25ef6-0746-4d4d-be27-c3f2cc0c1908
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554779820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3554779820
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2189512582
Short name T99
Test name
Test status
Simulation time 116580448 ps
CPU time 1.17 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 216864 kb
Host smart-1b47d747-fced-48f7-9a91-1a82a0390dbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189512582 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2189512582
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.3549531461
Short name T59
Test name
Test status
Simulation time 20829375 ps
CPU time 1.21 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 229604 kb
Host smart-4fb9fbe2-3b2b-4955-b6e8-35b8c6743de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549531461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.3549531461
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.881141126
Short name T51
Test name
Test status
Simulation time 89358443 ps
CPU time 1.15 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 216936 kb
Host smart-1dfc1f93-aae4-493f-b58f-1ed853322cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881141126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.881141126
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4108891045
Short name T446
Test name
Test status
Simulation time 41883416 ps
CPU time 0.91 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 215480 kb
Host smart-af572c16-cd76-40ba-8409-c6076f229c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108891045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4108891045
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.454804600
Short name T695
Test name
Test status
Simulation time 24912954 ps
CPU time 1.02 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 215184 kb
Host smart-29119887-51ea-4529-b40f-fb05e1b8d8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454804600 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.454804600
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4195146573
Short name T684
Test name
Test status
Simulation time 631044776 ps
CPU time 4.1 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:56 PM PDT 24
Peak memory 220000 kb
Host smart-493bddb1-5a2d-4a76-988f-0bfdf5262495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195146573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4195146573
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3767373935
Short name T219
Test name
Test status
Simulation time 38159950372 ps
CPU time 476.78 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:47:47 PM PDT 24
Peak memory 223740 kb
Host smart-7044dfdc-08b5-414b-b3ea-fb42e6503e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767373935 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3767373935
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3643324211
Short name T778
Test name
Test status
Simulation time 70178946 ps
CPU time 1.27 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 220032 kb
Host smart-2bcbb726-36eb-44aa-a26b-613c1d206480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643324211 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3643324211
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2547957629
Short name T447
Test name
Test status
Simulation time 20267458 ps
CPU time 1.05 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:54 PM PDT 24
Peak memory 206512 kb
Host smart-3aec4c79-3a51-4f3f-b54c-0845216badfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547957629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2547957629
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2250033340
Short name T168
Test name
Test status
Simulation time 14015211 ps
CPU time 0.92 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 216360 kb
Host smart-d7311355-b858-4e3e-a021-2e99d02b25f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250033340 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2250033340
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1497687180
Short name T134
Test name
Test status
Simulation time 138512291 ps
CPU time 0.98 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:49 PM PDT 24
Peak memory 216880 kb
Host smart-92480175-9714-4310-bd50-ae39eebceb52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497687180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1497687180
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.428303585
Short name T679
Test name
Test status
Simulation time 50944499 ps
CPU time 0.97 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 220412 kb
Host smart-e44f617e-80a9-4d32-9952-cc4656f703ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428303585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.428303585
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2528592856
Short name T315
Test name
Test status
Simulation time 36290416 ps
CPU time 1.52 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 218432 kb
Host smart-7394275e-aaa6-4f7b-ac1f-797827da3160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528592856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2528592856
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2780758955
Short name T190
Test name
Test status
Simulation time 41005008 ps
CPU time 0.96 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 215488 kb
Host smart-b3501477-28ae-466c-a4a0-1b9b1edeb5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780758955 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2780758955
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.843160727
Short name T313
Test name
Test status
Simulation time 16463271 ps
CPU time 0.98 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:54 PM PDT 24
Peak memory 215208 kb
Host smart-45ba1321-ab8d-4abc-8b0b-c5588535f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843160727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.843160727
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.4053116766
Short name T707
Test name
Test status
Simulation time 321745689 ps
CPU time 2.21 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 215224 kb
Host smart-9f2d073d-f935-4421-855e-cc18d91aeec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053116766 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.4053116766
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3395594600
Short name T248
Test name
Test status
Simulation time 31399452251 ps
CPU time 805.86 seconds
Started Jun 06 02:39:45 PM PDT 24
Finished Jun 06 02:53:12 PM PDT 24
Peak memory 223644 kb
Host smart-dced6148-f958-4fd2-988f-f6b47b1b765d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395594600 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3395594600
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2045235129
Short name T663
Test name
Test status
Simulation time 39440210 ps
CPU time 1.16 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 218256 kb
Host smart-8de3b740-f6a4-45dd-9bb3-995131c09070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045235129 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2045235129
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1190270208
Short name T629
Test name
Test status
Simulation time 13931190 ps
CPU time 0.89 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 206868 kb
Host smart-f35d6c8b-83dd-4609-b670-5420b190b18b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190270208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1190270208
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3483436806
Short name T457
Test name
Test status
Simulation time 29189516 ps
CPU time 0.83 seconds
Started Jun 06 02:39:46 PM PDT 24
Finished Jun 06 02:39:49 PM PDT 24
Peak memory 215876 kb
Host smart-849a9ba3-99ac-42d6-b265-42acc19c19a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483436806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3483436806
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1881194301
Short name T757
Test name
Test status
Simulation time 70122598 ps
CPU time 0.99 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 218008 kb
Host smart-c9912a34-cc49-4131-9f0e-3843330eda33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881194301 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1881194301
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.4080953341
Short name T8
Test name
Test status
Simulation time 167411344 ps
CPU time 0.97 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 219880 kb
Host smart-7f3cd1df-aa6c-4c62-9d3a-1e4136e8c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080953341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.4080953341
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3766519163
Short name T325
Test name
Test status
Simulation time 36548858 ps
CPU time 1.39 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 219564 kb
Host smart-325448f7-8432-47ec-ac59-b1cff978f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766519163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3766519163
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1937450303
Short name T40
Test name
Test status
Simulation time 38234660 ps
CPU time 0.88 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 215500 kb
Host smart-b5b990f9-ec88-4264-9f15-b85e46e87cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937450303 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1937450303
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2750666648
Short name T734
Test name
Test status
Simulation time 19729938 ps
CPU time 0.99 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 215244 kb
Host smart-6c73fce2-110e-4ba1-9604-8ab4f9503d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750666648 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2750666648
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1320389139
Short name T606
Test name
Test status
Simulation time 250708288 ps
CPU time 5.11 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:56 PM PDT 24
Peak memory 216816 kb
Host smart-0de31e3d-37e7-4da1-9a3e-5dcec5645a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320389139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1320389139
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_alert_test.1111624844
Short name T409
Test name
Test status
Simulation time 90820504 ps
CPU time 0.82 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 205848 kb
Host smart-0e4b47cb-dc2a-4d81-85fc-71f40d6c4749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111624844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1111624844
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3689754297
Short name T151
Test name
Test status
Simulation time 29419370 ps
CPU time 0.81 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 215932 kb
Host smart-37e13a98-24d9-43c6-9e46-11303f842e41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689754297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3689754297
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2398448291
Short name T773
Test name
Test status
Simulation time 59531194 ps
CPU time 1.33 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 216948 kb
Host smart-f8a234e7-ecf8-4c2b-bc20-91cac35b0a16
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398448291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2398448291
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2887628898
Short name T126
Test name
Test status
Simulation time 22095421 ps
CPU time 1.13 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 219356 kb
Host smart-363c85ff-2ba7-4788-8d83-4b5d9112c755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887628898 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2887628898
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2564808830
Short name T218
Test name
Test status
Simulation time 68631962 ps
CPU time 1.31 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 218848 kb
Host smart-04ed7873-d28e-4517-a16a-4c30b18dbf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564808830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2564808830
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.4130455739
Short name T58
Test name
Test status
Simulation time 51419930 ps
CPU time 1 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:02 PM PDT 24
Peak memory 224040 kb
Host smart-bb5e56ba-8c03-479e-9cda-da44dd1621b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130455739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.4130455739
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.98401092
Short name T743
Test name
Test status
Simulation time 19314872 ps
CPU time 1.05 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 215172 kb
Host smart-f1b9f50b-5211-4ef1-a51d-e911faca7b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98401092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.98401092
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3327964261
Short name T604
Test name
Test status
Simulation time 203746030 ps
CPU time 2.35 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 219476 kb
Host smart-846d449e-99b0-4099-aee3-73d1ab8a3324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327964261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3327964261
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.894130741
Short name T753
Test name
Test status
Simulation time 40493393766 ps
CPU time 779.38 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:52:50 PM PDT 24
Peak memory 218332 kb
Host smart-f13d6efb-c4a4-4c9e-904a-47a35abc4f95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894130741 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.894130741
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3869558540
Short name T160
Test name
Test status
Simulation time 39300866 ps
CPU time 1.16 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 218048 kb
Host smart-32431d16-595c-4351-be9d-af3cf5fbcff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869558540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3869558540
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3723381720
Short name T481
Test name
Test status
Simulation time 16716864 ps
CPU time 0.95 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 206760 kb
Host smart-651cf46a-17de-46c1-bf26-f26dcde556bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723381720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3723381720
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2305318766
Short name T428
Test name
Test status
Simulation time 11287444 ps
CPU time 0.85 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 215844 kb
Host smart-d1e76dd3-986e-4f9a-a4f4-72906a0321d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305318766 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2305318766
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1381915625
Short name T107
Test name
Test status
Simulation time 82899158 ps
CPU time 1.2 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:50 PM PDT 24
Peak memory 216796 kb
Host smart-2028e390-9904-45d2-8995-0f3ba3d2ef02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381915625 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1381915625
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1488691041
Short name T173
Test name
Test status
Simulation time 25151978 ps
CPU time 0.95 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 219184 kb
Host smart-302c61a8-8e2b-4c1c-801a-4b69e10ff3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488691041 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1488691041
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2947375717
Short name T833
Test name
Test status
Simulation time 67938708 ps
CPU time 2.33 seconds
Started Jun 06 02:39:47 PM PDT 24
Finished Jun 06 02:39:51 PM PDT 24
Peak memory 219736 kb
Host smart-0274afd2-7a3e-4624-b4d8-43daadf02ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947375717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2947375717
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4208652573
Short name T696
Test name
Test status
Simulation time 28037633 ps
CPU time 0.88 seconds
Started Jun 06 02:39:50 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 215552 kb
Host smart-fe2292a6-0c5e-4459-afc3-a156aef29e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208652573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4208652573
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1419091859
Short name T386
Test name
Test status
Simulation time 20964307 ps
CPU time 1.06 seconds
Started Jun 06 02:39:50 PM PDT 24
Finished Jun 06 02:39:54 PM PDT 24
Peak memory 215188 kb
Host smart-540a034c-73cb-448b-8f31-caf29832b7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419091859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1419091859
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.325036429
Short name T5
Test name
Test status
Simulation time 903698063 ps
CPU time 4.79 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 216904 kb
Host smart-a38d2524-9325-4321-a965-3bd5df8a5bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325036429 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.325036429
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1241089388
Short name T205
Test name
Test status
Simulation time 298932271599 ps
CPU time 938.73 seconds
Started Jun 06 02:39:48 PM PDT 24
Finished Jun 06 02:55:30 PM PDT 24
Peak memory 221208 kb
Host smart-f1fe7061-2ed7-46c4-b2d1-e9f1f327b2e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241089388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1241089388
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1641476542
Short name T222
Test name
Test status
Simulation time 56149898 ps
CPU time 1.26 seconds
Started Jun 06 02:38:51 PM PDT 24
Finished Jun 06 02:38:53 PM PDT 24
Peak memory 219728 kb
Host smart-3c666480-cc86-48c8-bd0b-94c60b517f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641476542 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1641476542
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3637012290
Short name T382
Test name
Test status
Simulation time 14906839 ps
CPU time 0.89 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 206440 kb
Host smart-40f46270-8f76-4f6a-b163-ee83cd931cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637012290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3637012290
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1287339576
Short name T747
Test name
Test status
Simulation time 14989533 ps
CPU time 0.87 seconds
Started Jun 06 02:38:48 PM PDT 24
Finished Jun 06 02:38:51 PM PDT 24
Peak memory 216100 kb
Host smart-63d5561c-1d12-4378-a9d0-36692f70f598
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287339576 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1287339576
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2668498291
Short name T407
Test name
Test status
Simulation time 43524429 ps
CPU time 1.1 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 215452 kb
Host smart-0f57f511-2aff-4bec-a144-513168fe1759
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668498291 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2668498291
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.460116837
Short name T527
Test name
Test status
Simulation time 71652731 ps
CPU time 1.07 seconds
Started Jun 06 02:38:48 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 219384 kb
Host smart-3504aee9-4f19-4eac-b2b5-fed83af16abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460116837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.460116837
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1775669271
Short name T68
Test name
Test status
Simulation time 39614340 ps
CPU time 1.52 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:51 PM PDT 24
Peak memory 218264 kb
Host smart-44286ead-da33-4ef8-a6e2-fcb3c3826e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775669271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1775669271
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3640955969
Short name T641
Test name
Test status
Simulation time 21256354 ps
CPU time 1.2 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 223996 kb
Host smart-fc9c2e14-8827-4593-b976-44a5537774ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640955969 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3640955969
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1905390420
Short name T300
Test name
Test status
Simulation time 45511348 ps
CPU time 0.88 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 207104 kb
Host smart-158a4884-ecc8-464b-a861-01bf90228701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905390420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1905390420
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3235330184
Short name T20
Test name
Test status
Simulation time 1987965732 ps
CPU time 9.01 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:56 PM PDT 24
Peak memory 238664 kb
Host smart-085cd922-b7a2-4989-bb36-1487cf53a65c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235330184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3235330184
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3029463009
Short name T366
Test name
Test status
Simulation time 25315377 ps
CPU time 0.97 seconds
Started Jun 06 02:38:50 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 215172 kb
Host smart-72b2b041-bdcc-4b7c-bf36-b9bd15c7927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029463009 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3029463009
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2588506759
Short name T317
Test name
Test status
Simulation time 298942966 ps
CPU time 5.75 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:55 PM PDT 24
Peak memory 220156 kb
Host smart-3c94042a-154c-4db1-aaff-03c64958548e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588506759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2588506759
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.363976829
Short name T512
Test name
Test status
Simulation time 109309593699 ps
CPU time 2528.12 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 03:20:57 PM PDT 24
Peak memory 228944 kb
Host smart-570770bc-40f1-49b7-910d-ddc13b5f3778
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363976829 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.363976829
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2219916943
Short name T86
Test name
Test status
Simulation time 79488218 ps
CPU time 1.09 seconds
Started Jun 06 02:39:46 PM PDT 24
Finished Jun 06 02:39:49 PM PDT 24
Peak memory 218776 kb
Host smart-ed28d122-0e46-43d0-be6b-7597a61ce0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219916943 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2219916943
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1421842941
Short name T715
Test name
Test status
Simulation time 30684131 ps
CPU time 0.77 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 206120 kb
Host smart-daa8b25a-c0d9-4f5d-8677-8f9881dbe005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421842941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1421842941
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4184579089
Short name T563
Test name
Test status
Simulation time 30966100 ps
CPU time 0.84 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:52 PM PDT 24
Peak memory 215220 kb
Host smart-9d4c6f0c-ef6b-44a7-b4ee-6f4ac0a0156e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184579089 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4184579089
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2722933521
Short name T417
Test name
Test status
Simulation time 136935238 ps
CPU time 1.22 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 216664 kb
Host smart-be7c0c31-2e40-4e59-a2ba-e6f020eca398
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722933521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2722933521
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3853290971
Short name T806
Test name
Test status
Simulation time 23241895 ps
CPU time 1.07 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:54 PM PDT 24
Peak memory 224024 kb
Host smart-3ec356f5-6ad0-451e-9c17-2e789b8d0e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853290971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3853290971
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.555506840
Short name T310
Test name
Test status
Simulation time 38428565 ps
CPU time 1.33 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 217972 kb
Host smart-a06a3b5a-15ab-46e9-80c1-1a931ef9d0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555506840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.555506840
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3869367078
Short name T174
Test name
Test status
Simulation time 36053523 ps
CPU time 0.89 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 215320 kb
Host smart-d0fe499a-8c6d-4202-85ec-db66bb41eefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869367078 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3869367078
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3453579283
Short name T408
Test name
Test status
Simulation time 16672422 ps
CPU time 0.96 seconds
Started Jun 06 02:39:50 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 215148 kb
Host smart-7e7124a4-fb70-4167-a892-69b86aaf231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453579283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3453579283
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3715345805
Short name T80
Test name
Test status
Simulation time 423577187 ps
CPU time 7.95 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:07 PM PDT 24
Peak memory 216776 kb
Host smart-c5295d4d-e7ad-4b47-aea2-663c2905bcaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715345805 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3715345805
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.873607367
Short name T553
Test name
Test status
Simulation time 122185846155 ps
CPU time 1786.67 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 03:09:39 PM PDT 24
Peak memory 228076 kb
Host smart-9cb8dd11-d091-42e5-8316-717a4fe923a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873607367 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.873607367
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.2684571784
Short name T656
Test name
Test status
Simulation time 91730439 ps
CPU time 1.19 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 206712 kb
Host smart-d5a74bfd-511b-4d95-8f77-71f66e127d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684571784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2684571784
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3563593540
Short name T390
Test name
Test status
Simulation time 229974723 ps
CPU time 1.22 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 216848 kb
Host smart-ad1f161a-455f-4b0f-9c2b-68924d566ac6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563593540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3563593540
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2155074141
Short name T666
Test name
Test status
Simulation time 19572721 ps
CPU time 1.08 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 218384 kb
Host smart-4fdc57d7-3779-415a-8a15-b16681f7bbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155074141 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2155074141
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.855436585
Short name T737
Test name
Test status
Simulation time 42190514 ps
CPU time 1.7 seconds
Started Jun 06 02:39:51 PM PDT 24
Finished Jun 06 02:39:55 PM PDT 24
Peak memory 217996 kb
Host smart-692747c1-a1e3-4878-a072-3bf41a878fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855436585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.855436585
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3846275143
Short name T834
Test name
Test status
Simulation time 27999165 ps
CPU time 1.23 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:06 PM PDT 24
Peak memory 223972 kb
Host smart-dd489b19-1c98-4983-9ffa-95736f8db052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846275143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3846275143
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.341339310
Short name T6
Test name
Test status
Simulation time 16782998 ps
CPU time 0.98 seconds
Started Jun 06 02:39:49 PM PDT 24
Finished Jun 06 02:39:53 PM PDT 24
Peak memory 215228 kb
Host smart-2e548f4b-b6fe-4c70-a238-9af1c7ed3e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341339310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.341339310
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3237037454
Short name T571
Test name
Test status
Simulation time 52446489 ps
CPU time 1.63 seconds
Started Jun 06 02:39:55 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 207008 kb
Host smart-bf8811e8-48fc-49e4-8117-fea35a8ecc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237037454 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3237037454
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3106159152
Short name T65
Test name
Test status
Simulation time 50062742174 ps
CPU time 630.01 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 218020 kb
Host smart-ecfac66b-71eb-46b9-bf50-8ab2d8986a94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106159152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3106159152
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2231264662
Short name T124
Test name
Test status
Simulation time 88252345 ps
CPU time 1.25 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 215560 kb
Host smart-b5058de1-2505-477f-b8f9-6fa4c93884c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231264662 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2231264662
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2326975326
Short name T654
Test name
Test status
Simulation time 28878454 ps
CPU time 0.94 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 214664 kb
Host smart-fa1c1404-495f-42ea-9399-8e54eef7b145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326975326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2326975326
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.296396720
Short name T198
Test name
Test status
Simulation time 39650842 ps
CPU time 0.88 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 215396 kb
Host smart-05a02267-1993-4ec4-9b4a-4aa5bc6efef9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296396720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.296396720
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2757993640
Short name T612
Test name
Test status
Simulation time 43221907 ps
CPU time 1.37 seconds
Started Jun 06 02:40:00 PM PDT 24
Finished Jun 06 02:40:06 PM PDT 24
Peak memory 215468 kb
Host smart-39d19d08-a079-4c70-9c33-42e5f7a65f9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757993640 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2757993640
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.296339920
Short name T509
Test name
Test status
Simulation time 71238301 ps
CPU time 1.23 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 225464 kb
Host smart-b5a47d2d-9911-4a61-9bd4-f27ff894cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296339920 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.296339920
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.688966944
Short name T353
Test name
Test status
Simulation time 150731522 ps
CPU time 1.37 seconds
Started Jun 06 02:39:54 PM PDT 24
Finished Jun 06 02:39:57 PM PDT 24
Peak memory 218312 kb
Host smart-9538279e-fa92-47fb-8694-d854cf47bafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688966944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.688966944
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2712726142
Short name T518
Test name
Test status
Simulation time 26966146 ps
CPU time 0.92 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:02 PM PDT 24
Peak memory 215448 kb
Host smart-fbfdeb60-7916-4396-8f55-44fa53d5a7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712726142 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2712726142
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2232854241
Short name T567
Test name
Test status
Simulation time 15528070 ps
CPU time 1 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 215164 kb
Host smart-b08c5e82-9cb0-4d9d-952d-6ca3fb206e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232854241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2232854241
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.1810807895
Short name T726
Test name
Test status
Simulation time 392987334 ps
CPU time 4.34 seconds
Started Jun 06 02:39:55 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 215196 kb
Host smart-951e04e9-5e81-4708-99a3-7c5fcd2a1c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810807895 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1810807895
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1682743366
Short name T204
Test name
Test status
Simulation time 240588299264 ps
CPU time 1437.29 seconds
Started Jun 06 02:40:00 PM PDT 24
Finished Jun 06 03:04:02 PM PDT 24
Peak memory 223132 kb
Host smart-40b9aca6-2e22-412e-8127-b3f5216b1655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682743366 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1682743366
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1419384176
Short name T161
Test name
Test status
Simulation time 21587280 ps
CPU time 1.14 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 218036 kb
Host smart-560856f7-cce4-4a17-8345-4e0949d0cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419384176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1419384176
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2642354645
Short name T803
Test name
Test status
Simulation time 31241444 ps
CPU time 0.95 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 206388 kb
Host smart-9f2dfa0e-1c34-4782-988f-aa580899b991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642354645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2642354645
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.4287933420
Short name T180
Test name
Test status
Simulation time 12188981 ps
CPU time 1 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 216468 kb
Host smart-4cc44a4d-4185-4b6b-848b-7d2493c860c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287933420 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4287933420
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1287140498
Short name T559
Test name
Test status
Simulation time 74329136 ps
CPU time 1.31 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:01 PM PDT 24
Peak memory 216668 kb
Host smart-6fb0d4ae-6f15-47c6-9b1f-847e6422c5f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287140498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1287140498
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3287422946
Short name T175
Test name
Test status
Simulation time 19304371 ps
CPU time 1.04 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 218280 kb
Host smart-cb2859a5-5998-40c2-9b35-f3fccd2548ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287422946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3287422946
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2643809217
Short name T687
Test name
Test status
Simulation time 109879744 ps
CPU time 1.65 seconds
Started Jun 06 02:39:54 PM PDT 24
Finished Jun 06 02:39:58 PM PDT 24
Peak memory 219172 kb
Host smart-820bf698-014c-4db2-9485-2cb748d49ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643809217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2643809217
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.715370559
Short name T384
Test name
Test status
Simulation time 43352819 ps
CPU time 0.96 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:05 PM PDT 24
Peak memory 223788 kb
Host smart-37da8d8b-2603-4bbc-a621-6e2a6234c50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715370559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.715370559
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2719309708
Short name T570
Test name
Test status
Simulation time 17843281 ps
CPU time 1 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 215224 kb
Host smart-07e0fa03-27a3-4279-bfa2-61939de277e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719309708 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2719309708
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2275818885
Short name T459
Test name
Test status
Simulation time 20392282 ps
CPU time 1.02 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 206212 kb
Host smart-0584dd29-1395-446d-8fd4-e7b191316171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275818885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2275818885
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1796994604
Short name T81
Test name
Test status
Simulation time 489930566164 ps
CPU time 632.6 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:50:31 PM PDT 24
Peak memory 223624 kb
Host smart-7896c73c-c283-472a-a4f3-f6a93d91cd6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796994604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1796994604
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.3422148509
Short name T712
Test name
Test status
Simulation time 23935983 ps
CPU time 0.97 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 206500 kb
Host smart-cc74b995-02fc-4883-af24-da9cb4f2348c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422148509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3422148509
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_err.3896306161
Short name T55
Test name
Test status
Simulation time 29099644 ps
CPU time 1.08 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:05 PM PDT 24
Peak memory 223772 kb
Host smart-c959f0e1-0788-4273-bc4a-f4fa7b10039c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896306161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3896306161
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2423609673
Short name T482
Test name
Test status
Simulation time 59421296 ps
CPU time 1.21 seconds
Started Jun 06 02:39:56 PM PDT 24
Finished Jun 06 02:40:00 PM PDT 24
Peak memory 218484 kb
Host smart-8fdd14b9-07fb-45a4-9c05-26579454d645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423609673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2423609673
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3348903044
Short name T683
Test name
Test status
Simulation time 22505959 ps
CPU time 1.17 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 224056 kb
Host smart-23f6b2dd-7561-4e64-b77a-de7a4c8d2cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348903044 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3348903044
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.4023024735
Short name T309
Test name
Test status
Simulation time 20300113 ps
CPU time 1.03 seconds
Started Jun 06 02:39:55 PM PDT 24
Finished Jun 06 02:39:58 PM PDT 24
Peak memory 215236 kb
Host smart-d2c3ce64-b082-4707-acdf-6271c1cb7cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023024735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4023024735
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2116121964
Short name T215
Test name
Test status
Simulation time 1428409941 ps
CPU time 2.41 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 215128 kb
Host smart-9f234ab6-606c-4de8-9ea7-c4af0342e5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116121964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2116121964
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3710527752
Short name T782
Test name
Test status
Simulation time 51607643391 ps
CPU time 1305.93 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 03:01:51 PM PDT 24
Peak memory 223080 kb
Host smart-c28f49a8-40bd-4bb6-a02f-db7b45be8c63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710527752 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3710527752
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.168116337
Short name T145
Test name
Test status
Simulation time 92385157 ps
CPU time 1.2 seconds
Started Jun 06 02:39:55 PM PDT 24
Finished Jun 06 02:39:59 PM PDT 24
Peak memory 219580 kb
Host smart-6732b7be-6fc7-48af-8ab6-bbd899188772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168116337 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.168116337
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2179095779
Short name T489
Test name
Test status
Simulation time 35348538 ps
CPU time 0.8 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 206096 kb
Host smart-14946af1-017c-441c-b369-84e3a1160d24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179095779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2179095779
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.194194103
Short name T771
Test name
Test status
Simulation time 82517460 ps
CPU time 0.94 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 216240 kb
Host smart-794627ee-dfe4-4315-9851-8ad0d5f29783
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194194103 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.194194103
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2707744728
Short name T127
Test name
Test status
Simulation time 57334999 ps
CPU time 1.08 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 216812 kb
Host smart-aa8afb29-3723-44ab-a4a9-ac7ab55bcaae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707744728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2707744728
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.625640264
Short name T639
Test name
Test status
Simulation time 34637494 ps
CPU time 1.06 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 217376 kb
Host smart-64470ad2-75f0-496a-92ed-4ec50f38feb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625640264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.625640264
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.805178362
Short name T74
Test name
Test status
Simulation time 35333365 ps
CPU time 1.34 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:03 PM PDT 24
Peak memory 216892 kb
Host smart-9b2c4df1-df59-4cc3-a2a6-9c472d069f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805178362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.805178362
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.128533564
Short name T401
Test name
Test status
Simulation time 84330337 ps
CPU time 0.87 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 215244 kb
Host smart-3edd5d84-6d92-48f8-ba3f-b955d94d496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128533564 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.128533564
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.667396350
Short name T217
Test name
Test status
Simulation time 16499665 ps
CPU time 1 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 215212 kb
Host smart-93f34476-61e3-4809-9b13-65fa7ffc825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667396350 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.667396350
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.4063100427
Short name T582
Test name
Test status
Simulation time 870817491 ps
CPU time 4.26 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:07 PM PDT 24
Peak memory 217068 kb
Host smart-fd349ef0-b3f7-4dab-96ea-3af9c7d7e922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063100427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.4063100427
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.178277707
Short name T491
Test name
Test status
Simulation time 290800886227 ps
CPU time 716.06 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:52:00 PM PDT 24
Peak memory 220804 kb
Host smart-24a23d55-4f43-4c34-9e86-3e6ead9dfd78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178277707 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.178277707
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1352228783
Short name T303
Test name
Test status
Simulation time 42863871 ps
CPU time 1.13 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 220508 kb
Host smart-165795ae-81ef-44ce-947b-d35c4763e5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352228783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1352228783
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3055418581
Short name T2
Test name
Test status
Simulation time 16616632 ps
CPU time 0.99 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 214668 kb
Host smart-f0c56a35-40f2-4f48-8039-3a3527875bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055418581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3055418581
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1464780539
Short name T196
Test name
Test status
Simulation time 30579914 ps
CPU time 0.84 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 215280 kb
Host smart-64291b84-2e52-494d-8aae-9e93ed44367d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464780539 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1464780539
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2884267993
Short name T769
Test name
Test status
Simulation time 45477408 ps
CPU time 1.41 seconds
Started Jun 06 02:40:06 PM PDT 24
Finished Jun 06 02:40:10 PM PDT 24
Peak memory 216700 kb
Host smart-68318f72-5a2a-476c-80f6-bb0637437235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884267993 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2884267993
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.177631675
Short name T184
Test name
Test status
Simulation time 41944019 ps
CPU time 1.14 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:13 PM PDT 24
Peak memory 219560 kb
Host smart-2867272a-916b-4439-b8c7-fb9d547e8a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177631675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.177631675
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3295232740
Short name T510
Test name
Test status
Simulation time 76512881 ps
CPU time 1.47 seconds
Started Jun 06 02:39:58 PM PDT 24
Finished Jun 06 02:40:04 PM PDT 24
Peak memory 218264 kb
Host smart-79e53291-57cd-40b7-a454-7b59d11ff11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295232740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3295232740
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3202137381
Short name T624
Test name
Test status
Simulation time 31566365 ps
CPU time 0.96 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 215456 kb
Host smart-b815d76a-3ba6-4efa-8e60-055193a6226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202137381 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3202137381
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1566514285
Short name T651
Test name
Test status
Simulation time 22557880 ps
CPU time 1.01 seconds
Started Jun 06 02:39:57 PM PDT 24
Finished Jun 06 02:40:02 PM PDT 24
Peak memory 215164 kb
Host smart-e626f139-1ff1-4057-b1ca-96fcc41249f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566514285 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1566514285
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3077923846
Short name T289
Test name
Test status
Simulation time 196287598 ps
CPU time 3.93 seconds
Started Jun 06 02:39:59 PM PDT 24
Finished Jun 06 02:40:08 PM PDT 24
Peak memory 216660 kb
Host smart-20e8c9b3-a38c-45a7-aa03-b730dec4f560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077923846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3077923846
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2997991339
Short name T355
Test name
Test status
Simulation time 74115668280 ps
CPU time 518.44 seconds
Started Jun 06 02:40:05 PM PDT 24
Finished Jun 06 02:48:46 PM PDT 24
Peak memory 218656 kb
Host smart-2c0ef32e-af5e-4605-9a70-db8527e61e4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997991339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2997991339
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1361838290
Short name T253
Test name
Test status
Simulation time 48084947 ps
CPU time 1.24 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:18 PM PDT 24
Peak memory 219484 kb
Host smart-47c27f4f-960b-4593-8ccd-c00009d34ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361838290 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1361838290
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1690589150
Short name T497
Test name
Test status
Simulation time 14935732 ps
CPU time 0.88 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 206408 kb
Host smart-d9995896-342f-4ebc-a78b-3553fe11e351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690589150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1690589150
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2807124827
Short name T744
Test name
Test status
Simulation time 12452149 ps
CPU time 0.88 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 215520 kb
Host smart-b589724f-5a39-43c5-a1ff-33bad14e78aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807124827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2807124827
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2763175406
Short name T414
Test name
Test status
Simulation time 44379225 ps
CPU time 1.06 seconds
Started Jun 06 02:40:06 PM PDT 24
Finished Jun 06 02:40:10 PM PDT 24
Peak memory 216828 kb
Host smart-e83f3174-d787-4738-809b-dd555626de20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763175406 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2763175406
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.2474437267
Short name T599
Test name
Test status
Simulation time 22218249 ps
CPU time 1.02 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 219448 kb
Host smart-17b1c9b8-0e80-42ea-adcb-8c89b5db7e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474437267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2474437267
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.81264741
Short name T360
Test name
Test status
Simulation time 46246313 ps
CPU time 1.64 seconds
Started Jun 06 02:40:06 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 216940 kb
Host smart-55560819-2654-4ef2-8601-5646ef64c267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81264741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.81264741
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3509624461
Short name T566
Test name
Test status
Simulation time 33234823 ps
CPU time 0.97 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 223944 kb
Host smart-d03ea306-e98b-44b0-bc53-b2f4b08674e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509624461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3509624461
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.230017279
Short name T391
Test name
Test status
Simulation time 34535728 ps
CPU time 0.9 seconds
Started Jun 06 02:40:05 PM PDT 24
Finished Jun 06 02:40:09 PM PDT 24
Peak memory 215440 kb
Host smart-debe8b2e-ac9f-40c5-956c-e47fe4b380c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230017279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.230017279
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3457261179
Short name T4
Test name
Test status
Simulation time 107427501 ps
CPU time 1.69 seconds
Started Jun 06 02:40:05 PM PDT 24
Finished Jun 06 02:40:09 PM PDT 24
Peak memory 217916 kb
Host smart-7c7e8ac9-7292-4a1d-b7b5-fa9663d79d1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457261179 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3457261179
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2155908688
Short name T290
Test name
Test status
Simulation time 15187165828 ps
CPU time 415.28 seconds
Started Jun 06 02:40:06 PM PDT 24
Finished Jun 06 02:47:05 PM PDT 24
Peak memory 217592 kb
Host smart-b81892ff-10fd-477d-80b1-284e6cf62670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155908688 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2155908688
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.2303657894
Short name T723
Test name
Test status
Simulation time 87843764 ps
CPU time 0.86 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:13 PM PDT 24
Peak memory 206160 kb
Host smart-4aa6f131-ac4f-43c6-a702-6ff6563250ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303657894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2303657894
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3649618322
Short name T197
Test name
Test status
Simulation time 19257925 ps
CPU time 0.9 seconds
Started Jun 06 02:40:13 PM PDT 24
Finished Jun 06 02:40:18 PM PDT 24
Peak memory 215504 kb
Host smart-cef41acb-7920-41f5-8a9f-ae382a10ea22
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649618322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3649618322
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1448206057
Short name T642
Test name
Test status
Simulation time 27668479 ps
CPU time 1.09 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:13 PM PDT 24
Peak memory 219376 kb
Host smart-2c8abd22-bae7-4e2f-912c-9ec2e409ed32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448206057 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1448206057
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3494555252
Short name T816
Test name
Test status
Simulation time 23916493 ps
CPU time 0.95 seconds
Started Jun 06 02:40:14 PM PDT 24
Finished Jun 06 02:40:18 PM PDT 24
Peak memory 218648 kb
Host smart-ae9d32e1-bee2-4d19-a8b3-f9a8c3ffe172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494555252 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3494555252
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.181885935
Short name T686
Test name
Test status
Simulation time 45602274 ps
CPU time 1.18 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 217036 kb
Host smart-a904921e-3b1a-4e62-b662-d7f6fd269951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181885935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.181885935
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3008313884
Short name T39
Test name
Test status
Simulation time 35220628 ps
CPU time 0.87 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:13 PM PDT 24
Peak memory 215584 kb
Host smart-74a6d325-a936-44f0-971d-197a7c82ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008313884 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3008313884
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3772101855
Short name T383
Test name
Test status
Simulation time 103567968 ps
CPU time 0.88 seconds
Started Jun 06 02:40:04 PM PDT 24
Finished Jun 06 02:40:08 PM PDT 24
Peak memory 215184 kb
Host smart-d752ea72-114a-45e1-a8e3-235bde2d0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772101855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3772101855
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4187852679
Short name T754
Test name
Test status
Simulation time 104432153 ps
CPU time 1.19 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 216840 kb
Host smart-8925e105-4e39-4b71-ab5a-4e492a76cad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187852679 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4187852679
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.17382367
Short name T42
Test name
Test status
Simulation time 39314575800 ps
CPU time 504.74 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:48:38 PM PDT 24
Peak memory 223644 kb
Host smart-e61ab18a-ae3b-4da1-a18f-13f921cbeb68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17382367 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.17382367
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.543113330
Short name T648
Test name
Test status
Simulation time 26345649 ps
CPU time 0.9 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 206460 kb
Host smart-e7b06906-6528-4867-8530-c4981fe7c5a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543113330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.543113330
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3738466953
Short name T138
Test name
Test status
Simulation time 10588186 ps
CPU time 0.84 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 215300 kb
Host smart-60453180-7556-4efd-a55c-98d1b69f135e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738466953 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3738466953
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1888200369
Short name T128
Test name
Test status
Simulation time 63715558 ps
CPU time 1.12 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 216660 kb
Host smart-4508b051-1aa5-4fb5-b87b-6d45347ae995
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888200369 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1888200369
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3051018234
Short name T141
Test name
Test status
Simulation time 35299497 ps
CPU time 0.91 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 218416 kb
Host smart-0c9bc2a5-ea4d-4edd-a91b-17783fd0791c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051018234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3051018234
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3600895983
Short name T346
Test name
Test status
Simulation time 32864581 ps
CPU time 1.01 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 216920 kb
Host smart-18eb1e93-c8f0-48aa-b8e2-159dcee730ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600895983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3600895983
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1630424646
Short name T721
Test name
Test status
Simulation time 26090274 ps
CPU time 0.95 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 215452 kb
Host smart-2f88fe61-e3f2-4fd5-8ccf-baf029963c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630424646 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1630424646
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.4128782058
Short name T364
Test name
Test status
Simulation time 18552393 ps
CPU time 1.06 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 207036 kb
Host smart-a7eadf33-9e0a-433f-9ce9-1eda12d432f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128782058 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4128782058
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2819773010
Short name T524
Test name
Test status
Simulation time 587983986 ps
CPU time 3.9 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 215228 kb
Host smart-ac699878-1be4-4230-80d0-2415e9241754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819773010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2819773010
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1448910353
Short name T203
Test name
Test status
Simulation time 213536649437 ps
CPU time 929.91 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:55:42 PM PDT 24
Peak memory 220884 kb
Host smart-e0e7e2a1-e5a8-472d-92d2-16deee1a32a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448910353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1448910353
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.931331674
Short name T667
Test name
Test status
Simulation time 212726608 ps
CPU time 1.05 seconds
Started Jun 06 02:38:45 PM PDT 24
Finished Jun 06 02:38:47 PM PDT 24
Peak memory 219188 kb
Host smart-b13b3ed9-8c7f-4890-84b7-9ada28536fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931331674 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.931331674
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3462730394
Short name T251
Test name
Test status
Simulation time 41875764 ps
CPU time 0.84 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 214492 kb
Host smart-4ccc3328-260b-44ea-b9c6-5424f5d448d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462730394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3462730394
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1633434882
Short name T440
Test name
Test status
Simulation time 63202324 ps
CPU time 1.01 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 217952 kb
Host smart-753f01e8-2139-47d5-83de-218d1d96172d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633434882 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1633434882
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.588884616
Short name T110
Test name
Test status
Simulation time 20568002 ps
CPU time 1.23 seconds
Started Jun 06 02:38:52 PM PDT 24
Finished Jun 06 02:38:55 PM PDT 24
Peak memory 219580 kb
Host smart-819bf06a-3063-4899-9f0f-8102552ce453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588884616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.588884616
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.273110053
Short name T274
Test name
Test status
Simulation time 65463986 ps
CPU time 1.12 seconds
Started Jun 06 02:38:50 PM PDT 24
Finished Jun 06 02:38:53 PM PDT 24
Peak memory 216904 kb
Host smart-816a59de-92de-4a7d-a17c-036b196968cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273110053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.273110053
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.851660937
Short name T714
Test name
Test status
Simulation time 21344212 ps
CPU time 1 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 215836 kb
Host smart-b0f87b3f-d2e2-4028-9d13-a0b26b5c2629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851660937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.851660937
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1558039876
Short name T693
Test name
Test status
Simulation time 123182101 ps
CPU time 0.89 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:49 PM PDT 24
Peak memory 206972 kb
Host smart-6142a5ca-fd47-4c58-86bc-081b12f6436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558039876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1558039876
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3600736037
Short name T735
Test name
Test status
Simulation time 26207374 ps
CPU time 0.94 seconds
Started Jun 06 02:38:48 PM PDT 24
Finished Jun 06 02:38:50 PM PDT 24
Peak memory 215284 kb
Host smart-7cdd65ab-f8ad-49f4-b0dd-8a1e6dde7646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600736037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3600736037
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2483121475
Short name T690
Test name
Test status
Simulation time 79823344 ps
CPU time 1.14 seconds
Started Jun 06 02:38:50 PM PDT 24
Finished Jun 06 02:38:53 PM PDT 24
Peak memory 217188 kb
Host smart-9171054d-713d-46c1-a6bc-ebabc2f9ebe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483121475 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2483121475
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.529849801
Short name T543
Test name
Test status
Simulation time 85053511731 ps
CPU time 1915.51 seconds
Started Jun 06 02:38:44 PM PDT 24
Finished Jun 06 03:10:42 PM PDT 24
Peak memory 226192 kb
Host smart-a2617bd6-191d-455d-a9cf-52f045c8cf13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529849801 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.529849801
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2320378407
Short name T183
Test name
Test status
Simulation time 19064035 ps
CPU time 1.11 seconds
Started Jun 06 02:40:10 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 223968 kb
Host smart-3d46e777-47dd-4d9a-a5ef-0cf664d56c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320378407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2320378407
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3869993479
Short name T286
Test name
Test status
Simulation time 157075861 ps
CPU time 2.47 seconds
Started Jun 06 02:40:10 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 219824 kb
Host smart-3e6ee224-2c84-4b47-b9a0-c94a7e13c2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869993479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3869993479
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1488093632
Short name T57
Test name
Test status
Simulation time 36414378 ps
CPU time 1.22 seconds
Started Jun 06 02:40:11 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 225564 kb
Host smart-96917baf-6fef-49cb-8610-b50c6a729cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488093632 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1488093632
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1303084637
Short name T530
Test name
Test status
Simulation time 24717031 ps
CPU time 1.5 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 216948 kb
Host smart-c98d22b4-9b3e-468b-86fd-f6f3b5f01d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303084637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1303084637
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2971924841
Short name T523
Test name
Test status
Simulation time 20459273 ps
CPU time 0.94 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 218216 kb
Host smart-e6d2cfc4-e52d-4bb5-93c9-6b302cf117ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971924841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2971924841
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1987035831
Short name T260
Test name
Test status
Simulation time 27967816 ps
CPU time 1.15 seconds
Started Jun 06 02:40:07 PM PDT 24
Finished Jun 06 02:40:12 PM PDT 24
Peak memory 218028 kb
Host smart-a91b9938-b8dc-49d7-92eb-36d6b0637704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987035831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1987035831
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1273191059
Short name T140
Test name
Test status
Simulation time 24014834 ps
CPU time 0.94 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 218292 kb
Host smart-7b74f810-7ae0-4974-ad53-bcd084bbd1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273191059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1273191059
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1060326494
Short name T394
Test name
Test status
Simulation time 54742720 ps
CPU time 1.37 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 216816 kb
Host smart-c03940d0-f7fe-4b25-a9ff-961c6131d506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060326494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1060326494
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.4111612662
Short name T148
Test name
Test status
Simulation time 26895928 ps
CPU time 1.06 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 224008 kb
Host smart-e87892f6-fa90-4886-bcab-cf652a9e1b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111612662 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.4111612662
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1500410090
Short name T484
Test name
Test status
Simulation time 35609370 ps
CPU time 1.33 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 218244 kb
Host smart-83e19815-eb93-4f30-8e28-051f0a749e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500410090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1500410090
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2905148080
Short name T155
Test name
Test status
Simulation time 19768178 ps
CPU time 1.18 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 224032 kb
Host smart-c961b38f-d141-4e1b-b3f7-01d21ebbf3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905148080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2905148080
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3809397925
Short name T767
Test name
Test status
Simulation time 99915325 ps
CPU time 1.36 seconds
Started Jun 06 02:40:12 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 218400 kb
Host smart-87a21b86-1873-4173-9a16-8d6ba2f2a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809397925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3809397925
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3882931487
Short name T105
Test name
Test status
Simulation time 35944897 ps
CPU time 1.11 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:13 PM PDT 24
Peak memory 219660 kb
Host smart-1e6c7a72-2825-42f6-959e-0072918208ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882931487 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3882931487
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1649869547
Short name T369
Test name
Test status
Simulation time 42189034 ps
CPU time 1.14 seconds
Started Jun 06 02:40:11 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 217104 kb
Host smart-dabc7f27-74b7-4975-83ec-c9d7dae95814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649869547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1649869547
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.4154074746
Short name T800
Test name
Test status
Simulation time 19629054 ps
CPU time 1.23 seconds
Started Jun 06 02:40:11 PM PDT 24
Finished Jun 06 02:40:17 PM PDT 24
Peak memory 224020 kb
Host smart-95049b80-26cf-4180-a7a9-f5fed11f0c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154074746 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.4154074746
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1588550547
Short name T630
Test name
Test status
Simulation time 80238493 ps
CPU time 1.57 seconds
Started Jun 06 02:40:08 PM PDT 24
Finished Jun 06 02:40:14 PM PDT 24
Peak memory 218456 kb
Host smart-9739614f-5927-474f-b511-d14736640a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588550547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1588550547
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1337944536
Short name T467
Test name
Test status
Simulation time 18130347 ps
CPU time 1.08 seconds
Started Jun 06 02:40:10 PM PDT 24
Finished Jun 06 02:40:16 PM PDT 24
Peak memory 218440 kb
Host smart-3ca3d8a0-52a3-403b-ac56-3bf56257f676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337944536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1337944536
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1995143046
Short name T740
Test name
Test status
Simulation time 118383657 ps
CPU time 1.61 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218812 kb
Host smart-267cc8db-a783-4dd8-944a-318fbe51d297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995143046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1995143046
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_genbits.1389655433
Short name T292
Test name
Test status
Simulation time 27629144 ps
CPU time 1.26 seconds
Started Jun 06 02:40:09 PM PDT 24
Finished Jun 06 02:40:15 PM PDT 24
Peak memory 218188 kb
Host smart-d065b6dd-9786-4a50-9c9e-7b8edcf97cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389655433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1389655433
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3628548271
Short name T622
Test name
Test status
Simulation time 28717171 ps
CPU time 1.27 seconds
Started Jun 06 02:38:45 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 219412 kb
Host smart-32321b4c-14b8-4652-b97d-bd5da30e31fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628548271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3628548271
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3474122496
Short name T590
Test name
Test status
Simulation time 153327152 ps
CPU time 1.95 seconds
Started Jun 06 02:38:48 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 206648 kb
Host smart-35b678bd-d370-4474-979a-86171e0172dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474122496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3474122496
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1134882556
Short name T623
Test name
Test status
Simulation time 21688157 ps
CPU time 0.85 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 216284 kb
Host smart-62fcd43e-2246-4f1c-96d2-cd6368339bf0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134882556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1134882556
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.433033020
Short name T777
Test name
Test status
Simulation time 115663104 ps
CPU time 1.22 seconds
Started Jun 06 02:38:52 PM PDT 24
Finished Jun 06 02:38:55 PM PDT 24
Peak memory 218244 kb
Host smart-df138d60-6686-446e-8e4a-1a271701f7b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433033020 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.433033020
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3225020081
Short name T339
Test name
Test status
Simulation time 28918960 ps
CPU time 0.83 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 218360 kb
Host smart-eb4cfc2b-3369-48d7-9e72-a92da75dd340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225020081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3225020081
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.2920265623
Short name T413
Test name
Test status
Simulation time 31470578 ps
CPU time 1.29 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:49 PM PDT 24
Peak memory 218160 kb
Host smart-b61b3ab7-bbd8-4166-80fe-929fd16459a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920265623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2920265623
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.394683660
Short name T368
Test name
Test status
Simulation time 25577107 ps
CPU time 1.05 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 223968 kb
Host smart-c70eb8c1-b123-4feb-8196-10b07680057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394683660 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.394683660
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.615749520
Short name T301
Test name
Test status
Simulation time 26121357 ps
CPU time 0.93 seconds
Started Jun 06 02:38:47 PM PDT 24
Finished Jun 06 02:38:49 PM PDT 24
Peak memory 207008 kb
Host smart-b7b385bc-5d84-46f6-aa12-93281e60b8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615749520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.615749520
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1348849810
Short name T698
Test name
Test status
Simulation time 148353378 ps
CPU time 0.97 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:49 PM PDT 24
Peak memory 215212 kb
Host smart-38b918b6-e1b2-4039-afbf-af89d92410b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348849810 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1348849810
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3628313463
Short name T426
Test name
Test status
Simulation time 416680032 ps
CPU time 3.04 seconds
Started Jun 06 02:38:48 PM PDT 24
Finished Jun 06 02:38:52 PM PDT 24
Peak memory 215160 kb
Host smart-43d6d11f-6378-4fc1-89df-8c8decae59d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628313463 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3628313463
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.231412197
Short name T496
Test name
Test status
Simulation time 130151586024 ps
CPU time 1477.49 seconds
Started Jun 06 02:38:49 PM PDT 24
Finished Jun 06 03:03:29 PM PDT 24
Peak memory 224296 kb
Host smart-290fae6b-781a-4fba-8df5-dac84ee6c539
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231412197 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.231412197
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2417463195
Short name T111
Test name
Test status
Simulation time 34001901 ps
CPU time 1.06 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 219524 kb
Host smart-8dc7cffb-59ae-4a47-bb40-87a64ac0b13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417463195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2417463195
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2229586151
Short name T561
Test name
Test status
Simulation time 199491352 ps
CPU time 1.03 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 217068 kb
Host smart-0d6e6d0f-a807-4a63-9b73-bc65119075fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229586151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2229586151
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.769134702
Short name T717
Test name
Test status
Simulation time 82970440 ps
CPU time 1 seconds
Started Jun 06 02:40:29 PM PDT 24
Finished Jun 06 02:40:33 PM PDT 24
Peak memory 218440 kb
Host smart-5edcfe56-b756-4c74-8ab2-9727b7847bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769134702 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.769134702
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1210697633
Short name T825
Test name
Test status
Simulation time 151619820 ps
CPU time 2.51 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 220036 kb
Host smart-6d0030de-a9ee-42a3-b175-bb2af8c5596d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210697633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1210697633
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1152277204
Short name T704
Test name
Test status
Simulation time 20397818 ps
CPU time 0.99 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218408 kb
Host smart-3f3649f9-221b-4a2f-aed0-b638a6bd7cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152277204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1152277204
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.681261384
Short name T493
Test name
Test status
Simulation time 75477165 ps
CPU time 1.61 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218364 kb
Host smart-c2ce00c1-f5ce-4eb3-bd03-de5c8724e7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681261384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.681261384
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_genbits.3021735568
Short name T817
Test name
Test status
Simulation time 86930885 ps
CPU time 1.33 seconds
Started Jun 06 02:40:19 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 218544 kb
Host smart-31dd2488-c1ac-4ef5-8153-12d409ea707e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021735568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3021735568
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4073659670
Short name T375
Test name
Test status
Simulation time 22375264 ps
CPU time 1 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 219528 kb
Host smart-fe902715-f6c4-4298-bfab-2bb253f27310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073659670 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4073659670
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.2350719884
Short name T592
Test name
Test status
Simulation time 20058900 ps
CPU time 1.07 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 218500 kb
Host smart-6d8af5e4-de88-45f5-a823-f2fbe9bcf969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350719884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2350719884
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2053981519
Short name T433
Test name
Test status
Simulation time 53237250 ps
CPU time 1.41 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218340 kb
Host smart-3127bcea-f912-4cbd-8b89-64c0f9a8ddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053981519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2053981519
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3435974230
Short name T454
Test name
Test status
Simulation time 77017320 ps
CPU time 1.09 seconds
Started Jun 06 02:40:15 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 219732 kb
Host smart-bc57d4fd-56b0-46e8-ade4-fbddbc2bf35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435974230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3435974230
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1585192507
Short name T727
Test name
Test status
Simulation time 39970635 ps
CPU time 1.36 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 217972 kb
Host smart-edb82e98-abe4-4e14-b902-2db057ba42bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585192507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1585192507
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2502202223
Short name T644
Test name
Test status
Simulation time 33634548 ps
CPU time 0.91 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 218264 kb
Host smart-7530b0d4-8288-41a3-acc8-a3570e3eebc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502202223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2502202223
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1392596250
Short name T69
Test name
Test status
Simulation time 49083772 ps
CPU time 1.73 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 218160 kb
Host smart-cf92c5b1-ed51-4b72-ab89-acddff27a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392596250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1392596250
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3647455200
Short name T121
Test name
Test status
Simulation time 33319538 ps
CPU time 1.53 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 225728 kb
Host smart-e3cef303-5694-4056-a97b-622f8c2cf094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647455200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3647455200
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1096064187
Short name T670
Test name
Test status
Simulation time 39474151 ps
CPU time 1.43 seconds
Started Jun 06 02:40:19 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 218128 kb
Host smart-6ee3b149-c0a0-4ccf-bd09-d2f56f9f4035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096064187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1096064187
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.59329042
Short name T805
Test name
Test status
Simulation time 21522263 ps
CPU time 0.93 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218184 kb
Host smart-1443a5fe-8aee-419d-8be1-60efb9258d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59329042 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.59329042
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.872420393
Short name T314
Test name
Test status
Simulation time 133118084 ps
CPU time 2.58 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 219700 kb
Host smart-cadead41-1b87-4547-95b3-52b1bf527928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872420393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.872420393
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.2402077790
Short name T363
Test name
Test status
Simulation time 92654469 ps
CPU time 0.81 seconds
Started Jun 06 02:39:00 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 206632 kb
Host smart-1befb8d0-031f-4964-81e2-882904169379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402077790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2402077790
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3949872012
Short name T438
Test name
Test status
Simulation time 27829495 ps
CPU time 0.8 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:38:57 PM PDT 24
Peak memory 215796 kb
Host smart-047bb13e-e8e1-4e60-a361-1cdb79328b2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949872012 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3949872012
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4102947988
Short name T100
Test name
Test status
Simulation time 82645309 ps
CPU time 1.25 seconds
Started Jun 06 02:38:58 PM PDT 24
Finished Jun 06 02:39:02 PM PDT 24
Peak memory 216828 kb
Host smart-61c5b3d5-cc83-42ad-aa3a-6b6e975aa79f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102947988 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4102947988
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.2629580072
Short name T113
Test name
Test status
Simulation time 68325384 ps
CPU time 1.12 seconds
Started Jun 06 02:39:01 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 229580 kb
Host smart-5bfb3294-3c50-41c2-b6d8-040c9c33a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629580072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.2629580072
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2828882664
Short name T548
Test name
Test status
Simulation time 43888788 ps
CPU time 1.19 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:48 PM PDT 24
Peak memory 219208 kb
Host smart-34c921a6-7120-4b54-b94c-3a67a4346654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828882664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2828882664
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2348116551
Short name T92
Test name
Test status
Simulation time 24892511 ps
CPU time 0.87 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:38:57 PM PDT 24
Peak memory 215860 kb
Host smart-2e3d8fa4-2170-4b9d-b292-04c20864ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348116551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2348116551
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1076023147
Short name T30
Test name
Test status
Simulation time 48456606 ps
CPU time 0.93 seconds
Started Jun 06 02:38:45 PM PDT 24
Finished Jun 06 02:38:47 PM PDT 24
Peak memory 207044 kb
Host smart-b804c898-5dbb-479b-91e8-81fb3a7b6fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076023147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1076023147
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3302548781
Short name T675
Test name
Test status
Simulation time 67879458 ps
CPU time 0.91 seconds
Started Jun 06 02:38:46 PM PDT 24
Finished Jun 06 02:38:49 PM PDT 24
Peak memory 215192 kb
Host smart-6738ec43-90db-4af8-86f8-f6acef2d49f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302548781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3302548781
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.3032358982
Short name T350
Test name
Test status
Simulation time 845525027 ps
CPU time 5.24 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:04 PM PDT 24
Peak memory 216984 kb
Host smart-7f5e0b4f-f800-4cd4-b011-4a76d43a9a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032358982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3032358982
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1688653590
Short name T688
Test name
Test status
Simulation time 19730421855 ps
CPU time 444.77 seconds
Started Jun 06 02:38:59 PM PDT 24
Finished Jun 06 02:46:26 PM PDT 24
Peak memory 217828 kb
Host smart-2b437b20-884b-45ba-a5b5-3a3948ed9cb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688653590 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1688653590
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3244379174
Short name T811
Test name
Test status
Simulation time 29457127 ps
CPU time 1.24 seconds
Started Jun 06 02:40:28 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 229700 kb
Host smart-1ed516b8-396e-4630-97cf-8f3c48f61fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244379174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3244379174
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1779928946
Short name T362
Test name
Test status
Simulation time 41545725 ps
CPU time 1.44 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218108 kb
Host smart-5c157446-f3fc-4ae5-a8ff-3af847b65dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779928946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1779928946
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2511461248
Short name T601
Test name
Test status
Simulation time 20991524 ps
CPU time 1.24 seconds
Started Jun 06 02:40:28 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 229636 kb
Host smart-80535ace-e24d-4343-9aba-c6887ef704e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511461248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2511461248
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2988292893
Short name T352
Test name
Test status
Simulation time 42136167 ps
CPU time 1.22 seconds
Started Jun 06 02:40:15 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 218084 kb
Host smart-62237979-2ecf-4bf8-beaa-d79250ffea5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988292893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2988292893
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1465586190
Short name T598
Test name
Test status
Simulation time 28433579 ps
CPU time 1.29 seconds
Started Jun 06 02:40:15 PM PDT 24
Finished Jun 06 02:40:20 PM PDT 24
Peak memory 225612 kb
Host smart-67ebbdf1-daa1-45e9-93c8-ef4d5e8b9278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465586190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1465586190
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2262813045
Short name T794
Test name
Test status
Simulation time 54896185 ps
CPU time 1.26 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 218220 kb
Host smart-daa36ef6-5fe7-4aa6-b37d-393d7b716644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262813045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2262813045
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.935105841
Short name T738
Test name
Test status
Simulation time 25466088 ps
CPU time 0.98 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218456 kb
Host smart-52bd635b-00f8-40c9-b1a2-f26979b45ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935105841 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.935105841
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1898627428
Short name T249
Test name
Test status
Simulation time 54980330 ps
CPU time 1.09 seconds
Started Jun 06 02:40:19 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 216976 kb
Host smart-345d7ee1-d916-4d0f-9fde-5e8e95c6e853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898627428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1898627428
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1700589768
Short name T576
Test name
Test status
Simulation time 29878315 ps
CPU time 0.86 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 219336 kb
Host smart-5a4fdc82-860e-43b0-aee2-2b9ab1e640d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700589768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1700589768
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2120426705
Short name T47
Test name
Test status
Simulation time 117440960 ps
CPU time 1.29 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 219256 kb
Host smart-5c8103a3-6eca-4810-bb90-addd238c92db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120426705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2120426705
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.4174270523
Short name T645
Test name
Test status
Simulation time 19358331 ps
CPU time 1.05 seconds
Started Jun 06 02:40:15 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 218560 kb
Host smart-dce8497e-2196-4e5f-aa41-ff0ba03f24e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174270523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.4174270523
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.129258862
Short name T72
Test name
Test status
Simulation time 64258474 ps
CPU time 1.28 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 216900 kb
Host smart-0e3c2f63-3316-46d4-8169-b10fe268f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129258862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.129258862
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.838585302
Short name T36
Test name
Test status
Simulation time 21578536 ps
CPU time 0.92 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 218376 kb
Host smart-6aebdccd-f5a3-4d3f-8238-57010b072d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838585302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.838585302
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2770493766
Short name T755
Test name
Test status
Simulation time 117619234 ps
CPU time 1.36 seconds
Started Jun 06 02:40:14 PM PDT 24
Finished Jun 06 02:40:19 PM PDT 24
Peak memory 218276 kb
Host smart-2848c0aa-728b-4e55-8acb-20abfa44cf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770493766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2770493766
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1090348591
Short name T348
Test name
Test status
Simulation time 44129786 ps
CPU time 1.13 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 219668 kb
Host smart-c6e30dc6-7c06-4538-97a6-a275d6d138fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090348591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1090348591
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.2506230468
Short name T221
Test name
Test status
Simulation time 18128521 ps
CPU time 1.01 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 218296 kb
Host smart-73ad0012-0833-4184-b734-ee4e43a3d07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506230468 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2506230468
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3879485471
Short name T575
Test name
Test status
Simulation time 71005627 ps
CPU time 1.21 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 217160 kb
Host smart-b79251be-733f-4bc5-85ae-3c7929566f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879485471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3879485471
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.4060195032
Short name T668
Test name
Test status
Simulation time 30000956 ps
CPU time 0.86 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218216 kb
Host smart-e292581c-0f08-4a57-bdd1-728774a11dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060195032 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.4060195032
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.732567362
Short name T647
Test name
Test status
Simulation time 48256302 ps
CPU time 1.46 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 217020 kb
Host smart-91b86d67-bf28-4f0a-bd27-99739e5d1253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732567362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.732567362
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert_test.910794879
Short name T501
Test name
Test status
Simulation time 98416884 ps
CPU time 1.05 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:38:58 PM PDT 24
Peak memory 214660 kb
Host smart-299422c6-e656-48fc-b9de-a7a1ab1f1031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910794879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.910794879
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3477941600
Short name T650
Test name
Test status
Simulation time 160033048 ps
CPU time 0.89 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 215804 kb
Host smart-540e233b-ce6c-444f-92a3-0b47a425c35d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477941600 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3477941600
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1345959230
Short name T760
Test name
Test status
Simulation time 90114708 ps
CPU time 1.02 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:38:58 PM PDT 24
Peak memory 216812 kb
Host smart-060730b6-34ff-4730-b98a-3054511ceecf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345959230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1345959230
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2110158765
Short name T761
Test name
Test status
Simulation time 23220868 ps
CPU time 0.93 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 218352 kb
Host smart-2077add8-dfd8-4b09-9400-4c46b5df99c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110158765 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2110158765
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3984558033
Short name T837
Test name
Test status
Simulation time 66440024 ps
CPU time 2.29 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 218204 kb
Host smart-b8ed3342-51c4-49de-90ee-e9ef0458b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984558033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3984558033
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3690809288
Short name T589
Test name
Test status
Simulation time 23894985 ps
CPU time 1.18 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 224024 kb
Host smart-498b7900-8c8d-4216-b859-c5882f655444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690809288 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3690809288
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3277162825
Short name T302
Test name
Test status
Simulation time 61227255 ps
CPU time 0.9 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 207084 kb
Host smart-d42a6348-8520-4bc1-86a7-c4114025ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277162825 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3277162825
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.4266875171
Short name T340
Test name
Test status
Simulation time 17309720 ps
CPU time 0.93 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:38:57 PM PDT 24
Peak memory 215220 kb
Host smart-9e6f9686-100f-4296-a50d-dba05e3d64fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266875171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.4266875171
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2049155024
Short name T661
Test name
Test status
Simulation time 182058156 ps
CPU time 4.09 seconds
Started Jun 06 02:38:55 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 216920 kb
Host smart-16c849e0-19e2-4c06-b412-21e4229b0dc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049155024 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2049155024
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3386968515
Short name T210
Test name
Test status
Simulation time 10768408123 ps
CPU time 118.58 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:40:59 PM PDT 24
Peak memory 221372 kb
Host smart-73862345-f2a5-4cd9-b3c4-d8caa3d0ad0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386968515 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3386968515
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_genbits.2588985994
Short name T547
Test name
Test status
Simulation time 63982617 ps
CPU time 1.26 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 216932 kb
Host smart-42f47c11-07a6-4646-8b74-242becd94ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588985994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2588985994
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2585526201
Short name T7
Test name
Test status
Simulation time 29161506 ps
CPU time 1.31 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 219640 kb
Host smart-02e07ae2-cd88-4a89-867b-68a2e3974d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585526201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2585526201
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2203016901
Short name T595
Test name
Test status
Simulation time 50690125 ps
CPU time 1.27 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 218200 kb
Host smart-c3ec5a7f-a80f-4e45-8ef3-f836f32e7131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203016901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2203016901
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.712179739
Short name T120
Test name
Test status
Simulation time 51367191 ps
CPU time 1.31 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 225668 kb
Host smart-8e8668d0-6773-44ac-ab63-88dee646ed6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712179739 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.712179739
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3382513771
Short name T708
Test name
Test status
Simulation time 50698290 ps
CPU time 1.81 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:23 PM PDT 24
Peak memory 217040 kb
Host smart-256e739a-170f-4580-9999-e2fab0ff7249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382513771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3382513771
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1133167146
Short name T109
Test name
Test status
Simulation time 26444015 ps
CPU time 1.28 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 229508 kb
Host smart-79ae81da-051c-4c0d-9a90-89c388da8680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133167146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1133167146
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1922171552
Short name T766
Test name
Test status
Simulation time 46789181 ps
CPU time 1.58 seconds
Started Jun 06 02:40:28 PM PDT 24
Finished Jun 06 02:40:33 PM PDT 24
Peak memory 218004 kb
Host smart-12b6e0b2-a944-439e-b8ab-819010bd1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922171552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1922171552
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.750383005
Short name T18
Test name
Test status
Simulation time 22888444 ps
CPU time 1.06 seconds
Started Jun 06 02:40:19 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 223956 kb
Host smart-e139b7e2-9b39-4e20-be48-e5c2c42626b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750383005 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.750383005
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2362157284
Short name T278
Test name
Test status
Simulation time 70535411 ps
CPU time 2.01 seconds
Started Jun 06 02:40:29 PM PDT 24
Finished Jun 06 02:40:34 PM PDT 24
Peak memory 219504 kb
Host smart-ecd73ce0-69c4-4fab-bd86-3b5c3d2a774f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362157284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2362157284
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3921219488
Short name T172
Test name
Test status
Simulation time 24641279 ps
CPU time 1.02 seconds
Started Jun 06 02:40:27 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 229592 kb
Host smart-2f3860e5-3be7-4053-835c-0d84ac285926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921219488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3921219488
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3412396533
Short name T263
Test name
Test status
Simulation time 70587157 ps
CPU time 1.25 seconds
Started Jun 06 02:40:27 PM PDT 24
Finished Jun 06 02:40:32 PM PDT 24
Peak memory 218176 kb
Host smart-5ae0f83e-a25e-418c-a3f3-58ce3afbb334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412396533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3412396533
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1792686779
Short name T572
Test name
Test status
Simulation time 18882679 ps
CPU time 1.04 seconds
Started Jun 06 02:40:18 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 218324 kb
Host smart-9c85f920-45a5-4221-9fef-596d9cd2ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792686779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1792686779
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.946688110
Short name T406
Test name
Test status
Simulation time 31526279 ps
CPU time 1.29 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:21 PM PDT 24
Peak memory 217144 kb
Host smart-48a65793-2ce5-47c3-8a92-d55f7a356db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946688110 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.946688110
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3764095256
Short name T365
Test name
Test status
Simulation time 69102220 ps
CPU time 0.94 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 219800 kb
Host smart-40bb01ec-1bb2-4c66-9d55-4a29af7d6c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764095256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3764095256
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2546006074
Short name T587
Test name
Test status
Simulation time 4584180533 ps
CPU time 87.69 seconds
Started Jun 06 02:40:21 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 218560 kb
Host smart-89c5d882-bbb5-4761-9a0e-f5acb0e94aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546006074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2546006074
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3749997364
Short name T17
Test name
Test status
Simulation time 19279911 ps
CPU time 1.15 seconds
Started Jun 06 02:40:21 PM PDT 24
Finished Jun 06 02:40:26 PM PDT 24
Peak memory 224044 kb
Host smart-6ad06997-6b40-4b31-b6fc-28518bf250f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749997364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3749997364
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3855125844
Short name T705
Test name
Test status
Simulation time 47662508 ps
CPU time 1.29 seconds
Started Jun 06 02:40:17 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 218180 kb
Host smart-f7b53caa-5c84-4e67-b7ff-a634614691a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855125844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3855125844
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1539011405
Short name T634
Test name
Test status
Simulation time 154939459 ps
CPU time 1.17 seconds
Started Jun 06 02:40:21 PM PDT 24
Finished Jun 06 02:40:26 PM PDT 24
Peak memory 219484 kb
Host smart-3091cdf6-56d4-4773-8d2c-39d9edbd20ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539011405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1539011405
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3022489897
Short name T420
Test name
Test status
Simulation time 42725256 ps
CPU time 1.77 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:27 PM PDT 24
Peak memory 219672 kb
Host smart-b7413d92-b681-4d82-9896-564553603ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022489897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3022489897
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert_test.1381425025
Short name T396
Test name
Test status
Simulation time 16857218 ps
CPU time 0.96 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 206528 kb
Host smart-5cea2f8a-c577-4f46-b885-c93cd43f1aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381425025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1381425025
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1948802392
Short name T787
Test name
Test status
Simulation time 11720799 ps
CPU time 0.93 seconds
Started Jun 06 02:38:58 PM PDT 24
Finished Jun 06 02:39:02 PM PDT 24
Peak memory 216152 kb
Host smart-c1c81629-22d7-4fb1-b94a-656727f4d84a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948802392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1948802392
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1423225507
Short name T550
Test name
Test status
Simulation time 71240537 ps
CPU time 1.28 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 216792 kb
Host smart-c44aeceb-c2d6-460a-832e-6ec9bda1659f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423225507 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1423225507
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1637508837
Short name T112
Test name
Test status
Simulation time 23931906 ps
CPU time 1.17 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:01 PM PDT 24
Peak memory 219476 kb
Host smart-19674fad-c72e-4544-ad14-3b79a62616e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637508837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1637508837
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1310983626
Short name T425
Test name
Test status
Simulation time 118321701 ps
CPU time 1.36 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:01 PM PDT 24
Peak memory 219848 kb
Host smart-c110cbc9-2b59-472a-8609-889ce895a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310983626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1310983626
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2244757098
Short name T94
Test name
Test status
Simulation time 45550618 ps
CPU time 0.81 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:38:59 PM PDT 24
Peak memory 215460 kb
Host smart-f2e2b0bd-8253-4217-8806-9779104719d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244757098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2244757098
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.4007342471
Short name T603
Test name
Test status
Simulation time 28567187 ps
CPU time 0.94 seconds
Started Jun 06 02:38:56 PM PDT 24
Finished Jun 06 02:39:00 PM PDT 24
Peak memory 215228 kb
Host smart-5bc19cc4-74b2-4aa2-a551-a3afe8fc194b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007342471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4007342471
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.577895853
Short name T556
Test name
Test status
Simulation time 570206236 ps
CPU time 3.69 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:39:03 PM PDT 24
Peak memory 216744 kb
Host smart-a8ed30de-84f9-4522-924c-af547d7f10b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577895853 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.577895853
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3333836693
Short name T574
Test name
Test status
Simulation time 55967401469 ps
CPU time 1231.31 seconds
Started Jun 06 02:38:57 PM PDT 24
Finished Jun 06 02:59:32 PM PDT 24
Peak memory 223724 kb
Host smart-5049daba-b31b-4612-8794-8d66b21a68ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333836693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3333836693
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1103508298
Short name T807
Test name
Test status
Simulation time 25609314 ps
CPU time 1.11 seconds
Started Jun 06 02:40:19 PM PDT 24
Finished Jun 06 02:40:24 PM PDT 24
Peak memory 229588 kb
Host smart-46235bd5-4d0c-4954-b201-6d7067c52224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103508298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1103508298
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3005650042
Short name T250
Test name
Test status
Simulation time 154018027 ps
CPU time 1.24 seconds
Started Jun 06 02:40:16 PM PDT 24
Finished Jun 06 02:40:22 PM PDT 24
Peak memory 217052 kb
Host smart-d31fd11b-2510-4959-bb8b-2e7fedbc9ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005650042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3005650042
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.2465732102
Short name T652
Test name
Test status
Simulation time 141283566 ps
CPU time 1.13 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 219660 kb
Host smart-95c44831-128c-4917-acae-071e221fae95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465732102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.2465732102
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.43958310
Short name T419
Test name
Test status
Simulation time 45519748 ps
CPU time 1.35 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:26 PM PDT 24
Peak memory 218124 kb
Host smart-dc5cfb11-1c2e-4a14-97eb-03fce30da813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43958310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.43958310
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3926564719
Short name T187
Test name
Test status
Simulation time 29437924 ps
CPU time 1.21 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:25 PM PDT 24
Peak memory 219576 kb
Host smart-81f9d4d2-bd78-4c51-a626-085950185df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926564719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3926564719
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1940804912
Short name T424
Test name
Test status
Simulation time 119702027 ps
CPU time 1.01 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:26 PM PDT 24
Peak memory 216952 kb
Host smart-a8473770-e305-4194-a1d7-41778c6ee8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940804912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1940804912
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3673006908
Short name T637
Test name
Test status
Simulation time 33054923 ps
CPU time 0.89 seconds
Started Jun 06 02:40:20 PM PDT 24
Finished Jun 06 02:40:26 PM PDT 24
Peak memory 218372 kb
Host smart-86bd10a2-ad69-49f6-b357-46a1bdf596ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673006908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3673006908
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1741818005
Short name T277
Test name
Test status
Simulation time 117474160 ps
CPU time 1.66 seconds
Started Jun 06 02:40:27 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 218184 kb
Host smart-b99c16e7-63d4-4bd2-99ea-1613559478d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741818005 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1741818005
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1129851855
Short name T135
Test name
Test status
Simulation time 42466182 ps
CPU time 0.81 seconds
Started Jun 06 02:40:22 PM PDT 24
Finished Jun 06 02:40:27 PM PDT 24
Peak memory 218360 kb
Host smart-1e7bdba9-ee3f-4b8b-961c-932826a359e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129851855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1129851855
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4121478944
Short name T13
Test name
Test status
Simulation time 94102742 ps
CPU time 1.32 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218276 kb
Host smart-981ff636-3656-4878-8740-4d301f8c9224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121478944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4121478944
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1273964304
Short name T540
Test name
Test status
Simulation time 67815861 ps
CPU time 1.23 seconds
Started Jun 06 02:40:27 PM PDT 24
Finished Jun 06 02:40:31 PM PDT 24
Peak memory 224628 kb
Host smart-8bb6d0e6-e285-4f84-997a-b11020408441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273964304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1273964304
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3312293850
Short name T455
Test name
Test status
Simulation time 103745975 ps
CPU time 1.37 seconds
Started Jun 06 02:40:30 PM PDT 24
Finished Jun 06 02:40:33 PM PDT 24
Peak memory 218404 kb
Host smart-1740fbe8-d673-4523-a34d-a573e39803c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312293850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3312293850
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.4157858878
Short name T170
Test name
Test status
Simulation time 22379775 ps
CPU time 0.92 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218356 kb
Host smart-29b3d6ce-9425-4fee-9197-0fef06bc36ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157858878 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4157858878
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1519356493
Short name T483
Test name
Test status
Simulation time 48258340 ps
CPU time 1.38 seconds
Started Jun 06 02:40:24 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 217056 kb
Host smart-0c6b5a34-bbed-4b01-ad4d-bffe9cb0b43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519356493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1519356493
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2192118872
Short name T332
Test name
Test status
Simulation time 19963122 ps
CPU time 0.95 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218460 kb
Host smart-a747d906-66e3-420e-a294-403ce3587c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192118872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2192118872
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2434108182
Short name T466
Test name
Test status
Simulation time 78842987 ps
CPU time 1.46 seconds
Started Jun 06 02:40:22 PM PDT 24
Finished Jun 06 02:40:27 PM PDT 24
Peak memory 218556 kb
Host smart-5895b7c1-7ec6-4c88-827b-4a050b8bb708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434108182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2434108182
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.884126194
Short name T422
Test name
Test status
Simulation time 32815033 ps
CPU time 1.03 seconds
Started Jun 06 02:40:26 PM PDT 24
Finished Jun 06 02:40:30 PM PDT 24
Peak memory 218644 kb
Host smart-8fa6a094-88b7-4904-b5dd-0b3942bb0c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884126194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.884126194
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2685913900
Short name T361
Test name
Test status
Simulation time 65254824 ps
CPU time 1.63 seconds
Started Jun 06 02:40:23 PM PDT 24
Finished Jun 06 02:40:28 PM PDT 24
Peak memory 218276 kb
Host smart-75a0ec22-9547-40e8-b1bb-e2cb7ba7ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685913900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2685913900
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2099477466
Short name T463
Test name
Test status
Simulation time 19816517 ps
CPU time 1.04 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 218668 kb
Host smart-5ffc61c4-980d-4927-8760-0229c27de1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099477466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2099477466
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.31545795
Short name T791
Test name
Test status
Simulation time 46296776 ps
CPU time 1.55 seconds
Started Jun 06 02:40:25 PM PDT 24
Finished Jun 06 02:40:29 PM PDT 24
Peak memory 217040 kb
Host smart-d265ee38-bd4d-45f9-bc17-7400197b0251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31545795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.31545795
Directory /workspace/99.edn_genbits/latest
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