Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.47 98.24 93.78 97.02 91.86 96.33 99.77 91.31


Total test records in report: 974
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T798 /workspace/coverage/default/237.edn_genbits.220892351 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:48 PM PDT 24 102105064 ps
T799 /workspace/coverage/default/195.edn_genbits.3959646629 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:49 PM PDT 24 49823668 ps
T800 /workspace/coverage/default/98.edn_err.256582334 Jun 09 01:55:58 PM PDT 24 Jun 09 01:56:00 PM PDT 24 27021585 ps
T801 /workspace/coverage/default/33.edn_err.283700277 Jun 09 01:55:14 PM PDT 24 Jun 09 01:55:16 PM PDT 24 21168603 ps
T802 /workspace/coverage/default/37.edn_smoke.3193837846 Jun 09 01:55:22 PM PDT 24 Jun 09 01:55:24 PM PDT 24 17525278 ps
T803 /workspace/coverage/default/85.edn_err.1780414338 Jun 09 01:55:50 PM PDT 24 Jun 09 01:55:52 PM PDT 24 91386249 ps
T804 /workspace/coverage/default/12.edn_smoke.3782977375 Jun 09 01:54:39 PM PDT 24 Jun 09 01:54:40 PM PDT 24 50622158 ps
T805 /workspace/coverage/default/0.edn_smoke.1951764052 Jun 09 01:54:26 PM PDT 24 Jun 09 01:54:27 PM PDT 24 23034326 ps
T806 /workspace/coverage/default/290.edn_genbits.633369996 Jun 09 01:56:47 PM PDT 24 Jun 09 01:56:49 PM PDT 24 93304238 ps
T807 /workspace/coverage/default/218.edn_genbits.929104591 Jun 09 01:56:47 PM PDT 24 Jun 09 01:56:49 PM PDT 24 116289992 ps
T808 /workspace/coverage/default/44.edn_disable_auto_req_mode.2039326093 Jun 09 01:55:35 PM PDT 24 Jun 09 01:55:37 PM PDT 24 109998655 ps
T809 /workspace/coverage/default/43.edn_err.1511908103 Jun 09 01:55:31 PM PDT 24 Jun 09 01:55:33 PM PDT 24 19811522 ps
T122 /workspace/coverage/default/47.edn_alert.2256952230 Jun 09 01:55:39 PM PDT 24 Jun 09 01:55:41 PM PDT 24 86369804 ps
T210 /workspace/coverage/default/91.edn_err.846823549 Jun 09 01:55:54 PM PDT 24 Jun 09 01:55:56 PM PDT 24 19924937 ps
T211 /workspace/coverage/default/142.edn_genbits.2870997257 Jun 09 01:56:16 PM PDT 24 Jun 09 01:56:17 PM PDT 24 60588011 ps
T212 /workspace/coverage/default/35.edn_genbits.1931987363 Jun 09 01:55:22 PM PDT 24 Jun 09 01:55:24 PM PDT 24 102788735 ps
T213 /workspace/coverage/default/3.edn_stress_all.1479114003 Jun 09 01:54:15 PM PDT 24 Jun 09 01:54:18 PM PDT 24 350297117 ps
T214 /workspace/coverage/default/1.edn_regwen.2311488701 Jun 09 01:54:10 PM PDT 24 Jun 09 01:54:11 PM PDT 24 35501955 ps
T215 /workspace/coverage/default/156.edn_genbits.1645134283 Jun 09 01:56:41 PM PDT 24 Jun 09 01:56:42 PM PDT 24 42179358 ps
T216 /workspace/coverage/default/173.edn_genbits.1926394436 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:49 PM PDT 24 49985892 ps
T217 /workspace/coverage/default/273.edn_genbits.1158810649 Jun 09 01:56:44 PM PDT 24 Jun 09 01:56:46 PM PDT 24 44542235 ps
T218 /workspace/coverage/default/38.edn_disable_auto_req_mode.139285295 Jun 09 01:55:28 PM PDT 24 Jun 09 01:55:29 PM PDT 24 35284850 ps
T810 /workspace/coverage/default/34.edn_smoke.1529451876 Jun 09 01:55:14 PM PDT 24 Jun 09 01:55:16 PM PDT 24 49382244 ps
T118 /workspace/coverage/default/2.edn_err.889564071 Jun 09 01:54:15 PM PDT 24 Jun 09 01:54:16 PM PDT 24 25407773 ps
T811 /workspace/coverage/default/238.edn_genbits.3045300186 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:49 PM PDT 24 119561324 ps
T812 /workspace/coverage/default/47.edn_smoke.3267184626 Jun 09 01:55:37 PM PDT 24 Jun 09 01:55:39 PM PDT 24 47353328 ps
T813 /workspace/coverage/default/15.edn_intr.3038965751 Jun 09 01:54:57 PM PDT 24 Jun 09 01:54:59 PM PDT 24 37996479 ps
T104 /workspace/coverage/default/17.edn_alert.3579260271 Jun 09 01:54:51 PM PDT 24 Jun 09 01:54:53 PM PDT 24 66783934 ps
T814 /workspace/coverage/default/193.edn_genbits.464162388 Jun 09 01:56:39 PM PDT 24 Jun 09 01:56:40 PM PDT 24 26973064 ps
T815 /workspace/coverage/default/78.edn_err.3547132972 Jun 09 01:55:51 PM PDT 24 Jun 09 01:55:52 PM PDT 24 18784281 ps
T816 /workspace/coverage/default/20.edn_alert_test.2697066217 Jun 09 01:54:52 PM PDT 24 Jun 09 01:54:54 PM PDT 24 44167055 ps
T817 /workspace/coverage/default/240.edn_genbits.2074831420 Jun 09 01:56:26 PM PDT 24 Jun 09 01:56:31 PM PDT 24 331183736 ps
T818 /workspace/coverage/default/151.edn_genbits.1557753439 Jun 09 01:56:42 PM PDT 24 Jun 09 01:56:44 PM PDT 24 375230929 ps
T819 /workspace/coverage/default/258.edn_genbits.710751895 Jun 09 01:56:45 PM PDT 24 Jun 09 01:56:47 PM PDT 24 53053669 ps
T820 /workspace/coverage/default/264.edn_genbits.4052900619 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:49 PM PDT 24 253954229 ps
T115 /workspace/coverage/default/19.edn_alert.3773895818 Jun 09 01:54:54 PM PDT 24 Jun 09 01:54:56 PM PDT 24 28212851 ps
T821 /workspace/coverage/default/46.edn_smoke.310766838 Jun 09 01:55:40 PM PDT 24 Jun 09 01:55:41 PM PDT 24 37774556 ps
T84 /workspace/coverage/default/0.edn_intr.1131841654 Jun 09 01:54:09 PM PDT 24 Jun 09 01:54:10 PM PDT 24 75958836 ps
T822 /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2357070825 Jun 09 01:54:10 PM PDT 24 Jun 09 02:05:59 PM PDT 24 124563925866 ps
T823 /workspace/coverage/default/13.edn_stress_all.2351829937 Jun 09 01:54:44 PM PDT 24 Jun 09 01:54:48 PM PDT 24 486605928 ps
T824 /workspace/coverage/default/43.edn_disable_auto_req_mode.1491124546 Jun 09 01:55:33 PM PDT 24 Jun 09 01:55:34 PM PDT 24 29953100 ps
T825 /workspace/coverage/default/6.edn_stress_all.762405693 Jun 09 01:54:24 PM PDT 24 Jun 09 01:54:31 PM PDT 24 281912578 ps
T826 /workspace/coverage/default/252.edn_genbits.1207198284 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:50 PM PDT 24 177611335 ps
T290 /workspace/coverage/default/49.edn_genbits.538543095 Jun 09 01:55:43 PM PDT 24 Jun 09 01:55:45 PM PDT 24 70006687 ps
T827 /workspace/coverage/default/97.edn_genbits.1758027975 Jun 09 01:55:58 PM PDT 24 Jun 09 01:56:01 PM PDT 24 49035210 ps
T828 /workspace/coverage/default/269.edn_genbits.3353497550 Jun 09 01:56:46 PM PDT 24 Jun 09 01:56:49 PM PDT 24 158260793 ps
T829 /workspace/coverage/default/227.edn_genbits.1663277854 Jun 09 01:56:44 PM PDT 24 Jun 09 01:56:47 PM PDT 24 198958460 ps
T830 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.762990518 Jun 09 01:55:33 PM PDT 24 Jun 09 02:05:32 PM PDT 24 243885962042 ps
T831 /workspace/coverage/default/96.edn_err.3105896179 Jun 09 01:55:55 PM PDT 24 Jun 09 01:55:57 PM PDT 24 31262094 ps
T832 /workspace/coverage/default/44.edn_intr.3854876768 Jun 09 01:55:38 PM PDT 24 Jun 09 01:55:40 PM PDT 24 59464995 ps
T833 /workspace/coverage/default/279.edn_genbits.1927604373 Jun 09 01:56:49 PM PDT 24 Jun 09 01:56:52 PM PDT 24 42220570 ps
T834 /workspace/coverage/default/2.edn_stress_all_with_rand_reset.950544752 Jun 09 01:54:13 PM PDT 24 Jun 09 02:08:34 PM PDT 24 120326580949 ps
T835 /workspace/coverage/default/65.edn_err.739342624 Jun 09 01:55:49 PM PDT 24 Jun 09 01:55:52 PM PDT 24 34067540 ps
T126 /workspace/coverage/default/4.edn_err.1987152649 Jun 09 01:54:22 PM PDT 24 Jun 09 01:54:23 PM PDT 24 61331913 ps
T836 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2843450934 Jun 09 01:54:20 PM PDT 24 Jun 09 02:07:15 PM PDT 24 34482705085 ps
T837 /workspace/coverage/default/98.edn_genbits.2327406459 Jun 09 01:55:58 PM PDT 24 Jun 09 01:56:00 PM PDT 24 41071803 ps
T838 /workspace/coverage/default/281.edn_genbits.1721892633 Jun 09 01:56:48 PM PDT 24 Jun 09 01:56:50 PM PDT 24 40448185 ps
T839 /workspace/coverage/default/45.edn_disable_auto_req_mode.3362669761 Jun 09 01:55:39 PM PDT 24 Jun 09 01:55:41 PM PDT 24 26951957 ps
T840 /workspace/coverage/default/175.edn_genbits.3539268024 Jun 09 01:56:42 PM PDT 24 Jun 09 01:56:44 PM PDT 24 119644760 ps
T237 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4064789001 Jun 09 12:47:12 PM PDT 24 Jun 09 12:47:13 PM PDT 24 18525176 ps
T238 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.394102994 Jun 09 12:47:20 PM PDT 24 Jun 09 12:47:22 PM PDT 24 40719250 ps
T841 /workspace/coverage/cover_reg_top/41.edn_intr_test.1237190076 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:39 PM PDT 24 46245242 ps
T239 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1303030625 Jun 09 12:47:10 PM PDT 24 Jun 09 12:47:11 PM PDT 24 43679720 ps
T842 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3049887449 Jun 09 12:47:15 PM PDT 24 Jun 09 12:47:17 PM PDT 24 139425542 ps
T843 /workspace/coverage/cover_reg_top/14.edn_intr_test.4095885148 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 16081574 ps
T844 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2639818950 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:35 PM PDT 24 33368237 ps
T845 /workspace/coverage/cover_reg_top/20.edn_intr_test.2786049788 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:34 PM PDT 24 15519557 ps
T219 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.802932706 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:30 PM PDT 24 57926536 ps
T846 /workspace/coverage/cover_reg_top/28.edn_intr_test.1804209773 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:34 PM PDT 24 15956021 ps
T240 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3322532383 Jun 09 12:47:05 PM PDT 24 Jun 09 12:47:07 PM PDT 24 15314753 ps
T847 /workspace/coverage/cover_reg_top/19.edn_tl_errors.785122795 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:39 PM PDT 24 111631974 ps
T220 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1861415780 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 63965375 ps
T848 /workspace/coverage/cover_reg_top/13.edn_csr_rw.855544026 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:25 PM PDT 24 116558132 ps
T221 /workspace/coverage/cover_reg_top/16.edn_csr_rw.921696520 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:29 PM PDT 24 12077624 ps
T849 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3015099042 Jun 09 12:47:02 PM PDT 24 Jun 09 12:47:06 PM PDT 24 425455985 ps
T850 /workspace/coverage/cover_reg_top/38.edn_intr_test.921048387 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:35 PM PDT 24 41769809 ps
T851 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2994469892 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:35 PM PDT 24 40832976 ps
T222 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3216049497 Jun 09 12:47:15 PM PDT 24 Jun 09 12:47:16 PM PDT 24 30635530 ps
T852 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3075785004 Jun 09 12:47:16 PM PDT 24 Jun 09 12:47:19 PM PDT 24 99308013 ps
T251 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2740322005 Jun 09 12:47:30 PM PDT 24 Jun 09 12:47:33 PM PDT 24 179036431 ps
T853 /workspace/coverage/cover_reg_top/7.edn_tl_errors.353043212 Jun 09 12:47:11 PM PDT 24 Jun 09 12:47:14 PM PDT 24 256340879 ps
T854 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.689721932 Jun 09 12:47:24 PM PDT 24 Jun 09 12:47:26 PM PDT 24 18085899 ps
T223 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.45174573 Jun 09 12:46:51 PM PDT 24 Jun 09 12:46:52 PM PDT 24 16438378 ps
T224 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1800614482 Jun 09 12:47:32 PM PDT 24 Jun 09 12:47:33 PM PDT 24 78707012 ps
T855 /workspace/coverage/cover_reg_top/35.edn_intr_test.1805451477 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 15587806 ps
T856 /workspace/coverage/cover_reg_top/2.edn_intr_test.4059849028 Jun 09 12:47:03 PM PDT 24 Jun 09 12:47:04 PM PDT 24 19277595 ps
T857 /workspace/coverage/cover_reg_top/40.edn_intr_test.3826480899 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:41 PM PDT 24 66709543 ps
T225 /workspace/coverage/cover_reg_top/12.edn_csr_rw.873269923 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:30 PM PDT 24 31535568 ps
T252 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1639049714 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:36 PM PDT 24 91261121 ps
T858 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2856416687 Jun 09 12:47:19 PM PDT 24 Jun 09 12:47:21 PM PDT 24 87030725 ps
T859 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2426335448 Jun 09 12:46:50 PM PDT 24 Jun 09 12:46:54 PM PDT 24 864753048 ps
T860 /workspace/coverage/cover_reg_top/46.edn_intr_test.1650903274 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:40 PM PDT 24 12848629 ps
T861 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2955456715 Jun 09 12:46:56 PM PDT 24 Jun 09 12:46:57 PM PDT 24 25782949 ps
T862 /workspace/coverage/cover_reg_top/12.edn_intr_test.3545643522 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 17466618 ps
T241 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.620891432 Jun 09 12:47:18 PM PDT 24 Jun 09 12:47:20 PM PDT 24 32441532 ps
T226 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2972355296 Jun 09 12:47:02 PM PDT 24 Jun 09 12:47:03 PM PDT 24 69740539 ps
T863 /workspace/coverage/cover_reg_top/45.edn_intr_test.4136595309 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 24047045 ps
T864 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3775070183 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:28 PM PDT 24 40209265 ps
T865 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1860766299 Jun 09 12:47:09 PM PDT 24 Jun 09 12:47:11 PM PDT 24 22547521 ps
T866 /workspace/coverage/cover_reg_top/31.edn_intr_test.1337517985 Jun 09 12:47:31 PM PDT 24 Jun 09 12:47:33 PM PDT 24 49655819 ps
T867 /workspace/coverage/cover_reg_top/17.edn_csr_rw.992404401 Jun 09 12:47:27 PM PDT 24 Jun 09 12:47:29 PM PDT 24 34819325 ps
T868 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2802653746 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:37 PM PDT 24 148595814 ps
T869 /workspace/coverage/cover_reg_top/19.edn_intr_test.1568579399 Jun 09 12:47:32 PM PDT 24 Jun 09 12:47:33 PM PDT 24 53020622 ps
T870 /workspace/coverage/cover_reg_top/4.edn_intr_test.2171521202 Jun 09 12:47:07 PM PDT 24 Jun 09 12:47:08 PM PDT 24 43212966 ps
T871 /workspace/coverage/cover_reg_top/13.edn_intr_test.583840739 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:29 PM PDT 24 37462490 ps
T872 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1304488901 Jun 09 12:46:51 PM PDT 24 Jun 09 12:46:53 PM PDT 24 49199331 ps
T873 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2778355451 Jun 09 12:46:57 PM PDT 24 Jun 09 12:47:01 PM PDT 24 487669328 ps
T874 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2052636619 Jun 09 12:46:50 PM PDT 24 Jun 09 12:46:52 PM PDT 24 97210367 ps
T875 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1369422379 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:28 PM PDT 24 213469874 ps
T876 /workspace/coverage/cover_reg_top/30.edn_intr_test.1461197846 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:36 PM PDT 24 56704937 ps
T227 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1478159180 Jun 09 12:47:01 PM PDT 24 Jun 09 12:47:03 PM PDT 24 136614418 ps
T242 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3534878456 Jun 09 12:47:16 PM PDT 24 Jun 09 12:47:17 PM PDT 24 15870729 ps
T877 /workspace/coverage/cover_reg_top/10.edn_intr_test.2145258472 Jun 09 12:47:14 PM PDT 24 Jun 09 12:47:15 PM PDT 24 26979632 ps
T878 /workspace/coverage/cover_reg_top/47.edn_intr_test.2102399613 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:39 PM PDT 24 27989819 ps
T253 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3967300591 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:28 PM PDT 24 255676422 ps
T879 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.245090779 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:25 PM PDT 24 72502262 ps
T228 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2224109602 Jun 09 12:47:11 PM PDT 24 Jun 09 12:47:13 PM PDT 24 36483630 ps
T258 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2097944398 Jun 09 12:47:18 PM PDT 24 Jun 09 12:47:21 PM PDT 24 179203928 ps
T880 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.312909540 Jun 09 12:47:13 PM PDT 24 Jun 09 12:47:14 PM PDT 24 32967969 ps
T881 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4152769082 Jun 09 12:47:10 PM PDT 24 Jun 09 12:47:12 PM PDT 24 101339416 ps
T882 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.59480093 Jun 09 12:46:53 PM PDT 24 Jun 09 12:46:54 PM PDT 24 234250430 ps
T229 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3319082005 Jun 09 12:47:16 PM PDT 24 Jun 09 12:47:17 PM PDT 24 11468213 ps
T883 /workspace/coverage/cover_reg_top/0.edn_intr_test.1207738611 Jun 09 12:46:46 PM PDT 24 Jun 09 12:46:47 PM PDT 24 14000198 ps
T884 /workspace/coverage/cover_reg_top/22.edn_intr_test.1706132016 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 15663366 ps
T257 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1711952884 Jun 09 12:47:10 PM PDT 24 Jun 09 12:47:12 PM PDT 24 43755426 ps
T885 /workspace/coverage/cover_reg_top/19.edn_csr_rw.2136741159 Jun 09 12:47:31 PM PDT 24 Jun 09 12:47:32 PM PDT 24 45505685 ps
T886 /workspace/coverage/cover_reg_top/32.edn_intr_test.2959721747 Jun 09 12:47:32 PM PDT 24 Jun 09 12:47:33 PM PDT 24 157677815 ps
T230 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2408919393 Jun 09 12:46:52 PM PDT 24 Jun 09 12:46:53 PM PDT 24 50483888 ps
T887 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1585992771 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:30 PM PDT 24 17416627 ps
T259 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3328447734 Jun 09 12:46:50 PM PDT 24 Jun 09 12:46:52 PM PDT 24 70965981 ps
T231 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2115138770 Jun 09 12:47:11 PM PDT 24 Jun 09 12:47:12 PM PDT 24 23958410 ps
T232 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3733645982 Jun 09 12:47:01 PM PDT 24 Jun 09 12:47:02 PM PDT 24 43779640 ps
T888 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3494858443 Jun 09 12:47:10 PM PDT 24 Jun 09 12:47:12 PM PDT 24 44951359 ps
T889 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2598483753 Jun 09 12:47:20 PM PDT 24 Jun 09 12:47:22 PM PDT 24 98375642 ps
T890 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2588853358 Jun 09 12:46:57 PM PDT 24 Jun 09 12:47:00 PM PDT 24 467217940 ps
T891 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2120529955 Jun 09 12:47:01 PM PDT 24 Jun 09 12:47:02 PM PDT 24 18327742 ps
T892 /workspace/coverage/cover_reg_top/8.edn_intr_test.1743101419 Jun 09 12:47:14 PM PDT 24 Jun 09 12:47:15 PM PDT 24 33726700 ps
T893 /workspace/coverage/cover_reg_top/33.edn_intr_test.3007979533 Jun 09 12:47:31 PM PDT 24 Jun 09 12:47:32 PM PDT 24 22690974 ps
T894 /workspace/coverage/cover_reg_top/17.edn_intr_test.2214673794 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:36 PM PDT 24 30064026 ps
T895 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2320577038 Jun 09 12:47:16 PM PDT 24 Jun 09 12:47:17 PM PDT 24 20560142 ps
T896 /workspace/coverage/cover_reg_top/34.edn_intr_test.231392275 Jun 09 12:47:31 PM PDT 24 Jun 09 12:47:33 PM PDT 24 12185593 ps
T897 /workspace/coverage/cover_reg_top/25.edn_intr_test.1167358355 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:36 PM PDT 24 14300695 ps
T898 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3319942813 Jun 09 12:47:05 PM PDT 24 Jun 09 12:47:09 PM PDT 24 84800075 ps
T899 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3575171078 Jun 09 12:47:17 PM PDT 24 Jun 09 12:47:18 PM PDT 24 12728932 ps
T900 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.208535921 Jun 09 12:47:07 PM PDT 24 Jun 09 12:47:09 PM PDT 24 32630975 ps
T901 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1717586253 Jun 09 12:47:22 PM PDT 24 Jun 09 12:47:23 PM PDT 24 67037371 ps
T902 /workspace/coverage/cover_reg_top/14.edn_tl_errors.4187312558 Jun 09 12:47:24 PM PDT 24 Jun 09 12:47:28 PM PDT 24 43207699 ps
T903 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2864392659 Jun 09 12:47:29 PM PDT 24 Jun 09 12:47:31 PM PDT 24 68920727 ps
T904 /workspace/coverage/cover_reg_top/15.edn_tl_errors.156217748 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:30 PM PDT 24 159407244 ps
T905 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1009548904 Jun 09 12:46:51 PM PDT 24 Jun 09 12:46:52 PM PDT 24 16534896 ps
T906 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.824722319 Jun 09 12:47:10 PM PDT 24 Jun 09 12:47:13 PM PDT 24 89013961 ps
T907 /workspace/coverage/cover_reg_top/15.edn_intr_test.13291758 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:27 PM PDT 24 65344246 ps
T908 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3910736564 Jun 09 12:47:04 PM PDT 24 Jun 09 12:47:05 PM PDT 24 30031335 ps
T909 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4067097309 Jun 09 12:47:01 PM PDT 24 Jun 09 12:47:02 PM PDT 24 88550729 ps
T910 /workspace/coverage/cover_reg_top/39.edn_intr_test.1944722614 Jun 09 12:47:30 PM PDT 24 Jun 09 12:47:31 PM PDT 24 47144732 ps
T911 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1883223114 Jun 09 12:47:29 PM PDT 24 Jun 09 12:47:30 PM PDT 24 27328267 ps
T912 /workspace/coverage/cover_reg_top/48.edn_intr_test.3763444699 Jun 09 12:47:39 PM PDT 24 Jun 09 12:47:40 PM PDT 24 39487844 ps
T913 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3312263959 Jun 09 12:47:19 PM PDT 24 Jun 09 12:47:22 PM PDT 24 63228678 ps
T914 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3818029497 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 17401139 ps
T915 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1646865635 Jun 09 12:47:11 PM PDT 24 Jun 09 12:47:12 PM PDT 24 32926311 ps
T916 /workspace/coverage/cover_reg_top/43.edn_intr_test.1135783378 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 23576660 ps
T917 /workspace/coverage/cover_reg_top/24.edn_intr_test.627349790 Jun 09 12:47:30 PM PDT 24 Jun 09 12:47:32 PM PDT 24 16011056 ps
T233 /workspace/coverage/cover_reg_top/1.edn_csr_rw.431703006 Jun 09 12:46:55 PM PDT 24 Jun 09 12:46:56 PM PDT 24 22087927 ps
T918 /workspace/coverage/cover_reg_top/26.edn_intr_test.2761765372 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:34 PM PDT 24 13607374 ps
T919 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.145317049 Jun 09 12:47:18 PM PDT 24 Jun 09 12:47:19 PM PDT 24 44084326 ps
T920 /workspace/coverage/cover_reg_top/21.edn_intr_test.561665647 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:34 PM PDT 24 18799921 ps
T921 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2286661266 Jun 09 12:47:00 PM PDT 24 Jun 09 12:47:03 PM PDT 24 711605262 ps
T922 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2150930516 Jun 09 12:46:57 PM PDT 24 Jun 09 12:47:00 PM PDT 24 150197537 ps
T923 /workspace/coverage/cover_reg_top/18.edn_intr_test.2143309983 Jun 09 12:47:29 PM PDT 24 Jun 09 12:47:30 PM PDT 24 20764708 ps
T924 /workspace/coverage/cover_reg_top/1.edn_intr_test.2817413723 Jun 09 12:46:58 PM PDT 24 Jun 09 12:47:00 PM PDT 24 26260019 ps
T260 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1896867132 Jun 09 12:47:22 PM PDT 24 Jun 09 12:47:24 PM PDT 24 49845464 ps
T925 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.101609687 Jun 09 12:47:05 PM PDT 24 Jun 09 12:47:07 PM PDT 24 19266394 ps
T926 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1112214279 Jun 09 12:47:24 PM PDT 24 Jun 09 12:47:26 PM PDT 24 88880499 ps
T927 /workspace/coverage/cover_reg_top/17.edn_tl_errors.1364968922 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:36 PM PDT 24 32511745 ps
T928 /workspace/coverage/cover_reg_top/11.edn_intr_test.905731293 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 60063996 ps
T929 /workspace/coverage/cover_reg_top/27.edn_intr_test.663061487 Jun 09 12:47:32 PM PDT 24 Jun 09 12:47:33 PM PDT 24 22334928 ps
T930 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2388983861 Jun 09 12:47:25 PM PDT 24 Jun 09 12:47:26 PM PDT 24 21423852 ps
T931 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2328109771 Jun 09 12:47:09 PM PDT 24 Jun 09 12:47:11 PM PDT 24 92390164 ps
T932 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1841799538 Jun 09 12:47:02 PM PDT 24 Jun 09 12:47:09 PM PDT 24 1004579426 ps
T933 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3120033611 Jun 09 12:47:34 PM PDT 24 Jun 09 12:47:36 PM PDT 24 36230535 ps
T934 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1887096480 Jun 09 12:47:12 PM PDT 24 Jun 09 12:47:14 PM PDT 24 280477008 ps
T935 /workspace/coverage/cover_reg_top/49.edn_intr_test.2678072614 Jun 09 12:47:38 PM PDT 24 Jun 09 12:47:39 PM PDT 24 14029800 ps
T936 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1999111906 Jun 09 12:47:15 PM PDT 24 Jun 09 12:47:16 PM PDT 24 24011481 ps
T937 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4149768170 Jun 09 12:47:29 PM PDT 24 Jun 09 12:47:31 PM PDT 24 19307579 ps
T234 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.998529314 Jun 09 12:47:14 PM PDT 24 Jun 09 12:47:21 PM PDT 24 291816875 ps
T938 /workspace/coverage/cover_reg_top/6.edn_intr_test.3478698237 Jun 09 12:47:13 PM PDT 24 Jun 09 12:47:15 PM PDT 24 15535488 ps
T939 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4042197542 Jun 09 12:47:06 PM PDT 24 Jun 09 12:47:08 PM PDT 24 62185342 ps
T940 /workspace/coverage/cover_reg_top/36.edn_intr_test.1415352500 Jun 09 12:47:32 PM PDT 24 Jun 09 12:47:33 PM PDT 24 156673302 ps
T941 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3229460841 Jun 09 12:47:02 PM PDT 24 Jun 09 12:47:05 PM PDT 24 134922011 ps
T942 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.751681844 Jun 09 12:47:26 PM PDT 24 Jun 09 12:47:28 PM PDT 24 26378456 ps
T943 /workspace/coverage/cover_reg_top/6.edn_tl_errors.3556601948 Jun 09 12:47:11 PM PDT 24 Jun 09 12:47:15 PM PDT 24 208142773 ps
T944 /workspace/coverage/cover_reg_top/16.edn_intr_test.232441446 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:34 PM PDT 24 93127872 ps
T945 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.894345564 Jun 09 12:47:27 PM PDT 24 Jun 09 12:47:29 PM PDT 24 188660607 ps
T946 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1340427231 Jun 09 12:46:59 PM PDT 24 Jun 09 12:47:01 PM PDT 24 39375731 ps
T235 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1282260685 Jun 09 12:46:51 PM PDT 24 Jun 09 12:46:53 PM PDT 24 79766823 ps
T947 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1719765238 Jun 09 12:47:19 PM PDT 24 Jun 09 12:47:21 PM PDT 24 30094068 ps
T948 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.610575626 Jun 09 12:47:24 PM PDT 24 Jun 09 12:47:26 PM PDT 24 318564539 ps
T949 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1426830990 Jun 09 12:47:24 PM PDT 24 Jun 09 12:47:26 PM PDT 24 800061593 ps
T950 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3946950064 Jun 09 12:46:58 PM PDT 24 Jun 09 12:47:05 PM PDT 24 264806498 ps
T951 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1564416677 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 19988320 ps
T952 /workspace/coverage/cover_reg_top/29.edn_intr_test.2520641435 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 17690282 ps
T953 /workspace/coverage/cover_reg_top/44.edn_intr_test.3616469514 Jun 09 12:47:40 PM PDT 24 Jun 09 12:47:41 PM PDT 24 21128863 ps
T954 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2013366417 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:30 PM PDT 24 67280180 ps
T955 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3495001700 Jun 09 12:47:25 PM PDT 24 Jun 09 12:47:29 PM PDT 24 329414519 ps
T956 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1330305411 Jun 09 12:47:33 PM PDT 24 Jun 09 12:47:35 PM PDT 24 24133284 ps
T957 /workspace/coverage/cover_reg_top/3.edn_intr_test.3075168722 Jun 09 12:47:02 PM PDT 24 Jun 09 12:47:04 PM PDT 24 42652186 ps
T958 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.406028731 Jun 09 12:47:09 PM PDT 24 Jun 09 12:47:11 PM PDT 24 22550089 ps
T959 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2647992760 Jun 09 12:47:27 PM PDT 24 Jun 09 12:47:29 PM PDT 24 36624143 ps
T960 /workspace/coverage/cover_reg_top/37.edn_intr_test.295158141 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:37 PM PDT 24 12337125 ps
T961 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3139576555 Jun 09 12:47:07 PM PDT 24 Jun 09 12:47:11 PM PDT 24 529647736 ps
T962 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2662351661 Jun 09 12:47:22 PM PDT 24 Jun 09 12:47:24 PM PDT 24 415738162 ps
T963 /workspace/coverage/cover_reg_top/7.edn_intr_test.4281016600 Jun 09 12:47:13 PM PDT 24 Jun 09 12:47:15 PM PDT 24 38581790 ps
T964 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3560936289 Jun 09 12:47:04 PM PDT 24 Jun 09 12:47:06 PM PDT 24 62488746 ps
T965 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2068735323 Jun 09 12:47:23 PM PDT 24 Jun 09 12:47:24 PM PDT 24 38991884 ps
T966 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1602849804 Jun 09 12:47:16 PM PDT 24 Jun 09 12:47:18 PM PDT 24 135863590 ps
T967 /workspace/coverage/cover_reg_top/42.edn_intr_test.2480933988 Jun 09 12:47:37 PM PDT 24 Jun 09 12:47:39 PM PDT 24 40198421 ps
T968 /workspace/coverage/cover_reg_top/9.edn_intr_test.2579226748 Jun 09 12:47:20 PM PDT 24 Jun 09 12:47:22 PM PDT 24 25465214 ps
T236 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1553838054 Jun 09 12:46:54 PM PDT 24 Jun 09 12:46:56 PM PDT 24 39906241 ps
T969 /workspace/coverage/cover_reg_top/23.edn_intr_test.1210891115 Jun 09 12:47:35 PM PDT 24 Jun 09 12:47:36 PM PDT 24 112841023 ps
T970 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2220916540 Jun 09 12:47:06 PM PDT 24 Jun 09 12:47:07 PM PDT 24 42977714 ps
T971 /workspace/coverage/cover_reg_top/5.edn_intr_test.3693453004 Jun 09 12:47:12 PM PDT 24 Jun 09 12:47:13 PM PDT 24 39125146 ps
T972 /workspace/coverage/cover_reg_top/12.edn_tl_errors.875926208 Jun 09 12:47:28 PM PDT 24 Jun 09 12:47:32 PM PDT 24 76109803 ps
T973 /workspace/coverage/cover_reg_top/8.edn_csr_rw.121308063 Jun 09 12:47:19 PM PDT 24 Jun 09 12:47:20 PM PDT 24 10906941 ps
T974 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4032638880 Jun 09 12:47:20 PM PDT 24 Jun 09 12:47:21 PM PDT 24 36937854 ps

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3214216879
Short name T20
Test name
Test status
Simulation time 80947422210 ps
CPU time 439.3 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 02:02:25 PM PDT 24
Peak memory 218220 kb
Host smart-6ee5a984-809d-4854-9b76-5158a6e0b346
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214216879 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3214216879
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/219.edn_genbits.1314868096
Short name T17
Test name
Test status
Simulation time 34933373 ps
CPU time 1.37 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219748 kb
Host smart-1ef70cc0-915f-445a-ad35-062788088097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314868096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1314868096
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1066131225
Short name T3
Test name
Test status
Simulation time 1684003896 ps
CPU time 4.44 seconds
Started Jun 09 01:54:20 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 236700 kb
Host smart-49fdf982-f549-47ba-a4eb-c35fcc88b6fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066131225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1066131225
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/16.edn_alert.140779320
Short name T29
Test name
Test status
Simulation time 34488958 ps
CPU time 1.19 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 219016 kb
Host smart-2cb74cce-6e84-48d7-8bde-1fa998ac8f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140779320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.140779320
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/58.edn_genbits.3782295116
Short name T45
Test name
Test status
Simulation time 152454743 ps
CPU time 1.55 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 218944 kb
Host smart-5453b07d-5d73-4b1e-bf5e-79d1129e2c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782295116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3782295116
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1440555205
Short name T59
Test name
Test status
Simulation time 551409203 ps
CPU time 8.56 seconds
Started Jun 09 01:54:12 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 239568 kb
Host smart-4a4b1abb-3c56-4411-87ef-09bfdc5dcc4b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440555205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1440555205
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3238349592
Short name T375
Test name
Test status
Simulation time 58389014 ps
CPU time 1.06 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 217888 kb
Host smart-2d73b954-ded0-429c-9ab4-f0cdd5764e77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238349592 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3238349592
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_intr.2297360701
Short name T42
Test name
Test status
Simulation time 62408687 ps
CPU time 0.98 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 223840 kb
Host smart-ba1ac7af-775b-4228-a623-130a7b5ea683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297360701 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2297360701
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2145239549
Short name T15
Test name
Test status
Simulation time 50205153 ps
CPU time 1.12 seconds
Started Jun 09 01:54:20 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 216944 kb
Host smart-bec79cc5-7077-4a59-91d2-c5ece2f51f04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145239549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2145239549
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_alert.1535462667
Short name T51
Test name
Test status
Simulation time 22287446 ps
CPU time 1.17 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 218268 kb
Host smart-fc0582c7-ab82-410d-afe2-83e86f393728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535462667 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1535462667
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert.1446789907
Short name T128
Test name
Test status
Simulation time 28800286 ps
CPU time 1.32 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:13 PM PDT 24
Peak memory 219212 kb
Host smart-da6b7190-d4eb-464f-b35f-94d276ee7018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446789907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1446789907
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/6.edn_regwen.3824519054
Short name T720
Test name
Test status
Simulation time 15901490 ps
CPU time 0.99 seconds
Started Jun 09 01:54:25 PM PDT 24
Finished Jun 09 01:54:27 PM PDT 24
Peak memory 206996 kb
Host smart-7b2117c3-f83f-4c60-b7da-1bb015f663f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824519054 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3824519054
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3342170127
Short name T199
Test name
Test status
Simulation time 78150334205 ps
CPU time 1023.63 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 02:12:06 PM PDT 24
Peak memory 223232 kb
Host smart-3cee8a7f-d1fc-4a26-8940-12985985ef37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342170127 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3342170127
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_disable.4079813410
Short name T27
Test name
Test status
Simulation time 33832753 ps
CPU time 0.85 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 216120 kb
Host smart-29071fd4-dee5-4e98-b9df-8735aad51ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079813410 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4079813410
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/6.edn_alert.1827025627
Short name T132
Test name
Test status
Simulation time 31746868 ps
CPU time 1.14 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 219272 kb
Host smart-f292d683-2672-4b32-93f0-49dbbf817c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827025627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1827025627
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.873269923
Short name T225
Test name
Test status
Simulation time 31535568 ps
CPU time 0.97 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 206248 kb
Host smart-6557adf7-e5f4-4f35-9ca8-82bc1989b216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873269923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.873269923
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2594253879
Short name T127
Test name
Test status
Simulation time 124647411 ps
CPU time 1.07 seconds
Started Jun 09 01:54:09 PM PDT 24
Finished Jun 09 01:54:10 PM PDT 24
Peak memory 218004 kb
Host smart-d73e3e95-988c-4dde-a6d7-333f28ded6f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594253879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2594253879
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2097944398
Short name T258
Test name
Test status
Simulation time 179203928 ps
CPU time 3.04 seconds
Started Jun 09 12:47:18 PM PDT 24
Finished Jun 09 12:47:21 PM PDT 24
Peak memory 214560 kb
Host smart-81d475ba-19ce-4823-87fc-29a0e2656079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097944398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2097944398
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/1.edn_disable.2994709973
Short name T182
Test name
Test status
Simulation time 22500968 ps
CPU time 0.9 seconds
Started Jun 09 01:54:16 PM PDT 24
Finished Jun 09 01:54:17 PM PDT 24
Peak memory 216284 kb
Host smart-2b0d58c3-3fea-45ee-b326-43c373cf6eb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994709973 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2994709973
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.586569299
Short name T166
Test name
Test status
Simulation time 19809587 ps
CPU time 1.01 seconds
Started Jun 09 01:54:40 PM PDT 24
Finished Jun 09 01:54:41 PM PDT 24
Peak memory 216292 kb
Host smart-f075ee1c-63ba-4a1d-b6ea-cf99c4c579e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586569299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.586569299
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable.599912035
Short name T725
Test name
Test status
Simulation time 22157672 ps
CPU time 0.87 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 216140 kb
Host smart-3beb9c27-da30-4eec-a5fe-95c70ea2d256
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599912035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.599912035
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/15.edn_alert.4144635645
Short name T302
Test name
Test status
Simulation time 249493563 ps
CPU time 1.44 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215580 kb
Host smart-f5fdc218-a161-4572-93cc-38d588faa33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144635645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4144635645
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/66.edn_genbits.866052629
Short name T74
Test name
Test status
Simulation time 51179121 ps
CPU time 1.61 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 219820 kb
Host smart-06b19791-ba64-4ccf-83fe-981ca3d084e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866052629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.866052629
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3749567213
Short name T2
Test name
Test status
Simulation time 21233721 ps
CPU time 1.08 seconds
Started Jun 09 01:54:20 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 215776 kb
Host smart-97d1e462-7ad5-450d-9b90-501b98c7ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749567213 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3749567213
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/41.edn_alert.2230576453
Short name T124
Test name
Test status
Simulation time 72019385 ps
CPU time 1.2 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 220408 kb
Host smart-16a8655d-b980-4a6b-8ad7-7087fcf625d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230576453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2230576453
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/164.edn_genbits.3842114883
Short name T278
Test name
Test status
Simulation time 45422674 ps
CPU time 1.82 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 218292 kb
Host smart-936f47e5-c687-4216-9038-6fe978499176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842114883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.3842114883
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.3415394188
Short name T305
Test name
Test status
Simulation time 87904563 ps
CPU time 1.16 seconds
Started Jun 09 01:54:09 PM PDT 24
Finished Jun 09 01:54:10 PM PDT 24
Peak memory 219460 kb
Host smart-bc6fe615-c31a-43ae-a1de-2ba488153c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415394188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3415394188
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.4023029999
Short name T96
Test name
Test status
Simulation time 76065039 ps
CPU time 1.2 seconds
Started Jun 09 01:54:43 PM PDT 24
Finished Jun 09 01:54:44 PM PDT 24
Peak memory 219392 kb
Host smart-c5f7562e-a3b3-4d58-b929-ab0af0b6e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023029999 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4023029999
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert.3154562336
Short name T297
Test name
Test status
Simulation time 28483266 ps
CPU time 1.25 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:50 PM PDT 24
Peak memory 218156 kb
Host smart-b74aa0ce-b4f1-4c81-81f8-731516671cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154562336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3154562336
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert.504065997
Short name T168
Test name
Test status
Simulation time 71968653 ps
CPU time 1.22 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 215580 kb
Host smart-283ca511-cffb-45cd-85c4-98665e545346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504065997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.504065997
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/57.edn_err.2528398306
Short name T169
Test name
Test status
Simulation time 34367504 ps
CPU time 1.01 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 223872 kb
Host smart-35a7b224-b831-45db-b46b-74818dc52006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528398306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2528398306
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/209.edn_genbits.1905896554
Short name T46
Test name
Test status
Simulation time 64094187 ps
CPU time 1.15 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216988 kb
Host smart-515bae17-c847-4191-ab0c-a456a39fb7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905896554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1905896554
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_genbits.2702862487
Short name T292
Test name
Test status
Simulation time 45193864 ps
CPU time 1.61 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 219600 kb
Host smart-d693c296-2358-4600-a5e5-5803af18d6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702862487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2702862487
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.995855870
Short name T669
Test name
Test status
Simulation time 30222983 ps
CPU time 0.83 seconds
Started Jun 09 01:54:11 PM PDT 24
Finished Jun 09 01:54:12 PM PDT 24
Peak memory 215296 kb
Host smart-6b859183-e12b-4d94-804d-7711cd4e02c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995855870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.995855870
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3943646405
Short name T514
Test name
Test status
Simulation time 67760675 ps
CPU time 0.96 seconds
Started Jun 09 01:55:17 PM PDT 24
Finished Jun 09 01:55:18 PM PDT 24
Peak memory 218364 kb
Host smart-c55805a5-59ea-44e3-931a-ff6a546c60df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943646405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3943646405
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_disable.1365408300
Short name T28
Test name
Test status
Simulation time 12829419 ps
CPU time 0.93 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 216284 kb
Host smart-1b33cab5-7253-46b7-83ab-a0b3f6f991be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365408300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1365408300
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/10.edn_intr.3229557394
Short name T85
Test name
Test status
Simulation time 37984368 ps
CPU time 0.86 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 215532 kb
Host smart-c0af1e17-e6ea-46cd-a436-26ffe411cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229557394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3229557394
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/1.edn_alert.3688495459
Short name T101
Test name
Test status
Simulation time 27694034 ps
CPU time 1.18 seconds
Started Jun 09 01:54:11 PM PDT 24
Finished Jun 09 01:54:12 PM PDT 24
Peak memory 218228 kb
Host smart-bfd7839f-4456-4d42-90fa-5ee1149453d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688495459 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3688495459
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/11.edn_err.627518300
Short name T793
Test name
Test status
Simulation time 54766808 ps
CPU time 0.98 seconds
Started Jun 09 01:54:38 PM PDT 24
Finished Jun 09 01:54:40 PM PDT 24
Peak memory 229344 kb
Host smart-3feacc4b-c2c3-4a48-924a-0a6890c2e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627518300 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.627518300
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2826416481
Short name T111
Test name
Test status
Simulation time 51214145 ps
CPU time 1.11 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 216784 kb
Host smart-7bf559fd-e132-4621-9b7b-b3a4573da8ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826416481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2826416481
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_alert.3579260271
Short name T104
Test name
Test status
Simulation time 66783934 ps
CPU time 1.12 seconds
Started Jun 09 01:54:51 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 219040 kb
Host smart-33b1b57c-30d7-4361-81ed-0fef6ed6c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579260271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3579260271
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable.2011667286
Short name T686
Test name
Test status
Simulation time 79281892 ps
CPU time 0.85 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 216272 kb
Host smart-dcd52020-d951-4f2d-bb76-61898d5303d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011667286 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2011667286
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.3122439410
Short name T754
Test name
Test status
Simulation time 62441266 ps
CPU time 1.3 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 216860 kb
Host smart-fa2c7028-8d28-4170-a36b-122ca93fc797
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122439410 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.3122439410
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_alert.3773895818
Short name T115
Test name
Test status
Simulation time 28212851 ps
CPU time 1.25 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 219804 kb
Host smart-a40f4db9-cbd7-4148-a503-69a164a01d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773895818 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3773895818
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert.850829962
Short name T149
Test name
Test status
Simulation time 76804416 ps
CPU time 1.13 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 218112 kb
Host smart-fcc6f550-550b-43e5-8757-97b67969815c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850829962 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.850829962
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert.1086405264
Short name T99
Test name
Test status
Simulation time 91547518 ps
CPU time 1.21 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 219940 kb
Host smart-60ee41c0-9271-4ba0-a31d-c51686fbe72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086405264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1086405264
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/31.edn_disable.4181239736
Short name T174
Test name
Test status
Simulation time 12741496 ps
CPU time 0.95 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 216280 kb
Host smart-47ab825d-5868-41d9-a69a-eb2bb755666c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181239736 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.4181239736
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.3115584109
Short name T188
Test name
Test status
Simulation time 30804894 ps
CPU time 0.83 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 216088 kb
Host smart-d35775d3-ce26-4f5f-a601-355ed9626bc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115584109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3115584109
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable.1548212713
Short name T190
Test name
Test status
Simulation time 10719570 ps
CPU time 0.88 seconds
Started Jun 09 01:55:27 PM PDT 24
Finished Jun 09 01:55:28 PM PDT 24
Peak memory 216168 kb
Host smart-8eb5742b-ee31-4afb-98aa-277df4439942
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548212713 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1548212713
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1701723622
Short name T164
Test name
Test status
Simulation time 18656189 ps
CPU time 1.16 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 224176 kb
Host smart-546ecba2-da00-40db-9240-5a8ff3cbdc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701723622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1701723622
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/5.edn_disable.2185053657
Short name T185
Test name
Test status
Simulation time 15579162 ps
CPU time 0.88 seconds
Started Jun 09 01:54:25 PM PDT 24
Finished Jun 09 01:54:27 PM PDT 24
Peak memory 216284 kb
Host smart-9537cabe-47f7-48c5-b10e-95e9e60a2e19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185053657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2185053657
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/18.edn_alert_test.2023529577
Short name T61
Test name
Test status
Simulation time 17173850 ps
CPU time 0.9 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 206532 kb
Host smart-8f0356a7-5cd1-4f72-b6a8-03efb013b050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023529577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2023529577
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.545054925
Short name T4
Test name
Test status
Simulation time 136678529498 ps
CPU time 877.66 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 02:09:11 PM PDT 24
Peak memory 222748 kb
Host smart-b7a6c8d8-15c5-4507-91dc-386bc54e3049
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545054925 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.545054925
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.1452645723
Short name T263
Test name
Test status
Simulation time 198506591 ps
CPU time 2.27 seconds
Started Jun 09 01:56:01 PM PDT 24
Finished Jun 09 01:56:04 PM PDT 24
Peak memory 217156 kb
Host smart-7b5ef1ea-00ae-490d-b12f-eed84312551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452645723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1452645723
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_genbits.524972278
Short name T254
Test name
Test status
Simulation time 85217167 ps
CPU time 1.18 seconds
Started Jun 09 01:55:56 PM PDT 24
Finished Jun 09 01:55:58 PM PDT 24
Peak memory 217028 kb
Host smart-8b49513a-1129-4d98-96a6-80cbe85b77c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524972278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.524972278
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1131841654
Short name T84
Test name
Test status
Simulation time 75958836 ps
CPU time 0.83 seconds
Started Jun 09 01:54:09 PM PDT 24
Finished Jun 09 01:54:10 PM PDT 24
Peak memory 215520 kb
Host smart-a1d01409-22ee-470d-9602-dd4b9c43c6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131841654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1131841654
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/83.edn_genbits.2222216074
Short name T285
Test name
Test status
Simulation time 66628099 ps
CPU time 1.29 seconds
Started Jun 09 01:55:53 PM PDT 24
Finished Jun 09 01:55:54 PM PDT 24
Peak memory 217176 kb
Host smart-dab39b0d-55ab-43dc-8831-ab7de6c6f685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222216074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2222216074
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.16420758
Short name T656
Test name
Test status
Simulation time 78843975 ps
CPU time 1.13 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 217164 kb
Host smart-c0350263-e458-40d3-93a3-bfb82fe17f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16420758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.16420758
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2588853358
Short name T890
Test name
Test status
Simulation time 467217940 ps
CPU time 2.43 seconds
Started Jun 09 12:46:57 PM PDT 24
Finished Jun 09 12:47:00 PM PDT 24
Peak memory 206372 kb
Host smart-6f3e91b9-bd7a-40d5-83ae-074b8850dc1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588853358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2588853358
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2647934866
Short name T422
Test name
Test status
Simulation time 85941036 ps
CPU time 1.28 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 216912 kb
Host smart-a920976c-72e7-4cd5-bcd9-21558e6321f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647934866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2647934866
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/100.edn_genbits.584168819
Short name T266
Test name
Test status
Simulation time 21899724 ps
CPU time 1.15 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 218124 kb
Host smart-157feb46-04d5-457a-b94b-ec5337f6d3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584168819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.584168819
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2311558925
Short name T18
Test name
Test status
Simulation time 108808624 ps
CPU time 1.33 seconds
Started Jun 09 01:54:37 PM PDT 24
Finished Jun 09 01:54:38 PM PDT 24
Peak memory 219268 kb
Host smart-ffd2280c-d182-45c7-8b70-e2e70acaea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311558925 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2311558925
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.398406823
Short name T273
Test name
Test status
Simulation time 53208982 ps
CPU time 1.4 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 218024 kb
Host smart-f4b71e4b-cac0-4f2e-8655-c349a31543bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398406823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.398406823
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/130.edn_genbits.1023295570
Short name T772
Test name
Test status
Simulation time 142785244 ps
CPU time 1.27 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 219160 kb
Host smart-f3dd50fc-a2e3-4325-ae4d-26c099cda564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023295570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1023295570
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3949141755
Short name T265
Test name
Test status
Simulation time 90713317 ps
CPU time 1.13 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 216992 kb
Host smart-ee9dba53-6830-4c97-9687-49d807e20753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949141755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3949141755
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4029879213
Short name T758
Test name
Test status
Simulation time 131122332108 ps
CPU time 769.82 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 02:07:38 PM PDT 24
Peak memory 221112 kb
Host smart-8d7a2523-1c29-4b0e-9dd0-9202d5387700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029879213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4029879213
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/212.edn_genbits.2656704986
Short name T289
Test name
Test status
Simulation time 83861860 ps
CPU time 1.66 seconds
Started Jun 09 01:56:26 PM PDT 24
Finished Jun 09 01:56:28 PM PDT 24
Peak memory 218416 kb
Host smart-867a1ab8-a426-45c5-bc94-1e7a9532179c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656704986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2656704986
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.1176084918
Short name T83
Test name
Test status
Simulation time 20572034 ps
CPU time 1.29 seconds
Started Jun 09 01:54:37 PM PDT 24
Finished Jun 09 01:54:39 PM PDT 24
Peak memory 215920 kb
Host smart-617f5294-a677-4357-afe7-460d781fddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176084918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1176084918
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/132.edn_genbits.3641733925
Short name T70
Test name
Test status
Simulation time 55908445 ps
CPU time 2.01 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:09 PM PDT 24
Peak memory 218228 kb
Host smart-5801a853-36a7-4211-8ddc-b99d5c639b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641733925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3641733925
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable.280250972
Short name T178
Test name
Test status
Simulation time 33706221 ps
CPU time 0.88 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:40 PM PDT 24
Peak memory 216160 kb
Host smart-60014256-527f-4d07-a36f-2b95574e9135
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280250972 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.280250972
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.538296786
Short name T181
Test name
Test status
Simulation time 12134517 ps
CPU time 0.91 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 216256 kb
Host smart-95c68ee9-9d1d-447c-9a66-a58b4a7861cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538296786 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.538296786
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2213795477
Short name T433
Test name
Test status
Simulation time 23827207 ps
CPU time 1.13 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 01:54:11 PM PDT 24
Peak memory 218620 kb
Host smart-61159b5b-91c7-43af-989f-7ccd8f846a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213795477 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2213795477
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1282260685
Short name T235
Test name
Test status
Simulation time 79766823 ps
CPU time 1.63 seconds
Started Jun 09 12:46:51 PM PDT 24
Finished Jun 09 12:46:53 PM PDT 24
Peak memory 206300 kb
Host smart-67c4ad68-f3bd-44ca-aed8-4d9c39a39d9e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282260685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1282260685
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2426335448
Short name T859
Test name
Test status
Simulation time 864753048 ps
CPU time 3.59 seconds
Started Jun 09 12:46:50 PM PDT 24
Finished Jun 09 12:46:54 PM PDT 24
Peak memory 206276 kb
Host smart-1a775306-7f70-44c6-b790-8d52c8b89f87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426335448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2426335448
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.45174573
Short name T223
Test name
Test status
Simulation time 16438378 ps
CPU time 0.97 seconds
Started Jun 09 12:46:51 PM PDT 24
Finished Jun 09 12:46:52 PM PDT 24
Peak memory 206228 kb
Host smart-a78dcfc9-416c-4d25-a1cf-6142c2cf8961
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45174573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.45174573
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1009548904
Short name T905
Test name
Test status
Simulation time 16534896 ps
CPU time 1.03 seconds
Started Jun 09 12:46:51 PM PDT 24
Finished Jun 09 12:46:52 PM PDT 24
Peak memory 206396 kb
Host smart-ef5613e3-789c-4067-9bae-26499b428c75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009548904 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1009548904
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2408919393
Short name T230
Test name
Test status
Simulation time 50483888 ps
CPU time 0.94 seconds
Started Jun 09 12:46:52 PM PDT 24
Finished Jun 09 12:46:53 PM PDT 24
Peak memory 206276 kb
Host smart-50bbceee-c491-412a-8c7d-edbc4da01186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408919393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2408919393
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1207738611
Short name T883
Test name
Test status
Simulation time 14000198 ps
CPU time 0.9 seconds
Started Jun 09 12:46:46 PM PDT 24
Finished Jun 09 12:46:47 PM PDT 24
Peak memory 206136 kb
Host smart-7d9c33b1-2230-46ff-aeb2-77978763e7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207738611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1207738611
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.59480093
Short name T882
Test name
Test status
Simulation time 234250430 ps
CPU time 1.44 seconds
Started Jun 09 12:46:53 PM PDT 24
Finished Jun 09 12:46:54 PM PDT 24
Peak memory 206344 kb
Host smart-0cd68901-27f1-4281-a826-cf367db351d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59480093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.59480093
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2052636619
Short name T874
Test name
Test status
Simulation time 97210367 ps
CPU time 2.05 seconds
Started Jun 09 12:46:50 PM PDT 24
Finished Jun 09 12:46:52 PM PDT 24
Peak memory 214532 kb
Host smart-38b7918b-aa2e-4710-8b03-13b4a620a513
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052636619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2052636619
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3328447734
Short name T259
Test name
Test status
Simulation time 70965981 ps
CPU time 2.12 seconds
Started Jun 09 12:46:50 PM PDT 24
Finished Jun 09 12:46:52 PM PDT 24
Peak memory 214544 kb
Host smart-970aec92-ca9e-4eed-a936-c94fb78a1ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328447734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3328447734
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1553838054
Short name T236
Test name
Test status
Simulation time 39906241 ps
CPU time 1.02 seconds
Started Jun 09 12:46:54 PM PDT 24
Finished Jun 09 12:46:56 PM PDT 24
Peak memory 206640 kb
Host smart-d8e2dbf9-4c13-4490-b904-9ba64be41199
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553838054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1553838054
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3946950064
Short name T950
Test name
Test status
Simulation time 264806498 ps
CPU time 6.47 seconds
Started Jun 09 12:46:58 PM PDT 24
Finished Jun 09 12:47:05 PM PDT 24
Peak memory 206304 kb
Host smart-4b30937d-3911-4563-8d09-3f56efafe70e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946950064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3946950064
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2955456715
Short name T861
Test name
Test status
Simulation time 25782949 ps
CPU time 0.89 seconds
Started Jun 09 12:46:56 PM PDT 24
Finished Jun 09 12:46:57 PM PDT 24
Peak memory 206276 kb
Host smart-6ec3ae8d-ac6f-465a-b89f-c6cfb17be507
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955456715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2955456715
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2150930516
Short name T922
Test name
Test status
Simulation time 150197537 ps
CPU time 2 seconds
Started Jun 09 12:46:57 PM PDT 24
Finished Jun 09 12:47:00 PM PDT 24
Peak memory 214784 kb
Host smart-85ff8f9b-79c8-403e-96b3-bcdc7cf8941d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150930516 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2150930516
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.431703006
Short name T233
Test name
Test status
Simulation time 22087927 ps
CPU time 0.87 seconds
Started Jun 09 12:46:55 PM PDT 24
Finished Jun 09 12:46:56 PM PDT 24
Peak memory 206260 kb
Host smart-8b773bc1-223f-4132-b27f-98c19b0221c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431703006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.431703006
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2817413723
Short name T924
Test name
Test status
Simulation time 26260019 ps
CPU time 0.88 seconds
Started Jun 09 12:46:58 PM PDT 24
Finished Jun 09 12:47:00 PM PDT 24
Peak memory 206216 kb
Host smart-64136680-288b-4361-b981-8dd2f335b4d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817413723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2817413723
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1340427231
Short name T946
Test name
Test status
Simulation time 39375731 ps
CPU time 1.11 seconds
Started Jun 09 12:46:59 PM PDT 24
Finished Jun 09 12:47:01 PM PDT 24
Peak memory 206272 kb
Host smart-707adb05-3e97-4606-b9f3-1d3c0d7f3f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340427231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1340427231
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1304488901
Short name T872
Test name
Test status
Simulation time 49199331 ps
CPU time 1.93 seconds
Started Jun 09 12:46:51 PM PDT 24
Finished Jun 09 12:46:53 PM PDT 24
Peak memory 214592 kb
Host smart-837563e0-9aa6-4c7c-914d-4600316b6ba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304488901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1304488901
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2598483753
Short name T889
Test name
Test status
Simulation time 98375642 ps
CPU time 1.31 seconds
Started Jun 09 12:47:20 PM PDT 24
Finished Jun 09 12:47:22 PM PDT 24
Peak memory 214664 kb
Host smart-83bce0e9-e1da-44cd-877f-5f108a90adb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598483753 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2598483753
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3319082005
Short name T229
Test name
Test status
Simulation time 11468213 ps
CPU time 0.85 seconds
Started Jun 09 12:47:16 PM PDT 24
Finished Jun 09 12:47:17 PM PDT 24
Peak memory 206276 kb
Host smart-872cfd55-0155-4aa1-82d2-344e30caa23f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319082005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3319082005
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.2145258472
Short name T877
Test name
Test status
Simulation time 26979632 ps
CPU time 0.91 seconds
Started Jun 09 12:47:14 PM PDT 24
Finished Jun 09 12:47:15 PM PDT 24
Peak memory 206216 kb
Host smart-7fa19155-3955-4069-9c83-ca2bfd084013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145258472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.2145258472
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.394102994
Short name T238
Test name
Test status
Simulation time 40719250 ps
CPU time 0.92 seconds
Started Jun 09 12:47:20 PM PDT 24
Finished Jun 09 12:47:22 PM PDT 24
Peak memory 206336 kb
Host smart-279c5610-eff4-42ff-9132-23e56ad1a160
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394102994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.394102994
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2856416687
Short name T858
Test name
Test status
Simulation time 87030725 ps
CPU time 1.85 seconds
Started Jun 09 12:47:19 PM PDT 24
Finished Jun 09 12:47:21 PM PDT 24
Peak memory 214536 kb
Host smart-c60ce0b0-dfa1-4276-a173-8f543006f7dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856416687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2856416687
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.145317049
Short name T919
Test name
Test status
Simulation time 44084326 ps
CPU time 1.66 seconds
Started Jun 09 12:47:18 PM PDT 24
Finished Jun 09 12:47:19 PM PDT 24
Peak memory 206324 kb
Host smart-49d121ae-c52b-4bc4-83f5-689173c2aa38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145317049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.145317049
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.689721932
Short name T854
Test name
Test status
Simulation time 18085899 ps
CPU time 1.09 seconds
Started Jun 09 12:47:24 PM PDT 24
Finished Jun 09 12:47:26 PM PDT 24
Peak memory 206540 kb
Host smart-bd8c5f9c-de89-4dc7-a72c-7ff23bba2187
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689721932 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.689721932
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1717586253
Short name T901
Test name
Test status
Simulation time 67037371 ps
CPU time 0.92 seconds
Started Jun 09 12:47:22 PM PDT 24
Finished Jun 09 12:47:23 PM PDT 24
Peak memory 206272 kb
Host smart-57f79a27-254f-40ef-97fa-ec7e9350b685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717586253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1717586253
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.905731293
Short name T928
Test name
Test status
Simulation time 60063996 ps
CPU time 0.88 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 205948 kb
Host smart-471b55cf-8c8c-41cb-8db3-ddbcb8fac8ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905731293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.905731293
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3818029497
Short name T914
Test name
Test status
Simulation time 17401139 ps
CPU time 1.16 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206272 kb
Host smart-6f661616-5134-43c4-aa92-b9c524a8cc0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818029497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3818029497
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3312263959
Short name T913
Test name
Test status
Simulation time 63228678 ps
CPU time 2.18 seconds
Started Jun 09 12:47:19 PM PDT 24
Finished Jun 09 12:47:22 PM PDT 24
Peak memory 214536 kb
Host smart-83d91e48-2afe-4d35-8d51-baae40c2c579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312263959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3312263959
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.610575626
Short name T948
Test name
Test status
Simulation time 318564539 ps
CPU time 2.05 seconds
Started Jun 09 12:47:24 PM PDT 24
Finished Jun 09 12:47:26 PM PDT 24
Peak memory 206332 kb
Host smart-d192703f-aa8e-48b5-bc82-3cbe7c0e30ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610575626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.610575626
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1585992771
Short name T887
Test name
Test status
Simulation time 17416627 ps
CPU time 1.03 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 206412 kb
Host smart-f5ebfa45-11d6-4409-b124-21dfa066f79a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585992771 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1585992771
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3545643522
Short name T862
Test name
Test status
Simulation time 17466618 ps
CPU time 0.87 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206208 kb
Host smart-608bc9a4-d8c2-48b4-9510-62c99817cbe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545643522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3545643522
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.245090779
Short name T879
Test name
Test status
Simulation time 72502262 ps
CPU time 1.1 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:25 PM PDT 24
Peak memory 206344 kb
Host smart-e20c81b3-5132-4982-89b1-7b346c3dbe80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245090779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.245090779
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.875926208
Short name T972
Test name
Test status
Simulation time 76109803 ps
CPU time 3.04 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:32 PM PDT 24
Peak memory 214592 kb
Host smart-2c99145b-1f2b-4370-a7bc-7933d5d5cd89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875926208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.875926208
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1426830990
Short name T949
Test name
Test status
Simulation time 800061593 ps
CPU time 2.28 seconds
Started Jun 09 12:47:24 PM PDT 24
Finished Jun 09 12:47:26 PM PDT 24
Peak memory 206392 kb
Host smart-592714a5-22c8-4fbc-be03-e8f2aa9b2729
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426830990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1426830990
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2388983861
Short name T930
Test name
Test status
Simulation time 21423852 ps
CPU time 1.19 seconds
Started Jun 09 12:47:25 PM PDT 24
Finished Jun 09 12:47:26 PM PDT 24
Peak memory 214652 kb
Host smart-466f4619-2c83-47af-93cd-7c54f8f182bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388983861 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2388983861
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.855544026
Short name T848
Test name
Test status
Simulation time 116558132 ps
CPU time 0.84 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:25 PM PDT 24
Peak memory 205956 kb
Host smart-292f5257-cd0b-4abf-9ce5-27220d432577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855544026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.855544026
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.583840739
Short name T871
Test name
Test status
Simulation time 37462490 ps
CPU time 0.84 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 205984 kb
Host smart-77bfa764-ca77-40b2-80ab-88484bbcd7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583840739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.583840739
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2068735323
Short name T965
Test name
Test status
Simulation time 38991884 ps
CPU time 1.15 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206472 kb
Host smart-42bfd1f6-78a1-4a2f-965a-6ac65c48c3fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068735323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2068735323
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1112214279
Short name T926
Test name
Test status
Simulation time 88880499 ps
CPU time 1.75 seconds
Started Jun 09 12:47:24 PM PDT 24
Finished Jun 09 12:47:26 PM PDT 24
Peak memory 214596 kb
Host smart-1d8987ca-d34f-4285-8846-5338f257a1be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112214279 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1112214279
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1896867132
Short name T260
Test name
Test status
Simulation time 49845464 ps
CPU time 1.77 seconds
Started Jun 09 12:47:22 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 214536 kb
Host smart-db9a9144-b046-4bdb-a638-b615db488fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896867132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1896867132
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2013366417
Short name T954
Test name
Test status
Simulation time 67280180 ps
CPU time 1.26 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 214680 kb
Host smart-880eaf90-1797-43ea-b9f7-95f5695e90d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013366417 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2013366417
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1861415780
Short name T220
Test name
Test status
Simulation time 63965375 ps
CPU time 0.9 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206284 kb
Host smart-00ae9873-ec5d-4d74-90e3-13260001ed8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861415780 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1861415780
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.4095885148
Short name T843
Test name
Test status
Simulation time 16081574 ps
CPU time 0.93 seconds
Started Jun 09 12:47:23 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206356 kb
Host smart-3dde3aca-8984-4f47-9392-4e801ea1359d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095885148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4095885148
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2864392659
Short name T903
Test name
Test status
Simulation time 68920727 ps
CPU time 1.48 seconds
Started Jun 09 12:47:29 PM PDT 24
Finished Jun 09 12:47:31 PM PDT 24
Peak memory 206344 kb
Host smart-b1f9fe0d-f44f-4329-b3da-1cbf630a609e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864392659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2864392659
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.4187312558
Short name T902
Test name
Test status
Simulation time 43207699 ps
CPU time 2.92 seconds
Started Jun 09 12:47:24 PM PDT 24
Finished Jun 09 12:47:28 PM PDT 24
Peak memory 214596 kb
Host smart-ae77983e-6718-478b-a29c-3ec4bd0dfa20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187312558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.4187312558
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2662351661
Short name T962
Test name
Test status
Simulation time 415738162 ps
CPU time 1.67 seconds
Started Jun 09 12:47:22 PM PDT 24
Finished Jun 09 12:47:24 PM PDT 24
Peak memory 206320 kb
Host smart-61162302-8344-4745-aac0-7cdd17485f88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662351661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2662351661
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4149768170
Short name T937
Test name
Test status
Simulation time 19307579 ps
CPU time 1.08 seconds
Started Jun 09 12:47:29 PM PDT 24
Finished Jun 09 12:47:31 PM PDT 24
Peak memory 206348 kb
Host smart-a7b4ea71-0dda-4cb8-a89a-0f7675ce568d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149768170 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4149768170
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1883223114
Short name T911
Test name
Test status
Simulation time 27328267 ps
CPU time 0.98 seconds
Started Jun 09 12:47:29 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 206256 kb
Host smart-9fdcdb83-836d-4e22-9c69-abced672eaaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883223114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1883223114
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.13291758
Short name T907
Test name
Test status
Simulation time 65344246 ps
CPU time 0.81 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:27 PM PDT 24
Peak memory 206212 kb
Host smart-f55c2563-74c7-4e81-b6d5-a43e9396c744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291758 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.13291758
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2647992760
Short name T959
Test name
Test status
Simulation time 36624143 ps
CPU time 1.15 seconds
Started Jun 09 12:47:27 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 206344 kb
Host smart-d5191d5d-b63c-4682-89b4-948f10c57a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647992760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2647992760
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.156217748
Short name T904
Test name
Test status
Simulation time 159407244 ps
CPU time 2.82 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 214600 kb
Host smart-b37efe2d-f1e9-4036-9f37-63deba240bc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156217748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.156217748
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.894345564
Short name T945
Test name
Test status
Simulation time 188660607 ps
CPU time 1.69 seconds
Started Jun 09 12:47:27 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 214532 kb
Host smart-087abe65-c79b-47a9-adaa-4b796b79e5e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894345564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.894345564
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2639818950
Short name T844
Test name
Test status
Simulation time 33368237 ps
CPU time 1.36 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:35 PM PDT 24
Peak memory 214672 kb
Host smart-d176532d-214f-4102-a3e5-97f6ef03b369
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639818950 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2639818950
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.921696520
Short name T221
Test name
Test status
Simulation time 12077624 ps
CPU time 0.9 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 206256 kb
Host smart-d4334644-79e8-4ebe-81aa-9ee4867c7687
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921696520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.921696520
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.232441446
Short name T944
Test name
Test status
Simulation time 93127872 ps
CPU time 0.87 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 206204 kb
Host smart-d8396d80-4fbf-493c-b997-95f3685af75c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232441446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.232441446
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.802932706
Short name T219
Test name
Test status
Simulation time 57926536 ps
CPU time 1.42 seconds
Started Jun 09 12:47:28 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 206324 kb
Host smart-2d636237-0154-4b81-99fb-098cd498f67e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802932706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_ou
tstanding.802932706
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1369422379
Short name T875
Test name
Test status
Simulation time 213469874 ps
CPU time 1.96 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:28 PM PDT 24
Peak memory 214536 kb
Host smart-7978000e-3e15-4571-b67b-f81c972d0bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369422379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1369422379
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.3967300591
Short name T253
Test name
Test status
Simulation time 255676422 ps
CPU time 2.22 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:28 PM PDT 24
Peak memory 206340 kb
Host smart-0c64dad9-c2f4-46b5-abfb-bdd725be915c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967300591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.3967300591
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3775070183
Short name T864
Test name
Test status
Simulation time 40209265 ps
CPU time 1.38 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:28 PM PDT 24
Peak memory 217792 kb
Host smart-5e93eb12-0038-45b6-b0f1-d8709c8f8e13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775070183 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3775070183
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.992404401
Short name T867
Test name
Test status
Simulation time 34819325 ps
CPU time 0.98 seconds
Started Jun 09 12:47:27 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 206184 kb
Host smart-88bada4e-2bfe-41da-8471-3381755d46cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992404401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.992404401
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2214673794
Short name T894
Test name
Test status
Simulation time 30064026 ps
CPU time 0.81 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 206000 kb
Host smart-6c215d19-c5ed-4949-a6f5-9fb24efbc231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214673794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2214673794
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1800614482
Short name T224
Test name
Test status
Simulation time 78707012 ps
CPU time 1.43 seconds
Started Jun 09 12:47:32 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206344 kb
Host smart-9019a86e-6a64-4055-b9b9-32c4a0aec871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800614482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1800614482
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.1364968922
Short name T927
Test name
Test status
Simulation time 32511745 ps
CPU time 2.34 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 214596 kb
Host smart-c9bb46d8-31ff-4178-b4f0-457f757b7848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364968922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.1364968922
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3495001700
Short name T955
Test name
Test status
Simulation time 329414519 ps
CPU time 2.98 seconds
Started Jun 09 12:47:25 PM PDT 24
Finished Jun 09 12:47:29 PM PDT 24
Peak memory 214648 kb
Host smart-292a0973-43f4-4ff6-a5fa-76b199da7386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495001700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3495001700
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.751681844
Short name T942
Test name
Test status
Simulation time 26378456 ps
CPU time 1.33 seconds
Started Jun 09 12:47:26 PM PDT 24
Finished Jun 09 12:47:28 PM PDT 24
Peak memory 214624 kb
Host smart-6cb478cd-bca2-4ca9-9f16-a4cf992d5c94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751681844 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.751681844
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2994469892
Short name T851
Test name
Test status
Simulation time 40832976 ps
CPU time 0.84 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:35 PM PDT 24
Peak memory 206064 kb
Host smart-5e2a132c-03d0-450d-b1cc-5b86fe2e5363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994469892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2994469892
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2143309983
Short name T923
Test name
Test status
Simulation time 20764708 ps
CPU time 0.87 seconds
Started Jun 09 12:47:29 PM PDT 24
Finished Jun 09 12:47:30 PM PDT 24
Peak memory 206000 kb
Host smart-d2981296-bd88-4620-be0f-46d53bbac4f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143309983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2143309983
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.1330305411
Short name T956
Test name
Test status
Simulation time 24133284 ps
CPU time 1.22 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:35 PM PDT 24
Peak memory 206428 kb
Host smart-30433e46-487b-4387-b337-982a4241524a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330305411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.1330305411
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2802653746
Short name T868
Test name
Test status
Simulation time 148595814 ps
CPU time 3.12 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 218888 kb
Host smart-d46b429d-ed45-4b7d-835c-01ba4fd261c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802653746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2802653746
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2740322005
Short name T251
Test name
Test status
Simulation time 179036431 ps
CPU time 2.61 seconds
Started Jun 09 12:47:30 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 214916 kb
Host smart-53cdeaee-be8f-4b0a-bf4f-30b0326f5311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740322005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2740322005
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3120033611
Short name T933
Test name
Test status
Simulation time 36230535 ps
CPU time 1.47 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 222820 kb
Host smart-2d4ab104-c7db-4eb7-9d4a-de7e86730580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120033611 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3120033611
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2136741159
Short name T885
Test name
Test status
Simulation time 45505685 ps
CPU time 0.89 seconds
Started Jun 09 12:47:31 PM PDT 24
Finished Jun 09 12:47:32 PM PDT 24
Peak memory 206272 kb
Host smart-804f4c68-ebe1-4f27-b1c1-39cca3933b54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136741159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2136741159
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.1568579399
Short name T869
Test name
Test status
Simulation time 53020622 ps
CPU time 0.93 seconds
Started Jun 09 12:47:32 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206188 kb
Host smart-4f23891c-7412-46a5-93e0-2b19f7521c38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568579399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1568579399
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1564416677
Short name T951
Test name
Test status
Simulation time 19988320 ps
CPU time 1.14 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 206316 kb
Host smart-b461da6d-9752-41ec-a93c-dcc1afa637b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564416677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1564416677
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.785122795
Short name T847
Test name
Test status
Simulation time 111631974 ps
CPU time 3.87 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 214788 kb
Host smart-b072b21f-cbce-476f-b4ec-48bdc350463f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785122795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.785122795
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1639049714
Short name T252
Test name
Test status
Simulation time 91261121 ps
CPU time 2.44 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 206340 kb
Host smart-734be62e-41fb-41e5-8759-251ad8c3de9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639049714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1639049714
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1478159180
Short name T227
Test name
Test status
Simulation time 136614418 ps
CPU time 1.56 seconds
Started Jun 09 12:47:01 PM PDT 24
Finished Jun 09 12:47:03 PM PDT 24
Peak memory 206244 kb
Host smart-693b59fb-7348-41fe-aa48-9470c8041cb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478159180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1478159180
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1841799538
Short name T932
Test name
Test status
Simulation time 1004579426 ps
CPU time 6.91 seconds
Started Jun 09 12:47:02 PM PDT 24
Finished Jun 09 12:47:09 PM PDT 24
Peak memory 206208 kb
Host smart-9f0e444b-7a44-4d79-918e-7742c22c2eb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841799538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1841799538
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2972355296
Short name T226
Test name
Test status
Simulation time 69740539 ps
CPU time 1.02 seconds
Started Jun 09 12:47:02 PM PDT 24
Finished Jun 09 12:47:03 PM PDT 24
Peak memory 206276 kb
Host smart-5dc9226c-ee91-4400-be01-eb43435d99ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972355296 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2972355296
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.4067097309
Short name T909
Test name
Test status
Simulation time 88550729 ps
CPU time 1.27 seconds
Started Jun 09 12:47:01 PM PDT 24
Finished Jun 09 12:47:02 PM PDT 24
Peak memory 214576 kb
Host smart-5a2f067b-1a4e-46d1-acdc-3e01c3cf3cfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067097309 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.4067097309
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3733645982
Short name T232
Test name
Test status
Simulation time 43779640 ps
CPU time 0.87 seconds
Started Jun 09 12:47:01 PM PDT 24
Finished Jun 09 12:47:02 PM PDT 24
Peak memory 206188 kb
Host smart-0725cd6a-1603-4112-8bc8-72d650a64005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733645982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3733645982
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4059849028
Short name T856
Test name
Test status
Simulation time 19277595 ps
CPU time 0.87 seconds
Started Jun 09 12:47:03 PM PDT 24
Finished Jun 09 12:47:04 PM PDT 24
Peak memory 206208 kb
Host smart-f9102b6c-bd5e-4139-94b6-3abef2d6e658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059849028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4059849028
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2120529955
Short name T891
Test name
Test status
Simulation time 18327742 ps
CPU time 1.18 seconds
Started Jun 09 12:47:01 PM PDT 24
Finished Jun 09 12:47:02 PM PDT 24
Peak memory 206500 kb
Host smart-cfbc70ef-282a-4b52-9974-2aa1ebc22086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120529955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2120529955
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2778355451
Short name T873
Test name
Test status
Simulation time 487669328 ps
CPU time 3.99 seconds
Started Jun 09 12:46:57 PM PDT 24
Finished Jun 09 12:47:01 PM PDT 24
Peak memory 214596 kb
Host smart-48f673c3-8be1-46ae-9eae-21cd9c1e04ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778355451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2778355451
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3229460841
Short name T941
Test name
Test status
Simulation time 134922011 ps
CPU time 1.65 seconds
Started Jun 09 12:47:02 PM PDT 24
Finished Jun 09 12:47:05 PM PDT 24
Peak memory 206436 kb
Host smart-c2435d1b-16a5-4b9e-a69d-6f96e33b31f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229460841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3229460841
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2786049788
Short name T845
Test name
Test status
Simulation time 15519557 ps
CPU time 0.92 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 206136 kb
Host smart-04251881-ceea-4441-ac26-bfc914b9bc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786049788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2786049788
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.561665647
Short name T920
Test name
Test status
Simulation time 18799921 ps
CPU time 0.81 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 205948 kb
Host smart-2f56cdf5-b0da-4e10-987f-4c571ba1e2ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561665647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.561665647
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1706132016
Short name T884
Test name
Test status
Simulation time 15663366 ps
CPU time 0.98 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 206208 kb
Host smart-9fd29c8c-2d7f-443a-ba37-d4acc41e6a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706132016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1706132016
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1210891115
Short name T969
Test name
Test status
Simulation time 112841023 ps
CPU time 0.89 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 205996 kb
Host smart-cfac0334-161a-4ccc-9347-36e5ceafd380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210891115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1210891115
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.627349790
Short name T917
Test name
Test status
Simulation time 16011056 ps
CPU time 0.91 seconds
Started Jun 09 12:47:30 PM PDT 24
Finished Jun 09 12:47:32 PM PDT 24
Peak memory 206144 kb
Host smart-2a95a970-a31d-42b1-880a-395e00d79b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627349790 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.627349790
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1167358355
Short name T897
Test name
Test status
Simulation time 14300695 ps
CPU time 0.86 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 206328 kb
Host smart-b192345b-5f81-4c48-81f8-ff06878e957d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167358355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1167358355
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2761765372
Short name T918
Test name
Test status
Simulation time 13607374 ps
CPU time 0.9 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 206212 kb
Host smart-2d65cf34-9482-45d0-8c8b-19201bf70814
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761765372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2761765372
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.663061487
Short name T929
Test name
Test status
Simulation time 22334928 ps
CPU time 0.9 seconds
Started Jun 09 12:47:32 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206184 kb
Host smart-113cab9a-9226-42d6-8ec4-d658ff90776e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663061487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.663061487
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1804209773
Short name T846
Test name
Test status
Simulation time 15956021 ps
CPU time 0.95 seconds
Started Jun 09 12:47:33 PM PDT 24
Finished Jun 09 12:47:34 PM PDT 24
Peak memory 206356 kb
Host smart-9bdcc060-6e23-4b3a-ba56-7ac5d317372e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804209773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1804209773
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2520641435
Short name T952
Test name
Test status
Simulation time 17690282 ps
CPU time 0.84 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 206176 kb
Host smart-8437b18a-8edf-418f-87a3-b18a6df602ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520641435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2520641435
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4042197542
Short name T939
Test name
Test status
Simulation time 62185342 ps
CPU time 1.57 seconds
Started Jun 09 12:47:06 PM PDT 24
Finished Jun 09 12:47:08 PM PDT 24
Peak memory 206276 kb
Host smart-6a28dd6e-5c5e-4eb8-b3f5-50673b8c3da5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042197542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4042197542
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3139576555
Short name T961
Test name
Test status
Simulation time 529647736 ps
CPU time 3.58 seconds
Started Jun 09 12:47:07 PM PDT 24
Finished Jun 09 12:47:11 PM PDT 24
Peak memory 206380 kb
Host smart-7248de53-46a6-4c7b-a7cf-7bcc955eb475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139576555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3139576555
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2220916540
Short name T970
Test name
Test status
Simulation time 42977714 ps
CPU time 0.88 seconds
Started Jun 09 12:47:06 PM PDT 24
Finished Jun 09 12:47:07 PM PDT 24
Peak memory 206064 kb
Host smart-0de6a24a-0213-4616-92b8-76f7e79b7e8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220916540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2220916540
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.208535921
Short name T900
Test name
Test status
Simulation time 32630975 ps
CPU time 1.21 seconds
Started Jun 09 12:47:07 PM PDT 24
Finished Jun 09 12:47:09 PM PDT 24
Peak memory 214564 kb
Host smart-0623d8be-5134-4098-ab45-b71ec8e4b529
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208535921 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.208535921
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3560936289
Short name T964
Test name
Test status
Simulation time 62488746 ps
CPU time 0.91 seconds
Started Jun 09 12:47:04 PM PDT 24
Finished Jun 09 12:47:06 PM PDT 24
Peak memory 206232 kb
Host smart-e233356d-68cd-4daa-942e-cd0459f8766c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560936289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3560936289
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3075168722
Short name T957
Test name
Test status
Simulation time 42652186 ps
CPU time 0.85 seconds
Started Jun 09 12:47:02 PM PDT 24
Finished Jun 09 12:47:04 PM PDT 24
Peak memory 206000 kb
Host smart-8e6403f9-5fa3-440e-be0b-5e645c495f91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075168722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3075168722
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.101609687
Short name T925
Test name
Test status
Simulation time 19266394 ps
CPU time 1.1 seconds
Started Jun 09 12:47:05 PM PDT 24
Finished Jun 09 12:47:07 PM PDT 24
Peak memory 206348 kb
Host smart-836b4e01-b05d-48b6-a911-6ef6c62c7faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101609687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.101609687
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3015099042
Short name T849
Test name
Test status
Simulation time 425455985 ps
CPU time 4.19 seconds
Started Jun 09 12:47:02 PM PDT 24
Finished Jun 09 12:47:06 PM PDT 24
Peak memory 214660 kb
Host smart-39420601-3127-4750-a003-f9bb95e70670
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015099042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3015099042
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2286661266
Short name T921
Test name
Test status
Simulation time 711605262 ps
CPU time 1.87 seconds
Started Jun 09 12:47:00 PM PDT 24
Finished Jun 09 12:47:03 PM PDT 24
Peak memory 214692 kb
Host smart-6ac07dd5-d69d-4a54-a182-ad9bc33969b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286661266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2286661266
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.1461197846
Short name T876
Test name
Test status
Simulation time 56704937 ps
CPU time 0.85 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:36 PM PDT 24
Peak memory 205996 kb
Host smart-6c762733-fb58-44d2-a0bf-2d36d4c0be97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461197846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1461197846
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1337517985
Short name T866
Test name
Test status
Simulation time 49655819 ps
CPU time 0.85 seconds
Started Jun 09 12:47:31 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206168 kb
Host smart-d774d381-7fa8-49ac-9958-231b2a6eea71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337517985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1337517985
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2959721747
Short name T886
Test name
Test status
Simulation time 157677815 ps
CPU time 0.97 seconds
Started Jun 09 12:47:32 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206204 kb
Host smart-12655c68-d4e9-4190-be8c-bdce19f58ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959721747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2959721747
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3007979533
Short name T893
Test name
Test status
Simulation time 22690974 ps
CPU time 0.83 seconds
Started Jun 09 12:47:31 PM PDT 24
Finished Jun 09 12:47:32 PM PDT 24
Peak memory 206208 kb
Host smart-6869bdca-4f05-4377-b5f4-7c0a9006c560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007979533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3007979533
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.231392275
Short name T896
Test name
Test status
Simulation time 12185593 ps
CPU time 0.86 seconds
Started Jun 09 12:47:31 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206468 kb
Host smart-8efc93a8-2151-4d02-9ac4-a521ea46c1bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231392275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.231392275
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1805451477
Short name T855
Test name
Test status
Simulation time 15587806 ps
CPU time 0.92 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 206324 kb
Host smart-e0080503-b88a-449f-9954-9a2b438b3566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805451477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1805451477
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1415352500
Short name T940
Test name
Test status
Simulation time 156673302 ps
CPU time 0.96 seconds
Started Jun 09 12:47:32 PM PDT 24
Finished Jun 09 12:47:33 PM PDT 24
Peak memory 206472 kb
Host smart-f16b2583-9b23-42cd-bd46-ddef339d075b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415352500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1415352500
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.295158141
Short name T960
Test name
Test status
Simulation time 12337125 ps
CPU time 0.9 seconds
Started Jun 09 12:47:35 PM PDT 24
Finished Jun 09 12:47:37 PM PDT 24
Peak memory 206196 kb
Host smart-a18cb616-83e9-4034-a580-759fc4219693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295158141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.295158141
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.921048387
Short name T850
Test name
Test status
Simulation time 41769809 ps
CPU time 0.86 seconds
Started Jun 09 12:47:34 PM PDT 24
Finished Jun 09 12:47:35 PM PDT 24
Peak memory 206216 kb
Host smart-eb39348a-9621-4283-ab77-c903a8474b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921048387 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.921048387
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1944722614
Short name T910
Test name
Test status
Simulation time 47144732 ps
CPU time 0.84 seconds
Started Jun 09 12:47:30 PM PDT 24
Finished Jun 09 12:47:31 PM PDT 24
Peak memory 206200 kb
Host smart-b21e295a-ffb1-437c-a5f9-7901c67a9c6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944722614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1944722614
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2224109602
Short name T228
Test name
Test status
Simulation time 36483630 ps
CPU time 1.32 seconds
Started Jun 09 12:47:11 PM PDT 24
Finished Jun 09 12:47:13 PM PDT 24
Peak memory 206276 kb
Host smart-77b14c51-69d5-4b8e-8d5e-5b736b45d812
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224109602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2224109602
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.998529314
Short name T234
Test name
Test status
Simulation time 291816875 ps
CPU time 6.16 seconds
Started Jun 09 12:47:14 PM PDT 24
Finished Jun 09 12:47:21 PM PDT 24
Peak memory 206272 kb
Host smart-86d1bfda-9986-47ea-9a6a-7c16dcb630cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998529314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.998529314
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3910736564
Short name T908
Test name
Test status
Simulation time 30031335 ps
CPU time 0.89 seconds
Started Jun 09 12:47:04 PM PDT 24
Finished Jun 09 12:47:05 PM PDT 24
Peak memory 206272 kb
Host smart-ada8672a-ac9c-4a31-9cad-c8208460f19c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910736564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3910736564
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.406028731
Short name T958
Test name
Test status
Simulation time 22550089 ps
CPU time 1.24 seconds
Started Jun 09 12:47:09 PM PDT 24
Finished Jun 09 12:47:11 PM PDT 24
Peak memory 216440 kb
Host smart-6f63b6a3-c441-4ae8-ad0a-bae595dcb178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406028731 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.406028731
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3322532383
Short name T240
Test name
Test status
Simulation time 15314753 ps
CPU time 0.86 seconds
Started Jun 09 12:47:05 PM PDT 24
Finished Jun 09 12:47:07 PM PDT 24
Peak memory 206272 kb
Host smart-c0304b89-bd93-47ce-96bd-e9b588da9d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322532383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3322532383
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2171521202
Short name T870
Test name
Test status
Simulation time 43212966 ps
CPU time 0.83 seconds
Started Jun 09 12:47:07 PM PDT 24
Finished Jun 09 12:47:08 PM PDT 24
Peak memory 206208 kb
Host smart-781629c1-83a2-41fd-85a4-33a91e1fcbc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171521202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2171521202
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.312909540
Short name T880
Test name
Test status
Simulation time 32967969 ps
CPU time 1.1 seconds
Started Jun 09 12:47:13 PM PDT 24
Finished Jun 09 12:47:14 PM PDT 24
Peak memory 206336 kb
Host smart-a6812223-0d1d-42d6-8c77-679be6d0c2e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312909540 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.312909540
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3319942813
Short name T898
Test name
Test status
Simulation time 84800075 ps
CPU time 3.03 seconds
Started Jun 09 12:47:05 PM PDT 24
Finished Jun 09 12:47:09 PM PDT 24
Peak memory 218700 kb
Host smart-7627e401-ab6f-4237-a083-8b65035cf11a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319942813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3319942813
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1711952884
Short name T257
Test name
Test status
Simulation time 43755426 ps
CPU time 1.5 seconds
Started Jun 09 12:47:10 PM PDT 24
Finished Jun 09 12:47:12 PM PDT 24
Peak memory 206676 kb
Host smart-c0bcd6a7-2256-4d22-96a5-f117ef4a1685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711952884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1711952884
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3826480899
Short name T857
Test name
Test status
Simulation time 66709543 ps
CPU time 0.92 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 206280 kb
Host smart-a424f5bf-7d96-429f-b496-e4693b38fbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826480899 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3826480899
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1237190076
Short name T841
Test name
Test status
Simulation time 46245242 ps
CPU time 0.87 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206204 kb
Host smart-ea4fe5cb-4f49-4c20-95da-d24e49568c0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237190076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1237190076
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2480933988
Short name T967
Test name
Test status
Simulation time 40198421 ps
CPU time 0.9 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206144 kb
Host smart-7160c46a-5157-4243-a98b-90c42e2e5207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480933988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2480933988
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1135783378
Short name T916
Test name
Test status
Simulation time 23576660 ps
CPU time 0.86 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206204 kb
Host smart-310495aa-fa49-432d-81ad-6620a8a18d99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135783378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1135783378
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3616469514
Short name T953
Test name
Test status
Simulation time 21128863 ps
CPU time 0.86 seconds
Started Jun 09 12:47:40 PM PDT 24
Finished Jun 09 12:47:41 PM PDT 24
Peak memory 206120 kb
Host smart-4a0b15c1-a821-413c-9de4-6e953f990420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616469514 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3616469514
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4136595309
Short name T863
Test name
Test status
Simulation time 24047045 ps
CPU time 0.92 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206204 kb
Host smart-1e16d1f3-329b-4a23-91d1-33d6213d2194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136595309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4136595309
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1650903274
Short name T860
Test name
Test status
Simulation time 12848629 ps
CPU time 0.91 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 206140 kb
Host smart-8cb3c7d8-abc8-4447-932a-e472665b2dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650903274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1650903274
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2102399613
Short name T878
Test name
Test status
Simulation time 27989819 ps
CPU time 0.89 seconds
Started Jun 09 12:47:37 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206160 kb
Host smart-583201ab-adab-444f-a9a8-82847e74e4ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102399613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2102399613
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3763444699
Short name T912
Test name
Test status
Simulation time 39487844 ps
CPU time 0.85 seconds
Started Jun 09 12:47:39 PM PDT 24
Finished Jun 09 12:47:40 PM PDT 24
Peak memory 205984 kb
Host smart-2b5e2141-1bf1-4bea-94d2-1cc98989358b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763444699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3763444699
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2678072614
Short name T935
Test name
Test status
Simulation time 14029800 ps
CPU time 0.92 seconds
Started Jun 09 12:47:38 PM PDT 24
Finished Jun 09 12:47:39 PM PDT 24
Peak memory 206204 kb
Host smart-4ac63906-111f-48f0-a09b-09cd3458cda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678072614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2678072614
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1860766299
Short name T865
Test name
Test status
Simulation time 22547521 ps
CPU time 1.39 seconds
Started Jun 09 12:47:09 PM PDT 24
Finished Jun 09 12:47:11 PM PDT 24
Peak memory 214624 kb
Host smart-520df8f5-86fd-498a-b28f-88a38829fbfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860766299 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1860766299
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1646865635
Short name T915
Test name
Test status
Simulation time 32926311 ps
CPU time 0.85 seconds
Started Jun 09 12:47:11 PM PDT 24
Finished Jun 09 12:47:12 PM PDT 24
Peak memory 206244 kb
Host smart-464781c2-5ec6-431a-8319-ea76a96bd590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646865635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1646865635
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3693453004
Short name T971
Test name
Test status
Simulation time 39125146 ps
CPU time 0.91 seconds
Started Jun 09 12:47:12 PM PDT 24
Finished Jun 09 12:47:13 PM PDT 24
Peak memory 206192 kb
Host smart-3203a22c-2a7a-4ac0-b3ca-eb746de3ec4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693453004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3693453004
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1303030625
Short name T239
Test name
Test status
Simulation time 43679720 ps
CPU time 0.94 seconds
Started Jun 09 12:47:10 PM PDT 24
Finished Jun 09 12:47:11 PM PDT 24
Peak memory 206336 kb
Host smart-cf4a9893-0665-419f-b492-74bb2328b09b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303030625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1303030625
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4152769082
Short name T881
Test name
Test status
Simulation time 101339416 ps
CPU time 1.91 seconds
Started Jun 09 12:47:10 PM PDT 24
Finished Jun 09 12:47:12 PM PDT 24
Peak memory 214640 kb
Host smart-995c53ae-5d82-4357-a7cf-e36c3772c855
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152769082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4152769082
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2328109771
Short name T931
Test name
Test status
Simulation time 92390164 ps
CPU time 1.61 seconds
Started Jun 09 12:47:09 PM PDT 24
Finished Jun 09 12:47:11 PM PDT 24
Peak memory 206592 kb
Host smart-a17abd07-ae27-4feb-9d01-d72eb9e7af81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328109771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2328109771
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3494858443
Short name T888
Test name
Test status
Simulation time 44951359 ps
CPU time 1.49 seconds
Started Jun 09 12:47:10 PM PDT 24
Finished Jun 09 12:47:12 PM PDT 24
Peak memory 217788 kb
Host smart-c023001b-be2b-411a-8b98-3ed292df875e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494858443 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3494858443
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2115138770
Short name T231
Test name
Test status
Simulation time 23958410 ps
CPU time 0.88 seconds
Started Jun 09 12:47:11 PM PDT 24
Finished Jun 09 12:47:12 PM PDT 24
Peak memory 206244 kb
Host smart-ad211b6b-8e2d-41d5-9ba1-b4f2a85e38a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115138770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2115138770
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3478698237
Short name T938
Test name
Test status
Simulation time 15535488 ps
CPU time 1.02 seconds
Started Jun 09 12:47:13 PM PDT 24
Finished Jun 09 12:47:15 PM PDT 24
Peak memory 206204 kb
Host smart-14f17c08-262c-4ccd-a785-b313e081091d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478698237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3478698237
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.4064789001
Short name T237
Test name
Test status
Simulation time 18525176 ps
CPU time 1.19 seconds
Started Jun 09 12:47:12 PM PDT 24
Finished Jun 09 12:47:13 PM PDT 24
Peak memory 206332 kb
Host smart-2e8e757e-6fe6-44c0-8c88-e1720efec273
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064789001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.4064789001
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.3556601948
Short name T943
Test name
Test status
Simulation time 208142773 ps
CPU time 3.63 seconds
Started Jun 09 12:47:11 PM PDT 24
Finished Jun 09 12:47:15 PM PDT 24
Peak memory 214600 kb
Host smart-fe887620-8ca1-48e9-88ea-88895dd06801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556601948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.3556601948
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.824722319
Short name T906
Test name
Test status
Simulation time 89013961 ps
CPU time 2.18 seconds
Started Jun 09 12:47:10 PM PDT 24
Finished Jun 09 12:47:13 PM PDT 24
Peak memory 206368 kb
Host smart-f8cfcf45-99b7-40ce-a9df-3f2a781a6e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824722319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.824722319
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2320577038
Short name T895
Test name
Test status
Simulation time 20560142 ps
CPU time 1.13 seconds
Started Jun 09 12:47:16 PM PDT 24
Finished Jun 09 12:47:17 PM PDT 24
Peak memory 214604 kb
Host smart-824bf012-42b2-40f9-b740-3c6f8c565d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320577038 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2320577038
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1999111906
Short name T936
Test name
Test status
Simulation time 24011481 ps
CPU time 0.91 seconds
Started Jun 09 12:47:15 PM PDT 24
Finished Jun 09 12:47:16 PM PDT 24
Peak memory 206548 kb
Host smart-08d8875b-612b-4824-919b-17d446372562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999111906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1999111906
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4281016600
Short name T963
Test name
Test status
Simulation time 38581790 ps
CPU time 0.84 seconds
Started Jun 09 12:47:13 PM PDT 24
Finished Jun 09 12:47:15 PM PDT 24
Peak memory 205956 kb
Host smart-433a9a54-3e29-42bb-b959-23e1a41d283c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281016600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4281016600
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3534878456
Short name T242
Test name
Test status
Simulation time 15870729 ps
CPU time 1.01 seconds
Started Jun 09 12:47:16 PM PDT 24
Finished Jun 09 12:47:17 PM PDT 24
Peak memory 206316 kb
Host smart-2d563a15-97eb-43e4-80f3-88c69d34f774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534878456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3534878456
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.353043212
Short name T853
Test name
Test status
Simulation time 256340879 ps
CPU time 3.06 seconds
Started Jun 09 12:47:11 PM PDT 24
Finished Jun 09 12:47:14 PM PDT 24
Peak memory 214600 kb
Host smart-a87fdf07-4eb7-4a95-9c9b-d8c775489551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353043212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.353043212
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1887096480
Short name T934
Test name
Test status
Simulation time 280477008 ps
CPU time 2.39 seconds
Started Jun 09 12:47:12 PM PDT 24
Finished Jun 09 12:47:14 PM PDT 24
Peak memory 214564 kb
Host smart-57dbd36b-6f93-4d6f-af01-66cb64f375ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887096480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1887096480
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1719765238
Short name T947
Test name
Test status
Simulation time 30094068 ps
CPU time 1.37 seconds
Started Jun 09 12:47:19 PM PDT 24
Finished Jun 09 12:47:21 PM PDT 24
Peak memory 217364 kb
Host smart-64cac5a0-c559-411c-abc9-7be91a55a339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719765238 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1719765238
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.121308063
Short name T973
Test name
Test status
Simulation time 10906941 ps
CPU time 0.88 seconds
Started Jun 09 12:47:19 PM PDT 24
Finished Jun 09 12:47:20 PM PDT 24
Peak memory 206276 kb
Host smart-eb7229f1-b2f8-4f41-b86e-61d706365505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121308063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.121308063
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1743101419
Short name T892
Test name
Test status
Simulation time 33726700 ps
CPU time 0.89 seconds
Started Jun 09 12:47:14 PM PDT 24
Finished Jun 09 12:47:15 PM PDT 24
Peak memory 206116 kb
Host smart-bf3b8632-37bd-461b-9043-cdd959ae5062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743101419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1743101419
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.620891432
Short name T241
Test name
Test status
Simulation time 32441532 ps
CPU time 1.09 seconds
Started Jun 09 12:47:18 PM PDT 24
Finished Jun 09 12:47:20 PM PDT 24
Peak memory 206336 kb
Host smart-e719a949-0c14-432e-aa18-db78bb59ebbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620891432 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.620891432
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3075785004
Short name T852
Test name
Test status
Simulation time 99308013 ps
CPU time 2.26 seconds
Started Jun 09 12:47:16 PM PDT 24
Finished Jun 09 12:47:19 PM PDT 24
Peak memory 214732 kb
Host smart-0fdfc949-98f8-4ebe-acd8-196227d8a046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075785004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3075785004
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1602849804
Short name T966
Test name
Test status
Simulation time 135863590 ps
CPU time 1.66 seconds
Started Jun 09 12:47:16 PM PDT 24
Finished Jun 09 12:47:18 PM PDT 24
Peak memory 214480 kb
Host smart-23372b1d-ee0f-46d6-bc09-31d84df168c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602849804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1602849804
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4032638880
Short name T974
Test name
Test status
Simulation time 36937854 ps
CPU time 1.08 seconds
Started Jun 09 12:47:20 PM PDT 24
Finished Jun 09 12:47:21 PM PDT 24
Peak memory 206412 kb
Host smart-fa0dc088-22a0-4a67-894d-07a38de20ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032638880 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4032638880
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3575171078
Short name T899
Test name
Test status
Simulation time 12728932 ps
CPU time 0.97 seconds
Started Jun 09 12:47:17 PM PDT 24
Finished Jun 09 12:47:18 PM PDT 24
Peak memory 206280 kb
Host smart-e9f34855-8402-4d7e-b333-95d2b2677dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575171078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3575171078
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2579226748
Short name T968
Test name
Test status
Simulation time 25465214 ps
CPU time 0.81 seconds
Started Jun 09 12:47:20 PM PDT 24
Finished Jun 09 12:47:22 PM PDT 24
Peak memory 205996 kb
Host smart-8c844adc-ed76-46bd-8dd4-16000185ae60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579226748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2579226748
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3216049497
Short name T222
Test name
Test status
Simulation time 30635530 ps
CPU time 1.07 seconds
Started Jun 09 12:47:15 PM PDT 24
Finished Jun 09 12:47:16 PM PDT 24
Peak memory 206336 kb
Host smart-abcc95f3-b76a-447c-84d5-747e1df4bf09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216049497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3216049497
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3049887449
Short name T842
Test name
Test status
Simulation time 139425542 ps
CPU time 1.79 seconds
Started Jun 09 12:47:15 PM PDT 24
Finished Jun 09 12:47:17 PM PDT 24
Peak memory 214616 kb
Host smart-376bc869-9ab7-4233-9c33-733d0a10799f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049887449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3049887449
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert_test.1504403016
Short name T726
Test name
Test status
Simulation time 71478663 ps
CPU time 0.95 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 01:54:11 PM PDT 24
Peak memory 206640 kb
Host smart-1a01dd90-0d27-4166-a367-9a24eb1be72a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504403016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1504403016
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_genbits.3134965954
Short name T673
Test name
Test status
Simulation time 77202748 ps
CPU time 1.2 seconds
Started Jun 09 01:54:11 PM PDT 24
Finished Jun 09 01:54:12 PM PDT 24
Peak memory 216860 kb
Host smart-d2890aa9-390a-4941-a7ee-73516f823509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134965954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3134965954
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_regwen.3818244725
Short name T26
Test name
Test status
Simulation time 15356926 ps
CPU time 0.95 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 01:54:12 PM PDT 24
Peak memory 206972 kb
Host smart-cb30ca74-7375-456c-94df-80493c680d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818244725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3818244725
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.1951764052
Short name T805
Test name
Test status
Simulation time 23034326 ps
CPU time 0.96 seconds
Started Jun 09 01:54:26 PM PDT 24
Finished Jun 09 01:54:27 PM PDT 24
Peak memory 215204 kb
Host smart-517bd1e6-7fb2-411b-ad5a-2561ee8d890b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951764052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1951764052
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.311386532
Short name T81
Test name
Test status
Simulation time 560405610 ps
CPU time 3.16 seconds
Started Jun 09 01:54:11 PM PDT 24
Finished Jun 09 01:54:14 PM PDT 24
Peak memory 219280 kb
Host smart-1731761b-fab1-4d5f-9320-a1cd4b91a445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311386532 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.311386532
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2357070825
Short name T822
Test name
Test status
Simulation time 124563925866 ps
CPU time 709.51 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 02:05:59 PM PDT 24
Peak memory 220800 kb
Host smart-f08495f0-8009-4df4-baa0-a85638d738cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357070825 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2357070825
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.67501668
Short name T471
Test name
Test status
Simulation time 46202195 ps
CPU time 0.83 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 206308 kb
Host smart-f09f39b4-3466-4c4e-a328-844859f71f75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67501668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.67501668
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4094460397
Short name T662
Test name
Test status
Simulation time 30516913 ps
CPU time 1.22 seconds
Started Jun 09 01:54:16 PM PDT 24
Finished Jun 09 01:54:18 PM PDT 24
Peak memory 219284 kb
Host smart-8d8ab798-8d98-4d4e-aa6e-d1cb2d19227e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094460397 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4094460397
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.294244158
Short name T5
Test name
Test status
Simulation time 23843121 ps
CPU time 1.15 seconds
Started Jun 09 01:54:17 PM PDT 24
Finished Jun 09 01:54:18 PM PDT 24
Peak memory 224088 kb
Host smart-2bd7c714-3a6b-4f97-9ef8-211130d03ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294244158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.294244158
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2452535152
Short name T658
Test name
Test status
Simulation time 80169414 ps
CPU time 1.18 seconds
Started Jun 09 01:54:09 PM PDT 24
Finished Jun 09 01:54:11 PM PDT 24
Peak memory 219624 kb
Host smart-3e165a5c-0346-4cbd-9a8e-d17dade48bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452535152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2452535152
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3942554759
Short name T341
Test name
Test status
Simulation time 34104228 ps
CPU time 0.93 seconds
Started Jun 09 01:54:09 PM PDT 24
Finished Jun 09 01:54:10 PM PDT 24
Peak memory 215500 kb
Host smart-2ca64167-86f6-44be-b9a3-84a7879422b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942554759 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3942554759
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.2311488701
Short name T214
Test name
Test status
Simulation time 35501955 ps
CPU time 0.95 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 01:54:11 PM PDT 24
Peak memory 206972 kb
Host smart-926f5baa-373d-4081-aa4e-5f3924e3205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311488701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2311488701
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3660646248
Short name T14
Test name
Test status
Simulation time 932044574 ps
CPU time 4.4 seconds
Started Jun 09 01:54:14 PM PDT 24
Finished Jun 09 01:54:19 PM PDT 24
Peak memory 239136 kb
Host smart-bfcd5e8c-2606-4165-a383-6f3acbc2794d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660646248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3660646248
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3481691380
Short name T718
Test name
Test status
Simulation time 77635082 ps
CPU time 0.93 seconds
Started Jun 09 01:54:10 PM PDT 24
Finished Jun 09 01:54:11 PM PDT 24
Peak memory 215172 kb
Host smart-dd731e2d-0bd4-467c-9a7a-3eefa4c6805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481691380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3481691380
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1391618204
Short name T409
Test name
Test status
Simulation time 46578819 ps
CPU time 1.4 seconds
Started Jun 09 01:54:08 PM PDT 24
Finished Jun 09 01:54:09 PM PDT 24
Peak memory 216876 kb
Host smart-53ebb5ee-c9a2-4c29-b715-f8093997db6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391618204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1391618204
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2386547527
Short name T204
Test name
Test status
Simulation time 294999321432 ps
CPU time 1605.52 seconds
Started Jun 09 01:54:12 PM PDT 24
Finished Jun 09 02:20:58 PM PDT 24
Peak memory 224528 kb
Host smart-da5570f4-cb1e-41bc-ab61-580dad7dd139
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386547527 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2386547527
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2812006882
Short name T538
Test name
Test status
Simulation time 68566275 ps
CPU time 0.95 seconds
Started Jun 09 01:54:36 PM PDT 24
Finished Jun 09 01:54:37 PM PDT 24
Peak memory 214704 kb
Host smart-7c1a9aa0-eb14-478c-999a-cd31eec531d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812006882 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2812006882
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.356305121
Short name T414
Test name
Test status
Simulation time 330468711 ps
CPU time 1.14 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 216804 kb
Host smart-1735b24d-1a7c-46f8-acee-aa4bfd6d57ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356305121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.356305121
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1206736065
Short name T151
Test name
Test status
Simulation time 40870342 ps
CPU time 0.89 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:40 PM PDT 24
Peak memory 215212 kb
Host smart-66720902-3621-4b54-b8ef-d790c8292d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206736065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1206736065
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_smoke.2310351458
Short name T744
Test name
Test status
Simulation time 40518142 ps
CPU time 0.94 seconds
Started Jun 09 01:54:35 PM PDT 24
Finished Jun 09 01:54:36 PM PDT 24
Peak memory 215196 kb
Host smart-d26ca3cc-357c-4884-992a-30200ab9b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310351458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2310351458
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.2562162811
Short name T316
Test name
Test status
Simulation time 168579089 ps
CPU time 3.52 seconds
Started Jun 09 01:54:32 PM PDT 24
Finished Jun 09 01:54:36 PM PDT 24
Peak memory 216796 kb
Host smart-5be4fbbd-2165-4c87-8e5a-40ae797a8819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562162811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2562162811
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/101.edn_genbits.1555623501
Short name T521
Test name
Test status
Simulation time 104951180 ps
CPU time 1.25 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 217004 kb
Host smart-48b90f2a-1549-4da8-9678-a15aaeab187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555623501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1555623501
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3051475606
Short name T598
Test name
Test status
Simulation time 38068993 ps
CPU time 1.3 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 218136 kb
Host smart-2a0c33b1-6183-48e1-aa18-b79a4f8bb4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051475606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3051475606
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3178975683
Short name T503
Test name
Test status
Simulation time 85871064 ps
CPU time 1.43 seconds
Started Jun 09 01:56:02 PM PDT 24
Finished Jun 09 01:56:03 PM PDT 24
Peak memory 216864 kb
Host smart-f8d55ae1-f580-4735-8d4a-0417ea9fc457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178975683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3178975683
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.747430961
Short name T470
Test name
Test status
Simulation time 48069844 ps
CPU time 1.19 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 218140 kb
Host smart-daba8ab2-2d52-4845-bdf9-de8e74a139e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747430961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.747430961
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1707666155
Short name T280
Test name
Test status
Simulation time 45368643 ps
CPU time 1.25 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 217076 kb
Host smart-6474d600-7a0e-43ba-9a97-a24045ec603f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707666155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1707666155
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.283693637
Short name T385
Test name
Test status
Simulation time 48828067 ps
CPU time 1.52 seconds
Started Jun 09 01:56:00 PM PDT 24
Finished Jun 09 01:56:02 PM PDT 24
Peak memory 218072 kb
Host smart-bb08d5ca-e862-4864-803f-1dffe5126d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283693637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.283693637
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2326271180
Short name T395
Test name
Test status
Simulation time 48788820 ps
CPU time 1.48 seconds
Started Jun 09 01:56:02 PM PDT 24
Finished Jun 09 01:56:03 PM PDT 24
Peak memory 218236 kb
Host smart-bf4b96aa-82ad-4e0f-9891-e114d218aa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326271180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2326271180
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.3062234213
Short name T532
Test name
Test status
Simulation time 40705591 ps
CPU time 1.37 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:55:59 PM PDT 24
Peak memory 219516 kb
Host smart-092e7ad5-4a07-47c4-8b7f-93d83e8ecaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062234213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3062234213
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1832818429
Short name T699
Test name
Test status
Simulation time 48835445 ps
CPU time 1.5 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 218316 kb
Host smart-0e59c736-a025-49ec-bb4e-1d405af8df1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832818429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1832818429
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.4217577081
Short name T614
Test name
Test status
Simulation time 14216282 ps
CPU time 0.88 seconds
Started Jun 09 01:54:38 PM PDT 24
Finished Jun 09 01:54:39 PM PDT 24
Peak memory 214720 kb
Host smart-9fdf4332-6c4d-4700-b95b-e44020cf039a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217577081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4217577081
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1650417754
Short name T665
Test name
Test status
Simulation time 37447664 ps
CPU time 1.23 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:41 PM PDT 24
Peak memory 218076 kb
Host smart-2e6cf860-08fe-45c2-ac9d-c60882103291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650417754 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1650417754
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.512762002
Short name T417
Test name
Test status
Simulation time 51763161 ps
CPU time 1.88 seconds
Started Jun 09 01:54:32 PM PDT 24
Finished Jun 09 01:54:34 PM PDT 24
Peak memory 218356 kb
Host smart-e6f5abca-0ced-4887-a92b-7aed3ea915df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512762002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.512762002
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.561212816
Short name T752
Test name
Test status
Simulation time 21911531 ps
CPU time 1.06 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 215520 kb
Host smart-51df356f-0cdf-460a-854f-d7186cf4756a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561212816 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.561212816
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.3135584538
Short name T425
Test name
Test status
Simulation time 75822153 ps
CPU time 0.88 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 01:54:34 PM PDT 24
Peak memory 215212 kb
Host smart-de2fe931-05a2-4d40-92d2-0f76c4a126f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135584538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3135584538
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2813188089
Short name T646
Test name
Test status
Simulation time 168235811 ps
CPU time 3.95 seconds
Started Jun 09 01:54:31 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 217172 kb
Host smart-a99f693e-00ee-4cf4-af02-997b993f8a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813188089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2813188089
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2285094560
Short name T576
Test name
Test status
Simulation time 22021738655 ps
CPU time 475.32 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 02:02:30 PM PDT 24
Peak memory 223500 kb
Host smart-efee7984-f01a-4bd1-a861-9c5d49ac583d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285094560 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2285094560
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.8218865
Short name T732
Test name
Test status
Simulation time 37570244 ps
CPU time 1.54 seconds
Started Jun 09 01:56:01 PM PDT 24
Finished Jun 09 01:56:03 PM PDT 24
Peak memory 218236 kb
Host smart-bc6948e2-e646-4e1b-99b3-afc5e618d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8218865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.8218865
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.915354375
Short name T460
Test name
Test status
Simulation time 33011385 ps
CPU time 1.28 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 216864 kb
Host smart-f62f5d1e-a6b8-4acb-bfe1-3591038b3a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915354375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.915354375
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.753633985
Short name T401
Test name
Test status
Simulation time 42266945 ps
CPU time 1.57 seconds
Started Jun 09 01:56:02 PM PDT 24
Finished Jun 09 01:56:04 PM PDT 24
Peak memory 219468 kb
Host smart-251caa05-7561-455f-8c6f-c83a25d7969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753633985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.753633985
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1234034642
Short name T9
Test name
Test status
Simulation time 54522303 ps
CPU time 1.31 seconds
Started Jun 09 01:56:02 PM PDT 24
Finished Jun 09 01:56:03 PM PDT 24
Peak memory 219452 kb
Host smart-00a1262b-45f4-4778-9acd-ed832e845f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234034642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1234034642
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1261427291
Short name T454
Test name
Test status
Simulation time 88745647 ps
CPU time 1.16 seconds
Started Jun 09 01:56:05 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 216752 kb
Host smart-581ed9e9-94d5-4bb3-9a4c-e8ac3259986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261427291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1261427291
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3542337013
Short name T768
Test name
Test status
Simulation time 49067502 ps
CPU time 1.18 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 219436 kb
Host smart-fd51178c-6d9c-4c02-b823-e7978a8c3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542337013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3542337013
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1035848748
Short name T747
Test name
Test status
Simulation time 101177763 ps
CPU time 1.02 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:05 PM PDT 24
Peak memory 216892 kb
Host smart-eea6d129-18b4-4a8a-ab00-479b1d0d5033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035848748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1035848748
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.837465957
Short name T394
Test name
Test status
Simulation time 78605233 ps
CPU time 1.04 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 216796 kb
Host smart-1b57089b-c197-4137-8d2e-696da64aaf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837465957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.837465957
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1785854781
Short name T30
Test name
Test status
Simulation time 74513237 ps
CPU time 1.15 seconds
Started Jun 09 01:54:40 PM PDT 24
Finished Jun 09 01:54:41 PM PDT 24
Peak memory 218840 kb
Host smart-75640a65-48ae-48d9-9a2e-8ee62d230ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785854781 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1785854781
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1699852641
Short name T784
Test name
Test status
Simulation time 15019475 ps
CPU time 0.89 seconds
Started Jun 09 01:54:43 PM PDT 24
Finished Jun 09 01:54:44 PM PDT 24
Peak memory 206488 kb
Host smart-89b6def0-1a45-45e7-8afe-3a98cf51d822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699852641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1699852641
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3435229550
Short name T540
Test name
Test status
Simulation time 51650081 ps
CPU time 1.19 seconds
Started Jun 09 01:54:42 PM PDT 24
Finished Jun 09 01:54:43 PM PDT 24
Peak memory 216800 kb
Host smart-5c590b67-0049-48cf-a907-f7ab94a65c6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435229550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3435229550
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3172027880
Short name T606
Test name
Test status
Simulation time 24259928 ps
CPU time 1.2 seconds
Started Jun 09 01:54:36 PM PDT 24
Finished Jun 09 01:54:38 PM PDT 24
Peak memory 220772 kb
Host smart-9ffcd1ed-ee7e-4484-bbb5-6e252bcc0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172027880 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3172027880
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2876076981
Short name T492
Test name
Test status
Simulation time 37361343 ps
CPU time 1.36 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:40 PM PDT 24
Peak memory 216904 kb
Host smart-430f6779-6c76-4de4-b714-ad9071a61751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876076981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2876076981
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.3782977375
Short name T804
Test name
Test status
Simulation time 50622158 ps
CPU time 0.96 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:40 PM PDT 24
Peak memory 215320 kb
Host smart-63adb9f5-c37c-4e85-911c-40966024aaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782977375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3782977375
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3570639741
Short name T415
Test name
Test status
Simulation time 378892531 ps
CPU time 4.39 seconds
Started Jun 09 01:54:37 PM PDT 24
Finished Jun 09 01:54:42 PM PDT 24
Peak memory 215232 kb
Host smart-08050d52-c9ac-4d26-b973-93df275cceaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570639741 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3570639741
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4071823550
Short name T201
Test name
Test status
Simulation time 60813720938 ps
CPU time 1404.6 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 02:18:04 PM PDT 24
Peak memory 221928 kb
Host smart-6db6720c-bab4-419d-ae97-00b724c86d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071823550 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4071823550
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2112569035
Short name T721
Test name
Test status
Simulation time 21148719 ps
CPU time 1.22 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 217000 kb
Host smart-a3b43870-8c96-4b87-a424-fc91b1c9fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112569035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2112569035
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.295062307
Short name T487
Test name
Test status
Simulation time 94284324 ps
CPU time 1.12 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 219472 kb
Host smart-71a135da-65c9-4767-b5a0-ea1aadb35626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295062307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.295062307
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2887756143
Short name T283
Test name
Test status
Simulation time 42448295 ps
CPU time 1.65 seconds
Started Jun 09 01:56:05 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 218268 kb
Host smart-32ce5f50-5f99-4f4a-bb72-83a2a15c7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887756143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2887756143
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1342841379
Short name T10
Test name
Test status
Simulation time 66990812 ps
CPU time 1.33 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 219656 kb
Host smart-54c94ea3-65df-4527-93d5-b85818ed6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342841379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1342841379
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2051542256
Short name T613
Test name
Test status
Simulation time 48217436 ps
CPU time 1.24 seconds
Started Jun 09 01:56:07 PM PDT 24
Finished Jun 09 01:56:09 PM PDT 24
Peak memory 218588 kb
Host smart-d3f8c2d6-36ae-4e1e-a488-bd073a49db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051542256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2051542256
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.261584876
Short name T582
Test name
Test status
Simulation time 122144635 ps
CPU time 1.49 seconds
Started Jun 09 01:56:05 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 217168 kb
Host smart-1eb9e11e-2642-4381-8685-e443c2d9ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261584876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.261584876
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1649182960
Short name T586
Test name
Test status
Simulation time 278131759 ps
CPU time 3.42 seconds
Started Jun 09 01:56:07 PM PDT 24
Finished Jun 09 01:56:10 PM PDT 24
Peak memory 219500 kb
Host smart-16e0633f-a978-4480-9e15-58276dd56fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649182960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1649182960
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1093687907
Short name T654
Test name
Test status
Simulation time 54604540 ps
CPU time 1.97 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 215276 kb
Host smart-b69525ad-1b15-487e-b892-5400611ffc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093687907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1093687907
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3595829838
Short name T684
Test name
Test status
Simulation time 57965032 ps
CPU time 0.97 seconds
Started Jun 09 01:56:05 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 215220 kb
Host smart-330ba6c2-f411-45af-9c4a-47714d77db3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595829838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3595829838
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1701563605
Short name T356
Test name
Test status
Simulation time 145691596 ps
CPU time 1.57 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 218404 kb
Host smart-488cc0f4-654c-485a-96a6-2c84955ca3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701563605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1701563605
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2984521665
Short name T737
Test name
Test status
Simulation time 25732812 ps
CPU time 0.95 seconds
Started Jun 09 01:54:42 PM PDT 24
Finished Jun 09 01:54:43 PM PDT 24
Peak memory 206604 kb
Host smart-d2c0c42f-12ae-4cdf-8268-4dfa10010760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984521665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2984521665
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2153775131
Short name T153
Test name
Test status
Simulation time 24226203 ps
CPU time 0.93 seconds
Started Jun 09 01:54:42 PM PDT 24
Finished Jun 09 01:54:43 PM PDT 24
Peak memory 216320 kb
Host smart-31a7ee6f-b588-4cde-a62c-da4703e60d46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153775131 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2153775131
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.356290705
Short name T789
Test name
Test status
Simulation time 33652031 ps
CPU time 1.27 seconds
Started Jun 09 01:54:43 PM PDT 24
Finished Jun 09 01:54:44 PM PDT 24
Peak memory 216776 kb
Host smart-868bc43e-b275-4c19-b5b8-deb626c9ba3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356290705 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.356290705
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1623355349
Short name T753
Test name
Test status
Simulation time 139627105 ps
CPU time 1.01 seconds
Started Jun 09 01:54:42 PM PDT 24
Finished Jun 09 01:54:43 PM PDT 24
Peak memory 219616 kb
Host smart-2483833a-b0aa-4d58-8c7e-ec17a67245c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623355349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1623355349
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3830587028
Short name T467
Test name
Test status
Simulation time 81492429 ps
CPU time 1.2 seconds
Started Jun 09 01:54:41 PM PDT 24
Finished Jun 09 01:54:42 PM PDT 24
Peak memory 216984 kb
Host smart-fd7f514e-7061-42ef-936d-c59da4834adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830587028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3830587028
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2934458016
Short name T325
Test name
Test status
Simulation time 22707219 ps
CPU time 1.11 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:46 PM PDT 24
Peak memory 215484 kb
Host smart-296f992d-6af5-4f7f-8fbc-27ceb4a097a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934458016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2934458016
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.843866241
Short name T553
Test name
Test status
Simulation time 35258019 ps
CPU time 0.91 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:47 PM PDT 24
Peak memory 215212 kb
Host smart-2e038444-67e1-40e1-bf89-66618e6297ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843866241 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.843866241
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.2351829937
Short name T823
Test name
Test status
Simulation time 486605928 ps
CPU time 3.22 seconds
Started Jun 09 01:54:44 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 219736 kb
Host smart-c70bd5d0-437d-4df1-9f72-b5092c49e8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351829937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.2351829937
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4258133053
Short name T529
Test name
Test status
Simulation time 50434192800 ps
CPU time 1070.37 seconds
Started Jun 09 01:54:44 PM PDT 24
Finished Jun 09 02:12:35 PM PDT 24
Peak memory 219236 kb
Host smart-c1657443-3da1-422e-8a3e-b224b61ae767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258133053 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4258133053
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.edn_genbits.2595115088
Short name T377
Test name
Test status
Simulation time 37140101 ps
CPU time 1.41 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 219496 kb
Host smart-5153094d-d7e0-40ee-b1d5-ffa37b6859a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595115088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2595115088
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.602492440
Short name T388
Test name
Test status
Simulation time 72254417 ps
CPU time 1.2 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 217268 kb
Host smart-1c1c3851-efdd-455e-bcd4-608613c1c1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602492440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.602492440
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2984453910
Short name T68
Test name
Test status
Simulation time 205110525 ps
CPU time 1.55 seconds
Started Jun 09 01:56:07 PM PDT 24
Finished Jun 09 01:56:09 PM PDT 24
Peak memory 216916 kb
Host smart-5c14fd3f-33f5-48c1-8854-560a6c364d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984453910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2984453910
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.3711824960
Short name T478
Test name
Test status
Simulation time 150768234 ps
CPU time 1.24 seconds
Started Jun 09 01:56:06 PM PDT 24
Finished Jun 09 01:56:07 PM PDT 24
Peak memory 218528 kb
Host smart-dce737b7-2269-424d-afb2-963d4f701571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711824960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3711824960
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3081178388
Short name T355
Test name
Test status
Simulation time 297315872 ps
CPU time 1.2 seconds
Started Jun 09 01:56:07 PM PDT 24
Finished Jun 09 01:56:08 PM PDT 24
Peak memory 216960 kb
Host smart-9c257e2e-6ba8-4fb4-847e-aea4c9e753e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081178388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3081178388
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1977460176
Short name T597
Test name
Test status
Simulation time 30435079 ps
CPU time 1.34 seconds
Started Jun 09 01:56:04 PM PDT 24
Finished Jun 09 01:56:06 PM PDT 24
Peak memory 218260 kb
Host smart-c6894509-2883-4a49-a5c5-b37fa873f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977460176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1977460176
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3622672047
Short name T287
Test name
Test status
Simulation time 53432123 ps
CPU time 1.31 seconds
Started Jun 09 01:56:07 PM PDT 24
Finished Jun 09 01:56:09 PM PDT 24
Peak memory 216940 kb
Host smart-90b26b13-46fa-467c-99d7-b87c40bd0c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622672047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3622672047
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2907530307
Short name T635
Test name
Test status
Simulation time 201364236 ps
CPU time 1.17 seconds
Started Jun 09 01:56:03 PM PDT 24
Finished Jun 09 01:56:05 PM PDT 24
Peak memory 216864 kb
Host smart-dc4088fe-0a39-4401-93b2-a70d7c1da96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907530307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2907530307
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.4157431456
Short name T588
Test name
Test status
Simulation time 43935321 ps
CPU time 0.83 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:46 PM PDT 24
Peak memory 206696 kb
Host smart-21a3a73a-4b6f-445e-b882-dbaf4b775dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157431456 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4157431456
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1749097119
Short name T152
Test name
Test status
Simulation time 23497725 ps
CPU time 0.94 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 216056 kb
Host smart-d2a448f4-9e87-4b24-98a5-c77829199c2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749097119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1749097119
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.459293274
Short name T468
Test name
Test status
Simulation time 31598944 ps
CPU time 1.11 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:50 PM PDT 24
Peak memory 224064 kb
Host smart-9ccf5f09-8ec8-4fad-8e9e-5f75a3918c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459293274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.459293274
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2935849502
Short name T739
Test name
Test status
Simulation time 58417790 ps
CPU time 1.34 seconds
Started Jun 09 01:54:43 PM PDT 24
Finished Jun 09 01:54:44 PM PDT 24
Peak memory 218348 kb
Host smart-9beda223-3322-42bf-a297-dbd1fa00789e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935849502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2935849502
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1097425821
Short name T87
Test name
Test status
Simulation time 19991765 ps
CPU time 1.03 seconds
Started Jun 09 01:54:44 PM PDT 24
Finished Jun 09 01:54:45 PM PDT 24
Peak memory 215888 kb
Host smart-235d0c3d-fc41-4fc9-9cd5-c4474c8f6f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097425821 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1097425821
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3964008484
Short name T312
Test name
Test status
Simulation time 22230895 ps
CPU time 0.92 seconds
Started Jun 09 01:54:43 PM PDT 24
Finished Jun 09 01:54:44 PM PDT 24
Peak memory 215200 kb
Host smart-3d4c0291-ad59-4759-a6b4-8012c22ab82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964008484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3964008484
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.701146615
Short name T248
Test name
Test status
Simulation time 431309246 ps
CPU time 2.61 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 215212 kb
Host smart-a57acc05-dafd-477a-afc1-b60b2f2414f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701146615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.701146615
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.4130573965
Short name T539
Test name
Test status
Simulation time 80600420097 ps
CPU time 448.71 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 02:02:16 PM PDT 24
Peak memory 218836 kb
Host smart-9ddc3896-d5c7-48d9-badf-e6d9a3a3ef3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130573965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.4130573965
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.856257960
Short name T12
Test name
Test status
Simulation time 224241010 ps
CPU time 2.93 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 219484 kb
Host smart-e7391957-3d76-494f-b5b1-190c79a415f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856257960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.856257960
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.3348354973
Short name T39
Test name
Test status
Simulation time 66239872 ps
CPU time 1 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 217012 kb
Host smart-6de176e9-1e5e-44dd-9219-c0b7c0c1d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348354973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.3348354973
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2870997257
Short name T211
Test name
Test status
Simulation time 60588011 ps
CPU time 1.15 seconds
Started Jun 09 01:56:16 PM PDT 24
Finished Jun 09 01:56:17 PM PDT 24
Peak memory 217044 kb
Host smart-abd47c6c-036c-46fb-a252-7c80f89e288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870997257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2870997257
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.544976965
Short name T369
Test name
Test status
Simulation time 29010328 ps
CPU time 1.23 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 217156 kb
Host smart-a738a92b-1346-4739-b220-3d86bdf50dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544976965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.544976965
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2166833937
Short name T637
Test name
Test status
Simulation time 39138349 ps
CPU time 1.52 seconds
Started Jun 09 01:56:39 PM PDT 24
Finished Jun 09 01:56:41 PM PDT 24
Peak memory 218212 kb
Host smart-1ca4221a-3f53-4a1b-bca2-90abea93a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166833937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2166833937
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.246131717
Short name T367
Test name
Test status
Simulation time 88356547 ps
CPU time 1.16 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 219396 kb
Host smart-e9987e1b-3e26-495f-9e41-6fb5ed14384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246131717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.246131717
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1332852671
Short name T443
Test name
Test status
Simulation time 68423708 ps
CPU time 1.49 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 218256 kb
Host smart-a4e3f2b2-6fb6-4ba7-b39c-9a609ebcc5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332852671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1332852671
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1933507057
Short name T780
Test name
Test status
Simulation time 103004382 ps
CPU time 1.13 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 218584 kb
Host smart-073c6378-d5d8-45de-9d30-f6c0f034be60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933507057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1933507057
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.211427208
Short name T346
Test name
Test status
Simulation time 39056877 ps
CPU time 1.11 seconds
Started Jun 09 01:56:38 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 216800 kb
Host smart-e0743bce-874b-4bda-a3a4-c6673b17c43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211427208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.211427208
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.3565844430
Short name T671
Test name
Test status
Simulation time 14789418 ps
CPU time 0.92 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:49 PM PDT 24
Peak memory 206492 kb
Host smart-d4493782-857f-42cd-8323-ad769872c141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565844430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3565844430
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.1078847324
Short name T380
Test name
Test status
Simulation time 21599286 ps
CPU time 0.86 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 215832 kb
Host smart-8df6b33f-dbc8-412e-8669-63f140baba96
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078847324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1078847324
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.118133437
Short name T431
Test name
Test status
Simulation time 136484924 ps
CPU time 1.14 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 216832 kb
Host smart-59f194da-d61e-446e-8d99-85aae009f8ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118133437 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_di
sable_auto_req_mode.118133437
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3991389444
Short name T432
Test name
Test status
Simulation time 31888178 ps
CPU time 0.95 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 219764 kb
Host smart-4a107924-852f-4828-865c-3143ea6e1a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991389444 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3991389444
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3496828253
Short name T778
Test name
Test status
Simulation time 91899106 ps
CPU time 1.28 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:50 PM PDT 24
Peak memory 219440 kb
Host smart-f8690b78-54c1-4c4b-a3bc-f99bbd863cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496828253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3496828253
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.3038965751
Short name T813
Test name
Test status
Simulation time 37996479 ps
CPU time 0.9 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 215092 kb
Host smart-81571c2d-ffdc-4615-99a9-f4752d3df4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038965751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3038965751
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2598026962
Short name T535
Test name
Test status
Simulation time 27140017 ps
CPU time 0.98 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 215184 kb
Host smart-848a32c6-c5ca-4131-938c-78010f6743fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598026962 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2598026962
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.720113854
Short name T90
Test name
Test status
Simulation time 396079838 ps
CPU time 4.2 seconds
Started Jun 09 01:54:46 PM PDT 24
Finished Jun 09 01:54:51 PM PDT 24
Peak memory 215240 kb
Host smart-38b47863-255d-49fd-ab6c-d6394a73255d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720113854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.720113854
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.3807028729
Short name T357
Test name
Test status
Simulation time 34372591 ps
CPU time 1.24 seconds
Started Jun 09 01:56:39 PM PDT 24
Finished Jun 09 01:56:41 PM PDT 24
Peak memory 217212 kb
Host smart-5607f0a9-e9b9-4515-82be-5100d8d862ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807028729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3807028729
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1557753439
Short name T818
Test name
Test status
Simulation time 375230929 ps
CPU time 1.24 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 216896 kb
Host smart-29a09513-9610-4010-ab16-7f1ed35d809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557753439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1557753439
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.338606530
Short name T554
Test name
Test status
Simulation time 61752931 ps
CPU time 1.65 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 218276 kb
Host smart-ab598f39-be0b-428a-b1d7-5c005a84ef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338606530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.338606530
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.855594741
Short name T383
Test name
Test status
Simulation time 57629461 ps
CPU time 1.57 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:41 PM PDT 24
Peak memory 218436 kb
Host smart-2cd7748a-63b2-4338-b327-dc6994839c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855594741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.855594741
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.774401154
Short name T286
Test name
Test status
Simulation time 10401935869 ps
CPU time 135.49 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:58:55 PM PDT 24
Peak memory 220132 kb
Host smart-59630306-3803-469b-89e8-5600a84a9333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774401154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.774401154
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3491611360
Short name T405
Test name
Test status
Simulation time 98532932 ps
CPU time 1.45 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 218484 kb
Host smart-5a1f9943-a72c-4abe-a906-e5fd0692fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491611360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3491611360
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.1645134283
Short name T215
Test name
Test status
Simulation time 42179358 ps
CPU time 1.37 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 218176 kb
Host smart-65ad4536-48ca-4800-aef4-29fa765bafbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645134283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1645134283
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2010550798
Short name T568
Test name
Test status
Simulation time 41142051 ps
CPU time 1.57 seconds
Started Jun 09 01:56:39 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 216792 kb
Host smart-878df2fe-82bf-46cc-a9e8-f4c6373335d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010550798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2010550798
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1615663588
Short name T653
Test name
Test status
Simulation time 49142672 ps
CPU time 2.09 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 220004 kb
Host smart-d7356a13-e39d-4dbd-8b86-2e6a7a462f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615663588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1615663588
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2534323368
Short name T611
Test name
Test status
Simulation time 49920105 ps
CPU time 1.58 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218048 kb
Host smart-a4f846f6-f95f-4597-aaaf-e212f429d47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534323368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2534323368
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.2841791243
Short name T480
Test name
Test status
Simulation time 25793625 ps
CPU time 0.81 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 206204 kb
Host smart-11c8ad46-a86a-4e5b-86fd-d890697dade0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841791243 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2841791243
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4147124386
Short name T154
Test name
Test status
Simulation time 23786906 ps
CPU time 0.84 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:46 PM PDT 24
Peak memory 216268 kb
Host smart-26d2de85-2e3d-4f20-a6d4-54013e5c1ca0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147124386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4147124386
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3883338125
Short name T608
Test name
Test status
Simulation time 149585593 ps
CPU time 1.34 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 216940 kb
Host smart-dbdf4452-918d-49c9-922c-4f9f3489bc54
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883338125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3883338125
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.546515
Short name T125
Test name
Test status
Simulation time 43274491 ps
CPU time 1.21 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 229492 kb
Host smart-26f26de1-d40b-4ade-b315-d8204401bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546515 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.546515
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.801783600
Short name T373
Test name
Test status
Simulation time 42759117 ps
CPU time 1.44 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 01:54:48 PM PDT 24
Peak memory 216904 kb
Host smart-7486703d-f31b-48bd-8691-573bc0d4bc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801783600 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.801783600
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1341564580
Short name T332
Test name
Test status
Simulation time 21207550 ps
CPU time 1.11 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 215508 kb
Host smart-bf9b29d9-f915-4e29-be36-2128664d9f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341564580 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1341564580
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1379189299
Short name T710
Test name
Test status
Simulation time 17775283 ps
CPU time 1 seconds
Started Jun 09 01:54:45 PM PDT 24
Finished Jun 09 01:54:46 PM PDT 24
Peak memory 215276 kb
Host smart-9c8b3a38-4b41-4fc6-ab44-7772ae60250d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379189299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1379189299
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3969401314
Short name T466
Test name
Test status
Simulation time 574192950 ps
CPU time 3.83 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 01:54:51 PM PDT 24
Peak memory 215212 kb
Host smart-1109451a-1baa-4982-97af-6d9b96e6bc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969401314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3969401314
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1986820906
Short name T506
Test name
Test status
Simulation time 107924389311 ps
CPU time 1415.26 seconds
Started Jun 09 01:54:47 PM PDT 24
Finished Jun 09 02:18:23 PM PDT 24
Peak memory 223268 kb
Host smart-89429221-3b06-4dc6-b58e-3529f8d4d269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986820906 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1986820906
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1614270384
Short name T648
Test name
Test status
Simulation time 47147734 ps
CPU time 1.09 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 219388 kb
Host smart-690fbdb3-6e8b-4019-92f9-f6a876e5fcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614270384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1614270384
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2593570305
Short name T334
Test name
Test status
Simulation time 37558566 ps
CPU time 1.1 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 217004 kb
Host smart-ff0f816e-d53b-435c-af99-021da03ae815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593570305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2593570305
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.2179280931
Short name T795
Test name
Test status
Simulation time 172487960 ps
CPU time 2.87 seconds
Started Jun 09 01:56:39 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 220088 kb
Host smart-7a78be56-0b8f-4250-9d41-7358b56ae721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179280931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2179280931
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2392251866
Short name T336
Test name
Test status
Simulation time 28788938 ps
CPU time 1.27 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 216980 kb
Host smart-e0a19982-3ee1-4173-88e2-93971b82599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392251866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2392251866
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.444355429
Short name T67
Test name
Test status
Simulation time 51086394 ps
CPU time 1.44 seconds
Started Jun 09 01:56:36 PM PDT 24
Finished Jun 09 01:56:38 PM PDT 24
Peak memory 218460 kb
Host smart-de8d5dda-7282-4760-9606-448b873b25dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444355429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.444355429
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.510005855
Short name T672
Test name
Test status
Simulation time 75645017 ps
CPU time 1.36 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 218780 kb
Host smart-df0954a4-436c-46be-98e0-9040a473321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510005855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.510005855
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3356149617
Short name T510
Test name
Test status
Simulation time 84234113 ps
CPU time 1.43 seconds
Started Jun 09 01:56:16 PM PDT 24
Finished Jun 09 01:56:18 PM PDT 24
Peak memory 218600 kb
Host smart-72d7b42d-be10-4d56-bfa7-307f10266956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356149617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3356149617
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2229311949
Short name T451
Test name
Test status
Simulation time 80681551 ps
CPU time 1.78 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 218276 kb
Host smart-4547b7f4-7539-4d38-b246-300494fad33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229311949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2229311949
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2919708660
Short name T618
Test name
Test status
Simulation time 33529750 ps
CPU time 1.59 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 217304 kb
Host smart-56598471-7134-4b44-ac60-c52b7aee0222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919708660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2919708660
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.3313281785
Short name T643
Test name
Test status
Simulation time 18106541 ps
CPU time 0.97 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 206516 kb
Host smart-fa17db90-0f5e-4958-8a39-85a77e4b99f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313281785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3313281785
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.889445304
Short name T390
Test name
Test status
Simulation time 28927645 ps
CPU time 0.93 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:49 PM PDT 24
Peak memory 218500 kb
Host smart-1e6154a7-7de8-41a3-8084-650af557ba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889445304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.889445304
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3904361513
Short name T406
Test name
Test status
Simulation time 117718393 ps
CPU time 1.08 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:50 PM PDT 24
Peak memory 216924 kb
Host smart-5f95da52-2110-4fb7-9a80-c55b7608ec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904361513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3904361513
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3704393027
Short name T66
Test name
Test status
Simulation time 33930140 ps
CPU time 0.92 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 215120 kb
Host smart-96dd3a3f-8bfb-43cc-8c4d-6b3d968bef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704393027 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3704393027
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.73235828
Short name T319
Test name
Test status
Simulation time 23114381 ps
CPU time 1 seconds
Started Jun 09 01:54:48 PM PDT 24
Finished Jun 09 01:54:50 PM PDT 24
Peak memory 215192 kb
Host smart-adc56c4e-4e2a-4146-a810-13ab3cfdc5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73235828 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.73235828
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2612106651
Short name T476
Test name
Test status
Simulation time 250425549 ps
CPU time 3 seconds
Started Jun 09 01:54:51 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 216784 kb
Host smart-42f13dad-8916-49eb-b8fd-6728ac50f742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612106651 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2612106651
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1549285851
Short name T244
Test name
Test status
Simulation time 232525460841 ps
CPU time 2090.71 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 02:29:49 PM PDT 24
Peak memory 229552 kb
Host smart-637ebf34-bdcf-48ec-86fa-f6a3d0e3a52c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549285851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1549285851
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4055915941
Short name T652
Test name
Test status
Simulation time 48909398 ps
CPU time 1.68 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 218108 kb
Host smart-7d2c0c88-d230-4a89-9265-07d015443755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055915941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4055915941
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1549633243
Short name T1
Test name
Test status
Simulation time 104492798 ps
CPU time 1.49 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218168 kb
Host smart-a3c1fdd5-9bd2-49d3-8536-b8bddd3835cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549633243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1549633243
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2764554790
Short name T363
Test name
Test status
Simulation time 28497760 ps
CPU time 1.23 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 216808 kb
Host smart-0a932424-763b-4634-ab16-dc75f3a64b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764554790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2764554790
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1926394436
Short name T216
Test name
Test status
Simulation time 49985892 ps
CPU time 1.52 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 217924 kb
Host smart-b4555484-40da-45eb-bc1a-0a1bf6ffe13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926394436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1926394436
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3579327518
Short name T275
Test name
Test status
Simulation time 46956127 ps
CPU time 1.86 seconds
Started Jun 09 01:56:38 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 217992 kb
Host smart-8a499507-2b21-4cd9-a506-bd8ddb46a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579327518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3579327518
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3539268024
Short name T840
Test name
Test status
Simulation time 119644760 ps
CPU time 1.31 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 218008 kb
Host smart-90c86c49-5a7d-4493-8a69-920a0759701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539268024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3539268024
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.4275271664
Short name T361
Test name
Test status
Simulation time 27481923 ps
CPU time 1.21 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216908 kb
Host smart-f810a5fe-e959-4a3c-99ee-e2d834893631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275271664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.4275271664
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2467980275
Short name T484
Test name
Test status
Simulation time 133606657 ps
CPU time 1.62 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 218512 kb
Host smart-03504a9a-f153-4ed5-8f20-b9e00a541a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467980275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2467980275
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.210937429
Short name T712
Test name
Test status
Simulation time 70536092 ps
CPU time 1.75 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218156 kb
Host smart-fd03266c-704a-4648-b3d2-92292160a311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210937429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.210937429
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable.1449022879
Short name T398
Test name
Test status
Simulation time 15632764 ps
CPU time 0.98 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 216336 kb
Host smart-fe25e740-6b78-4874-9a84-4d3fe1dcdbb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449022879 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1449022879
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3329660869
Short name T592
Test name
Test status
Simulation time 29944641 ps
CPU time 1.21 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 229764 kb
Host smart-476e74eb-b6d2-468f-85e9-0d304c12890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329660869 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3329660869
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.592457937
Short name T268
Test name
Test status
Simulation time 42406944 ps
CPU time 1.14 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 219620 kb
Host smart-abd83981-b20f-4f08-aacb-86fc4ab89d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592457937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.592457937
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2536984608
Short name T43
Test name
Test status
Simulation time 26422240 ps
CPU time 1.02 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 215360 kb
Host smart-3300dfea-6a52-4ccc-9e34-e83c8d2e526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536984608 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2536984608
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2055687392
Short name T442
Test name
Test status
Simulation time 141888249 ps
CPU time 0.94 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 215184 kb
Host smart-37cd6d19-d670-49ed-953d-ff962c3982a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055687392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2055687392
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.1528799503
Short name T501
Test name
Test status
Simulation time 57360662 ps
CPU time 1.3 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 216784 kb
Host smart-2847a3d0-8649-416e-93df-9eec3176ba67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528799503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1528799503
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1356487959
Short name T411
Test name
Test status
Simulation time 145355535076 ps
CPU time 887.74 seconds
Started Jun 09 01:54:59 PM PDT 24
Finished Jun 09 02:09:47 PM PDT 24
Peak memory 220740 kb
Host smart-af4ceb62-c351-40fd-a209-578a55b5d1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356487959 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1356487959
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2161878155
Short name T567
Test name
Test status
Simulation time 33272767 ps
CPU time 1.41 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 217980 kb
Host smart-49b169a4-83e1-4216-a2cd-13320fdd6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161878155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2161878155
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1875367114
Short name T424
Test name
Test status
Simulation time 27157974 ps
CPU time 1.2 seconds
Started Jun 09 01:56:29 PM PDT 24
Finished Jun 09 01:56:31 PM PDT 24
Peak memory 217024 kb
Host smart-9ff3b853-a1d0-441e-8a02-cf651ee15a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875367114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1875367114
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.968674720
Short name T243
Test name
Test status
Simulation time 70469833 ps
CPU time 1.17 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 216880 kb
Host smart-8a5e2679-e033-4830-9a27-c5cd20c78378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968674720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.968674720
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2089943904
Short name T516
Test name
Test status
Simulation time 196702187 ps
CPU time 1.99 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 217372 kb
Host smart-0b926f84-40d6-440a-adf3-da0ad2a5cf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089943904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2089943904
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.834289815
Short name T473
Test name
Test status
Simulation time 34430044 ps
CPU time 1.49 seconds
Started Jun 09 01:56:38 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 218336 kb
Host smart-4229cb02-fdff-4566-8f8f-7d389961b359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834289815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.834289815
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2807164169
Short name T556
Test name
Test status
Simulation time 76513481 ps
CPU time 1.4 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 218260 kb
Host smart-75ab3a0f-9710-4a7b-9307-647db4187142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807164169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2807164169
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3661257494
Short name T610
Test name
Test status
Simulation time 40831575 ps
CPU time 1.48 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 216852 kb
Host smart-5c373294-41f0-4863-90f5-f7cd8745a9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661257494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3661257494
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4152922563
Short name T256
Test name
Test status
Simulation time 59400594 ps
CPU time 1.88 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 219620 kb
Host smart-c47dd92b-ee36-4d8e-b5e6-800bd656c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152922563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4152922563
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1186789175
Short name T674
Test name
Test status
Simulation time 81825258 ps
CPU time 1.03 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 217024 kb
Host smart-592d00e3-c2e5-4709-9974-7aff16918da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186789175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1186789175
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2219005667
Short name T714
Test name
Test status
Simulation time 57973658 ps
CPU time 1.12 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 218668 kb
Host smart-7edb7a4f-3897-4df5-8f21-f2ff2c40e25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219005667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2219005667
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.567978233
Short name T327
Test name
Test status
Simulation time 81142447 ps
CPU time 0.93 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 214720 kb
Host smart-55cab4c1-d88a-4090-9832-6dac0d5ee833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567978233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.567978233
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3169816429
Short name T623
Test name
Test status
Simulation time 12962858 ps
CPU time 0.92 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 215504 kb
Host smart-b663d6b6-8253-479d-b1de-d5eb3d97f5f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169816429 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3169816429
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2259426696
Short name T293
Test name
Test status
Simulation time 74642856 ps
CPU time 1.03 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 217940 kb
Host smart-60e6d94c-92b6-488a-83e1-51852a2edfee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259426696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2259426696
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2578361685
Short name T110
Test name
Test status
Simulation time 54931427 ps
CPU time 1.11 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 220684 kb
Host smart-76ac4ddb-4993-4ec4-8dea-daf29e8ce0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578361685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2578361685
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.4124703345
Short name T601
Test name
Test status
Simulation time 46431736 ps
CPU time 1.08 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 216984 kb
Host smart-3d9f452b-6f88-4c83-bd1c-84b675bfab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124703345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.4124703345
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3727593790
Short name T511
Test name
Test status
Simulation time 26853340 ps
CPU time 1.07 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 224084 kb
Host smart-afb6dbea-a52d-476b-b666-de4f3c9c28a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727593790 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3727593790
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2903903943
Short name T624
Test name
Test status
Simulation time 27323428 ps
CPU time 0.93 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215152 kb
Host smart-37e2ff56-3069-44ce-9ef7-c755baa7a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903903943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2903903943
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.961014759
Short name T724
Test name
Test status
Simulation time 198454651 ps
CPU time 3.19 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:04 PM PDT 24
Peak memory 215196 kb
Host smart-cb52e8a1-17b3-4807-8ec8-ed8d410542a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961014759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.961014759
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.4285786065
Short name T202
Test name
Test status
Simulation time 51918359243 ps
CPU time 1089.26 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 02:13:03 PM PDT 24
Peak memory 218800 kb
Host smart-e871c46a-bc53-4fea-91d1-2ecd88df6d89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285786065 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.4285786065
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2024676833
Short name T347
Test name
Test status
Simulation time 51431424 ps
CPU time 1.37 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:44 PM PDT 24
Peak memory 218332 kb
Host smart-c55fcc9d-5edb-4a8c-929b-d8457e82a3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024676833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2024676833
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.66168800
Short name T638
Test name
Test status
Simulation time 236260603 ps
CPU time 1.23 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216936 kb
Host smart-3512e53e-226e-4808-b712-e0e5e5e63560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66168800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.66168800
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2071946655
Short name T595
Test name
Test status
Simulation time 41208142 ps
CPU time 1.47 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 216908 kb
Host smart-d236dace-9dba-49d1-9af7-e35990aea487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071946655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2071946655
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.464162388
Short name T814
Test name
Test status
Simulation time 26973064 ps
CPU time 1.13 seconds
Started Jun 09 01:56:39 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 216912 kb
Host smart-4cc182c9-c36a-446e-bfd7-7169b4964dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464162388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.464162388
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3932021524
Short name T497
Test name
Test status
Simulation time 74307230 ps
CPU time 1.42 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218236 kb
Host smart-8d518ff4-e171-4a83-ba9c-402cdef4cea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932021524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3932021524
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3959646629
Short name T799
Test name
Test status
Simulation time 49823668 ps
CPU time 2.08 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 217080 kb
Host smart-7b34e03f-afbd-45d9-9a39-b33d4e8c1833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959646629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3959646629
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.556525892
Short name T269
Test name
Test status
Simulation time 96723140 ps
CPU time 1.3 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 216932 kb
Host smart-9b117244-194e-4839-ad88-c2a91b37ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556525892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.556525892
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.4191514269
Short name T580
Test name
Test status
Simulation time 32151140 ps
CPU time 1.35 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 217308 kb
Host smart-d8af537d-8551-42b3-9cb2-95f28b47bbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191514269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.4191514269
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1934154108
Short name T621
Test name
Test status
Simulation time 143829950 ps
CPU time 1.48 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 218472 kb
Host smart-2f240c62-9185-4ea6-b6c0-a8f434f5ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934154108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1934154108
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4142091671
Short name T517
Test name
Test status
Simulation time 63388356 ps
CPU time 1.6 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 219712 kb
Host smart-eb5dc5df-b7d7-4526-80d7-c12d3a1bdf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142091671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4142091671
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2249831578
Short name T94
Test name
Test status
Simulation time 29185751 ps
CPU time 1.25 seconds
Started Jun 09 01:54:16 PM PDT 24
Finished Jun 09 01:54:17 PM PDT 24
Peak memory 218048 kb
Host smart-df044e7a-5697-4d32-bac9-55e46fda2f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249831578 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2249831578
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3583119841
Short name T548
Test name
Test status
Simulation time 21964080 ps
CPU time 1.01 seconds
Started Jun 09 01:54:14 PM PDT 24
Finished Jun 09 01:54:15 PM PDT 24
Peak memory 206572 kb
Host smart-491ae16d-aee8-4309-8516-cef771deed5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583119841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3583119841
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2705115768
Short name T645
Test name
Test status
Simulation time 32942240 ps
CPU time 0.84 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 216000 kb
Host smart-51138bc6-6f49-4a66-9be0-c5649ef58c42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705115768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2705115768
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3110943071
Short name T625
Test name
Test status
Simulation time 72727585 ps
CPU time 1.23 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:17 PM PDT 24
Peak memory 216752 kb
Host smart-1f4057bc-660c-4408-ab3d-32886a8c4969
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110943071 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3110943071
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.889564071
Short name T118
Test name
Test status
Simulation time 25407773 ps
CPU time 1.26 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 219876 kb
Host smart-ab4b4ad4-2232-450c-bc26-114cee774cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889564071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.889564071
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.439015163
Short name T277
Test name
Test status
Simulation time 268487913 ps
CPU time 1.02 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 215172 kb
Host smart-6c6c2f81-9fd4-4227-b8cb-1b4826cba378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439015163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.439015163
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3273802854
Short name T386
Test name
Test status
Simulation time 23954939 ps
CPU time 1.11 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 215520 kb
Host smart-5338f198-3ad7-4e98-b976-c62b2b59e31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273802854 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3273802854
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.2049619741
Short name T300
Test name
Test status
Simulation time 26528821 ps
CPU time 0.91 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:20 PM PDT 24
Peak memory 206972 kb
Host smart-f27f01b7-d380-4c46-83fd-960a6e51fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049619741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2049619741
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.373404757
Short name T60
Test name
Test status
Simulation time 1932329863 ps
CPU time 7.59 seconds
Started Jun 09 01:54:14 PM PDT 24
Finished Jun 09 01:54:22 PM PDT 24
Peak memory 240232 kb
Host smart-4a74777b-e8d4-47ae-97a4-272712f889cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373404757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.373404757
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3350408021
Short name T320
Test name
Test status
Simulation time 50757736 ps
CPU time 0.92 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 215232 kb
Host smart-f0bc8e91-0564-47be-b331-61e6e99dd285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350408021 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3350408021
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.365895647
Short name T617
Test name
Test status
Simulation time 259740789 ps
CPU time 5.3 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:23 PM PDT 24
Peak memory 216820 kb
Host smart-67bab31d-e840-405b-b662-e7dcac09a283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365895647 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.365895647
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.950544752
Short name T834
Test name
Test status
Simulation time 120326580949 ps
CPU time 859.7 seconds
Started Jun 09 01:54:13 PM PDT 24
Finished Jun 09 02:08:34 PM PDT 24
Peak memory 223668 kb
Host smart-47e11533-c8a2-4221-adac-085cb8db9b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950544752 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.950544752
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.4276248920
Short name T97
Test name
Test status
Simulation time 61679836 ps
CPU time 1.09 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 218104 kb
Host smart-7c6cb0fe-15d8-41b7-97ae-e5e4f3418832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276248920 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.4276248920
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2697066217
Short name T816
Test name
Test status
Simulation time 44167055 ps
CPU time 0.84 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 206268 kb
Host smart-e6293c7f-0961-4e93-9917-cd04b6d216bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697066217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2697066217
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.1439785936
Short name T756
Test name
Test status
Simulation time 92494025 ps
CPU time 1.12 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 216856 kb
Host smart-1a3c61e5-97f2-49bb-890e-9068c355ea06
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439785936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.1439785936
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1502780736
Short name T106
Test name
Test status
Simulation time 20554730 ps
CPU time 1.34 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 229648 kb
Host smart-daa2560d-85e5-4bcc-8369-9ba3890499c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502780736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1502780736
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_intr.3826732467
Short name T609
Test name
Test status
Simulation time 26713112 ps
CPU time 0.95 seconds
Started Jun 09 01:54:51 PM PDT 24
Finished Jun 09 01:54:53 PM PDT 24
Peak memory 215504 kb
Host smart-12e3c147-dab1-4194-80ba-fd2817fdf021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826732467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3826732467
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1154021070
Short name T771
Test name
Test status
Simulation time 29716249 ps
CPU time 0.99 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215172 kb
Host smart-62decc1a-080b-4f50-bf1a-ac7385ee439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154021070 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1154021070
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3714087415
Short name T481
Test name
Test status
Simulation time 610200822 ps
CPU time 1.78 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:56 PM PDT 24
Peak memory 215136 kb
Host smart-c21d84ed-343f-4d7c-b2ce-6ad0705a7a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714087415 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3714087415
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2187321842
Short name T527
Test name
Test status
Simulation time 292577908201 ps
CPU time 492.72 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 02:03:06 PM PDT 24
Peak memory 218824 kb
Host smart-b2e79a8d-d8b7-43df-a192-327138d608aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187321842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2187321842
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1162413937
Short name T564
Test name
Test status
Simulation time 35753597 ps
CPU time 1.36 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 215184 kb
Host smart-d7bbce94-017d-4419-8c14-4432e863bb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162413937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1162413937
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1106815100
Short name T328
Test name
Test status
Simulation time 70180942 ps
CPU time 1.32 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 218088 kb
Host smart-47a12dfe-cde4-4cb3-84a4-4e665cfa0232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106815100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1106815100
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2627197453
Short name T49
Test name
Test status
Simulation time 41732563 ps
CPU time 1.72 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 217944 kb
Host smart-aed11c1a-f4dc-498c-85d1-c6abf6117d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627197453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2627197453
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2098173638
Short name T792
Test name
Test status
Simulation time 49031258 ps
CPU time 1.19 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 219592 kb
Host smart-ce8aae90-f349-4641-841c-27e8c448c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098173638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2098173638
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1180999051
Short name T555
Test name
Test status
Simulation time 52716482 ps
CPU time 1.19 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 217084 kb
Host smart-33c6a10b-ebd4-49a1-a9fa-0ae8d84476f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180999051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1180999051
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1179448780
Short name T668
Test name
Test status
Simulation time 64234244 ps
CPU time 1.3 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218052 kb
Host smart-e3a38ca0-0a73-4173-9bcf-04a1c02ccbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179448780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1179448780
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2044504344
Short name T620
Test name
Test status
Simulation time 46284395 ps
CPU time 1.09 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 218340 kb
Host smart-ea4a7745-7ba6-4a73-b1d0-a628117130ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044504344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2044504344
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3227514182
Short name T391
Test name
Test status
Simulation time 55618741 ps
CPU time 1.56 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218220 kb
Host smart-ac61e38e-852a-4588-a109-e20b8e6cd26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227514182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3227514182
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.206244842
Short name T742
Test name
Test status
Simulation time 120350161 ps
CPU time 1.38 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 219500 kb
Host smart-6e8b71c3-c213-478e-8139-594a2a3bdc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206244842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.206244842
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.2586051012
Short name T98
Test name
Test status
Simulation time 40687548 ps
CPU time 1.12 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:58 PM PDT 24
Peak memory 219276 kb
Host smart-53507d06-84e1-4c5c-992a-90122f536acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586051012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2586051012
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2263303632
Short name T315
Test name
Test status
Simulation time 17404361 ps
CPU time 0.97 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 206508 kb
Host smart-c6d2e58b-6c90-4d8d-b744-425ca7545ea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263303632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2263303632
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.996068556
Short name T566
Test name
Test status
Simulation time 77404040 ps
CPU time 0.8 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215308 kb
Host smart-055a0302-4f90-447c-bdc0-0289e436c531
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996068556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.996068556
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.776186450
Short name T449
Test name
Test status
Simulation time 112573856 ps
CPU time 1.01 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 216768 kb
Host smart-48be3820-7d7e-42b2-891b-690d11e3df01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776186450 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.776186450
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3109379224
Short name T150
Test name
Test status
Simulation time 23101990 ps
CPU time 1.03 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 224076 kb
Host smart-3639e4c6-6f87-4434-a04f-4226889d8c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109379224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3109379224
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2454961170
Short name T757
Test name
Test status
Simulation time 39800702 ps
CPU time 1.05 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 216996 kb
Host smart-0f49f4d4-7692-4695-97c4-122cc122bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454961170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2454961170
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2116270711
Short name T368
Test name
Test status
Simulation time 24296282 ps
CPU time 1.15 seconds
Started Jun 09 01:54:54 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 224108 kb
Host smart-51419def-42f8-4221-a23d-0e682725806c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116270711 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2116270711
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1110539381
Short name T641
Test name
Test status
Simulation time 19060737 ps
CPU time 0.99 seconds
Started Jun 09 01:54:52 PM PDT 24
Finished Jun 09 01:54:54 PM PDT 24
Peak memory 215136 kb
Host smart-cccf152d-21c0-4769-970f-2df75479b58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110539381 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1110539381
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.445347822
Short name T352
Test name
Test status
Simulation time 78746472 ps
CPU time 1.42 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 01:54:55 PM PDT 24
Peak memory 207128 kb
Host smart-507f14f0-1129-413d-856c-156a53b4d12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445347822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.445347822
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2805887885
Short name T365
Test name
Test status
Simulation time 89962866022 ps
CPU time 640.4 seconds
Started Jun 09 01:54:53 PM PDT 24
Finished Jun 09 02:05:34 PM PDT 24
Peak memory 219876 kb
Host smart-3f25f9d2-20d2-4e14-9d50-9688f760d867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805887885 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2805887885
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.198549476
Short name T47
Test name
Test status
Simulation time 94966736 ps
CPU time 1.54 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218552 kb
Host smart-00d96be3-90f1-4a62-943c-f27b85e4bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198549476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.198549476
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3703314082
Short name T354
Test name
Test status
Simulation time 80218418 ps
CPU time 1.12 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216980 kb
Host smart-9fd28179-f507-405f-b650-5ef29d788cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703314082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3703314082
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3321310705
Short name T550
Test name
Test status
Simulation time 86661367 ps
CPU time 1.77 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 219624 kb
Host smart-e08c82c7-c75f-4647-af71-dc235bde1e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321310705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3321310705
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.2954734221
Short name T436
Test name
Test status
Simulation time 56537699 ps
CPU time 1.3 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218468 kb
Host smart-2a2b132d-0b9f-4678-8a27-509599e547f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954734221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2954734221
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2841618410
Short name T791
Test name
Test status
Simulation time 85628372 ps
CPU time 1.45 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218364 kb
Host smart-f5da5867-3d74-4be1-be14-e43e7d7d903b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841618410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2841618410
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.4255743504
Short name T769
Test name
Test status
Simulation time 64860030 ps
CPU time 1.55 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219592 kb
Host smart-19bea1bf-957d-454a-80b9-323b85fd42e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255743504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.4255743504
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1605132270
Short name T587
Test name
Test status
Simulation time 35376168 ps
CPU time 1.04 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 218384 kb
Host smart-e146c601-c313-40bb-9119-52c4844ae496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605132270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1605132270
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.929104591
Short name T807
Test name
Test status
Simulation time 116289992 ps
CPU time 1.19 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 218372 kb
Host smart-e8d391a6-7523-4899-b531-29e276f11484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929104591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.929104591
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.3984675632
Short name T304
Test name
Test status
Simulation time 84827341 ps
CPU time 1.29 seconds
Started Jun 09 01:55:04 PM PDT 24
Finished Jun 09 01:55:06 PM PDT 24
Peak memory 218604 kb
Host smart-e4a6ddaf-59b5-4de2-a462-414d06efb95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984675632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3984675632
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1965281467
Short name T313
Test name
Test status
Simulation time 66830147 ps
CPU time 0.98 seconds
Started Jun 09 01:55:03 PM PDT 24
Finished Jun 09 01:55:05 PM PDT 24
Peak memory 206480 kb
Host smart-a7aafed6-3b4a-41e2-afde-fc6738e5159c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965281467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1965281467
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3168154358
Short name T195
Test name
Test status
Simulation time 12757096 ps
CPU time 0.94 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:58 PM PDT 24
Peak memory 207276 kb
Host smart-3872ee97-c5cb-435d-9430-08844d3538cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168154358 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3168154358
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2269916385
Short name T755
Test name
Test status
Simulation time 27134205 ps
CPU time 1.18 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 218164 kb
Host smart-82bfd20b-4692-4650-abc4-be1f5193a620
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269916385 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2269916385
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.841875953
Short name T577
Test name
Test status
Simulation time 46855200 ps
CPU time 0.99 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 218620 kb
Host smart-6a83d73e-7892-476c-8b7d-095213f4edfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841875953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.841875953
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.461434757
Short name T728
Test name
Test status
Simulation time 41771346 ps
CPU time 1.49 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 218264 kb
Host smart-7fe96a4b-ed9c-4215-9bf1-29d1b0e22726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461434757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.461434757
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2367547265
Short name T35
Test name
Test status
Simulation time 22409151 ps
CPU time 1.09 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215852 kb
Host smart-a236f81c-00c9-4ce1-9456-a24431f56237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367547265 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2367547265
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3971359625
Short name T702
Test name
Test status
Simulation time 25116215 ps
CPU time 0.92 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:58 PM PDT 24
Peak memory 215180 kb
Host smart-46db4f0b-c73a-45fb-ad10-cb5cb9feb4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971359625 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3971359625
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.945761882
Short name T557
Test name
Test status
Simulation time 1732010589 ps
CPU time 3.29 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:55:00 PM PDT 24
Peak memory 216688 kb
Host smart-6394f5c8-1daf-4860-ba5f-63fa26faceb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945761882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.945761882
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3838979607
Short name T634
Test name
Test status
Simulation time 113271441558 ps
CPU time 759.11 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 02:07:36 PM PDT 24
Peak memory 221016 kb
Host smart-50fdca60-81db-4a91-9dce-b6544b99d5e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838979607 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3838979607
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.477912856
Short name T420
Test name
Test status
Simulation time 72633406 ps
CPU time 1.52 seconds
Started Jun 09 01:56:31 PM PDT 24
Finished Jun 09 01:56:33 PM PDT 24
Peak memory 215200 kb
Host smart-9c743fb7-ad2b-4775-9ba0-5ce2c7518de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477912856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.477912856
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1725480398
Short name T331
Test name
Test status
Simulation time 96434997 ps
CPU time 2.13 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 219808 kb
Host smart-1afae842-d4dd-48d2-b43c-8c8838bc0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725480398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1725480398
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.459147090
Short name T524
Test name
Test status
Simulation time 210762087 ps
CPU time 1.28 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 216864 kb
Host smart-a339008a-a7e4-4fe3-9fe8-f4d57989ef25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459147090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.459147090
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4117193176
Short name T464
Test name
Test status
Simulation time 40901000 ps
CPU time 1.64 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 215124 kb
Host smart-710ea0e8-7ce5-4b5e-9fa2-9d427a7c8508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117193176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4117193176
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.538482127
Short name T366
Test name
Test status
Simulation time 76830065 ps
CPU time 1.23 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 218208 kb
Host smart-c0266141-d9c0-471b-9579-4db266672832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538482127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.538482127
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1409469902
Short name T603
Test name
Test status
Simulation time 63685496 ps
CPU time 1.38 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 218224 kb
Host smart-8eb72b55-ad58-4eb4-a20c-20ebfcdbd756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409469902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1409469902
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.552664881
Short name T743
Test name
Test status
Simulation time 94092885 ps
CPU time 1.23 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 219352 kb
Host smart-f0c6315f-dc95-4fa0-8929-386485392581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552664881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.552664881
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1663277854
Short name T829
Test name
Test status
Simulation time 198958460 ps
CPU time 2.85 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 219748 kb
Host smart-96d228b8-54b1-46c3-a0cb-9dff71579eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663277854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1663277854
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.640519950
Short name T416
Test name
Test status
Simulation time 265261674 ps
CPU time 1.72 seconds
Started Jun 09 01:56:38 PM PDT 24
Finished Jun 09 01:56:40 PM PDT 24
Peak memory 218828 kb
Host smart-69097df8-d37a-4c95-a58e-f22d1ee6cddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640519950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.640519950
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2349455075
Short name T561
Test name
Test status
Simulation time 79793204 ps
CPU time 1.92 seconds
Started Jun 09 01:56:15 PM PDT 24
Finished Jun 09 01:56:17 PM PDT 24
Peak memory 219648 kb
Host smart-5c510065-31a9-4204-9c6f-e9c1abe34711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349455075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2349455075
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1015740871
Short name T156
Test name
Test status
Simulation time 28431701 ps
CPU time 1.33 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 219428 kb
Host smart-a678cec3-6854-46bf-93a2-da5f1599f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015740871 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1015740871
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1042651343
Short name T309
Test name
Test status
Simulation time 49214721 ps
CPU time 0.94 seconds
Started Jun 09 01:54:59 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 206624 kb
Host smart-74bccb66-56bd-4181-ae6a-d6ef0c6d0d00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042651343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1042651343
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3443803581
Short name T751
Test name
Test status
Simulation time 10464226 ps
CPU time 0.93 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:58 PM PDT 24
Peak memory 216160 kb
Host smart-142140e4-0cd9-41f3-b45c-b7d5ee0c5b74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443803581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3443803581
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3719937016
Short name T530
Test name
Test status
Simulation time 47089587 ps
CPU time 1.21 seconds
Started Jun 09 01:54:56 PM PDT 24
Finished Jun 09 01:54:58 PM PDT 24
Peak memory 216660 kb
Host smart-951023f6-84bb-4567-a2e9-4616e4e951bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719937016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3719937016
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3480013353
Short name T323
Test name
Test status
Simulation time 18506166 ps
CPU time 1.13 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 224044 kb
Host smart-7ddeca8f-adb1-45e5-b9f6-8c44961dd836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480013353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3480013353
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2115122672
Short name T337
Test name
Test status
Simulation time 90372368 ps
CPU time 1.32 seconds
Started Jun 09 01:54:58 PM PDT 24
Finished Jun 09 01:54:59 PM PDT 24
Peak memory 218492 kb
Host smart-de139788-7c9f-49a9-9d8d-474fc63bc60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115122672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2115122672
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.22147875
Short name T482
Test name
Test status
Simulation time 25496241 ps
CPU time 0.99 seconds
Started Jun 09 01:54:55 PM PDT 24
Finished Jun 09 01:54:57 PM PDT 24
Peak memory 215884 kb
Host smart-82ae3c4d-8e2c-49aa-b3f5-724fa388b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22147875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.22147875
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2791845333
Short name T343
Test name
Test status
Simulation time 86146416 ps
CPU time 0.89 seconds
Started Jun 09 01:55:04 PM PDT 24
Finished Jun 09 01:55:05 PM PDT 24
Peak memory 215176 kb
Host smart-f082c702-7c7a-4990-80ad-3036445becd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791845333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2791845333
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1972560322
Short name T209
Test name
Test status
Simulation time 309212827 ps
CPU time 5.9 seconds
Started Jun 09 01:54:57 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 216952 kb
Host smart-07c84b8d-878f-4f77-9fc1-dce9931d5731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972560322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1972560322
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2530445797
Short name T267
Test name
Test status
Simulation time 160452221055 ps
CPU time 1886.23 seconds
Started Jun 09 01:54:58 PM PDT 24
Finished Jun 09 02:26:25 PM PDT 24
Peak memory 226088 kb
Host smart-2fc4aa97-a821-4609-9f6f-2289581023b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530445797 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2530445797
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2178270496
Short name T281
Test name
Test status
Simulation time 240833275 ps
CPU time 3.61 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 219720 kb
Host smart-713db9e3-cc1f-449e-abb4-2fa23ecf41b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178270496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2178270496
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.510440479
Short name T607
Test name
Test status
Simulation time 322842510 ps
CPU time 1.19 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216872 kb
Host smart-00f45e2a-574e-4848-9b58-6d5dbd768046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510440479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.510440479
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2009117486
Short name T782
Test name
Test status
Simulation time 115685171 ps
CPU time 1.29 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 216864 kb
Host smart-17486bf6-559b-45f3-80a1-ae866ad75968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009117486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2009117486
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.778168552
Short name T452
Test name
Test status
Simulation time 37176296 ps
CPU time 1.45 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 217004 kb
Host smart-72d82ed0-c0f4-4612-8af1-2f9af5ba0fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778168552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.778168552
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2963267757
Short name T602
Test name
Test status
Simulation time 73726542 ps
CPU time 1.24 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 216832 kb
Host smart-f9b8d3d7-fcf6-4ace-aac3-8e564e1a6f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963267757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2963267757
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2979380193
Short name T262
Test name
Test status
Simulation time 56369470 ps
CPU time 1.8 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 217212 kb
Host smart-2a5c6261-daf8-479e-975f-55a67876db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979380193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2979380193
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.452789204
Short name T763
Test name
Test status
Simulation time 40782730 ps
CPU time 1.12 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 218112 kb
Host smart-5fd0b748-0e8f-4040-bf10-9147af6e4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452789204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.452789204
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.220892351
Short name T798
Test name
Test status
Simulation time 102105064 ps
CPU time 1.48 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218764 kb
Host smart-e0f50a2f-fe9b-4fe0-b93d-dd58a6bced83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220892351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.220892351
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3045300186
Short name T811
Test name
Test status
Simulation time 119561324 ps
CPU time 2 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 219620 kb
Host smart-9383af6e-9f86-47e5-965e-8573c69fda8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045300186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3045300186
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2713874657
Short name T711
Test name
Test status
Simulation time 87528084 ps
CPU time 1.19 seconds
Started Jun 09 01:56:20 PM PDT 24
Finished Jun 09 01:56:22 PM PDT 24
Peak memory 217032 kb
Host smart-817e7e48-ff27-4d1f-a602-436cb84a8971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713874657 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2713874657
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1598033899
Short name T95
Test name
Test status
Simulation time 23271618 ps
CPU time 1.12 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 219572 kb
Host smart-927a0fe8-7067-466c-9d8f-c87d7c9bbedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598033899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1598033899
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.3361835988
Short name T479
Test name
Test status
Simulation time 54458998 ps
CPU time 0.96 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 206552 kb
Host smart-e64288f1-96b3-4e27-aacc-b2e191ca05dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361835988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3361835988
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2310878100
Short name T698
Test name
Test status
Simulation time 14770300 ps
CPU time 0.94 seconds
Started Jun 09 01:55:04 PM PDT 24
Finished Jun 09 01:55:05 PM PDT 24
Peak memory 216324 kb
Host smart-510fc4df-b13e-4257-93f1-8e7fa72764b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310878100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2310878100
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1268982533
Short name T560
Test name
Test status
Simulation time 52980322 ps
CPU time 1.16 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 216712 kb
Host smart-ebac5525-ba52-4e1c-8a2b-964dc0b8c584
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268982533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1268982533
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1939164256
Short name T764
Test name
Test status
Simulation time 22230627 ps
CPU time 0.91 seconds
Started Jun 09 01:54:59 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 218636 kb
Host smart-0ccab3a9-80c6-4528-a81e-96995e8f2b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939164256 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1939164256
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.2384024160
Short name T38
Test name
Test status
Simulation time 63944981 ps
CPU time 1.78 seconds
Started Jun 09 01:55:03 PM PDT 24
Finished Jun 09 01:55:05 PM PDT 24
Peak memory 218032 kb
Host smart-7c0d2d0c-9360-459d-ae29-732852e5da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384024160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2384024160
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.2774087292
Short name T494
Test name
Test status
Simulation time 46177437 ps
CPU time 1 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 224048 kb
Host smart-ffb18fd0-ad94-4d12-8d3c-c986de4d1803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774087292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2774087292
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2118361367
Short name T677
Test name
Test status
Simulation time 39003396 ps
CPU time 0.9 seconds
Started Jun 09 01:55:03 PM PDT 24
Finished Jun 09 01:55:04 PM PDT 24
Peak memory 215228 kb
Host smart-4a3a1839-420f-4742-9774-bdb6d07b3667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118361367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2118361367
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3926583984
Short name T444
Test name
Test status
Simulation time 320684003 ps
CPU time 6.58 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 216904 kb
Host smart-4bfa3903-85f4-4e8a-b4f4-ab4efab296a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926583984 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3926583984
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1265750115
Short name T695
Test name
Test status
Simulation time 357142487380 ps
CPU time 2172.34 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 02:31:15 PM PDT 24
Peak memory 227332 kb
Host smart-bb97a016-f67c-4651-bf99-3adc7f93fdcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265750115 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1265750115
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2074831420
Short name T817
Test name
Test status
Simulation time 331183736 ps
CPU time 4.45 seconds
Started Jun 09 01:56:26 PM PDT 24
Finished Jun 09 01:56:31 PM PDT 24
Peak memory 219236 kb
Host smart-2f1f7272-af45-4648-81c0-4dcc58fc0c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074831420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2074831420
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3926628599
Short name T730
Test name
Test status
Simulation time 34941342 ps
CPU time 1.06 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216876 kb
Host smart-50c4079f-cd05-4811-900a-a79366eaacaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926628599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3926628599
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3014121769
Short name T350
Test name
Test status
Simulation time 99061550 ps
CPU time 1.17 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 217056 kb
Host smart-de698c27-4853-42cc-9cd9-7d9fa5610af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014121769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3014121769
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4149024661
Short name T629
Test name
Test status
Simulation time 114271937 ps
CPU time 1.02 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 216920 kb
Host smart-792fccb3-8c62-4ab0-813c-63319e10e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149024661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4149024661
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.25895220
Short name T693
Test name
Test status
Simulation time 106286115 ps
CPU time 1.27 seconds
Started Jun 09 01:56:30 PM PDT 24
Finished Jun 09 01:56:32 PM PDT 24
Peak memory 218372 kb
Host smart-b90a7fb1-be21-4131-9de9-ff790de87cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25895220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.25895220
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4009131430
Short name T562
Test name
Test status
Simulation time 62026298 ps
CPU time 1.27 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 216952 kb
Host smart-ef7bc9b8-b0dd-4fd5-ab3a-d2cecc8ac404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009131430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4009131430
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2467886469
Short name T342
Test name
Test status
Simulation time 123773095 ps
CPU time 1.05 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216980 kb
Host smart-0bfedf0a-8b23-4db5-9fd2-fe469ba8cb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467886469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2467886469
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2130970808
Short name T324
Test name
Test status
Simulation time 67937826 ps
CPU time 1.1 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 216908 kb
Host smart-2071c31b-bd4c-4677-b54f-507c5b3a8e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130970808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2130970808
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3938854795
Short name T650
Test name
Test status
Simulation time 53114028 ps
CPU time 1.15 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 218068 kb
Host smart-d6ca0e47-5240-419a-b9fa-08120f9e47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938854795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3938854795
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3109718945
Short name T719
Test name
Test status
Simulation time 48323851 ps
CPU time 1.49 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 217048 kb
Host smart-9aad45fb-a6ee-47ca-8b3e-73e2e6e4236e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109718945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3109718945
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2494647305
Short name T145
Test name
Test status
Simulation time 42763277 ps
CPU time 1.13 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 218040 kb
Host smart-5d5b4293-bd5a-4bf9-86d4-6b7af53f2d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494647305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2494647305
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3237379313
Short name T583
Test name
Test status
Simulation time 13522925 ps
CPU time 0.9 seconds
Started Jun 09 01:55:03 PM PDT 24
Finished Jun 09 01:55:04 PM PDT 24
Peak memory 206484 kb
Host smart-a1994bfd-616c-44f2-ac08-86cd82ad1960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237379313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3237379313
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3687047609
Short name T192
Test name
Test status
Simulation time 13970573 ps
CPU time 0.9 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 215444 kb
Host smart-f002678a-1c86-48ee-ac38-3927003f8221
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687047609 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3687047609
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2718530046
Short name T515
Test name
Test status
Simulation time 59233654 ps
CPU time 1.14 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 218416 kb
Host smart-fbc80c4c-f080-46a0-8bb2-9ff5952f17ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718530046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2718530046
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2044721472
Short name T176
Test name
Test status
Simulation time 19746710 ps
CPU time 1.08 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 218480 kb
Host smart-0f354514-3559-475b-975c-71a6355887e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044721472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2044721472
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.478045165
Short name T746
Test name
Test status
Simulation time 88492046 ps
CPU time 1.22 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 218504 kb
Host smart-3756ee0d-166f-4d17-b54b-62658df05441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478045165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.478045165
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2056910187
Short name T82
Test name
Test status
Simulation time 34128997 ps
CPU time 0.93 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 215732 kb
Host smart-51fbfe6e-d148-4b3b-a9b9-33dd308f2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056910187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2056910187
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2185799040
Short name T447
Test name
Test status
Simulation time 17411139 ps
CPU time 0.97 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 215152 kb
Host smart-98b706f4-3ee6-4d78-9c28-0a39955a414e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185799040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2185799040
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2396735582
Short name T571
Test name
Test status
Simulation time 42862541 ps
CPU time 1.02 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 01:55:03 PM PDT 24
Peak memory 206204 kb
Host smart-686a3d67-af73-4d55-b6b1-eabca70aca7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396735582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2396735582
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/250.edn_genbits.862482914
Short name T722
Test name
Test status
Simulation time 71736968 ps
CPU time 2.73 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219896 kb
Host smart-bd2ed2ad-14ca-499b-aa9a-09273928e00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862482914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.862482914
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2793490373
Short name T453
Test name
Test status
Simulation time 90098636 ps
CPU time 2.93 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 215092 kb
Host smart-549acd1e-4eb9-4738-a87e-9af88d5c575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793490373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2793490373
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1207198284
Short name T826
Test name
Test status
Simulation time 177611335 ps
CPU time 2.51 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 217116 kb
Host smart-ba30ed6f-3c34-4950-943b-ab17e520a6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207198284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1207198284
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3315481788
Short name T713
Test name
Test status
Simulation time 62543781 ps
CPU time 1.14 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 216880 kb
Host smart-601ca665-6977-400d-9f91-1b689eb8727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315481788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3315481788
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1056579687
Short name T308
Test name
Test status
Simulation time 45158198 ps
CPU time 1.45 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 215204 kb
Host smart-3abd9f4f-f3b6-4501-beed-f13871b7f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056579687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1056579687
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.248621118
Short name T485
Test name
Test status
Simulation time 203180757 ps
CPU time 1.5 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 218336 kb
Host smart-662d8e09-27b2-4fa9-8251-46f04fa25b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248621118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.248621118
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1161220972
Short name T463
Test name
Test status
Simulation time 65701825 ps
CPU time 1.16 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 216904 kb
Host smart-756e6f86-166d-4c58-9cb0-452015821a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161220972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1161220972
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.560188706
Short name T462
Test name
Test status
Simulation time 137036650 ps
CPU time 1.88 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 218152 kb
Host smart-a780c3c7-e244-4eb4-bd1f-5b9ccbabcec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560188706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.560188706
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.710751895
Short name T819
Test name
Test status
Simulation time 53053669 ps
CPU time 1.1 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:47 PM PDT 24
Peak memory 216904 kb
Host smart-c1115fe7-8b6a-490d-9c20-9bcb159d23f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710751895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.710751895
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4083963540
Short name T703
Test name
Test status
Simulation time 176747755 ps
CPU time 0.94 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 217032 kb
Host smart-f91d212e-37c9-479b-95cd-4fed24a90f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083963540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4083963540
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.3225293991
Short name T318
Test name
Test status
Simulation time 43798509 ps
CPU time 0.86 seconds
Started Jun 09 01:55:01 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 206232 kb
Host smart-ef66b180-7892-4d6f-8d92-0edf9324063a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225293991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3225293991
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2277482058
Short name T194
Test name
Test status
Simulation time 43660107 ps
CPU time 0.83 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:13 PM PDT 24
Peak memory 216100 kb
Host smart-01f398b8-5330-42ae-8908-ae2d19ac8766
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277482058 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2277482058
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2493795933
Short name T121
Test name
Test status
Simulation time 74183077 ps
CPU time 1.08 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:14 PM PDT 24
Peak memory 215504 kb
Host smart-9acd5d2b-26b2-4496-9998-a6d23fce50e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493795933 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2493795933
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1402883921
Short name T407
Test name
Test status
Simulation time 30790579 ps
CPU time 1.27 seconds
Started Jun 09 01:54:59 PM PDT 24
Finished Jun 09 01:55:01 PM PDT 24
Peak memory 219596 kb
Host smart-986ccbf7-2409-4760-b071-86699f877879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402883921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1402883921
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2176128871
Short name T76
Test name
Test status
Simulation time 44678605 ps
CPU time 1.35 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 218552 kb
Host smart-86083876-11c1-4b79-93a3-149d1b5ed20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176128871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2176128871
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2601575021
Short name T549
Test name
Test status
Simulation time 25777088 ps
CPU time 0.94 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:13 PM PDT 24
Peak memory 215344 kb
Host smart-906d6224-4544-466e-94af-a24a9cddf2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601575021 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2601575021
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3393271093
Short name T439
Test name
Test status
Simulation time 25519851 ps
CPU time 0.96 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 215164 kb
Host smart-9989593e-c29c-4e04-8ca4-8066bbf13364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393271093 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3393271093
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1442772498
Short name T551
Test name
Test status
Simulation time 495849785 ps
CPU time 5.23 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 215272 kb
Host smart-0446bfa8-e88c-4f58-9b16-94d11c56562e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442772498 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1442772498
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3825099705
Short name T205
Test name
Test status
Simulation time 66419956410 ps
CPU time 703.09 seconds
Started Jun 09 01:55:02 PM PDT 24
Finished Jun 09 02:06:45 PM PDT 24
Peak memory 219684 kb
Host smart-074a3a0c-45c2-495d-a17e-ed1d506fbfae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825099705 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3825099705
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.161357440
Short name T412
Test name
Test status
Simulation time 109576422 ps
CPU time 2.43 seconds
Started Jun 09 01:56:42 PM PDT 24
Finished Jun 09 01:56:45 PM PDT 24
Peak memory 219696 kb
Host smart-47b4da65-0f92-4d89-a1d1-72581cfde324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161357440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.161357440
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.987277278
Short name T499
Test name
Test status
Simulation time 38057467 ps
CPU time 1.17 seconds
Started Jun 09 01:56:40 PM PDT 24
Finished Jun 09 01:56:42 PM PDT 24
Peak memory 219636 kb
Host smart-b8b4d0f8-83a2-4d5b-a06b-ff9ab6a9f6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987277278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.987277278
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1301612989
Short name T700
Test name
Test status
Simulation time 61710658 ps
CPU time 1.15 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 218516 kb
Host smart-d5b99a49-fe17-43e3-b7f4-a463e2e075f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301612989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1301612989
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.911824391
Short name T307
Test name
Test status
Simulation time 46400391 ps
CPU time 1.64 seconds
Started Jun 09 01:56:43 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 219568 kb
Host smart-9fe71084-c513-445d-b680-adcba9030af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911824391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.911824391
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4052900619
Short name T820
Test name
Test status
Simulation time 253954229 ps
CPU time 1.82 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 218552 kb
Host smart-8750a979-0061-4c99-80f6-9bce3d82080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052900619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4052900619
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2362645745
Short name T261
Test name
Test status
Simulation time 120252200 ps
CPU time 1.81 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 219740 kb
Host smart-2fc1e2b2-2f46-404d-ab4e-be89f4f3cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362645745 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2362645745
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3660515940
Short name T63
Test name
Test status
Simulation time 1110222743 ps
CPU time 8.13 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 218268 kb
Host smart-1f0d43fb-facc-49ba-928b-22908b2710df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660515940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3660515940
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2483330553
Short name T276
Test name
Test status
Simulation time 57921611 ps
CPU time 1.07 seconds
Started Jun 09 01:56:38 PM PDT 24
Finished Jun 09 01:56:39 PM PDT 24
Peak memory 216916 kb
Host smart-e12a70ee-a392-4e92-9d70-85ca865d9159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483330553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2483330553
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.848510456
Short name T272
Test name
Test status
Simulation time 43767336 ps
CPU time 1.47 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 216704 kb
Host smart-c0ac0bee-cefb-4440-bec2-6a48a508eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848510456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.848510456
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3353497550
Short name T828
Test name
Test status
Simulation time 158260793 ps
CPU time 1.55 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 218272 kb
Host smart-ae1d175a-d47d-49d0-8639-709e18c83b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353497550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3353497550
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3607611375
Short name T247
Test name
Test status
Simulation time 153182051 ps
CPU time 0.84 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 214508 kb
Host smart-9227c64a-d862-436e-821b-b76a3c67487f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607611375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3607611375
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3539759443
Short name T137
Test name
Test status
Simulation time 12953204 ps
CPU time 0.95 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:06 PM PDT 24
Peak memory 215476 kb
Host smart-197ebeef-84df-4663-b0f4-a860b4188515
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539759443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3539759443
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.2158200268
Short name T107
Test name
Test status
Simulation time 41867205 ps
CPU time 1.25 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 216876 kb
Host smart-67f50497-b6d0-4e2d-b8a3-ba6f9840845a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158200268 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.2158200268
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.997952203
Short name T738
Test name
Test status
Simulation time 30018313 ps
CPU time 1.38 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 225868 kb
Host smart-272fbab5-60b4-487b-b0c2-b2f2d7eef8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997952203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.997952203
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4163368376
Short name T284
Test name
Test status
Simulation time 146556439 ps
CPU time 1.5 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 218572 kb
Host smart-66961b83-3f82-4acf-9b35-a3a072b63f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163368376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4163368376
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.4190025108
Short name T639
Test name
Test status
Simulation time 38574035 ps
CPU time 0.88 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 215176 kb
Host smart-b2fe9abb-4baf-4d3d-9bbe-b18c143635b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190025108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.4190025108
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2521786555
Short name T585
Test name
Test status
Simulation time 96218562 ps
CPU time 0.88 seconds
Started Jun 09 01:55:00 PM PDT 24
Finished Jun 09 01:55:02 PM PDT 24
Peak memory 215204 kb
Host smart-f2b975c6-77c5-4ad0-b213-ac415c37a8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521786555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2521786555
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1556825613
Short name T448
Test name
Test status
Simulation time 281382850 ps
CPU time 5.6 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:11 PM PDT 24
Peak memory 215272 kb
Host smart-3c75eb48-318e-4ad3-8874-1abd7b19428a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556825613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1556825613
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/270.edn_genbits.1442751355
Short name T477
Test name
Test status
Simulation time 213975825 ps
CPU time 1.13 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 217056 kb
Host smart-4b19083b-3ab1-438a-8a67-ba4a8cb34531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442751355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1442751355
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3007840506
Short name T519
Test name
Test status
Simulation time 58741328 ps
CPU time 1.33 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219004 kb
Host smart-bf2aab84-58d2-46df-9776-054ec71eaef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007840506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3007840506
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2857477775
Short name T781
Test name
Test status
Simulation time 35332191 ps
CPU time 1.45 seconds
Started Jun 09 01:56:41 PM PDT 24
Finished Jun 09 01:56:43 PM PDT 24
Peak memory 218024 kb
Host smart-89737351-7cd7-4a9a-9972-e87ba3952961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857477775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2857477775
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1158810649
Short name T217
Test name
Test status
Simulation time 44542235 ps
CPU time 1.5 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 216852 kb
Host smart-0ede6695-1c23-4a7b-8b68-66118ca1ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158810649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1158810649
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.347140451
Short name T644
Test name
Test status
Simulation time 36091761 ps
CPU time 1.34 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 216872 kb
Host smart-a529dc65-df2d-4ed8-af3b-d4ccbdb750a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347140451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.347140451
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3622816746
Short name T374
Test name
Test status
Simulation time 70894717 ps
CPU time 1.53 seconds
Started Jun 09 01:56:45 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218308 kb
Host smart-21fd9afc-c656-4cd1-8cb5-410d2633d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622816746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3622816746
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1771343515
Short name T11
Test name
Test status
Simulation time 30165931 ps
CPU time 1.29 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219052 kb
Host smart-19db87cb-ae00-41ee-994f-4c10ba084710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771343515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1771343515
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.4098657388
Short name T715
Test name
Test status
Simulation time 58752676 ps
CPU time 1.08 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 216956 kb
Host smart-6b0c9447-fedf-4b87-af4b-e87e209d8afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098657388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.4098657388
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2880819805
Short name T628
Test name
Test status
Simulation time 45026234 ps
CPU time 1.23 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 219764 kb
Host smart-a8ac477c-ec88-4171-93d9-ca5ee2fa0ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880819805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2880819805
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1927604373
Short name T833
Test name
Test status
Simulation time 42220570 ps
CPU time 1.6 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 218148 kb
Host smart-3385db98-4d45-4e99-9261-b3833fd0d24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927604373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1927604373
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert_test.2406493496
Short name T488
Test name
Test status
Simulation time 34992959 ps
CPU time 0.99 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 206608 kb
Host smart-6c1682f6-16bb-433c-b85b-19bbbe55d563
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406493496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2406493496
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2349652419
Short name T326
Test name
Test status
Simulation time 53502353 ps
CPU time 1.08 seconds
Started Jun 09 01:55:04 PM PDT 24
Finished Jun 09 01:55:05 PM PDT 24
Peak memory 216880 kb
Host smart-8f9e0763-6d34-4a01-bb10-b79f72470e9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349652419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2349652419
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3313218085
Short name T664
Test name
Test status
Simulation time 33019315 ps
CPU time 1.01 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 219928 kb
Host smart-e4b56d1f-3cc8-447e-a43d-6c4a3ddfe0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313218085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3313218085
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.421499286
Short name T306
Test name
Test status
Simulation time 68341185 ps
CPU time 2.38 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 219536 kb
Host smart-b29b087d-3c8c-4e71-b851-af29cd68c9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421499286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.421499286
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2571437217
Short name T44
Test name
Test status
Simulation time 23036876 ps
CPU time 1.08 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 215372 kb
Host smart-1c888761-f0f6-44c5-bbbf-18a0ec3c330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571437217 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2571437217
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2935657124
Short name T437
Test name
Test status
Simulation time 24917620 ps
CPU time 0.98 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 215184 kb
Host smart-25133487-9ab4-438a-b783-03aae42e83d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935657124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2935657124
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.1059465062
Short name T750
Test name
Test status
Simulation time 533023289 ps
CPU time 5.96 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 216816 kb
Host smart-e4fed253-cbf9-4581-9398-84379e0a6cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059465062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1059465062
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1652246731
Short name T37
Test name
Test status
Simulation time 171687105596 ps
CPU time 892.2 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 02:10:01 PM PDT 24
Peak memory 220624 kb
Host smart-6294fcad-fa7a-4d08-9444-fb4ae7b9ccf3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652246731 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1652246731
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1193475152
Short name T288
Test name
Test status
Simulation time 105038104 ps
CPU time 1.29 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 218492 kb
Host smart-f0585e2d-edb3-4445-ada3-b8c00b250514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193475152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1193475152
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1721892633
Short name T838
Test name
Test status
Simulation time 40448185 ps
CPU time 1.42 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 217988 kb
Host smart-519fcc9c-38e5-487e-b8c6-1ade02942a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721892633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1721892633
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.695759701
Short name T543
Test name
Test status
Simulation time 53518843 ps
CPU time 1.19 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 218124 kb
Host smart-e0e1680b-0263-4244-9a4b-a9e351fd2e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695759701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.695759701
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3410764092
Short name T461
Test name
Test status
Simulation time 27568087 ps
CPU time 1.24 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 219428 kb
Host smart-a3677770-a9cb-43ce-8830-f4d49b0b2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410764092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3410764092
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3040556106
Short name T282
Test name
Test status
Simulation time 56632330 ps
CPU time 1.23 seconds
Started Jun 09 01:56:46 PM PDT 24
Finished Jun 09 01:56:48 PM PDT 24
Peak memory 218192 kb
Host smart-7f054bff-9698-413a-9049-da63ed9b37c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040556106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3040556106
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3920129559
Short name T279
Test name
Test status
Simulation time 33808945 ps
CPU time 1.47 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 217976 kb
Host smart-c9111be8-3000-4bcf-acf4-a2f10f7f80e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920129559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3920129559
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.3486621051
Short name T376
Test name
Test status
Simulation time 149921351 ps
CPU time 1.04 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 216880 kb
Host smart-b145007b-5834-478d-a654-8cefbc993fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486621051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3486621051
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3800492221
Short name T518
Test name
Test status
Simulation time 239228853 ps
CPU time 1.04 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 216768 kb
Host smart-ae5137f9-eeed-4506-b0f5-9452af5d6173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800492221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3800492221
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4151878363
Short name T633
Test name
Test status
Simulation time 47501190 ps
CPU time 1.23 seconds
Started Jun 09 01:56:51 PM PDT 24
Finished Jun 09 01:56:53 PM PDT 24
Peak memory 216984 kb
Host smart-7e480879-00aa-4e97-8e6f-04376423933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151878363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4151878363
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2830546426
Short name T72
Test name
Test status
Simulation time 119519723 ps
CPU time 1.35 seconds
Started Jun 09 01:56:44 PM PDT 24
Finished Jun 09 01:56:46 PM PDT 24
Peak memory 219920 kb
Host smart-cdd2b1f2-6d12-4fd6-b954-ea976c60c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830546426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2830546426
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.1779977251
Short name T777
Test name
Test status
Simulation time 63942820 ps
CPU time 0.96 seconds
Started Jun 09 01:55:04 PM PDT 24
Finished Jun 09 01:55:06 PM PDT 24
Peak memory 214696 kb
Host smart-9f9d0e55-dfac-453f-a180-735ef4b572eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779977251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1779977251
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1402046074
Short name T193
Test name
Test status
Simulation time 19124531 ps
CPU time 0.88 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 215296 kb
Host smart-dea37826-5e13-431d-930a-75d8397e4c39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402046074 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1402046074
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3731904540
Short name T250
Test name
Test status
Simulation time 100685674 ps
CPU time 1.13 seconds
Started Jun 09 01:55:05 PM PDT 24
Finished Jun 09 01:55:07 PM PDT 24
Peak memory 216924 kb
Host smart-e72c84fb-4a51-4bd5-862d-bbdb355295b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731904540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3731904540
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.4091472137
Short name T616
Test name
Test status
Simulation time 35514005 ps
CPU time 1.57 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 01:55:10 PM PDT 24
Peak memory 225816 kb
Host smart-a79b3d79-40f9-40ef-a09c-ffdd1b397e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091472137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.4091472137
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.468348624
Short name T552
Test name
Test status
Simulation time 39565292 ps
CPU time 1.65 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 218076 kb
Host smart-6769feb9-469b-49ce-8ec6-d5a230c2fd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468348624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.468348624
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.627810830
Short name T56
Test name
Test status
Simulation time 34209185 ps
CPU time 1.05 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 224100 kb
Host smart-81c1b827-e5f2-42dd-a878-e972e66b0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627810830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.627810830
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.863131261
Short name T379
Test name
Test status
Simulation time 32033145 ps
CPU time 0.96 seconds
Started Jun 09 01:55:06 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 215208 kb
Host smart-c4c96843-6da2-4266-b375-4c7ac51b243d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863131261 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.863131261
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3809865540
Short name T759
Test name
Test status
Simulation time 276213803 ps
CPU time 5.32 seconds
Started Jun 09 01:55:09 PM PDT 24
Finished Jun 09 01:55:14 PM PDT 24
Peak memory 216712 kb
Host smart-449dba6d-783e-4aca-a772-b9d3e079728f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809865540 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3809865540
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3963632071
Short name T359
Test name
Test status
Simulation time 20210304072 ps
CPU time 258.76 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:59:26 PM PDT 24
Peak memory 218116 kb
Host smart-0dcf21a8-edbd-4a8a-9052-294d9e6bae67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963632071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3963632071
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.633369996
Short name T806
Test name
Test status
Simulation time 93304238 ps
CPU time 1.23 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 217132 kb
Host smart-72e33292-4764-4cb8-9bc8-5771f035d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633369996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.633369996
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.694286352
Short name T349
Test name
Test status
Simulation time 46012046 ps
CPU time 1.03 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 216948 kb
Host smart-96f30e6f-82b8-4658-be4c-77ee0727e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694286352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.694286352
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2082837112
Short name T599
Test name
Test status
Simulation time 57481631 ps
CPU time 1.25 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 216944 kb
Host smart-825f62d1-296f-45ff-a15f-5783cd7a5023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082837112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2082837112
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2232192219
Short name T536
Test name
Test status
Simulation time 108273613 ps
CPU time 1.24 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 216872 kb
Host smart-a47b7e03-ae67-456d-8c3c-e06e47492dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232192219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2232192219
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3287816724
Short name T581
Test name
Test status
Simulation time 121216993 ps
CPU time 1.39 seconds
Started Jun 09 01:56:48 PM PDT 24
Finished Jun 09 01:56:50 PM PDT 24
Peak memory 218404 kb
Host smart-cd1c4198-52fc-47dd-a7ec-49bfdf8b0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287816724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3287816724
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1870216051
Short name T428
Test name
Test status
Simulation time 60595862 ps
CPU time 1.29 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 217056 kb
Host smart-1f0d5049-9ad0-4168-93b9-247c3a75a254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870216051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1870216051
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3103377330
Short name T749
Test name
Test status
Simulation time 43777087 ps
CPU time 1.52 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 218128 kb
Host smart-de4861ab-d0c6-4c2d-ad49-1178992e0a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103377330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3103377330
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2541379899
Short name T486
Test name
Test status
Simulation time 80467033 ps
CPU time 1.2 seconds
Started Jun 09 01:56:50 PM PDT 24
Finished Jun 09 01:56:52 PM PDT 24
Peak memory 216836 kb
Host smart-35fc64a2-f4ef-4403-a481-48cb9cc71b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541379899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2541379899
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1567915187
Short name T445
Test name
Test status
Simulation time 62264287 ps
CPU time 0.98 seconds
Started Jun 09 01:56:49 PM PDT 24
Finished Jun 09 01:56:51 PM PDT 24
Peak memory 217000 kb
Host smart-bbe298d0-7dc8-41cf-a7e2-632705573279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567915187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1567915187
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2656441184
Short name T403
Test name
Test status
Simulation time 111585022 ps
CPU time 1.31 seconds
Started Jun 09 01:56:47 PM PDT 24
Finished Jun 09 01:56:49 PM PDT 24
Peak memory 217012 kb
Host smart-49085352-85f3-48c6-a170-8ef24d8454c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656441184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2656441184
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4173792065
Short name T140
Test name
Test status
Simulation time 173402691 ps
CPU time 1.23 seconds
Started Jun 09 01:54:16 PM PDT 24
Finished Jun 09 01:54:18 PM PDT 24
Peak memory 215576 kb
Host smart-265f37e3-aed2-48eb-bc4e-b9e9175d20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173792065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4173792065
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2195585872
Short name T666
Test name
Test status
Simulation time 54714275 ps
CPU time 0.9 seconds
Started Jun 09 01:54:21 PM PDT 24
Finished Jun 09 01:54:22 PM PDT 24
Peak memory 206600 kb
Host smart-00b2fd1a-4315-409e-bde5-a4f68fc99489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195585872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2195585872
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.2356743324
Short name T636
Test name
Test status
Simulation time 11202953 ps
CPU time 0.92 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:20 PM PDT 24
Peak memory 215844 kb
Host smart-245b5065-b420-47fa-9162-89a3a46a1c6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356743324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2356743324
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.915277482
Short name T108
Test name
Test status
Simulation time 115922054 ps
CPU time 1.24 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 216820 kb
Host smart-715443ba-52cc-4823-83a3-ff62e59482db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915277482 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.915277482
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.170449188
Short name T441
Test name
Test status
Simulation time 77570289 ps
CPU time 1.12 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 219740 kb
Host smart-8714b2e9-8fc6-4df1-80be-f5a29d411356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170449188 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.170449188
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1064726688
Short name T496
Test name
Test status
Simulation time 57716325 ps
CPU time 1.32 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:17 PM PDT 24
Peak memory 217980 kb
Host smart-085160c1-80fd-4032-b266-50216080c608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064726688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1064726688
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1004088742
Short name T647
Test name
Test status
Simulation time 20434282 ps
CPU time 1.15 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:16 PM PDT 24
Peak memory 215968 kb
Host smart-cc25a264-750e-470b-80ea-e7571da671af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004088742 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1004088742
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2952543202
Short name T301
Test name
Test status
Simulation time 22579434 ps
CPU time 0.96 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 01:54:24 PM PDT 24
Peak memory 207032 kb
Host smart-24af7f5a-6088-48c0-9414-6d019714ce07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952543202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2952543202
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.747949509
Short name T333
Test name
Test status
Simulation time 37220670 ps
CPU time 0.89 seconds
Started Jun 09 01:54:22 PM PDT 24
Finished Jun 09 01:54:23 PM PDT 24
Peak memory 215032 kb
Host smart-991ae2be-e583-4497-a813-0abc822b1551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747949509 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.747949509
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1479114003
Short name T213
Test name
Test status
Simulation time 350297117 ps
CPU time 2.35 seconds
Started Jun 09 01:54:15 PM PDT 24
Finished Jun 09 01:54:18 PM PDT 24
Peak memory 215220 kb
Host smart-d643adbe-a085-4265-8146-577823ca5d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479114003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1479114003
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1751280098
Short name T575
Test name
Test status
Simulation time 186507770690 ps
CPU time 783.66 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 02:07:27 PM PDT 24
Peak memory 223568 kb
Host smart-9ff1e321-b2da-447c-b4dc-b1df8eb8ce06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751280098 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1751280098
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.2957071932
Short name T351
Test name
Test status
Simulation time 12371551 ps
CPU time 0.85 seconds
Started Jun 09 01:55:08 PM PDT 24
Finished Jun 09 01:55:09 PM PDT 24
Peak memory 205764 kb
Host smart-6ba99397-c16c-4cb6-a7cc-574a23a5e2d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957071932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2957071932
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1068226579
Short name T589
Test name
Test status
Simulation time 30644989 ps
CPU time 0.89 seconds
Started Jun 09 01:55:13 PM PDT 24
Finished Jun 09 01:55:14 PM PDT 24
Peak memory 216120 kb
Host smart-77090ee6-63a5-4fab-b8b3-f5553ff22396
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068226579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1068226579
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1468197879
Short name T40
Test name
Test status
Simulation time 31367026 ps
CPU time 1.15 seconds
Started Jun 09 01:55:10 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 216620 kb
Host smart-bbf2f60c-65e8-4e92-849c-717a98ab7971
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468197879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1468197879
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1949912181
Short name T183
Test name
Test status
Simulation time 38126959 ps
CPU time 1.11 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 218732 kb
Host smart-46c455ec-5f73-4a31-9550-d9c2944565ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949912181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1949912181
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1281422962
Short name T594
Test name
Test status
Simulation time 184903800 ps
CPU time 1.02 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 217052 kb
Host smart-153243b6-b9f1-463b-bde5-2f271868ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281422962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1281422962
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3662056535
Short name T57
Test name
Test status
Simulation time 34640631 ps
CPU time 1 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 223860 kb
Host smart-7593d735-d483-4fb8-8855-faa8f00edf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662056535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3662056535
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3284078137
Short name T631
Test name
Test status
Simulation time 46705116 ps
CPU time 0.93 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:08 PM PDT 24
Peak memory 215224 kb
Host smart-e5950138-ae35-4e48-8b1e-5c88eb171f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284078137 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3284078137
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.823606505
Short name T796
Test name
Test status
Simulation time 612757832 ps
CPU time 4.13 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 215204 kb
Host smart-3c6453a2-6eb2-4733-81f8-8ec6752cd77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823606505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.823606505
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.845649464
Short name T559
Test name
Test status
Simulation time 21381372696 ps
CPU time 168.68 seconds
Started Jun 09 01:55:07 PM PDT 24
Finished Jun 09 01:57:56 PM PDT 24
Peak memory 218412 kb
Host smart-3cec9797-e289-4190-9608-826a5edb8abb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845649464 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.845649464
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.3155686924
Short name T500
Test name
Test status
Simulation time 71823406 ps
CPU time 0.87 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 215072 kb
Host smart-9f4d7c0b-47fe-43a3-94ae-6d1a2d9def4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155686924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3155686924
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2914865682
Short name T709
Test name
Test status
Simulation time 91670503 ps
CPU time 1.02 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 218124 kb
Host smart-b9b7ba04-55ff-41fb-a214-baff3a380641
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914865682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2914865682
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3296374902
Short name T123
Test name
Test status
Simulation time 34173784 ps
CPU time 1.07 seconds
Started Jun 09 01:55:10 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 224016 kb
Host smart-1d27ea27-9162-4e90-a43c-985196fd7169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296374902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3296374902
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.156694359
Short name T688
Test name
Test status
Simulation time 33947364 ps
CPU time 1.41 seconds
Started Jun 09 01:55:13 PM PDT 24
Finished Jun 09 01:55:15 PM PDT 24
Peak memory 219592 kb
Host smart-31dd5306-8b62-4ce9-95aa-dce9403165e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156694359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.156694359
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.1654266690
Short name T426
Test name
Test status
Simulation time 39054998 ps
CPU time 0.88 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:13 PM PDT 24
Peak memory 215632 kb
Host smart-74ba4ee7-1afe-4dfe-ac06-a29da96e60a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654266690 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1654266690
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2540555152
Short name T472
Test name
Test status
Simulation time 16777380 ps
CPU time 1.04 seconds
Started Jun 09 01:55:10 PM PDT 24
Finished Jun 09 01:55:11 PM PDT 24
Peak memory 215204 kb
Host smart-3bfee391-f1a3-4a75-bd0a-3301bf6b3dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540555152 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2540555152
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3297631756
Short name T689
Test name
Test status
Simulation time 579454260 ps
CPU time 2.9 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:15 PM PDT 24
Peak memory 215180 kb
Host smart-e7d0ac07-d6aa-4ae5-8d56-096c3a33d858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297631756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3297631756
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1797047837
Short name T683
Test name
Test status
Simulation time 78602087312 ps
CPU time 916.16 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 02:10:28 PM PDT 24
Peak memory 222192 kb
Host smart-8ad2a3e9-5777-4a65-bb33-167ea3590e41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797047837 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1797047837
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.3094592988
Short name T338
Test name
Test status
Simulation time 20568469 ps
CPU time 1.06 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 214708 kb
Host smart-46e6dc6b-a345-47ef-9f28-f2422af48295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094592988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3094592988
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.273788364
Short name T187
Test name
Test status
Simulation time 99207264 ps
CPU time 0.94 seconds
Started Jun 09 01:55:16 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 216136 kb
Host smart-c5bbeece-f409-4a03-8c89-369db58e2399
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273788364 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.273788364
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1554234608
Short name T119
Test name
Test status
Simulation time 42029523 ps
CPU time 1.04 seconds
Started Jun 09 01:55:16 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 219360 kb
Host smart-4ab56760-0384-4dc6-a5d1-5652ec1ecfc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554234608 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1554234608
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.364187829
Short name T186
Test name
Test status
Simulation time 32558019 ps
CPU time 0.9 seconds
Started Jun 09 01:55:13 PM PDT 24
Finished Jun 09 01:55:14 PM PDT 24
Peak memory 218692 kb
Host smart-9075f885-f131-4e6b-9cd7-59f4a850379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364187829 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.364187829
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2820241989
Short name T207
Test name
Test status
Simulation time 208218662 ps
CPU time 1.27 seconds
Started Jun 09 01:55:09 PM PDT 24
Finished Jun 09 01:55:10 PM PDT 24
Peak memory 215224 kb
Host smart-33cc2b85-ae5a-4213-b39c-9babe320da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820241989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2820241989
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1205573480
Short name T34
Test name
Test status
Simulation time 23605110 ps
CPU time 0.95 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 215796 kb
Host smart-620b74ca-e729-4ae1-995c-17a869ed8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205573480 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1205573480
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2332173967
Short name T489
Test name
Test status
Simulation time 18845619 ps
CPU time 1.03 seconds
Started Jun 09 01:55:11 PM PDT 24
Finished Jun 09 01:55:12 PM PDT 24
Peak memory 215204 kb
Host smart-64059623-ee3d-463b-a0f6-5f0e52a37e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332173967 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2332173967
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.363954245
Short name T760
Test name
Test status
Simulation time 289356504 ps
CPU time 3.32 seconds
Started Jun 09 01:55:10 PM PDT 24
Finished Jun 09 01:55:13 PM PDT 24
Peak memory 216812 kb
Host smart-fee137f5-1c06-4328-a6ae-c439a89d1a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363954245 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.363954245
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3795388946
Short name T474
Test name
Test status
Simulation time 135606522009 ps
CPU time 1514.99 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 02:20:27 PM PDT 24
Peak memory 224776 kb
Host smart-eb981d61-c172-4994-adad-bdd062392165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795388946 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3795388946
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3280521496
Short name T303
Test name
Test status
Simulation time 71883736 ps
CPU time 1.13 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 219128 kb
Host smart-f072031e-e837-4215-ba3b-2396871c3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280521496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3280521496
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2528832318
Short name T705
Test name
Test status
Simulation time 49267618 ps
CPU time 0.87 seconds
Started Jun 09 01:55:16 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 206496 kb
Host smart-28aef2aa-9a44-49ee-a28f-15cf99446b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528832318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2528832318
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.810122129
Short name T563
Test name
Test status
Simulation time 11971229 ps
CPU time 0.87 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 215852 kb
Host smart-4ad970d4-f0bb-471f-9391-e9779a8b3e13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810122129 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.810122129
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.237623050
Short name T249
Test name
Test status
Simulation time 47126752 ps
CPU time 1.14 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 216776 kb
Host smart-318fa6be-8556-434c-aa92-ca97d24466d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237623050 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.237623050
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.283700277
Short name T801
Test name
Test status
Simulation time 21168603 ps
CPU time 1.22 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 229608 kb
Host smart-4f2eda2d-3d38-45b3-b454-1d3eec0b043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283700277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.283700277
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3701172033
Short name T274
Test name
Test status
Simulation time 52848372 ps
CPU time 1.54 seconds
Started Jun 09 01:55:17 PM PDT 24
Finished Jun 09 01:55:19 PM PDT 24
Peak memory 218228 kb
Host smart-e93d936d-a5bb-47c1-9a57-55d987d7fdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701172033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3701172033
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1324998831
Short name T410
Test name
Test status
Simulation time 24101824 ps
CPU time 1.1 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 215416 kb
Host smart-45444eb0-fb8f-4842-91fb-a2cb18b0e574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324998831 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1324998831
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.145840831
Short name T716
Test name
Test status
Simulation time 49102421 ps
CPU time 0.92 seconds
Started Jun 09 01:55:15 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 215176 kb
Host smart-b659b67f-bce5-4e05-af64-8bd29cfc1d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145840831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.145840831
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.594795140
Short name T311
Test name
Test status
Simulation time 138426686 ps
CPU time 2.06 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 215216 kb
Host smart-1c2eb818-a7ac-436d-8821-dae2cf24ac49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594795140 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.594795140
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4112120267
Short name T381
Test name
Test status
Simulation time 89452878666 ps
CPU time 1095.42 seconds
Started Jun 09 01:55:16 PM PDT 24
Finished Jun 09 02:13:32 PM PDT 24
Peak memory 224600 kb
Host smart-da3d196e-7d2f-4099-9042-d225235168dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112120267 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4112120267
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1349263587
Short name T171
Test name
Test status
Simulation time 28847700 ps
CPU time 1.23 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 218428 kb
Host smart-ca6c2320-9303-4a81-ac70-91e3ac839173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349263587 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1349263587
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4125064862
Short name T54
Test name
Test status
Simulation time 19278280 ps
CPU time 0.99 seconds
Started Jun 09 01:55:18 PM PDT 24
Finished Jun 09 01:55:20 PM PDT 24
Peak memory 206572 kb
Host smart-1e9da730-83df-45ba-83bd-aa5ba3da401b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125064862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4125064862
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1140307724
Short name T640
Test name
Test status
Simulation time 50329208 ps
CPU time 1.15 seconds
Started Jun 09 01:55:18 PM PDT 24
Finished Jun 09 01:55:19 PM PDT 24
Peak memory 216716 kb
Host smart-876142c3-3dca-4253-8f95-452813d3bfdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140307724 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1140307724
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.805843992
Short name T657
Test name
Test status
Simulation time 20175514 ps
CPU time 1.17 seconds
Started Jun 09 01:55:21 PM PDT 24
Finished Jun 09 01:55:22 PM PDT 24
Peak memory 224040 kb
Host smart-5140aca4-a5a3-41e1-8e36-a726b8113c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805843992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.805843992
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1863452020
Short name T723
Test name
Test status
Simulation time 109223873 ps
CPU time 1.74 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 219924 kb
Host smart-62d24020-c31a-42cc-9d62-96b17516dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863452020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1863452020
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.4169876108
Short name T584
Test name
Test status
Simulation time 22771365 ps
CPU time 1.11 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:20 PM PDT 24
Peak memory 215388 kb
Host smart-0c56b0a5-2447-433f-8865-36848516e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169876108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.4169876108
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1529451876
Short name T810
Test name
Test status
Simulation time 49382244 ps
CPU time 1 seconds
Started Jun 09 01:55:14 PM PDT 24
Finished Jun 09 01:55:16 PM PDT 24
Peak memory 215196 kb
Host smart-989edba5-4e9e-4bbd-a783-1e8024426a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529451876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1529451876
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2530721688
Short name T590
Test name
Test status
Simulation time 261571879 ps
CPU time 4.69 seconds
Started Jun 09 01:55:12 PM PDT 24
Finished Jun 09 01:55:17 PM PDT 24
Peak memory 216852 kb
Host smart-d3c0687d-64e2-4603-b7b3-bd832df553aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530721688 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2530721688
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2500335449
Short name T91
Test name
Test status
Simulation time 353974557266 ps
CPU time 721.9 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 02:07:22 PM PDT 24
Peak memory 219836 kb
Host smart-7375518c-2216-495e-a22a-6979da6cd52a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500335449 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2500335449
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3827277090
Short name T167
Test name
Test status
Simulation time 137094449 ps
CPU time 1.26 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 219064 kb
Host smart-e97b3649-65af-44cf-8560-268e31a83310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827277090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3827277090
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3846017857
Short name T619
Test name
Test status
Simulation time 19610355 ps
CPU time 0.87 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 01:55:23 PM PDT 24
Peak memory 206316 kb
Host smart-5c919e5b-ea5a-4908-9914-b11831f36e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846017857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3846017857
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2270563484
Short name T180
Test name
Test status
Simulation time 43630056 ps
CPU time 0.89 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 01:55:23 PM PDT 24
Peak memory 215304 kb
Host smart-ea8f48d2-c462-48ea-9d1c-a8b9075466be
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270563484 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2270563484
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.627597726
Short name T600
Test name
Test status
Simulation time 39496206 ps
CPU time 1.19 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 232276 kb
Host smart-6c4fee59-8996-4b09-b4b4-259e460c5d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627597726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.627597726
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1931987363
Short name T212
Test name
Test status
Simulation time 102788735 ps
CPU time 1.41 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 01:55:24 PM PDT 24
Peak memory 216820 kb
Host smart-46fc3a41-0978-4e31-995b-43aca057e478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931987363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1931987363
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1055276515
Short name T31
Test name
Test status
Simulation time 43653518 ps
CPU time 0.87 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:20 PM PDT 24
Peak memory 215652 kb
Host smart-af3eda0a-c263-47c1-a4f3-123f69f5bc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055276515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1055276515
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.430148175
Short name T504
Test name
Test status
Simulation time 47975537 ps
CPU time 0.88 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 215212 kb
Host smart-8aa1b008-66b7-450f-945e-de80cb3cb724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430148175 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.430148175
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.751239045
Short name T773
Test name
Test status
Simulation time 90593070 ps
CPU time 1.53 seconds
Started Jun 09 01:55:20 PM PDT 24
Finished Jun 09 01:55:22 PM PDT 24
Peak memory 216908 kb
Host smart-756d4ac0-5a02-404c-9544-06af378d6fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751239045 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.751239045
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1521597528
Short name T62
Test name
Test status
Simulation time 51848285317 ps
CPU time 568.7 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 02:04:50 PM PDT 24
Peak memory 223544 kb
Host smart-79e72013-a27a-412d-ad55-e92f834a4307
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521597528 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1521597528
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1170627465
Short name T114
Test name
Test status
Simulation time 370483885 ps
CPU time 1.51 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 219292 kb
Host smart-da7afa3f-f399-45ab-bbab-857b36da5b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170627465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1170627465
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.577900843
Short name T591
Test name
Test status
Simulation time 139353519 ps
CPU time 0.79 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:25 PM PDT 24
Peak memory 205832 kb
Host smart-d4464d47-f48a-4ba8-9d56-aef85aacc68f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577900843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.577900843
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1199513947
Short name T112
Test name
Test status
Simulation time 34007061 ps
CPU time 1.25 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:26 PM PDT 24
Peak memory 216760 kb
Host smart-de684956-cbe0-4c13-b4e2-8479d5a49702
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199513947 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1199513947
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.3123648706
Short name T507
Test name
Test status
Simulation time 50754392 ps
CPU time 1.21 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 218368 kb
Host smart-658c6f46-fd8d-4880-bc84-90bfc8dc3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123648706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3123648706
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1496850751
Short name T86
Test name
Test status
Simulation time 25096174 ps
CPU time 1.01 seconds
Started Jun 09 01:55:23 PM PDT 24
Finished Jun 09 01:55:25 PM PDT 24
Peak memory 215788 kb
Host smart-8800c0b6-32f6-41bc-b31f-798bfde11de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496850751 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1496850751
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1939365242
Short name T528
Test name
Test status
Simulation time 35638750 ps
CPU time 0.93 seconds
Started Jun 09 01:55:23 PM PDT 24
Finished Jun 09 01:55:24 PM PDT 24
Peak memory 215208 kb
Host smart-728c35d8-17a3-4fdc-aa5e-67e04ead4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939365242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1939365242
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2707754178
Short name T396
Test name
Test status
Simulation time 58280271 ps
CPU time 1.68 seconds
Started Jun 09 01:55:19 PM PDT 24
Finished Jun 09 01:55:21 PM PDT 24
Peak memory 219296 kb
Host smart-3f63bdea-312f-42a8-b3fc-dd97ed0b400b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707754178 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2707754178
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.796665732
Short name T434
Test name
Test status
Simulation time 28755242642 ps
CPU time 351.38 seconds
Started Jun 09 01:55:21 PM PDT 24
Finished Jun 09 02:01:13 PM PDT 24
Peak memory 218556 kb
Host smart-4ea5e2e6-ce55-4b6f-a2a3-2b6c099979dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796665732 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.796665732
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1767255315
Short name T144
Test name
Test status
Simulation time 43205203 ps
CPU time 1.16 seconds
Started Jun 09 01:55:23 PM PDT 24
Finished Jun 09 01:55:25 PM PDT 24
Peak memory 219224 kb
Host smart-18a48ce3-f1a3-4009-9d10-9dfb15dd9614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767255315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1767255315
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.3277653923
Short name T574
Test name
Test status
Simulation time 34025674 ps
CPU time 0.93 seconds
Started Jun 09 01:55:26 PM PDT 24
Finished Jun 09 01:55:27 PM PDT 24
Peak memory 206548 kb
Host smart-c692fb7b-8cce-45dd-8f1b-ec860c2105f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277653923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3277653923
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3499373705
Short name T160
Test name
Test status
Simulation time 14089970 ps
CPU time 0.93 seconds
Started Jun 09 01:55:25 PM PDT 24
Finished Jun 09 01:55:26 PM PDT 24
Peak memory 216324 kb
Host smart-909e5dc2-28a1-4afd-8d8f-2a0b9b8bb4a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499373705 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3499373705
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3377596499
Short name T458
Test name
Test status
Simulation time 196369947 ps
CPU time 1.15 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:26 PM PDT 24
Peak memory 218104 kb
Host smart-b86e62ae-9cd9-41c8-968f-a8c503cdab0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377596499 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3377596499
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.843382870
Short name T774
Test name
Test status
Simulation time 54777294 ps
CPU time 0.98 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:26 PM PDT 24
Peak memory 219896 kb
Host smart-eb339613-50de-49cd-b702-418b7a494d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843382870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.843382870
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1393589482
Short name T475
Test name
Test status
Simulation time 35703525 ps
CPU time 1.16 seconds
Started Jun 09 01:55:26 PM PDT 24
Finished Jun 09 01:55:27 PM PDT 24
Peak memory 218156 kb
Host smart-58a7a3c4-8f51-4a36-bf91-13d9d4a4dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393589482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1393589482
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.776350407
Short name T733
Test name
Test status
Simulation time 27601807 ps
CPU time 0.91 seconds
Started Jun 09 01:55:26 PM PDT 24
Finished Jun 09 01:55:27 PM PDT 24
Peak memory 215512 kb
Host smart-3987e8f7-9e65-4034-b9bc-5b0354b78c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776350407 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.776350407
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3193837846
Short name T802
Test name
Test status
Simulation time 17525278 ps
CPU time 1.04 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 01:55:24 PM PDT 24
Peak memory 215160 kb
Host smart-a10b7fad-d36d-4970-bdbf-b8b780f52abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193837846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3193837846
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3777778413
Short name T19
Test name
Test status
Simulation time 222330494 ps
CPU time 2.68 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:28 PM PDT 24
Peak memory 219460 kb
Host smart-f9379a52-eff8-4f63-9c55-ee9406efa10c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777778413 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3777778413
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1376716637
Short name T565
Test name
Test status
Simulation time 89833245773 ps
CPU time 1817.58 seconds
Started Jun 09 01:55:22 PM PDT 24
Finished Jun 09 02:25:40 PM PDT 24
Peak memory 225244 kb
Host smart-75f31a10-d857-4ea4-916a-d591b5c4d853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376716637 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1376716637
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1480278126
Short name T103
Test name
Test status
Simulation time 101526738 ps
CPU time 1.22 seconds
Started Jun 09 01:55:25 PM PDT 24
Finished Jun 09 01:55:27 PM PDT 24
Peak memory 219412 kb
Host smart-55254ec4-dfc8-45a7-95a8-d5d8c5321db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480278126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1480278126
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.1702543048
Short name T430
Test name
Test status
Simulation time 58100789 ps
CPU time 0.98 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 206584 kb
Host smart-ab5aec19-44d2-446d-9d07-768fd5692443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702543048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.1702543048
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.4249214259
Short name T491
Test name
Test status
Simulation time 22196592 ps
CPU time 0.86 seconds
Started Jun 09 01:55:27 PM PDT 24
Finished Jun 09 01:55:28 PM PDT 24
Peak memory 215276 kb
Host smart-9aeafd7b-753f-489e-b4ff-5ad93edd802b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249214259 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.4249214259
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.139285295
Short name T218
Test name
Test status
Simulation time 35284850 ps
CPU time 1.21 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:29 PM PDT 24
Peak memory 216828 kb
Host smart-11b34ae8-2d32-4efe-8816-5234f9504163
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139285295 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_di
sable_auto_req_mode.139285295
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3478193967
Short name T605
Test name
Test status
Simulation time 59159314 ps
CPU time 1.14 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:29 PM PDT 24
Peak memory 219820 kb
Host smart-a1da0075-b9ae-42c9-87e4-28b4a92bf953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478193967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3478193967
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1117722420
Short name T676
Test name
Test status
Simulation time 89297718 ps
CPU time 1.28 seconds
Started Jun 09 01:55:23 PM PDT 24
Finished Jun 09 01:55:25 PM PDT 24
Peak memory 218480 kb
Host smart-a95cca73-6b5f-426b-9236-a709b09599c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117722420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1117722420
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.100414649
Short name T440
Test name
Test status
Simulation time 43124198 ps
CPU time 0.89 seconds
Started Jun 09 01:55:26 PM PDT 24
Finished Jun 09 01:55:28 PM PDT 24
Peak memory 215180 kb
Host smart-67274b37-7fd2-46ff-8479-fe48a6335e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100414649 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.100414649
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3673089221
Short name T310
Test name
Test status
Simulation time 24420102 ps
CPU time 1.03 seconds
Started Jun 09 01:55:24 PM PDT 24
Finished Jun 09 01:55:25 PM PDT 24
Peak memory 215140 kb
Host smart-a788d4fe-b195-41dd-a480-e5eaa8379724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673089221 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3673089221
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2541623084
Short name T329
Test name
Test status
Simulation time 389212237 ps
CPU time 7.26 seconds
Started Jun 09 01:55:23 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 216716 kb
Host smart-c8a6ccc4-8b75-42ce-854b-96558abdb559
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541623084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2541623084
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.76482804
Short name T198
Test name
Test status
Simulation time 70650934737 ps
CPU time 774.58 seconds
Started Jun 09 01:55:27 PM PDT 24
Finished Jun 09 02:08:22 PM PDT 24
Peak memory 218900 kb
Host smart-afee01ea-adf0-446e-9802-e3ea87abbe8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76482804 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.76482804
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.351742736
Short name T141
Test name
Test status
Simulation time 24329542 ps
CPU time 1.18 seconds
Started Jun 09 01:55:27 PM PDT 24
Finished Jun 09 01:55:29 PM PDT 24
Peak memory 219572 kb
Host smart-315294e5-0597-4e78-a24a-b406a4bf79f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351742736 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.351742736
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.571417053
Short name T675
Test name
Test status
Simulation time 70225008 ps
CPU time 0.8 seconds
Started Jun 09 01:55:30 PM PDT 24
Finished Jun 09 01:55:31 PM PDT 24
Peak memory 206132 kb
Host smart-ce6efdf5-4479-417c-ab70-c252d904fc61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571417053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.571417053
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2057452733
Short name T522
Test name
Test status
Simulation time 20582067 ps
CPU time 0.85 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 01:55:34 PM PDT 24
Peak memory 215864 kb
Host smart-a8b9e933-c1ec-43f2-a449-68ab98d8de3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057452733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2057452733
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2511510870
Short name T80
Test name
Test status
Simulation time 41025624 ps
CPU time 1.12 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 216812 kb
Host smart-06aa8d11-17d6-4bab-8a92-b4d48803d14b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511510870 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2511510870
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.3111817750
Short name T143
Test name
Test status
Simulation time 40367998 ps
CPU time 1.02 seconds
Started Jun 09 01:55:30 PM PDT 24
Finished Jun 09 01:55:32 PM PDT 24
Peak memory 223844 kb
Host smart-feed31c2-4169-450b-b89b-1c15cb535c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111817750 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3111817750
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3096026617
Short name T408
Test name
Test status
Simulation time 42294185 ps
CPU time 1.5 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 215176 kb
Host smart-71de6285-c15b-423d-87c8-44d3ad82c932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096026617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3096026617
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.2956739669
Short name T708
Test name
Test status
Simulation time 31561551 ps
CPU time 0.89 seconds
Started Jun 09 01:55:27 PM PDT 24
Finished Jun 09 01:55:28 PM PDT 24
Peak memory 215288 kb
Host smart-4585bce3-f07e-4c52-8c34-e929ce637aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956739669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.2956739669
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2153453299
Short name T450
Test name
Test status
Simulation time 14541103 ps
CPU time 0.98 seconds
Started Jun 09 01:55:29 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 215200 kb
Host smart-517c59e7-16f3-436e-8a17-7f2c7fece667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153453299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2153453299
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2415436667
Short name T748
Test name
Test status
Simulation time 583415320 ps
CPU time 3.18 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:32 PM PDT 24
Peak memory 216812 kb
Host smart-ab644145-768c-4548-a714-2459f8da82af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415436667 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2415436667
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1697612159
Short name T89
Test name
Test status
Simulation time 35550372675 ps
CPU time 825.73 seconds
Started Jun 09 01:55:31 PM PDT 24
Finished Jun 09 02:09:17 PM PDT 24
Peak memory 223572 kb
Host smart-6f4752d4-f7d2-4a3a-b027-c0f9c2ec2172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697612159 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1697612159
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.524869027
Short name T196
Test name
Test status
Simulation time 54521224 ps
CPU time 1.16 seconds
Started Jun 09 01:54:20 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 218780 kb
Host smart-06dda478-ca31-472c-9301-bb77dbdf9bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524869027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.524869027
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3495261158
Short name T360
Test name
Test status
Simulation time 55674534 ps
CPU time 0.87 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 206524 kb
Host smart-f600c069-3688-45a7-9b97-f2aeeffe0487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495261158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3495261158
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1865575064
Short name T65
Test name
Test status
Simulation time 60079295 ps
CPU time 0.83 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:20 PM PDT 24
Peak memory 216184 kb
Host smart-7d556986-3935-476b-811c-368587f257c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865575064 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1865575064
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1987152649
Short name T126
Test name
Test status
Simulation time 61331913 ps
CPU time 0.97 seconds
Started Jun 09 01:54:22 PM PDT 24
Finished Jun 09 01:54:23 PM PDT 24
Peak memory 219740 kb
Host smart-b8636828-59aa-4c3b-84b4-fcb3e175328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987152649 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1987152649
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4086799945
Short name T48
Test name
Test status
Simulation time 67913734 ps
CPU time 1.58 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 218484 kb
Host smart-dfe2d90b-cba5-4db8-a8ba-8c22d1d5f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086799945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4086799945
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.1067208150
Short name T299
Test name
Test status
Simulation time 16044478 ps
CPU time 0.96 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 207004 kb
Host smart-cec016dd-8ece-4b39-983f-6fa7f7914249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067208150 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1067208150
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2848160402
Short name T13
Test name
Test status
Simulation time 232506595 ps
CPU time 4.18 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:22 PM PDT 24
Peak memory 236268 kb
Host smart-e275b4d2-5c7a-4a74-8b76-0f93b21817a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848160402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2848160402
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.1312421209
Short name T456
Test name
Test status
Simulation time 16857869 ps
CPU time 1.03 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:20 PM PDT 24
Peak memory 215192 kb
Host smart-604054e5-9864-4b54-86fd-cbe9187408b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312421209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1312421209
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1720346644
Short name T783
Test name
Test status
Simulation time 120192009 ps
CPU time 1.14 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 206536 kb
Host smart-8d6a6975-4bff-4d4d-b4cc-154e4cc2b210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720346644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1720346644
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2843450934
Short name T836
Test name
Test status
Simulation time 34482705085 ps
CPU time 774.74 seconds
Started Jun 09 01:54:20 PM PDT 24
Finished Jun 09 02:07:15 PM PDT 24
Peak memory 217092 kb
Host smart-4dd1e7fa-a545-46a2-a5ee-c07ce0efbb4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843450934 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2843450934
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3729194738
Short name T102
Test name
Test status
Simulation time 25558652 ps
CPU time 1.18 seconds
Started Jun 09 01:55:30 PM PDT 24
Finished Jun 09 01:55:32 PM PDT 24
Peak memory 218196 kb
Host smart-e028da5c-72e4-4920-af65-5cea0c88cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729194738 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3729194738
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2704178100
Short name T246
Test name
Test status
Simulation time 18337245 ps
CPU time 0.81 seconds
Started Jun 09 01:55:31 PM PDT 24
Finished Jun 09 01:55:32 PM PDT 24
Peak memory 206668 kb
Host smart-af3bb34c-3edd-4bef-b1c5-8ef45fb4ef1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704178100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2704178100
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.689236279
Short name T77
Test name
Test status
Simulation time 11702513 ps
CPU time 0.89 seconds
Started Jun 09 01:55:31 PM PDT 24
Finished Jun 09 01:55:32 PM PDT 24
Peak memory 216268 kb
Host smart-a9726a0c-3731-44aa-aaf9-0bc2b7a65a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689236279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.689236279
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.507662545
Short name T179
Test name
Test status
Simulation time 59334645 ps
CPU time 1.15 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 217052 kb
Host smart-60af2ebf-a7fb-4d52-99e5-04c52c0f6b86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507662545 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.507662545
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1028487507
Short name T173
Test name
Test status
Simulation time 20210344 ps
CPU time 1.11 seconds
Started Jun 09 01:55:31 PM PDT 24
Finished Jun 09 01:55:33 PM PDT 24
Peak memory 219460 kb
Host smart-9bf8ddf7-b0c3-4178-b3b4-2d9b99943502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028487507 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1028487507
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1736017888
Short name T762
Test name
Test status
Simulation time 45448162 ps
CPU time 1.77 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 219948 kb
Host smart-ffd26d8e-2c48-41b9-8c2a-1148fc43a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736017888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1736017888
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2860875744
Short name T340
Test name
Test status
Simulation time 21241557 ps
CPU time 1.1 seconds
Started Jun 09 01:55:29 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 215496 kb
Host smart-f8bd813a-541f-4d1b-904f-27fd1f796cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860875744 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2860875744
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1141780866
Short name T399
Test name
Test status
Simulation time 23061942 ps
CPU time 0.98 seconds
Started Jun 09 01:55:28 PM PDT 24
Finished Jun 09 01:55:30 PM PDT 24
Peak memory 215204 kb
Host smart-3c4a36b9-a51d-4418-b781-a5ad94b0c432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141780866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1141780866
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2561140871
Short name T23
Test name
Test status
Simulation time 1109830306 ps
CPU time 5.89 seconds
Started Jun 09 01:55:30 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 216820 kb
Host smart-500c24d7-d039-44a5-badb-5e5799fe9b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561140871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2561140871
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2395441170
Short name T197
Test name
Test status
Simulation time 57463164749 ps
CPU time 1253.35 seconds
Started Jun 09 01:55:30 PM PDT 24
Finished Jun 09 02:16:24 PM PDT 24
Peak memory 220116 kb
Host smart-536b7a6e-e3f9-4877-9cb3-fa36ff244c3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395441170 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2395441170
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert_test.1642635108
Short name T578
Test name
Test status
Simulation time 26368017 ps
CPU time 0.94 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 206524 kb
Host smart-91d93c4b-5ba3-4ceb-b9d6-ba0ce46b93b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642635108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1642635108
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.733447575
Short name T177
Test name
Test status
Simulation time 56986521 ps
CPU time 1.14 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 219488 kb
Host smart-9fbe7a9d-9abc-47ec-9ad5-03d4ca966a28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733447575 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.733447575
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2321477295
Short name T727
Test name
Test status
Simulation time 26377030 ps
CPU time 0.98 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 219492 kb
Host smart-9a452053-b240-4397-b57c-1c47bd8fcdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321477295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2321477295
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3849581834
Short name T745
Test name
Test status
Simulation time 74430471 ps
CPU time 1.18 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215188 kb
Host smart-d054ab2f-c1c5-4df8-a68e-8cbd9f04fa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849581834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3849581834
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4079349502
Short name T317
Test name
Test status
Simulation time 42888495 ps
CPU time 0.88 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 01:55:34 PM PDT 24
Peak memory 215708 kb
Host smart-516887bc-7f71-4a78-a80b-e739e6262f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079349502 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4079349502
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.101644964
Short name T542
Test name
Test status
Simulation time 17932863 ps
CPU time 1.05 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:37 PM PDT 24
Peak memory 215184 kb
Host smart-d34d715a-1fdf-4f7d-be29-d9205691db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101644964 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.101644964
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.4115974536
Short name T397
Test name
Test status
Simulation time 90750304 ps
CPU time 1.31 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215208 kb
Host smart-04db6ba2-bd3d-4f2e-9134-aee7d3eebb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115974536 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.4115974536
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.21316165
Short name T200
Test name
Test status
Simulation time 107158028514 ps
CPU time 669.24 seconds
Started Jun 09 01:55:35 PM PDT 24
Finished Jun 09 02:06:45 PM PDT 24
Peak memory 223624 kb
Host smart-c3856d89-7c80-4d7c-a437-80129eefcb75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21316165 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.21316165
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.1713371379
Short name T537
Test name
Test status
Simulation time 31303964 ps
CPU time 1 seconds
Started Jun 09 01:55:32 PM PDT 24
Finished Jun 09 01:55:34 PM PDT 24
Peak memory 214708 kb
Host smart-81c2d680-d886-4906-9d28-f8be8b736b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713371379 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1713371379
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3991059941
Short name T694
Test name
Test status
Simulation time 98786166 ps
CPU time 0.77 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 216140 kb
Host smart-3f6903e1-3b47-4796-b7bc-3efdfc62c16f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991059941 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3991059941
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4087458815
Short name T421
Test name
Test status
Simulation time 55628611 ps
CPU time 1.2 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 218260 kb
Host smart-dc6575aa-be72-44e5-94e2-6c769932e21b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087458815 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4087458815
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2905606398
Short name T189
Test name
Test status
Simulation time 19398826 ps
CPU time 1.1 seconds
Started Jun 09 01:55:32 PM PDT 24
Finished Jun 09 01:55:34 PM PDT 24
Peak memory 219628 kb
Host smart-f47b0f7c-af44-4913-93c7-4beeee1a6f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905606398 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2905606398
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.34864966
Short name T402
Test name
Test status
Simulation time 296732695 ps
CPU time 1.72 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 218468 kb
Host smart-6885154f-ace0-4c53-aed8-dbc5be07e887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34864966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.34864966
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2590355427
Short name T495
Test name
Test status
Simulation time 25446603 ps
CPU time 1.07 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 224064 kb
Host smart-feba0307-3574-415b-9179-aee949303d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590355427 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2590355427
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1395849640
Short name T498
Test name
Test status
Simulation time 73024713 ps
CPU time 0.9 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 215188 kb
Host smart-298d3ba6-3079-4b9f-a968-2f6717f2fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395849640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1395849640
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.872373675
Short name T761
Test name
Test status
Simulation time 279598469 ps
CPU time 1.95 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 219572 kb
Host smart-e059a5d8-9909-49f2-b304-e45914cd1f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872373675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.872373675
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.762990518
Short name T830
Test name
Test status
Simulation time 243885962042 ps
CPU time 598.82 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 02:05:32 PM PDT 24
Peak memory 219244 kb
Host smart-63781dc7-9729-41a6-a270-4b09e167a0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762990518 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.762990518
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.3600387971
Short name T155
Test name
Test status
Simulation time 52282209 ps
CPU time 1.08 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 218232 kb
Host smart-bee644fe-955a-4049-ae31-89e4fd0e1ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600387971 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.3600387971
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1580949095
Short name T345
Test name
Test status
Simulation time 25417027 ps
CPU time 0.91 seconds
Started Jun 09 01:55:35 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 206528 kb
Host smart-b155de36-eddc-4218-aa33-a205498626c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580949095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1580949095
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.138528151
Short name T73
Test name
Test status
Simulation time 16936727 ps
CPU time 0.83 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 216200 kb
Host smart-706ed214-8cb2-424a-81a4-abea67b90816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138528151 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.138528151
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1491124546
Short name T824
Test name
Test status
Simulation time 29953100 ps
CPU time 1.04 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 01:55:34 PM PDT 24
Peak memory 215548 kb
Host smart-1beb09e8-3809-41ec-9a22-ed7863545cb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491124546 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1491124546
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1511908103
Short name T809
Test name
Test status
Simulation time 19811522 ps
CPU time 1.06 seconds
Started Jun 09 01:55:31 PM PDT 24
Finished Jun 09 01:55:33 PM PDT 24
Peak memory 218476 kb
Host smart-aeff80d6-7228-42df-acdb-26ca0788a295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511908103 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1511908103
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2614947084
Short name T670
Test name
Test status
Simulation time 89024975 ps
CPU time 1.51 seconds
Started Jun 09 01:55:35 PM PDT 24
Finished Jun 09 01:55:37 PM PDT 24
Peak memory 218584 kb
Host smart-699bca56-42ec-465f-b15c-0cf7779235bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614947084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2614947084
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2518752624
Short name T78
Test name
Test status
Simulation time 28513902 ps
CPU time 0.98 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 215372 kb
Host smart-fad0bd19-ecf8-4769-a042-5b603eeb8144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518752624 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2518752624
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.660350715
Short name T680
Test name
Test status
Simulation time 28295117 ps
CPU time 1 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:35 PM PDT 24
Peak memory 215216 kb
Host smart-0565e9d8-723a-41b7-8139-a2a320990df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660350715 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.660350715
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.398102560
Short name T446
Test name
Test status
Simulation time 306903597 ps
CPU time 3.04 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 217020 kb
Host smart-78fc24cd-d739-42b3-95d0-a7f13d6d2093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398102560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.398102560
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1020645351
Short name T786
Test name
Test status
Simulation time 105701433789 ps
CPU time 1343.96 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 02:18:03 PM PDT 24
Peak memory 225440 kb
Host smart-4b6540b5-225b-451b-9cf2-62a69d4a808d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020645351 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1020645351
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert_test.3609431565
Short name T53
Test name
Test status
Simulation time 30885275 ps
CPU time 0.99 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 214764 kb
Host smart-428f2ab8-e516-4875-995a-39e033132085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609431565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3609431565
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.3108521399
Short name T191
Test name
Test status
Simulation time 23866216 ps
CPU time 0.87 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 216344 kb
Host smart-be0b06c2-04ae-481a-9c98-0f0124eb532e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108521399 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3108521399
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2039326093
Short name T808
Test name
Test status
Simulation time 109998655 ps
CPU time 1.11 seconds
Started Jun 09 01:55:35 PM PDT 24
Finished Jun 09 01:55:37 PM PDT 24
Peak memory 216900 kb
Host smart-be792a5b-6498-4961-9511-1a4230ba7ee9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039326093 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2039326093
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.380115280
Short name T413
Test name
Test status
Simulation time 30246845 ps
CPU time 0.9 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218316 kb
Host smart-151fddbc-ef3b-4330-9062-ed028b791fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380115280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.380115280
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1938693102
Short name T505
Test name
Test status
Simulation time 76915587 ps
CPU time 1.35 seconds
Started Jun 09 01:55:35 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 218276 kb
Host smart-b55c2025-4ad3-4ce7-84ed-53e1f8e3335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938693102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1938693102
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3854876768
Short name T832
Test name
Test status
Simulation time 59464995 ps
CPU time 0.87 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215208 kb
Host smart-53fee079-790d-4d87-b5c4-eeb997c3f7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854876768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3854876768
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.731918168
Short name T88
Test name
Test status
Simulation time 19628145 ps
CPU time 0.97 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 215192 kb
Host smart-d832a6aa-9c04-4cf2-9358-989939640204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731918168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.731918168
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3394117964
Short name T679
Test name
Test status
Simulation time 334184496 ps
CPU time 3.55 seconds
Started Jun 09 01:55:34 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 216716 kb
Host smart-3d3864bb-d4f3-42be-8e6d-39abcd73053c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394117964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3394117964
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3563397409
Short name T322
Test name
Test status
Simulation time 144835280222 ps
CPU time 1387.27 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 02:18:46 PM PDT 24
Peak memory 222848 kb
Host smart-c37bfc14-9108-4583-b6ed-1b053cf1ed0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563397409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3563397409
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.621225237
Short name T298
Test name
Test status
Simulation time 80204343 ps
CPU time 1.17 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 219632 kb
Host smart-fa0f5c77-7004-4504-9da7-b6e57f5b342c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621225237 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.621225237
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.1108094872
Short name T523
Test name
Test status
Simulation time 58242122 ps
CPU time 0.89 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215112 kb
Host smart-b14bce57-7a97-4cfb-af16-fdffacacf40c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108094872 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1108094872
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.3243089167
Short name T572
Test name
Test status
Simulation time 22440720 ps
CPU time 0.91 seconds
Started Jun 09 01:55:40 PM PDT 24
Finished Jun 09 01:55:42 PM PDT 24
Peak memory 216232 kb
Host smart-a3b1471c-cf93-4e88-adbc-f38ee79148d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243089167 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3243089167
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3362669761
Short name T839
Test name
Test status
Simulation time 26951957 ps
CPU time 1.15 seconds
Started Jun 09 01:55:39 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 216884 kb
Host smart-b50c404c-96c4-4a25-a13b-41e1445539f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362669761 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3362669761
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2186687496
Short name T692
Test name
Test status
Simulation time 19988172 ps
CPU time 1.05 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218716 kb
Host smart-0f6824d6-1dae-426a-a6e1-e33530521150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186687496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2186687496
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2757163512
Short name T508
Test name
Test status
Simulation time 103210880 ps
CPU time 2.33 seconds
Started Jun 09 01:55:33 PM PDT 24
Finished Jun 09 01:55:36 PM PDT 24
Peak memory 219560 kb
Host smart-d28a0944-30de-41a8-bb34-9a25eb137e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757163512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2757163512
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3059295837
Short name T21
Test name
Test status
Simulation time 35868845 ps
CPU time 0.94 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 215400 kb
Host smart-c7c07ba5-7549-40b9-8e8f-2a1a268acfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059295837 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3059295837
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2994543112
Short name T418
Test name
Test status
Simulation time 18114004 ps
CPU time 0.99 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215208 kb
Host smart-ab28b351-2993-4905-abd5-4e2aa4c52bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994543112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2994543112
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1496776565
Short name T660
Test name
Test status
Simulation time 190365748 ps
CPU time 1.24 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 217148 kb
Host smart-888e4a2d-4098-4859-8eeb-254e6fbfeb20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496776565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1496776565
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2219652265
Short name T339
Test name
Test status
Simulation time 86436346809 ps
CPU time 1937.19 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 02:27:57 PM PDT 24
Peak memory 226432 kb
Host smart-2e380c06-ea4a-4757-bf3e-d5e5d4721fbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219652265 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2219652265
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.123237079
Short name T296
Test name
Test status
Simulation time 74929630 ps
CPU time 1.11 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 219412 kb
Host smart-29148c5c-0345-41ad-96fb-e9c6846967ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123237079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.123237079
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2516221697
Short name T348
Test name
Test status
Simulation time 43641337 ps
CPU time 0.82 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 206164 kb
Host smart-12f8a41e-9904-4184-8b43-bf8fbbcadc4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516221697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2516221697
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.2408926537
Short name T632
Test name
Test status
Simulation time 27876845 ps
CPU time 0.83 seconds
Started Jun 09 01:55:39 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215276 kb
Host smart-591d7795-5afa-4d38-a348-e742d652e219
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408926537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2408926537
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4188477964
Short name T697
Test name
Test status
Simulation time 143227929 ps
CPU time 1.08 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 216660 kb
Host smart-7f4b3a16-7576-4277-a7ae-2f6f89528f1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188477964 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4188477964
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3904062205
Short name T184
Test name
Test status
Simulation time 43453813 ps
CPU time 0.95 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218728 kb
Host smart-7936d1ed-7bfb-4784-8a6f-acf36e354c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904062205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3904062205
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.5005464
Short name T741
Test name
Test status
Simulation time 137732370 ps
CPU time 1.32 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218480 kb
Host smart-486fa171-16e9-46c8-8868-844362e7e061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5005464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.5005464
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2153518311
Short name T36
Test name
Test status
Simulation time 23048468 ps
CPU time 0.96 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 215824 kb
Host smart-520d3e35-f765-4cc8-a88b-f9345c1fb51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153518311 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2153518311
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.310766838
Short name T821
Test name
Test status
Simulation time 37774556 ps
CPU time 0.96 seconds
Started Jun 09 01:55:40 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 215208 kb
Host smart-9e45e4ae-307f-4817-bf88-5daf3769fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310766838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.310766838
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.412213079
Short name T735
Test name
Test status
Simulation time 48716187 ps
CPU time 1.54 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 216680 kb
Host smart-c3dad1f4-4c11-4cce-b655-add751e3bd1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412213079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.412213079
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.591581138
Short name T465
Test name
Test status
Simulation time 158692095278 ps
CPU time 926.2 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 02:11:05 PM PDT 24
Peak memory 220688 kb
Host smart-ea7038f2-c332-4321-b4a1-b6c8de798b21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591581138 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.591581138
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2256952230
Short name T122
Test name
Test status
Simulation time 86369804 ps
CPU time 1.14 seconds
Started Jun 09 01:55:39 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 219204 kb
Host smart-263fe98d-45b6-4fae-ad55-b1fed29287b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256952230 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2256952230
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.786538542
Short name T384
Test name
Test status
Simulation time 52490110 ps
CPU time 0.94 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 206476 kb
Host smart-a95b26af-2cd7-46a4-a9e1-f3a4985fce05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786538542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.786538542
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1275957047
Short name T630
Test name
Test status
Simulation time 33985889 ps
CPU time 0.88 seconds
Started Jun 09 01:55:39 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 215840 kb
Host smart-4725930c-b44f-4ab0-bf08-efd83d7bf7e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275957047 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1275957047
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3473484300
Short name T120
Test name
Test status
Simulation time 44323885 ps
CPU time 1.06 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 219524 kb
Host smart-a63b472d-0f5b-4d79-9256-f2f3378a26d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473484300 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3473484300
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1599168310
Short name T170
Test name
Test status
Simulation time 23174041 ps
CPU time 0.92 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218516 kb
Host smart-f139f1b0-8500-40c9-87fb-22db99e6f68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599168310 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1599168310
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.206523922
Short name T255
Test name
Test status
Simulation time 42010533 ps
CPU time 1.5 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:41 PM PDT 24
Peak memory 219528 kb
Host smart-57de87d1-0b8b-4691-a3dd-4b560dbdee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206523922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.206523922
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.670420174
Short name T33
Test name
Test status
Simulation time 25366327 ps
CPU time 0.94 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 215780 kb
Host smart-25ea17c8-78a0-493e-b86b-35423b6549ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670420174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.670420174
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3267184626
Short name T812
Test name
Test status
Simulation time 47353328 ps
CPU time 0.88 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 215432 kb
Host smart-56d1a2a4-1466-4883-a6cf-8b3ce369a48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267184626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3267184626
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2972187670
Short name T678
Test name
Test status
Simulation time 46868934 ps
CPU time 0.94 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:39 PM PDT 24
Peak memory 206356 kb
Host smart-34ada02f-d468-4ba4-8c29-01add26ec222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972187670 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2972187670
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3513917291
Short name T573
Test name
Test status
Simulation time 74232976428 ps
CPU time 698.88 seconds
Started Jun 09 01:55:39 PM PDT 24
Finished Jun 09 02:07:18 PM PDT 24
Peak memory 221328 kb
Host smart-14c7c265-f49b-4b59-a13c-acab63272e8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513917291 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3513917291
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2258824680
Short name T109
Test name
Test status
Simulation time 208968547 ps
CPU time 1.28 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:55:40 PM PDT 24
Peak memory 218096 kb
Host smart-9931555e-fa03-4358-91e0-376ebc1c7ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258824680 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2258824680
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.605524316
Short name T682
Test name
Test status
Simulation time 19421539 ps
CPU time 1.01 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:46 PM PDT 24
Peak memory 214712 kb
Host smart-864c362c-3f7f-47cf-b920-7464af18045f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605524316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.605524316
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3286930251
Short name T22
Test name
Test status
Simulation time 13574354 ps
CPU time 0.9 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 216416 kb
Host smart-a81dcfa1-8d48-457f-bbd4-4224b3556eaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286930251 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3286930251
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1826470110
Short name T627
Test name
Test status
Simulation time 47897577 ps
CPU time 1.07 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 216756 kb
Host smart-144d9ddf-6b91-4a03-98a1-bcd5127fc9f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826470110 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1826470110
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.1517950366
Short name T469
Test name
Test status
Simulation time 19824444 ps
CPU time 1.1 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:37 PM PDT 24
Peak memory 218564 kb
Host smart-2314e70b-9970-4c92-8c5b-f62b6b1223a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517950366 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1517950366
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3176392551
Short name T435
Test name
Test status
Simulation time 209795518 ps
CPU time 1.19 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 216968 kb
Host smart-e3d00182-c107-4da3-8b4c-b931d6d12871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176392551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3176392551
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3687432351
Short name T794
Test name
Test status
Simulation time 28201640 ps
CPU time 0.98 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 215408 kb
Host smart-01f90283-fed8-447c-bb63-e22f7150ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687432351 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3687432351
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3146194991
Short name T419
Test name
Test status
Simulation time 41568297 ps
CPU time 0.91 seconds
Started Jun 09 01:55:36 PM PDT 24
Finished Jun 09 01:55:38 PM PDT 24
Peak memory 215188 kb
Host smart-eb34ba99-bb48-4389-8d9b-e88ded337fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146194991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3146194991
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1937137079
Short name T493
Test name
Test status
Simulation time 207514753 ps
CPU time 4.53 seconds
Started Jun 09 01:55:37 PM PDT 24
Finished Jun 09 01:55:43 PM PDT 24
Peak memory 215208 kb
Host smart-ad8bc762-22f2-4578-b510-51731f491b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937137079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1937137079
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1050260357
Short name T659
Test name
Test status
Simulation time 9024054671 ps
CPU time 227.91 seconds
Started Jun 09 01:55:38 PM PDT 24
Finished Jun 09 01:59:27 PM PDT 24
Peak memory 218016 kb
Host smart-2f3b33d7-0d68-455a-bbd5-d749b42f95c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050260357 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1050260357
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2764777844
Short name T148
Test name
Test status
Simulation time 24198759 ps
CPU time 1.24 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219132 kb
Host smart-27844dce-c518-43f4-8636-450a2ef7f275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764777844 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2764777844
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1051446660
Short name T541
Test name
Test status
Simulation time 28151246 ps
CPU time 1.14 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 206588 kb
Host smart-760c0523-5731-4453-b7ba-432e71664e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051446660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1051446660
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1594072279
Short name T797
Test name
Test status
Simulation time 26961615 ps
CPU time 0.78 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 216456 kb
Host smart-f1a1f7e4-4207-4c31-90e0-b3e82fbbec62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594072279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1594072279
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2158651155
Short name T661
Test name
Test status
Simulation time 57589526 ps
CPU time 1.1 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 216908 kb
Host smart-dbb0fa6a-58b0-4044-8ac5-2be0a4e16cb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158651155 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2158651155
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3498717289
Short name T502
Test name
Test status
Simulation time 18837954 ps
CPU time 1.08 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:46 PM PDT 24
Peak memory 218284 kb
Host smart-1f0613e6-5519-4451-b617-b999578b23cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498717289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3498717289
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.538543095
Short name T290
Test name
Test status
Simulation time 70006687 ps
CPU time 1.46 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 218424 kb
Host smart-76263fc4-c046-4788-b427-b27098879c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538543095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.538543095
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_smoke.219782917
Short name T372
Test name
Test status
Simulation time 38928081 ps
CPU time 0.89 seconds
Started Jun 09 01:55:45 PM PDT 24
Finished Jun 09 01:55:46 PM PDT 24
Peak memory 215192 kb
Host smart-bb483803-713c-48e4-a898-f10255f4e27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219782917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.219782917
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1034154677
Short name T208
Test name
Test status
Simulation time 140029126 ps
CPU time 2.99 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 216788 kb
Host smart-7fd9c793-ab93-4a67-923b-2d80930c7518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034154677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1034154677
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.4219381648
Short name T776
Test name
Test status
Simulation time 77194278439 ps
CPU time 983.27 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 02:12:10 PM PDT 24
Peak memory 223576 kb
Host smart-bc54e6cc-640b-4547-a095-b2fecb351644
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219381648 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.4219381648
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4007519959
Short name T92
Test name
Test status
Simulation time 28828912 ps
CPU time 1.26 seconds
Started Jun 09 01:54:25 PM PDT 24
Finished Jun 09 01:54:27 PM PDT 24
Peak memory 219376 kb
Host smart-fbc5154f-20d3-4cb2-9fdd-6906fa6b3246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007519959 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4007519959
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.859971739
Short name T335
Test name
Test status
Simulation time 28937282 ps
CPU time 1.15 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 214956 kb
Host smart-34c00fab-4e15-4e63-bd4b-cce484bdd94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859971739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.859971739
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2568830659
Short name T16
Test name
Test status
Simulation time 147792219 ps
CPU time 1.18 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:26 PM PDT 24
Peak memory 216668 kb
Host smart-33284400-9a5d-4ac7-93b1-8ca94cec14cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568830659 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2568830659
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3893571292
Short name T163
Test name
Test status
Simulation time 19856069 ps
CPU time 1.08 seconds
Started Jun 09 01:54:25 PM PDT 24
Finished Jun 09 01:54:26 PM PDT 24
Peak memory 218540 kb
Host smart-ba2c26c2-6a2b-4018-ac9f-8ac94bf20f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893571292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3893571292
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2662391264
Short name T387
Test name
Test status
Simulation time 30212099 ps
CPU time 1.21 seconds
Started Jun 09 01:54:19 PM PDT 24
Finished Jun 09 01:54:21 PM PDT 24
Peak memory 216912 kb
Host smart-46ff22ec-3142-4478-ba13-02c6321c6267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662391264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2662391264
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3821817147
Short name T731
Test name
Test status
Simulation time 20877616 ps
CPU time 1.03 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 01:54:24 PM PDT 24
Peak memory 215944 kb
Host smart-f480bc1e-cd02-4cc5-a051-0113bd537c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821817147 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3821817147
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.2377942262
Short name T24
Test name
Test status
Simulation time 17904913 ps
CPU time 0.98 seconds
Started Jun 09 01:54:18 PM PDT 24
Finished Jun 09 01:54:20 PM PDT 24
Peak memory 206996 kb
Host smart-5f4693f5-80fa-4c12-b144-1e65583f4d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377942262 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2377942262
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.268515168
Short name T704
Test name
Test status
Simulation time 16225192 ps
CPU time 1.03 seconds
Started Jun 09 01:54:22 PM PDT 24
Finished Jun 09 01:54:23 PM PDT 24
Peak memory 215184 kb
Host smart-1a6377b3-f890-4a6b-ae9d-e2212b03a6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268515168 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.268515168
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3648442889
Short name T687
Test name
Test status
Simulation time 826585144 ps
CPU time 5.05 seconds
Started Jun 09 01:54:27 PM PDT 24
Finished Jun 09 01:54:33 PM PDT 24
Peak memory 216656 kb
Host smart-f8954060-0dd7-40c6-abdd-3c53153d8fd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648442889 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3648442889
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.2899810174
Short name T203
Test name
Test status
Simulation time 156800782573 ps
CPU time 1641.1 seconds
Started Jun 09 01:54:25 PM PDT 24
Finished Jun 09 02:21:47 PM PDT 24
Peak memory 225344 kb
Host smart-f01080ac-852f-4a62-b343-143b9e843d0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899810174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.2899810174
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.118654520
Short name T175
Test name
Test status
Simulation time 23413813 ps
CPU time 1.1 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 218464 kb
Host smart-6c972e82-f462-4fde-b288-e4822a7343e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118654520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.118654520
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2252883629
Short name T429
Test name
Test status
Simulation time 28406375 ps
CPU time 1.23 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 217036 kb
Host smart-1f548308-8729-44d3-8932-0c4f4593b70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252883629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2252883629
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.927681958
Short name T162
Test name
Test status
Simulation time 23922012 ps
CPU time 0.93 seconds
Started Jun 09 01:55:45 PM PDT 24
Finished Jun 09 01:55:46 PM PDT 24
Peak memory 218372 kb
Host smart-09efc171-47f1-4e66-bde9-7fbb35ef9c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927681958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.927681958
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.357737284
Short name T701
Test name
Test status
Simulation time 115731930 ps
CPU time 1.26 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 218600 kb
Host smart-4d1973bc-72b0-4291-99de-bc9d56cf28e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357737284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.357737284
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.4261381390
Short name T790
Test name
Test status
Simulation time 33397967 ps
CPU time 1.05 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 218480 kb
Host smart-e3f49362-8b6d-4909-95fe-72304d4a6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261381390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.4261381390
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1745635968
Short name T321
Test name
Test status
Simulation time 39756057 ps
CPU time 1.41 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 215200 kb
Host smart-15f1e06b-0903-48f0-a9f8-39460dc79559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745635968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1745635968
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2350387778
Short name T526
Test name
Test status
Simulation time 56123293 ps
CPU time 1.34 seconds
Started Jun 09 01:55:40 PM PDT 24
Finished Jun 09 01:55:42 PM PDT 24
Peak memory 219596 kb
Host smart-13330672-6c0c-46e1-8122-65813a3474c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350387778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2350387778
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2037620870
Short name T459
Test name
Test status
Simulation time 97773747 ps
CPU time 1.18 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 218116 kb
Host smart-a30c2f6f-5151-4811-9d85-74c9debc11d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037620870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2037620870
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3462339570
Short name T788
Test name
Test status
Simulation time 23711354 ps
CPU time 1.03 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:51 PM PDT 24
Peak memory 218588 kb
Host smart-a506ad71-52f9-4abb-9ce3-875568f39622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462339570 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3462339570
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.471210442
Short name T663
Test name
Test status
Simulation time 44064292 ps
CPU time 1.51 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 218208 kb
Host smart-3f5a9889-6ad7-4f0a-baf9-487768a01ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471210442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.471210442
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3102248620
Short name T294
Test name
Test status
Simulation time 76800838 ps
CPU time 0.9 seconds
Started Jun 09 01:55:43 PM PDT 24
Finished Jun 09 01:55:44 PM PDT 24
Peak memory 218392 kb
Host smart-3f663c83-323d-47ee-bf23-a33376a6b115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102248620 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3102248620
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2829742557
Short name T787
Test name
Test status
Simulation time 51229394 ps
CPU time 1.48 seconds
Started Jun 09 01:55:42 PM PDT 24
Finished Jun 09 01:55:43 PM PDT 24
Peak memory 218340 kb
Host smart-2322208f-0119-4ab4-93f0-af81d5bf018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829742557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2829742557
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3090469503
Short name T509
Test name
Test status
Simulation time 19797702 ps
CPU time 1.13 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:47 PM PDT 24
Peak memory 219784 kb
Host smart-31ba311b-6c32-41a6-8fbc-c67a4985a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090469503 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3090469503
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3730023924
Short name T651
Test name
Test status
Simulation time 364674594 ps
CPU time 3.51 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 219652 kb
Host smart-75c71399-ed01-4b82-8b99-06deee67e78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730023924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3730023924
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_genbits.4187375827
Short name T685
Test name
Test status
Simulation time 74892177 ps
CPU time 1.33 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219792 kb
Host smart-880bfc88-cb0e-4a22-ba11-52b0b0d0a98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187375827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.4187375827
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2848988200
Short name T370
Test name
Test status
Simulation time 21822848 ps
CPU time 0.9 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 218344 kb
Host smart-da12f82d-47d1-4fb1-a10d-a87fe9cf4346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848988200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2848988200
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/59.edn_err.3091373941
Short name T717
Test name
Test status
Simulation time 34667489 ps
CPU time 0.94 seconds
Started Jun 09 01:55:44 PM PDT 24
Finished Jun 09 01:55:45 PM PDT 24
Peak memory 219816 kb
Host smart-be2da1aa-9e9a-4d17-ae89-5aa8308ee5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091373941 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3091373941
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2273364493
Short name T626
Test name
Test status
Simulation time 107009661 ps
CPU time 1.43 seconds
Started Jun 09 01:55:41 PM PDT 24
Finished Jun 09 01:55:43 PM PDT 24
Peak memory 216948 kb
Host smart-233ba96a-8097-4563-a33f-3881a9167137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273364493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2273364493
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.3732776519
Short name T779
Test name
Test status
Simulation time 17333704 ps
CPU time 0.97 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 206520 kb
Host smart-324b8740-8aa9-4901-8171-55ff183225e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732776519 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3732776519
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2495227610
Short name T79
Test name
Test status
Simulation time 45012221 ps
CPU time 0.87 seconds
Started Jun 09 01:54:23 PM PDT 24
Finished Jun 09 01:54:24 PM PDT 24
Peak memory 216316 kb
Host smart-415be7cf-094f-4e50-9763-1e070dd53d8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495227610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2495227610
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.1773646527
Short name T113
Test name
Test status
Simulation time 44656379 ps
CPU time 1.43 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:26 PM PDT 24
Peak memory 216812 kb
Host smart-d462cef5-c375-4d0e-b590-09eb785767c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773646527 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.1773646527
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.604170462
Short name T117
Test name
Test status
Simulation time 94167317 ps
CPU time 1.02 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 219536 kb
Host smart-c9b53359-d029-4d81-8c5c-5b19346d6bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604170462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.604170462
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.436189263
Short name T579
Test name
Test status
Simulation time 255461271 ps
CPU time 1.35 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:26 PM PDT 24
Peak memory 218652 kb
Host smart-a8ea95db-56e7-40a1-8019-a367b2cfa33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436189263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.436189263
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.977162957
Short name T544
Test name
Test status
Simulation time 29789206 ps
CPU time 1.02 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 215492 kb
Host smart-6feecbac-b288-4976-ab40-e55b326d413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977162957 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.977162957
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3090610067
Short name T765
Test name
Test status
Simulation time 16920971 ps
CPU time 1 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 215216 kb
Host smart-619001f8-99e3-4ef0-b605-d0da9eb745eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090610067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3090610067
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.762405693
Short name T825
Test name
Test status
Simulation time 281912578 ps
CPU time 5.95 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 216860 kb
Host smart-ee182100-5052-4d82-9539-7f10070ce842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762405693 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.762405693
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2831991943
Short name T358
Test name
Test status
Simulation time 24973064764 ps
CPU time 635.88 seconds
Started Jun 09 01:54:26 PM PDT 24
Finished Jun 09 02:05:02 PM PDT 24
Peak memory 217644 kb
Host smart-b53bdb36-9c29-4e88-8f70-3ffbd94c7d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831991943 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2831991943
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3914141661
Short name T159
Test name
Test status
Simulation time 19192012 ps
CPU time 1.13 seconds
Started Jun 09 01:55:48 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 224060 kb
Host smart-e9f1099c-de2c-48e8-b483-5ce75d6e23c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914141661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3914141661
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3757487719
Short name T400
Test name
Test status
Simulation time 243066915 ps
CPU time 1.52 seconds
Started Jun 09 01:55:47 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 218224 kb
Host smart-0d3c5cb7-847b-434c-bb0a-59c2bed225cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757487719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3757487719
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3319563799
Short name T775
Test name
Test status
Simulation time 23733469 ps
CPU time 0.95 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 218436 kb
Host smart-1226ce1c-bc6f-4d52-a0e1-cf098b41dc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319563799 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3319563799
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2203814347
Short name T69
Test name
Test status
Simulation time 78377458 ps
CPU time 2.6 seconds
Started Jun 09 01:55:47 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 219512 kb
Host smart-67f1200b-17f4-4437-8c92-8492c1395f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203814347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2203814347
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3909197925
Short name T142
Test name
Test status
Simulation time 20195936 ps
CPU time 1.15 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 224068 kb
Host smart-282d8fcb-b68a-4d5a-8713-d1a0e7ee21cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909197925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3909197925
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3511943202
Short name T404
Test name
Test status
Simulation time 37698805 ps
CPU time 1.3 seconds
Started Jun 09 01:55:45 PM PDT 24
Finished Jun 09 01:55:47 PM PDT 24
Peak memory 217928 kb
Host smart-e5577212-bc76-4018-850e-1acc34635bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511943202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3511943202
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1558856828
Short name T41
Test name
Test status
Simulation time 19063373 ps
CPU time 1.08 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:47 PM PDT 24
Peak memory 218700 kb
Host smart-209c0c2d-0c6a-44a3-9a63-167073da7d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558856828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1558856828
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.80328453
Short name T8
Test name
Test status
Simulation time 159053006 ps
CPU time 1.98 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 219708 kb
Host smart-d0568ce2-32bc-4f24-ab5e-f12e2b58fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80328453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.80328453
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3758693537
Short name T52
Test name
Test status
Simulation time 24628376 ps
CPU time 0.96 seconds
Started Jun 09 01:55:47 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 219588 kb
Host smart-d5cf9481-d905-4bec-9c03-c85f2fa6c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758693537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3758693537
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2465483429
Short name T427
Test name
Test status
Simulation time 77627562 ps
CPU time 1.05 seconds
Started Jun 09 01:55:48 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 218268 kb
Host smart-e6068736-5e20-4b3e-9122-2519c32c35d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465483429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2465483429
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.739342624
Short name T835
Test name
Test status
Simulation time 34067540 ps
CPU time 1.39 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219564 kb
Host smart-ea8ac99d-ea99-47fe-9b12-510d4593047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739342624 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.739342624
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2936870489
Short name T570
Test name
Test status
Simulation time 72897997 ps
CPU time 1.28 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 218368 kb
Host smart-c8e0bbaf-a870-4789-a87e-878f0a1f1bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936870489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2936870489
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1658448098
Short name T172
Test name
Test status
Simulation time 25795086 ps
CPU time 0.94 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:51 PM PDT 24
Peak memory 219560 kb
Host smart-2643bfc8-3f0a-430b-bb60-f4ef40aa332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658448098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1658448098
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/67.edn_err.3198003607
Short name T105
Test name
Test status
Simulation time 25584860 ps
CPU time 1.25 seconds
Started Jun 09 01:55:47 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 219812 kb
Host smart-6232fe1e-7c90-4d90-8d35-ab4375b10d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198003607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3198003607
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3988379477
Short name T364
Test name
Test status
Simulation time 48161713 ps
CPU time 1.78 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 218188 kb
Host smart-9e12fde3-9a5e-43ff-9339-6c50f78e7213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988379477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3988379477
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1428086191
Short name T134
Test name
Test status
Simulation time 44822946 ps
CPU time 1.3 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 225744 kb
Host smart-910b320c-254c-4ab9-9b7e-2d56e1b6f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428086191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1428086191
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1210744342
Short name T534
Test name
Test status
Simulation time 55567723 ps
CPU time 1.64 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 215200 kb
Host smart-481e887d-d5e8-4c40-a3c3-d3df0987cdde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210744342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1210744342
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3183994267
Short name T615
Test name
Test status
Simulation time 44803035 ps
CPU time 1.13 seconds
Started Jun 09 01:55:48 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 224044 kb
Host smart-5e967eae-983b-4957-a142-38649a6853cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183994267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3183994267
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3129152101
Short name T438
Test name
Test status
Simulation time 32817810 ps
CPU time 1.32 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:47 PM PDT 24
Peak memory 219408 kb
Host smart-338c3870-4aa4-4d82-b2a6-e5f72c89489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129152101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3129152101
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1294835590
Short name T133
Test name
Test status
Simulation time 44380288 ps
CPU time 1.26 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 218620 kb
Host smart-4c718146-ea73-41b9-83cf-4528fac33b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294835590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1294835590
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.2201668806
Short name T393
Test name
Test status
Simulation time 51967864 ps
CPU time 0.93 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 215056 kb
Host smart-15e1f3fc-58c8-41a9-88f1-c06f969bed45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201668806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.2201668806
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3033777733
Short name T139
Test name
Test status
Simulation time 24471047 ps
CPU time 0.87 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 215324 kb
Host smart-81e6f9bf-584b-4054-90a0-cc35f0cedb46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033777733 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3033777733
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.4106669068
Short name T455
Test name
Test status
Simulation time 104315722 ps
CPU time 1.07 seconds
Started Jun 09 01:54:30 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 217996 kb
Host smart-147fa65d-65ab-4fd0-8d83-5987330cf7e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106669068 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.4106669068
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.1906744130
Short name T55
Test name
Test status
Simulation time 23885821 ps
CPU time 1.09 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 224084 kb
Host smart-7ad1aa3b-ccad-4edc-b189-5a552aba1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906744130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1906744130
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3183054880
Short name T546
Test name
Test status
Simulation time 58871000 ps
CPU time 1.32 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:26 PM PDT 24
Peak memory 218280 kb
Host smart-6194ef1d-28b9-4d2f-b329-18c174673ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183054880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3183054880
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4025260819
Short name T32
Test name
Test status
Simulation time 24859235 ps
CPU time 0.94 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:29 PM PDT 24
Peak memory 215984 kb
Host smart-c2d66200-6029-44f9-868f-0b6a302d6744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025260819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4025260819
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.738439010
Short name T295
Test name
Test status
Simulation time 56479219 ps
CPU time 0.93 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 207032 kb
Host smart-78022705-3416-4d89-8d34-5d1398a71e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738439010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.738439010
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.174386566
Short name T642
Test name
Test status
Simulation time 72045199 ps
CPU time 0.87 seconds
Started Jun 09 01:54:24 PM PDT 24
Finished Jun 09 01:54:25 PM PDT 24
Peak memory 215152 kb
Host smart-d42fcf07-4057-46e6-9c95-119a54288644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174386566 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.174386566
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1048659458
Short name T593
Test name
Test status
Simulation time 240304315 ps
CPU time 3.5 seconds
Started Jun 09 01:54:27 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 215292 kb
Host smart-40963fa3-fc7f-4ca3-8d62-e80f7f189e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048659458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1048659458
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.2125821138
Short name T206
Test name
Test status
Simulation time 77202050308 ps
CPU time 412.44 seconds
Started Jun 09 01:54:27 PM PDT 24
Finished Jun 09 02:01:20 PM PDT 24
Peak memory 217912 kb
Host smart-54634c0f-a1cd-4efb-9bc4-50406d98e516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125821138 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.2125821138
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2452771418
Short name T138
Test name
Test status
Simulation time 33697068 ps
CPU time 0.91 seconds
Started Jun 09 01:55:47 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 218304 kb
Host smart-036e33f6-cd23-477e-9650-1a20f3b93bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452771418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2452771418
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2580491400
Short name T604
Test name
Test status
Simulation time 44516222 ps
CPU time 1.54 seconds
Started Jun 09 01:55:46 PM PDT 24
Finished Jun 09 01:55:48 PM PDT 24
Peak memory 218252 kb
Host smart-5264493c-885f-4f4c-8089-431d78533d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580491400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2580491400
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1722806037
Short name T785
Test name
Test status
Simulation time 33022775 ps
CPU time 0.91 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:51 PM PDT 24
Peak memory 218388 kb
Host smart-62e123cc-0be1-450f-a58c-6445b396f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722806037 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1722806037
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.63859839
Short name T512
Test name
Test status
Simulation time 40280736 ps
CPU time 1.34 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 216796 kb
Host smart-9c1a7471-55bd-4849-a864-aafb60b6f139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63859839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.63859839
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3119150393
Short name T135
Test name
Test status
Simulation time 29662539 ps
CPU time 1.36 seconds
Started Jun 09 01:55:48 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 225148 kb
Host smart-9b482228-4508-4f29-bf42-b657fb80b2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119150393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3119150393
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2719368623
Short name T525
Test name
Test status
Simulation time 136687407 ps
CPU time 1.83 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218628 kb
Host smart-59c8d761-64ba-472e-9827-23b0a322d6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719368623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2719368623
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3419872426
Short name T6
Test name
Test status
Simulation time 50734714 ps
CPU time 1.12 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:55:50 PM PDT 24
Peak memory 229676 kb
Host smart-c3de9a62-3e1d-452e-b65d-23567e2391d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419872426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3419872426
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.681683660
Short name T696
Test name
Test status
Simulation time 60634233 ps
CPU time 1.27 seconds
Started Jun 09 01:55:48 PM PDT 24
Finished Jun 09 01:55:49 PM PDT 24
Peak memory 216988 kb
Host smart-0ca28127-8154-4e5c-99da-6490ee3c88d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681683660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.681683660
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1249665621
Short name T147
Test name
Test status
Simulation time 22070531 ps
CPU time 1.12 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:55 PM PDT 24
Peak memory 224080 kb
Host smart-24bf1edc-3974-49f8-a105-188c7969aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249665621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1249665621
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2116770934
Short name T382
Test name
Test status
Simulation time 118604396 ps
CPU time 1.44 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218356 kb
Host smart-22767202-756a-4c7e-91b0-46a1bed2778a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116770934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2116770934
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.697514545
Short name T690
Test name
Test status
Simulation time 71871185 ps
CPU time 1.08 seconds
Started Jun 09 01:55:52 PM PDT 24
Finished Jun 09 01:55:54 PM PDT 24
Peak memory 219780 kb
Host smart-2be6d55f-5a08-43d6-8fcb-ab85183aa585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697514545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.697514545
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1740002879
Short name T655
Test name
Test status
Simulation time 66271204 ps
CPU time 1.81 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219044 kb
Host smart-dbfa5954-c851-4a19-914e-38711f9f4bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740002879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1740002879
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3916780560
Short name T622
Test name
Test status
Simulation time 21050807 ps
CPU time 1.08 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 219488 kb
Host smart-237c311d-5093-4c0a-9b83-16f45c5cb85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916780560 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3916780560
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2294077478
Short name T271
Test name
Test status
Simulation time 65168818 ps
CPU time 1.1 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 216944 kb
Host smart-aecef387-0374-46f9-82e8-cadeb20140f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294077478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2294077478
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1318334699
Short name T770
Test name
Test status
Simulation time 19695545 ps
CPU time 1.07 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219500 kb
Host smart-dd891272-a793-498b-ada1-71d14d968787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318334699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1318334699
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.381700661
Short name T706
Test name
Test status
Simulation time 8802847339 ps
CPU time 119.87 seconds
Started Jun 09 01:55:49 PM PDT 24
Finished Jun 09 01:57:49 PM PDT 24
Peak memory 218284 kb
Host smart-9e4264c9-7c1c-4c1b-b052-3c44a1739e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381700661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.381700661
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3547132972
Short name T815
Test name
Test status
Simulation time 18784281 ps
CPU time 1.07 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 218488 kb
Host smart-a317a5a1-412e-4335-a23d-d8f49680e40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547132972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3547132972
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3680515169
Short name T330
Test name
Test status
Simulation time 45325221 ps
CPU time 1.81 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218428 kb
Host smart-a52e8a5e-f56e-4339-bb30-d133b2745c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680515169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3680515169
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.494202123
Short name T667
Test name
Test status
Simulation time 33038734 ps
CPU time 1.08 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 219668 kb
Host smart-c30d5e5c-8a51-493e-8868-ab5b49bdbe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494202123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.494202123
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2929424220
Short name T344
Test name
Test status
Simulation time 35617549 ps
CPU time 1.32 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 217760 kb
Host smart-79bc1ac1-f2fc-46c3-b70f-9eba5c4e1dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929424220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2929424220
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2908270187
Short name T116
Test name
Test status
Simulation time 52714296 ps
CPU time 1.23 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 219044 kb
Host smart-96f0274a-5d21-47bd-9933-1973dfcdc30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908270187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2908270187
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2139826038
Short name T681
Test name
Test status
Simulation time 12777648 ps
CPU time 0.92 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 206532 kb
Host smart-20ddf6d9-a0ee-4f79-bf23-44a48b1f5ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139826038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2139826038
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3084379755
Short name T734
Test name
Test status
Simulation time 10742290 ps
CPU time 0.91 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 215828 kb
Host smart-81c5bf54-951b-4880-91ac-4fc0a4b2ad40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084379755 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3084379755
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3772644194
Short name T513
Test name
Test status
Simulation time 82261012 ps
CPU time 1.11 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 216788 kb
Host smart-579fa254-bb71-4902-b573-d981705c81bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772644194 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3772644194
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3547944523
Short name T483
Test name
Test status
Simulation time 34333395 ps
CPU time 0.95 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 223824 kb
Host smart-585ac8be-cf96-4bb7-8d6b-9ce890dc84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547944523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3547944523
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3120447500
Short name T353
Test name
Test status
Simulation time 62462312 ps
CPU time 1.58 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 218324 kb
Host smart-787bda56-e217-4ea8-9019-2d2e9ceef0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120447500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3120447500
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3360313322
Short name T691
Test name
Test status
Simulation time 31893942 ps
CPU time 0.91 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 215488 kb
Host smart-1eeadcfd-d386-4f3d-81ca-c1a7d6476a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360313322 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3360313322
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3375011751
Short name T767
Test name
Test status
Simulation time 14720419 ps
CPU time 1.06 seconds
Started Jun 09 01:54:31 PM PDT 24
Finished Jun 09 01:54:33 PM PDT 24
Peak memory 206948 kb
Host smart-50054661-aa33-4186-90b1-c82122f6136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375011751 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3375011751
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1373001713
Short name T314
Test name
Test status
Simulation time 40282209 ps
CPU time 0.9 seconds
Started Jun 09 01:54:30 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 215216 kb
Host smart-258241e1-568a-4282-9142-b3d90bb27eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373001713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1373001713
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1185583359
Short name T766
Test name
Test status
Simulation time 510962828 ps
CPU time 2.22 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 215196 kb
Host smart-979cf90b-82ba-486b-a09e-fd32094a0acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185583359 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1185583359
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.59659931
Short name T740
Test name
Test status
Simulation time 32501326232 ps
CPU time 346.13 seconds
Started Jun 09 01:54:27 PM PDT 24
Finished Jun 09 02:00:14 PM PDT 24
Peak memory 218764 kb
Host smart-fcff5211-95f4-4656-947c-10f44c229cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59659931 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.59659931
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1876595953
Short name T569
Test name
Test status
Simulation time 30466272 ps
CPU time 0.93 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:55 PM PDT 24
Peak memory 223868 kb
Host smart-c9d2547e-9327-482e-8586-03146db49202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876595953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1876595953
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2352882216
Short name T270
Test name
Test status
Simulation time 67100581 ps
CPU time 2.32 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 219212 kb
Host smart-38ce4e55-9467-4b07-a2bc-f3f7fa198b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352882216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2352882216
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3868817673
Short name T612
Test name
Test status
Simulation time 50279436 ps
CPU time 0.83 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218364 kb
Host smart-a304363f-ce2d-48f1-a8ab-fd6d8f3c34f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868817673 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3868817673
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.864518995
Short name T423
Test name
Test status
Simulation time 134268653 ps
CPU time 1.25 seconds
Started Jun 09 01:55:53 PM PDT 24
Finished Jun 09 01:55:55 PM PDT 24
Peak memory 217116 kb
Host smart-7738949c-b4c9-4c32-ab60-89dee619802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864518995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.864518995
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.4112307833
Short name T146
Test name
Test status
Simulation time 21063429 ps
CPU time 1.01 seconds
Started Jun 09 01:55:52 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218424 kb
Host smart-28844851-0cb3-4691-9d6b-7fbbc276d02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112307833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4112307833
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1532832641
Short name T596
Test name
Test status
Simulation time 50828012 ps
CPU time 1.45 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 218564 kb
Host smart-3b0bcf42-1698-483b-b386-10ec78cd3a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532832641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1532832641
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.4008356139
Short name T165
Test name
Test status
Simulation time 19156694 ps
CPU time 1.07 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 218584 kb
Host smart-b4f6af01-2066-4c20-9eec-9a70841519c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008356139 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.4008356139
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/84.edn_err.1394975589
Short name T729
Test name
Test status
Simulation time 50705692 ps
CPU time 1.21 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:55 PM PDT 24
Peak memory 219664 kb
Host smart-e446e1bf-4a0e-4d6f-b36b-4776e7524c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394975589 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1394975589
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.4291843562
Short name T520
Test name
Test status
Simulation time 38064623 ps
CPU time 1.27 seconds
Started Jun 09 01:55:51 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 216880 kb
Host smart-541f2437-0f68-43e9-a897-0b11a422f552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291843562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.4291843562
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1780414338
Short name T803
Test name
Test status
Simulation time 91386249 ps
CPU time 0.84 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 218116 kb
Host smart-fc4a3e63-38cb-411d-ac12-e9f4f6020761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780414338 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1780414338
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.703905431
Short name T457
Test name
Test status
Simulation time 59645644 ps
CPU time 1.25 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 216956 kb
Host smart-013bcaae-c7c8-459f-b5bb-daf957d60b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703905431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.703905431
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1795767322
Short name T392
Test name
Test status
Simulation time 32691788 ps
CPU time 0.94 seconds
Started Jun 09 01:55:52 PM PDT 24
Finished Jun 09 01:55:54 PM PDT 24
Peak memory 218452 kb
Host smart-cb6cb5df-7a9b-4b39-a91d-d4ee67c03cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795767322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1795767322
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3575921773
Short name T50
Test name
Test status
Simulation time 48516351 ps
CPU time 1.7 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:52 PM PDT 24
Peak memory 218408 kb
Host smart-8ab967f1-ea26-4743-b8fb-6826ba2a6b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575921773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3575921773
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.3779731349
Short name T129
Test name
Test status
Simulation time 99175578 ps
CPU time 0.98 seconds
Started Jun 09 01:55:52 PM PDT 24
Finished Jun 09 01:55:54 PM PDT 24
Peak memory 219680 kb
Host smart-55ed10f8-31c4-453b-8ee3-193785d05243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779731349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.3779731349
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2569787549
Short name T371
Test name
Test status
Simulation time 111618781 ps
CPU time 1.54 seconds
Started Jun 09 01:55:50 PM PDT 24
Finished Jun 09 01:55:53 PM PDT 24
Peak memory 218324 kb
Host smart-2723104c-a2be-48f0-9767-e0abe41a538a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569787549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2569787549
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1422719185
Short name T490
Test name
Test status
Simulation time 21463408 ps
CPU time 1.05 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 218524 kb
Host smart-9e89acc3-3e29-4bae-9382-06a053a7f1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422719185 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1422719185
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3988935996
Short name T245
Test name
Test status
Simulation time 86094038 ps
CPU time 1.15 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 217072 kb
Host smart-5a133f55-95c2-4734-a83f-acc0fcadb7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988935996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3988935996
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1825038676
Short name T7
Test name
Test status
Simulation time 59685843 ps
CPU time 1.42 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 225928 kb
Host smart-59084650-3374-4fe3-86e7-dcb3bd3936db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825038676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1825038676
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1810099519
Short name T389
Test name
Test status
Simulation time 173068541 ps
CPU time 2.77 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:58 PM PDT 24
Peak memory 219224 kb
Host smart-94e3713f-fc09-4d5d-ac0d-97b5aa21b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810099519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1810099519
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.58421857
Short name T93
Test name
Test status
Simulation time 41727572 ps
CPU time 1.08 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 01:54:36 PM PDT 24
Peak memory 219208 kb
Host smart-e3bf421c-2a57-4016-b2d1-7841e2f2c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58421857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.58421857
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2854053136
Short name T736
Test name
Test status
Simulation time 76354322 ps
CPU time 0.93 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 01:54:34 PM PDT 24
Peak memory 206572 kb
Host smart-da4afa7b-2e96-46a2-8104-b22cda8b5d0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854053136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2854053136
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1553268180
Short name T161
Test name
Test status
Simulation time 43288195 ps
CPU time 0.88 seconds
Started Jun 09 01:54:39 PM PDT 24
Finished Jun 09 01:54:41 PM PDT 24
Peak memory 216292 kb
Host smart-c20fa1b6-c166-4f82-b15e-87da436ca974
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553268180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1553268180
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1075975117
Short name T131
Test name
Test status
Simulation time 46958965 ps
CPU time 1.15 seconds
Started Jun 09 01:54:34 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 216660 kb
Host smart-61afc50e-b504-4f26-81ca-825bb1e418a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075975117 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1075975117
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3961330758
Short name T547
Test name
Test status
Simulation time 19399673 ps
CPU time 1.19 seconds
Started Jun 09 01:54:33 PM PDT 24
Finished Jun 09 01:54:35 PM PDT 24
Peak memory 224068 kb
Host smart-1d1142ff-cc39-4935-a244-add9945a818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961330758 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3961330758
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4264974839
Short name T71
Test name
Test status
Simulation time 42503483 ps
CPU time 1.45 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:31 PM PDT 24
Peak memory 215164 kb
Host smart-02c160f7-9e58-4b63-9e56-93ef4402fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264974839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4264974839
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2146888493
Short name T100
Test name
Test status
Simulation time 25541803 ps
CPU time 0.99 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:29 PM PDT 24
Peak memory 215868 kb
Host smart-1f17c9bb-8f96-4a76-a04d-3f3705be637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146888493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2146888493
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3676290605
Short name T25
Test name
Test status
Simulation time 36408556 ps
CPU time 0.95 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:29 PM PDT 24
Peak memory 207016 kb
Host smart-61538f36-efbe-40ee-bf9b-e25dcd726f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676290605 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3676290605
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.2988401817
Short name T64
Test name
Test status
Simulation time 114230558 ps
CPU time 0.86 seconds
Started Jun 09 01:54:29 PM PDT 24
Finished Jun 09 01:54:30 PM PDT 24
Peak memory 214980 kb
Host smart-2834e1dc-8e7e-4a89-8402-e8e5664a4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988401817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2988401817
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2737752219
Short name T558
Test name
Test status
Simulation time 1849406183 ps
CPU time 3.57 seconds
Started Jun 09 01:54:28 PM PDT 24
Finished Jun 09 01:54:32 PM PDT 24
Peak memory 216980 kb
Host smart-f5d0ffd1-69e4-425a-929b-f2891072b99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737752219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2737752219
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3374333083
Short name T545
Test name
Test status
Simulation time 25030689968 ps
CPU time 661.32 seconds
Started Jun 09 01:54:31 PM PDT 24
Finished Jun 09 02:05:33 PM PDT 24
Peak memory 223568 kb
Host smart-2e368347-92d2-47da-b0a6-b12621186c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374333083 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3374333083
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3890916178
Short name T157
Test name
Test status
Simulation time 33021391 ps
CPU time 0.81 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 218312 kb
Host smart-c6cbb48f-c27b-4d32-8456-a14f52bd280b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890916178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3890916178
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3414370165
Short name T362
Test name
Test status
Simulation time 51790811 ps
CPU time 1.65 seconds
Started Jun 09 01:55:56 PM PDT 24
Finished Jun 09 01:55:58 PM PDT 24
Peak memory 218124 kb
Host smart-69727dbf-f69e-4aa2-9dce-260bbf4928a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414370165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3414370165
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.846823549
Short name T210
Test name
Test status
Simulation time 19924937 ps
CPU time 1.19 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 229660 kb
Host smart-a77b2361-600f-4f5f-b5fe-fd482cb43200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846823549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.846823549
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.229279768
Short name T378
Test name
Test status
Simulation time 193593951 ps
CPU time 1.39 seconds
Started Jun 09 01:55:56 PM PDT 24
Finished Jun 09 01:55:58 PM PDT 24
Peak memory 218256 kb
Host smart-8209acfd-0937-4eac-8159-3c04cb7375ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229279768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.229279768
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3590931695
Short name T649
Test name
Test status
Simulation time 93171626 ps
CPU time 1.28 seconds
Started Jun 09 01:55:56 PM PDT 24
Finished Jun 09 01:55:58 PM PDT 24
Peak memory 225648 kb
Host smart-c80f501e-c78f-4575-add9-3280bb7876bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590931695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3590931695
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.3924550681
Short name T264
Test name
Test status
Simulation time 76410180 ps
CPU time 2.12 seconds
Started Jun 09 01:55:57 PM PDT 24
Finished Jun 09 01:55:59 PM PDT 24
Peak memory 218156 kb
Host smart-80c04188-2b22-49af-b6ef-6545908fadc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924550681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.3924550681
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3467181232
Short name T707
Test name
Test status
Simulation time 23702137 ps
CPU time 1.09 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 218288 kb
Host smart-570fd3c8-ec9c-44c0-89ca-6d5355e4d1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467181232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3467181232
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.303734069
Short name T533
Test name
Test status
Simulation time 72190395 ps
CPU time 1.43 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 217040 kb
Host smart-59de89a9-29b3-4807-824f-b73be4af48b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303734069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.303734069
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.4275610132
Short name T58
Test name
Test status
Simulation time 28558866 ps
CPU time 1 seconds
Started Jun 09 01:55:54 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 223852 kb
Host smart-cee8f322-8e84-4c1c-a9dd-37cc8a2e4f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275610132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.4275610132
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3443028045
Short name T75
Test name
Test status
Simulation time 46660554 ps
CPU time 1.79 seconds
Started Jun 09 01:55:57 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 218316 kb
Host smart-9a6900af-6bb5-49e6-b9d5-9a0da74abf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443028045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3443028045
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1609004684
Short name T136
Test name
Test status
Simulation time 35463412 ps
CPU time 0.91 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 223860 kb
Host smart-4ad93a16-2ffb-4ce7-a7a9-30df2def19dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609004684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1609004684
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.639368567
Short name T531
Test name
Test status
Simulation time 124100965 ps
CPU time 1.4 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:56 PM PDT 24
Peak memory 218548 kb
Host smart-3142d34b-0637-463e-92dc-f0310b3ad51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639368567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.639368567
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3105896179
Short name T831
Test name
Test status
Simulation time 31262094 ps
CPU time 0.98 seconds
Started Jun 09 01:55:55 PM PDT 24
Finished Jun 09 01:55:57 PM PDT 24
Peak memory 223884 kb
Host smart-a2443885-1b6c-47cb-8184-c4a82af16acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105896179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3105896179
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.2820561231
Short name T130
Test name
Test status
Simulation time 40131076 ps
CPU time 1.15 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:55:59 PM PDT 24
Peak memory 220604 kb
Host smart-cfbe4a2a-bf27-4ae3-93a2-dffa54a02bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820561231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2820561231
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.1758027975
Short name T827
Test name
Test status
Simulation time 49035210 ps
CPU time 1.76 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 219744 kb
Host smart-4cb43a7f-27e5-4ea6-8392-18e489c7f48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758027975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.1758027975
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.256582334
Short name T800
Test name
Test status
Simulation time 27021585 ps
CPU time 1.18 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 218616 kb
Host smart-03d24bef-054b-4f8a-be8e-fdd999007530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256582334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.256582334
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2327406459
Short name T837
Test name
Test status
Simulation time 41071803 ps
CPU time 1.09 seconds
Started Jun 09 01:55:58 PM PDT 24
Finished Jun 09 01:56:00 PM PDT 24
Peak memory 219552 kb
Host smart-d903355f-6812-4843-8b93-74ddb74ac427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327406459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2327406459
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3370951451
Short name T158
Test name
Test status
Simulation time 21182339 ps
CPU time 1.08 seconds
Started Jun 09 01:56:16 PM PDT 24
Finished Jun 09 01:56:18 PM PDT 24
Peak memory 224048 kb
Host smart-2830fe92-ec1d-4e75-9834-5e7b6febf8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370951451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3370951451
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3959192084
Short name T291
Test name
Test status
Simulation time 70537840 ps
CPU time 1.48 seconds
Started Jun 09 01:55:59 PM PDT 24
Finished Jun 09 01:56:01 PM PDT 24
Peak memory 219712 kb
Host smart-cbc3bb23-9c2e-430a-b387-6a3d06e9873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959192084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3959192084
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%