Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.56 98.24 93.78 97.02 91.86 96.33 99.77 91.89


Total test records in report: 976
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T794 /workspace/coverage/default/26.edn_disable_auto_req_mode.1437173073 Jun 10 06:33:33 PM PDT 24 Jun 10 06:33:34 PM PDT 24 159699422 ps
T795 /workspace/coverage/default/12.edn_alert_test.2747683543 Jun 10 06:33:00 PM PDT 24 Jun 10 06:33:01 PM PDT 24 20114931 ps
T234 /workspace/coverage/default/1.edn_disable_auto_req_mode.2732586056 Jun 10 06:31:59 PM PDT 24 Jun 10 06:32:00 PM PDT 24 89297610 ps
T796 /workspace/coverage/default/18.edn_genbits.1565986207 Jun 10 06:33:14 PM PDT 24 Jun 10 06:33:15 PM PDT 24 153346403 ps
T797 /workspace/coverage/default/23.edn_intr.2736922411 Jun 10 06:33:29 PM PDT 24 Jun 10 06:33:31 PM PDT 24 26587473 ps
T798 /workspace/coverage/default/6.edn_smoke.691266599 Jun 10 06:32:32 PM PDT 24 Jun 10 06:32:33 PM PDT 24 100871983 ps
T280 /workspace/coverage/default/1.edn_alert.2179702423 Jun 10 06:31:57 PM PDT 24 Jun 10 06:31:59 PM PDT 24 23580817 ps
T799 /workspace/coverage/default/31.edn_err.2892523407 Jun 10 06:33:39 PM PDT 24 Jun 10 06:33:41 PM PDT 24 18838506 ps
T800 /workspace/coverage/default/208.edn_genbits.3383578886 Jun 10 06:35:05 PM PDT 24 Jun 10 06:35:07 PM PDT 24 77248515 ps
T160 /workspace/coverage/default/34.edn_alert.3702644593 Jun 10 06:33:51 PM PDT 24 Jun 10 06:33:53 PM PDT 24 22939257 ps
T180 /workspace/coverage/default/35.edn_alert.3338544049 Jun 10 06:33:48 PM PDT 24 Jun 10 06:33:50 PM PDT 24 178920535 ps
T801 /workspace/coverage/default/47.edn_err.952551894 Jun 10 06:34:12 PM PDT 24 Jun 10 06:34:13 PM PDT 24 22727395 ps
T802 /workspace/coverage/default/23.edn_genbits.2535551620 Jun 10 06:33:25 PM PDT 24 Jun 10 06:33:27 PM PDT 24 35662496 ps
T803 /workspace/coverage/default/209.edn_genbits.2519980660 Jun 10 06:35:03 PM PDT 24 Jun 10 06:35:05 PM PDT 24 93413732 ps
T804 /workspace/coverage/default/2.edn_stress_all.1994890981 Jun 10 06:32:02 PM PDT 24 Jun 10 06:32:07 PM PDT 24 418771426 ps
T805 /workspace/coverage/default/185.edn_genbits.319263899 Jun 10 06:35:00 PM PDT 24 Jun 10 06:35:02 PM PDT 24 71969884 ps
T806 /workspace/coverage/default/287.edn_genbits.1845680711 Jun 10 06:35:11 PM PDT 24 Jun 10 06:35:13 PM PDT 24 54104832 ps
T807 /workspace/coverage/default/95.edn_err.2763425267 Jun 10 06:34:33 PM PDT 24 Jun 10 06:34:35 PM PDT 24 18962992 ps
T808 /workspace/coverage/default/10.edn_err.2815729110 Jun 10 06:33:04 PM PDT 24 Jun 10 06:33:05 PM PDT 24 20864227 ps
T809 /workspace/coverage/default/10.edn_intr.130298149 Jun 10 06:33:00 PM PDT 24 Jun 10 06:33:02 PM PDT 24 27563464 ps
T810 /workspace/coverage/default/21.edn_smoke.2638847356 Jun 10 06:33:24 PM PDT 24 Jun 10 06:33:25 PM PDT 24 16951801 ps
T811 /workspace/coverage/default/38.edn_stress_all.4288128393 Jun 10 06:33:52 PM PDT 24 Jun 10 06:33:58 PM PDT 24 609019720 ps
T153 /workspace/coverage/default/22.edn_alert.2281681359 Jun 10 06:33:25 PM PDT 24 Jun 10 06:33:27 PM PDT 24 24733762 ps
T812 /workspace/coverage/default/127.edn_genbits.492540111 Jun 10 06:34:40 PM PDT 24 Jun 10 06:34:41 PM PDT 24 84995793 ps
T813 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1634000368 Jun 10 06:33:03 PM PDT 24 Jun 10 06:56:44 PM PDT 24 121598652616 ps
T165 /workspace/coverage/default/40.edn_alert.1002870015 Jun 10 06:34:00 PM PDT 24 Jun 10 06:34:01 PM PDT 24 21463464 ps
T814 /workspace/coverage/default/253.edn_genbits.70606114 Jun 10 06:35:01 PM PDT 24 Jun 10 06:35:03 PM PDT 24 99415451 ps
T815 /workspace/coverage/default/265.edn_genbits.1914247762 Jun 10 06:35:09 PM PDT 24 Jun 10 06:35:10 PM PDT 24 330801892 ps
T816 /workspace/coverage/default/225.edn_genbits.2733577109 Jun 10 06:35:00 PM PDT 24 Jun 10 06:35:01 PM PDT 24 135292967 ps
T300 /workspace/coverage/default/294.edn_genbits.740003219 Jun 10 06:35:12 PM PDT 24 Jun 10 06:35:14 PM PDT 24 28075685 ps
T817 /workspace/coverage/default/247.edn_genbits.1888072588 Jun 10 06:35:01 PM PDT 24 Jun 10 06:35:03 PM PDT 24 26594807 ps
T204 /workspace/coverage/default/19.edn_disable_auto_req_mode.2678468914 Jun 10 06:33:19 PM PDT 24 Jun 10 06:33:21 PM PDT 24 51452863 ps
T818 /workspace/coverage/default/41.edn_alert_test.3975501843 Jun 10 06:34:05 PM PDT 24 Jun 10 06:34:07 PM PDT 24 33120950 ps
T819 /workspace/coverage/default/270.edn_genbits.4038998892 Jun 10 06:35:11 PM PDT 24 Jun 10 06:35:13 PM PDT 24 27511779 ps
T820 /workspace/coverage/default/191.edn_genbits.3962531791 Jun 10 06:34:55 PM PDT 24 Jun 10 06:34:56 PM PDT 24 68777972 ps
T821 /workspace/coverage/default/80.edn_err.611234282 Jun 10 06:34:29 PM PDT 24 Jun 10 06:34:30 PM PDT 24 37351687 ps
T822 /workspace/coverage/default/42.edn_stress_all.2614887104 Jun 10 06:34:03 PM PDT 24 Jun 10 06:34:07 PM PDT 24 694542278 ps
T823 /workspace/coverage/default/16.edn_disable_auto_req_mode.2341929567 Jun 10 06:33:10 PM PDT 24 Jun 10 06:33:11 PM PDT 24 61556727 ps
T824 /workspace/coverage/default/10.edn_alert_test.853554209 Jun 10 06:32:58 PM PDT 24 Jun 10 06:32:59 PM PDT 24 190196941 ps
T119 /workspace/coverage/default/0.edn_disable_auto_req_mode.997878158 Jun 10 06:31:48 PM PDT 24 Jun 10 06:31:49 PM PDT 24 33197580 ps
T825 /workspace/coverage/default/219.edn_genbits.3289968328 Jun 10 06:35:09 PM PDT 24 Jun 10 06:35:10 PM PDT 24 70557951 ps
T826 /workspace/coverage/default/45.edn_smoke.3394115916 Jun 10 06:34:06 PM PDT 24 Jun 10 06:34:07 PM PDT 24 40087895 ps
T827 /workspace/coverage/default/38.edn_alert.3048473388 Jun 10 06:33:53 PM PDT 24 Jun 10 06:33:55 PM PDT 24 36999364 ps
T828 /workspace/coverage/default/60.edn_genbits.987479044 Jun 10 06:34:22 PM PDT 24 Jun 10 06:34:23 PM PDT 24 32731498 ps
T829 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.323183568 Jun 10 06:34:09 PM PDT 24 Jun 10 06:49:43 PM PDT 24 165114346266 ps
T830 /workspace/coverage/default/59.edn_err.2254143562 Jun 10 06:34:20 PM PDT 24 Jun 10 06:34:21 PM PDT 24 31836537 ps
T154 /workspace/coverage/default/2.edn_alert.1021471764 Jun 10 06:32:07 PM PDT 24 Jun 10 06:32:09 PM PDT 24 108454487 ps
T199 /workspace/coverage/default/52.edn_err.3423442944 Jun 10 06:34:23 PM PDT 24 Jun 10 06:34:24 PM PDT 24 62157896 ps
T831 /workspace/coverage/default/68.edn_genbits.2068940778 Jun 10 06:34:26 PM PDT 24 Jun 10 06:34:29 PM PDT 24 127342817 ps
T832 /workspace/coverage/default/224.edn_genbits.1080093319 Jun 10 06:35:01 PM PDT 24 Jun 10 06:35:03 PM PDT 24 46774022 ps
T833 /workspace/coverage/default/5.edn_genbits.3113771211 Jun 10 06:32:28 PM PDT 24 Jun 10 06:32:29 PM PDT 24 74441304 ps
T200 /workspace/coverage/default/14.edn_disable.920229383 Jun 10 06:33:04 PM PDT 24 Jun 10 06:33:05 PM PDT 24 30580968 ps
T834 /workspace/coverage/default/61.edn_genbits.3169849921 Jun 10 06:34:21 PM PDT 24 Jun 10 06:34:22 PM PDT 24 104534612 ps
T835 /workspace/coverage/default/41.edn_stress_all.3895706244 Jun 10 06:34:04 PM PDT 24 Jun 10 06:34:08 PM PDT 24 514994768 ps
T836 /workspace/coverage/default/118.edn_genbits.2577510260 Jun 10 06:34:40 PM PDT 24 Jun 10 06:34:42 PM PDT 24 179154745 ps
T837 /workspace/coverage/default/91.edn_err.3874849147 Jun 10 06:34:32 PM PDT 24 Jun 10 06:34:34 PM PDT 24 21685683 ps
T838 /workspace/coverage/default/58.edn_err.4024499902 Jun 10 06:34:15 PM PDT 24 Jun 10 06:34:16 PM PDT 24 18561442 ps
T839 /workspace/coverage/default/97.edn_err.405524729 Jun 10 06:34:37 PM PDT 24 Jun 10 06:34:39 PM PDT 24 36324134 ps
T840 /workspace/coverage/default/51.edn_err.4118609036 Jun 10 06:34:19 PM PDT 24 Jun 10 06:34:20 PM PDT 24 37480105 ps
T95 /workspace/coverage/default/24.edn_intr.377431612 Jun 10 06:33:26 PM PDT 24 Jun 10 06:33:28 PM PDT 24 35761798 ps
T841 /workspace/coverage/default/197.edn_genbits.1394021885 Jun 10 06:34:53 PM PDT 24 Jun 10 06:34:55 PM PDT 24 36183713 ps
T842 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1765065568 Jun 10 07:43:23 PM PDT 24 Jun 10 07:43:27 PM PDT 24 32199357 ps
T843 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2286988182 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:04 PM PDT 24 200494977 ps
T267 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1097494300 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:03 PM PDT 24 333806867 ps
T235 /workspace/coverage/cover_reg_top/8.edn_csr_rw.568057805 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:09 PM PDT 24 14811673 ps
T268 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3380979966 Jun 10 07:43:19 PM PDT 24 Jun 10 07:43:24 PM PDT 24 141014180 ps
T236 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3691640001 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:57 PM PDT 24 84946807 ps
T269 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4289676537 Jun 10 07:42:47 PM PDT 24 Jun 10 07:42:51 PM PDT 24 59933139 ps
T844 /workspace/coverage/cover_reg_top/4.edn_intr_test.567283947 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:02 PM PDT 24 36392518 ps
T845 /workspace/coverage/cover_reg_top/9.edn_intr_test.595981130 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:09 PM PDT 24 11800547 ps
T846 /workspace/coverage/cover_reg_top/10.edn_intr_test.145319038 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:09 PM PDT 24 51191350 ps
T237 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1950522378 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:57 PM PDT 24 216802496 ps
T847 /workspace/coverage/cover_reg_top/1.edn_intr_test.1024859178 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:52 PM PDT 24 26858846 ps
T238 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3729746955 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 30537184 ps
T848 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4125055842 Jun 10 07:43:19 PM PDT 24 Jun 10 07:43:22 PM PDT 24 52688179 ps
T849 /workspace/coverage/cover_reg_top/15.edn_intr_test.2166061757 Jun 10 07:43:17 PM PDT 24 Jun 10 07:43:20 PM PDT 24 92579749 ps
T850 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2542626874 Jun 10 07:43:03 PM PDT 24 Jun 10 07:43:06 PM PDT 24 20970901 ps
T851 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1914271707 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 102447735 ps
T852 /workspace/coverage/cover_reg_top/18.edn_tl_errors.4184762673 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:31 PM PDT 24 196101649 ps
T251 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1818782869 Jun 10 07:43:17 PM PDT 24 Jun 10 07:43:20 PM PDT 24 31494749 ps
T239 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2818493338 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 37945871 ps
T853 /workspace/coverage/cover_reg_top/26.edn_intr_test.2842598492 Jun 10 07:43:31 PM PDT 24 Jun 10 07:43:35 PM PDT 24 11181494 ps
T854 /workspace/coverage/cover_reg_top/30.edn_intr_test.3223060242 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:39 PM PDT 24 16241817 ps
T275 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.781394282 Jun 10 07:43:32 PM PDT 24 Jun 10 07:43:39 PM PDT 24 220819932 ps
T252 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.663883209 Jun 10 07:43:04 PM PDT 24 Jun 10 07:43:07 PM PDT 24 129540747 ps
T855 /workspace/coverage/cover_reg_top/47.edn_intr_test.837842259 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:40 PM PDT 24 21182449 ps
T276 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.588276464 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 330854469 ps
T240 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2753229665 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 36760164 ps
T856 /workspace/coverage/cover_reg_top/13.edn_intr_test.1604888970 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 11408322 ps
T857 /workspace/coverage/cover_reg_top/32.edn_intr_test.2278980753 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:43 PM PDT 24 15595871 ps
T858 /workspace/coverage/cover_reg_top/34.edn_intr_test.693558490 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 11235225 ps
T859 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.444231838 Jun 10 07:43:08 PM PDT 24 Jun 10 07:43:12 PM PDT 24 38794783 ps
T241 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3411409033 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:59 PM PDT 24 41730821 ps
T860 /workspace/coverage/cover_reg_top/6.edn_csr_rw.1717788178 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:09 PM PDT 24 28468338 ps
T861 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1695343059 Jun 10 07:42:47 PM PDT 24 Jun 10 07:42:50 PM PDT 24 21839396 ps
T253 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2537617543 Jun 10 07:42:47 PM PDT 24 Jun 10 07:42:50 PM PDT 24 71399120 ps
T862 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3278316830 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:54 PM PDT 24 133163759 ps
T863 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3312773931 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 96537702 ps
T254 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3635101298 Jun 10 07:42:47 PM PDT 24 Jun 10 07:42:51 PM PDT 24 106748486 ps
T864 /workspace/coverage/cover_reg_top/45.edn_intr_test.113155364 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:44 PM PDT 24 37747969 ps
T865 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.522639214 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 44524587 ps
T242 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.395970685 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 18867235 ps
T255 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3528219737 Jun 10 07:43:04 PM PDT 24 Jun 10 07:43:08 PM PDT 24 312592535 ps
T243 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2733315290 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 44447519 ps
T866 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4020738025 Jun 10 07:43:00 PM PDT 24 Jun 10 07:43:03 PM PDT 24 65814642 ps
T867 /workspace/coverage/cover_reg_top/40.edn_intr_test.3228049703 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 16774615 ps
T868 /workspace/coverage/cover_reg_top/19.edn_tl_errors.27844576 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:31 PM PDT 24 46347145 ps
T869 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2091223374 Jun 10 07:43:16 PM PDT 24 Jun 10 07:43:20 PM PDT 24 224822045 ps
T244 /workspace/coverage/cover_reg_top/13.edn_csr_rw.389066467 Jun 10 07:43:17 PM PDT 24 Jun 10 07:43:20 PM PDT 24 68255052 ps
T870 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2910654115 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:08 PM PDT 24 36358701 ps
T871 /workspace/coverage/cover_reg_top/11.edn_intr_test.3138878190 Jun 10 07:43:16 PM PDT 24 Jun 10 07:43:18 PM PDT 24 15188482 ps
T872 /workspace/coverage/cover_reg_top/25.edn_intr_test.2177482723 Jun 10 07:43:34 PM PDT 24 Jun 10 07:43:37 PM PDT 24 16291362 ps
T873 /workspace/coverage/cover_reg_top/48.edn_intr_test.1367666876 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:44 PM PDT 24 39482265 ps
T245 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3389918328 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:58 PM PDT 24 43443730 ps
T874 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1777007227 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 61948460 ps
T272 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3154145011 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 67502213 ps
T875 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.922223286 Jun 10 07:43:33 PM PDT 24 Jun 10 07:43:37 PM PDT 24 38082809 ps
T876 /workspace/coverage/cover_reg_top/22.edn_intr_test.2787448315 Jun 10 07:43:30 PM PDT 24 Jun 10 07:43:34 PM PDT 24 13698260 ps
T877 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.405201405 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 26852904 ps
T878 /workspace/coverage/cover_reg_top/21.edn_intr_test.3694986317 Jun 10 07:43:30 PM PDT 24 Jun 10 07:43:34 PM PDT 24 18271992 ps
T879 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1414103064 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:09 PM PDT 24 30124314 ps
T880 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1369300011 Jun 10 07:43:07 PM PDT 24 Jun 10 07:43:12 PM PDT 24 75300047 ps
T881 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3667869916 Jun 10 07:43:17 PM PDT 24 Jun 10 07:43:20 PM PDT 24 44156525 ps
T882 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1004697611 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:09 PM PDT 24 103153232 ps
T883 /workspace/coverage/cover_reg_top/12.edn_tl_errors.613020288 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:19 PM PDT 24 327899020 ps
T884 /workspace/coverage/cover_reg_top/6.edn_intr_test.45502545 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:08 PM PDT 24 169080482 ps
T885 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3234093566 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 79484006 ps
T886 /workspace/coverage/cover_reg_top/14.edn_intr_test.1137740747 Jun 10 07:43:13 PM PDT 24 Jun 10 07:43:16 PM PDT 24 51710255 ps
T887 /workspace/coverage/cover_reg_top/17.edn_intr_test.1443175088 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:30 PM PDT 24 126042099 ps
T888 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1573387730 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:52 PM PDT 24 36888385 ps
T889 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2602314548 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 18416004 ps
T890 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3397066962 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:08 PM PDT 24 19387430 ps
T891 /workspace/coverage/cover_reg_top/7.edn_intr_test.1096324803 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:09 PM PDT 24 17694172 ps
T892 /workspace/coverage/cover_reg_top/38.edn_intr_test.2809915260 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:43 PM PDT 24 47112976 ps
T893 /workspace/coverage/cover_reg_top/18.edn_intr_test.3923312215 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:31 PM PDT 24 15424508 ps
T894 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1821005294 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:12 PM PDT 24 234094214 ps
T895 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1712432500 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:32 PM PDT 24 50840897 ps
T896 /workspace/coverage/cover_reg_top/35.edn_intr_test.3099144321 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:39 PM PDT 24 36183921 ps
T246 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4033072001 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:04 PM PDT 24 58192980 ps
T897 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3274270052 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:31 PM PDT 24 673302439 ps
T898 /workspace/coverage/cover_reg_top/43.edn_intr_test.1613033273 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:39 PM PDT 24 20331503 ps
T899 /workspace/coverage/cover_reg_top/27.edn_intr_test.73740349 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 21447766 ps
T900 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1186932867 Jun 10 07:43:30 PM PDT 24 Jun 10 07:43:34 PM PDT 24 52821150 ps
T901 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3083298090 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:58 PM PDT 24 26805305 ps
T902 /workspace/coverage/cover_reg_top/44.edn_intr_test.759302649 Jun 10 07:43:39 PM PDT 24 Jun 10 07:43:44 PM PDT 24 78210488 ps
T903 /workspace/coverage/cover_reg_top/11.edn_csr_rw.879733124 Jun 10 07:43:16 PM PDT 24 Jun 10 07:43:19 PM PDT 24 41098631 ps
T904 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1411592373 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:08 PM PDT 24 27458473 ps
T905 /workspace/coverage/cover_reg_top/31.edn_intr_test.1935174319 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:43 PM PDT 24 70925083 ps
T906 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1458070390 Jun 10 07:43:30 PM PDT 24 Jun 10 07:43:34 PM PDT 24 21041471 ps
T907 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2625854352 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:49 PM PDT 24 22416775 ps
T908 /workspace/coverage/cover_reg_top/19.edn_csr_rw.4164622441 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 21368495 ps
T273 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3204501610 Jun 10 07:43:26 PM PDT 24 Jun 10 07:43:30 PM PDT 24 152564537 ps
T909 /workspace/coverage/cover_reg_top/28.edn_intr_test.1728118918 Jun 10 07:43:31 PM PDT 24 Jun 10 07:43:35 PM PDT 24 12222004 ps
T274 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2909758034 Jun 10 07:43:16 PM PDT 24 Jun 10 07:43:19 PM PDT 24 146469670 ps
T910 /workspace/coverage/cover_reg_top/33.edn_intr_test.1553593783 Jun 10 07:43:36 PM PDT 24 Jun 10 07:43:39 PM PDT 24 56566722 ps
T911 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1274956418 Jun 10 07:43:18 PM PDT 24 Jun 10 07:43:21 PM PDT 24 22706284 ps
T912 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3790110229 Jun 10 07:43:25 PM PDT 24 Jun 10 07:43:28 PM PDT 24 118389560 ps
T913 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.279279475 Jun 10 07:43:09 PM PDT 24 Jun 10 07:43:13 PM PDT 24 63496433 ps
T914 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.676876477 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:32 PM PDT 24 371734559 ps
T915 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4163507798 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 17303173 ps
T247 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3843133852 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:16 PM PDT 24 13139989 ps
T916 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1635480751 Jun 10 07:43:05 PM PDT 24 Jun 10 07:43:09 PM PDT 24 98087245 ps
T917 /workspace/coverage/cover_reg_top/1.edn_csr_rw.663306374 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:52 PM PDT 24 60377614 ps
T918 /workspace/coverage/cover_reg_top/2.edn_intr_test.3817161727 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:49 PM PDT 24 31093221 ps
T919 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2942780317 Jun 10 07:43:21 PM PDT 24 Jun 10 07:43:23 PM PDT 24 28835670 ps
T920 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2746010195 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 38473248 ps
T921 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2315422998 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 184351521 ps
T922 /workspace/coverage/cover_reg_top/46.edn_intr_test.1441776848 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:39 PM PDT 24 13012645 ps
T923 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3546676118 Jun 10 07:42:56 PM PDT 24 Jun 10 07:42:59 PM PDT 24 62023376 ps
T248 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.326689800 Jun 10 07:42:57 PM PDT 24 Jun 10 07:43:01 PM PDT 24 20654475 ps
T924 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.451909548 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:52 PM PDT 24 57686282 ps
T925 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2444920895 Jun 10 07:43:24 PM PDT 24 Jun 10 07:43:27 PM PDT 24 30948090 ps
T249 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.781772335 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:53 PM PDT 24 80432598 ps
T277 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1132876896 Jun 10 07:43:18 PM PDT 24 Jun 10 07:43:22 PM PDT 24 645650498 ps
T926 /workspace/coverage/cover_reg_top/12.edn_intr_test.2682666850 Jun 10 07:43:13 PM PDT 24 Jun 10 07:43:16 PM PDT 24 12863531 ps
T927 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1165396473 Jun 10 07:42:49 PM PDT 24 Jun 10 07:42:55 PM PDT 24 181059586 ps
T928 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.243981509 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:32 PM PDT 24 69286288 ps
T929 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3086678715 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 64412296 ps
T930 /workspace/coverage/cover_reg_top/16.edn_intr_test.1435554822 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:30 PM PDT 24 14977089 ps
T931 /workspace/coverage/cover_reg_top/16.edn_csr_rw.584181808 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:31 PM PDT 24 19397608 ps
T932 /workspace/coverage/cover_reg_top/39.edn_intr_test.1318240416 Jun 10 07:43:34 PM PDT 24 Jun 10 07:43:38 PM PDT 24 26308420 ps
T933 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2308539844 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:54 PM PDT 24 558500354 ps
T934 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2043988455 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:02 PM PDT 24 10747076 ps
T935 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3929818118 Jun 10 07:43:15 PM PDT 24 Jun 10 07:43:19 PM PDT 24 50063289 ps
T936 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3736616629 Jun 10 07:43:16 PM PDT 24 Jun 10 07:43:18 PM PDT 24 34660408 ps
T937 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.862552908 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:00 PM PDT 24 95228223 ps
T938 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.288205870 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 49935531 ps
T939 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3862380639 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 29203952 ps
T940 /workspace/coverage/cover_reg_top/19.edn_intr_test.4248922326 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 22803890 ps
T941 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3216581669 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 25882742 ps
T942 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1683596455 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:50 PM PDT 24 176651531 ps
T943 /workspace/coverage/cover_reg_top/41.edn_intr_test.294123982 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 16432437 ps
T944 /workspace/coverage/cover_reg_top/16.edn_tl_errors.2972148698 Jun 10 07:43:17 PM PDT 24 Jun 10 07:43:20 PM PDT 24 214858827 ps
T945 /workspace/coverage/cover_reg_top/0.edn_intr_test.903282768 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:48 PM PDT 24 55138892 ps
T946 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1657421318 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 20042766 ps
T947 /workspace/coverage/cover_reg_top/15.edn_tl_errors.340940873 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 76443431 ps
T948 /workspace/coverage/cover_reg_top/24.edn_intr_test.837660908 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:31 PM PDT 24 106850999 ps
T949 /workspace/coverage/cover_reg_top/49.edn_intr_test.1783615370 Jun 10 07:43:38 PM PDT 24 Jun 10 07:43:42 PM PDT 24 28665657 ps
T950 /workspace/coverage/cover_reg_top/5.edn_intr_test.3759816684 Jun 10 07:42:56 PM PDT 24 Jun 10 07:42:59 PM PDT 24 31495000 ps
T951 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1547430186 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:49 PM PDT 24 30374483 ps
T952 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3652212091 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:58 PM PDT 24 47233754 ps
T953 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.129619372 Jun 10 07:43:23 PM PDT 24 Jun 10 07:43:26 PM PDT 24 44217593 ps
T954 /workspace/coverage/cover_reg_top/14.edn_csr_rw.752309488 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 94609101 ps
T955 /workspace/coverage/cover_reg_top/4.edn_tl_errors.15707020 Jun 10 07:42:55 PM PDT 24 Jun 10 07:42:59 PM PDT 24 124766595 ps
T956 /workspace/coverage/cover_reg_top/3.edn_intr_test.2620331821 Jun 10 07:42:56 PM PDT 24 Jun 10 07:42:59 PM PDT 24 48166012 ps
T957 /workspace/coverage/cover_reg_top/29.edn_intr_test.601987280 Jun 10 07:43:33 PM PDT 24 Jun 10 07:43:37 PM PDT 24 47011046 ps
T958 /workspace/coverage/cover_reg_top/23.edn_intr_test.1359206236 Jun 10 07:43:29 PM PDT 24 Jun 10 07:43:33 PM PDT 24 28273521 ps
T959 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.808307403 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:30 PM PDT 24 40355041 ps
T960 /workspace/coverage/cover_reg_top/8.edn_intr_test.3695503546 Jun 10 07:43:08 PM PDT 24 Jun 10 07:43:12 PM PDT 24 32331485 ps
T961 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1184258900 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 30689716 ps
T962 /workspace/coverage/cover_reg_top/36.edn_intr_test.2930685480 Jun 10 07:43:40 PM PDT 24 Jun 10 07:43:44 PM PDT 24 19119918 ps
T963 /workspace/coverage/cover_reg_top/1.edn_tl_errors.5463994 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:53 PM PDT 24 43740711 ps
T964 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1736204395 Jun 10 07:43:15 PM PDT 24 Jun 10 07:43:18 PM PDT 24 21712331 ps
T965 /workspace/coverage/cover_reg_top/20.edn_intr_test.2450315952 Jun 10 07:43:27 PM PDT 24 Jun 10 07:43:30 PM PDT 24 163920751 ps
T966 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.514897720 Jun 10 07:43:13 PM PDT 24 Jun 10 07:43:16 PM PDT 24 189042029 ps
T967 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2104559038 Jun 10 07:43:06 PM PDT 24 Jun 10 07:43:10 PM PDT 24 78564888 ps
T968 /workspace/coverage/cover_reg_top/42.edn_intr_test.4206736490 Jun 10 07:43:35 PM PDT 24 Jun 10 07:43:38 PM PDT 24 15275774 ps
T969 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1044965752 Jun 10 07:42:58 PM PDT 24 Jun 10 07:43:02 PM PDT 24 107201529 ps
T970 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3459501642 Jun 10 07:43:14 PM PDT 24 Jun 10 07:43:17 PM PDT 24 86960516 ps
T971 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.111266872 Jun 10 07:43:04 PM PDT 24 Jun 10 07:43:07 PM PDT 24 80409336 ps
T972 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1320491208 Jun 10 07:42:47 PM PDT 24 Jun 10 07:42:51 PM PDT 24 214255961 ps
T250 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3356239609 Jun 10 07:42:56 PM PDT 24 Jun 10 07:43:02 PM PDT 24 413196948 ps
T973 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2667821200 Jun 10 07:43:28 PM PDT 24 Jun 10 07:43:31 PM PDT 24 32619059 ps
T974 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.480719171 Jun 10 07:42:48 PM PDT 24 Jun 10 07:42:52 PM PDT 24 29939223 ps
T975 /workspace/coverage/cover_reg_top/37.edn_intr_test.2097314143 Jun 10 07:43:37 PM PDT 24 Jun 10 07:43:41 PM PDT 24 41546521 ps
T976 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231367461 Jun 10 07:42:46 PM PDT 24 Jun 10 07:42:50 PM PDT 24 155254041 ps

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2674019991
Short name T4
Test name
Test status
Simulation time 73843695045 ps
CPU time 500.77 seconds
Started Jun 10 06:33:22 PM PDT 24
Finished Jun 10 06:41:44 PM PDT 24
Peak memory 219816 kb
Host smart-2a1ecc39-34ca-4900-a88e-18de010f56da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674019991 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2674019991
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/267.edn_genbits.2871127212
Short name T21
Test name
Test status
Simulation time 147649429 ps
CPU time 1.27 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 218124 kb
Host smart-fa12475b-b256-455c-85ff-4d30264b2bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871127212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2871127212
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_err.3097469228
Short name T5
Test name
Test status
Simulation time 82554704 ps
CPU time 1.2 seconds
Started Jun 10 06:33:09 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 225732 kb
Host smart-e7543732-9303-4528-8dd9-5188928e4d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097469228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3097469228
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3536975327
Short name T17
Test name
Test status
Simulation time 425456881 ps
CPU time 7.54 seconds
Started Jun 10 06:32:13 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 237568 kb
Host smart-0a837f63-5be2-4fa6-89eb-50920ea348b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536975327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3536975327
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/47.edn_alert.2496977909
Short name T28
Test name
Test status
Simulation time 46004286 ps
CPU time 1.22 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 218884 kb
Host smart-0ec57e34-b024-4f58-91d9-719ebff1689f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496977909 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2496977909
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/142.edn_genbits.239030366
Short name T42
Test name
Test status
Simulation time 110472078 ps
CPU time 1.61 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 218216 kb
Host smart-8b00a2ff-0bb6-4d6d-b19b-035c49298d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239030366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.239030366
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1885907636
Short name T335
Test name
Test status
Simulation time 358978726 ps
CPU time 1.19 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:01 PM PDT 24
Peak memory 217952 kb
Host smart-278393aa-4df9-4f0d-850e-4bfed4880fd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885907636 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1885907636
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.868314860
Short name T39
Test name
Test status
Simulation time 324369552310 ps
CPU time 1530.88 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:59:24 PM PDT 24
Peak memory 223552 kb
Host smart-0b2fc700-3ef5-4ab1-a3ac-89a32a4b53c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868314860 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.868314860
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2746455828
Short name T173
Test name
Test status
Simulation time 56432438 ps
CPU time 1.11 seconds
Started Jun 10 06:33:41 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 219812 kb
Host smart-ddf12cd7-9af8-477d-bec3-dfebd556971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746455828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2746455828
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/39.edn_err.3895691036
Short name T2
Test name
Test status
Simulation time 74596979 ps
CPU time 1.33 seconds
Started Jun 10 06:33:55 PM PDT 24
Finished Jun 10 06:33:57 PM PDT 24
Peak memory 225636 kb
Host smart-18ba0a59-3d3a-4f53-bb24-e85d82c963ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895691036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3895691036
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/16.edn_alert.2374500743
Short name T113
Test name
Test status
Simulation time 90154165 ps
CPU time 1.2 seconds
Started Jun 10 06:33:11 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 219960 kb
Host smart-9202b464-81b4-4a2e-b558-f14ad058380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374500743 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2374500743
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.1582933480
Short name T282
Test name
Test status
Simulation time 19033129 ps
CPU time 1.02 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:54 PM PDT 24
Peak memory 207032 kb
Host smart-21bed8a3-ec02-4f3f-b3bf-0d3c841fef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582933480 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1582933480
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3131762072
Short name T138
Test name
Test status
Simulation time 105680544 ps
CPU time 1.15 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:52 PM PDT 24
Peak memory 218084 kb
Host smart-21f99a68-a73b-4785-93e3-9601a1aeb76d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131762072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3131762072
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_alert.3477639797
Short name T102
Test name
Test status
Simulation time 27951609 ps
CPU time 1.27 seconds
Started Jun 10 06:33:56 PM PDT 24
Finished Jun 10 06:33:57 PM PDT 24
Peak memory 219000 kb
Host smart-081a6fa5-6b2b-4323-91e5-37ac71cc58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477639797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3477639797
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1048755277
Short name T80
Test name
Test status
Simulation time 16837655 ps
CPU time 0.86 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:33:09 PM PDT 24
Peak memory 214980 kb
Host smart-0157f611-647f-4af9-aa19-0b51ad2c92bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048755277 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1048755277
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.588276464
Short name T276
Test name
Test status
Simulation time 330854469 ps
CPU time 2.34 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 206428 kb
Host smart-9d7973ab-6445-406d-a39c-5664b2fef65e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588276464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.588276464
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2733315290
Short name T243
Test name
Test status
Simulation time 44447519 ps
CPU time 0.88 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206316 kb
Host smart-45bfeca2-9a42-4496-953d-4319be1f9c7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733315290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2733315290
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2267710695
Short name T117
Test name
Test status
Simulation time 239000758 ps
CPU time 1.07 seconds
Started Jun 10 06:33:13 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 216708 kb
Host smart-e3fcb99c-99df-486b-92b1-2e98d757b095
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267710695 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2267710695
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_alert.2236411496
Short name T147
Test name
Test status
Simulation time 33303745 ps
CPU time 1.38 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 219608 kb
Host smart-a4f42f93-5bc2-457d-a647-7dcebfde71f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236411496 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2236411496
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/12.edn_disable.3799289967
Short name T186
Test name
Test status
Simulation time 14906778 ps
CPU time 0.93 seconds
Started Jun 10 06:33:02 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 216360 kb
Host smart-1e44c8fd-d80b-4d51-b472-8a7f42202bcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799289967 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.3799289967
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable.3271816446
Short name T198
Test name
Test status
Simulation time 11003217 ps
CPU time 0.86 seconds
Started Jun 10 06:33:17 PM PDT 24
Finished Jun 10 06:33:19 PM PDT 24
Peak memory 215964 kb
Host smart-4d65aa33-bd7c-443d-8c77-1e5ea06099dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271816446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3271816446
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/29.edn_alert.1603461393
Short name T265
Test name
Test status
Simulation time 47199829 ps
CPU time 1.17 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 219492 kb
Host smart-a0ae0738-65a5-4ee5-936e-7e243f2cf531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603461393 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1603461393
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert.1973128082
Short name T106
Test name
Test status
Simulation time 24087024 ps
CPU time 1.18 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 220364 kb
Host smart-3cd67d4d-a5cd-4811-a144-28f44e4d5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973128082 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1973128082
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert.1849774273
Short name T125
Test name
Test status
Simulation time 32461574 ps
CPU time 1.21 seconds
Started Jun 10 06:33:13 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 218292 kb
Host smart-c1bcde82-400c-4e96-ab09-6af96423db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849774273 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1849774273
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert.1021471764
Short name T154
Test name
Test status
Simulation time 108454487 ps
CPU time 1.26 seconds
Started Jun 10 06:32:07 PM PDT 24
Finished Jun 10 06:32:09 PM PDT 24
Peak memory 218808 kb
Host smart-5b791ac1-463d-4f2e-a476-21f2e4cba03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021471764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1021471764
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/28.edn_err.688262486
Short name T49
Test name
Test status
Simulation time 26664651 ps
CPU time 0.89 seconds
Started Jun 10 06:33:38 PM PDT 24
Finished Jun 10 06:33:39 PM PDT 24
Peak memory 219264 kb
Host smart-a29d3f9a-9cd9-4885-9969-8330be115b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688262486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.688262486
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/14.edn_intr.3635477630
Short name T36
Test name
Test status
Simulation time 25876663 ps
CPU time 0.93 seconds
Started Jun 10 06:33:05 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 215804 kb
Host smart-82fcd29d-1430-48a5-92da-a48d2e8676be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635477630 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3635477630
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/26.edn_disable.671500466
Short name T23
Test name
Test status
Simulation time 42863253 ps
CPU time 0.87 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 215304 kb
Host smart-76e39933-d2ca-4211-bc41-0147c979c3b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671500466 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.671500466
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/4.edn_alert.2285817770
Short name T178
Test name
Test status
Simulation time 28298148 ps
CPU time 1.18 seconds
Started Jun 10 06:32:27 PM PDT 24
Finished Jun 10 06:32:29 PM PDT 24
Peak memory 219416 kb
Host smart-89d8bc62-15fb-444c-93e6-2b060fc8c305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285817770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2285817770
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert.1002870015
Short name T165
Test name
Test status
Simulation time 21463464 ps
CPU time 1.11 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:01 PM PDT 24
Peak memory 215716 kb
Host smart-c919675c-93d7-4cf5-9343-1ef7c119e567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002870015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1002870015
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.30608230
Short name T85
Test name
Test status
Simulation time 81430081 ps
CPU time 1.18 seconds
Started Jun 10 06:34:10 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 216892 kb
Host smart-1a3b82de-d659-4998-9e95-fda3640d3140
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_dis
able_auto_req_mode.30608230
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3701046240
Short name T181
Test name
Test status
Simulation time 19267228 ps
CPU time 1.04 seconds
Started Jun 10 06:34:06 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 218568 kb
Host smart-2d09a3e2-1864-4a57-a2b0-8bba98f0f285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701046240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3701046240
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/170.edn_genbits.361325468
Short name T89
Test name
Test status
Simulation time 58643982 ps
CPU time 1.47 seconds
Started Jun 10 06:34:49 PM PDT 24
Finished Jun 10 06:34:50 PM PDT 24
Peak memory 217352 kb
Host smart-aeac5b06-4463-4ec2-857d-4c18a0c34de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361325468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.361325468
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1532819359
Short name T11
Test name
Test status
Simulation time 69662687 ps
CPU time 1.18 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 219452 kb
Host smart-daf58203-fe73-4b19-9277-1997d4a37f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532819359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1532819359
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_genbits.2773862578
Short name T296
Test name
Test status
Simulation time 93655345 ps
CPU time 1.18 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:27 PM PDT 24
Peak memory 217016 kb
Host smart-a0889efc-994d-4b13-b70a-d7ea4e4368c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773862578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2773862578
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1810101164
Short name T756
Test name
Test status
Simulation time 57309294 ps
CPU time 1.18 seconds
Started Jun 10 06:32:12 PM PDT 24
Finished Jun 10 06:32:14 PM PDT 24
Peak memory 219384 kb
Host smart-b6fd22b3-e777-4c87-8b19-3a7f5bdc8479
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810101164 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1810101164
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_intr.2431667320
Short name T38
Test name
Test status
Simulation time 48082457 ps
CPU time 0.83 seconds
Started Jun 10 06:31:57 PM PDT 24
Finished Jun 10 06:31:59 PM PDT 24
Peak memory 215516 kb
Host smart-a8941986-0e15-417c-b9cf-0afa8abf7877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431667320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2431667320
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/11.edn_alert.394012367
Short name T103
Test name
Test status
Simulation time 49858715 ps
CPU time 1.25 seconds
Started Jun 10 06:32:59 PM PDT 24
Finished Jun 10 06:33:00 PM PDT 24
Peak memory 218028 kb
Host smart-22863636-0631-486b-9133-c18c76a8c921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394012367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.394012367
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.920229383
Short name T200
Test name
Test status
Simulation time 30580968 ps
CPU time 0.8 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 216244 kb
Host smart-38cfd8f2-3825-44bb-b7ae-769bcda4e074
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920229383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.920229383
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1692793472
Short name T172
Test name
Test status
Simulation time 89171241 ps
CPU time 0.83 seconds
Started Jun 10 06:33:06 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 218204 kb
Host smart-3ec372c5-39a3-4d3c-b806-1ead2d41e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692793472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1692793472
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1231388103
Short name T421
Test name
Test status
Simulation time 28001519 ps
CPU time 1.03 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 216620 kb
Host smart-da3d26f3-5a4f-403c-9065-595bd1f8c4ac
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231388103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1231388103
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_alert.2571481711
Short name T140
Test name
Test status
Simulation time 48664948 ps
CPU time 1.18 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:16 PM PDT 24
Peak memory 218320 kb
Host smart-0b7f1746-39ef-449d-98e7-7a23a97dbab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571481711 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2571481711
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.2067310102
Short name T81
Test name
Test status
Simulation time 17712019 ps
CPU time 0.82 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 216164 kb
Host smart-4206b1ab-ddcf-4a69-8c8f-8d8dcc87b772
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067310102 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2067310102
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.2678468914
Short name T204
Test name
Test status
Simulation time 51452863 ps
CPU time 1.52 seconds
Started Jun 10 06:33:19 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 216732 kb
Host smart-9027b1ca-06f7-4125-9229-4f6210e9b4a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678468914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.2678468914
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.3814851333
Short name T195
Test name
Test status
Simulation time 34600485 ps
CPU time 0.84 seconds
Started Jun 10 06:32:11 PM PDT 24
Finished Jun 10 06:32:13 PM PDT 24
Peak memory 216136 kb
Host smart-9b611af1-ba6e-4510-9886-a7ce53418085
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814851333 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3814851333
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/20.edn_alert.999455117
Short name T734
Test name
Test status
Simulation time 91369296 ps
CPU time 1.34 seconds
Started Jun 10 06:33:21 PM PDT 24
Finished Jun 10 06:33:23 PM PDT 24
Peak memory 220068 kb
Host smart-b2a6ce13-d564-41da-8d18-5a9c67dd0e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999455117 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.999455117
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/22.edn_disable.3541485667
Short name T202
Test name
Test status
Simulation time 19622934 ps
CPU time 0.88 seconds
Started Jun 10 06:33:23 PM PDT 24
Finished Jun 10 06:33:24 PM PDT 24
Peak memory 216096 kb
Host smart-4d7c49f5-06d4-4b87-836f-2d99d1c50df6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541485667 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3541485667
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/3.edn_alert.3544795074
Short name T159
Test name
Test status
Simulation time 66954385 ps
CPU time 1.04 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 215508 kb
Host smart-25762a68-d7b3-43cf-8fb5-f3d8886fc91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544795074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.3544795074
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert.32079134
Short name T105
Test name
Test status
Simulation time 113920451 ps
CPU time 1.2 seconds
Started Jun 10 06:34:10 PM PDT 24
Finished Jun 10 06:34:12 PM PDT 24
Peak memory 218340 kb
Host smart-3f436b72-6675-473d-ac5c-7b1d7616a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32079134 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.32079134
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2806745302
Short name T61
Test name
Test status
Simulation time 13372691 ps
CPU time 0.88 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 215084 kb
Host smart-7d44cf22-25ee-4e7d-9ea7-8620197d225f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806745302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2806745302
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/157.edn_genbits.1396592787
Short name T299
Test name
Test status
Simulation time 90502210 ps
CPU time 1.41 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218416 kb
Host smart-b1cd9e1e-d084-4ee5-ba12-3bddb593c1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396592787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1396592787
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3307736678
Short name T294
Test name
Test status
Simulation time 144172868 ps
CPU time 3.17 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 219904 kb
Host smart-f38a5bd4-6d3e-4e4b-9ddf-2c912e5061d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307736678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3307736678
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1630702728
Short name T288
Test name
Test status
Simulation time 35285407 ps
CPU time 1.48 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 218088 kb
Host smart-8fc6ae3b-1564-423d-bca2-c00abcff83e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630702728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1630702728
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.69181065
Short name T769
Test name
Test status
Simulation time 21273416 ps
CPU time 1.09 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 215884 kb
Host smart-6b573999-53a8-43c9-8367-2e9ea212054c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69181065 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.69181065
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/15.edn_alert.4116598340
Short name T101
Test name
Test status
Simulation time 102905290 ps
CPU time 1.22 seconds
Started Jun 10 06:33:12 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 219604 kb
Host smart-3119aae6-afa1-46ba-b909-aed912586ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116598340 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4116598340
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/190.edn_genbits.1248223822
Short name T47
Test name
Test status
Simulation time 37329761 ps
CPU time 1.35 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:57 PM PDT 24
Peak memory 217028 kb
Host smart-92e2cba4-3aca-4a81-b446-1437a9db67db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248223822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1248223822
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1142742193
Short name T331
Test name
Test status
Simulation time 21093162 ps
CPU time 1.08 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:33:08 PM PDT 24
Peak memory 215424 kb
Host smart-b9d8d925-7ad6-4849-93c0-108f8a6e7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142742193 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1142742193
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2909758034
Short name T274
Test name
Test status
Simulation time 146469670 ps
CPU time 1.7 seconds
Started Jun 10 07:43:16 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 206468 kb
Host smart-cdf1fdf0-6f7c-4583-be22-90b982d6c857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909758034 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2909758034
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all.3241051870
Short name T229
Test name
Test status
Simulation time 334083188 ps
CPU time 6.47 seconds
Started Jun 10 06:31:44 PM PDT 24
Finished Jun 10 06:31:50 PM PDT 24
Peak memory 215272 kb
Host smart-2ad593bf-b576-4af5-9d88-ad46f2ee43fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241051870 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3241051870
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/114.edn_genbits.2688743603
Short name T535
Test name
Test status
Simulation time 24022316 ps
CPU time 1.26 seconds
Started Jun 10 06:34:40 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 219460 kb
Host smart-145f4fe1-093f-4357-948a-d192590234d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688743603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2688743603
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2313025020
Short name T507
Test name
Test status
Simulation time 33397246 ps
CPU time 1.29 seconds
Started Jun 10 06:34:43 PM PDT 24
Finished Jun 10 06:34:44 PM PDT 24
Peak memory 216932 kb
Host smart-736f614b-1525-4646-aacd-e2eaed0cdfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313025020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2313025020
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3860271636
Short name T270
Test name
Test status
Simulation time 76295439 ps
CPU time 1.16 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 218416 kb
Host smart-54f8200d-b5d0-41be-b4c6-e575d2e37285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860271636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3860271636
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1764776362
Short name T303
Test name
Test status
Simulation time 56305165 ps
CPU time 1.45 seconds
Started Jun 10 06:34:40 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 218104 kb
Host smart-215acc93-a664-4445-96ea-bfda5ce33511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764776362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1764776362
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1729833004
Short name T304
Test name
Test status
Simulation time 89399053 ps
CPU time 3.05 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:58 PM PDT 24
Peak memory 219728 kb
Host smart-bcfe31ff-bcd7-4aa1-bea9-eb851913d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729833004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1729833004
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.875490563
Short name T308
Test name
Test status
Simulation time 61413092 ps
CPU time 1.12 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:55 PM PDT 24
Peak memory 218344 kb
Host smart-b4c75e46-0c6c-4ae9-a45e-5342340ffa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875490563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.875490563
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4269869452
Short name T263
Test name
Test status
Simulation time 32303737 ps
CPU time 1.27 seconds
Started Jun 10 06:33:20 PM PDT 24
Finished Jun 10 06:33:22 PM PDT 24
Peak memory 216844 kb
Host smart-570adc56-d6da-41de-8332-21c1b59bc6f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269869452 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4269869452
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/201.edn_genbits.1947048364
Short name T59
Test name
Test status
Simulation time 76628321 ps
CPU time 1.31 seconds
Started Jun 10 06:34:57 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 217036 kb
Host smart-df4bd269-135a-4345-9a4d-59226c889532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947048364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1947048364
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_genbits.753863367
Short name T301
Test name
Test status
Simulation time 51177079 ps
CPU time 1.26 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 219576 kb
Host smart-82601100-fd4a-4af7-906f-fe206aaa7a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753863367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.753863367
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.151903099
Short name T94
Test name
Test status
Simulation time 27097807 ps
CPU time 0.98 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 215880 kb
Host smart-b76eabe9-1ca3-46fb-8871-63c178198af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151903099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.151903099
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1547430186
Short name T951
Test name
Test status
Simulation time 30374483 ps
CPU time 1.05 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:49 PM PDT 24
Peak memory 206440 kb
Host smart-f43a4ed3-dda5-4628-b11a-0ba31f2dfe53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547430186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1547430186
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1950522378
Short name T237
Test name
Test status
Simulation time 216802496 ps
CPU time 5.74 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 206436 kb
Host smart-5ea9fe20-c641-4b72-a494-1ca4ade20882
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950522378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1950522378
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1573387730
Short name T888
Test name
Test status
Simulation time 36888385 ps
CPU time 0.88 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 206432 kb
Host smart-01993db6-06c3-4dd7-885a-d7f939109d72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573387730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1573387730
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1320491208
Short name T972
Test name
Test status
Simulation time 214255961 ps
CPU time 1.26 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:42:51 PM PDT 24
Peak memory 214692 kb
Host smart-2c9e4004-bfce-4b52-88cf-204f9b7a4faf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320491208 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1320491208
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2537617543
Short name T253
Test name
Test status
Simulation time 71399120 ps
CPU time 0.95 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 206292 kb
Host smart-e498b907-13b5-4684-9ae8-77e9d9d56b01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537617543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2537617543
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.903282768
Short name T945
Test name
Test status
Simulation time 55138892 ps
CPU time 0.86 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:48 PM PDT 24
Peak memory 206304 kb
Host smart-5a7f2b45-ec17-4006-a5f0-46e6da85e938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903282768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.903282768
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3635101298
Short name T254
Test name
Test status
Simulation time 106748486 ps
CPU time 1.28 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:42:51 PM PDT 24
Peak memory 206416 kb
Host smart-a82e0213-06c3-4861-8644-e3f9f22bfcc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635101298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3635101298
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1165396473
Short name T927
Test name
Test status
Simulation time 181059586 ps
CPU time 2.03 seconds
Started Jun 10 07:42:49 PM PDT 24
Finished Jun 10 07:42:55 PM PDT 24
Peak memory 214728 kb
Host smart-3d939a16-4670-402d-8562-a4f47a5bb059
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165396473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1165396473
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231367461
Short name T976
Test name
Test status
Simulation time 155254041 ps
CPU time 2.36 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 206700 kb
Host smart-e3ceebdd-ca64-4916-9db0-9235be44a9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231367461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4231367461
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1695343059
Short name T861
Test name
Test status
Simulation time 21839396 ps
CPU time 1.14 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 206440 kb
Host smart-92c3a0c2-b0ed-4a4c-b07d-dce3e728dfe5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695343059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1695343059
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.781772335
Short name T249
Test name
Test status
Simulation time 80432598 ps
CPU time 2.03 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:53 PM PDT 24
Peak memory 206444 kb
Host smart-3eb1232d-08d7-4512-8217-fc2236be82cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781772335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.781772335
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.480719171
Short name T974
Test name
Test status
Simulation time 29939223 ps
CPU time 0.83 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 206148 kb
Host smart-bde871ba-31da-46c8-bd72-616d9ad48aee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480719171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.480719171
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2308539844
Short name T933
Test name
Test status
Simulation time 558500354 ps
CPU time 2.36 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:54 PM PDT 24
Peak memory 214664 kb
Host smart-ef0152c6-c731-429d-a94f-d132c495a36f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308539844 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2308539844
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.663306374
Short name T917
Test name
Test status
Simulation time 60377614 ps
CPU time 0.87 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 206328 kb
Host smart-9fde4498-b9b3-4ad7-a1e1-440f27e9f421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663306374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.663306374
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.1024859178
Short name T847
Test name
Test status
Simulation time 26858846 ps
CPU time 0.82 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 206160 kb
Host smart-d960a8b3-0068-43ba-8c41-967cd9d4ee98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024859178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.1024859178
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.451909548
Short name T924
Test name
Test status
Simulation time 57686282 ps
CPU time 1.3 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:52 PM PDT 24
Peak memory 206584 kb
Host smart-e91c392a-dfac-4fea-bc47-53c1de03dd3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451909548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.451909548
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.5463994
Short name T963
Test name
Test status
Simulation time 43740711 ps
CPU time 1.76 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:53 PM PDT 24
Peak memory 214716 kb
Host smart-190cbf3c-4ce8-49e2-96d2-b8a148532aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5463994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.5463994
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1683596455
Short name T942
Test name
Test status
Simulation time 176651531 ps
CPU time 1.57 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:50 PM PDT 24
Peak memory 206412 kb
Host smart-081a73ec-6ce4-457b-83b7-ed724c8907ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683596455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1683596455
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.4125055842
Short name T848
Test name
Test status
Simulation time 52688179 ps
CPU time 1.65 seconds
Started Jun 10 07:43:19 PM PDT 24
Finished Jun 10 07:43:22 PM PDT 24
Peak memory 214844 kb
Host smart-c4c38bf2-6d0b-4b51-a6a0-1b457a7a64e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125055842 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.4125055842
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1004697611
Short name T882
Test name
Test status
Simulation time 103153232 ps
CPU time 0.87 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206140 kb
Host smart-e3572281-efe5-4675-9b5b-517824cec389
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004697611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1004697611
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.145319038
Short name T846
Test name
Test status
Simulation time 51191350 ps
CPU time 0.81 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206092 kb
Host smart-90da73ea-5d72-4d66-8ec2-48ebd5e84b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145319038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.145319038
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3528219737
Short name T255
Test name
Test status
Simulation time 312592535 ps
CPU time 1.47 seconds
Started Jun 10 07:43:04 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 206428 kb
Host smart-ca319a6e-38c9-4608-9f2b-0083e37a81a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528219737 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3528219737
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1821005294
Short name T894
Test name
Test status
Simulation time 234094214 ps
CPU time 2.56 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 214676 kb
Host smart-cab40fc5-c23b-493e-94ae-4b49ac4f5b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821005294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1821005294
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1369300011
Short name T880
Test name
Test status
Simulation time 75300047 ps
CPU time 1.47 seconds
Started Jun 10 07:43:07 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 206448 kb
Host smart-bd338ffd-f598-41f0-aa4f-f03df504ee04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369300011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1369300011
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1765065568
Short name T842
Test name
Test status
Simulation time 32199357 ps
CPU time 1.53 seconds
Started Jun 10 07:43:23 PM PDT 24
Finished Jun 10 07:43:27 PM PDT 24
Peak memory 214724 kb
Host smart-d33152d0-350e-4e2d-91dd-8b1c6fb64689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765065568 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1765065568
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.879733124
Short name T903
Test name
Test status
Simulation time 41098631 ps
CPU time 0.88 seconds
Started Jun 10 07:43:16 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 206196 kb
Host smart-0b8b12fa-25fd-4a94-ac2c-cfad728f6006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879733124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.879733124
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.3138878190
Short name T871
Test name
Test status
Simulation time 15188482 ps
CPU time 0.92 seconds
Started Jun 10 07:43:16 PM PDT 24
Finished Jun 10 07:43:18 PM PDT 24
Peak memory 206276 kb
Host smart-014ec0d3-60a0-4739-b459-3f9d5eda09f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138878190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.3138878190
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3729746955
Short name T238
Test name
Test status
Simulation time 30537184 ps
CPU time 1.12 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 206352 kb
Host smart-d9852d36-ed1c-4944-9dfa-85e71eb66fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729746955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3729746955
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3929818118
Short name T935
Test name
Test status
Simulation time 50063289 ps
CPU time 2.08 seconds
Started Jun 10 07:43:15 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 214752 kb
Host smart-bf620385-2add-4efa-beac-70a9bc6a43c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929818118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3929818118
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.514897720
Short name T966
Test name
Test status
Simulation time 189042029 ps
CPU time 1.57 seconds
Started Jun 10 07:43:13 PM PDT 24
Finished Jun 10 07:43:16 PM PDT 24
Peak memory 214628 kb
Host smart-64599743-08c4-4759-912f-425dd9511193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514897720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.514897720
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1736204395
Short name T964
Test name
Test status
Simulation time 21712331 ps
CPU time 1.46 seconds
Started Jun 10 07:43:15 PM PDT 24
Finished Jun 10 07:43:18 PM PDT 24
Peak memory 218732 kb
Host smart-d6cadf86-1693-42da-afd8-7676f83502fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736204395 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1736204395
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3843133852
Short name T247
Test name
Test status
Simulation time 13139989 ps
CPU time 0.94 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:16 PM PDT 24
Peak memory 206340 kb
Host smart-8407b7ad-e38a-4d8f-8fba-39f95a88568d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843133852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3843133852
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2682666850
Short name T926
Test name
Test status
Simulation time 12863531 ps
CPU time 0.86 seconds
Started Jun 10 07:43:13 PM PDT 24
Finished Jun 10 07:43:16 PM PDT 24
Peak memory 206292 kb
Host smart-87a125a7-9d6c-4ec0-8e66-276314dce7ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682666850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2682666850
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1818782869
Short name T251
Test name
Test status
Simulation time 31494749 ps
CPU time 1.33 seconds
Started Jun 10 07:43:17 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 206504 kb
Host smart-96c8b98a-eacb-419f-8a45-6de44fa108a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818782869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1818782869
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.613020288
Short name T883
Test name
Test status
Simulation time 327899020 ps
CPU time 2.92 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:19 PM PDT 24
Peak memory 214836 kb
Host smart-6c1fc2c1-ef01-4399-b8e1-4162679dca85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613020288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.613020288
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3380979966
Short name T268
Test name
Test status
Simulation time 141014180 ps
CPU time 2.98 seconds
Started Jun 10 07:43:19 PM PDT 24
Finished Jun 10 07:43:24 PM PDT 24
Peak memory 206564 kb
Host smart-6df44a68-f1c6-40be-8ed5-f4819b435257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380979966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3380979966
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2444920895
Short name T925
Test name
Test status
Simulation time 30948090 ps
CPU time 1.07 seconds
Started Jun 10 07:43:24 PM PDT 24
Finished Jun 10 07:43:27 PM PDT 24
Peak memory 206576 kb
Host smart-06a82711-3613-4e05-83f3-4724951ff5f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444920895 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2444920895
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.389066467
Short name T244
Test name
Test status
Simulation time 68255052 ps
CPU time 0.92 seconds
Started Jun 10 07:43:17 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 206584 kb
Host smart-51c0d274-6c48-4e1c-b6d2-858d3cf609ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389066467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.389066467
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1604888970
Short name T856
Test name
Test status
Simulation time 11408322 ps
CPU time 0.85 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 206292 kb
Host smart-708b06c5-5903-427c-a5e5-9932772a0be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604888970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1604888970
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2942780317
Short name T919
Test name
Test status
Simulation time 28835670 ps
CPU time 1.02 seconds
Started Jun 10 07:43:21 PM PDT 24
Finished Jun 10 07:43:23 PM PDT 24
Peak memory 206424 kb
Host smart-650730d9-4dd6-49ed-b0d9-24594a7be767
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942780317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2942780317
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3736616629
Short name T936
Test name
Test status
Simulation time 34660408 ps
CPU time 1.3 seconds
Started Jun 10 07:43:16 PM PDT 24
Finished Jun 10 07:43:18 PM PDT 24
Peak memory 214692 kb
Host smart-bbd8bad6-2c35-4f14-b241-9d9686496f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736616629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3736616629
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3667869916
Short name T881
Test name
Test status
Simulation time 44156525 ps
CPU time 1.56 seconds
Started Jun 10 07:43:17 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 206496 kb
Host smart-1594132d-5a16-45b0-a3c6-a3fb7545ccbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667869916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3667869916
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3234093566
Short name T885
Test name
Test status
Simulation time 79484006 ps
CPU time 1.15 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 214652 kb
Host smart-004f583b-9751-452f-95fe-1aadf6afd057
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234093566 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3234093566
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.752309488
Short name T954
Test name
Test status
Simulation time 94609101 ps
CPU time 0.79 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 206156 kb
Host smart-1973a03c-73fb-483d-8e42-035379414507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752309488 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.752309488
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1137740747
Short name T886
Test name
Test status
Simulation time 51710255 ps
CPU time 0.88 seconds
Started Jun 10 07:43:13 PM PDT 24
Finished Jun 10 07:43:16 PM PDT 24
Peak memory 206436 kb
Host smart-81573ff4-563d-4655-a88c-5ecd4654ece1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137740747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1137740747
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3862380639
Short name T939
Test name
Test status
Simulation time 29203952 ps
CPU time 1.05 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 206396 kb
Host smart-f49c8454-cdac-454f-9596-7b75371ef1d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862380639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3862380639
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1657421318
Short name T946
Test name
Test status
Simulation time 20042766 ps
CPU time 1.34 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 214840 kb
Host smart-fed8af39-3d98-4089-839c-ffacff68e4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657421318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1657421318
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.129619372
Short name T953
Test name
Test status
Simulation time 44217593 ps
CPU time 1.29 seconds
Started Jun 10 07:43:23 PM PDT 24
Finished Jun 10 07:43:26 PM PDT 24
Peak memory 214684 kb
Host smart-85f8fff0-2f85-47b5-91b6-9347a8eee75e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129619372 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.129619372
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1274956418
Short name T911
Test name
Test status
Simulation time 22706284 ps
CPU time 0.88 seconds
Started Jun 10 07:43:18 PM PDT 24
Finished Jun 10 07:43:21 PM PDT 24
Peak memory 206352 kb
Host smart-484c5acd-283d-4207-a5cd-c1149d2beaf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274956418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1274956418
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2166061757
Short name T849
Test name
Test status
Simulation time 92579749 ps
CPU time 0.88 seconds
Started Jun 10 07:43:17 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 206432 kb
Host smart-c30df1e5-7678-4d98-812d-e7a35bc5bc76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166061757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2166061757
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3459501642
Short name T970
Test name
Test status
Simulation time 86960516 ps
CPU time 1.15 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 206404 kb
Host smart-dcfa0717-64c7-4d18-8c5b-85b0eb230377
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459501642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3459501642
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.340940873
Short name T947
Test name
Test status
Simulation time 76443431 ps
CPU time 1.87 seconds
Started Jun 10 07:43:14 PM PDT 24
Finished Jun 10 07:43:17 PM PDT 24
Peak memory 214740 kb
Host smart-a5269692-4eb6-4d7e-b2d7-cc7ddf985bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340940873 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.340940873
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1132876896
Short name T277
Test name
Test status
Simulation time 645650498 ps
CPU time 1.6 seconds
Started Jun 10 07:43:18 PM PDT 24
Finished Jun 10 07:43:22 PM PDT 24
Peak memory 206480 kb
Host smart-05dc4732-88ef-4c31-988e-d2c8b2803ffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132876896 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1132876896
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.405201405
Short name T877
Test name
Test status
Simulation time 26852904 ps
CPU time 0.95 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206340 kb
Host smart-24e1774e-1011-4dd8-b883-c3d800858a76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405201405 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.405201405
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.584181808
Short name T931
Test name
Test status
Simulation time 19397608 ps
CPU time 0.91 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 206364 kb
Host smart-be8537bb-d845-457c-ad32-80630f9b63b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584181808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.584181808
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.1435554822
Short name T930
Test name
Test status
Simulation time 14977089 ps
CPU time 0.92 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 206304 kb
Host smart-44d277a0-d382-43bb-a4db-3e157720de22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435554822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.1435554822
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3216581669
Short name T941
Test name
Test status
Simulation time 25882742 ps
CPU time 1.2 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206392 kb
Host smart-f759ed95-98b7-4854-90b9-f6bc415ba0d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216581669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3216581669
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.2972148698
Short name T944
Test name
Test status
Simulation time 214858827 ps
CPU time 1.96 seconds
Started Jun 10 07:43:17 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 214700 kb
Host smart-53bac041-3825-405a-a16d-c0fa568c396b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972148698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.2972148698
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2091223374
Short name T869
Test name
Test status
Simulation time 224822045 ps
CPU time 1.9 seconds
Started Jun 10 07:43:16 PM PDT 24
Finished Jun 10 07:43:20 PM PDT 24
Peak memory 206404 kb
Host smart-36cea0c0-24ef-44e8-900c-f11b041e3546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091223374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2091223374
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2667821200
Short name T973
Test name
Test status
Simulation time 32619059 ps
CPU time 1.09 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 206492 kb
Host smart-26af5525-c456-47cf-b78b-4871d038009b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667821200 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2667821200
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3790110229
Short name T912
Test name
Test status
Simulation time 118389560 ps
CPU time 0.84 seconds
Started Jun 10 07:43:25 PM PDT 24
Finished Jun 10 07:43:28 PM PDT 24
Peak memory 206404 kb
Host smart-8a3f006a-855d-4178-b351-340757142155
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790110229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3790110229
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1443175088
Short name T887
Test name
Test status
Simulation time 126042099 ps
CPU time 0.93 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 206432 kb
Host smart-960990c9-d13c-4bbf-b521-ed2cdc0d7c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443175088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1443175088
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.808307403
Short name T959
Test name
Test status
Simulation time 40355041 ps
CPU time 0.95 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 206492 kb
Host smart-46be8ee4-5a70-47a4-a8ff-46d231ab9dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808307403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.808307403
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3274270052
Short name T897
Test name
Test status
Simulation time 673302439 ps
CPU time 2.27 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 214656 kb
Host smart-61c308a5-524a-459c-b5c6-25501c419754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274270052 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3274270052
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3204501610
Short name T273
Test name
Test status
Simulation time 152564537 ps
CPU time 1.48 seconds
Started Jun 10 07:43:26 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 214660 kb
Host smart-3b301333-33dd-4e35-a6ef-47b435920ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204501610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3204501610
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.243981509
Short name T928
Test name
Test status
Simulation time 69286288 ps
CPU time 1.06 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:32 PM PDT 24
Peak memory 214744 kb
Host smart-20efd7cb-37ca-4b7e-8040-175eb6a1a289
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243981509 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.243981509
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1458070390
Short name T906
Test name
Test status
Simulation time 21041471 ps
CPU time 0.88 seconds
Started Jun 10 07:43:30 PM PDT 24
Finished Jun 10 07:43:34 PM PDT 24
Peak memory 206132 kb
Host smart-483d5194-f1d6-49d7-b07d-6b17dbdf98d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458070390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1458070390
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.3923312215
Short name T893
Test name
Test status
Simulation time 15424508 ps
CPU time 0.89 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 206424 kb
Host smart-bd0824b0-b89d-429f-9809-ff173c78cd1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923312215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.3923312215
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.922223286
Short name T875
Test name
Test status
Simulation time 38082809 ps
CPU time 1.07 seconds
Started Jun 10 07:43:33 PM PDT 24
Finished Jun 10 07:43:37 PM PDT 24
Peak memory 206424 kb
Host smart-ce90b4bd-f8bd-4c3e-a8b9-088bb1777824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922223286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.922223286
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.4184762673
Short name T852
Test name
Test status
Simulation time 196101649 ps
CPU time 2.15 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 214788 kb
Host smart-2f57741d-4ff1-4085-8e87-478e7e0e4cc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184762673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4184762673
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.676876477
Short name T914
Test name
Test status
Simulation time 371734559 ps
CPU time 2.72 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:32 PM PDT 24
Peak memory 206512 kb
Host smart-87404668-9559-43c3-a113-bcaec6125c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676876477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.676876477
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1186932867
Short name T900
Test name
Test status
Simulation time 52821150 ps
CPU time 1.02 seconds
Started Jun 10 07:43:30 PM PDT 24
Finished Jun 10 07:43:34 PM PDT 24
Peak memory 214536 kb
Host smart-b30c3f7a-877f-4c6d-9044-0477408b6a37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186932867 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1186932867
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.4164622441
Short name T908
Test name
Test status
Simulation time 21368495 ps
CPU time 0.87 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206280 kb
Host smart-db91bad4-9ba1-4184-b15d-6d7745cb9d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164622441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4164622441
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4248922326
Short name T940
Test name
Test status
Simulation time 22803890 ps
CPU time 0.86 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206252 kb
Host smart-f336cdbd-d5a6-4c00-afcf-9c42a13dfd90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248922326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4248922326
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1712432500
Short name T895
Test name
Test status
Simulation time 50840897 ps
CPU time 1.12 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:32 PM PDT 24
Peak memory 206396 kb
Host smart-1cd2baf2-ff2e-4c55-8db6-1899fbe3c031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712432500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1712432500
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.27844576
Short name T868
Test name
Test status
Simulation time 46347145 ps
CPU time 1.84 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 214748 kb
Host smart-32903eab-eda8-4134-a322-c3cf6829efd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27844576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.27844576
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.781394282
Short name T275
Test name
Test status
Simulation time 220819932 ps
CPU time 4.05 seconds
Started Jun 10 07:43:32 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206648 kb
Host smart-cacb8890-0998-4b34-887a-5199138020ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781394282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.781394282
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.3411409033
Short name T241
Test name
Test status
Simulation time 41730821 ps
CPU time 1.62 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 206332 kb
Host smart-c7bf2a84-5187-42ab-af9e-93864db88c8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411409033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.3411409033
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3356239609
Short name T250
Test name
Test status
Simulation time 413196948 ps
CPU time 3.26 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:02 PM PDT 24
Peak memory 206304 kb
Host smart-a4c8a91e-4063-4183-94c0-ee666da749bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356239609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3356239609
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2625854352
Short name T907
Test name
Test status
Simulation time 22416775 ps
CPU time 1.03 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:49 PM PDT 24
Peak memory 206204 kb
Host smart-a326f467-71a1-476a-93cd-929117e66326
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625854352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2625854352
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.862552908
Short name T937
Test name
Test status
Simulation time 95228223 ps
CPU time 1.04 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 206636 kb
Host smart-dd5cf7b8-5062-4a17-a9d6-853f608c9aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862552908 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.862552908
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1044965752
Short name T969
Test name
Test status
Simulation time 107201529 ps
CPU time 0.98 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:02 PM PDT 24
Peak memory 206320 kb
Host smart-f89eeb93-86cc-446a-bb62-c717955d2f16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044965752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1044965752
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3817161727
Short name T918
Test name
Test status
Simulation time 31093221 ps
CPU time 0.93 seconds
Started Jun 10 07:42:46 PM PDT 24
Finished Jun 10 07:42:49 PM PDT 24
Peak memory 206276 kb
Host smart-06aced32-dd0a-454b-8c5a-2498ba5ce221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817161727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3817161727
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2753229665
Short name T240
Test name
Test status
Simulation time 36760164 ps
CPU time 1.04 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206476 kb
Host smart-72a4eff8-fb07-49f9-980e-8d4de1d4c7a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753229665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.2753229665
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3278316830
Short name T862
Test name
Test status
Simulation time 133163759 ps
CPU time 2.53 seconds
Started Jun 10 07:42:48 PM PDT 24
Finished Jun 10 07:42:54 PM PDT 24
Peak memory 214716 kb
Host smart-2b0b71d1-9ae6-487b-9926-2af58eb0bc9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278316830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3278316830
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.4289676537
Short name T269
Test name
Test status
Simulation time 59933139 ps
CPU time 1.55 seconds
Started Jun 10 07:42:47 PM PDT 24
Finished Jun 10 07:42:51 PM PDT 24
Peak memory 214708 kb
Host smart-1815db88-2c61-4599-9db4-f6d03649a5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289676537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.4289676537
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2450315952
Short name T965
Test name
Test status
Simulation time 163920751 ps
CPU time 0.84 seconds
Started Jun 10 07:43:27 PM PDT 24
Finished Jun 10 07:43:30 PM PDT 24
Peak memory 206024 kb
Host smart-e1e9ebe3-c517-44ba-ac46-2d3e30e408e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450315952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2450315952
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3694986317
Short name T878
Test name
Test status
Simulation time 18271992 ps
CPU time 0.83 seconds
Started Jun 10 07:43:30 PM PDT 24
Finished Jun 10 07:43:34 PM PDT 24
Peak memory 206084 kb
Host smart-637c708e-4e5f-4704-a4c4-e8567e6041c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694986317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3694986317
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2787448315
Short name T876
Test name
Test status
Simulation time 13698260 ps
CPU time 1 seconds
Started Jun 10 07:43:30 PM PDT 24
Finished Jun 10 07:43:34 PM PDT 24
Peak memory 206284 kb
Host smart-2fa202d3-7d64-4eac-9044-40742e9eaf97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787448315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2787448315
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1359206236
Short name T958
Test name
Test status
Simulation time 28273521 ps
CPU time 0.87 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206432 kb
Host smart-e5c5c209-7848-43a7-8ec2-b79d6e89daaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359206236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1359206236
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.837660908
Short name T948
Test name
Test status
Simulation time 106850999 ps
CPU time 0.91 seconds
Started Jun 10 07:43:28 PM PDT 24
Finished Jun 10 07:43:31 PM PDT 24
Peak memory 206292 kb
Host smart-76ecd4bd-cdb0-430b-aad5-a451d8e1dea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837660908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.837660908
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2177482723
Short name T872
Test name
Test status
Simulation time 16291362 ps
CPU time 0.89 seconds
Started Jun 10 07:43:34 PM PDT 24
Finished Jun 10 07:43:37 PM PDT 24
Peak memory 206484 kb
Host smart-dc747e71-5e90-40ec-87a0-0a91a2a914dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177482723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2177482723
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.2842598492
Short name T853
Test name
Test status
Simulation time 11181494 ps
CPU time 0.82 seconds
Started Jun 10 07:43:31 PM PDT 24
Finished Jun 10 07:43:35 PM PDT 24
Peak memory 206272 kb
Host smart-11a4b6c8-7b17-4521-b852-e5c9112563b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842598492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.2842598492
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.73740349
Short name T899
Test name
Test status
Simulation time 21447766 ps
CPU time 0.81 seconds
Started Jun 10 07:43:29 PM PDT 24
Finished Jun 10 07:43:33 PM PDT 24
Peak memory 206048 kb
Host smart-0fd20bc3-9d9b-44fb-a785-e581eda9efbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73740349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.73740349
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1728118918
Short name T909
Test name
Test status
Simulation time 12222004 ps
CPU time 0.95 seconds
Started Jun 10 07:43:31 PM PDT 24
Finished Jun 10 07:43:35 PM PDT 24
Peak memory 206364 kb
Host smart-f0d393f9-24ed-4a19-a981-1773c3a6cd48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728118918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1728118918
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.601987280
Short name T957
Test name
Test status
Simulation time 47011046 ps
CPU time 0.9 seconds
Started Jun 10 07:43:33 PM PDT 24
Finished Jun 10 07:43:37 PM PDT 24
Peak memory 206272 kb
Host smart-3f8d3bbb-75b2-4977-acda-78bdc96af855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601987280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.601987280
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.395970685
Short name T242
Test name
Test status
Simulation time 18867235 ps
CPU time 1.21 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206368 kb
Host smart-f10c382f-84dc-4974-9063-027ce3e5c4e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395970685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.395970685
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3086678715
Short name T929
Test name
Test status
Simulation time 64412296 ps
CPU time 2.1 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 206444 kb
Host smart-62a01867-5899-4b3c-92c3-0b0451dd4e79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086678715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3086678715
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3389918328
Short name T245
Test name
Test status
Simulation time 43443730 ps
CPU time 0.84 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:58 PM PDT 24
Peak memory 206140 kb
Host smart-479ffe08-902a-4c7a-b900-8d1e6dc9d87b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389918328 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3389918328
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3652212091
Short name T952
Test name
Test status
Simulation time 47233754 ps
CPU time 1.25 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:58 PM PDT 24
Peak memory 216376 kb
Host smart-792d3260-8ac9-498e-a806-bd30b74026b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652212091 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3652212091
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2043988455
Short name T934
Test name
Test status
Simulation time 10747076 ps
CPU time 0.85 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:02 PM PDT 24
Peak memory 206356 kb
Host smart-445a8aa9-be3c-4651-b64b-326e5c39809b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043988455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2043988455
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2620331821
Short name T956
Test name
Test status
Simulation time 48166012 ps
CPU time 0.77 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 206084 kb
Host smart-cd5ffa69-71da-447a-8030-01ae6860aad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620331821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2620331821
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4163507798
Short name T915
Test name
Test status
Simulation time 17303173 ps
CPU time 1.01 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 206432 kb
Host smart-6d43cac7-6bcf-47b2-af9a-d089f510fa1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163507798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.4163507798
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3083298090
Short name T901
Test name
Test status
Simulation time 26805305 ps
CPU time 1.52 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:58 PM PDT 24
Peak memory 214640 kb
Host smart-cbb3c488-6f80-4324-9662-48d5f5cdeefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083298090 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3083298090
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1097494300
Short name T267
Test name
Test status
Simulation time 333806867 ps
CPU time 2.11 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:03 PM PDT 24
Peak memory 206396 kb
Host smart-663f9d04-3f75-4e2e-996f-91f0289f2173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097494300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1097494300
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3223060242
Short name T854
Test name
Test status
Simulation time 16241817 ps
CPU time 0.85 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206304 kb
Host smart-f3e9f94a-d7fe-4724-88ea-19caeefff512
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223060242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3223060242
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1935174319
Short name T905
Test name
Test status
Simulation time 70925083 ps
CPU time 0.83 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 205924 kb
Host smart-4759ae53-e8f1-4048-98c3-d386434e6ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935174319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1935174319
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.2278980753
Short name T857
Test name
Test status
Simulation time 15595871 ps
CPU time 0.97 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 206284 kb
Host smart-27074b81-8e0b-4870-bec6-003c8d60f8ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278980753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2278980753
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.1553593783
Short name T910
Test name
Test status
Simulation time 56566722 ps
CPU time 0.9 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206252 kb
Host smart-b0393adb-8ef8-4177-8082-cf8a10964a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553593783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.1553593783
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.693558490
Short name T858
Test name
Test status
Simulation time 11235225 ps
CPU time 0.85 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 206268 kb
Host smart-d1094e85-f7bf-4e62-aa4f-bd676f5029d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693558490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.693558490
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3099144321
Short name T896
Test name
Test status
Simulation time 36183921 ps
CPU time 0.81 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206220 kb
Host smart-e0ac43c4-4040-4c1d-992a-55ff33f934ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099144321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3099144321
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2930685480
Short name T962
Test name
Test status
Simulation time 19119918 ps
CPU time 0.85 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 206152 kb
Host smart-4f67c374-a42e-4cd1-b61c-015b7999c927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930685480 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2930685480
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2097314143
Short name T975
Test name
Test status
Simulation time 41546521 ps
CPU time 0.87 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 206292 kb
Host smart-618eccfc-160a-47bb-aded-d0e97ee0f6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097314143 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2097314143
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2809915260
Short name T892
Test name
Test status
Simulation time 47112976 ps
CPU time 0.96 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:43 PM PDT 24
Peak memory 206432 kb
Host smart-d9dca4ca-7bfc-4d5a-bd7e-51893ede1658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809915260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2809915260
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.1318240416
Short name T932
Test name
Test status
Simulation time 26308420 ps
CPU time 0.87 seconds
Started Jun 10 07:43:34 PM PDT 24
Finished Jun 10 07:43:38 PM PDT 24
Peak memory 206288 kb
Host smart-2dd6c1c4-334b-45ea-96a5-e755468d0d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318240416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.1318240416
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.326689800
Short name T248
Test name
Test status
Simulation time 20654475 ps
CPU time 1.34 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206368 kb
Host smart-d48345f4-e201-4d4a-9f88-2de47fe42e29
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326689800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.326689800
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.4033072001
Short name T246
Test name
Test status
Simulation time 58192980 ps
CPU time 3.3 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 206364 kb
Host smart-70c39215-4d20-4a2e-a99b-2ffa2859c05d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033072001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.4033072001
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2602314548
Short name T889
Test name
Test status
Simulation time 18416004 ps
CPU time 1.03 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206344 kb
Host smart-b42cd928-2c07-43f5-85df-1191d2e44645
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602314548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2602314548
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1777007227
Short name T874
Test name
Test status
Simulation time 61948460 ps
CPU time 1.18 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 214844 kb
Host smart-e82c8b91-a00e-4854-86f7-7c82432e6e1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777007227 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1777007227
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3546676118
Short name T923
Test name
Test status
Simulation time 62023376 ps
CPU time 0.91 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 206356 kb
Host smart-c1b44338-5f7a-4a31-90c4-795b8f040b65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546676118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3546676118
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.567283947
Short name T844
Test name
Test status
Simulation time 36392518 ps
CPU time 0.84 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:02 PM PDT 24
Peak memory 206364 kb
Host smart-0d6510d8-6b7b-4e10-96e1-48f814dc6d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567283947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.567283947
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3691640001
Short name T236
Test name
Test status
Simulation time 84946807 ps
CPU time 1.11 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:57 PM PDT 24
Peak memory 206416 kb
Host smart-9925795e-af00-455c-b74c-8f83c6d863cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691640001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3691640001
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.15707020
Short name T955
Test name
Test status
Simulation time 124766595 ps
CPU time 2.78 seconds
Started Jun 10 07:42:55 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 214792 kb
Host smart-84a9fb5f-10e0-4774-9fce-4a2c83bcb1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15707020 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.15707020
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.3154145011
Short name T272
Test name
Test status
Simulation time 67502213 ps
CPU time 1.61 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 206424 kb
Host smart-01caf8ad-8fbd-4ab0-b110-cc188d25719e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154145011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.3154145011
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.3228049703
Short name T867
Test name
Test status
Simulation time 16774615 ps
CPU time 0.86 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 206084 kb
Host smart-bb4e7152-bc90-4a35-99a6-51afae998927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228049703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.3228049703
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.294123982
Short name T943
Test name
Test status
Simulation time 16432437 ps
CPU time 0.95 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:41 PM PDT 24
Peak memory 206272 kb
Host smart-81e4378f-c45f-4a19-be31-4fbf7de8947a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294123982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.294123982
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.4206736490
Short name T968
Test name
Test status
Simulation time 15275774 ps
CPU time 0.92 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:38 PM PDT 24
Peak memory 206232 kb
Host smart-d3281eea-8b34-4ccb-a050-10401510c5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206736490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.4206736490
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1613033273
Short name T898
Test name
Test status
Simulation time 20331503 ps
CPU time 0.82 seconds
Started Jun 10 07:43:36 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206080 kb
Host smart-f7b2c585-eac2-4b57-8f4d-9183c33da8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613033273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1613033273
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.759302649
Short name T902
Test name
Test status
Simulation time 78210488 ps
CPU time 0.86 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 206080 kb
Host smart-b7f31caf-dded-4878-aeca-e8a77304bdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759302649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.759302649
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.113155364
Short name T864
Test name
Test status
Simulation time 37747969 ps
CPU time 0.82 seconds
Started Jun 10 07:43:39 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 206072 kb
Host smart-2eadc53f-9c30-4081-9192-7e916f7b503f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113155364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.113155364
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1441776848
Short name T922
Test name
Test status
Simulation time 13012645 ps
CPU time 0.88 seconds
Started Jun 10 07:43:35 PM PDT 24
Finished Jun 10 07:43:39 PM PDT 24
Peak memory 206264 kb
Host smart-36e33a75-723d-4d74-8d93-8b1ef4a0be07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441776848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1441776848
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.837842259
Short name T855
Test name
Test status
Simulation time 21182449 ps
CPU time 0.85 seconds
Started Jun 10 07:43:37 PM PDT 24
Finished Jun 10 07:43:40 PM PDT 24
Peak memory 206272 kb
Host smart-ec3403bc-5fff-4aa2-9513-3fffbe0ad458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837842259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.837842259
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1367666876
Short name T873
Test name
Test status
Simulation time 39482265 ps
CPU time 0.82 seconds
Started Jun 10 07:43:40 PM PDT 24
Finished Jun 10 07:43:44 PM PDT 24
Peak memory 206040 kb
Host smart-0630e914-185c-4f30-822b-f4f6048b692f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367666876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1367666876
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1783615370
Short name T949
Test name
Test status
Simulation time 28665657 ps
CPU time 0.89 seconds
Started Jun 10 07:43:38 PM PDT 24
Finished Jun 10 07:43:42 PM PDT 24
Peak memory 206288 kb
Host smart-6e5561d1-5f44-4879-804b-418a706e2a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783615370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1783615370
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4020738025
Short name T866
Test name
Test status
Simulation time 65814642 ps
CPU time 1.08 seconds
Started Jun 10 07:43:00 PM PDT 24
Finished Jun 10 07:43:03 PM PDT 24
Peak memory 214764 kb
Host smart-9e2645ad-3ee3-442b-ba2e-5bd05e343299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020738025 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4020738025
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.3759816684
Short name T950
Test name
Test status
Simulation time 31495000 ps
CPU time 0.82 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:42:59 PM PDT 24
Peak memory 206072 kb
Host smart-234c39e8-fc9a-45a4-86ce-3d36b2a5cf79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759816684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3759816684
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2818493338
Short name T239
Test name
Test status
Simulation time 37945871 ps
CPU time 1.07 seconds
Started Jun 10 07:42:57 PM PDT 24
Finished Jun 10 07:43:01 PM PDT 24
Peak memory 206404 kb
Host smart-f3913909-33ef-4696-b50a-736c5b79e586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818493338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2818493338
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2286988182
Short name T843
Test name
Test status
Simulation time 200494977 ps
CPU time 3.76 seconds
Started Jun 10 07:42:58 PM PDT 24
Finished Jun 10 07:43:04 PM PDT 24
Peak memory 214760 kb
Host smart-a79e798a-a8ad-40b6-9288-205c2f1c5f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286988182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2286988182
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1414103064
Short name T879
Test name
Test status
Simulation time 30124314 ps
CPU time 1.35 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 214820 kb
Host smart-f5974d40-f212-49ff-8869-9a3ebde3a110
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414103064 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1414103064
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.1717788178
Short name T860
Test name
Test status
Simulation time 28468338 ps
CPU time 0.95 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206292 kb
Host smart-9a1a5ad5-b626-4415-81ee-543b019f409b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717788178 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.1717788178
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.45502545
Short name T884
Test name
Test status
Simulation time 169080482 ps
CPU time 0.9 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 206272 kb
Host smart-cfd48108-e1cb-4ae8-b01d-33dcf4b4092a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45502545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.45502545
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.279279475
Short name T913
Test name
Test status
Simulation time 63496433 ps
CPU time 1.17 seconds
Started Jun 10 07:43:09 PM PDT 24
Finished Jun 10 07:43:13 PM PDT 24
Peak memory 206404 kb
Host smart-94b871b0-1c25-4f6c-a35b-4b91bc7f627a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279279475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.279279475
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1914271707
Short name T851
Test name
Test status
Simulation time 102447735 ps
CPU time 1.8 seconds
Started Jun 10 07:42:56 PM PDT 24
Finished Jun 10 07:43:00 PM PDT 24
Peak memory 218428 kb
Host smart-3eb69a78-cf2a-48a6-bd05-114ecb88148e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914271707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1914271707
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.288205870
Short name T938
Test name
Test status
Simulation time 49935531 ps
CPU time 1.87 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 206492 kb
Host smart-fe810c17-eb32-48b6-a81f-c4650bdb30ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288205870 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.288205870
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.111266872
Short name T971
Test name
Test status
Simulation time 80409336 ps
CPU time 1.31 seconds
Started Jun 10 07:43:04 PM PDT 24
Finished Jun 10 07:43:07 PM PDT 24
Peak memory 214704 kb
Host smart-06a63e1d-68e3-4729-b6aa-2b1ce9cb7dc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111266872 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.111266872
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1411592373
Short name T904
Test name
Test status
Simulation time 27458473 ps
CPU time 0.85 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 206316 kb
Host smart-8d6fc5ea-e904-4427-a259-88352cde9ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411592373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1411592373
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1096324803
Short name T891
Test name
Test status
Simulation time 17694172 ps
CPU time 0.81 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206068 kb
Host smart-920f9aaf-4d6f-4174-80f8-17b9ff947236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096324803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1096324803
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.663883209
Short name T252
Test name
Test status
Simulation time 129540747 ps
CPU time 1.43 seconds
Started Jun 10 07:43:04 PM PDT 24
Finished Jun 10 07:43:07 PM PDT 24
Peak memory 206480 kb
Host smart-73911b8b-a30b-43b8-9cd4-f3c89618ecbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663883209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.663883209
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2746010195
Short name T920
Test name
Test status
Simulation time 38473248 ps
CPU time 1.64 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 214680 kb
Host smart-bf463468-ea93-43ca-8afd-3b643a83c84a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746010195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2746010195
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.522639214
Short name T865
Test name
Test status
Simulation time 44524587 ps
CPU time 1.56 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 206504 kb
Host smart-648c2630-28f5-4c8f-aa0b-21ea31daebe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522639214 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.522639214
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.444231838
Short name T859
Test name
Test status
Simulation time 38794783 ps
CPU time 1.13 seconds
Started Jun 10 07:43:08 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 216568 kb
Host smart-5bd3e751-91a7-4e02-ba20-51b8de6448f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444231838 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.444231838
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.568057805
Short name T235
Test name
Test status
Simulation time 14811673 ps
CPU time 0.96 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206372 kb
Host smart-1d9898b9-c769-449f-9e3b-85cec572a4d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568057805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.568057805
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3695503546
Short name T960
Test name
Test status
Simulation time 32331485 ps
CPU time 0.91 seconds
Started Jun 10 07:43:08 PM PDT 24
Finished Jun 10 07:43:12 PM PDT 24
Peak memory 206408 kb
Host smart-6d3706f0-7758-49a5-949e-961b9a896ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695503546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3695503546
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2910654115
Short name T870
Test name
Test status
Simulation time 36358701 ps
CPU time 1.01 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 206420 kb
Host smart-610d9e1a-c5d6-4042-9c6b-4ed029c7d41b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910654115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2910654115
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2542626874
Short name T850
Test name
Test status
Simulation time 20970901 ps
CPU time 1.52 seconds
Started Jun 10 07:43:03 PM PDT 24
Finished Jun 10 07:43:06 PM PDT 24
Peak memory 214680 kb
Host smart-c82a3ee1-355c-45cd-9384-163ba8695b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542626874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2542626874
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1635480751
Short name T916
Test name
Test status
Simulation time 98087245 ps
CPU time 1.68 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206572 kb
Host smart-7161aebe-3c6a-4b0f-8b21-25a44aa1f3a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635480751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1635480751
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3312773931
Short name T863
Test name
Test status
Simulation time 96537702 ps
CPU time 1.54 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 214684 kb
Host smart-80b64036-2482-43c0-a78b-97c3ca17c200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312773931 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3312773931
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3397066962
Short name T890
Test name
Test status
Simulation time 19387430 ps
CPU time 0.98 seconds
Started Jun 10 07:43:05 PM PDT 24
Finished Jun 10 07:43:08 PM PDT 24
Peak memory 206292 kb
Host smart-265814e0-c020-4545-a686-b6d81c543321
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397066962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3397066962
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.595981130
Short name T845
Test name
Test status
Simulation time 11800547 ps
CPU time 0.86 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:09 PM PDT 24
Peak memory 206228 kb
Host smart-2294d315-9543-411b-9ef5-d6dc91e7d0d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595981130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.595981130
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2104559038
Short name T967
Test name
Test status
Simulation time 78564888 ps
CPU time 1.4 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 206476 kb
Host smart-df3a05ce-a4c2-4aa0-b1e0-f5d626724752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104559038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2104559038
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1184258900
Short name T961
Test name
Test status
Simulation time 30689716 ps
CPU time 2.07 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 214700 kb
Host smart-3e16f954-48c1-41e7-b797-ba8163366188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184258900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1184258900
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2315422998
Short name T921
Test name
Test status
Simulation time 184351521 ps
CPU time 1.66 seconds
Started Jun 10 07:43:06 PM PDT 24
Finished Jun 10 07:43:10 PM PDT 24
Peak memory 206548 kb
Host smart-c99afe6d-e944-4a06-a4b5-54cf8f168c95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315422998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2315422998
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.684490067
Short name T793
Test name
Test status
Simulation time 46184505 ps
CPU time 1.2 seconds
Started Jun 10 06:31:49 PM PDT 24
Finished Jun 10 06:31:51 PM PDT 24
Peak memory 220152 kb
Host smart-144289ca-2761-440f-b564-4135735ae9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684490067 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.684490067
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1095949889
Short name T553
Test name
Test status
Simulation time 25584372 ps
CPU time 0.86 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 214736 kb
Host smart-2176ff2a-29e0-4cd2-a8d2-66bc634126ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095949889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1095949889
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1789954356
Short name T60
Test name
Test status
Simulation time 45975477 ps
CPU time 0.9 seconds
Started Jun 10 06:31:49 PM PDT 24
Finished Jun 10 06:31:50 PM PDT 24
Peak memory 215828 kb
Host smart-7138397d-bc89-412a-885d-c44ad777ffdb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789954356 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1789954356
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.997878158
Short name T119
Test name
Test status
Simulation time 33197580 ps
CPU time 1.17 seconds
Started Jun 10 06:31:48 PM PDT 24
Finished Jun 10 06:31:49 PM PDT 24
Peak memory 216788 kb
Host smart-f52016f5-fc26-41a4-ad42-d482afbbc282
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997878158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.997878158
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3531568022
Short name T116
Test name
Test status
Simulation time 36719076 ps
CPU time 1.09 seconds
Started Jun 10 06:31:50 PM PDT 24
Finished Jun 10 06:31:51 PM PDT 24
Peak memory 219704 kb
Host smart-ac31c153-d0f5-4899-90bf-9f19a317dea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531568022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3531568022
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2525205959
Short name T271
Test name
Test status
Simulation time 40536904 ps
CPU time 1.52 seconds
Started Jun 10 06:31:40 PM PDT 24
Finished Jun 10 06:31:42 PM PDT 24
Peak memory 217988 kb
Host smart-343f9e4b-ebe1-4f92-bd88-7c883e859c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525205959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2525205959
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1141624462
Short name T387
Test name
Test status
Simulation time 30204382 ps
CPU time 0.91 seconds
Started Jun 10 06:31:54 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 215412 kb
Host smart-31aa34e7-a135-42e9-91b4-b6f868415807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141624462 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1141624462
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1800449940
Short name T284
Test name
Test status
Simulation time 40535912 ps
CPU time 0.92 seconds
Started Jun 10 06:31:40 PM PDT 24
Finished Jun 10 06:31:41 PM PDT 24
Peak memory 206964 kb
Host smart-0cbb4a40-557e-4926-866a-99a0f9aa0b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800449940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1800449940
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.4126677349
Short name T18
Test name
Test status
Simulation time 272482825 ps
CPU time 4.66 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:58 PM PDT 24
Peak memory 236004 kb
Host smart-c8518b91-1522-44a6-b7e9-49d7e627a031
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126677349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.4126677349
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.888118185
Short name T626
Test name
Test status
Simulation time 17245455 ps
CPU time 0.98 seconds
Started Jun 10 06:31:44 PM PDT 24
Finished Jun 10 06:31:45 PM PDT 24
Peak memory 215216 kb
Host smart-a22416cc-c85a-470b-9b9d-bf8f5cfcb5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888118185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.888118185
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.4112802174
Short name T306
Test name
Test status
Simulation time 139737457861 ps
CPU time 888.74 seconds
Started Jun 10 06:31:46 PM PDT 24
Finished Jun 10 06:46:35 PM PDT 24
Peak memory 221352 kb
Host smart-b850513e-9d74-4e6e-bc27-98ffa0628968
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112802174 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.4112802174
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2179702423
Short name T280
Test name
Test status
Simulation time 23580817 ps
CPU time 1.22 seconds
Started Jun 10 06:31:57 PM PDT 24
Finished Jun 10 06:31:59 PM PDT 24
Peak memory 218400 kb
Host smart-f437cb56-4467-4924-b45c-b2a91ab9a470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179702423 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2179702423
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.4225821722
Short name T758
Test name
Test status
Simulation time 32195897 ps
CPU time 1.2 seconds
Started Jun 10 06:32:00 PM PDT 24
Finished Jun 10 06:32:02 PM PDT 24
Peak memory 206784 kb
Host smart-bf19113f-4180-4df5-97e4-542e1080348a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225821722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.4225821722
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.1268383436
Short name T633
Test name
Test status
Simulation time 44134344 ps
CPU time 0.91 seconds
Started Jun 10 06:32:00 PM PDT 24
Finished Jun 10 06:32:01 PM PDT 24
Peak memory 216140 kb
Host smart-fec06411-7019-45d3-b026-35e4bc751abc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268383436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1268383436
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2732586056
Short name T234
Test name
Test status
Simulation time 89297610 ps
CPU time 1.01 seconds
Started Jun 10 06:31:59 PM PDT 24
Finished Jun 10 06:32:00 PM PDT 24
Peak memory 218108 kb
Host smart-ed2e306e-2961-46af-b462-d994e730caf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732586056 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2732586056
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2517735303
Short name T279
Test name
Test status
Simulation time 25795851 ps
CPU time 0.95 seconds
Started Jun 10 06:31:56 PM PDT 24
Finished Jun 10 06:31:57 PM PDT 24
Peak memory 218640 kb
Host smart-36f59d2d-261e-4338-bfb3-618077ad5093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517735303 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2517735303
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2772280689
Short name T704
Test name
Test status
Simulation time 36597454 ps
CPU time 1.37 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:54 PM PDT 24
Peak memory 216900 kb
Host smart-58c45687-9a6f-4f60-a865-6b8d22e393a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772280689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2772280689
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.682692610
Short name T57
Test name
Test status
Simulation time 993152075 ps
CPU time 7.89 seconds
Started Jun 10 06:32:03 PM PDT 24
Finished Jun 10 06:32:12 PM PDT 24
Peak memory 237108 kb
Host smart-c27c1bec-4b88-492c-ac11-658738b8652c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682692610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.682692610
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3065564209
Short name T488
Test name
Test status
Simulation time 59401254 ps
CPU time 0.93 seconds
Started Jun 10 06:31:53 PM PDT 24
Finished Jun 10 06:31:55 PM PDT 24
Peak memory 215204 kb
Host smart-2782046a-351d-424b-a63a-b23c90892522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065564209 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3065564209
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1668056956
Short name T369
Test name
Test status
Simulation time 93000336 ps
CPU time 2.24 seconds
Started Jun 10 06:31:52 PM PDT 24
Finished Jun 10 06:31:54 PM PDT 24
Peak memory 215136 kb
Host smart-8431adef-1ff2-42d6-9ac3-6e34986b3c07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668056956 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1668056956
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.931997154
Short name T213
Test name
Test status
Simulation time 924511183704 ps
CPU time 2220.79 seconds
Started Jun 10 06:31:58 PM PDT 24
Finished Jun 10 07:08:59 PM PDT 24
Peak memory 228864 kb
Host smart-09569330-c5a3-4ded-8bc4-8e814bc33319
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931997154 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.931997154
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3021130336
Short name T99
Test name
Test status
Simulation time 87421174 ps
CPU time 1.15 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 215608 kb
Host smart-a78cc76e-173e-48a3-b3d9-7d92dcd642a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021130336 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3021130336
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.853554209
Short name T824
Test name
Test status
Simulation time 190196941 ps
CPU time 0.98 seconds
Started Jun 10 06:32:58 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 215116 kb
Host smart-d52541e8-bb5c-4911-9992-a38221711f34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853554209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.853554209
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.410985108
Short name T604
Test name
Test status
Simulation time 111831129 ps
CPU time 0.93 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 215852 kb
Host smart-3180de1a-df19-43e6-8eb6-a91d9cbeb990
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410985108 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.410985108
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.779900896
Short name T465
Test name
Test status
Simulation time 45842518 ps
CPU time 1.19 seconds
Started Jun 10 06:32:59 PM PDT 24
Finished Jun 10 06:33:01 PM PDT 24
Peak memory 218088 kb
Host smart-b384c472-d464-417e-bcbc-72c9ad888baa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779900896 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di
sable_auto_req_mode.779900896
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.2815729110
Short name T808
Test name
Test status
Simulation time 20864227 ps
CPU time 1.06 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 218608 kb
Host smart-4dd6902a-15dc-45fb-9c1d-7325063ddf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815729110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2815729110
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1858343982
Short name T453
Test name
Test status
Simulation time 63609279 ps
CPU time 1.28 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:33:06 PM PDT 24
Peak memory 218208 kb
Host smart-0da10148-3c69-4889-9725-4e790b38308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858343982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1858343982
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.130298149
Short name T809
Test name
Test status
Simulation time 27563464 ps
CPU time 0.91 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:02 PM PDT 24
Peak memory 215396 kb
Host smart-11d9bf65-8500-4eaf-9ab2-f3965466c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130298149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.130298149
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1098369112
Short name T738
Test name
Test status
Simulation time 24306457 ps
CPU time 0.93 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:57 PM PDT 24
Peak memory 215216 kb
Host smart-e4c79fa4-462c-45e2-82b0-e562d729b4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098369112 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1098369112
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4274450600
Short name T516
Test name
Test status
Simulation time 398762506 ps
CPU time 4.92 seconds
Started Jun 10 06:32:58 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 215380 kb
Host smart-f64d3a28-f659-45ef-8033-be28e1590a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274450600 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4274450600
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.4051324021
Short name T753
Test name
Test status
Simulation time 12875989159 ps
CPU time 276.14 seconds
Started Jun 10 06:32:59 PM PDT 24
Finished Jun 10 06:37:35 PM PDT 24
Peak memory 217456 kb
Host smart-2866e731-4109-412d-b885-2ad4f6517ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051324021 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.4051324021
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3389648423
Short name T537
Test name
Test status
Simulation time 160305402 ps
CPU time 1.24 seconds
Started Jun 10 06:34:38 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 217168 kb
Host smart-0dcec566-fa02-41bd-b982-9a3a4855fcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389648423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3389648423
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.963173143
Short name T413
Test name
Test status
Simulation time 99485026 ps
CPU time 1.39 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:37 PM PDT 24
Peak memory 218244 kb
Host smart-6b73f0c2-037d-4e8d-80e8-36b8f931355e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963173143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.963173143
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3076988570
Short name T405
Test name
Test status
Simulation time 28237664 ps
CPU time 1.25 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 217020 kb
Host smart-2452adb7-1571-4173-80d3-15053327bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076988570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3076988570
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.330379103
Short name T45
Test name
Test status
Simulation time 40032945 ps
CPU time 1.45 seconds
Started Jun 10 06:34:37 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 218020 kb
Host smart-690c8c1a-cc53-4676-8188-476babf52c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330379103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.330379103
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2537836321
Short name T473
Test name
Test status
Simulation time 34397884 ps
CPU time 1.05 seconds
Started Jun 10 06:34:37 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 216796 kb
Host smart-bd7e3d09-52f7-41df-931d-8351ebb2053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537836321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2537836321
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1417296521
Short name T550
Test name
Test status
Simulation time 100060362 ps
CPU time 1.19 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 216904 kb
Host smart-59edce18-aa7e-46d7-8cbc-d4e76426c7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417296521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1417296521
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1535700674
Short name T297
Test name
Test status
Simulation time 40727141 ps
CPU time 1.41 seconds
Started Jun 10 06:34:43 PM PDT 24
Finished Jun 10 06:34:44 PM PDT 24
Peak memory 217080 kb
Host smart-cdf9bec4-1998-4839-889c-5d47dca39dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535700674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1535700674
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.4029834219
Short name T542
Test name
Test status
Simulation time 59616847 ps
CPU time 2.06 seconds
Started Jun 10 06:34:43 PM PDT 24
Finished Jun 10 06:34:45 PM PDT 24
Peak memory 218268 kb
Host smart-5af38f91-1d19-485e-8368-ce882ff55661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029834219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.4029834219
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1812463711
Short name T641
Test name
Test status
Simulation time 47590865 ps
CPU time 1.01 seconds
Started Jun 10 06:34:42 PM PDT 24
Finished Jun 10 06:34:43 PM PDT 24
Peak memory 216892 kb
Host smart-89d820e9-3ad6-422e-82db-bbd416e32965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812463711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1812463711
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3841982460
Short name T745
Test name
Test status
Simulation time 137553429 ps
CPU time 2.88 seconds
Started Jun 10 06:34:44 PM PDT 24
Finished Jun 10 06:34:47 PM PDT 24
Peak memory 219128 kb
Host smart-f2482d5c-310a-4583-a273-43c0f29bff44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841982460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3841982460
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1963792824
Short name T493
Test name
Test status
Simulation time 22008318 ps
CPU time 1.04 seconds
Started Jun 10 06:33:03 PM PDT 24
Finished Jun 10 06:33:04 PM PDT 24
Peak memory 206668 kb
Host smart-7a0e63ca-6088-4e82-bfd0-497a2aa5907c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963792824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1963792824
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.2390774641
Short name T501
Test name
Test status
Simulation time 12128731 ps
CPU time 0.91 seconds
Started Jun 10 06:32:59 PM PDT 24
Finished Jun 10 06:33:00 PM PDT 24
Peak memory 216068 kb
Host smart-6c91038e-70f8-49bf-8a6c-8dfcea486b85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390774641 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2390774641
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1799871454
Short name T19
Test name
Test status
Simulation time 27863021 ps
CPU time 1.13 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:02 PM PDT 24
Peak memory 217008 kb
Host smart-ad7d3431-edec-44b0-9302-20867ed0051f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799871454 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1799871454
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2666242200
Short name T703
Test name
Test status
Simulation time 29017908 ps
CPU time 1.2 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:02 PM PDT 24
Peak memory 219568 kb
Host smart-642701ed-b427-4c61-bcd7-3e6ec64cbf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666242200 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2666242200
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1782075804
Short name T630
Test name
Test status
Simulation time 88553181 ps
CPU time 2.36 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 217120 kb
Host smart-b3c49235-6f13-4a5b-a76d-8dc0e0b58fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782075804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1782075804
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.2570596395
Short name T35
Test name
Test status
Simulation time 33799379 ps
CPU time 0.92 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:58 PM PDT 24
Peak memory 215580 kb
Host smart-4e413a4e-b71b-441a-be32-b3d9522b4613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570596395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2570596395
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.928889269
Short name T489
Test name
Test status
Simulation time 35642102 ps
CPU time 0.92 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 215216 kb
Host smart-edc07d3e-1e85-4337-9968-479300241b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928889269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.928889269
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.247093946
Short name T398
Test name
Test status
Simulation time 231930690 ps
CPU time 1.85 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:58 PM PDT 24
Peak memory 217144 kb
Host smart-e4f31608-8b58-4ccd-84d7-a46ff046b05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247093946 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.247093946
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1699756554
Short name T219
Test name
Test status
Simulation time 221705986233 ps
CPU time 931.88 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:48:37 PM PDT 24
Peak memory 219708 kb
Host smart-8889834d-aa02-42e8-bf3c-b7263b1007cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699756554 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1699756554
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2309261857
Short name T624
Test name
Test status
Simulation time 46357878 ps
CPU time 1.24 seconds
Started Jun 10 06:34:42 PM PDT 24
Finished Jun 10 06:34:44 PM PDT 24
Peak memory 218464 kb
Host smart-29cbc99c-7dbd-44a5-9489-6da11e0037a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309261857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2309261857
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.875252437
Short name T697
Test name
Test status
Simulation time 58800314 ps
CPU time 2.16 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 218248 kb
Host smart-d19ee2bf-9841-4c48-83f2-a523fc68dddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875252437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.875252437
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1362804143
Short name T636
Test name
Test status
Simulation time 52177740 ps
CPU time 1.84 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:43 PM PDT 24
Peak memory 216904 kb
Host smart-faf97527-12a4-49af-8797-7756e0db58f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362804143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1362804143
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1537032835
Short name T46
Test name
Test status
Simulation time 107603480 ps
CPU time 1.66 seconds
Started Jun 10 06:34:42 PM PDT 24
Finished Jun 10 06:34:44 PM PDT 24
Peak memory 218416 kb
Host smart-40861594-26fc-4faf-adb6-b6e813ae1d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537032835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1537032835
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.4288960066
Short name T652
Test name
Test status
Simulation time 50897859 ps
CPU time 1.45 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:43 PM PDT 24
Peak memory 217068 kb
Host smart-59e7a1c1-6fb5-4632-8152-bf784e259f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288960066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.4288960066
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2577510260
Short name T836
Test name
Test status
Simulation time 179154745 ps
CPU time 1.03 seconds
Started Jun 10 06:34:40 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 216780 kb
Host smart-e0356852-ca47-4a92-b921-e6becb20217e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577510260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2577510260
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3361177178
Short name T723
Test name
Test status
Simulation time 59555555 ps
CPU time 1.57 seconds
Started Jun 10 06:34:47 PM PDT 24
Finished Jun 10 06:34:49 PM PDT 24
Peak memory 218240 kb
Host smart-cf037b11-ef10-433a-82ac-77e93cf7f2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361177178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3361177178
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2821868797
Short name T104
Test name
Test status
Simulation time 32854615 ps
CPU time 1.23 seconds
Started Jun 10 06:33:01 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 219464 kb
Host smart-76f23a43-11c8-4a89-a9a8-ec4859f4b1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821868797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2821868797
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2747683543
Short name T795
Test name
Test status
Simulation time 20114931 ps
CPU time 0.99 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:01 PM PDT 24
Peak memory 206600 kb
Host smart-63a49525-6fd0-4721-ae33-4d290ee00f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747683543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2747683543
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3698359407
Short name T83
Test name
Test status
Simulation time 72378468 ps
CPU time 1.28 seconds
Started Jun 10 06:33:04 PM PDT 24
Finished Jun 10 06:33:06 PM PDT 24
Peak memory 216688 kb
Host smart-ece7fcac-51b0-4d0e-b23b-517dfb97b94e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698359407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3698359407
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.222362474
Short name T678
Test name
Test status
Simulation time 31342675 ps
CPU time 0.87 seconds
Started Jun 10 06:33:19 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 219104 kb
Host smart-5187fa8c-4338-472a-99b3-a3166d5de252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222362474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.222362474
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1676695188
Short name T440
Test name
Test status
Simulation time 77118599 ps
CPU time 1.16 seconds
Started Jun 10 06:33:02 PM PDT 24
Finished Jun 10 06:33:04 PM PDT 24
Peak memory 217000 kb
Host smart-f835973a-1b48-4320-9376-5b3c5474ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676695188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1676695188
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.237195932
Short name T665
Test name
Test status
Simulation time 33307719 ps
CPU time 0.9 seconds
Started Jun 10 06:33:03 PM PDT 24
Finished Jun 10 06:33:04 PM PDT 24
Peak memory 215408 kb
Host smart-89109ef5-595e-47a7-b8f2-4424ec941e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237195932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.237195932
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2608631849
Short name T585
Test name
Test status
Simulation time 17151458 ps
CPU time 1.16 seconds
Started Jun 10 06:33:02 PM PDT 24
Finished Jun 10 06:33:03 PM PDT 24
Peak memory 215188 kb
Host smart-eba7d2ce-91dc-4751-8a6b-bea3f7f4a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608631849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2608631849
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2538989509
Short name T556
Test name
Test status
Simulation time 42310195 ps
CPU time 1.15 seconds
Started Jun 10 06:33:02 PM PDT 24
Finished Jun 10 06:33:04 PM PDT 24
Peak memory 206340 kb
Host smart-74ceef0d-69a6-439c-afa6-31eb3b937997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538989509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2538989509
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1634000368
Short name T813
Test name
Test status
Simulation time 121598652616 ps
CPU time 1420.42 seconds
Started Jun 10 06:33:03 PM PDT 24
Finished Jun 10 06:56:44 PM PDT 24
Peak memory 223544 kb
Host smart-a7c4ea73-ba7d-4c1a-85f1-ec9a9a16fe97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634000368 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1634000368
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2009682340
Short name T345
Test name
Test status
Simulation time 122474716 ps
CPU time 1.3 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:43 PM PDT 24
Peak memory 216940 kb
Host smart-9cbda070-43e5-482c-af25-9e2be41874a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009682340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2009682340
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.4175597220
Short name T426
Test name
Test status
Simulation time 94421416 ps
CPU time 1.37 seconds
Started Jun 10 06:34:44 PM PDT 24
Finished Jun 10 06:34:45 PM PDT 24
Peak memory 218228 kb
Host smart-f5886b18-ba5e-47b9-aad9-8e5527ceb07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175597220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4175597220
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3723470318
Short name T484
Test name
Test status
Simulation time 175556224 ps
CPU time 2.79 seconds
Started Jun 10 06:34:42 PM PDT 24
Finished Jun 10 06:34:45 PM PDT 24
Peak memory 218620 kb
Host smart-4389a9dd-5cec-4786-80ba-b2c60aa63407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723470318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3723470318
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.65816237
Short name T343
Test name
Test status
Simulation time 24753119 ps
CPU time 1.16 seconds
Started Jun 10 06:34:44 PM PDT 24
Finished Jun 10 06:34:45 PM PDT 24
Peak memory 216952 kb
Host smart-d7312dd0-b7f9-4ec8-9c46-72104a05f37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65816237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.65816237
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3310728422
Short name T462
Test name
Test status
Simulation time 135436154 ps
CPU time 3.15 seconds
Started Jun 10 06:34:43 PM PDT 24
Finished Jun 10 06:34:46 PM PDT 24
Peak memory 218404 kb
Host smart-1b6d89d9-ffe8-4966-9bd7-e488206b3404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310728422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3310728422
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3572053811
Short name T777
Test name
Test status
Simulation time 101301477 ps
CPU time 1.13 seconds
Started Jun 10 06:34:41 PM PDT 24
Finished Jun 10 06:34:42 PM PDT 24
Peak memory 218856 kb
Host smart-f53db287-f038-4658-a84a-efb13d163688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572053811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3572053811
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.492540111
Short name T812
Test name
Test status
Simulation time 84995793 ps
CPU time 1.33 seconds
Started Jun 10 06:34:40 PM PDT 24
Finished Jun 10 06:34:41 PM PDT 24
Peak memory 215280 kb
Host smart-b4949ae9-7523-48f3-a929-67bfcd790b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492540111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.492540111
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3377703155
Short name T591
Test name
Test status
Simulation time 45215378 ps
CPU time 1.34 seconds
Started Jun 10 06:34:44 PM PDT 24
Finished Jun 10 06:34:46 PM PDT 24
Peak memory 218316 kb
Host smart-9db80168-4c7e-4731-929c-c799214b096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377703155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3377703155
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2237254319
Short name T690
Test name
Test status
Simulation time 50823575 ps
CPU time 1.46 seconds
Started Jun 10 06:34:52 PM PDT 24
Finished Jun 10 06:34:53 PM PDT 24
Peak memory 218528 kb
Host smart-869caa4e-74ef-419d-b4ed-93d47c14dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237254319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2237254319
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.4033631701
Short name T713
Test name
Test status
Simulation time 14399551 ps
CPU time 0.92 seconds
Started Jun 10 06:33:06 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 206568 kb
Host smart-046be612-de7e-4e42-b627-ac838c5e2a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033631701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4033631701
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_err.1167220498
Short name T127
Test name
Test status
Simulation time 31233928 ps
CPU time 0.92 seconds
Started Jun 10 06:33:09 PM PDT 24
Finished Jun 10 06:33:10 PM PDT 24
Peak memory 219512 kb
Host smart-920bce40-5cac-4523-b7fa-1a0ac631d59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167220498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1167220498
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3863786666
Short name T614
Test name
Test status
Simulation time 46932299 ps
CPU time 1.51 seconds
Started Jun 10 06:33:03 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 219508 kb
Host smart-67bed4e0-aec2-43f0-a0f1-16798066bcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863786666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3863786666
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.732759847
Short name T574
Test name
Test status
Simulation time 27849647 ps
CPU time 0.89 seconds
Started Jun 10 06:33:06 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 215652 kb
Host smart-556de89c-867a-47fa-a920-8295e9649cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732759847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.732759847
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3540533773
Short name T528
Test name
Test status
Simulation time 13881554 ps
CPU time 1 seconds
Started Jun 10 06:33:00 PM PDT 24
Finished Jun 10 06:33:02 PM PDT 24
Peak memory 215184 kb
Host smart-6ed8c678-efb8-4d82-8099-24326c5b6bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540533773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3540533773
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3621613031
Short name T598
Test name
Test status
Simulation time 82871356 ps
CPU time 2.14 seconds
Started Jun 10 06:33:02 PM PDT 24
Finished Jun 10 06:33:04 PM PDT 24
Peak memory 217000 kb
Host smart-2b9d9a5f-9b23-4caf-84a0-278936e79f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621613031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3621613031
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2901061335
Short name T356
Test name
Test status
Simulation time 45175458928 ps
CPU time 228.1 seconds
Started Jun 10 06:33:13 PM PDT 24
Finished Jun 10 06:37:01 PM PDT 24
Peak memory 217200 kb
Host smart-b8ce4815-273c-4ef1-90b8-8b51c73cb581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901061335 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2901061335
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2115683082
Short name T623
Test name
Test status
Simulation time 34903238 ps
CPU time 1.2 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:55 PM PDT 24
Peak memory 216996 kb
Host smart-119492b3-58b2-4a3f-b637-7099ca0daf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115683082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2115683082
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.315077841
Short name T607
Test name
Test status
Simulation time 31888108 ps
CPU time 1.34 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218144 kb
Host smart-9dad9f9c-b074-4cb1-a33a-a51e82d08a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315077841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.315077841
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2658311073
Short name T445
Test name
Test status
Simulation time 53591043 ps
CPU time 1.26 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 218376 kb
Host smart-f058cb59-96a9-4a63-a22e-11a342587b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658311073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2658311073
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3915331471
Short name T79
Test name
Test status
Simulation time 46301691 ps
CPU time 1.27 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 219736 kb
Host smart-9852edab-40e3-40cb-9940-d9278ca6c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915331471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3915331471
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3867485984
Short name T486
Test name
Test status
Simulation time 50365971 ps
CPU time 1.56 seconds
Started Jun 10 06:34:45 PM PDT 24
Finished Jun 10 06:34:47 PM PDT 24
Peak memory 218168 kb
Host smart-8ac40418-1ace-45f8-9c89-75f6d32eceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867485984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3867485984
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2488810872
Short name T733
Test name
Test status
Simulation time 320533268 ps
CPU time 3.48 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 219868 kb
Host smart-3347c0f9-c563-4957-b2a1-6b912a53b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488810872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2488810872
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3589696768
Short name T422
Test name
Test status
Simulation time 125749121 ps
CPU time 1.42 seconds
Started Jun 10 06:34:51 PM PDT 24
Finished Jun 10 06:34:53 PM PDT 24
Peak memory 218560 kb
Host smart-f431d08a-8a86-437a-9390-5930145aa13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589696768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3589696768
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2504712569
Short name T773
Test name
Test status
Simulation time 171297153 ps
CPU time 1.24 seconds
Started Jun 10 06:34:45 PM PDT 24
Finished Jun 10 06:34:46 PM PDT 24
Peak memory 216976 kb
Host smart-59a52fe7-bb79-4062-9e59-112fbea239bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504712569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2504712569
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.3920864756
Short name T726
Test name
Test status
Simulation time 34961035 ps
CPU time 1.61 seconds
Started Jun 10 06:34:45 PM PDT 24
Finished Jun 10 06:34:47 PM PDT 24
Peak memory 218096 kb
Host smart-9d346ef9-4289-49ac-a247-e3c91fb69e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920864756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3920864756
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.3795761294
Short name T460
Test name
Test status
Simulation time 75201058 ps
CPU time 1.69 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 219756 kb
Host smart-1afa8a74-0f28-4066-8a95-1338736cbc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795761294 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3795761294
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2809269342
Short name T694
Test name
Test status
Simulation time 41484720 ps
CPU time 1.14 seconds
Started Jun 10 06:33:08 PM PDT 24
Finished Jun 10 06:33:09 PM PDT 24
Peak memory 219596 kb
Host smart-73aaa5fb-2003-437f-bf02-74e05e2224ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809269342 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2809269342
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.704222675
Short name T334
Test name
Test status
Simulation time 151475582 ps
CPU time 1.28 seconds
Started Jun 10 06:33:13 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 214908 kb
Host smart-fc1dd58e-1db9-494c-a20a-8d87d289697f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704222675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.704222675
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.3831650711
Short name T628
Test name
Test status
Simulation time 40187259 ps
CPU time 1.21 seconds
Started Jun 10 06:33:05 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 218148 kb
Host smart-f34d028c-69b9-4eb1-9e9f-0e3aac98ce0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831650711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.3831650711
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_genbits.3852073455
Short name T416
Test name
Test status
Simulation time 60852358 ps
CPU time 1.26 seconds
Started Jun 10 06:33:03 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 219564 kb
Host smart-28dbd44a-140f-465d-aa7f-5f02c4cf895c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852073455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3852073455
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.884184169
Short name T727
Test name
Test status
Simulation time 28091387 ps
CPU time 0.95 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:33:08 PM PDT 24
Peak memory 215132 kb
Host smart-d140ddc5-e764-4c85-8d7b-61309f803dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884184169 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.884184169
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1675161447
Short name T291
Test name
Test status
Simulation time 175459832 ps
CPU time 3.7 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 216604 kb
Host smart-71c01d7b-7006-41a9-a0ef-5773370c56f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675161447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1675161447
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2369910275
Short name T646
Test name
Test status
Simulation time 156121318532 ps
CPU time 982.69 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:49:31 PM PDT 24
Peak memory 222180 kb
Host smart-0bf5b6bf-695e-4fdd-a52c-90970e62b59d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369910275 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2369910275
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2900033684
Short name T724
Test name
Test status
Simulation time 30686668 ps
CPU time 1.3 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218048 kb
Host smart-60f2d563-de23-42f9-882a-d85c0432d9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900033684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2900033684
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1250562136
Short name T763
Test name
Test status
Simulation time 43928510 ps
CPU time 1.45 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:47 PM PDT 24
Peak memory 218024 kb
Host smart-a3248540-cf1e-4581-b0e4-2fe9b9426504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250562136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1250562136
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2877856102
Short name T324
Test name
Test status
Simulation time 52238647 ps
CPU time 1.19 seconds
Started Jun 10 06:34:45 PM PDT 24
Finished Jun 10 06:34:46 PM PDT 24
Peak memory 216940 kb
Host smart-94e6e0b6-043b-401a-aeed-f2e65faa6659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877856102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2877856102
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.635621041
Short name T402
Test name
Test status
Simulation time 52723847 ps
CPU time 1.61 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 218300 kb
Host smart-ea413e5d-336d-4924-8df5-d88d81cd29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635621041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.635621041
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.872808561
Short name T475
Test name
Test status
Simulation time 52000318 ps
CPU time 1.65 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218264 kb
Host smart-5afca7f8-937b-482d-9374-cd020e906d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872808561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.872808561
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2252541064
Short name T461
Test name
Test status
Simulation time 55419368 ps
CPU time 1.21 seconds
Started Jun 10 06:34:47 PM PDT 24
Finished Jun 10 06:34:49 PM PDT 24
Peak memory 217996 kb
Host smart-256d89f4-ee0b-4db8-92bd-8486e79e2f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252541064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2252541064
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1376168071
Short name T549
Test name
Test status
Simulation time 111652841 ps
CPU time 1.49 seconds
Started Jun 10 06:34:45 PM PDT 24
Finished Jun 10 06:34:47 PM PDT 24
Peak memory 218000 kb
Host smart-627741f2-a9db-4ee7-8716-56aabd9faeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376168071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1376168071
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1549299451
Short name T565
Test name
Test status
Simulation time 57777198 ps
CPU time 1.44 seconds
Started Jun 10 06:34:46 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 218152 kb
Host smart-3d49213a-92eb-469b-9ad9-bca2be38caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549299451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1549299451
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2008960595
Short name T314
Test name
Test status
Simulation time 46991364 ps
CPU time 0.97 seconds
Started Jun 10 06:34:49 PM PDT 24
Finished Jun 10 06:34:50 PM PDT 24
Peak memory 216808 kb
Host smart-2d2bfca0-f1e8-4a97-b34c-06484fe5ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008960595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2008960595
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.4230796998
Short name T761
Test name
Test status
Simulation time 48583525 ps
CPU time 0.99 seconds
Started Jun 10 06:33:12 PM PDT 24
Finished Jun 10 06:33:13 PM PDT 24
Peak memory 215072 kb
Host smart-dc6e876a-b1b5-49a4-939e-67894db857e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230796998 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.4230796998
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3612540603
Short name T617
Test name
Test status
Simulation time 152151339 ps
CPU time 0.85 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 216272 kb
Host smart-c11f98fe-5a9a-4fe4-a29d-7453c79fed87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612540603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3612540603
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1805638936
Short name T722
Test name
Test status
Simulation time 47987999 ps
CPU time 1.51 seconds
Started Jun 10 06:33:12 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 216720 kb
Host smart-7b59cdf4-c66e-4020-8828-3f96b43053eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805638936 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1805638936
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_genbits.1605305127
Short name T411
Test name
Test status
Simulation time 41980832 ps
CPU time 1.45 seconds
Started Jun 10 06:33:05 PM PDT 24
Finished Jun 10 06:33:07 PM PDT 24
Peak memory 218352 kb
Host smart-4284877b-e283-4960-b164-e8959e547195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605305127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1605305127
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.1054999701
Short name T425
Test name
Test status
Simulation time 47515792 ps
CPU time 0.9 seconds
Started Jun 10 06:33:13 PM PDT 24
Finished Jun 10 06:33:14 PM PDT 24
Peak memory 215200 kb
Host smart-cb4775d6-32d1-4e45-8acd-78ef536e63d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054999701 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1054999701
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1775381031
Short name T349
Test name
Test status
Simulation time 318142289 ps
CPU time 2.23 seconds
Started Jun 10 06:33:07 PM PDT 24
Finished Jun 10 06:33:10 PM PDT 24
Peak memory 215312 kb
Host smart-4ebff30c-de13-404e-9411-d8eb353066f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775381031 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1775381031
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3438469556
Short name T214
Test name
Test status
Simulation time 434100726106 ps
CPU time 2977.92 seconds
Started Jun 10 06:33:05 PM PDT 24
Finished Jun 10 07:22:44 PM PDT 24
Peak memory 233968 kb
Host smart-5b4910f3-bdd1-4662-88a1-18fbc8420a84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438469556 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3438469556
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2021335509
Short name T725
Test name
Test status
Simulation time 206190658 ps
CPU time 2.86 seconds
Started Jun 10 06:34:48 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 218204 kb
Host smart-4f8a17f8-c833-421f-a368-e0b91928b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021335509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2021335509
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1074944098
Short name T709
Test name
Test status
Simulation time 57185472 ps
CPU time 1.31 seconds
Started Jun 10 06:34:47 PM PDT 24
Finished Jun 10 06:34:48 PM PDT 24
Peak memory 218248 kb
Host smart-682f6368-b116-48e1-983b-0ded1e167f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074944098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1074944098
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4251593460
Short name T620
Test name
Test status
Simulation time 41598351 ps
CPU time 1.67 seconds
Started Jun 10 06:34:52 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 218008 kb
Host smart-33072943-2ebc-4b6d-9f59-5284706ecf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251593460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4251593460
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3083602805
Short name T419
Test name
Test status
Simulation time 61269585 ps
CPU time 1.41 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 219868 kb
Host smart-ae36c0f3-523c-4c82-8432-4b5827134dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083602805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3083602805
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.2382612213
Short name T749
Test name
Test status
Simulation time 33994111 ps
CPU time 1.1 seconds
Started Jun 10 06:34:57 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 219552 kb
Host smart-11fece0e-fe5c-43cc-928c-2a4848a3ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382612213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2382612213
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2319240464
Short name T403
Test name
Test status
Simulation time 52728680 ps
CPU time 1.92 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:58 PM PDT 24
Peak memory 218296 kb
Host smart-49bef6e5-14d1-467e-b680-b8b489449c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319240464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2319240464
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3778585453
Short name T351
Test name
Test status
Simulation time 376977646 ps
CPU time 1.45 seconds
Started Jun 10 06:34:52 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 219744 kb
Host smart-8b09b14f-6d37-4a5e-b289-123c22ad683e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778585453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3778585453
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2670350972
Short name T397
Test name
Test status
Simulation time 54142551 ps
CPU time 1.56 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 218076 kb
Host smart-3313d8bd-809f-463e-8695-2c37f73df554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670350972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2670350972
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.320340889
Short name T571
Test name
Test status
Simulation time 38492163 ps
CPU time 1.41 seconds
Started Jun 10 06:34:48 PM PDT 24
Finished Jun 10 06:34:50 PM PDT 24
Peak memory 218276 kb
Host smart-0985b606-49aa-4528-8901-f824fe0460cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320340889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.320340889
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert_test.3569416285
Short name T400
Test name
Test status
Simulation time 53819212 ps
CPU time 0.98 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 214760 kb
Host smart-0bb87d97-370f-428c-9740-4996da3963ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569416285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3569416285
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3341179812
Short name T193
Test name
Test status
Simulation time 82353798 ps
CPU time 0.82 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 216312 kb
Host smart-ac1d7747-c373-45cc-926c-91690cffa615
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341179812 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3341179812
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2341929567
Short name T823
Test name
Test status
Simulation time 61556727 ps
CPU time 1.02 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 218180 kb
Host smart-f2485d00-84b3-492c-8b63-d6f6a34bb849
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341929567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2341929567
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1070390270
Short name T155
Test name
Test status
Simulation time 23508010 ps
CPU time 0.98 seconds
Started Jun 10 06:33:11 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 218524 kb
Host smart-ea878617-18e7-456c-8cc8-ffa363c471c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070390270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1070390270
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.1544440534
Short name T339
Test name
Test status
Simulation time 31215610 ps
CPU time 1.28 seconds
Started Jun 10 06:33:09 PM PDT 24
Finished Jun 10 06:33:10 PM PDT 24
Peak memory 218136 kb
Host smart-fc7d5a57-f417-46fa-9369-9c271ee88f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544440534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1544440534
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3467442263
Short name T108
Test name
Test status
Simulation time 21014719 ps
CPU time 1.12 seconds
Started Jun 10 06:33:11 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 215868 kb
Host smart-99429c79-81d7-4b9a-a268-fc5686f8c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467442263 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3467442263
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4002647760
Short name T765
Test name
Test status
Simulation time 55414968 ps
CPU time 0.98 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 215216 kb
Host smart-8ed50ac9-7b9a-4ff6-b3db-1124988e8a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002647760 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4002647760
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.4093181104
Short name T232
Test name
Test status
Simulation time 356368622 ps
CPU time 1.66 seconds
Started Jun 10 06:33:09 PM PDT 24
Finished Jun 10 06:33:11 PM PDT 24
Peak memory 216748 kb
Host smart-7344473d-ae91-47c9-9c2e-a024bcf6baa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093181104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.4093181104
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1326508957
Short name T212
Test name
Test status
Simulation time 71719798828 ps
CPU time 1049.29 seconds
Started Jun 10 06:33:11 PM PDT 24
Finished Jun 10 06:50:41 PM PDT 24
Peak memory 220576 kb
Host smart-d3858a05-35c9-4500-8024-a8a79d110a8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326508957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1326508957
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1653199109
Short name T24
Test name
Test status
Simulation time 50277307 ps
CPU time 1.26 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 217128 kb
Host smart-0d34ae61-e38c-41ea-a6b2-5f38b67f992d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653199109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1653199109
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3199389580
Short name T770
Test name
Test status
Simulation time 47890324 ps
CPU time 1.54 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:55 PM PDT 24
Peak memory 216824 kb
Host smart-9a775f57-0f04-4abd-94bb-c881c04ce5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199389580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3199389580
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3813525347
Short name T354
Test name
Test status
Simulation time 30865980 ps
CPU time 1.34 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218144 kb
Host smart-747a589d-f5e6-4cd4-b676-4433608f1a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813525347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3813525347
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1834649940
Short name T311
Test name
Test status
Simulation time 118558891 ps
CPU time 1.72 seconds
Started Jun 10 06:34:56 PM PDT 24
Finished Jun 10 06:34:58 PM PDT 24
Peak memory 218536 kb
Host smart-b9913f7e-3726-4983-a654-b181692ce0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834649940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1834649940
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.383624447
Short name T87
Test name
Test status
Simulation time 71483827 ps
CPU time 1.59 seconds
Started Jun 10 06:34:50 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 219724 kb
Host smart-d1a9708a-5348-4f69-aa90-1899a197473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383624447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.383624447
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2196020735
Short name T295
Test name
Test status
Simulation time 165035906 ps
CPU time 2.69 seconds
Started Jun 10 06:34:49 PM PDT 24
Finished Jun 10 06:34:52 PM PDT 24
Peak memory 219636 kb
Host smart-a3faed67-d74a-4f91-a0fb-43e3837ecc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196020735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2196020735
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.593472261
Short name T390
Test name
Test status
Simulation time 44505388 ps
CPU time 1.78 seconds
Started Jun 10 06:34:49 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 218316 kb
Host smart-ca48dae3-9244-4568-afd5-ede0c9f400ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593472261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.593472261
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.4167475848
Short name T581
Test name
Test status
Simulation time 219224225 ps
CPU time 1.17 seconds
Started Jun 10 06:34:51 PM PDT 24
Finished Jun 10 06:34:53 PM PDT 24
Peak memory 216964 kb
Host smart-864fa224-50e5-4f3c-8c12-7889c1d0ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167475848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.4167475848
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1618391277
Short name T622
Test name
Test status
Simulation time 88077183 ps
CPU time 1.13 seconds
Started Jun 10 06:34:57 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 218084 kb
Host smart-ee578223-05b5-4f9f-9af4-3e309a205050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618391277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1618391277
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4206710631
Short name T226
Test name
Test status
Simulation time 92311761 ps
CPU time 1.14 seconds
Started Jun 10 06:34:47 PM PDT 24
Finished Jun 10 06:34:49 PM PDT 24
Peak memory 219588 kb
Host smart-c34d8b20-0b8c-4ea8-af33-d3d6fa6f4d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206710631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4206710631
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3076040121
Short name T179
Test name
Test status
Simulation time 26400534 ps
CPU time 1.19 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 218252 kb
Host smart-8277670c-9a4c-49c2-8303-501c355d274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076040121 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3076040121
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3452264670
Short name T772
Test name
Test status
Simulation time 55557831 ps
CPU time 0.9 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 214724 kb
Host smart-849040ad-1bdb-4916-8559-6c17009456c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452264670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3452264670
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.103936456
Short name T333
Test name
Test status
Simulation time 12095925 ps
CPU time 0.9 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 216060 kb
Host smart-85986d34-b035-4d1b-8749-876aae793ffb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103936456 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.103936456
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.2154628221
Short name T454
Test name
Test status
Simulation time 30335234 ps
CPU time 1.1 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 220540 kb
Host smart-71ab56e2-39f7-4f91-8c4c-02b83cc4b3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154628221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2154628221
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1472323822
Short name T754
Test name
Test status
Simulation time 75000437 ps
CPU time 1.7 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 218356 kb
Host smart-5a74ebc8-4c1b-4b61-a2fe-1fd3e5e21ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472323822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1472323822
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.722930337
Short name T362
Test name
Test status
Simulation time 89165873 ps
CPU time 0.86 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 215200 kb
Host smart-3d0f1329-1dd8-48a3-bae9-23db572807e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722930337 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.722930337
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2441182722
Short name T638
Test name
Test status
Simulation time 16463318 ps
CPU time 0.99 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:12 PM PDT 24
Peak memory 215196 kb
Host smart-2cdd492b-d9ce-40ab-9ffc-7e2734180779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441182722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2441182722
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3447470989
Short name T644
Test name
Test status
Simulation time 196961238 ps
CPU time 4.15 seconds
Started Jun 10 06:33:10 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 215196 kb
Host smart-93bf0a4c-3652-47c7-b5b9-c394f386eb54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447470989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3447470989
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.377083890
Short name T613
Test name
Test status
Simulation time 102365720520 ps
CPU time 1308.51 seconds
Started Jun 10 06:33:11 PM PDT 24
Finished Jun 10 06:55:00 PM PDT 24
Peak memory 225256 kb
Host smart-6d690e82-2ff9-4b32-bbd8-0ca9a9417e53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377083890 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.377083890
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.edn_genbits.1117981018
Short name T458
Test name
Test status
Simulation time 61642914 ps
CPU time 1.69 seconds
Started Jun 10 06:34:50 PM PDT 24
Finished Jun 10 06:34:52 PM PDT 24
Peak memory 218284 kb
Host smart-21cdeb02-251e-4415-a88b-f1e497a4a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117981018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1117981018
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.727861564
Short name T388
Test name
Test status
Simulation time 49421915 ps
CPU time 1.2 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 216872 kb
Host smart-59aeeaf8-137c-4fce-9931-a95523db8e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727861564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.727861564
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2432634346
Short name T657
Test name
Test status
Simulation time 294292496 ps
CPU time 4.03 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 217296 kb
Host smart-07ae2f95-332d-4f37-a332-83336899a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432634346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2432634346
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.922635644
Short name T367
Test name
Test status
Simulation time 107449348 ps
CPU time 1.21 seconds
Started Jun 10 06:34:49 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 219448 kb
Host smart-dfb56e7a-fae3-4fb4-a6ce-59405cb5d998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922635644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.922635644
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.773237504
Short name T10
Test name
Test status
Simulation time 69821658 ps
CPU time 2.14 seconds
Started Jun 10 06:34:51 PM PDT 24
Finished Jun 10 06:34:53 PM PDT 24
Peak memory 218884 kb
Host smart-e2c20ec1-8b1d-4999-b64c-5d0c381f461d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773237504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.773237504
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1335419871
Short name T436
Test name
Test status
Simulation time 52559305 ps
CPU time 1.81 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 217972 kb
Host smart-ce75b18d-ecd7-469b-ac04-c9ab062c98b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335419871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1335419871
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.4173456634
Short name T639
Test name
Test status
Simulation time 145447602 ps
CPU time 3.27 seconds
Started Jun 10 06:34:48 PM PDT 24
Finished Jun 10 06:34:51 PM PDT 24
Peak memory 219924 kb
Host smart-88942cb5-488c-4af6-af59-4afec6347f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173456634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.4173456634
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3620318109
Short name T317
Test name
Test status
Simulation time 134366907 ps
CPU time 1.14 seconds
Started Jun 10 06:34:57 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 216820 kb
Host smart-4f448d0e-90d8-4057-9743-365075afa3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620318109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3620318109
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_disable.3927577240
Short name T732
Test name
Test status
Simulation time 31483939 ps
CPU time 0.83 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 215868 kb
Host smart-dde330aa-1e0f-4fd6-8668-01782c6668b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927577240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.3927577240
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.697232834
Short name T143
Test name
Test status
Simulation time 57260850 ps
CPU time 1.09 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:18 PM PDT 24
Peak memory 216752 kb
Host smart-f489b9ac-f6b8-4709-8099-da5c0a139c83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697232834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.697232834
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.854500471
Short name T382
Test name
Test status
Simulation time 34360532 ps
CPU time 0.99 seconds
Started Jun 10 06:33:15 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 223820 kb
Host smart-0ec0cbb5-2a40-4237-8fe8-79fe382a377e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854500471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.854500471
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1565986207
Short name T796
Test name
Test status
Simulation time 153346403 ps
CPU time 1.26 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:15 PM PDT 24
Peak memory 216948 kb
Host smart-3cac1b98-3e38-4591-ad41-237c39f7fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565986207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1565986207
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.3812907750
Short name T432
Test name
Test status
Simulation time 40282461 ps
CPU time 0.95 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 215220 kb
Host smart-05db9894-877b-4153-ba68-435c8956c0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812907750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3812907750
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4222837903
Short name T352
Test name
Test status
Simulation time 855028378 ps
CPU time 4.97 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:33:20 PM PDT 24
Peak memory 215208 kb
Host smart-54e0627a-fec6-44d6-af22-66101324971a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222837903 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4222837903
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3610024126
Short name T786
Test name
Test status
Simulation time 92686229754 ps
CPU time 599.88 seconds
Started Jun 10 06:33:14 PM PDT 24
Finished Jun 10 06:43:14 PM PDT 24
Peak memory 221168 kb
Host smart-e1298ff1-1f2a-4d5a-928c-f9e79fe29791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610024126 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3610024126
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.485932850
Short name T408
Test name
Test status
Simulation time 74397369 ps
CPU time 1.44 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218548 kb
Host smart-687f6eb3-8087-4953-af63-e474e4e599e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485932850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.485932850
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1491975624
Short name T566
Test name
Test status
Simulation time 29689634 ps
CPU time 1.37 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 218148 kb
Host smart-19edf127-aa9a-4207-b70e-42c9425e3dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491975624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1491975624
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.147116217
Short name T616
Test name
Test status
Simulation time 77303327 ps
CPU time 1.15 seconds
Started Jun 10 06:34:56 PM PDT 24
Finished Jun 10 06:34:58 PM PDT 24
Peak memory 219452 kb
Host smart-5095509f-0fa0-42cf-8966-ab4cba592896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147116217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.147116217
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.573608913
Short name T579
Test name
Test status
Simulation time 199943461 ps
CPU time 1.17 seconds
Started Jun 10 06:34:56 PM PDT 24
Finished Jun 10 06:34:57 PM PDT 24
Peak memory 217292 kb
Host smart-a218ce05-cf13-4dc9-8abe-430604438adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573608913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.573608913
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.319263899
Short name T805
Test name
Test status
Simulation time 71969884 ps
CPU time 1.66 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 218032 kb
Host smart-28ffb372-93ba-483b-b002-c0ed7ea344d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319263899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.319263899
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3205615252
Short name T557
Test name
Test status
Simulation time 122560514 ps
CPU time 1.04 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 216968 kb
Host smart-e771d09e-bd54-416f-953d-ece27147011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205615252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3205615252
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3387109003
Short name T468
Test name
Test status
Simulation time 42625355 ps
CPU time 1.49 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218156 kb
Host smart-19b43923-7cf5-4aa2-b073-2884baaeee66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387109003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3387109003
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1847595992
Short name T71
Test name
Test status
Simulation time 47826458 ps
CPU time 1.51 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 218404 kb
Host smart-77f69141-6f6e-4297-af54-c660e3ec8400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847595992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1847595992
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.205276013
Short name T718
Test name
Test status
Simulation time 170623017 ps
CPU time 1.36 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 217204 kb
Host smart-f0c77346-09bd-459c-9379-e1b8d51fc108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205276013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.205276013
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1522317563
Short name T111
Test name
Test status
Simulation time 98567707 ps
CPU time 1.26 seconds
Started Jun 10 06:33:19 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 218768 kb
Host smart-eb6143ff-95e8-42ec-aa27-06f66699950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522317563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1522317563
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.190032722
Short name T747
Test name
Test status
Simulation time 26414995 ps
CPU time 0.99 seconds
Started Jun 10 06:33:18 PM PDT 24
Finished Jun 10 06:33:19 PM PDT 24
Peak memory 214768 kb
Host smart-9f0537de-fc18-477a-a7d1-ba95de8c606e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190032722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.190032722
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.1620062800
Short name T780
Test name
Test status
Simulation time 24738212 ps
CPU time 0.97 seconds
Started Jun 10 06:33:18 PM PDT 24
Finished Jun 10 06:33:19 PM PDT 24
Peak memory 218548 kb
Host smart-e3779972-4034-4bc9-81ae-7cf3d8ed4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620062800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1620062800
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3300332193
Short name T583
Test name
Test status
Simulation time 58833154 ps
CPU time 1.32 seconds
Started Jun 10 06:33:17 PM PDT 24
Finished Jun 10 06:33:18 PM PDT 24
Peak memory 216884 kb
Host smart-51aa4abe-e811-4d2a-85ae-160661e34f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300332193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3300332193
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.1772802458
Short name T612
Test name
Test status
Simulation time 44184877 ps
CPU time 1.17 seconds
Started Jun 10 06:33:18 PM PDT 24
Finished Jun 10 06:33:20 PM PDT 24
Peak memory 225264 kb
Host smart-811ef41e-15e7-432a-9546-838f10a271b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772802458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1772802458
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2170855270
Short name T357
Test name
Test status
Simulation time 16963898 ps
CPU time 0.99 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:17 PM PDT 24
Peak memory 215204 kb
Host smart-32495eda-6e5e-4e26-a2ee-19ba07aa650d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170855270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2170855270
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3571909430
Short name T228
Test name
Test status
Simulation time 509530638 ps
CPU time 5.57 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:22 PM PDT 24
Peak memory 215228 kb
Host smart-2d5b2abf-d05c-4a83-accc-cac709d36b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571909430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3571909430
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2246476326
Short name T729
Test name
Test status
Simulation time 110597452264 ps
CPU time 1392.09 seconds
Started Jun 10 06:33:17 PM PDT 24
Finished Jun 10 06:56:30 PM PDT 24
Peak memory 225840 kb
Host smart-b0ca6f20-5b39-48e5-9e8b-8a7f03bf4605
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246476326 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2246476326
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.edn_genbits.3962531791
Short name T820
Test name
Test status
Simulation time 68777972 ps
CPU time 1.17 seconds
Started Jun 10 06:34:55 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 216996 kb
Host smart-37ea3e97-34c9-48bf-a8a8-4ce9853ba52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962531791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3962531791
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1684357838
Short name T671
Test name
Test status
Simulation time 36103376 ps
CPU time 1.12 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:55 PM PDT 24
Peak memory 218212 kb
Host smart-13a63d95-dab9-4bfa-a27b-26d3f9bd3aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684357838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1684357838
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3290718881
Short name T526
Test name
Test status
Simulation time 49079317 ps
CPU time 1.82 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:57 PM PDT 24
Peak memory 218128 kb
Host smart-77998f1d-64d3-4e3e-a82f-3ccec737f981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290718881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3290718881
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3990362580
Short name T737
Test name
Test status
Simulation time 85380752 ps
CPU time 1.28 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 218372 kb
Host smart-5ad0927d-236a-43dc-be7e-31a2e894e423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990362580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3990362580
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3007544622
Short name T543
Test name
Test status
Simulation time 82240818 ps
CPU time 1.44 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:56 PM PDT 24
Peak memory 218344 kb
Host smart-4157f204-1c1a-4544-9951-cf291c0260bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007544622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3007544622
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3597338465
Short name T746
Test name
Test status
Simulation time 59553962 ps
CPU time 1.22 seconds
Started Jun 10 06:34:52 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 218432 kb
Host smart-4997ec87-ace4-42d9-9c7d-22ab75794910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597338465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3597338465
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1394021885
Short name T841
Test name
Test status
Simulation time 36183713 ps
CPU time 1.41 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:55 PM PDT 24
Peak memory 216932 kb
Host smart-9c1f4ed3-fffe-48ea-b567-39733f7425b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394021885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1394021885
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1140927263
Short name T667
Test name
Test status
Simulation time 108731861 ps
CPU time 1.67 seconds
Started Jun 10 06:34:54 PM PDT 24
Finished Jun 10 06:34:57 PM PDT 24
Peak memory 218700 kb
Host smart-3d2e5783-e115-4dd6-8b98-fe2741dff312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140927263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1140927263
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3080055129
Short name T504
Test name
Test status
Simulation time 51166487 ps
CPU time 1.6 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 218320 kb
Host smart-38f01392-ad9d-4598-aec8-07deb899018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080055129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3080055129
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.1976724497
Short name T662
Test name
Test status
Simulation time 26973616 ps
CPU time 0.91 seconds
Started Jun 10 06:32:13 PM PDT 24
Finished Jun 10 06:32:14 PM PDT 24
Peak memory 214744 kb
Host smart-496d854b-74f6-4ace-8753-f48e660d9044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976724497 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1976724497
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_err.2404381717
Short name T52
Test name
Test status
Simulation time 29198461 ps
CPU time 1.33 seconds
Started Jun 10 06:32:08 PM PDT 24
Finished Jun 10 06:32:09 PM PDT 24
Peak memory 225048 kb
Host smart-693bbd0d-56dd-4805-a313-793cab3ac917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404381717 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2404381717
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1504202145
Short name T441
Test name
Test status
Simulation time 49967473 ps
CPU time 1.06 seconds
Started Jun 10 06:32:03 PM PDT 24
Finished Jun 10 06:32:05 PM PDT 24
Peak memory 219460 kb
Host smart-2ed4281b-f1fd-4aec-9e94-99d5896e343f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504202145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1504202145
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2872581373
Short name T752
Test name
Test status
Simulation time 37099226 ps
CPU time 0.85 seconds
Started Jun 10 06:32:09 PM PDT 24
Finished Jun 10 06:32:10 PM PDT 24
Peak memory 215532 kb
Host smart-f8b3fb33-7f26-40b1-81a1-c378e485f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872581373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2872581373
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1707602578
Short name T283
Test name
Test status
Simulation time 16370107 ps
CPU time 0.94 seconds
Started Jun 10 06:32:05 PM PDT 24
Finished Jun 10 06:32:07 PM PDT 24
Peak memory 206992 kb
Host smart-574834f5-40f1-46e1-a359-5f3696370e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707602578 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1707602578
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_smoke.2716888909
Short name T789
Test name
Test status
Simulation time 27539193 ps
CPU time 0.96 seconds
Started Jun 10 06:32:00 PM PDT 24
Finished Jun 10 06:32:01 PM PDT 24
Peak memory 215212 kb
Host smart-4b1f54df-ac3e-4a7d-b8aa-e00718bd5196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716888909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2716888909
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1994890981
Short name T804
Test name
Test status
Simulation time 418771426 ps
CPU time 4.25 seconds
Started Jun 10 06:32:02 PM PDT 24
Finished Jun 10 06:32:07 PM PDT 24
Peak memory 219668 kb
Host smart-330fabd4-47af-4a32-b011-354a55008d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994890981 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1994890981
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.890616401
Short name T225
Test name
Test status
Simulation time 109225800343 ps
CPU time 1243.83 seconds
Started Jun 10 06:32:09 PM PDT 24
Finished Jun 10 06:52:53 PM PDT 24
Peak memory 222696 kb
Host smart-73ed518d-b484-4e75-9bbb-5fce05cf602d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890616401 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.890616401
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.4262345957
Short name T320
Test name
Test status
Simulation time 55601031 ps
CPU time 0.86 seconds
Started Jun 10 06:33:20 PM PDT 24
Finished Jun 10 06:33:22 PM PDT 24
Peak memory 214936 kb
Host smart-21d47de6-9644-4d35-85f3-3523fb364217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262345957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4262345957
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.1586762401
Short name T136
Test name
Test status
Simulation time 23592997 ps
CPU time 0.96 seconds
Started Jun 10 06:33:20 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 218524 kb
Host smart-b53baabd-d3d8-4908-9265-66a23bc78b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586762401 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1586762401
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2168961371
Short name T785
Test name
Test status
Simulation time 40158259 ps
CPU time 1.56 seconds
Started Jun 10 06:33:19 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 217048 kb
Host smart-db52c2dc-430e-4221-b6c4-a8678a6f0ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168961371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2168961371
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1999867950
Short name T735
Test name
Test status
Simulation time 21787174 ps
CPU time 1.06 seconds
Started Jun 10 06:33:20 PM PDT 24
Finished Jun 10 06:33:21 PM PDT 24
Peak memory 215864 kb
Host smart-acd78d86-2ab0-4fdc-9f3b-d4ce7a3cc3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999867950 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1999867950
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.455305811
Short name T330
Test name
Test status
Simulation time 25037519 ps
CPU time 0.91 seconds
Started Jun 10 06:33:18 PM PDT 24
Finished Jun 10 06:33:19 PM PDT 24
Peak memory 215204 kb
Host smart-aeb9513f-0c2d-4773-8f97-7b4f37fc0c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455305811 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.455305811
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3104006947
Short name T479
Test name
Test status
Simulation time 39213398 ps
CPU time 1.4 seconds
Started Jun 10 06:33:16 PM PDT 24
Finished Jun 10 06:33:18 PM PDT 24
Peak memory 216836 kb
Host smart-0811ec25-00b5-4c4b-a085-1f3044cd97e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104006947 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3104006947
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.221406569
Short name T217
Test name
Test status
Simulation time 116456648965 ps
CPU time 1356.99 seconds
Started Jun 10 06:33:18 PM PDT 24
Finished Jun 10 06:55:55 PM PDT 24
Peak memory 222048 kb
Host smart-7231e12e-3e86-45f8-8ac4-e06d4bae7a7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221406569 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.221406569
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2961531275
Short name T44
Test name
Test status
Simulation time 74826064 ps
CPU time 1.39 seconds
Started Jun 10 06:34:56 PM PDT 24
Finished Jun 10 06:34:57 PM PDT 24
Peak memory 218440 kb
Host smart-71ab4d5d-095c-422a-bc82-efff4cb9c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961531275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2961531275
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2591607396
Short name T512
Test name
Test status
Simulation time 69526082 ps
CPU time 1.43 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 219680 kb
Host smart-de8f2ce2-197c-41bb-8264-77b83967ee67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591607396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2591607396
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3929847078
Short name T340
Test name
Test status
Simulation time 283823087 ps
CPU time 1.79 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:02 PM PDT 24
Peak memory 218616 kb
Host smart-8974425b-c336-47e4-8c5f-af9a432437d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929847078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3929847078
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3311344982
Short name T659
Test name
Test status
Simulation time 52717973 ps
CPU time 1.45 seconds
Started Jun 10 06:34:53 PM PDT 24
Finished Jun 10 06:34:54 PM PDT 24
Peak memory 216788 kb
Host smart-fee48e99-a375-4aee-8214-effe44d1a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311344982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3311344982
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3404664104
Short name T372
Test name
Test status
Simulation time 89819130 ps
CPU time 1.21 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 216988 kb
Host smart-6491d982-f3bf-4a38-87a4-f9ab7cd1f7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404664104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3404664104
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3446383694
Short name T327
Test name
Test status
Simulation time 43818838 ps
CPU time 1.51 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218064 kb
Host smart-53597333-0c2a-4289-a463-6c3663c922eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446383694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3446383694
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1669059916
Short name T292
Test name
Test status
Simulation time 25324811 ps
CPU time 1.25 seconds
Started Jun 10 06:35:02 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 218200 kb
Host smart-8734e7ea-1200-41c0-8f93-89b38adfbb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669059916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1669059916
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3383578886
Short name T800
Test name
Test status
Simulation time 77248515 ps
CPU time 1.83 seconds
Started Jun 10 06:35:05 PM PDT 24
Finished Jun 10 06:35:07 PM PDT 24
Peak memory 219716 kb
Host smart-3c6ab3a4-7fcd-458e-8dc5-af23f3d67580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383578886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3383578886
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2519980660
Short name T803
Test name
Test status
Simulation time 93413732 ps
CPU time 1.52 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:05 PM PDT 24
Peak memory 218524 kb
Host smart-b3cedeaf-5ec2-471c-a279-271996746a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519980660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2519980660
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.243839608
Short name T134
Test name
Test status
Simulation time 62739606 ps
CPU time 1.34 seconds
Started Jun 10 06:33:22 PM PDT 24
Finished Jun 10 06:33:24 PM PDT 24
Peak memory 215700 kb
Host smart-1b7b2a69-c96e-4902-aa1c-1738ef0fcd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243839608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.243839608
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2145187151
Short name T437
Test name
Test status
Simulation time 54979132 ps
CPU time 1.04 seconds
Started Jun 10 06:33:22 PM PDT 24
Finished Jun 10 06:33:23 PM PDT 24
Peak memory 214804 kb
Host smart-2b574cec-4bf6-4b9e-a544-fb5f6a549074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145187151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2145187151
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2877397023
Short name T77
Test name
Test status
Simulation time 32811170 ps
CPU time 0.89 seconds
Started Jun 10 06:33:24 PM PDT 24
Finished Jun 10 06:33:26 PM PDT 24
Peak memory 215340 kb
Host smart-32802311-a41e-4599-96ec-3b08e50d1cca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877397023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2877397023
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2850722441
Short name T705
Test name
Test status
Simulation time 84872061 ps
CPU time 1.1 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 216696 kb
Host smart-ce5c8275-0a22-4026-8f09-e71df8b48124
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850722441 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2850722441
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4100861179
Short name T171
Test name
Test status
Simulation time 32854117 ps
CPU time 0.92 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 218264 kb
Host smart-8a8fe24a-c1f2-404c-ae2f-dc3f575a53ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100861179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4100861179
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2756619508
Short name T642
Test name
Test status
Simulation time 119618500 ps
CPU time 1.21 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 216868 kb
Host smart-aa48cb31-12f0-49b6-98c7-aef341c8203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756619508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2756619508
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.653877739
Short name T55
Test name
Test status
Simulation time 31177148 ps
CPU time 0.99 seconds
Started Jun 10 06:33:23 PM PDT 24
Finished Jun 10 06:33:24 PM PDT 24
Peak memory 223840 kb
Host smart-7ca8d3e9-1469-4c24-ade7-9432a76386d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653877739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.653877739
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2638847356
Short name T810
Test name
Test status
Simulation time 16951801 ps
CPU time 0.99 seconds
Started Jun 10 06:33:24 PM PDT 24
Finished Jun 10 06:33:25 PM PDT 24
Peak memory 215212 kb
Host smart-9dc1b3fa-2113-4924-9e6a-ade6a323aafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638847356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2638847356
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.508254422
Short name T710
Test name
Test status
Simulation time 330491403 ps
CPU time 1.78 seconds
Started Jun 10 06:33:23 PM PDT 24
Finished Jun 10 06:33:25 PM PDT 24
Peak memory 217108 kb
Host smart-26cb9350-98bc-4303-869d-5a3b56c7d1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508254422 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.508254422
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1169992559
Short name T689
Test name
Test status
Simulation time 37630218513 ps
CPU time 850.78 seconds
Started Jun 10 06:33:25 PM PDT 24
Finished Jun 10 06:47:36 PM PDT 24
Peak memory 217056 kb
Host smart-c6890307-8332-4712-a4ed-16b8f99e0fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169992559 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1169992559
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.885734986
Short name T13
Test name
Test status
Simulation time 78178100 ps
CPU time 1.22 seconds
Started Jun 10 06:35:02 PM PDT 24
Finished Jun 10 06:35:03 PM PDT 24
Peak memory 219604 kb
Host smart-3a70c7ed-f44d-4ab5-8681-9a1468e87861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885734986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.885734986
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.1845386125
Short name T289
Test name
Test status
Simulation time 152658670 ps
CPU time 1.14 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 216976 kb
Host smart-9cced697-f5fe-4368-8dd3-d313f247d66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845386125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1845386125
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2479744501
Short name T318
Test name
Test status
Simulation time 41518404 ps
CPU time 1.14 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218212 kb
Host smart-37dc6b80-b9b6-4e3c-a054-7e53e4b0eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479744501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2479744501
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.294985751
Short name T471
Test name
Test status
Simulation time 48512726 ps
CPU time 1.17 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 218420 kb
Host smart-6d285bd1-e890-462b-8fc9-6e3269b043a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294985751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.294985751
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1875525210
Short name T472
Test name
Test status
Simulation time 32299634 ps
CPU time 1.31 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218044 kb
Host smart-e1f90b0f-f10e-4720-89cc-598cc7893e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875525210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1875525210
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1438023718
Short name T9
Test name
Test status
Simulation time 68208234 ps
CPU time 1.2 seconds
Started Jun 10 06:35:07 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 219532 kb
Host smart-d2a59ce9-9de3-42e5-999c-8ee96cf211f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438023718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1438023718
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1445641424
Short name T310
Test name
Test status
Simulation time 92333607 ps
CPU time 1.04 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:34:59 PM PDT 24
Peak memory 216972 kb
Host smart-0ed42593-0441-487f-b3bd-111c69322916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445641424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1445641424
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2510885077
Short name T455
Test name
Test status
Simulation time 40017732 ps
CPU time 1.51 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 216932 kb
Host smart-6f424bef-f2f3-4a9b-b3ed-1bb66b925de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510885077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2510885077
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3289968328
Short name T825
Test name
Test status
Simulation time 70557951 ps
CPU time 1.3 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:10 PM PDT 24
Peak memory 219552 kb
Host smart-1452eeca-d2d8-4de6-8b78-b627593e483d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289968328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3289968328
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2281681359
Short name T153
Test name
Test status
Simulation time 24733762 ps
CPU time 1.18 seconds
Started Jun 10 06:33:25 PM PDT 24
Finished Jun 10 06:33:27 PM PDT 24
Peak memory 220436 kb
Host smart-916d5c62-58d1-4093-a636-af154f9ea1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281681359 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2281681359
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1742916161
Short name T609
Test name
Test status
Simulation time 33497861 ps
CPU time 0.95 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 215080 kb
Host smart-cc8b7a54-0eeb-47d4-ab35-20b1bbb9c001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742916161 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1742916161
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.331406162
Short name T118
Test name
Test status
Simulation time 183287029 ps
CPU time 1.12 seconds
Started Jun 10 06:33:24 PM PDT 24
Finished Jun 10 06:33:25 PM PDT 24
Peak memory 216668 kb
Host smart-599e6614-98de-4f84-8c46-5e92349ddf80
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331406162 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.331406162
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.2980588217
Short name T601
Test name
Test status
Simulation time 27978645 ps
CPU time 1.08 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 219752 kb
Host smart-0aa69cb3-6b14-4bca-bf8f-bed2879ff423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980588217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2980588217
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1516849731
Short name T6
Test name
Test status
Simulation time 48457688 ps
CPU time 1.56 seconds
Started Jun 10 06:33:21 PM PDT 24
Finished Jun 10 06:33:23 PM PDT 24
Peak memory 217960 kb
Host smart-9e05e011-0709-4d12-8573-f9718de9b7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516849731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1516849731
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.3261731045
Short name T96
Test name
Test status
Simulation time 24029666 ps
CPU time 0.92 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 215896 kb
Host smart-a5e0a3c4-7287-4fc2-9670-0af75bfd7dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261731045 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.3261731045
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2858761387
Short name T650
Test name
Test status
Simulation time 109728812 ps
CPU time 0.87 seconds
Started Jun 10 06:33:22 PM PDT 24
Finished Jun 10 06:33:23 PM PDT 24
Peak memory 215204 kb
Host smart-10d3f61a-432f-40fc-b8e9-3207f5441521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858761387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2858761387
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4159332095
Short name T68
Test name
Test status
Simulation time 1241532443 ps
CPU time 4.55 seconds
Started Jun 10 06:33:23 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 216848 kb
Host smart-4cdac1e0-8b23-4f97-b449-33cc30e2aded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159332095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4159332095
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.1254476882
Short name T596
Test name
Test status
Simulation time 59497224 ps
CPU time 2.13 seconds
Started Jun 10 06:35:07 PM PDT 24
Finished Jun 10 06:35:09 PM PDT 24
Peak memory 218100 kb
Host smart-6b479fff-0e9e-4b3c-b0b6-c9b3f02d84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254476882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1254476882
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.4201430562
Short name T348
Test name
Test status
Simulation time 82865527 ps
CPU time 1.35 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 215280 kb
Host smart-fe1d3397-51f9-4d23-9afc-6f829c94791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201430562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.4201430562
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1647654975
Short name T621
Test name
Test status
Simulation time 356030905 ps
CPU time 1.86 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 218672 kb
Host smart-c403cb37-faff-4ba4-9255-6760fc5d06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647654975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1647654975
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3145561349
Short name T742
Test name
Test status
Simulation time 50844675 ps
CPU time 1.4 seconds
Started Jun 10 06:35:04 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 218152 kb
Host smart-6618328a-b869-4986-8e89-cd3fae5dd664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145561349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3145561349
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1080093319
Short name T832
Test name
Test status
Simulation time 46774022 ps
CPU time 1.95 seconds
Started Jun 10 06:35:01 PM PDT 24
Finished Jun 10 06:35:03 PM PDT 24
Peak memory 218228 kb
Host smart-9e504659-4d47-48ec-ba9a-95c924c76157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080093319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1080093319
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2733577109
Short name T816
Test name
Test status
Simulation time 135292967 ps
CPU time 1.1 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 216880 kb
Host smart-8d4422b3-9888-4d9b-9718-98b9dcb81835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733577109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2733577109
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.981623560
Short name T532
Test name
Test status
Simulation time 73036552 ps
CPU time 1.05 seconds
Started Jun 10 06:35:04 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 216932 kb
Host smart-e73f20c5-bb2b-4277-bfff-e465628e2345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981623560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.981623560
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2416415340
Short name T663
Test name
Test status
Simulation time 41390614 ps
CPU time 1.23 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218472 kb
Host smart-047dc349-1a4e-4b33-af3e-e961a5bb559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416415340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2416415340
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.952576540
Short name T748
Test name
Test status
Simulation time 32939108 ps
CPU time 1.49 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 219764 kb
Host smart-c80d89cd-c629-494a-b94b-86ed582c3f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952576540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.952576540
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1991871126
Short name T309
Test name
Test status
Simulation time 41813759 ps
CPU time 1.28 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 218376 kb
Host smart-68dd89ac-ed1f-419b-b300-a1a4139e3a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991871126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1991871126
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.4167802251
Short name T433
Test name
Test status
Simulation time 28974646 ps
CPU time 0.95 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 206612 kb
Host smart-b9801d76-9ca8-41f6-b239-52d993d32e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167802251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.4167802251
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1290826885
Short name T177
Test name
Test status
Simulation time 14024471 ps
CPU time 0.93 seconds
Started Jun 10 06:33:29 PM PDT 24
Finished Jun 10 06:33:30 PM PDT 24
Peak memory 216348 kb
Host smart-b7f4d090-18b1-4313-8c83-c1724a2719e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290826885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1290826885
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.1871213349
Short name T741
Test name
Test status
Simulation time 25788167 ps
CPU time 1.15 seconds
Started Jun 10 06:33:28 PM PDT 24
Finished Jun 10 06:33:30 PM PDT 24
Peak memory 219536 kb
Host smart-66aab8a8-73c5-4c67-86b4-986c7d6a11e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871213349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.1871213349
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.1372781054
Short name T53
Test name
Test status
Simulation time 29846477 ps
CPU time 1.01 seconds
Started Jun 10 06:33:29 PM PDT 24
Finished Jun 10 06:33:30 PM PDT 24
Peak memory 223844 kb
Host smart-6e8ccd42-b693-4231-8a07-26e21f3eddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372781054 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1372781054
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2535551620
Short name T802
Test name
Test status
Simulation time 35662496 ps
CPU time 1.04 seconds
Started Jun 10 06:33:25 PM PDT 24
Finished Jun 10 06:33:27 PM PDT 24
Peak memory 217020 kb
Host smart-13e8a83b-d938-484d-b238-38b8b29454a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535551620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2535551620
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2736922411
Short name T797
Test name
Test status
Simulation time 26587473 ps
CPU time 1.09 seconds
Started Jun 10 06:33:29 PM PDT 24
Finished Jun 10 06:33:31 PM PDT 24
Peak memory 224060 kb
Host smart-cf15dba1-5864-472a-b63c-ca1d289fbcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736922411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2736922411
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.638842864
Short name T409
Test name
Test status
Simulation time 41042195 ps
CPU time 0.97 seconds
Started Jun 10 06:33:24 PM PDT 24
Finished Jun 10 06:33:26 PM PDT 24
Peak memory 215268 kb
Host smart-d6851c72-25d3-4aee-876e-8a7233124c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638842864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.638842864
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.572513743
Short name T188
Test name
Test status
Simulation time 280109930 ps
CPU time 5.64 seconds
Started Jun 10 06:33:22 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 219612 kb
Host smart-1095f858-326d-483d-95e4-7eea03b82f27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572513743 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.572513743
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1975544043
Short name T498
Test name
Test status
Simulation time 39841530047 ps
CPU time 1004.77 seconds
Started Jun 10 06:33:23 PM PDT 24
Finished Jun 10 06:50:08 PM PDT 24
Peak memory 220428 kb
Host smart-38987f0b-5e8d-41c0-8ebf-5d92f4050a47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975544043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1975544043
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1176457760
Short name T660
Test name
Test status
Simulation time 35798169 ps
CPU time 1.32 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 219652 kb
Host smart-e690a108-2587-4d3c-b4b9-c3c76dd28fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176457760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1176457760
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1637251605
Short name T675
Test name
Test status
Simulation time 43864174 ps
CPU time 1.82 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218080 kb
Host smart-6bd19659-e834-4211-94f8-3b77d9f11c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637251605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1637251605
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1652478983
Short name T457
Test name
Test status
Simulation time 37759453 ps
CPU time 1.37 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:05 PM PDT 24
Peak memory 217960 kb
Host smart-8ce5fc30-c13b-4ad3-a849-63cdab561781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652478983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1652478983
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3139249453
Short name T449
Test name
Test status
Simulation time 30267106 ps
CPU time 1.41 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 217072 kb
Host smart-23c6163d-23bf-44f7-8a16-da408b2a533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139249453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3139249453
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.3642340873
Short name T302
Test name
Test status
Simulation time 59905082 ps
CPU time 1.47 seconds
Started Jun 10 06:34:59 PM PDT 24
Finished Jun 10 06:35:01 PM PDT 24
Peak memory 218240 kb
Host smart-7293e64d-432c-475a-9e26-e6563f0a2abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642340873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3642340873
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1991412668
Short name T568
Test name
Test status
Simulation time 79314875 ps
CPU time 1.28 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 216848 kb
Host smart-94826171-b68b-4212-bca0-27c5fdc8ac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991412668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1991412668
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1581217728
Short name T355
Test name
Test status
Simulation time 85019883 ps
CPU time 3.02 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 219816 kb
Host smart-d56662ab-59db-483c-9ac6-eae220c09cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581217728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1581217728
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.1914062791
Short name T716
Test name
Test status
Simulation time 47285812 ps
CPU time 1.2 seconds
Started Jun 10 06:35:05 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 217044 kb
Host smart-d6524068-e9ec-4ce2-aa05-6a8b6b409fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914062791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1914062791
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.351009104
Short name T661
Test name
Test status
Simulation time 41248104 ps
CPU time 1.45 seconds
Started Jun 10 06:35:08 PM PDT 24
Finished Jun 10 06:35:10 PM PDT 24
Peak memory 219264 kb
Host smart-32f1f5eb-3510-4727-926a-dcc6f1556ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351009104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.351009104
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4181511190
Short name T555
Test name
Test status
Simulation time 66006619 ps
CPU time 1.46 seconds
Started Jun 10 06:34:58 PM PDT 24
Finished Jun 10 06:35:00 PM PDT 24
Peak memory 218508 kb
Host smart-52edd894-f939-4188-b703-40b012622c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181511190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4181511190
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.2463147856
Short name T98
Test name
Test status
Simulation time 50077307 ps
CPU time 1.22 seconds
Started Jun 10 06:33:28 PM PDT 24
Finished Jun 10 06:33:30 PM PDT 24
Peak memory 219136 kb
Host smart-f368a478-f874-4778-b511-d3e7ea535a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463147856 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2463147856
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1605731723
Short name T685
Test name
Test status
Simulation time 20742984 ps
CPU time 0.93 seconds
Started Jun 10 06:33:25 PM PDT 24
Finished Jun 10 06:33:27 PM PDT 24
Peak memory 214756 kb
Host smart-9829104b-2881-4894-b0ca-ff1350832468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605731723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1605731723
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2656981625
Short name T191
Test name
Test status
Simulation time 50246260 ps
CPU time 0.89 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 216084 kb
Host smart-0a853c29-8b47-4d2e-a628-4a76f7cd8bc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656981625 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2656981625
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.3928040521
Short name T374
Test name
Test status
Simulation time 26232121 ps
CPU time 1.03 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:31 PM PDT 24
Peak memory 217892 kb
Host smart-b16908a4-fc9b-49e8-8dc6-62ee4f1a5e39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928040521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.3928040521
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.1914576808
Short name T130
Test name
Test status
Simulation time 54605896 ps
CPU time 1.05 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 229736 kb
Host smart-325b90a9-2aee-4fc8-97dc-dc72f308b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914576808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1914576808
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1835897203
Short name T760
Test name
Test status
Simulation time 43407086 ps
CPU time 1.62 seconds
Started Jun 10 06:33:28 PM PDT 24
Finished Jun 10 06:33:30 PM PDT 24
Peak memory 219776 kb
Host smart-43c24b24-237d-4e3e-a995-1be121b7172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835897203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1835897203
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.377431612
Short name T95
Test name
Test status
Simulation time 35761798 ps
CPU time 0.9 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 215544 kb
Host smart-67bb4946-8436-4a51-beff-5dc0206cda07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377431612 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.377431612
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3126992725
Short name T431
Test name
Test status
Simulation time 18400311 ps
CPU time 1.02 seconds
Started Jun 10 06:33:28 PM PDT 24
Finished Jun 10 06:33:29 PM PDT 24
Peak memory 215192 kb
Host smart-add8ce73-88e8-46f2-8e42-99136547adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126992725 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3126992725
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1519724010
Short name T551
Test name
Test status
Simulation time 81004651 ps
CPU time 1.46 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:29 PM PDT 24
Peak memory 216976 kb
Host smart-7abeb350-9a8f-48e6-ac82-173ae9df1814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519724010 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1519724010
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2225813216
Short name T40
Test name
Test status
Simulation time 71426982970 ps
CPU time 449.87 seconds
Started Jun 10 06:33:28 PM PDT 24
Finished Jun 10 06:40:58 PM PDT 24
Peak memory 223568 kb
Host smart-f0983690-cd50-4ab4-8957-0405cdd0a7bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225813216 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2225813216
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1828617795
Short name T562
Test name
Test status
Simulation time 66921418 ps
CPU time 1.19 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 216880 kb
Host smart-da0ad27d-ecc4-42a0-b1dd-1363a3bfdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828617795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1828617795
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1447504587
Short name T452
Test name
Test status
Simulation time 59584931 ps
CPU time 1.34 seconds
Started Jun 10 06:35:02 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 217064 kb
Host smart-a7132f4f-4e34-4086-bf13-1334b2cbcbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447504587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1447504587
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1711280679
Short name T586
Test name
Test status
Simulation time 41056527 ps
CPU time 1.28 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 219552 kb
Host smart-33aca4bf-9c81-4e31-a8de-59ade7a7b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711280679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1711280679
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4122878315
Short name T674
Test name
Test status
Simulation time 66882741 ps
CPU time 1.25 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 218604 kb
Host smart-6ba1df39-f178-4b65-b928-f2f7718288b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122878315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4122878315
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3771835008
Short name T319
Test name
Test status
Simulation time 67152515 ps
CPU time 1.18 seconds
Started Jun 10 06:35:07 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 217132 kb
Host smart-c2aea8a9-553f-4a60-8cd5-5072d8ff4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771835008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3771835008
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1272604162
Short name T427
Test name
Test status
Simulation time 102436152 ps
CPU time 1.46 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 219444 kb
Host smart-57f4810f-3d58-41b3-abb8-4a5d147fd612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272604162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1272604162
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1888072588
Short name T817
Test name
Test status
Simulation time 26594807 ps
CPU time 1.21 seconds
Started Jun 10 06:35:01 PM PDT 24
Finished Jun 10 06:35:03 PM PDT 24
Peak memory 216744 kb
Host smart-d2d761bb-0d2e-4d98-abe3-6696c4e1dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888072588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1888072588
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2859342783
Short name T313
Test name
Test status
Simulation time 69665035 ps
CPU time 1.37 seconds
Started Jun 10 06:35:03 PM PDT 24
Finished Jun 10 06:35:05 PM PDT 24
Peak memory 217144 kb
Host smart-28db3ade-d7fe-4639-b182-2ab71d084a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859342783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2859342783
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.1900588531
Short name T307
Test name
Test status
Simulation time 71791691 ps
CPU time 1.72 seconds
Started Jun 10 06:35:00 PM PDT 24
Finished Jun 10 06:35:03 PM PDT 24
Peak memory 218376 kb
Host smart-c15972f5-49d5-4d53-84f7-8f1d8f36817c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900588531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.1900588531
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.168325770
Short name T483
Test name
Test status
Simulation time 127238989 ps
CPU time 0.91 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:35 PM PDT 24
Peak memory 206468 kb
Host smart-645e8d9a-833c-4b1d-bb23-f15ee7d68107
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168325770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.168325770
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.537522140
Short name T209
Test name
Test status
Simulation time 11005524 ps
CPU time 0.9 seconds
Started Jun 10 06:33:33 PM PDT 24
Finished Jun 10 06:33:34 PM PDT 24
Peak memory 216148 kb
Host smart-ee4783e2-a0a3-4f29-973c-d65eb2f7eac5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537522140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.537522140
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.548295083
Short name T544
Test name
Test status
Simulation time 100617152 ps
CPU time 1.14 seconds
Started Jun 10 06:33:32 PM PDT 24
Finished Jun 10 06:33:34 PM PDT 24
Peak memory 216980 kb
Host smart-795af8d0-7327-4240-a64e-baa10f29be18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548295083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.548295083
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.112092191
Short name T149
Test name
Test status
Simulation time 30626877 ps
CPU time 1.32 seconds
Started Jun 10 06:33:37 PM PDT 24
Finished Jun 10 06:33:39 PM PDT 24
Peak memory 225796 kb
Host smart-75d5e604-1093-4328-a5b5-1e39df070478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112092191 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.112092191
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3286598121
Short name T368
Test name
Test status
Simulation time 64470889 ps
CPU time 1.6 seconds
Started Jun 10 06:33:26 PM PDT 24
Finished Jun 10 06:33:28 PM PDT 24
Peak memory 218240 kb
Host smart-638c021a-7f24-41f5-a01b-0c5977a92f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286598121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3286598121
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.56500305
Short name T430
Test name
Test status
Simulation time 21634755 ps
CPU time 1.07 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 215932 kb
Host smart-fe907f8a-4a37-4d6e-aa1f-b6c736111f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56500305 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.56500305
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3532958510
Short name T572
Test name
Test status
Simulation time 19663596 ps
CPU time 0.9 seconds
Started Jun 10 06:33:25 PM PDT 24
Finished Jun 10 06:33:26 PM PDT 24
Peak memory 215184 kb
Host smart-cf5afcd3-e2ed-4391-a9ab-b462771fec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532958510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3532958510
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2526594503
Short name T373
Test name
Test status
Simulation time 1313251793 ps
CPU time 5.31 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 06:33:33 PM PDT 24
Peak memory 216968 kb
Host smart-9692a75e-4298-4ddb-aee6-98b44e7d5293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526594503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2526594503
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4209933045
Short name T223
Test name
Test status
Simulation time 754952350638 ps
CPU time 1668.01 seconds
Started Jun 10 06:33:27 PM PDT 24
Finished Jun 10 07:01:16 PM PDT 24
Peak memory 224112 kb
Host smart-b84c3759-1b91-4ce6-9a3a-142cf42a381a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209933045 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4209933045
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1908086882
Short name T84
Test name
Test status
Simulation time 47741515 ps
CPU time 1.72 seconds
Started Jun 10 06:35:07 PM PDT 24
Finished Jun 10 06:35:09 PM PDT 24
Peak memory 219856 kb
Host smart-b1942220-5f65-465c-affe-b2e3e4595e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908086882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1908086882
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3984991185
Short name T315
Test name
Test status
Simulation time 437041151 ps
CPU time 4.52 seconds
Started Jun 10 06:35:01 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 219028 kb
Host smart-7c4b357a-329a-41cf-8f1e-f3180254043d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984991185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3984991185
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2427862355
Short name T573
Test name
Test status
Simulation time 102072071 ps
CPU time 1.52 seconds
Started Jun 10 06:35:02 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 216984 kb
Host smart-4b5baf2d-de4d-4350-b0a7-efb3fcfced2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427862355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2427862355
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.70606114
Short name T814
Test name
Test status
Simulation time 99415451 ps
CPU time 1.45 seconds
Started Jun 10 06:35:01 PM PDT 24
Finished Jun 10 06:35:03 PM PDT 24
Peak memory 218376 kb
Host smart-f8f666d2-3e48-4898-b6b6-9dae56802f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70606114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.70606114
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.4039502768
Short name T594
Test name
Test status
Simulation time 54577792 ps
CPU time 1.39 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 218348 kb
Host smart-11b2a446-a148-4ce1-94a9-a8e1be75220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039502768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.4039502768
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2795217908
Short name T523
Test name
Test status
Simulation time 4116932486 ps
CPU time 83.63 seconds
Started Jun 10 06:35:02 PM PDT 24
Finished Jun 10 06:36:26 PM PDT 24
Peak memory 220140 kb
Host smart-8d9b6f31-2f24-4741-aaa5-098edb46f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795217908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2795217908
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2764493880
Short name T595
Test name
Test status
Simulation time 155386053 ps
CPU time 1.1 seconds
Started Jun 10 06:35:07 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 216908 kb
Host smart-df0cdb76-7137-4b88-b6a6-28acae45f650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764493880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2764493880
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.642202671
Short name T278
Test name
Test status
Simulation time 26592703 ps
CPU time 1.4 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 217248 kb
Host smart-66485403-c6ce-4a0f-aa99-424e8b32cf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642202671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.642202671
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1088260111
Short name T673
Test name
Test status
Simulation time 129036322 ps
CPU time 3.08 seconds
Started Jun 10 06:35:01 PM PDT 24
Finished Jun 10 06:35:04 PM PDT 24
Peak memory 219892 kb
Host smart-171d3601-8737-451b-aae6-7572e3df7759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088260111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1088260111
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4182770823
Short name T359
Test name
Test status
Simulation time 40801791 ps
CPU time 1.27 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 218280 kb
Host smart-731d9b25-9358-4f38-a665-90b771d3d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182770823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4182770823
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3254129381
Short name T112
Test name
Test status
Simulation time 201140395 ps
CPU time 1.39 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:38 PM PDT 24
Peak memory 219476 kb
Host smart-dc9596f7-916c-4fef-a83b-5cda1437d4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254129381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3254129381
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1329063182
Short name T599
Test name
Test status
Simulation time 27765216 ps
CPU time 0.92 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:35 PM PDT 24
Peak memory 206592 kb
Host smart-b2ad2e82-bd42-48a8-aab5-b5cce8b1b466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329063182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1329063182
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1437173073
Short name T794
Test name
Test status
Simulation time 159699422 ps
CPU time 1.07 seconds
Started Jun 10 06:33:33 PM PDT 24
Finished Jun 10 06:33:34 PM PDT 24
Peak memory 216764 kb
Host smart-fe7874da-4ad2-4812-b183-76b5a35be494
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437173073 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1437173073
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1821713339
Short name T51
Test name
Test status
Simulation time 34595798 ps
CPU time 1.01 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:33:33 PM PDT 24
Peak memory 223872 kb
Host smart-6c111f66-58e6-47c1-b413-1be068423e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821713339 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1821713339
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.4194095634
Short name T776
Test name
Test status
Simulation time 230309374 ps
CPU time 3.2 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:40 PM PDT 24
Peak memory 217208 kb
Host smart-5ed5b13a-6587-46a1-a503-99ecf72a79de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194095634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.4194095634
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.1939168906
Short name T767
Test name
Test status
Simulation time 27298449 ps
CPU time 1.01 seconds
Started Jun 10 06:33:32 PM PDT 24
Finished Jun 10 06:33:33 PM PDT 24
Peak memory 215400 kb
Host smart-844da7d4-35b2-4573-80e8-d42f514d6d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939168906 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1939168906
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.518037359
Short name T450
Test name
Test status
Simulation time 41280476 ps
CPU time 0.97 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 206924 kb
Host smart-c73de8e8-3bbd-434c-bd04-a184e4e2ab11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518037359 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.518037359
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3902580434
Short name T443
Test name
Test status
Simulation time 459949680 ps
CPU time 3.05 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 216668 kb
Host smart-c77245ce-c86a-40ba-9f31-f84b0b7e744b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902580434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3902580434
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.709671923
Short name T218
Test name
Test status
Simulation time 25515577887 ps
CPU time 573.24 seconds
Started Jun 10 06:33:32 PM PDT 24
Finished Jun 10 06:43:06 PM PDT 24
Peak memory 217648 kb
Host smart-ab1a0e8f-4095-4e4c-ac18-9e7d2c22a6d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709671923 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.709671923
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.308193225
Short name T82
Test name
Test status
Simulation time 175210516 ps
CPU time 1.91 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 219932 kb
Host smart-d440f31d-fd86-4f78-a408-ade131884cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308193225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.308193225
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.197971305
Short name T312
Test name
Test status
Simulation time 59895778 ps
CPU time 1.73 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:11 PM PDT 24
Peak memory 218512 kb
Host smart-f187f8ec-6718-4cd8-accd-ea3ddc70fd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197971305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.197971305
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.10263983
Short name T492
Test name
Test status
Simulation time 82787987 ps
CPU time 1.16 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 216904 kb
Host smart-614149d1-b09a-4f68-ba39-9d8f2f6effb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10263983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.10263983
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3152115093
Short name T548
Test name
Test status
Simulation time 455458493 ps
CPU time 1.4 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 216920 kb
Host smart-3307bd41-df46-44b6-9607-809cb73df99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152115093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3152115093
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4159643328
Short name T1
Test name
Test status
Simulation time 52272925 ps
CPU time 1.45 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 218440 kb
Host smart-bab4d51e-65f2-4c08-9189-376af6af8b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159643328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4159643328
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1914247762
Short name T815
Test name
Test status
Simulation time 330801892 ps
CPU time 1.24 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:10 PM PDT 24
Peak memory 217028 kb
Host smart-2b61152e-6516-41da-8967-83e0069a2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914247762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1914247762
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1765719688
Short name T474
Test name
Test status
Simulation time 29583983 ps
CPU time 1.19 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 216844 kb
Host smart-d2f888f3-6772-4356-8374-b014c39cb6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765719688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1765719688
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2354369099
Short name T341
Test name
Test status
Simulation time 43555833 ps
CPU time 1.62 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 216792 kb
Host smart-8f6bf25d-bceb-42c9-8365-fb618f01fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354369099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2354369099
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4288536338
Short name T464
Test name
Test status
Simulation time 42565063 ps
CPU time 1.47 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:15 PM PDT 24
Peak memory 218132 kb
Host smart-13888252-1ecd-40bf-80a3-d1e7a1ebf34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288536338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4288536338
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.864300824
Short name T183
Test name
Test status
Simulation time 67570471 ps
CPU time 1.11 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 218444 kb
Host smart-3c763b95-274e-4b47-96b0-84d4bc4d9bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864300824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.864300824
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1980201111
Short name T322
Test name
Test status
Simulation time 14225049 ps
CPU time 0.93 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:31 PM PDT 24
Peak memory 206552 kb
Host smart-b22e74b4-09af-46bb-a3c1-bd9c7be25808
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980201111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1980201111
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.2225140564
Short name T176
Test name
Test status
Simulation time 13997220 ps
CPU time 0.9 seconds
Started Jun 10 06:33:32 PM PDT 24
Finished Jun 10 06:33:34 PM PDT 24
Peak memory 216368 kb
Host smart-ab65c98d-94df-4e86-90f5-32fc200a261b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225140564 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.2225140564
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.891727649
Short name T410
Test name
Test status
Simulation time 47012494 ps
CPU time 1.12 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 216964 kb
Host smart-ed641bb1-99bf-4cd8-839c-2c445bb37d35
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891727649 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.891727649
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.998072184
Short name T670
Test name
Test status
Simulation time 19553666 ps
CPU time 1.05 seconds
Started Jun 10 06:33:30 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 218312 kb
Host smart-b9612283-239e-4891-86ad-2debaae94f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998072184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.998072184
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.510351118
Short name T615
Test name
Test status
Simulation time 131911888 ps
CPU time 1.39 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 218376 kb
Host smart-2a45388b-7641-4351-98e9-43640068255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510351118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.510351118
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.139905233
Short name T567
Test name
Test status
Simulation time 24180894 ps
CPU time 0.96 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:33:32 PM PDT 24
Peak memory 215940 kb
Host smart-f32e169e-2798-4b98-b7c5-b0518ac34bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139905233 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.139905233
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.2557100170
Short name T762
Test name
Test status
Simulation time 29597916 ps
CPU time 0.96 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:38 PM PDT 24
Peak memory 207048 kb
Host smart-b7aaaf9c-5088-4886-af80-2e4fc50af979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557100170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2557100170
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1219043471
Short name T88
Test name
Test status
Simulation time 34341855 ps
CPU time 1.28 seconds
Started Jun 10 06:33:32 PM PDT 24
Finished Jun 10 06:33:34 PM PDT 24
Peak memory 217088 kb
Host smart-aa57cfae-2932-4917-a667-7e3bbdfe1ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219043471 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1219043471
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2583537816
Short name T563
Test name
Test status
Simulation time 111952125234 ps
CPU time 1265.09 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:54:37 PM PDT 24
Peak memory 223660 kb
Host smart-e52f7927-3d98-4945-a676-7cb72d12e581
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583537816 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2583537816
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.4038998892
Short name T819
Test name
Test status
Simulation time 27511779 ps
CPU time 1.25 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 219144 kb
Host smart-9b37d7b9-8084-47ae-91f7-e4dfe8257d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038998892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4038998892
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.273609883
Short name T365
Test name
Test status
Simulation time 45753349 ps
CPU time 1.45 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 216796 kb
Host smart-b167f019-3b85-4ba6-add5-61d8250dfe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273609883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.273609883
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2979836370
Short name T513
Test name
Test status
Simulation time 38167247 ps
CPU time 1.21 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 219480 kb
Host smart-7e9a8959-4bf3-4613-b774-a6ca7ff700ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979836370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2979836370
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.729236202
Short name T605
Test name
Test status
Simulation time 57833417 ps
CPU time 1.49 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 218192 kb
Host smart-5f804f89-49a3-4fd9-ab2f-d7b4fb92f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729236202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.729236202
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1436592281
Short name T290
Test name
Test status
Simulation time 76705564 ps
CPU time 1.16 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 218480 kb
Host smart-92a9a956-39f7-4989-a1e1-c2c93c973668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436592281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1436592281
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1276707693
Short name T669
Test name
Test status
Simulation time 291180393 ps
CPU time 1.29 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:35:22 PM PDT 24
Peak memory 219704 kb
Host smart-ecbc9cc8-6863-4ba0-ace0-db4c26a5d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276707693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1276707693
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3652035779
Short name T696
Test name
Test status
Simulation time 44724296 ps
CPU time 1.5 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 218120 kb
Host smart-a32c268e-9d18-4378-9c84-71f8c41305f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652035779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3652035779
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.670375448
Short name T76
Test name
Test status
Simulation time 209859005 ps
CPU time 2.36 seconds
Started Jun 10 06:35:06 PM PDT 24
Finished Jun 10 06:35:08 PM PDT 24
Peak memory 219896 kb
Host smart-a894e119-56b4-4f81-b90e-c375a1db4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670375448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.670375448
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.323278249
Short name T298
Test name
Test status
Simulation time 84418946 ps
CPU time 1.52 seconds
Started Jun 10 06:35:04 PM PDT 24
Finished Jun 10 06:35:06 PM PDT 24
Peak memory 218692 kb
Host smart-28d1b02f-6994-41f3-b935-ce287ae6dc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323278249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.323278249
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3859696379
Short name T184
Test name
Test status
Simulation time 54315333 ps
CPU time 1.3 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 215588 kb
Host smart-e4e4b181-0efb-4a45-9d7f-76191f43c86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859696379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3859696379
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.420264359
Short name T491
Test name
Test status
Simulation time 18200031 ps
CPU time 0.94 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:35 PM PDT 24
Peak memory 206444 kb
Host smart-f065cd45-7ca0-47c0-bafe-2a19d2c51f55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420264359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.420264359
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.652868723
Short name T570
Test name
Test status
Simulation time 31984247 ps
CPU time 0.85 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 216296 kb
Host smart-64ef2c70-306d-4fce-b571-d1aec1111cba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652868723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.652868723
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1104598874
Short name T131
Test name
Test status
Simulation time 33555108 ps
CPU time 1.01 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:36 PM PDT 24
Peak memory 218324 kb
Host smart-6e0cfc8f-ec69-47b3-94c0-7fb6771734bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104598874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1104598874
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_genbits.630199290
Short name T640
Test name
Test status
Simulation time 131386795 ps
CPU time 1.72 seconds
Started Jun 10 06:33:37 PM PDT 24
Finished Jun 10 06:33:39 PM PDT 24
Peak memory 218824 kb
Host smart-274683e3-caa6-4d04-b8e1-5886311f3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630199290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.630199290
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.383946939
Short name T593
Test name
Test status
Simulation time 23701582 ps
CPU time 0.97 seconds
Started Jun 10 06:33:37 PM PDT 24
Finished Jun 10 06:33:39 PM PDT 24
Peak memory 215404 kb
Host smart-98e3b5e1-9b3d-4691-ae20-7572e58d1f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383946939 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.383946939
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1823067173
Short name T629
Test name
Test status
Simulation time 49213008 ps
CPU time 0.9 seconds
Started Jun 10 06:33:31 PM PDT 24
Finished Jun 10 06:33:33 PM PDT 24
Peak memory 215200 kb
Host smart-ff017585-7979-42a8-a562-ce5c8d4e0d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823067173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1823067173
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2730075213
Short name T448
Test name
Test status
Simulation time 96351007 ps
CPU time 2.44 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 219516 kb
Host smart-ed473c97-ece4-4158-b2b5-b9a7fba9f608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730075213 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2730075213
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3921518548
Short name T261
Test name
Test status
Simulation time 217334276361 ps
CPU time 1273.45 seconds
Started Jun 10 06:33:37 PM PDT 24
Finished Jun 10 06:54:51 PM PDT 24
Peak memory 223828 kb
Host smart-7283f9c8-e23a-4b20-a0c4-8c02e4582f7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921518548 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3921518548
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2382675167
Short name T12
Test name
Test status
Simulation time 43934429 ps
CPU time 1.47 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:35:23 PM PDT 24
Peak memory 215252 kb
Host smart-397f5472-cbb7-4bac-af5a-a2bc728e62e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382675167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2382675167
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3755574728
Short name T490
Test name
Test status
Simulation time 110495378 ps
CPU time 1.3 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 216892 kb
Host smart-64e3ad61-d292-4270-9597-a36fd2a8c310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755574728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3755574728
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.115937047
Short name T511
Test name
Test status
Simulation time 51430783 ps
CPU time 1.74 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 217044 kb
Host smart-d6b1cc3d-541e-441f-92b9-a2cbd30849d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115937047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.115937047
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1130528369
Short name T321
Test name
Test status
Simulation time 71171512 ps
CPU time 2.5 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:16 PM PDT 24
Peak memory 219484 kb
Host smart-8edb0b5a-77e1-4af5-b44b-841a20c24f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130528369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1130528369
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.71362834
Short name T540
Test name
Test status
Simulation time 137028089 ps
CPU time 1.15 seconds
Started Jun 10 06:35:20 PM PDT 24
Finished Jun 10 06:35:21 PM PDT 24
Peak memory 218268 kb
Host smart-f4e4779f-9704-402f-82bc-ba94aca9f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71362834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.71362834
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3390961664
Short name T417
Test name
Test status
Simulation time 73775445 ps
CPU time 1.16 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 216940 kb
Host smart-58bdb863-9a2c-4f60-96fe-7a1546704bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390961664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3390961664
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1346192336
Short name T530
Test name
Test status
Simulation time 36824372 ps
CPU time 1.27 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 217976 kb
Host smart-da0421d3-16b4-4806-a577-cf3aa0b41a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346192336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1346192336
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1845680711
Short name T806
Test name
Test status
Simulation time 54104832 ps
CPU time 1.46 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 218312 kb
Host smart-5b5866fd-67c4-4a11-985a-5d51709cfa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845680711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1845680711
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3724654114
Short name T342
Test name
Test status
Simulation time 96634308 ps
CPU time 1.05 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 216872 kb
Host smart-e6280dae-f7cf-4bba-a15f-7ec629060e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724654114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3724654114
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.1944230442
Short name T580
Test name
Test status
Simulation time 33710987 ps
CPU time 1.19 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 218072 kb
Host smart-d2ff6410-8681-4579-94d7-d24d84617dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944230442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.1944230442
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.2722232986
Short name T782
Test name
Test status
Simulation time 19401973 ps
CPU time 1.03 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:36 PM PDT 24
Peak memory 206636 kb
Host smart-6e15a2ad-07ac-480c-ba1a-2ee0090fb7d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722232986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2722232986
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1518592127
Short name T370
Test name
Test status
Simulation time 11648759 ps
CPU time 0.9 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 216000 kb
Host smart-694d4daa-ea8e-40ac-b7c7-49a521eb59e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518592127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1518592127
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.2991726742
Short name T668
Test name
Test status
Simulation time 45307739 ps
CPU time 1.15 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 216888 kb
Host smart-be410c8c-2d37-4637-9a00-5e99a3958704
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991726742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.2991726742
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3492263591
Short name T519
Test name
Test status
Simulation time 27739529 ps
CPU time 1.15 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:37 PM PDT 24
Peak memory 220540 kb
Host smart-01afc9df-0095-4265-9356-ed0dea410b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492263591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3492263591
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.137820642
Short name T625
Test name
Test status
Simulation time 131257425 ps
CPU time 3.04 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:39 PM PDT 24
Peak memory 219916 kb
Host smart-4c65d18c-d053-4448-b033-27602d54b757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137820642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.137820642
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_smoke.697891272
Short name T527
Test name
Test status
Simulation time 71489823 ps
CPU time 0.94 seconds
Started Jun 10 06:33:34 PM PDT 24
Finished Jun 10 06:33:35 PM PDT 24
Peak memory 215232 kb
Host smart-22c7510f-d4ad-4cdf-bd6c-8126370d514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697891272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.697891272
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1551472132
Short name T360
Test name
Test status
Simulation time 312888813 ps
CPU time 1.63 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:38 PM PDT 24
Peak memory 215200 kb
Host smart-6a7cf64b-1f57-41a8-a888-575c3b5bc4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551472132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1551472132
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.936394671
Short name T385
Test name
Test status
Simulation time 117645187980 ps
CPU time 1032.74 seconds
Started Jun 10 06:33:38 PM PDT 24
Finished Jun 10 06:50:51 PM PDT 24
Peak memory 221512 kb
Host smart-52bba7eb-1a14-4464-8bad-a7e48b07b615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936394671 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.936394671
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.4018982242
Short name T679
Test name
Test status
Simulation time 75772193 ps
CPU time 1.37 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 219512 kb
Host smart-4907a65c-2473-4868-a53e-cfdbefab544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018982242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.4018982242
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.3724728052
Short name T74
Test name
Test status
Simulation time 145464505 ps
CPU time 2.96 seconds
Started Jun 10 06:35:21 PM PDT 24
Finished Jun 10 06:35:24 PM PDT 24
Peak memory 219104 kb
Host smart-1fe907e1-c0c8-4de1-92fd-2919df71bff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724728052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.3724728052
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2554648387
Short name T559
Test name
Test status
Simulation time 39723037 ps
CPU time 1.46 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:15 PM PDT 24
Peak memory 216816 kb
Host smart-6af53078-36a1-4a53-a020-7f7fca0c89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554648387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2554648387
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2692717179
Short name T575
Test name
Test status
Simulation time 51436610 ps
CPU time 1.29 seconds
Started Jun 10 06:35:10 PM PDT 24
Finished Jun 10 06:35:12 PM PDT 24
Peak memory 218396 kb
Host smart-07ba3f1f-62b0-4c8a-92b3-3a3b5bdd35a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692717179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2692717179
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.740003219
Short name T300
Test name
Test status
Simulation time 28075685 ps
CPU time 1.23 seconds
Started Jun 10 06:35:12 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 217140 kb
Host smart-2df3f20e-2c80-4618-b733-e0a022090c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740003219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.740003219
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.442605849
Short name T588
Test name
Test status
Simulation time 187030616 ps
CPU time 1.65 seconds
Started Jun 10 06:35:15 PM PDT 24
Finished Jun 10 06:35:17 PM PDT 24
Peak memory 218532 kb
Host smart-f967a37b-d6fe-4b67-b1f6-924923f3725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442605849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.442605849
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.194038029
Short name T456
Test name
Test status
Simulation time 303928032 ps
CPU time 4.41 seconds
Started Jun 10 06:35:09 PM PDT 24
Finished Jun 10 06:35:14 PM PDT 24
Peak memory 219984 kb
Host smart-fb4de98c-823a-4a76-9846-1e971f817532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194038029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.194038029
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2911695559
Short name T610
Test name
Test status
Simulation time 81080905 ps
CPU time 1.11 seconds
Started Jun 10 06:35:13 PM PDT 24
Finished Jun 10 06:35:15 PM PDT 24
Peak memory 218024 kb
Host smart-52ec65b3-6a12-498e-ad97-6453c1d8987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911695559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2911695559
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.849186603
Short name T520
Test name
Test status
Simulation time 78888149 ps
CPU time 1.13 seconds
Started Jun 10 06:35:22 PM PDT 24
Finished Jun 10 06:35:23 PM PDT 24
Peak memory 217048 kb
Host smart-f256159f-ee3b-42af-b144-0af18d8c79e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849186603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.849186603
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1591893158
Short name T687
Test name
Test status
Simulation time 159639393 ps
CPU time 1.53 seconds
Started Jun 10 06:35:11 PM PDT 24
Finished Jun 10 06:35:13 PM PDT 24
Peak memory 218380 kb
Host smart-237b2066-0d40-44c9-9325-04dc2bd360c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591893158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1591893158
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.3635858864
Short name T361
Test name
Test status
Simulation time 22622548 ps
CPU time 0.9 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 206576 kb
Host smart-f72e51ca-5910-48fb-9694-e96b6787e152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635858864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3635858864
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3191343532
Short name T197
Test name
Test status
Simulation time 37965575 ps
CPU time 0.87 seconds
Started Jun 10 06:32:21 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 216136 kb
Host smart-21585440-082d-416a-9b6d-f96478e4e9ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191343532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3191343532
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3408431690
Short name T627
Test name
Test status
Simulation time 37852139 ps
CPU time 1.09 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 217000 kb
Host smart-85c214a2-d63b-4bdb-8195-aab9bec4fd56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408431690 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3408431690
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.271131751
Short name T166
Test name
Test status
Simulation time 39508935 ps
CPU time 0.87 seconds
Started Jun 10 06:32:21 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 218296 kb
Host smart-d7d888fc-396d-4478-993d-af8e9250cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271131751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.271131751
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2144221395
Short name T576
Test name
Test status
Simulation time 66933906 ps
CPU time 2.54 seconds
Started Jun 10 06:32:21 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 219696 kb
Host smart-7466a09d-b9ad-4c28-b36d-dfaf142998f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144221395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2144221395
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.595987548
Short name T714
Test name
Test status
Simulation time 20379090 ps
CPU time 1.09 seconds
Started Jun 10 06:32:15 PM PDT 24
Finished Jun 10 06:32:17 PM PDT 24
Peak memory 215744 kb
Host smart-2ccb6a3f-b57d-4ac0-a11f-68e5147fdb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595987548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.595987548
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1926060747
Short name T281
Test name
Test status
Simulation time 26519328 ps
CPU time 0.9 seconds
Started Jun 10 06:32:15 PM PDT 24
Finished Jun 10 06:32:16 PM PDT 24
Peak memory 207008 kb
Host smart-2779c6d7-e4c6-48d6-9ff2-3f1bc953a81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926060747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1926060747
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.130717770
Short name T58
Test name
Test status
Simulation time 1817387971 ps
CPU time 5.97 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:28 PM PDT 24
Peak memory 236416 kb
Host smart-7b2cfa3a-4118-49f7-b913-142179047a35
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130717770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.130717770
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2287069809
Short name T775
Test name
Test status
Simulation time 15340510 ps
CPU time 0.98 seconds
Started Jun 10 06:32:12 PM PDT 24
Finished Jun 10 06:32:14 PM PDT 24
Peak memory 215200 kb
Host smart-dd92da90-ad6d-4ffb-8c88-0fd7e32812a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287069809 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2287069809
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1466951635
Short name T587
Test name
Test status
Simulation time 389685086 ps
CPU time 4.17 seconds
Started Jun 10 06:32:16 PM PDT 24
Finished Jun 10 06:32:21 PM PDT 24
Peak memory 219672 kb
Host smart-223a1331-e6c6-4d80-937a-ca50048163c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466951635 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1466951635
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3388497936
Short name T698
Test name
Test status
Simulation time 110721104543 ps
CPU time 1824.28 seconds
Started Jun 10 06:32:17 PM PDT 24
Finished Jun 10 07:02:42 PM PDT 24
Peak memory 228680 kb
Host smart-944937ff-f2c3-478b-b9fa-251cfce1157e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388497936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3388497936
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.305711706
Short name T129
Test name
Test status
Simulation time 176038097 ps
CPU time 1.25 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 219240 kb
Host smart-8e61c3e3-6beb-498d-a4ad-59626a72050e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305711706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.305711706
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.4202821750
Short name T323
Test name
Test status
Simulation time 56827913 ps
CPU time 0.92 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 206604 kb
Host smart-83361e9a-4f27-47bd-9c08-51aeea95b709
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202821750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.4202821750
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4168372194
Short name T602
Test name
Test status
Simulation time 29463612 ps
CPU time 0.88 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:40 PM PDT 24
Peak memory 215324 kb
Host smart-0746030f-db7b-4c3a-b441-1b0ed465781b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168372194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4168372194
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.641431207
Short name T121
Test name
Test status
Simulation time 91557455 ps
CPU time 1.07 seconds
Started Jun 10 06:33:41 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 216688 kb
Host smart-1404ebe0-e90c-487b-84d6-141185b0c53e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641431207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.641431207
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.750382470
Short name T109
Test name
Test status
Simulation time 37929681 ps
CPU time 1.18 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 217340 kb
Host smart-1a9a1dff-2d06-462f-b16c-b4fd5a97659a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750382470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.750382470
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1479858689
Short name T672
Test name
Test status
Simulation time 41189372 ps
CPU time 1.59 seconds
Started Jun 10 06:33:36 PM PDT 24
Finished Jun 10 06:33:38 PM PDT 24
Peak memory 218216 kb
Host smart-ad158cb5-0454-400d-925b-7e9aa75c5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479858689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1479858689
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.650498749
Short name T32
Test name
Test status
Simulation time 20031294 ps
CPU time 1.11 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 215848 kb
Host smart-145b3b75-d05e-41d1-92fb-dbfdf66c5a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650498749 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.650498749
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3921538743
Short name T606
Test name
Test status
Simulation time 40033460 ps
CPU time 0.87 seconds
Started Jun 10 06:33:35 PM PDT 24
Finished Jun 10 06:33:36 PM PDT 24
Peak memory 215220 kb
Host smart-a9cba4a0-f50f-4f3c-b4ce-ea621863989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921538743 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3921538743
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.449501437
Short name T260
Test name
Test status
Simulation time 80996202 ps
CPU time 2.12 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 216864 kb
Host smart-3988b1cd-7573-4621-94d4-c9e555820a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449501437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.449501437
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2456062213
Short name T262
Test name
Test status
Simulation time 109110528106 ps
CPU time 1422.79 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:57:23 PM PDT 24
Peak memory 225828 kb
Host smart-6fb72474-7b2c-4c24-a344-9022d24cc196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456062213 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2456062213
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert_test.1854301765
Short name T65
Test name
Test status
Simulation time 133561700 ps
CPU time 0.96 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 215156 kb
Host smart-b8bb33ff-7a8a-40a6-8c0a-53c28964ff48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854301765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1854301765
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1668640020
Short name T206
Test name
Test status
Simulation time 45422698 ps
CPU time 0.8 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:40 PM PDT 24
Peak memory 215280 kb
Host smart-589185f0-0e5a-4343-8f96-f50130224973
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668640020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1668640020
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1619304431
Short name T256
Test name
Test status
Simulation time 55288876 ps
CPU time 1.11 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:44 PM PDT 24
Peak memory 218256 kb
Host smart-5402b70a-c8ca-48d0-9aa4-7aa75804a924
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619304431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1619304431
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2892523407
Short name T799
Test name
Test status
Simulation time 18838506 ps
CPU time 1.06 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 218520 kb
Host smart-68f8317a-c171-4449-8ab0-24cfe1a81c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892523407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2892523407
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1739743933
Short name T463
Test name
Test status
Simulation time 99012493 ps
CPU time 1.46 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 220056 kb
Host smart-ca62fe7f-3df0-4e96-80cd-d93bc203de9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739743933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1739743933
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3304072582
Short name T578
Test name
Test status
Simulation time 34522693 ps
CPU time 0.88 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 215700 kb
Host smart-cb6a91d3-ed09-4f57-acbc-7f91e5d4e83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304072582 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3304072582
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.14155481
Short name T69
Test name
Test status
Simulation time 15855856 ps
CPU time 0.96 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:40 PM PDT 24
Peak memory 215240 kb
Host smart-9b49c229-aaa7-42bb-8b33-ec4fe79970f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14155481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.14155481
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.2330772588
Short name T328
Test name
Test status
Simulation time 306686492 ps
CPU time 2.05 seconds
Started Jun 10 06:33:41 PM PDT 24
Finished Jun 10 06:33:43 PM PDT 24
Peak memory 215212 kb
Host smart-0fa7608c-13fc-451c-9636-501e613f6fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330772588 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.2330772588
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.809180639
Short name T545
Test name
Test status
Simulation time 16484040648 ps
CPU time 441.85 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:41:02 PM PDT 24
Peak memory 223576 kb
Host smart-2104a2ce-dd86-4822-8abd-28c0e067a405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809180639 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.809180639
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.3998570232
Short name T442
Test name
Test status
Simulation time 185452797 ps
CPU time 0.95 seconds
Started Jun 10 06:33:44 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 214744 kb
Host smart-ca9b673b-eeee-439b-9e39-492846cc1cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998570232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3998570232
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.474013121
Short name T169
Test name
Test status
Simulation time 22578025 ps
CPU time 0.91 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:44 PM PDT 24
Peak memory 216128 kb
Host smart-fb922a77-4c73-4a50-94bc-40b000dca74a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474013121 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.474013121
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2824653374
Short name T499
Test name
Test status
Simulation time 22140337 ps
CPU time 0.99 seconds
Started Jun 10 06:33:46 PM PDT 24
Finished Jun 10 06:33:47 PM PDT 24
Peak memory 217904 kb
Host smart-15715c94-ef3f-4807-899d-1fd45fa41cb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824653374 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2824653374
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1728219647
Short name T110
Test name
Test status
Simulation time 55894988 ps
CPU time 0.99 seconds
Started Jun 10 06:33:42 PM PDT 24
Finished Jun 10 06:33:44 PM PDT 24
Peak memory 229612 kb
Host smart-a5a55a15-d3fa-4e92-8278-f54b63a17e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728219647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1728219647
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2084568047
Short name T485
Test name
Test status
Simulation time 37724758 ps
CPU time 1.18 seconds
Started Jun 10 06:33:39 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 216900 kb
Host smart-05869327-fc47-40e4-806e-4d337e0ea582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084568047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2084568047
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.226908879
Short name T325
Test name
Test status
Simulation time 24243524 ps
CPU time 0.92 seconds
Started Jun 10 06:33:41 PM PDT 24
Finished Jun 10 06:33:42 PM PDT 24
Peak memory 215496 kb
Host smart-27312216-f906-4bc9-a5eb-8410af5108fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226908879 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.226908879
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.398650179
Short name T399
Test name
Test status
Simulation time 84105553 ps
CPU time 0.96 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 06:33:41 PM PDT 24
Peak memory 215232 kb
Host smart-4fffebb8-7441-4841-a2de-d2c92cf41c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398650179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.398650179
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.627332062
Short name T67
Test name
Test status
Simulation time 247388891 ps
CPU time 5.02 seconds
Started Jun 10 06:33:42 PM PDT 24
Finished Jun 10 06:33:47 PM PDT 24
Peak memory 216904 kb
Host smart-eae9adf9-9907-456a-9e0d-aeec0501d1f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627332062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.627332062
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3006968150
Short name T384
Test name
Test status
Simulation time 253651588481 ps
CPU time 1911.23 seconds
Started Jun 10 06:33:40 PM PDT 24
Finished Jun 10 07:05:32 PM PDT 24
Peak memory 226480 kb
Host smart-5008a281-d3fd-4c81-92bd-6514483d9976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006968150 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3006968150
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3562225232
Short name T141
Test name
Test status
Simulation time 24693568 ps
CPU time 1.14 seconds
Started Jun 10 06:33:44 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 219232 kb
Host smart-804fc846-3c85-4ee9-99cb-1c45d07ca458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562225232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3562225232
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1257244459
Short name T558
Test name
Test status
Simulation time 18145199 ps
CPU time 0.85 seconds
Started Jun 10 06:33:42 PM PDT 24
Finished Jun 10 06:33:43 PM PDT 24
Peak memory 206716 kb
Host smart-934c698b-b920-461a-965d-01201fb84ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257244459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1257244459
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2069169031
Short name T781
Test name
Test status
Simulation time 98352835 ps
CPU time 1.06 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 216904 kb
Host smart-91d1dc58-16de-4d05-abc3-83dba505b29c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069169031 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2069169031
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.740716427
Short name T128
Test name
Test status
Simulation time 45189307 ps
CPU time 0.96 seconds
Started Jun 10 06:33:46 PM PDT 24
Finished Jun 10 06:33:47 PM PDT 24
Peak memory 219544 kb
Host smart-fbb643b3-9d11-4b1c-b77f-69acfa532a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740716427 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.740716427
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1982986496
Short name T739
Test name
Test status
Simulation time 71230616 ps
CPU time 2.79 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:46 PM PDT 24
Peak memory 217204 kb
Host smart-0f0b92f7-32c7-4c63-ac12-5f55e306e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982986496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1982986496
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2310836776
Short name T525
Test name
Test status
Simulation time 29825959 ps
CPU time 0.95 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 215520 kb
Host smart-e30b482b-dd3b-4fd2-b0c0-8cba24276763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310836776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2310836776
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.675556346
Short name T478
Test name
Test status
Simulation time 37539160 ps
CPU time 0.97 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:45 PM PDT 24
Peak memory 207000 kb
Host smart-9c07ee62-47a2-458e-b81c-26da21c8ecbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675556346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.675556346
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1894206906
Short name T699
Test name
Test status
Simulation time 347936736 ps
CPU time 4.11 seconds
Started Jun 10 06:33:42 PM PDT 24
Finished Jun 10 06:33:46 PM PDT 24
Peak memory 217000 kb
Host smart-a9326248-3f0c-4c5c-a7e5-450b75694e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894206906 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1894206906
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.150540095
Short name T424
Test name
Test status
Simulation time 570230043546 ps
CPU time 1743.29 seconds
Started Jun 10 06:33:45 PM PDT 24
Finished Jun 10 07:02:49 PM PDT 24
Peak memory 227204 kb
Host smart-0800f636-39f8-46fc-ac96-6b33674b94d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150540095 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.150540095
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3702644593
Short name T160
Test name
Test status
Simulation time 22939257 ps
CPU time 1.16 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 215584 kb
Host smart-58c12e2f-5761-4240-9d66-64a906dd2b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702644593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3702644593
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.778205281
Short name T64
Test name
Test status
Simulation time 17954823 ps
CPU time 0.99 seconds
Started Jun 10 06:33:49 PM PDT 24
Finished Jun 10 06:33:50 PM PDT 24
Peak memory 206612 kb
Host smart-3d2aa7b7-f0bf-4321-aafe-b9c89c1bb69c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778205281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.778205281
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.862014072
Short name T719
Test name
Test status
Simulation time 41440930 ps
CPU time 0.89 seconds
Started Jun 10 06:33:48 PM PDT 24
Finished Jun 10 06:33:49 PM PDT 24
Peak memory 216124 kb
Host smart-e2113077-d65a-4d8b-a5f8-2c1d726bb7f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862014072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.862014072
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1594141737
Short name T139
Test name
Test status
Simulation time 107012760 ps
CPU time 1.09 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 216900 kb
Host smart-4081be26-5bb6-4bae-bb05-11bb9d303616
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594141737 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1594141737
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.711190580
Short name T693
Test name
Test status
Simulation time 23295455 ps
CPU time 0.93 seconds
Started Jun 10 06:33:48 PM PDT 24
Finished Jun 10 06:33:49 PM PDT 24
Peak memory 218564 kb
Host smart-5e6aec9b-36be-4388-abb1-70cebf7df493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711190580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.711190580
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.726894269
Short name T651
Test name
Test status
Simulation time 57828050 ps
CPU time 1.88 seconds
Started Jun 10 06:33:46 PM PDT 24
Finished Jun 10 06:33:48 PM PDT 24
Peak memory 218188 kb
Host smart-64d11e40-fee8-49fe-baf4-15bfedd19c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726894269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.726894269
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3397097993
Short name T258
Test name
Test status
Simulation time 26073484 ps
CPU time 0.94 seconds
Started Jun 10 06:33:49 PM PDT 24
Finished Jun 10 06:33:50 PM PDT 24
Peak memory 215392 kb
Host smart-beec6733-09e3-43f2-853d-37a75944c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397097993 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3397097993
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2282240674
Short name T744
Test name
Test status
Simulation time 27793934 ps
CPU time 0.89 seconds
Started Jun 10 06:33:43 PM PDT 24
Finished Jun 10 06:33:44 PM PDT 24
Peak memory 215204 kb
Host smart-865ae909-3ec3-41a5-938f-fb99c5ae8fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282240674 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2282240674
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3403136114
Short name T375
Test name
Test status
Simulation time 277767029 ps
CPU time 5.29 seconds
Started Jun 10 06:33:47 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 216816 kb
Host smart-cc3f0029-ade8-47e5-a74c-bcb0a87713cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403136114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3403136114
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2630513306
Short name T215
Test name
Test status
Simulation time 48271499971 ps
CPU time 620.73 seconds
Started Jun 10 06:33:49 PM PDT 24
Finished Jun 10 06:44:10 PM PDT 24
Peak memory 217708 kb
Host smart-01c2dd21-a5b0-4d2f-baa2-51946e61006c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630513306 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2630513306
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3338544049
Short name T180
Test name
Test status
Simulation time 178920535 ps
CPU time 1.25 seconds
Started Jun 10 06:33:48 PM PDT 24
Finished Jun 10 06:33:50 PM PDT 24
Peak memory 215624 kb
Host smart-0722cbad-b49e-4e40-b214-09e81cf8a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338544049 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3338544049
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.1823386326
Short name T336
Test name
Test status
Simulation time 46329940 ps
CPU time 0.89 seconds
Started Jun 10 06:33:48 PM PDT 24
Finished Jun 10 06:33:49 PM PDT 24
Peak memory 215124 kb
Host smart-290a223f-0333-44d8-a6ec-46347693a940
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823386326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1823386326
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.450086431
Short name T205
Test name
Test status
Simulation time 29579428 ps
CPU time 0.84 seconds
Started Jun 10 06:33:48 PM PDT 24
Finished Jun 10 06:33:49 PM PDT 24
Peak memory 215316 kb
Host smart-481146af-e65e-4129-87bd-08079c69b514
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450086431 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.450086431
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2881474567
Short name T539
Test name
Test status
Simulation time 168406691 ps
CPU time 1.18 seconds
Started Jun 10 06:33:47 PM PDT 24
Finished Jun 10 06:33:48 PM PDT 24
Peak memory 219268 kb
Host smart-a1a5ed46-2172-4789-842a-047feb207367
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881474567 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2881474567
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.602781172
Short name T584
Test name
Test status
Simulation time 111465945 ps
CPU time 1.17 seconds
Started Jun 10 06:33:47 PM PDT 24
Finished Jun 10 06:33:49 PM PDT 24
Peak memory 219644 kb
Host smart-e5b7bce5-0756-4c73-8643-b85556a6ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602781172 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.602781172
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.465803056
Short name T233
Test name
Test status
Simulation time 52950261 ps
CPU time 1.17 seconds
Started Jun 10 06:33:50 PM PDT 24
Finished Jun 10 06:33:51 PM PDT 24
Peak memory 218204 kb
Host smart-6d94e1bc-19c4-4676-ac9f-6efe278d1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465803056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.465803056
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3713032235
Short name T381
Test name
Test status
Simulation time 34856606 ps
CPU time 0.99 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 224068 kb
Host smart-9aac4789-8a09-41d0-8154-44487c651b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713032235 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3713032235
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1036817943
Short name T466
Test name
Test status
Simulation time 17000481 ps
CPU time 1.03 seconds
Started Jun 10 06:33:49 PM PDT 24
Finished Jun 10 06:33:50 PM PDT 24
Peak memory 215204 kb
Host smart-b425f055-f253-4cfc-ae4c-1a21761e73a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036817943 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1036817943
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.789364141
Short name T187
Test name
Test status
Simulation time 296555246 ps
CPU time 1.8 seconds
Started Jun 10 06:33:49 PM PDT 24
Finished Jun 10 06:33:51 PM PDT 24
Peak memory 216580 kb
Host smart-0d29df0a-188b-4285-a888-bdc8633f2d3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789364141 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.789364141
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3450418215
Short name T582
Test name
Test status
Simulation time 37838139268 ps
CPU time 930.41 seconds
Started Jun 10 06:33:50 PM PDT 24
Finished Jun 10 06:49:21 PM PDT 24
Peak memory 218936 kb
Host smart-ecc7c786-76c7-4295-963e-fcb8d80e3a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450418215 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3450418215
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3399582157
Short name T123
Test name
Test status
Simulation time 55569294 ps
CPU time 1.34 seconds
Started Jun 10 06:33:53 PM PDT 24
Finished Jun 10 06:33:55 PM PDT 24
Peak memory 219296 kb
Host smart-ecda3343-0117-4bb9-a649-2f6585c5b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399582157 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3399582157
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1383211747
Short name T569
Test name
Test status
Simulation time 21638450 ps
CPU time 0.93 seconds
Started Jun 10 06:33:50 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 215104 kb
Host smart-cc69d28e-e285-48e0-9237-f2d2cb3feb0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383211747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1383211747
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4128296006
Short name T78
Test name
Test status
Simulation time 23427585 ps
CPU time 0.88 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 216476 kb
Host smart-ddd74858-1f55-46d0-96b3-981d47e98bd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128296006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4128296006
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.703432207
Short name T392
Test name
Test status
Simulation time 303278296 ps
CPU time 1.24 seconds
Started Jun 10 06:33:55 PM PDT 24
Finished Jun 10 06:33:56 PM PDT 24
Peak memory 216824 kb
Host smart-1a3befa2-d528-472f-9c40-c5b4a38b1de2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703432207 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.703432207
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1406988022
Short name T115
Test name
Test status
Simulation time 29699070 ps
CPU time 1.03 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:59 PM PDT 24
Peak memory 219692 kb
Host smart-97078107-f2f5-4c17-99bb-016cd0877977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406988022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1406988022
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2963566181
Short name T631
Test name
Test status
Simulation time 76159877 ps
CPU time 1.1 seconds
Started Jun 10 06:33:50 PM PDT 24
Finished Jun 10 06:33:51 PM PDT 24
Peak memory 215264 kb
Host smart-789f126c-ac31-4c3c-b8bb-759ae284984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963566181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2963566181
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.3209572299
Short name T93
Test name
Test status
Simulation time 38745225 ps
CPU time 0.85 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 215692 kb
Host smart-eff1d1b4-7edc-4025-b5d7-8d937f931105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209572299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3209572299
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2889849102
Short name T683
Test name
Test status
Simulation time 90084945 ps
CPU time 0.93 seconds
Started Jun 10 06:33:46 PM PDT 24
Finished Jun 10 06:33:48 PM PDT 24
Peak memory 215172 kb
Host smart-cad30782-0230-420b-90a7-0ceb9bfce360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889849102 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2889849102
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3632974372
Short name T533
Test name
Test status
Simulation time 291946751 ps
CPU time 3.67 seconds
Started Jun 10 06:33:46 PM PDT 24
Finished Jun 10 06:33:50 PM PDT 24
Peak memory 216756 kb
Host smart-1a018dc9-d751-4c3f-857c-b553a267684f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632974372 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3632974372
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.241029551
Short name T152
Test name
Test status
Simulation time 71693656 ps
CPU time 1.09 seconds
Started Jun 10 06:33:54 PM PDT 24
Finished Jun 10 06:33:55 PM PDT 24
Peak memory 219880 kb
Host smart-0bb160e4-22e2-4095-9290-88854bc1c2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241029551 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.241029551
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2196038510
Short name T396
Test name
Test status
Simulation time 22817218 ps
CPU time 0.85 seconds
Started Jun 10 06:33:53 PM PDT 24
Finished Jun 10 06:33:54 PM PDT 24
Peak memory 206744 kb
Host smart-f3ec4e3f-e990-4c6e-8608-b7f788da6c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196038510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2196038510
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1465214072
Short name T736
Test name
Test status
Simulation time 11142491 ps
CPU time 0.9 seconds
Started Jun 10 06:33:53 PM PDT 24
Finished Jun 10 06:33:55 PM PDT 24
Peak memory 215304 kb
Host smart-729c56f0-a715-47b5-b8cc-563dd9a28e2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465214072 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1465214072
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2777326138
Short name T447
Test name
Test status
Simulation time 59314143 ps
CPU time 1.27 seconds
Started Jun 10 06:33:50 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 215488 kb
Host smart-742f4b62-de86-4d82-b004-bf0e982fe8f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777326138 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2777326138
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1694794450
Short name T31
Test name
Test status
Simulation time 42624354 ps
CPU time 0.88 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 219300 kb
Host smart-af0889c9-ecdd-4eb0-b21f-8bacff12bdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694794450 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1694794450
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1535445884
Short name T676
Test name
Test status
Simulation time 310797515 ps
CPU time 3.72 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:33:57 PM PDT 24
Peak memory 219784 kb
Host smart-1c53b8ef-0ae5-41d8-8d89-ed1bae23b127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535445884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1535445884
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1220238359
Short name T691
Test name
Test status
Simulation time 32145421 ps
CPU time 0.91 seconds
Started Jun 10 06:33:51 PM PDT 24
Finished Jun 10 06:33:52 PM PDT 24
Peak memory 215416 kb
Host smart-cb9d60ac-c929-41de-89a4-99cf1fc4f358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220238359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1220238359
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1199608779
Short name T632
Test name
Test status
Simulation time 19195515 ps
CPU time 1.01 seconds
Started Jun 10 06:33:53 PM PDT 24
Finished Jun 10 06:33:54 PM PDT 24
Peak memory 215220 kb
Host smart-e684441d-e05d-4e1a-a376-e3e76a3b1fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199608779 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1199608779
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.60533862
Short name T637
Test name
Test status
Simulation time 284781651 ps
CPU time 5.47 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 218100 kb
Host smart-79a9f45a-151e-496f-ac7b-841e8c46bb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60533862 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.60533862
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2462733397
Short name T222
Test name
Test status
Simulation time 329289439652 ps
CPU time 423.16 seconds
Started Jun 10 06:33:54 PM PDT 24
Finished Jun 10 06:40:57 PM PDT 24
Peak memory 218236 kb
Host smart-9ed5c188-0c58-4af8-8c95-d8cdae48dd5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462733397 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2462733397
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3048473388
Short name T827
Test name
Test status
Simulation time 36999364 ps
CPU time 1.16 seconds
Started Jun 10 06:33:53 PM PDT 24
Finished Jun 10 06:33:55 PM PDT 24
Peak memory 218244 kb
Host smart-81051993-b773-46b8-99ba-4f7f500e1816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048473388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3048473388
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4030989065
Short name T395
Test name
Test status
Simulation time 10852437 ps
CPU time 0.83 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 206736 kb
Host smart-5e5f5489-4dc9-4a0d-bfef-1edd530d0156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030989065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4030989065
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.860246898
Short name T158
Test name
Test status
Simulation time 33394897 ps
CPU time 0.85 seconds
Started Jun 10 06:33:56 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 216164 kb
Host smart-5a568916-8613-4c5b-824b-b48ed8c1af1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860246898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.860246898
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4174366161
Short name T132
Test name
Test status
Simulation time 131454720 ps
CPU time 1.04 seconds
Started Jun 10 06:33:56 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 218372 kb
Host smart-09e05ca4-76a0-4e38-bfb9-72d1c2b5b337
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174366161 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4174366161
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.423842533
Short name T347
Test name
Test status
Simulation time 21557398 ps
CPU time 0.96 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 218632 kb
Host smart-bc698af4-0677-4aca-a3e3-509d32515d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423842533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.423842533
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1817173680
Short name T619
Test name
Test status
Simulation time 71235483 ps
CPU time 1.57 seconds
Started Jun 10 06:33:55 PM PDT 24
Finished Jun 10 06:33:57 PM PDT 24
Peak memory 218228 kb
Host smart-0ba43af5-994c-4bbc-b47d-866d44b9d4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817173680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1817173680
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.3701532360
Short name T645
Test name
Test status
Simulation time 21908323 ps
CPU time 1.09 seconds
Started Jun 10 06:33:56 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 215556 kb
Host smart-90b808f2-b674-4067-871f-a222ac0c0c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701532360 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3701532360
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2865068888
Short name T634
Test name
Test status
Simulation time 51107035 ps
CPU time 1 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:33:53 PM PDT 24
Peak memory 206960 kb
Host smart-d0fd1532-bf12-4788-991e-1b471461f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865068888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2865068888
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4288128393
Short name T811
Test name
Test status
Simulation time 609019720 ps
CPU time 5.6 seconds
Started Jun 10 06:33:52 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 216828 kb
Host smart-c37fbf47-8d4b-41dc-964d-da80aa513588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288128393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4288128393
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert_test.700527732
Short name T564
Test name
Test status
Simulation time 38596595 ps
CPU time 0.88 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:02 PM PDT 24
Peak memory 214732 kb
Host smart-e3deeee1-8a13-43f4-b233-cc0df1845290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700527732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.700527732
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2361972932
Short name T677
Test name
Test status
Simulation time 13068206 ps
CPU time 0.9 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 215504 kb
Host smart-ae293934-1218-45aa-9c1d-635c3a4d8d45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361972932 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2361972932
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.749819242
Short name T706
Test name
Test status
Simulation time 41222690 ps
CPU time 1.18 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:59 PM PDT 24
Peak memory 216828 kb
Host smart-2f1990a9-a365-47bd-94e9-96d86e75115c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749819242 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.749819242
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_genbits.58313282
Short name T740
Test name
Test status
Simulation time 52161183 ps
CPU time 1.55 seconds
Started Jun 10 06:33:56 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 218692 kb
Host smart-73d91b80-0a04-4d11-ab3f-55ed5b60a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58313282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.58313282
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.35816120
Short name T33
Test name
Test status
Simulation time 33541267 ps
CPU time 0.88 seconds
Started Jun 10 06:33:59 PM PDT 24
Finished Jun 10 06:34:00 PM PDT 24
Peak memory 215592 kb
Host smart-31f510fc-23bf-436e-bb2a-c5c46aa431bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35816120 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.35816120
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.417369713
Short name T364
Test name
Test status
Simulation time 72938761 ps
CPU time 0.93 seconds
Started Jun 10 06:33:57 PM PDT 24
Finished Jun 10 06:33:58 PM PDT 24
Peak memory 215204 kb
Host smart-276bfc1f-b008-4c1e-b47f-fa8e9efb34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417369713 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.417369713
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2130790341
Short name T522
Test name
Test status
Simulation time 349050010 ps
CPU time 6.4 seconds
Started Jun 10 06:33:59 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 216864 kb
Host smart-35225975-3d82-46dc-aa90-d0811b7fa152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130790341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2130790341
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4231314758
Short name T216
Test name
Test status
Simulation time 44569925362 ps
CPU time 531.51 seconds
Started Jun 10 06:33:54 PM PDT 24
Finished Jun 10 06:42:46 PM PDT 24
Peak memory 223584 kb
Host smart-8a01bc05-764c-4113-a944-de12e83b4820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231314758 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4231314758
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert_test.1772647510
Short name T50
Test name
Test status
Simulation time 74900493 ps
CPU time 0.85 seconds
Started Jun 10 06:32:31 PM PDT 24
Finished Jun 10 06:32:32 PM PDT 24
Peak memory 214556 kb
Host smart-94abe472-0c0b-4fb7-8450-de9704d03fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772647510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1772647510
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.663513689
Short name T771
Test name
Test status
Simulation time 23410984 ps
CPU time 0.86 seconds
Started Jun 10 06:32:27 PM PDT 24
Finished Jun 10 06:32:28 PM PDT 24
Peak memory 215964 kb
Host smart-3ee23f80-420c-4cc9-a336-bc9878395a71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663513689 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.663513689
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2656486114
Short name T201
Test name
Test status
Simulation time 44718210 ps
CPU time 1.33 seconds
Started Jun 10 06:32:24 PM PDT 24
Finished Jun 10 06:32:26 PM PDT 24
Peak memory 215532 kb
Host smart-70c01816-a3cc-40cf-bba6-4e99a46eb198
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656486114 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2656486114
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2312189496
Short name T189
Test name
Test status
Simulation time 33217443 ps
CPU time 0.88 seconds
Started Jun 10 06:32:23 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 218648 kb
Host smart-23487a44-1179-4be2-9863-dfbcff9e3d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312189496 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2312189496
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.306812297
Short name T14
Test name
Test status
Simulation time 152139244 ps
CPU time 3.4 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 217332 kb
Host smart-1981e1e4-31e7-49e0-a7dc-f2cdc4a49491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306812297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.306812297
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2278137925
Short name T34
Test name
Test status
Simulation time 35205790 ps
CPU time 0.84 seconds
Started Jun 10 06:32:23 PM PDT 24
Finished Jun 10 06:32:24 PM PDT 24
Peak memory 215484 kb
Host smart-548df0fb-2081-46a4-aa6b-a16f56f18585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278137925 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2278137925
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.3788837027
Short name T286
Test name
Test status
Simulation time 17396667 ps
CPU time 0.97 seconds
Started Jun 10 06:32:22 PM PDT 24
Finished Jun 10 06:32:23 PM PDT 24
Peak memory 206992 kb
Host smart-548a14e2-d897-409e-8767-525d5d655d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788837027 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3788837027
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3553802721
Short name T16
Test name
Test status
Simulation time 863844690 ps
CPU time 7.72 seconds
Started Jun 10 06:32:26 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 236040 kb
Host smart-9a7fd76b-ba68-4ec7-bea7-13e9a0af2739
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553802721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3553802721
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.509507622
Short name T482
Test name
Test status
Simulation time 29188238 ps
CPU time 0.93 seconds
Started Jun 10 06:32:21 PM PDT 24
Finished Jun 10 06:32:22 PM PDT 24
Peak memory 215184 kb
Host smart-c6c8b806-6d36-434b-af61-ac8d97c966d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509507622 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.509507622
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2087704730
Short name T414
Test name
Test status
Simulation time 171905206 ps
CPU time 3.69 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:34 PM PDT 24
Peak memory 215216 kb
Host smart-54ec0ac4-a391-4891-b5ec-83f0ff5809af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087704730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2087704730
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2604564321
Short name T221
Test name
Test status
Simulation time 107003750122 ps
CPU time 614.98 seconds
Started Jun 10 06:32:26 PM PDT 24
Finished Jun 10 06:42:41 PM PDT 24
Peak memory 219252 kb
Host smart-d6020660-7bdd-4285-bead-f0a4151ea647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604564321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2604564321
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert_test.3938921493
Short name T531
Test name
Test status
Simulation time 17192485 ps
CPU time 1.06 seconds
Started Jun 10 06:34:01 PM PDT 24
Finished Jun 10 06:34:02 PM PDT 24
Peak memory 206592 kb
Host smart-c12d24d4-f41d-4c2f-9a8f-67b667b842db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938921493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3938921493
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1139735657
Short name T207
Test name
Test status
Simulation time 15597001 ps
CPU time 0.88 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:01 PM PDT 24
Peak memory 215304 kb
Host smart-635db818-db7c-4769-82d2-fb1dbce341d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139735657 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1139735657
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.1600928479
Short name T8
Test name
Test status
Simulation time 29723112 ps
CPU time 1.07 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:01 PM PDT 24
Peak memory 219748 kb
Host smart-29a17371-9e2b-4732-9f3d-e97ba1f3f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600928479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1600928479
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2783865811
Short name T648
Test name
Test status
Simulation time 55029904 ps
CPU time 1.37 seconds
Started Jun 10 06:33:59 PM PDT 24
Finished Jun 10 06:34:01 PM PDT 24
Peak memory 218120 kb
Host smart-cb4571e1-cc23-4eb3-bac1-10a6751ec5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783865811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2783865811
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2004180183
Short name T500
Test name
Test status
Simulation time 23324803 ps
CPU time 1.07 seconds
Started Jun 10 06:34:02 PM PDT 24
Finished Jun 10 06:34:04 PM PDT 24
Peak memory 215472 kb
Host smart-59e3b2ff-9b54-4738-af17-2f59dc8f85e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004180183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2004180183
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2328125132
Short name T514
Test name
Test status
Simulation time 39225482 ps
CPU time 0.9 seconds
Started Jun 10 06:34:05 PM PDT 24
Finished Jun 10 06:34:06 PM PDT 24
Peak memory 207036 kb
Host smart-980d23f3-4745-47aa-bf58-9cb9a260c09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328125132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2328125132
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.752233824
Short name T476
Test name
Test status
Simulation time 168975177 ps
CPU time 3.12 seconds
Started Jun 10 06:34:00 PM PDT 24
Finished Jun 10 06:34:03 PM PDT 24
Peak memory 215420 kb
Host smart-88718bba-95ff-414d-9c18-8a5922df8c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752233824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.752233824
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2482246747
Short name T350
Test name
Test status
Simulation time 357739685767 ps
CPU time 2465.24 seconds
Started Jun 10 06:33:58 PM PDT 24
Finished Jun 10 07:15:04 PM PDT 24
Peak memory 231240 kb
Host smart-0c9ee438-dca8-4dfb-af18-d1c88c23763c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482246747 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2482246747
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3609562612
Short name T120
Test name
Test status
Simulation time 61082492 ps
CPU time 1.24 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:09 PM PDT 24
Peak memory 219736 kb
Host smart-9cae6f2b-92e6-46f3-97ec-5377eb04ca0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609562612 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3609562612
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.3975501843
Short name T818
Test name
Test status
Simulation time 33120950 ps
CPU time 0.81 seconds
Started Jun 10 06:34:05 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 205864 kb
Host smart-455a2858-b758-41c7-a122-bdade2b5c136
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975501843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3975501843
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.746229451
Short name T196
Test name
Test status
Simulation time 10726707 ps
CPU time 0.95 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 216296 kb
Host smart-ebcbb49e-184f-412a-876e-ee0b69b70f28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746229451 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.746229451
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3429187346
Short name T107
Test name
Test status
Simulation time 45280468 ps
CPU time 1.38 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 216848 kb
Host smart-21707029-c353-4649-bf34-e42f8bab0f14
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429187346 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3429187346
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2500416395
Short name T148
Test name
Test status
Simulation time 24808246 ps
CPU time 1 seconds
Started Jun 10 06:34:06 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 218560 kb
Host smart-e9fd6068-bfe0-4e80-8f3f-dbe5cdd22fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500416395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2500416395
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3631074025
Short name T546
Test name
Test status
Simulation time 44590660 ps
CPU time 1.12 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:06 PM PDT 24
Peak memory 216876 kb
Host smart-8a7f9b93-1dd1-4701-8dd4-4e7cbfaa695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631074025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3631074025
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2691972297
Short name T37
Test name
Test status
Simulation time 27522596 ps
CPU time 0.87 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:08 PM PDT 24
Peak memory 215696 kb
Host smart-74e205e7-d8fe-4f31-b783-0ca956280096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691972297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2691972297
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1911299212
Short name T695
Test name
Test status
Simulation time 25242722 ps
CPU time 0.92 seconds
Started Jun 10 06:34:01 PM PDT 24
Finished Jun 10 06:34:02 PM PDT 24
Peak memory 215220 kb
Host smart-e9424a1e-ec45-4405-a0df-2cee446828c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911299212 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1911299212
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3895706244
Short name T835
Test name
Test status
Simulation time 514994768 ps
CPU time 3.5 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:08 PM PDT 24
Peak memory 219528 kb
Host smart-09fee835-2ef9-431f-b2af-d1d2001729fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895706244 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3895706244
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1965715340
Short name T707
Test name
Test status
Simulation time 65147146892 ps
CPU time 395.52 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:40:43 PM PDT 24
Peak memory 223636 kb
Host smart-42105a1a-a9e5-4340-b95e-efd1f4d5e935
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965715340 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1965715340
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.241178569
Short name T164
Test name
Test status
Simulation time 29150639 ps
CPU time 1.28 seconds
Started Jun 10 06:34:05 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 220296 kb
Host smart-a3564c73-3887-4ff7-9445-77315bd02147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241178569 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.241178569
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1524932773
Short name T3
Test name
Test status
Simulation time 18147884 ps
CPU time 0.98 seconds
Started Jun 10 06:34:03 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 215076 kb
Host smart-647d4bd4-108a-4ec9-bec5-0789292e5605
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524932773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1524932773
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1646298443
Short name T597
Test name
Test status
Simulation time 23329551 ps
CPU time 0.87 seconds
Started Jun 10 06:34:02 PM PDT 24
Finished Jun 10 06:34:04 PM PDT 24
Peak memory 216172 kb
Host smart-03299032-e42a-43e0-917e-dd664a39c6f6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646298443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1646298443
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2359600747
Short name T434
Test name
Test status
Simulation time 120198247 ps
CPU time 1.25 seconds
Started Jun 10 06:34:05 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 219344 kb
Host smart-8373212b-a337-4821-9cc6-23e5f8a688a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359600747 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2359600747
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1718039811
Short name T168
Test name
Test status
Simulation time 54302505 ps
CPU time 1.01 seconds
Started Jun 10 06:34:06 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 223840 kb
Host smart-2e7fd41c-e085-41eb-a66c-280466636adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718039811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1718039811
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3721147594
Short name T787
Test name
Test status
Simulation time 85937961 ps
CPU time 2.18 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 218424 kb
Host smart-10841af1-da78-4bd2-932b-57d41e5fc33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721147594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3721147594
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2230154938
Short name T496
Test name
Test status
Simulation time 36417910 ps
CPU time 0.86 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 215560 kb
Host smart-4697ae85-e8ee-4ea7-bf42-d13c23a41f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230154938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2230154938
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.237947991
Short name T418
Test name
Test status
Simulation time 40462231 ps
CPU time 0.94 seconds
Started Jun 10 06:34:04 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 215276 kb
Host smart-06ec0534-a6fa-406d-a82c-4282eb472758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237947991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.237947991
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2614887104
Short name T822
Test name
Test status
Simulation time 694542278 ps
CPU time 2.75 seconds
Started Jun 10 06:34:03 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 216796 kb
Host smart-6ea94150-3043-41d4-9d1d-f3ba848ba47f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614887104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2614887104
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2279509792
Short name T554
Test name
Test status
Simulation time 188374369454 ps
CPU time 1099.16 seconds
Started Jun 10 06:34:06 PM PDT 24
Finished Jun 10 06:52:26 PM PDT 24
Peak memory 221480 kb
Host smart-41047ed7-9a0b-4d29-8f46-b11be1272d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279509792 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2279509792
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2173060500
Short name T30
Test name
Test status
Simulation time 264939393 ps
CPU time 1.39 seconds
Started Jun 10 06:34:05 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 219156 kb
Host smart-65452555-8ca6-48df-8a84-5fb32870da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173060500 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2173060500
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.2904690792
Short name T502
Test name
Test status
Simulation time 50682784 ps
CPU time 0.91 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 206668 kb
Host smart-df069f68-9a08-450c-8e8b-bcf40ec75f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904690792 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2904690792
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1936268465
Short name T715
Test name
Test status
Simulation time 21020003 ps
CPU time 0.84 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:19 PM PDT 24
Peak memory 215856 kb
Host smart-d81bf072-44ef-4cd2-895c-b7055c5b1c9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936268465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1936268465
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_genbits.419958374
Short name T743
Test name
Test status
Simulation time 52189816 ps
CPU time 1.37 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:09 PM PDT 24
Peak memory 218616 kb
Host smart-adb0ef86-8304-4b10-968a-a42aee3fafd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419958374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.419958374
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.196814833
Short name T728
Test name
Test status
Simulation time 30926196 ps
CPU time 1.03 seconds
Started Jun 10 06:34:03 PM PDT 24
Finished Jun 10 06:34:05 PM PDT 24
Peak memory 224004 kb
Host smart-53b2c959-427d-4fa1-a5d6-7b78dd145ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196814833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.196814833
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2510873812
Short name T759
Test name
Test status
Simulation time 15963376 ps
CPU time 0.96 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:08 PM PDT 24
Peak memory 215228 kb
Host smart-0e84f360-67ec-4ae1-a489-b586a92a4771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510873812 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2510873812
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.110411660
Short name T227
Test name
Test status
Simulation time 262803717 ps
CPU time 3.65 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 217048 kb
Host smart-abdb7426-5875-4e56-afd6-376c7967560f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110411660 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.110411660
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.857442669
Short name T62
Test name
Test status
Simulation time 149182510631 ps
CPU time 504.42 seconds
Started Jun 10 06:34:03 PM PDT 24
Finished Jun 10 06:42:28 PM PDT 24
Peak memory 223620 kb
Host smart-9fc2b9af-0592-4270-ba0d-1e2a0532dfce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857442669 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.857442669
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2704636102
Short name T611
Test name
Test status
Simulation time 115637389 ps
CPU time 1.18 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:09 PM PDT 24
Peak memory 218788 kb
Host smart-a74fd6bf-3bf3-4663-827a-56af35f82ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704636102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2704636102
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.854001185
Short name T757
Test name
Test status
Simulation time 59872985 ps
CPU time 0.89 seconds
Started Jun 10 06:34:10 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 215124 kb
Host smart-00996618-4138-4248-89d3-37d4b97b11a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854001185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.854001185
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.15370693
Short name T406
Test name
Test status
Simulation time 28234871 ps
CPU time 0.82 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 215848 kb
Host smart-d435f1b7-0dd3-4e72-ba27-d832c33f6268
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370693 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.15370693
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3729696485
Short name T692
Test name
Test status
Simulation time 92553751 ps
CPU time 1.1 seconds
Started Jun 10 06:34:10 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 215604 kb
Host smart-16c9e975-f926-467d-9205-ee4d1c60802c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729696485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3729696485
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.3332475540
Short name T538
Test name
Test status
Simulation time 41507248 ps
CPU time 0.91 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 218616 kb
Host smart-8919d8ea-98c1-439e-87a2-5836e5e7d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332475540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3332475540
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1779578081
Short name T48
Test name
Test status
Simulation time 53710905 ps
CPU time 1.89 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 218244 kb
Host smart-c584355c-61e2-4e9f-ac3d-04cf24a2e8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779578081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1779578081
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3279565825
Short name T712
Test name
Test status
Simulation time 20365693 ps
CPU time 1.23 seconds
Started Jun 10 06:34:08 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 223988 kb
Host smart-1e86d549-2ba4-452d-b74a-d0f7d014c8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279565825 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3279565825
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1064226569
Short name T401
Test name
Test status
Simulation time 16984116 ps
CPU time 0.96 seconds
Started Jun 10 06:34:11 PM PDT 24
Finished Jun 10 06:34:12 PM PDT 24
Peak memory 215244 kb
Host smart-b3f34ccc-8aa7-40cd-a44b-ea2d3f8c448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064226569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1064226569
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1477351850
Short name T358
Test name
Test status
Simulation time 70187598 ps
CPU time 1.98 seconds
Started Jun 10 06:34:08 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 215228 kb
Host smart-e7ced6ae-6a10-4d2f-abea-0c6c0257b4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477351850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1477351850
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2124415614
Short name T192
Test name
Test status
Simulation time 89925291583 ps
CPU time 2158.61 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 07:10:06 PM PDT 24
Peak memory 230476 kb
Host smart-33d2d2a7-edc5-4ad6-b204-3d8f9043db7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124415614 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2124415614
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert_test.1935984836
Short name T510
Test name
Test status
Simulation time 16737422 ps
CPU time 0.95 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 214736 kb
Host smart-895791fd-1778-4472-9981-4f2ed2a35418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935984836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1935984836
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.4015611753
Short name T175
Test name
Test status
Simulation time 18732873 ps
CPU time 0.87 seconds
Started Jun 10 06:34:22 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 216152 kb
Host smart-0e576cff-bbbb-41b5-881f-5416b6debcf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015611753 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4015611753
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3182947102
Short name T133
Test name
Test status
Simulation time 35309805 ps
CPU time 1.21 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:11 PM PDT 24
Peak memory 219484 kb
Host smart-d9e687ab-09d0-4052-bac5-a109c8c54291
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182947102 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3182947102
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.445678641
Short name T54
Test name
Test status
Simulation time 50439626 ps
CPU time 1.14 seconds
Started Jun 10 06:34:07 PM PDT 24
Finished Jun 10 06:34:09 PM PDT 24
Peak memory 224144 kb
Host smart-9ec4ff38-d6e8-4510-bb75-a9851a7a016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445678641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.445678641
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2056639241
Short name T316
Test name
Test status
Simulation time 142599109 ps
CPU time 1.14 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 219704 kb
Host smart-07bd7764-db80-4710-b9b0-0aff733bb662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056639241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2056639241
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.946048684
Short name T608
Test name
Test status
Simulation time 54576927 ps
CPU time 0.91 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 215164 kb
Host smart-17e13a2e-d40d-4edc-a92e-7de169777d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946048684 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.946048684
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3394115916
Short name T826
Test name
Test status
Simulation time 40087895 ps
CPU time 0.9 seconds
Started Jun 10 06:34:06 PM PDT 24
Finished Jun 10 06:34:07 PM PDT 24
Peak memory 215152 kb
Host smart-329f3628-c38a-4613-8db7-15a9c0eb9d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394115916 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3394115916
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1913946379
Short name T377
Test name
Test status
Simulation time 502662492 ps
CPU time 3.17 seconds
Started Jun 10 06:34:08 PM PDT 24
Finished Jun 10 06:34:12 PM PDT 24
Peak memory 216840 kb
Host smart-37b18d2d-aa07-4653-ad6a-d4debd25b41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913946379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1913946379
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.323183568
Short name T829
Test name
Test status
Simulation time 165114346266 ps
CPU time 933.54 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:49:43 PM PDT 24
Peak memory 220536 kb
Host smart-0e45ea33-92d1-4a1e-acf1-242b67c6c335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323183568 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.323183568
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.416338558
Short name T681
Test name
Test status
Simulation time 23333770 ps
CPU time 1.28 seconds
Started Jun 10 06:34:11 PM PDT 24
Finished Jun 10 06:34:13 PM PDT 24
Peak memory 218196 kb
Host smart-868ac783-3487-487e-a003-9d3bda3edf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416338558 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.416338558
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3398882167
Short name T655
Test name
Test status
Simulation time 23382092 ps
CPU time 0.92 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 206592 kb
Host smart-b4730f4a-753c-41a8-92e7-b34096093e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398882167 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3398882167
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.4085798766
Short name T643
Test name
Test status
Simulation time 42282429 ps
CPU time 0.88 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 216156 kb
Host smart-366b43e5-c760-48fa-8642-119cb47660ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085798766 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.4085798766
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2008331801
Short name T145
Test name
Test status
Simulation time 108842091 ps
CPU time 1.09 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 216748 kb
Host smart-c637aa18-7196-496f-9a1d-53973140086c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008331801 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2008331801
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3543870849
Short name T686
Test name
Test status
Simulation time 135021145 ps
CPU time 1.06 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 219620 kb
Host smart-670b4ab6-1b9e-4407-aa89-2b34b667875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543870849 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3543870849
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.414528738
Short name T70
Test name
Test status
Simulation time 56241223 ps
CPU time 1.05 seconds
Started Jun 10 06:34:09 PM PDT 24
Finished Jun 10 06:34:10 PM PDT 24
Peak memory 216984 kb
Host smart-e76e49ea-0503-43e5-b286-b6339c9362ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414528738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.414528738
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1611636129
Short name T653
Test name
Test status
Simulation time 39196818 ps
CPU time 0.95 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:17 PM PDT 24
Peak memory 215420 kb
Host smart-62eca5f4-4387-4542-b464-9c96d8b5c85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611636129 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1611636129
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3083303818
Short name T552
Test name
Test status
Simulation time 27485098 ps
CPU time 0.95 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 215224 kb
Host smart-f9e09915-2be5-4a6f-a94a-abe298d99510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083303818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3083303818
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.130073501
Short name T326
Test name
Test status
Simulation time 829868207 ps
CPU time 4.99 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:24 PM PDT 24
Peak memory 216828 kb
Host smart-51a73332-39f8-463f-8936-139a60e60cf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130073501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.130073501
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.2853050666
Short name T518
Test name
Test status
Simulation time 49624473618 ps
CPU time 1216.16 seconds
Started Jun 10 06:34:12 PM PDT 24
Finished Jun 10 06:54:29 PM PDT 24
Peak memory 220100 kb
Host smart-3fb36fd8-a728-467f-9cd8-5a31d61dd7bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853050666 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.2853050666
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert_test.530086175
Short name T344
Test name
Test status
Simulation time 14993115 ps
CPU time 0.9 seconds
Started Jun 10 06:34:14 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 214720 kb
Host smart-bc5f5bb7-fbbe-46ed-a4cf-3a619460190d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530086175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.530086175
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.191993333
Short name T211
Test name
Test status
Simulation time 12717968 ps
CPU time 0.96 seconds
Started Jun 10 06:34:14 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 215492 kb
Host smart-c1dd2edc-0333-4f64-85c9-4c068adbe652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191993333 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.191993333
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1153164753
Short name T480
Test name
Test status
Simulation time 112666182 ps
CPU time 1.14 seconds
Started Jun 10 06:34:11 PM PDT 24
Finished Jun 10 06:34:13 PM PDT 24
Peak memory 218076 kb
Host smart-4ff519be-8b70-4c97-b237-153f38848778
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153164753 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1153164753
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.952551894
Short name T801
Test name
Test status
Simulation time 22727395 ps
CPU time 1.18 seconds
Started Jun 10 06:34:12 PM PDT 24
Finished Jun 10 06:34:13 PM PDT 24
Peak memory 219896 kb
Host smart-2ba49a69-3856-4bc7-ae3f-eb1cc1ff2848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952551894 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.952551894
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1814794221
Short name T779
Test name
Test status
Simulation time 67218810 ps
CPU time 1.15 seconds
Started Jun 10 06:34:14 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 216928 kb
Host smart-55d28a60-2bfe-40da-866e-9f96f7875e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814794221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1814794221
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1984253639
Short name T415
Test name
Test status
Simulation time 28037295 ps
CPU time 0.97 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 215800 kb
Host smart-a16be765-5dad-40a7-823d-eaddb7d6e293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984253639 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1984253639
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.11831835
Short name T230
Test name
Test status
Simulation time 27140625 ps
CPU time 0.94 seconds
Started Jun 10 06:34:12 PM PDT 24
Finished Jun 10 06:34:13 PM PDT 24
Peak memory 215220 kb
Host smart-835fe703-bd32-4311-9c6a-136ec03a6795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11831835 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.11831835
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2879462854
Short name T541
Test name
Test status
Simulation time 141485389 ps
CPU time 2.07 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 216864 kb
Host smart-d73a246c-b2dd-4559-afa2-071ea1e633d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879462854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2879462854
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2537883937
Short name T701
Test name
Test status
Simulation time 472139094109 ps
CPU time 742.66 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:46:38 PM PDT 24
Peak memory 219152 kb
Host smart-91d36701-cfe3-4425-834c-1808ddb03ac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537883937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2537883937
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2234925938
Short name T135
Test name
Test status
Simulation time 48064983 ps
CPU time 1.21 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 220388 kb
Host smart-8c4759be-d951-49af-adf7-01b33098706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234925938 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2234925938
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2413281198
Short name T451
Test name
Test status
Simulation time 28217808 ps
CPU time 0.89 seconds
Started Jun 10 06:34:17 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 206296 kb
Host smart-10459b64-0200-40fa-9619-a9284efd73a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413281198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2413281198
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.1140381328
Short name T194
Test name
Test status
Simulation time 17565018 ps
CPU time 0.83 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 216156 kb
Host smart-cd2dd5df-e07c-41b9-88f2-f9212d3b8166
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140381328 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.1140381328
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.283343744
Short name T122
Test name
Test status
Simulation time 46341893 ps
CPU time 1.05 seconds
Started Jun 10 06:34:14 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 216764 kb
Host smart-30c6a81a-1851-49f5-933b-3b7e5a046896
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283343744 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.283343744
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2351445192
Short name T259
Test name
Test status
Simulation time 19647980 ps
CPU time 1.05 seconds
Started Jun 10 06:34:14 PM PDT 24
Finished Jun 10 06:34:15 PM PDT 24
Peak memory 218620 kb
Host smart-8ae46831-d116-4a94-a4f8-6cfe9b423b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351445192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2351445192
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1709403176
Short name T784
Test name
Test status
Simulation time 29265160 ps
CPU time 1.25 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 216920 kb
Host smart-7e20f6fc-967a-4a8e-a30f-9b422e80531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709403176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1709403176
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2744102505
Short name T680
Test name
Test status
Simulation time 35631425 ps
CPU time 0.84 seconds
Started Jun 10 06:34:12 PM PDT 24
Finished Jun 10 06:34:13 PM PDT 24
Peak memory 215220 kb
Host smart-9979a4fa-eb21-452c-a083-0f48f8885642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744102505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2744102505
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.576067280
Short name T766
Test name
Test status
Simulation time 44037739 ps
CPU time 0.93 seconds
Started Jun 10 06:34:13 PM PDT 24
Finished Jun 10 06:34:14 PM PDT 24
Peak memory 215216 kb
Host smart-be3dda3b-f051-4bf5-9fdf-453e22b2ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576067280 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.576067280
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.765765342
Short name T379
Test name
Test status
Simulation time 274861627 ps
CPU time 1.39 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 216992 kb
Host smart-7c9c8bd3-cd4a-4804-85a0-cadf6c909751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765765342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.765765342
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2612638189
Short name T635
Test name
Test status
Simulation time 40967440927 ps
CPU time 188.41 seconds
Started Jun 10 06:34:12 PM PDT 24
Finished Jun 10 06:37:20 PM PDT 24
Peak memory 218432 kb
Host smart-357187b2-3a8e-467a-aceb-71ecc36d753a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612638189 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2612638189
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.75252150
Short name T124
Test name
Test status
Simulation time 27042785 ps
CPU time 1.32 seconds
Started Jun 10 06:34:17 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 219868 kb
Host smart-1b16bac4-2095-479b-9129-4964f9480fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75252150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.75252150
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3224302767
Short name T391
Test name
Test status
Simulation time 49286208 ps
CPU time 0.9 seconds
Started Jun 10 06:34:25 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 214720 kb
Host smart-c6347276-d10c-4d3b-8cd6-e2db1debed4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224302767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3224302767
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2769695894
Short name T163
Test name
Test status
Simulation time 11088287 ps
CPU time 0.9 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:19 PM PDT 24
Peak memory 216048 kb
Host smart-08cb696b-ed97-4c2b-886e-3d6eb56e2676
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769695894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2769695894
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.854277252
Short name T144
Test name
Test status
Simulation time 40213412 ps
CPU time 1.22 seconds
Started Jun 10 06:34:16 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 216708 kb
Host smart-db110fd4-dc3a-4d83-884a-e8ac1bddacfb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854277252 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.854277252
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1644523474
Short name T72
Test name
Test status
Simulation time 24685792 ps
CPU time 1.09 seconds
Started Jun 10 06:34:17 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 218552 kb
Host smart-28c39822-4c30-4473-938c-00f8ef1c75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644523474 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1644523474
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.4153348080
Short name T788
Test name
Test status
Simulation time 80059453 ps
CPU time 1.45 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 218048 kb
Host smart-3a65cdce-21b2-440e-875a-910e2b4a201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153348080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4153348080
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2698296785
Short name T423
Test name
Test status
Simulation time 37855062 ps
CPU time 0.89 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:19 PM PDT 24
Peak memory 215176 kb
Host smart-1fb9e40e-3bf5-454e-b004-4b55d07d211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698296785 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2698296785
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.866555416
Short name T577
Test name
Test status
Simulation time 19550157 ps
CPU time 1.07 seconds
Started Jun 10 06:34:16 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 215268 kb
Host smart-82479dcf-4949-4fdc-961d-3d6a77ad1a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866555416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.866555416
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2136683596
Short name T666
Test name
Test status
Simulation time 394862218 ps
CPU time 4.5 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 215328 kb
Host smart-7922a772-01e4-40ea-bb2b-8cb69da83f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136683596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2136683596
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2419073603
Short name T220
Test name
Test status
Simulation time 48131386849 ps
CPU time 345.84 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:40:07 PM PDT 24
Peak memory 218224 kb
Host smart-6af56696-3e3e-4702-83df-ed55a4a2f781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419073603 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2419073603
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1369335568
Short name T170
Test name
Test status
Simulation time 35749826 ps
CPU time 1.05 seconds
Started Jun 10 06:32:34 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 218128 kb
Host smart-2bce0355-d8b8-4f0f-850a-82511331ff8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369335568 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1369335568
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1629270350
Short name T231
Test name
Test status
Simulation time 83266757 ps
CPU time 0.87 seconds
Started Jun 10 06:32:33 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 206760 kb
Host smart-01ffccac-ca76-4541-9b26-7c57f6fce234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629270350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1629270350
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1167925092
Short name T618
Test name
Test status
Simulation time 10399566 ps
CPU time 0.86 seconds
Started Jun 10 06:32:34 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 216304 kb
Host smart-32e4ec40-45fb-46eb-8c41-903824003375
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167925092 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1167925092
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3965509765
Short name T264
Test name
Test status
Simulation time 51642835 ps
CPU time 0.97 seconds
Started Jun 10 06:32:30 PM PDT 24
Finished Jun 10 06:32:32 PM PDT 24
Peak memory 218356 kb
Host smart-e72795f1-02e7-4dce-b4c5-2250c774c0db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965509765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3965509765
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3838030419
Short name T371
Test name
Test status
Simulation time 20283741 ps
CPU time 1.15 seconds
Started Jun 10 06:32:34 PM PDT 24
Finished Jun 10 06:32:36 PM PDT 24
Peak memory 224044 kb
Host smart-48acffa7-3790-40de-9d09-99155fa9d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838030419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3838030419
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.3113771211
Short name T833
Test name
Test status
Simulation time 74441304 ps
CPU time 1.13 seconds
Started Jun 10 06:32:28 PM PDT 24
Finished Jun 10 06:32:29 PM PDT 24
Peak memory 218380 kb
Host smart-bf14f615-0ee9-4249-a386-e02f1f03dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113771211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.3113771211
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.601883844
Short name T407
Test name
Test status
Simulation time 37118779 ps
CPU time 0.86 seconds
Started Jun 10 06:32:27 PM PDT 24
Finished Jun 10 06:32:28 PM PDT 24
Peak memory 215200 kb
Host smart-250d610d-e94c-402e-a321-1be3a0fba26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601883844 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.601883844
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.4022088248
Short name T287
Test name
Test status
Simulation time 51060778 ps
CPU time 0.91 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:30 PM PDT 24
Peak memory 206960 kb
Host smart-a74d2fbf-b07b-4b70-9280-a8e8fb0a9569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022088248 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4022088248
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1155350114
Short name T517
Test name
Test status
Simulation time 19892465 ps
CPU time 1.06 seconds
Started Jun 10 06:32:34 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 215212 kb
Host smart-28abe9bc-5713-4404-a682-9ed1266e0f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155350114 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1155350114
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2601826199
Short name T768
Test name
Test status
Simulation time 281556928 ps
CPU time 5.6 seconds
Started Jun 10 06:32:29 PM PDT 24
Finished Jun 10 06:32:35 PM PDT 24
Peak memory 215316 kb
Host smart-72090a3b-5b5b-453b-badd-0ab6eb4eb089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601826199 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2601826199
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4021400570
Short name T481
Test name
Test status
Simulation time 25824103981 ps
CPU time 427.1 seconds
Started Jun 10 06:32:31 PM PDT 24
Finished Jun 10 06:39:38 PM PDT 24
Peak memory 221200 kb
Host smart-b05540c4-eae0-48d6-aff3-bb466ff7414f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021400570 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4021400570
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2253940599
Short name T731
Test name
Test status
Simulation time 28794813 ps
CPU time 1.28 seconds
Started Jun 10 06:34:16 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 219664 kb
Host smart-9ee6a69c-e197-42e2-ad21-d028fe309d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253940599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2253940599
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2768738591
Short name T75
Test name
Test status
Simulation time 29946647 ps
CPU time 1.46 seconds
Started Jun 10 06:34:16 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 218140 kb
Host smart-1f5a4bbb-09fe-4114-8ef5-2782d778a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768738591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2768738591
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.4118609036
Short name T840
Test name
Test status
Simulation time 37480105 ps
CPU time 0.88 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 219384 kb
Host smart-a74bc828-178a-4edb-89d4-690f9c495e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118609036 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4118609036
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3104108933
Short name T90
Test name
Test status
Simulation time 67027647 ps
CPU time 1.38 seconds
Started Jun 10 06:34:17 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 215268 kb
Host smart-d94aa3c9-ed62-4884-9183-db3503e67700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104108933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3104108933
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3423442944
Short name T199
Test name
Test status
Simulation time 62157896 ps
CPU time 1.12 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:24 PM PDT 24
Peak memory 219524 kb
Host smart-fd806cf4-e5b3-4e58-aa25-e5ab2b94360f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423442944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3423442944
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1071268823
Short name T41
Test name
Test status
Simulation time 57286765 ps
CPU time 1.33 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 216880 kb
Host smart-ec2e827b-603d-4ae0-b0a3-a2dff2ef41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071268823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1071268823
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3924088857
Short name T151
Test name
Test status
Simulation time 45367933 ps
CPU time 1.15 seconds
Started Jun 10 06:34:25 PM PDT 24
Finished Jun 10 06:34:27 PM PDT 24
Peak memory 219668 kb
Host smart-a2870a9a-9e9a-4209-b3a9-a0802d741a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924088857 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3924088857
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4283893983
Short name T682
Test name
Test status
Simulation time 68679663 ps
CPU time 1.3 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:22 PM PDT 24
Peak memory 215244 kb
Host smart-66506316-7a05-4bbf-ab24-1533aa21aea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283893983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4283893983
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1454661946
Short name T654
Test name
Test status
Simulation time 77603828 ps
CPU time 1.21 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 225836 kb
Host smart-4d53559a-05bf-400c-8444-bdfd10b7c19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454661946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1454661946
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3773730161
Short name T438
Test name
Test status
Simulation time 29760239 ps
CPU time 1.36 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 218256 kb
Host smart-c9ff9b53-2c68-4838-b72c-acbba504382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773730161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3773730161
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2157609510
Short name T162
Test name
Test status
Simulation time 19226945 ps
CPU time 1.17 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 224104 kb
Host smart-66d318eb-ca74-4c41-8779-aa4df3fd24d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157609510 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2157609510
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.375608780
Short name T63
Test name
Test status
Simulation time 92152914 ps
CPU time 1.03 seconds
Started Jun 10 06:34:18 PM PDT 24
Finished Jun 10 06:34:19 PM PDT 24
Peak memory 216740 kb
Host smart-facdff27-eec1-409c-a02a-620a2a785dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375608780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.375608780
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1112721438
Short name T161
Test name
Test status
Simulation time 19301321 ps
CPU time 1.09 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:24 PM PDT 24
Peak memory 218532 kb
Host smart-11166d15-6bd5-4ab0-aefa-8479e003d9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112721438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1112721438
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.415002634
Short name T592
Test name
Test status
Simulation time 126857697 ps
CPU time 1.48 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 218536 kb
Host smart-c14b21aa-9fa1-4d96-b9c9-3efc99d434a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415002634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.415002634
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3403336223
Short name T412
Test name
Test status
Simulation time 19727640 ps
CPU time 1.21 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 224068 kb
Host smart-39201bf6-2dc8-49f0-a36f-b376eba383f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403336223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3403336223
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.53017412
Short name T509
Test name
Test status
Simulation time 83827911 ps
CPU time 2.71 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:18 PM PDT 24
Peak memory 219608 kb
Host smart-6a54f3f8-9ae3-4543-8347-12ffbd5f47d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53017412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.53017412
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.4024499902
Short name T838
Test name
Test status
Simulation time 18561442 ps
CPU time 1 seconds
Started Jun 10 06:34:15 PM PDT 24
Finished Jun 10 06:34:16 PM PDT 24
Peak memory 218268 kb
Host smart-fc3114c6-c368-4e2c-b89c-8ca1f6ddf3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024499902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4024499902
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2345388259
Short name T376
Test name
Test status
Simulation time 32640915 ps
CPU time 1.35 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:24 PM PDT 24
Peak memory 217100 kb
Host smart-072fe41f-7429-4fd8-8f06-aa94d8cd1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345388259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2345388259
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2254143562
Short name T830
Test name
Test status
Simulation time 31836537 ps
CPU time 0.92 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 218296 kb
Host smart-d574a464-b476-4744-9a15-3a98c2568641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254143562 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2254143562
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1053738037
Short name T721
Test name
Test status
Simulation time 150106550 ps
CPU time 1.02 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 216840 kb
Host smart-408f69e2-ac1b-4ba3-b828-5c2cf1b2ed90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053738037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1053738037
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.20447388
Short name T146
Test name
Test status
Simulation time 54353902 ps
CPU time 1.26 seconds
Started Jun 10 06:32:46 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 218476 kb
Host smart-d05bd279-175c-465d-952f-0ec8ebcec1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20447388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.20447388
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1206029842
Short name T560
Test name
Test status
Simulation time 62380075 ps
CPU time 0.99 seconds
Started Jun 10 06:32:42 PM PDT 24
Finished Jun 10 06:32:43 PM PDT 24
Peak memory 214740 kb
Host smart-2c8182cf-335d-409c-8660-b567c0a6bcf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206029842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1206029842
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.933843112
Short name T208
Test name
Test status
Simulation time 64694425 ps
CPU time 0.85 seconds
Started Jun 10 06:32:42 PM PDT 24
Finished Jun 10 06:32:43 PM PDT 24
Peak memory 216260 kb
Host smart-b0e51204-fe12-4ed1-b1c7-50eaabbbf886
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933843112 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.933843112
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.4191491139
Short name T386
Test name
Test status
Simulation time 52090054 ps
CPU time 1.18 seconds
Started Jun 10 06:32:41 PM PDT 24
Finished Jun 10 06:32:42 PM PDT 24
Peak memory 218160 kb
Host smart-e71b554e-4199-4b6d-aac6-e9a37bef170d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191491139 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.4191491139
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2894108039
Short name T778
Test name
Test status
Simulation time 64073221 ps
CPU time 1.01 seconds
Started Jun 10 06:32:41 PM PDT 24
Finished Jun 10 06:32:42 PM PDT 24
Peak memory 219704 kb
Host smart-17001180-078b-479e-8498-136efd2bce6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894108039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2894108039
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.272512570
Short name T536
Test name
Test status
Simulation time 35128010 ps
CPU time 1.3 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:38 PM PDT 24
Peak memory 218244 kb
Host smart-69338758-60a3-46f9-8ac5-4c422cd5c201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272512570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.272512570
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.516567892
Short name T521
Test name
Test status
Simulation time 21884144 ps
CPU time 0.93 seconds
Started Jun 10 06:32:46 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 215872 kb
Host smart-267e8793-ea50-43ef-8bde-c716bfbee869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516567892 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.516567892
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4269482973
Short name T26
Test name
Test status
Simulation time 53826092 ps
CPU time 0.98 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:38 PM PDT 24
Peak memory 206984 kb
Host smart-c03ed829-e563-4916-a7de-30fe760dd56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269482973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4269482973
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.691266599
Short name T798
Test name
Test status
Simulation time 100871983 ps
CPU time 0.88 seconds
Started Jun 10 06:32:32 PM PDT 24
Finished Jun 10 06:32:33 PM PDT 24
Peak memory 207004 kb
Host smart-f768743a-4bae-4edd-847e-7639f936589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691266599 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.691266599
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1177149818
Short name T505
Test name
Test status
Simulation time 885762169 ps
CPU time 5.09 seconds
Started Jun 10 06:32:37 PM PDT 24
Finished Jun 10 06:32:42 PM PDT 24
Peak memory 217028 kb
Host smart-d7402a3b-972d-4728-9dab-6141731336b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177149818 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1177149818
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1875814006
Short name T467
Test name
Test status
Simulation time 23642797576 ps
CPU time 552.07 seconds
Started Jun 10 06:32:36 PM PDT 24
Finished Jun 10 06:41:49 PM PDT 24
Peak memory 223168 kb
Host smart-b62a45bf-ce92-45ef-94e8-20b37e42ced1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875814006 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1875814006
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3921219982
Short name T114
Test name
Test status
Simulation time 21311933 ps
CPU time 1.13 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 219800 kb
Host smart-34b2dece-ab29-4392-8403-3e6449ac2c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921219982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3921219982
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.987479044
Short name T828
Test name
Test status
Simulation time 32731498 ps
CPU time 1.27 seconds
Started Jun 10 06:34:22 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 218096 kb
Host smart-eb55c534-8a88-4660-8881-11a16bd73762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987479044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.987479044
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3945991089
Short name T380
Test name
Test status
Simulation time 32974914 ps
CPU time 0.92 seconds
Started Jun 10 06:34:22 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 218316 kb
Host smart-e33a7d6d-3e50-44f3-9f54-36c5979abfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945991089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3945991089
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3169849921
Short name T834
Test name
Test status
Simulation time 104534612 ps
CPU time 0.97 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:22 PM PDT 24
Peak memory 216964 kb
Host smart-8aef1ecc-aa6e-4c54-8249-93a2d0e19cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169849921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3169849921
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.1960079585
Short name T600
Test name
Test status
Simulation time 32445708 ps
CPU time 0.97 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 223884 kb
Host smart-a5f1821f-38a9-424f-9b71-446601dc945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960079585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1960079585
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3203272012
Short name T750
Test name
Test status
Simulation time 35485665 ps
CPU time 1.07 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 216840 kb
Host smart-f6f15f69-1c4d-4c43-b17e-9f965df57d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203272012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3203272012
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2844862262
Short name T720
Test name
Test status
Simulation time 18439285 ps
CPU time 1.01 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:21 PM PDT 24
Peak memory 218232 kb
Host smart-890d9196-08aa-44c9-8c5c-2c23893c3e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844862262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2844862262
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2891208607
Short name T664
Test name
Test status
Simulation time 93604152 ps
CPU time 1.07 seconds
Started Jun 10 06:34:21 PM PDT 24
Finished Jun 10 06:34:22 PM PDT 24
Peak memory 216796 kb
Host smart-340cf1e7-29c6-4fb3-87d0-bf89ef5b60c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891208607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2891208607
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.279408678
Short name T15
Test name
Test status
Simulation time 76659896 ps
CPU time 0.95 seconds
Started Jun 10 06:34:22 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 223808 kb
Host smart-7767219b-2ef6-4605-883d-feb563675945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279408678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.279408678
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.997143080
Short name T43
Test name
Test status
Simulation time 145982123 ps
CPU time 1.11 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 216964 kb
Host smart-7e22fbd9-0480-4261-abd1-7f935b6d11da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997143080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.997143080
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2177753289
Short name T190
Test name
Test status
Simulation time 46447604 ps
CPU time 0.97 seconds
Started Jun 10 06:34:19 PM PDT 24
Finished Jun 10 06:34:20 PM PDT 24
Peak memory 218668 kb
Host smart-05683048-a0d5-4c7a-8146-58845e49c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177753289 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2177753289
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1654350847
Short name T420
Test name
Test status
Simulation time 114893403 ps
CPU time 2.45 seconds
Started Jun 10 06:34:20 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 219364 kb
Host smart-117cd952-fb29-4a28-ba0b-d6e3fba3142a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654350847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1654350847
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.707898385
Short name T156
Test name
Test status
Simulation time 22389561 ps
CPU time 1.02 seconds
Started Jun 10 06:34:25 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 223988 kb
Host smart-1bfc0d9d-221f-44b4-8831-053abbd3474c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707898385 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.707898385
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3425038835
Short name T603
Test name
Test status
Simulation time 196185825 ps
CPU time 1.15 seconds
Started Jun 10 06:34:22 PM PDT 24
Finished Jun 10 06:34:23 PM PDT 24
Peak memory 215236 kb
Host smart-980a4278-12e6-4dd6-9f86-6c431b000c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425038835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3425038835
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2116124897
Short name T547
Test name
Test status
Simulation time 88337856 ps
CPU time 0.89 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 218444 kb
Host smart-afe57079-6ec9-4fa4-a118-d841def955ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116124897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2116124897
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.3423926599
Short name T470
Test name
Test status
Simulation time 45846517 ps
CPU time 1.55 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 218132 kb
Host smart-b6e3008b-edf0-4c06-a596-065a9f81061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423926599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3423926599
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1716754325
Short name T203
Test name
Test status
Simulation time 29808561 ps
CPU time 1.42 seconds
Started Jun 10 06:34:27 PM PDT 24
Finished Jun 10 06:34:29 PM PDT 24
Peak memory 225744 kb
Host smart-d065620f-f7b8-4f6b-9093-06a5c814fa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716754325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1716754325
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2068940778
Short name T831
Test name
Test status
Simulation time 127342817 ps
CPU time 1.85 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:29 PM PDT 24
Peak memory 218696 kb
Host smart-d042009d-7985-465e-8b06-ccea94c762d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068940778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2068940778
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.4020713547
Short name T92
Test name
Test status
Simulation time 33068431 ps
CPU time 0.93 seconds
Started Jun 10 06:34:24 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 219556 kb
Host smart-a6e6b1bb-5899-48b1-8c3a-363a38794b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020713547 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.4020713547
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.477685673
Short name T389
Test name
Test status
Simulation time 45514933 ps
CPU time 1.52 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 216892 kb
Host smart-a969e199-e956-488f-bd45-aea4d0527e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477685673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.477685673
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1694151916
Short name T266
Test name
Test status
Simulation time 60098459 ps
CPU time 1.22 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 218788 kb
Host smart-9a0241ed-d49c-4931-926d-ca816c48bac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694151916 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1694151916
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.861487184
Short name T378
Test name
Test status
Simulation time 22414886 ps
CPU time 0.9 seconds
Started Jun 10 06:32:50 PM PDT 24
Finished Jun 10 06:32:52 PM PDT 24
Peak memory 215080 kb
Host smart-f921b38e-5f93-4c97-ac5e-c6120d83e591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861487184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.861487184
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_err.104686441
Short name T708
Test name
Test status
Simulation time 19793864 ps
CPU time 1.13 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:32:49 PM PDT 24
Peak memory 224076 kb
Host smart-2e38f59c-6306-4a93-aff1-9365124eead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104686441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.104686441
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1506464826
Short name T684
Test name
Test status
Simulation time 39764226 ps
CPU time 1.84 seconds
Started Jun 10 06:32:45 PM PDT 24
Finished Jun 10 06:32:48 PM PDT 24
Peak memory 216932 kb
Host smart-414d7424-e9a0-49e1-9f6f-a74ae85b2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506464826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1506464826
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.978629486
Short name T337
Test name
Test status
Simulation time 37497686 ps
CPU time 0.89 seconds
Started Jun 10 06:32:45 PM PDT 24
Finished Jun 10 06:32:46 PM PDT 24
Peak memory 215168 kb
Host smart-b1aa9bc6-628f-448f-a071-3accf1003cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978629486 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.978629486
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.2316551140
Short name T27
Test name
Test status
Simulation time 74128717 ps
CPU time 1 seconds
Started Jun 10 06:32:44 PM PDT 24
Finished Jun 10 06:32:45 PM PDT 24
Peak memory 207004 kb
Host smart-16002274-4ffe-46f6-981c-cbb8e2719f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316551140 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.2316551140
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4025432419
Short name T495
Test name
Test status
Simulation time 39569172 ps
CPU time 0.88 seconds
Started Jun 10 06:32:40 PM PDT 24
Finished Jun 10 06:32:41 PM PDT 24
Peak memory 215208 kb
Host smart-8530f384-d12d-43be-9f38-ed6895fb26d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025432419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4025432419
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2718473823
Short name T429
Test name
Test status
Simulation time 173295820 ps
CPU time 1.49 seconds
Started Jun 10 06:32:45 PM PDT 24
Finished Jun 10 06:32:47 PM PDT 24
Peak memory 216812 kb
Host smart-7ba18844-dd9e-4555-9b14-c8d949b8bdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718473823 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2718473823
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1866480729
Short name T688
Test name
Test status
Simulation time 55501269817 ps
CPU time 522.11 seconds
Started Jun 10 06:32:47 PM PDT 24
Finished Jun 10 06:41:30 PM PDT 24
Peak memory 219744 kb
Host smart-3c2f6a13-b43c-4762-b7f8-ae23d9afbe04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866480729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1866480729
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.291361129
Short name T185
Test name
Test status
Simulation time 26346959 ps
CPU time 0.99 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:25 PM PDT 24
Peak memory 219516 kb
Host smart-e056ea98-91af-4b4b-9194-12093e45e474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291361129 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.291361129
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1567234699
Short name T589
Test name
Test status
Simulation time 51755845 ps
CPU time 1.63 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 218532 kb
Host smart-bf3fd87c-f1b0-4be0-a7c4-d5feff1f1799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567234699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1567234699
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.816174777
Short name T353
Test name
Test status
Simulation time 33761347 ps
CPU time 1.16 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 219712 kb
Host smart-1c6ace67-cf08-4867-a535-5a9ea88b34b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816174777 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.816174777
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1410185158
Short name T329
Test name
Test status
Simulation time 35048468 ps
CPU time 1.57 seconds
Started Jun 10 06:34:24 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 218300 kb
Host smart-6e4e5610-3294-4d1e-9c6d-d98c555f4f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410185158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1410185158
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1999243346
Short name T142
Test name
Test status
Simulation time 55926820 ps
CPU time 0.89 seconds
Started Jun 10 06:34:25 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 219708 kb
Host smart-8289864e-29c1-4907-84d5-022ad780c808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999243346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1999243346
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3091091106
Short name T764
Test name
Test status
Simulation time 84232732 ps
CPU time 3.09 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 219868 kb
Host smart-644ab50d-ed78-46e5-bfb6-f15cc1066dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091091106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3091091106
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3905447093
Short name T711
Test name
Test status
Simulation time 149172262 ps
CPU time 1.13 seconds
Started Jun 10 06:34:24 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 225816 kb
Host smart-7eda03a7-9d37-420a-b6b6-e7abea5b56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905447093 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3905447093
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1970812566
Short name T647
Test name
Test status
Simulation time 53157410 ps
CPU time 1.22 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 218440 kb
Host smart-aad7eb45-36cb-42d6-8f9a-a6ac5967a078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970812566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1970812566
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.3348633895
Short name T561
Test name
Test status
Simulation time 70617667 ps
CPU time 1.2 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:27 PM PDT 24
Peak memory 225696 kb
Host smart-2706f16b-167b-46e8-b160-32d237cc038d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348633895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3348633895
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.535239093
Short name T338
Test name
Test status
Simulation time 46501391 ps
CPU time 1.7 seconds
Started Jun 10 06:34:26 PM PDT 24
Finished Jun 10 06:34:28 PM PDT 24
Peak memory 216980 kb
Host smart-f680a719-103b-477e-aa2c-9cc008df3cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535239093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.535239093
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.1119282095
Short name T126
Test name
Test status
Simulation time 95900567 ps
CPU time 0.89 seconds
Started Jun 10 06:34:23 PM PDT 24
Finished Jun 10 06:34:24 PM PDT 24
Peak memory 219500 kb
Host smart-c00f56ac-5331-4487-8b60-2e6038563824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119282095 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1119282095
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2747578107
Short name T305
Test name
Test status
Simulation time 36999337 ps
CPU time 1.42 seconds
Started Jun 10 06:34:25 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 219596 kb
Host smart-ed3ee0f0-2867-4b31-90d1-bccdb0d8ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747578107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2747578107
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2880121860
Short name T383
Test name
Test status
Simulation time 25962576 ps
CPU time 1.12 seconds
Started Jun 10 06:34:24 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 219680 kb
Host smart-0d365108-9604-4319-83a5-5caba2895e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880121860 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2880121860
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3409267734
Short name T477
Test name
Test status
Simulation time 64048346 ps
CPU time 1.67 seconds
Started Jun 10 06:34:24 PM PDT 24
Finished Jun 10 06:34:26 PM PDT 24
Peak memory 216860 kb
Host smart-6f6e26c3-684b-4ea6-bd95-f727f20f82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409267734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3409267734
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.121548875
Short name T167
Test name
Test status
Simulation time 36702088 ps
CPU time 0.88 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:32 PM PDT 24
Peak memory 218292 kb
Host smart-72ecca60-b1f8-4661-ac96-d17e939db272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121548875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.121548875
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/78.edn_err.3084242282
Short name T157
Test name
Test status
Simulation time 30653899 ps
CPU time 1.21 seconds
Started Jun 10 06:34:28 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 219708 kb
Host smart-aa2ef3ba-b3e0-4d3c-baac-2e56432dab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084242282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3084242282
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.111194042
Short name T22
Test name
Test status
Simulation time 101534288 ps
CPU time 1.13 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:32 PM PDT 24
Peak memory 216980 kb
Host smart-0735d02c-1ecd-4606-98e5-02783fac4f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111194042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.111194042
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.181760063
Short name T137
Test name
Test status
Simulation time 45432955 ps
CPU time 1.1 seconds
Started Jun 10 06:34:32 PM PDT 24
Finished Jun 10 06:34:33 PM PDT 24
Peak memory 229740 kb
Host smart-eab82351-f3d1-471a-a67a-e6cc8fd91556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181760063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.181760063
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.125394332
Short name T428
Test name
Test status
Simulation time 33653194 ps
CPU time 1.35 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 219508 kb
Host smart-173ce74b-99de-4206-8521-40d3f8bc9d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125394332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.125394332
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2141847592
Short name T29
Test name
Test status
Simulation time 27137572 ps
CPU time 1.2 seconds
Started Jun 10 06:32:53 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 218512 kb
Host smart-63540392-bef9-4241-bade-1f5f45bd3d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141847592 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2141847592
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3447293652
Short name T702
Test name
Test status
Simulation time 87740389 ps
CPU time 0.9 seconds
Started Jun 10 06:32:53 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 206508 kb
Host smart-7614bf91-5923-43fe-93bb-b6ed9ec4ba2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447293652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3447293652
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2489367887
Short name T700
Test name
Test status
Simulation time 143308510 ps
CPU time 0.9 seconds
Started Jun 10 06:32:55 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 215292 kb
Host smart-b8cd8ba0-8366-47dc-bcc0-9a9531c77cc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489367887 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2489367887
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.874175026
Short name T524
Test name
Test status
Simulation time 113869875 ps
CPU time 1.13 seconds
Started Jun 10 06:32:53 PM PDT 24
Finished Jun 10 06:32:54 PM PDT 24
Peak memory 215636 kb
Host smart-7c02ee28-a6b6-4d38-9336-314d30d7d270
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874175026 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_dis
able_auto_req_mode.874175026
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3030558214
Short name T730
Test name
Test status
Simulation time 25140223 ps
CPU time 1.24 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:58 PM PDT 24
Peak memory 220612 kb
Host smart-e3c087ed-7eb1-4172-a1e2-9c357c8984e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030558214 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3030558214
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_intr.140648772
Short name T257
Test name
Test status
Simulation time 21566510 ps
CPU time 1.1 seconds
Started Jun 10 06:32:54 PM PDT 24
Finished Jun 10 06:32:55 PM PDT 24
Peak memory 215388 kb
Host smart-659c1815-db09-48eb-996c-3d2069a03539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140648772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.140648772
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3302062399
Short name T285
Test name
Test status
Simulation time 22543669 ps
CPU time 0.93 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:50 PM PDT 24
Peak memory 206948 kb
Host smart-c2fdd47e-49f3-43f0-84e3-9968638ed80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302062399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3302062399
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2071282747
Short name T658
Test name
Test status
Simulation time 30991225 ps
CPU time 0.91 seconds
Started Jun 10 06:32:49 PM PDT 24
Finished Jun 10 06:32:51 PM PDT 24
Peak memory 215236 kb
Host smart-8a945fca-dd37-4540-91a1-c9c14139421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071282747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2071282747
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3575587182
Short name T783
Test name
Test status
Simulation time 122438346 ps
CPU time 1.43 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:57 PM PDT 24
Peak memory 216800 kb
Host smart-ab91b5c1-d783-4d83-839e-60ec635c1747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575587182 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3575587182
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.1415039315
Short name T755
Test name
Test status
Simulation time 132767629756 ps
CPU time 839.61 seconds
Started Jun 10 06:32:55 PM PDT 24
Finished Jun 10 06:46:56 PM PDT 24
Peak memory 221260 kb
Host smart-d9410a3c-9007-436d-b29c-709662cdac31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415039315 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.1415039315
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.611234282
Short name T821
Test name
Test status
Simulation time 37351687 ps
CPU time 0.88 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 218380 kb
Host smart-6148296e-0c05-41a5-96d8-306ab97b5552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611234282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.611234282
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3905267375
Short name T774
Test name
Test status
Simulation time 32734181 ps
CPU time 1.38 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 216948 kb
Host smart-eee6a847-1400-4ea1-9c13-8a294dac3b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905267375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3905267375
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1070220640
Short name T656
Test name
Test status
Simulation time 19512896 ps
CPU time 1.17 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:32 PM PDT 24
Peak memory 224040 kb
Host smart-d46f2983-6a26-435e-a13b-8501d01578ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070220640 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1070220640
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3266960014
Short name T346
Test name
Test status
Simulation time 41962824 ps
CPU time 1.25 seconds
Started Jun 10 06:34:28 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 218928 kb
Host smart-1cddd6ee-c241-483a-8249-627670a270c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266960014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3266960014
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.3941818386
Short name T56
Test name
Test status
Simulation time 68930396 ps
CPU time 1.08 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 229404 kb
Host smart-75d918f8-d8e6-47f4-a6b7-66ba7951d4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941818386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.3941818386
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.582429435
Short name T649
Test name
Test status
Simulation time 43029023 ps
CPU time 1.5 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:32 PM PDT 24
Peak memory 217144 kb
Host smart-8ec28ff0-adc9-4d25-ae93-c44afc896d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582429435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.582429435
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1718886699
Short name T182
Test name
Test status
Simulation time 32130980 ps
CPU time 0.92 seconds
Started Jun 10 06:34:30 PM PDT 24
Finished Jun 10 06:34:32 PM PDT 24
Peak memory 218176 kb
Host smart-43d7f6fc-7d07-4e6a-9329-5e95ac490c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718886699 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1718886699
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.54216507
Short name T791
Test name
Test status
Simulation time 36477542 ps
CPU time 1.42 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 217968 kb
Host smart-7aab62f6-e745-496c-bf34-b6f32902d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54216507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.54216507
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2611921913
Short name T590
Test name
Test status
Simulation time 41314079 ps
CPU time 0.9 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 218640 kb
Host smart-0d3624aa-df29-497d-8856-f761233f5ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611921913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2611921913
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1139540085
Short name T293
Test name
Test status
Simulation time 51187875 ps
CPU time 1.21 seconds
Started Jun 10 06:34:28 PM PDT 24
Finished Jun 10 06:34:29 PM PDT 24
Peak memory 219456 kb
Host smart-bf688439-d315-4087-bae7-21c9ab4a40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139540085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1139540085
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.144954140
Short name T717
Test name
Test status
Simulation time 136637353 ps
CPU time 0.93 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 219560 kb
Host smart-c8f2f2b0-ffc6-4f71-adc3-d0efb0c1df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144954140 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.144954140
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1750026557
Short name T508
Test name
Test status
Simulation time 42698715 ps
CPU time 1.47 seconds
Started Jun 10 06:34:32 PM PDT 24
Finished Jun 10 06:34:33 PM PDT 24
Peak memory 218292 kb
Host smart-a304b6be-a872-43ce-b494-9ce6e80d4687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750026557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1750026557
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3075922859
Short name T7
Test name
Test status
Simulation time 20606951 ps
CPU time 1.1 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:31 PM PDT 24
Peak memory 219544 kb
Host smart-f7c2e236-c6e7-491f-b963-554ac091288a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075922859 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3075922859
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3394353125
Short name T86
Test name
Test status
Simulation time 56522232 ps
CPU time 1.36 seconds
Started Jun 10 06:34:29 PM PDT 24
Finished Jun 10 06:34:30 PM PDT 24
Peak memory 217060 kb
Host smart-30f084df-bd29-4223-897f-9126c4908b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394353125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3394353125
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1568187684
Short name T751
Test name
Test status
Simulation time 24640305 ps
CPU time 1.15 seconds
Started Jun 10 06:34:34 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 219804 kb
Host smart-b3d64136-e1a0-42ea-94b5-63648eb4574d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568187684 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1568187684
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3527159761
Short name T792
Test name
Test status
Simulation time 90974261 ps
CPU time 1.17 seconds
Started Jun 10 06:34:31 PM PDT 24
Finished Jun 10 06:34:33 PM PDT 24
Peak memory 218216 kb
Host smart-8b2389cb-5e63-4ac7-862d-0a99eb453074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527159761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3527159761
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1196699400
Short name T459
Test name
Test status
Simulation time 20267990 ps
CPU time 1.1 seconds
Started Jun 10 06:34:33 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 224000 kb
Host smart-21c821bc-9f52-49dc-91a4-9014e2146793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196699400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1196699400
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1009378425
Short name T393
Test name
Test status
Simulation time 42335195 ps
CPU time 1.43 seconds
Started Jun 10 06:34:34 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 218172 kb
Host smart-8c1f5d0c-0eac-4e42-8236-31871ae26969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009378425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1009378425
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.313665208
Short name T506
Test name
Test status
Simulation time 32806946 ps
CPU time 0.97 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 223836 kb
Host smart-f704036b-809f-489b-9365-5ddcf355778c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313665208 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.313665208
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3790893019
Short name T529
Test name
Test status
Simulation time 27034306 ps
CPU time 1.31 seconds
Started Jun 10 06:34:32 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 219548 kb
Host smart-16ce7f57-bd16-48a0-8c1f-e93fdfbe583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790893019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3790893019
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.105246098
Short name T100
Test name
Test status
Simulation time 29753132 ps
CPU time 1.24 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:32:58 PM PDT 24
Peak memory 219184 kb
Host smart-9e350886-5987-4185-9e2b-f4d4b2d5f9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105246098 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.105246098
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1238882798
Short name T404
Test name
Test status
Simulation time 27402666 ps
CPU time 0.91 seconds
Started Jun 10 06:32:59 PM PDT 24
Finished Jun 10 06:33:01 PM PDT 24
Peak memory 206572 kb
Host smart-9c9d29dd-c0d9-4f0a-b80f-e519865cf5bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238882798 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1238882798
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.185295901
Short name T210
Test name
Test status
Simulation time 55264389 ps
CPU time 0.89 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:32:57 PM PDT 24
Peak memory 215304 kb
Host smart-c87fe88d-0882-4eea-be3b-0f06313bdf32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185295901 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.185295901
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2109894565
Short name T66
Test name
Test status
Simulation time 32933006 ps
CPU time 1.24 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 216684 kb
Host smart-a47e109f-f650-4529-a49f-998508f5b1e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109894565 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2109894565
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3324784435
Short name T332
Test name
Test status
Simulation time 17998244 ps
CPU time 1.05 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 218396 kb
Host smart-d0f1f93f-0ad3-4e31-85cd-fd1642667e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324784435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3324784435
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3571371631
Short name T497
Test name
Test status
Simulation time 77242124 ps
CPU time 1.7 seconds
Started Jun 10 06:32:57 PM PDT 24
Finished Jun 10 06:33:00 PM PDT 24
Peak memory 218312 kb
Host smart-7b5332fb-eb2f-400a-9770-df22975b1f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571371631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3571371631
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3774114900
Short name T91
Test name
Test status
Simulation time 26677469 ps
CPU time 0.96 seconds
Started Jun 10 06:32:58 PM PDT 24
Finished Jun 10 06:32:59 PM PDT 24
Peak memory 215780 kb
Host smart-44d49b46-0ab5-4059-9407-5d941da61b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774114900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3774114900
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.3845721364
Short name T25
Test name
Test status
Simulation time 19724114 ps
CPU time 1.08 seconds
Started Jun 10 06:32:55 PM PDT 24
Finished Jun 10 06:32:56 PM PDT 24
Peak memory 207044 kb
Host smart-abd8a0f7-af2b-4c3f-a8f2-60f7058728b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845721364 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.3845721364
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.204665887
Short name T439
Test name
Test status
Simulation time 40204059 ps
CPU time 0.87 seconds
Started Jun 10 06:32:52 PM PDT 24
Finished Jun 10 06:32:53 PM PDT 24
Peak memory 215228 kb
Host smart-169801a4-29a2-4f07-91bf-5b8a7e6016b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204665887 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.204665887
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1119769748
Short name T97
Test name
Test status
Simulation time 334849009 ps
CPU time 6.67 seconds
Started Jun 10 06:32:58 PM PDT 24
Finished Jun 10 06:33:05 PM PDT 24
Peak memory 215200 kb
Host smart-e08b8d98-1250-4027-868c-007c6c2e8651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119769748 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1119769748
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3056300262
Short name T224
Test name
Test status
Simulation time 46151902285 ps
CPU time 994.65 seconds
Started Jun 10 06:32:56 PM PDT 24
Finished Jun 10 06:49:32 PM PDT 24
Peak memory 223588 kb
Host smart-54676c98-575f-4576-8818-1d56286162ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056300262 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3056300262
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1054695280
Short name T790
Test name
Test status
Simulation time 88814660 ps
CPU time 1.28 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:37 PM PDT 24
Peak memory 225776 kb
Host smart-bb7d4c77-5530-468c-a7b0-c9c93e66a720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054695280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1054695280
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3227470593
Short name T444
Test name
Test status
Simulation time 42830391 ps
CPU time 1.52 seconds
Started Jun 10 06:34:33 PM PDT 24
Finished Jun 10 06:34:35 PM PDT 24
Peak memory 218172 kb
Host smart-8cefd459-86e1-4188-8468-cdb5e1f6dd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227470593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3227470593
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3874849147
Short name T837
Test name
Test status
Simulation time 21685683 ps
CPU time 0.9 seconds
Started Jun 10 06:34:32 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 218152 kb
Host smart-bc384631-9d36-4b2e-b74b-90330899af2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874849147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3874849147
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2568889096
Short name T363
Test name
Test status
Simulation time 39560782 ps
CPU time 1.14 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:37 PM PDT 24
Peak memory 217980 kb
Host smart-d906cfb7-5e70-49a1-b19e-def562a205ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568889096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2568889096
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3291193021
Short name T503
Test name
Test status
Simulation time 27676983 ps
CPU time 0.92 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:37 PM PDT 24
Peak memory 218692 kb
Host smart-33c18eb5-6624-48f5-a61a-2b0eb6ecad09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291193021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3291193021
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1299450963
Short name T487
Test name
Test status
Simulation time 62356991 ps
CPU time 1.12 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 218044 kb
Host smart-422b5100-60a3-42b0-9b6c-493581c079e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299450963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1299450963
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3697180549
Short name T150
Test name
Test status
Simulation time 19527989 ps
CPU time 1.1 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 218536 kb
Host smart-b38823cd-702b-48ed-8b24-027d81b467ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697180549 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3697180549
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3304273458
Short name T534
Test name
Test status
Simulation time 90175440 ps
CPU time 1.31 seconds
Started Jun 10 06:34:34 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 218260 kb
Host smart-f754d93c-0229-4356-83f0-9cf44981ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304273458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3304273458
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2005894097
Short name T469
Test name
Test status
Simulation time 23204803 ps
CPU time 1.07 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 218628 kb
Host smart-b8e48226-346c-49f1-ae09-b35ca4f5d8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005894097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2005894097
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.500662542
Short name T20
Test name
Test status
Simulation time 59884178 ps
CPU time 1.35 seconds
Started Jun 10 06:34:33 PM PDT 24
Finished Jun 10 06:34:34 PM PDT 24
Peak memory 219620 kb
Host smart-cd4d2891-c457-42f7-8e03-ceaad6ea2ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500662542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.500662542
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2763425267
Short name T807
Test name
Test status
Simulation time 18962992 ps
CPU time 1.1 seconds
Started Jun 10 06:34:33 PM PDT 24
Finished Jun 10 06:34:35 PM PDT 24
Peak memory 224148 kb
Host smart-71322b63-dbaa-4ca9-a032-7c4ed4c98f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763425267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2763425267
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2712508025
Short name T366
Test name
Test status
Simulation time 46556418 ps
CPU time 1.02 seconds
Started Jun 10 06:34:35 PM PDT 24
Finished Jun 10 06:34:36 PM PDT 24
Peak memory 218844 kb
Host smart-4ac4eb3b-ed2d-4e7c-8c36-1d99fbc5515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712508025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2712508025
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.195362203
Short name T394
Test name
Test status
Simulation time 29697722 ps
CPU time 0.94 seconds
Started Jun 10 06:34:38 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 223884 kb
Host smart-ad065478-cae8-40cf-a146-da1fbe637486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195362203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.195362203
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.418839201
Short name T73
Test name
Test status
Simulation time 266945926 ps
CPU time 1.29 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 216840 kb
Host smart-a18fe62d-8b0f-4738-8bde-736b679e8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418839201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.418839201
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.405524729
Short name T839
Test name
Test status
Simulation time 36324134 ps
CPU time 0.83 seconds
Started Jun 10 06:34:37 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 218284 kb
Host smart-e95a330b-560a-4c17-9513-6c29857ccf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405524729 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.405524729
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.160226040
Short name T515
Test name
Test status
Simulation time 43909514 ps
CPU time 1.69 seconds
Started Jun 10 06:34:38 PM PDT 24
Finished Jun 10 06:34:40 PM PDT 24
Peak memory 216952 kb
Host smart-e0198a32-4065-4230-9552-273bac3baf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160226040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.160226040
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1086113220
Short name T174
Test name
Test status
Simulation time 22630986 ps
CPU time 1.06 seconds
Started Jun 10 06:34:38 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 224132 kb
Host smart-daec8399-f2c0-4110-96fa-a69dae10c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086113220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1086113220
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.3993329430
Short name T494
Test name
Test status
Simulation time 101281988 ps
CPU time 0.97 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 216904 kb
Host smart-fadfcec0-f460-45e2-95c5-71b8ac56325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993329430 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.3993329430
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2722644604
Short name T435
Test name
Test status
Simulation time 238141853 ps
CPU time 1.02 seconds
Started Jun 10 06:34:37 PM PDT 24
Finished Jun 10 06:34:39 PM PDT 24
Peak memory 219624 kb
Host smart-1c7c4bd7-6ebc-416c-bd35-2f6bc838a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722644604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2722644604
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2774743709
Short name T446
Test name
Test status
Simulation time 40811905 ps
CPU time 1.59 seconds
Started Jun 10 06:34:36 PM PDT 24
Finished Jun 10 06:34:38 PM PDT 24
Peak memory 215228 kb
Host smart-fdb7d2f5-8bd8-4fa2-8bfa-83a39808845f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774743709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2774743709
Directory /workspace/99.edn_genbits/latest
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